Devices like the ATSAM series chips have retained registers
which are used to store memory. The memory is accessed just
like RAM, but since they are registers, their size and
address is used directly.
This commit adds a near complete copy of the generic retained
ram driver and bindings file, adding the reg property to
the bindings file, and updating the init macro in the driver
to use the reg address and size.
Signed-off-by: Bjarki Arge Andreasen <bjarki@arge-andreasen.me>
Rename old rpl_crb to rpl_s_crb, which is needed for adding other
Raptor Lake boards. Main changes should be in the board device tree
configuration raptor_lake_p vs raptor_lake_s.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Add SOC definition for MK22F12 series, larger LQFP-144 K22 series
parts that feature additional peripheral instances.
Additionally, these parts differ from the standard MK22 in the following
ways:
- SYSMPU peripheral is present, so an MPU definition is required
- No external oscillator divider is present
This commit also updates the NXP HAL to include pin control files for
these SOCs.
Signed-off-by: Daniel DeGrasse <daniel@degrasse.com>
Declare the SRAM0 region as memory-region
for the stm32f745 serie. Will be included for the stm32f746
for the stm32f765 serie. Will be included for the stm32f767
for the stm32f722 serie. Will be included for the stm32f723
Signed-off-by: Francois Ramu <francois.ramu@st.com>
This commit updates the Ambiq Apollo4x series soc clock frequency
of defined instances to align with context of these dts files.
Signed-off-by: Aaron Ye <aye@ambiq.com>
ESP32 family pinctrl files are currently placed in hal_espressif.
Move to main branch as part of pinctrl dt-bindings.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Add a property to the mdio controller binding to describe the MDC
frequency generated by the controller.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
We might have to do this differently:
Configure rng default clock in .dtsi
Set board specific config in .dts
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
SRAM6 is used by RF and should be defined as RAM_NOCACHE
to allow unaligned access reads.
"IO" might be a better match but is not available on this arch.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This commits create the dts binding for Ambiq BT HCI instance.
And create the SPI based common HCI driver for Ambiq Apollox
Blue SoC and the extended soc driver for HCI.
Signed-off-by: Aaron Ye <aye@ambiq.com>
Add a device driver to read events from a Linux evdev device node and
inject them back as Zephyr input events.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Generic Connector for the apollo4p_evb
Ran tests/drivers/gpio/gpio_basic_api
Ambiq does not support DUAL Edged Interrupts.
Added Connector Usages as defined by the Ambiq BSP.
Signed-off-by: Richard Wheatley <richard.wheatley@ambiq.com>
USB Audio Class 2 (UAC2) includes a method to describe audio device
topology to host using a set of class specific descriptors. The audio
device description includes complete sample clock topology and audio
processing organization.
Zephyr specific bindings are supposed to allow user to create reasonably
simple audio device description using devicetree syntax. The bindings
currently include only the absolute minimum set required for headset
example. Bindings for other entities (Clock Selector, Clock Multiplier,
Mixer Unit, Selector Unit, Feature Unit, Sample Rate Converter,
variuos Effect Units, various Processing Units, Extension Unit) can be
added later together with the actual USB class implementation.
The main idea is that user does create one zephyr,uac2 compatible node
for every USB Audio 2 class instance. Note that in majority of cases
just one USB Audio 2 class is necessary because the number of streaming
interfaces is virtually unlimited (USB Audio 2 class can have up to 255
entities). The zephyr,uac2 node includes child nodes with compatibles
set to desired entity or audiostreaming interface. The parent-child
relationship is necessary to allow grouping entities to correct audio
class instance.
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
The gpio_pca953x gpio driver doesn't have
the input latch and interrupt mask
configuration which causes a lack of accessing
and using those features on an gpio expander
device. Fix it by adding input latch and
interrupt mask configurations in this driver.
Signed-off-by: Vudang Thaihai <vudang.thaihai@brillpower.com>
The LIS2DU12 is a linear 3-axis accelerometer with advanced digital
functions whose MEMS and ASIC have been expressly designed to build
an outstanding ultralow-power architecture in which the anti-aliasing
filter operates with a current consumption among the lowest in the
market.
This driver is based on stmemsc HAL i/f v2.3
https://www.st.com/en/datasheet/lis2du12.pdf
Signed-off-by: Armando Visconti <armando.visconti@st.com>
The STM32F722 is similar to the STM32F723, but lacks the latter's
more advanced USB PHY. Otherwise, they are virtually identical.
Signed-off-by: Evan Perry Grove <evan@4grove.com>
Add support for enabling the clock security system, which can detect
failures of the HSE clock.
Includes tests for nucleo_h743zi and nucleo_g474re.
Signed-off-by: Kevin ORourke <kevin.orourke@ferroamp.se>
Rename the native Linux SocketCAN driver to reflect that it can can now be
used in both native_posix and native_sim (with or without an embedded
C-library).
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Add SMBus devices to all SoCs which have either
a st,stm32-i2c-v1 or st,stm32-i2c-v2.
Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
Change the name of the node for the lptim used as lowpower
tick source to stm32_lp_tick_source.
Once enabled, this node is known as stm32_lp_tick_source
That will avoid naming the node lptim1 or lptim2 or lptim, etc.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The commit fixes the SHA driver because the ROM API has the following
changes from ES to QS chip:
1. base addres: from 0x13c -> 0x148
2. required SHA context buffer size : from 228 -> 240 bytes
This change also adds a check for the pre-allocated buffer size of the
SHA context when the driver initiliazes.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Add "st,hci-spi-v1.yaml" to represent STMicroelectronics SPI protocol V1
which is used by BlueNRG-MS devices.
Add "st,hci-spi-v2.yaml" to show STMicroelectronics SPI protocol V2
utilized by BlueNRG-1 and successor devices.
Signed-off-by: Ali Hozhabri <ali.hozhabri@st.com>
Add support for uc8175 display driver. uc8175 has a slightly
different command/data length requirements for certain registers,
namely TRES and PTL, compared to uc8176/uc8179
This commit refactors the driver code and such that setting TRES and PTL
registers are now done by function pointers provided by config->quirks,
by the same token as how it is done for setting CDI register
Signed-off-by: Xiao Qin <xiaoq@google.com>
This patch adds definitions for the nRF9151,
which is software-compatible with nRF9161.
Signed-off-by: Maximilian Deubel <maximilian.deubel@nordicsemi.no>
Add `compatible` node to Ambiq SoCs, along with secondary common compat,
since they share many similarities.
Signed-off-by: Mateusz Karlic <mkarlic@antmicro.com>
- PHY can be set up as rmii but still use 25 MHz MDC, add DT property
value for this case
- Fix KSZ8081 driver spamming phy status in debug level logging,
and fix some other state/logging logic
- Fix PHY driver not rescheduling monitor work if first configuration
fails, change code path to use goto for errors
- Handle case where some phys are not using the gpio pins in phy driver
Make GPIO properties of ksz8081 phy optional since these hardware pins
may be unused on some boards
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Define the edge-trigger register base address based on whether
the PLIC node in the devicetree has an additional compatible
that supports edge-triggered interrupt.
Limited the implementation to Andes NCEPLIC100 only, updated
the devicetree binding of `andes_v5_ae350` accordingly.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Add code to configure and program Lcu, Trgmux and Emios_Icu IPs to
get the the rotations by the motor in radians.
Co-authored-by: Benjamin Perseghetti <bperseghetti@rudislabs.com>
Co-authored-by: Peter van der Perk <peter.vanderperk@nxp.com>
Co-authored-by: Mayank Mahajan <mayankmahajan.x@nxp.com>
Signed-off-by: Sumit Batra <sumit.batra@nxp.com>
