The LPC platforms define memory in SRAM blocks that can be
combined to represent larger memory blocks to the CPU. Change
the M4 allocation to use SRAM0+SRAM1 for 128K.
Signed-off-by: David Leach <david.leach@nxp.com>
LPC platforms define multiple SRAM memory blocks that are contiguous
in memory but the zephyr build system doesn't have a method to
specify all the nodes to be used for a CPU's chosen "zephyr,sram"
node. To be able to get full use of memory, sram0 is redefined to
80KB in size.
Fixes#43872
Signed-off-by: David Leach <david.leach@nxp.com>
remove existing SDMMC SPI driver, since it is replaced by the SPI mode
SD host controller driver.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
with the legacy USDHC driver fully removed from the tree, the
nxp,imx-usdhc binding can now be used for the new SD host controller
driver.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
all in tree SOCs with the USDHC peripheral have now been converted to
use the new SD host controller USDHC driver, so remove legacy NXP disk
USDHC driver.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
added support for NXP iMX RT600/RT500 to use to SDHC driver, with SD
subsystem. Tested with RT685 EVK
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add SDHC driver implementing spi mode support for SD cards. This driver
implements the standard SD host controller APIs, and sets the host
property "is_spi" to indicate to the SD subsystem the card will be
running in SPI mode.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add generic SDHC dts binding, as well as DTS binding for NXP USDHC.
Update iMX.RT DTS binding to use USDHC compatible
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Changes signature so it takes uint32_t instead of pointer to a
register.
Later `sys_read*` and `sys_write*` functions are used, which cast
given address to volatile pointer anyway.
This required changing types of some fields in LiteX GPIO driver and
removal of two casts in clock control driver.
There was a weird assert from LiteX GPIO driver, which checked whether
size of first register in dts was a multiple of 4.
It didn't make much sense, so I removed it.
Previous dts was describing size of a register in terms of subregisters
used. New one uses size of register, so right now it is almost always
4 bytes.
Most drivers don't read register size from dts anyway, so only changes
had to be made in GPIO and clock control drivers.
Both use `litex_read` and `litex_write` to operate on `n`bytes.
Now GPIO driver calculates this `n` value in compile time from given
number of pins and stores it in `reg_size` field of config struct like
before.
Registe sizes in clock control driver are hardcoded, because they are
tied to LiteX wrapper anyway.
This makes it possible to have code, independent of CSR data width.
Signed-off-by: Michal Sieron <msieron@internships.antmicro.com>
Make the LSE driving capability configurable for the STM32 series.
Fixes#44737.
Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
Fix the descriptions for the ST STM32 FDCAN devicetree bindings. These
are derivates of the Bosch M_CAN, but they target specific SoC
implementations.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Rename the base Bosch M_CAN CAN-FD controller devicetree binding to
match the product name and the upstream Linux devicetree binding.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Fold the simple bosch,m-can devicetree binding into the front-end
devicetree bindings. The bosch,m-can compatible is not used in Zephyr.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
MCP4728 is a 12-bit, Quad Digital-to-Analog Converter with EEPROM Memory.
Controlled via I2C interface.
Signed-off-by: Marek Janus <marek.janus@grinn-global.com>
In 92d8329d5b a new DT property was introduced to set the WQ priority
of the instance. The fallback value when the property was not present
was arbitrarily set to <0 PRIO_PREEMPT>.
The problem is that this value is actually changing the behaviour for
the code that is not explicitly setting the DT property, breaking in
some cases the existing code.
Move the default value to <0 PRIO_COOP> to give the old code a
consistent behaviour before and after the 92d8329d5b commit.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Add a GPIO pass-thru map for accessing the full range (0 to 39) of ESP32
GPIO pins by their datasheet number.
GPIOs 0 to 31 are mapped to gpio0 while GPIOs 32 to 39 are mapped to
gpio1.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
This is a follow-up to commit 1a01ca2adf.
Since support for pinctrl has been added to the qdec_nrfx driver,
the related binding can no longer require the `a-pin` and `b-pin`
properties to be defined.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Add DT option to configure the data ready interrupt mode.
Latched is the default; pulsed can be enabled through
the drdy-pulsed DT, if desired.
Signed-off-by: Maxime Vincent <maxime@veemax.be>
Add FDS (Filtered Data Type Selection) + High-Pass reference mode support
(FDS in CTRL6, HP_REF_MODE in CTRL7)
Values are configurable through DT per instance.
Signed-off-by: Maxime Vincent <maxime@veemax.be>
fvp-baser-aemv8r has four pl011_uart devices and all of then have
been added in this patch.
only uart0 and uart1 are enabled as default in fvp_baser_aemv8r.dts
Signed-off-by: Huifeng Zhang <Huifeng.Zhang@arm.com>
STM32WB55xG MCUs include 256 KiB of SRAM split into three banks.
The size of the main bank is 192 KiB, and not 96 KiB as it was
specified in the device tree. This commit fixes the issue and
also updates the definition of the NUCLEO-WB55 board, based on
a STM32WB55RG MCU.
Signed-off-by: Thomas Altenbach <taltenbach@witekio.com>
The PWM period cell will soon be required by the pwm_dt_spec facilities,
this patch adds support for it.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The binding has no corresponding driver and it is not referenced
anywhere, so drop it.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The binding did not define the PWM cells. Only channel and period have
been added as they are the minimum required ones (flags are not supported).
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The PWM period cell will soon be required by the pwm_dt_spec facilities.
This patch adds support for it.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
In order to be consistent with other platforms, include the PWM
dt-bindings by default.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The PWM period cell will soon be required by the pwm_dt_spec facilities.
This patch adds support for it.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The period cell will soon be required by the pwm_dt_spec facilities,
this patch adds support for it.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
In order to be consistent with other platforms, include the PWM
dt-bindings by default.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The PWM period cell will soon be required by the pwm_dt_spec facilities,
this patch adds support for it.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The period cell will soon be required by the pwm_dt_spec facilities,
this patch adds it.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Include the PWM dt-bindings by default, so that boards can use utilities
like PWM_MSEC() without extra includes. This is a common pattern done
for e.g. i2c or gpio.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The period cell will soon be required by the pwm_dt_spec facilities,
this patch adds it. Note that flags have not been added as they are
optional and not supported anyway.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Introduce has-interrupt-mask-reg DTS property for nxp,pca95xx driver.
This additionnal property allow to specify that the gpio expander has an
interrupt mask register that must be configured by the driver.
This allow to use this driver with PCAL95xx.
This fixes issue #44834.
Signed-off-by: Xavier Chapron <xavier.chapron@stimio.fr>
In order to be consistent with other platforms, include the PWM
dt-bindings by default.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
NXP LPUART IP supports loopback mode, where TX is internally connected
to RX input. Allow setting loopback mode up via the "nxp,loopback" dts
property.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Align the board dts with the recent changes in the "nordic,nrf-sw-pwm"
binding (remove the no longer existing `channel-count` property) and
add a node representing the edge connector for convenient referring
to SoC pins connected to it.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
