Add MEC175x SoC series support to the Microchip XEC ADC driver.
Refactor the driver to use DTS-encoded GIRQ and PCR properties
instead of series-specific ifdefs, enabling a unified driver
across MEC150x, MEC172x, and MEC175x.
Update mec_adc.h register definitions to support all three SoC
series with proper Kconfig guards for 16-channel ADC variants.
Signed-off-by: Srinivas Edireswarapu <srinivas.edireswarapu@microchip.com>
Add coordinator driver for RISC-V Advanced Interrupt Architecture (AIA)
that provides a unified API wrapping APLIC and IMSIC operations.
The coordinator simplifies application code by providing wrapper functions
for common AIA operations:
- IRQ enable/disable: Manages IMSIC EIID enable/disable
- Source configuration: Configures APLIC source trigger modes
- MSI routing: Routes APLIC sources to specific harts and EIIDs
- Source enable: Enables APLIC interrupt sources
- GENMSI injection: Software-triggered MSI via APLIC GENMSI
Note: In AIA-MSI mode, APLIC sources and IMSIC EIIDs are decoupled.
irq_enable() only enables the EIID in IMSIC; APLIC sources must be
configured separately via the source configuration APIs.
Signed-off-by: Afonso Oliveira <afonso.oliveira707@gmail.com>
Add RISC-V APLIC driver split into shared core and MSI-specific
modules following the GICv3/ITS pattern:
- intc_riscv_aplic_priv.h: private header with struct aplic_cfg,
register helpers, and aplic_msi_init() declaration
- intc_riscv_aplic.c: core driver with domain enable, source
configuration, device instantiation; calls aplic_msi_init()
when CONFIG_RISCV_APLIC_MSI is enabled
- intc_riscv_aplic_msi.c: MSI-specific code for APLIC target
routing, GENMSI injection, and MSI address geometry setup
This split allows direct delivery mode support to be added later
without touching MSI code.
Signed-off-by: Afonso Oliveira <afonso.oliveira707@gmail.com>
Add RISCV_APLIC base Kconfig (enabled by DT_HAS_RISCV_APLIC_ENABLED)
and RISCV_APLIC_MSI sub-config that is only available when every APLIC
node in the devicetree has an msi-parent property. This prevents
build failures when APLIC is used in direct delivery mode without an
IMSIC. Update CMakeLists.txt to build intc_riscv_aplic.c for the
base config and intc_riscv_aplic_msi.c for the MSI sub-config.
Signed-off-by: Afonso Oliveira <afonso.oliveira707@gmail.com>
Replace open-coded fragment loop with NET_PKT_FRAG_FOR_EACH() macro
in eth_dwc_xgmac_send().
Signed-off-by: Muhammad Waleed Badar <walid.badar@gmail.com>
Replace open-coded fragment loop with NET_PKT_FRAG_FOR_EACH() macro
in eth_intel_igc_tx_data().
Signed-off-by: Muhammad Waleed Badar <walid.badar@gmail.com>
Move SSDE enable after preload to prevent premature SSL interrupts
Fix DMA fallback to always have ISR variables available
Signed-off-by: Mohamed Azhar <mohamed.azhar@microchip.com>
Switch interface gating from carrier on/off to the dormant flag,
matching nrf_wifi/nxp/airoc/esp_at/esp_hosted. Carrier is set
once at init; dormant toggles per association on STA and per
AP_START/AP_STOP on AP. This preserves IP and IPv6 link-local
state across transient drops instead of tearing them down.
Allow AP TX in AP_STARTED and AP_DISCONNECTED (no clients yet,
or last client left) in addition to AP_CONNECTED, so broadcast
traffic is not rejected with -EIO.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
The driver on init currently only updates control register bits that
differ from their reset values, implicitly assuming that all other
bits are still in their default state.
This assumption can break if the registers were previously modified,
e.g. 12-hour mode was selected, leading to invalid time readings
such as 32:57:12 from rtc_get_time().
Fix this by explicitly programming all control register fields
to the configuration expected by the driver, instead of relying
on the hardware reset state.
Signed-off-by: Tim Pambor <tim.pambor@codewrights.de>
atcwdt200 already supports the CONFIG_WDT_DISABLE_AT_BOOT feature.
However, HAS_WDT_DISABLE_AT_BOOT was not enabled in the driver config layer
at that time.
This PR fixes that issue.
Signed-off-by: Kevin Wang <kevinwang821020@google.com>
DLISTSTART is a 32-bit hardware register, while the indirect display
list pointer is represented as a pointer. Assigning the pointer directly
to the register triggers -Wint-conversion with newer GCC versions.
Cast through uintptr_t before converting to uint32_t to make the address
conversion explicit.
Signed-off-by: Zhaoming Li <lizhaoming634@gmail.com>
add reset controller support for the NXP ACMP driver
and use reset controller APIs if available.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
PatchRAM records store the HCI opcode as a little-endian value in the
firmware image. Read it with sys_get_le16() instead of casting the byte
pointer to uint16_t, which can fault on targets that do not allow
unaligned accesses.
Signed-off-by: Matthias Ringwald <matthias@ringwald.ch>
This algorithm is not actually supported by the driver; don't select the
Kconfig option saying the driver supports it.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Add configurable timeout(forever by default) for waiting on
data valid interrupt to prevent blocking forever if the
interrupt is unexpectedly disabled.
If k_sem_take() times out, disable adc interrupt and then
read adc value if the data is valid as fallback path.
Signed-off-by: Ren Chen <Ren.Chen@ite.com.tw>
Edge devices have multiple addresses for the external memory.
SAHB (0x60.., 0x70.. for ns and s access respectively) which
are uncached but programmable and CBUS (0x08.. and 0x18..
for ns and s access respectively) which are cached and improve
performance.
Additionally, cm33 can use both SAHB aliases and CBUS alises
but cm55 can only use SAHB aliases.
Therefore this commit redefines entirely the memory map to
use mapped partitions are offsets from the base region and
selecting the base region accordingly for
the three use cases. (cm33s, cm33ns - for eval board, cm55).
To this selected set USE_DT_CODE_PARTITION
to yes for all cores in defconfig.
Additionally cleaned up config BUILD_OUTPUT_ADJUST_LMA to be
more clear in its use.
Updated the custom linker script with the mapped partitions
updates that were added to the base linker ascript in arm.
Updated the metadata function to handle the addresses
gymnastics.
Signed-off-by: Laura Carlesso <laura.carlesso@infineon.com>
Fix missing last period when running samples/drivers/pwm/event. The last
period was incomplete because it is stopped immediately before the new
period became effective.
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
Use dt_compat_any_has_prop for CONFIG_UART_MCHP_DMA_DRIVEN to allow
mixed DMA/interrupt configurations. Added has_dma field and runtime
checks to select transfer mode per UART instance based on device tree
dmas property presence.
Signed-off-by: Fabin V Martin <Fabinv.Martin@microchip.com>
Add a generic GPIO driver for a memory-mapped output latch register.
Include the driver implementation and devicetree binding.
Also add the required Kconfig and CMake integration.
Signed-off-by: Zhaoming Li <lizhaoming634@gmail.com>
Refactor the Microchip XEC tachometer driver to use DTS-encoded
GIRQ and PCR properties instead of series-specific ifdefs,
enabling a unified driver across MEC150x, MEC172x, and MEC175x.
Fix build error from incorrect PCR devicetree configuration.
Remove duplicate include and add missing static qualifier to
tach_xec_sample_fetch().
Co-authored-by: Andy Chang <andy.chang@microchip.com>
Signed-off-by: Andy Chang <andy.chang@microchip.com>
Signed-off-by: Srinivas Edireswarapu <srinivas.edireswarapu@microchip.com>
Fix misaligned break statements in pwm_xec_pm_action() switch-case
block to match the case indentation level.
Signed-off-by: Srinivas Edireswarapu <srinivas.edireswarapu@microchip.com>
Refactor the Microchip XEC PWM driver to use DTS-encoded PCR
property via soc_xec_pcr_sleep_en_clear(), replacing per-SoC
ifdefs for PCR init. Move PCR enable before pinctrl apply in
the init sequence.
Signed-off-by: Srinivas Edireswarapu <srinivas.edireswarapu@microchip.com>
Added latch detection mode based on DTS property.
Required register is inaccessible in non-secure
builds and on nRF54H20 SoC. Added hidden Kconfig
to guard it.
Signed-off-by: Michał Stasiak <michal.stasiak@nordicsemi.no>
Building mr_canhubk3 fails due to improper function declaration.
Fix issue by fixing declaration of eth_nxp_s32_start & eth_nxp_s32_stop.
Fixes issue #108630.
Signed-off-by: Gal Raifen <galraifen15@gmail.com>
Rather than passing every possible script into the common modem
instantiation macro, use a struct to hold all the scripts and pass the
struct instead.
The advantage of this approach is that it makes adding new optional
scripts much less invasive. The script only needs to be added to the
struct and populated in the drivers that will use it, no need to modify
the global macro.
Signed-off-by: Jordan Yates <jordan@embeint.com>
Use the correct timing properties for bee_keyscan configuration.
- use common.poll_period_us for manual scan timer
- calculate rel_cnt from release_time_us
- fix autoscan build assert guard
- remove stale debounce_down_us assertion
This fixes mismatched devicetree property usage in the driver.
Signed-off-by: Yuzhuo Liu <yuzhuo_liu@realsil.com.cn>
the virtio driver is using k_aligned_alloc and therefore
uses the system heap, add the
HEAP_MEM_POOL_ADD_SIZE_VIRTIO Kconfig,
so we have enought heap for it.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
Fix two issues in DMA driver:
1. ISR was invoking callback for all interrupts including suspend.
Add check to invoke callback only for transfer complete (TCMPL)
or transfer error (TERR) interrupts.
2. dma_get_status returned stale pending_length after config/reload
because write-back descriptor was not synced with base descriptor.
Sync write-back in dma_mchp_config and dmac_desc_reload_block.
Also improve type safety by changing void* to dmac_descriptor_registers_t*
in descriptor setup functions.
Signed-off-by: Arunprasath P <arunprasath.p@microchip.com>
Use dt_compat_any_has_prop for CONFIG_I2C_MCHP_DMA_DRIVEN to allow
mixed DMA/interrupt configurations. Added has_dma field and runtime
checks to select transfer mode per I2C instance based on device tree
dmas property presence.
Signed-off-by: Fabin V Martin <Fabinv.Martin@microchip.com>
Add a retained memory driver for GD32 backup SRAM.
The driver exposes the memory region defined by devicetree reg, enables
the BKPSRAM clock gate, and optionally enables a vin-supply regulator
for retention power.
Signed-off-by: Aleksandr Senin <al@meshium.net>
Add a regulator driver for the GD32 Backup SRAM LDO (BLDO) controlled via
PMU. This enables modelling BLDO as a standard supply in devicetree
(vin-supply) and allows consumers to request retention power through
the regulator API.
Signed-off-by: Aleksandr Senin <al@meshium.net>
Introduce Kconfig symbol to add mutex lock protection to the driver API.
Prevent multi-threaded access from a pre-emptive thread.
Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
Enable the optional clock described in devicetree during eDMA
driver initialization.
Keep RT7xx request-enable programming in board init so this
branch only moves the clock-control portion into the driver.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
Add RT7xx eDMA clock IDs to the MCUX SYSCON clock bindings and
handle them in the shared clock control driver.
This provides the common gate support needed for RT7xx eDMA
instances to be managed through the clock control API.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
Add optional devicetree reset support to the MCUX eDMA
driver and deassert the reset line during initialization
when a reset specifier is provided.
Boards which do not describe a reset remain unchanged.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
Align eth_wch with updated ethernet API by passing net_if to
and eth_wch_stop/start() from PHY link state change handling.
Signed-off-by: Fabian Blatz <fabianblatz@gmail.com>
