The PDP context might be active.
If that's the case, the AT+QIACT command returns an error.
It's then not possible to succeed at setting up the module.
Furthermore, we apply the logic described in the Quectel Documentation :
- If there is an issue 3 consecutive times on activating/deactivating
the context, we restart the module.
- If the AT+QIDEAT command returns an error, we restart the module.
This PR is bug-fix aimed.
We leave parameterization of context ID for future enhancement.
Signed-off-by: Thomas LE ROUX <thomas.leroux@smile.fr>
In NPCX7 series, it contains two tachometer (TACH) modules that contains
two Independent timers (counter 1 and 2). They are used to capture a
counter value when an event is detected via the external pads (TA or
TB).
The CL also includes:
— Add npcx tachometer device tree declarations.
— Zephyr sensor api implementation for tachometer.
— Enable "tach1" device in npcx7m6fb.dts for testing.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
The stm32 uart driver fails to build on certian platforms due to
changes introduced by:
commit 3c18bcbf77
Author: Francois Ramu <francois.ramu@st.com>
Date: Wed Jan 27 10:27:33 2021 +0100
drivers: serial: stm32 restore uart after lowpower
Fix this by adding some ifdef's around the code that is specific to the
given platforms that the code works on.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Current implementation of uart_npcx_irq_{tx,rx}_ready always returns
false if the respective interrupt enable bit is not set, which means
that the api cannot be used if the interrupts are temporarily disabled
for whatever reasons, breaking patterns such as [1].
Other uart drivers also seems to not have this check, this patch removes
it from the NPCX driver too.
[1] https://github.com/zephyrproject-rtos/zephyr/blob/master/drivers/console/uart_console.c#L549
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Since the uart device clock will be stopped after ec entered sleep or
deep sleep state and restore its clock automatically, there is no need
to implement code for suspending and resuming devices manually.
The driver still needs to check the current status of uart device when
it wants to change its power state to LOW or SUSPEND power state. It is
crucial to forbid ec enters sleep or deep sleep state when uart device
is busy with transmitting data. Or we will observe broken characters on
the uart console.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This CL introduces power management driver that improves the efficiency
of ec operation by adjusting the chip’s power consumption to the level
of activity required by the application in npcx series.
The following list summarizes the main properties of the various chip
power states. Please refer the power.c file for more detail.
Main power states in npcx series include:
- Active: Core, RAM and modules operate at the clocks generated by PLL.
- Idle: Enter this state when the Core executes WFI or WFE instruction.
- Sleep: clock is stopped for most of modules but PLL is enabled.
- Deep Sleep: As Sleep mode but PLL is disabled.
- Standby: All power rails are turned off besides standby and battery
power rails.
And this CL implements one power state, PM_STATE_SUSPEND_TO_IDLE, with
two sub-states for Zephyr power management system.
Sub-state 0 - "Deep Sleep" mode with “Instant” wake-up if residency
time is greater or equal to 1 ms
Sub-state 1 - "Deep Sleep" mode with "Standard" wake-up if residency
time is greater or equal to 201 ms
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This CL introduces a kernel device driver implemented by the internal
64/32-bit timers in Nuvoton NPCX series. Via these two kinds of timer,
the driver provides an standard "system clock driver" interface.
It includes:
- A system timer based on an ITIM64 (Internal 64-bit timer) instance,
clocked by APB2 which freq is CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC.
- Its prescaler is set to 1 and provide the kernel cycles reading
without handling overflow mechanism.
- A event timer based on an ITIM32 (Internal 32-bit timer) instance,
clocked by LCLK which frequency is 32KHz and still activated when ec
entered "idle/deep idle" power state for better power consumption.
- Its prescaler is set to 1 and provide timeout event mechansim.
- Compensate system timer which clock is gating for better power
consumption after ec left"idle/deep idle" power state.
This CL passed starve, timer_api, and timer_monotonic test suites.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This will export the stm32_clock_control_init function
to restore the clocks after the low power modes.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Rework the checks for INPSEL, INNSEL, and C0_OFFSET_BIT presence to
avoid warnings when -Wexpansion-to-defined is enabled.
The warning was enabled in c7bc6380bd.
Fixes#32475.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
This fixes the logic in erase_sector() for clearing the previous
sector number. The logic was reversed, clearing bits it should not
clear and keeping previous bits of the sector number. In practice this
does not seem to have had any effect on the current functionality, but
it will start to matter later if e.g. flash interrupts are enabled.
Signed-off-by: Göran Weinholt <goran.weinholt@endian.se>
Modifications to incorporate latest write to new flash area
Modification to avoid writing garbage to new flash area when compactor
is called during init.
Modifications to allow erase at partition size instead of eeprom
pagesize.
Modifications to better separate rambuf usage from flash usage.
Corrected some errors in compactor
Signed-off-by: Laczen JMS <laczenjms@gmail.com>
This driver emulates a EEPROM device in flash.
Reworked implementation with modified flash layout.
The emulation represents the EEPROM in flash as a region that is a
direct map of the eeprom data followed by a region where changes to
the eeprom data is stored. Changes are written as address-data
combinations. The size of such a combination is determined by the
flash write block size and the size of the eeprom (required address
space), with a minimum of 4 byte.
The eeprom page needs to be a multiple of the flash page. Multiple
eeprom pages is also so supported and increases the number of writes
that can be performed.
The eeprom size, pagesize and the flash partition used for the eeprom
are defined in the dts. The flash partition should allow at least two
eeprom pages. For fast read access a rambuffer can be enabled for the
eeprom (by setting the option rambuf in the dts).
Signed-off-by: Laczen JMS <laczenjms@gmail.com>
CAN_SYNC_SEG and ts1 are in common units. Both need to be scaled by 1000
to calculate the sample point.
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
In the npcx i2c FIFO mechanism, the hardware will release SCL bus
immediately after the driver reads data from FIFO. That's why we need
to hold SCL bus before configuring the next transaction. Once it was
done, the driver release the bus for the next transaction.
But during the last transaction, the driver releases SCL first then
starts a STOP condition. At this moment, the SCL is pulled high by PU
resistance and driven to low for generating STOP condition later. This
additional clock might influence some i2c devices if they don't reset
their state machine after receiving STOP.
This CL fixes this issue by two steps:
1. Distinguish that it's the last read transaction with STOP condition?
2. If so, issue STOP condition before reading FIFO instead of holding
SCL bus. Then the hardware will generate it immediately after reading
FIFO.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
The definition to check if timers have up to 6 channels was causing
warnings when -Wexpansion-to-defined was enabled.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
The first uart instance was already devicetree based. To be consistent
convert the second instance to also be devicetree based.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
QDEC_NRFX shall depend on either HAS_HW_NRF_QDEC,
or HAS_HW_NRF_QDEC0, since in the nRF5340 Application
core definition we select HAS_HW_NRF_QDEC0 instead of
HAS_HW_NRF_QDEC.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
While running certain peci command, observed when FW attempts
to read last byte (Response FCS), PECI host controller returned
“Read FIFO” empty. Since “Read FIFO” is empty FW didn’t read
the response FCS.
Due to this issue, FW getting corrupted response from the PECI
controller for all the subsequent PECI commands.
To address this issue, FW waits for “Read FIFO” filled up by
the PECI controller.
Signed-off-by: Diwakar C <diwakar.c@intel.com>
Convert from device_get_binding to DEVICE_DT_GET. In doing this we
no longer need the label in the devicetree node so we remove that.
Removed all __ASSERT_NO_MSG(clk) since we'll get a build error if
DEVICE_DT_GET cant be satisfied, and the clock control api's will
handle reporting if the device_is_ready.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This fixes a missing bit in the registers description
which results to wrong FIFO ODR configuration
when trying to configure a FIFO ODR higher than 833Hz
Signed-off-by: Clotilde Sattler <clotilde.sattler@stimio.fr>
Switch to use DEVICE_DT_GET instead of device_get_binding for pinmux
device. As part of this change drop the "label" property from
the pinmux devicetree node and update the binding and dts files to
reflect that.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
