Otherwise a glitch can appear on the PWM output when the GPIOTE channel
is reconfigured (when GPIOTE releases the pin, GPIO takes control and
drives it to the last written state which may be different than that
used recently by GPIOTE).
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Rework the devicetree definition for smsc91x to put the mdio and
ethernet device at the same level, and make the phy a child of the mdio
node.
This allows matching up the device initialization sequence with the
devicetree hierarchy.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Move few variable inside a case statement to avoid build warning for
unused variables in some specific configuration.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
This driver implements an MDIO device. Enable the MDIO driver to avoid a
build error for:
orphan section `._device.static.3_CONFIG_MDIO_INIT_PRIORITY_'
Also set the proper compatible in mdio_shell so that the ethernet tests
build correctly.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Rename the STM32H7 FDCAN driver Kconfig symbol and implementation file to
match the naming used in the ST reference manuals.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Rename the STM32 FDCAN driver Kconfig symbol and implementation file to
match the naming used in the ST reference manuals.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Rename the STM32 bxCAN driver DTS compatible, Kconfig symbol, and
implementation file to match the naming used in the ST reference manuals.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Fold the contents of the private header for the STM32 bxCAN driver into the
implementation file.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
The timing_max parameters defined in the stm32 bxcan driver don't match the
register description in the reference manuals.
- sjw does have only 2 bits representing 1 to 4 tq.
- phase_seg1 and phase_seg2 max is one tq higher.
I have checked the following reference manuals and all match:
- RM0090: STM32F405, F415, F407, F417, F427, F437 AND F429
- RM0008: STM32F101, F102, F103, F105, F107 advanced arm-based mcus
- RM0351, RM0394: all STM32L4
- RM0091: all STM32F0 with CAN support
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
Following #60410, the NXP S32 external interrupt controller device
initializes after the core interrupt controller. Bump the NXP S32 intc
init level to initialize after the core intc and before the GPIO
device driver.
Fixes#61218
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Check the packet lenght in flash_write operation beforeSigned-off-by
copying it to an internal buffer.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
In case CAN-FD mode is not enabled the mcux flexcan driver supports
CAN_MODE_3_SAMPLES.
This has been removed inadvertently while adding can-fd support.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
Add ipm driver to use Inter Processor Interrupts
on Xilinx ZynqMP platform. This patch also adds sample
application that shows use of xlnx ipm driver.
This driver uses default arm gic interrupt controller
and works only for lockstep mode of cortex-r5f
cluster for now.
In split mode the cortex-r5 cluster will
have two r5f cores and they are expected to work in AMP
mode. If both r5f cores run simultaneouly, only one of
the core is able to receive IPI interrupts at this time
and it will be the one that started later. In future
this limitation shall be removed.
Signed-off-by: Tanmay Shah <tanmay.shah@amd.com>
the dev pointer is already dereferenced before this function is
called, so this check does not make any sense.
Signed-off-by: Jacob Siverskog <jacob@teenage.engineering>
Following #56576, the `cs` field in `struct spi_config` is of type
`struct spi_cs_control` instead of a pointer to the same type.
This PR updated the driver to use `spi_cs_is_gpio()` helper to
check if SPI CS is controlled using a GPIO.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
This change introduces a new PWM driver for all CC13/26xx SoC.
See the documentation in ti,cc13xx-cc26xx-timer-pwm.yaml for detailed
usage instructions.
Signed-off-by: Florian Grandel <fgrandel@code-for-humans.de>
In case of HDA Link DMA FIFORDY bit is RO according
to HW specification thus should be managed by HDA controller.
Add a logic to set FIFORDY for HDA Host DMA only
Signed-off-by: Ievgen Ganakov <ievgen.ganakov@intel.com>
Allow properties 'regulator-min-microvolt' and 'regulator-max-microvolt'
for fixed regulators: Note: they should be equal.
Add simple functions for getting list of allowed and count of voltages.
Signed-off-by: Mykola Kvach <mykola_kvach@epam.com>
Possible situation is that in some driver, devices can be controlled in
different ways: in some, we can only turn the power on or off, in others,
we can only control the voltage, and in some, we can control power supply
or voltage level. There may also be devices where there is no control
over power supply at all. A clear example of this can be eMMC devices
where the voltage is usually fixed and they are always powered on.
However, we would like to have a common code for controlling all the
mentioned types of devices, at least the driver shouldn't worry about the
implementation details of voltage regulators. Therefore, there may exist
empty regulators - regulators that only contain information about the
supported voltage, and we cannot change anything in them. The device tree
node description for such a regulator is only necessary for compatibility
with other regulators. Hence, we need to add the possibility of the
existence of such a dummy fixed-regulator.
In this commit, support for a fixed dummy regulator without the ability
for any control has been added. Note that such support also exists in the
Linux kernel. In other words, the logic of the fixed regulator has been
aligned with the logic of the fixed regulator inside the Linux kernel.
Signed-off-by: Mykola Kvach <mykola_kvach@epam.com>
This commit removes the direct calls of the PPP API of the
network device used by gsm_ppp.c
These calls are now performed by the L2 PPP interface when it
is brought up or down using net_if_up() or net_if_down()
Signed-off-by: Bjarki Arge Andreasen <bjarkix123@gmail.com>
Some architectures such as RISC-v support more than 255 interrupts
per aggrigator. This diff adds the ability to forgo the aggrigator
pattern and use a configurable number of bits for multilevel
interruts.
Signed-off-by: Joshua Lilly <jgl@meta.com>
Select PCIE and DYNAMIC_INTERRUPTS as they are needed for driver to
work. This allows to remove board configuration overlay files.
Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
Looking back at the current INPUT_LISTENER_CB_DEFINE api naming, it
feels like it's a bit overloaded. Rename it to a simpler
INPUT_CALLBACK_DEFINE.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
This fixes a shadow variables found by -Wshadow.
The variable ep_ctx is only used in certain switch cases
so declare it when it is needed.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Removes the shadow variable found by -Wshadow. The value of this
variable is the same throughout the for loop, so there is no
need to assign it again for each iteration.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
TC "test_single_shot_alarm_notop" is failing because there were 2 ISR
callbacks instead of one. this is because of invoking
ifx_cat1_counter_set_int_pending incorrectly. Updated
ifx_cat1_counter_set_alarm to fix this
Signed-off-by: Sreeram Tatapudi <sreeram.praveen@infineon.com>
