The `fcntl.h` header has never been a part of ISO C so move it to
`include/zephyr/posix`.
To ensure a smooth migration, a header was left in
`lib/libc/minimal/include` that prints a deprecation warning.
Users should either include `<zephyr/posix/fcntl.h>` or switch to
`CONFIG_POSIX_API=y`.
Signed-off-by: Chris Friedt <cfriedt@meta.com>
In case user didn't set mac address in any way (locally defined or
randomly generated), define mac address using device unique id.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Deprecate Kconfig mac address related symbols and replace by existing
device tree properties:
- local-mac-address
- zephyr,random-mac-address
User who wants to keep using deprecating method of defining random
MAC address using Kconfig should set CONFIG_ETH_STM32_HAL_RANDOM_MAC=y.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
In order to ease deprecation of these methods (in favor of dt based
configuration), introduce a choice for MAC address configuration method.
Default to random method (no change).
User wanting to still use ETH_STM32_HAL_MACX symbols should define
CONFIG_ETH_STM32_HAL_USER_STATIC_MAC=y
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Setting a detected packet family (ipv4 or ipv6) in net_context level
instead in lower layers for AF_PACKET/SOCK_RAW/IPPROTO_RAW type sockets
when sending data.
Signed-off-by: Jani Hirsimäki <jani.hirsimaki@nordicsemi.no>
BUCK1/2 are defined as "always on" regulators, however, there is a
special override register that allows to turn them on/off.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Some regulators are enabled by default, however, such condition cannot
be captured now by the regulator driver API. Refactor
regulator_common_init_enable to regulator_common_init (enable removed,
as it also sets mode) and add a new argument to specify such condition.
With this change, regulator_disable() and regulator_is_enabled() work as
expected without a first call to regulator_enable().
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Vbus detection is required by self-powered, with external non-USB
supply, devices to have an operational USB peripheral. The voltage
sensing, when enabled, is performed via a designated pin (PA9 is
the most common).
For greater details see section 2.6, ST application note AN4879.
Signed-off-by: Raul Pando <raul.pando@bytegrity.co.uk>
When using watchdog which doesn't support callbacks (e.g. STM32 IWDG)
it's very useful to have counter based watchdog with shorter timeout.
This way we can gather useful information before IWDG resets SOC.
In above case it's usually not desired to reset SOC when counter
watchdog is triggerd, because we can lose information about reset cause.
For example, STM32 can determine if the reset was caused by watchdog.
Another use case for counter watchdog without SOC reset is to detect
slow code paths.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
Now that both RTC source clock Kconfig symbols are disabled by default,
we invert the ifdef so that in the absence of configuration we still
fall in the LSI configuration.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Following #50104, properly deprecates old Kconfig symbols concerning
RTC source clock and makes them optional to have them disabled by
default.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Now that compatible is directly linked with driver version,
use DT compat based Kconfig flag to build the correct flash driver
version.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Instead of introducing a vX driver version, use series name.
With this commit F0, F1, F3, L0 and L1 series are using F1 flash driver.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Instead of relying on STM32Cube API, use clock_control framework
for clock configuration inside this driver.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
In preparation of the introduction of dt configured clock in this
driver, refactor clock related clocks.
- remove start_ble_rf()
- Move IPCC clock activation in c2_reset()
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
As long as LSE clock is set in device tree, configuration will be
done in clock control driver, no need to do it here.
Besides, remove back up domain related code as this is also already
handled in clock_control driver.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Remove code related to LSI used as clock source for RF wakeup,
it isn't a valid clock source.
Also don't disable LSI when LSE is selected.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Update the SBS Gauge driver that implements the fuel_gauge API to implement
a set_property function allowing the writing of an SBS word to the
manufacturer access register per the SBS spec.
Includes an update to the SBS Gauge emulator and SBS fuel gauge tests to
weakly verify the code runs.
Signed-off-by: Aaron Massey <aaronmassey@google.com>
Implement and weakly test fetching the manufacturer access word from an SBS
compatible fuel gauge.
Signed-off-by: Aaron Massey <aaronmassey@google.com>
Current divisor is 10000000 (should be 1000000).
For example, ESP32_CLK_CPU_240M / 10000000 == 24 MHz (incorrect).
Signed-off-by: Chris Wilson <christopher.david.wilson@gmail.com>
This change for addressing the below symptoms.
Two FW images have different h2ram offset settings.
Jumping to each other will cause offset setting errors.
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
At default, IBF (input buffer full) interrupt status will be cleared
after reading keyboard data input register (KBHIDIR) in ISR.
For request to clear OBF (output buffer full), we need to enable clear
mode. In the mode, IBF status cannot be cleared by reading KBHIDIR
register. It means that if AP output data to 60h/64h port during the
mode enable, IBF interrupt will keep triggering until the watchdog is
reset. This patch addresses this issue.
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Following updates previously done for other drivers, rename all
occurrences of S32 to NXP S32 to avoid ambiguity.
Signed-off-by: Manuel Arguelles <manuel.arguelles@nxp.com>
Following updates previously done for other drivers, rename all
occurrences of S32 to NXP S32 to avoid ambiguity.
Signed-off-by: Manuel Arguelles <manuel.arguelles@nxp.com>
Following updates previously done for other drivers, rename all
occurrences of S32 to NXP S32 to avoid ambiguity.
Signed-off-by: Manuel Arguelles <manuel.arguelles@nxp.com>
Add support FD frame filter to configure type frame for
each Rx msg to receive corresponding frames (classic, FD frames).
The Bosch M_CAN driver does not support FD frame filter,
so inmplement driver to handle it in software.
Signed-off-by: Cong Nguyen Huu <cong.nguyenhuu@nxp.com>
The number of extended filters can be up to 15 for MCUs like the NXP
LPC55Sxx series, so the flags don't fit into uint8_t.
Fixes#53417
Signed-off-by: Martin Jäger <martin@libre.solar>
hal_espressif systimer HAL calls are based on 1MHz reference.
This changes systimer driver to allow max clocking reference of 16MHz
and increases soc tick resolution by reducing min delay interval.
This also sets all ESP32-C3 socs to 16MHz hardware cycles reference.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
ISO/IEC 9899:1999 (C Standard), §7.4 Character handling <ctype.h>:
In all cases the argument is an int, the value of which shall be
representable as an unsigned char or shall equal the value of the macro
EOF. If the argument has any other value, the behavior is undefined.
So add a cast to unsigned char to make sure we do not trigger UB.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Introduce driver for APS6408L PSRAM, built on top of the MCUX memc
driver for flexSPI. This driver supports operating the PSRAM in high
speed mode (200MHz or more). Note that in order to support this
PSRAM's alignment requirements, either ahb-read-addr-opt or
ahb-prefetch must be set for the FlexSPI instance.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
memc driver was setup to always assume the flexSPI would be in XIP mode,
and skip init. This is only true for the active flexSPI, which is
typically FlexSPI1. Fix this check to only skip init for FlexSPI1
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Rename flexspi-hyperram driver to flexspi-s27ks0641, and update
function names. This driver is only capable of supporting the
s27ks0641 HyperRAM chip, as the lookup table given in this driver
is specific to the s27ks0641.
Rename the flexspi-hyperram binding to reflect this, to
prevent confusion from users.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Printing of NACK messages should be set to LOG_DBG to avoid spamming.
When we scan whether there is a target device through I2C, if we use
LOG_ERR, it will frequently print out NACK messages. So it is set to
LOG_DBG in the case of NACK.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Fix a bug that causes not handling an IDLE line detection interrupt for
some STM chips, e.g. STM32F412. It impacts the async UART
communication - an information that data have been recieved is lost.
The issue occurs when the IDLE flag is set during handling another UART
interrupt, e.g Transmission complete. The ISR calls uart_stm32_err_check
function, which clears the noise error flag with LL_USART_ClearFlag_NE
without any additional checks. Unfortunately, clearing the noise flag
also clears the IDLE flag for some chips(an read to the USART_SR
register followed by a read to the USART_DR register for STM32F412
clears PE, FE, NF, ORE and IDLE flags), hence the ISR is not called
again for the IDLE event. The IDLE flag is no longer set.
Add checking the noise flag before clearing it.
Signed-off-by: Dawid Niedzwiecki <dn@semihalf.com>
ESP32 and ESP32-S2 HW clock are tied to DTS clock configuration.
This changes updates the default configuration to retrieve
this information from DTS.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Only relocate memc driver when CONFIG_FLASH=y.
CONFIG_FLASH_MCUX_FLEXSPI_XIP previously was dependent on
CONFIG_FLASH, but the scope of this Kconfig has changed.
Due to this, the memc driver now must have two checks, as it should not
relocated when the driver is being used for a memory controller that does
not expose the flash driver interface.
Since the NXP HAL also relocates the underlying FlexSPI driver
using a similar check, it is updated in this commit as well.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
The addresses of the flash and flash controller of the RP2040
SoC were mixed up. There was no clear distinction between the
flash and the flash controller, which was unclear but also
caused a DTC warning.
This commit makes the distinction clearer: The SSI peripheral at
0x18000000 is the flash controller, and the flash itself starts
at 0x10000000. The flash driver and rpi_pico.dts were fixed
accordingly.
Signed-off-by: Yonatan Schachter <yonatan.schachter@gmail.com>
