Microchip MEC172x has a modified eSPI SAF hardware implementation.
Hardware changes include multiple clock dividers for each SPI
flash device and data transfer using QMSPI local DMA.
espi reset interrupt is made a higer priority in MEC172x devicetree
because espi reset event resets all espi hardware and we don't
to want to service any other espi interrupt blocks when espi reset
occurs.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Microchip MEC172x QMSPI expanded its clock divider register
field from 8 to 16 bits. QMSPI source clock is on the fast
peripheral domain therefore get the frequency from the clock
control driver.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Microchip MEC172x CPU and fast peripheral (QMSPI and PK) are
clock source is based upon an OTP setting. Add logic to adjust
clock source based on OTP value. If the OTP value is ever changed
this fix will allow calcluation of correct clock rate.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Remove all obsolete DISK_FLASH* Kconfig options.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
Use devicetree to obtain information for all zephyr flash disks.
Co-authored-by: Johann Fischer <johann.fischer@nordicsemi.no>
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
In order to avoid using multiple sources of truth for the platfom's
endianness, convert the in-tree code to use the (BIG|LITTLE)_ENDIAN
Kconfig variables exclusively, instead of the compiler's
__BYTE_ORDER__.
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
GICR_TYPER is a 64 bit register. On AArch32 when one uses sys_read64(),
this results in ldrd instruction. When Zephyr runs as a VM, 'LDRD'
instruction on an emulated MMIO region gets trapped to the hypervisor as
data abort.
Refer the following paragraph from ARM DDI 0487G.b ID072021 :-
Section - "ISS encoding for an exception from a Data Abort",
"For other faults reported in ESR_EL2, ISV is 0 except for the following
stage 2 aborts:
AArch32 instructions where the instruction:
— Is an LDR, LDA, LDRT, LDRSH, LDRSHT, LDRH, LDAH, LDRHT, LDRSB, LDRSBT,
LDRB, LDAB, LDRBT, STR, STL, STRT, STRH, STLH, STRHT, STRB, STLB, or STRBT
instruction."
As 'LDRD' is not in the list, so ISV==0. This implies that Arm could not
decode the instruction for the hypervisor (in EL2) to execute it.
Thus, we have abstracted this read into arm_gic_get_typer().
For AArch64, we use sys_read64() as before.
For AArch32, we use sys_read32() twice to read the lower and upper 32 bits
of GICR_TYPER.
Thus, we ensure that when the access is trapped for AArch32, Arm generates
a valid ISS so that hypervisor can execute it.
Signed-off-by: Ayan Kumar Halder <ayankuma@amd.com>
To avoid legacy extended adv repots blocking important
events or work, mark them as discaradble.
Signed-off-by: Martin Tverdal <martin.tverdal@nordicsemi.no>
Print the error messages about the state of the host register
when the I2C transfers fail. This is useful for debugging.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
DMIC does not need to use SOFT_RESET bit to start collecting data if
periodic_start bit is enabled.
Signed-off-by: Damian Nikodem <damian.nikodem@intel.com>
If cfg_hi and cfg_lo are not set to zero in config setting, different
dma slot value is bitwise ORred to the previous set value. Thus fix it.
Signed-off-by: Jaska Uimonen <jaska.uimonen@linux.intel.com>
This adds an entropy driver calling the PSA Crypto psa_generate_random()
API to get random bytes.
Currently this only uses the TFM provided psa_generate_random().
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Valerio Setti <vsetti@baylibre.com>
Refactors all sensor drivers to use SENSOR_DEVICE_DT_INST_DEFINE, which
is a sensor-specific variant of DEVICE_DT_INST_DEFINE that provides a
common place to instantiate additional data structures for the future
sensor subsystem and/or sensor driver stats.
This approach was inspired by I2C_DEVICE_DT_INST_DEFINE to streamline
adding I2C stats support across all I2C drivers.
Signed-off-by: Maureen Helm <maureen.helm@intel.com>
Without this define, the structure iis2dh_device_config
is defined incorrectly.
The structure is defined in iis2dh.h file as follows:
struct iis2dh_device_config {
struct spi_dt_spec spi;
struct i2c_dt_spec i2c;
uint8_t pm;
struct gpio_dt_spec int_gpio;
};
without the macro
the structure is defined as
struct iis2dh_device_config {
uint8_t pm;
struct gpio_dt_spec int_gpio;
};
which results in accessing the wrong data when
calling iis2dh_init_interrupt
function (or any other functions in this file)
Signed-off-by: Mehdi Zemzem <mehdi.zemzem2@gmail.com>
Move runtime checks to use arch_num_cpus() and build checks
to use CONFIG_MP_MAX_NUM_CPUS. This is to allow runtime
determination of the number of CPUs in the future.
Signed-off-by: Kumar Gala <kumar.gala@intel.com>
While the 'count' value "should" never be larger than two digits,
increase the size of the snprintk buffer to be large enough to hold
the longest possible value.
Signed-off-by: Keith Packard <keithp@keithp.com>
The can_frame and can_filter structs support a number of different flags
(standard/extended CAN ID type, Remote Transmission Request, CAN-FD format,
Bit Rate Switch, ...). Each of these flags is represented as a discrete bit
in the given structure.
This design pattern requires every user of these structs to initialize all
of these flags to either 0 or 1, which does not scale well for future flag
additions.
Some of these flags have associated enumerations to be used for assignment,
some do not. CAN drivers and protocols tend to rely on the logical value of
the flag instead of using the enumeration, leading to a very fragile
API. The enumerations are used inconsistently between the can_frame and
can_filter structures, which further complicates the API.
Instead, convert these flags to bitfields with separate flag definitions
for the can_frame and can_filter structures. This API allows for future
extensions without having to revisit existing users of the two
structures. Furthermore, this allows driver to easily check for unsupported
flags in the respective API calls.
As this change leads to the "id_mask" field of the can_filter to be the
only mask present in that structure, rename it to "mask" for simplicity.
Fixes: #50776
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Replace usage of CONFIG_MP_NUM_CPUS with CONFIG_MP_MAX_NUM_CPUS for
init and declaration as we phase out CONFIG_MP_NUM_CPUS usage.
Signed-off-by: Kumar Gala <kumar.gala@intel.com>
Replace unnecessary `BT_HEXDUMP_DBG` with `LOG_HEXDUMP_DBG`.
`BT_HEXDUMP_DBG` did an extra cast to `const uint8_t *` on its first
argument. This was probably the reason it was introduced. But the
current definition of `LOG_HEXDUMP_DBG` does this cast for us.
Signed-off-by: Théo Battrel <theo.battrel@nordicsemi.no>
It looks like this platform is using soc.h to declare some display APIs,
imxrt_pre/post_init_display_interface(). This likely deserves a better
design, but for now let's fix compiler warnings.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Update TCPC driver to use DT_HAS_<compat>_ENABLED Kconfig symbol
to expose the driver and enable it by default based on devicetree.
Signed-off-by: Sam Hurst <sbh1187@gmail.com>
The "@return" command should be used for the arbitrary return
description, and "@retval <return value>" for the description
of named return value
Signed-off-by: Sam Hurst <sbh1187@gmail.com>
Use DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) to determine
number of potential interrupt sources. This mitigates
the wasting of memory on devices with mutliple UCPD ports
but only one UCPD port is used.
Signed-off-by: Sam Hurst <sbh1187@gmail.com>
Assign the pins for the STM32G071b and STM32G081b STM32
UCPD peripherals so the UCPD driver can properly
configure the device.
Signed-off-by: Sam Hurst <sbh1187@gmail.com>
When there is a timeout for an i2c transaction, the i2c driver should do
the recovery logic to make the bus and driver state machine go back to
idle. Otherwise, it will cause the following transaction to fail because
the state machine keeps in an inappropriate state.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Executing code out of RAM on IT8xxx2 requires that the relevant
addresses be mapped onto the CPU's instruction memory bus, referred to
by ITE documentation as Instruction Local Memory (ILM). ILM mappings
configure blocks of RAM to be used for accesses to chosen addresses when
performing instruction fetch, instead of the memory that would normally
be accessed at that address.
ILM must be used for some chip features (particularly Flash
self-programming, to execute from RAM while writing to Flash), and has
historically been configured in the Flash driver. The RAM for that was
hard-coded as a single 4k block in the linker script. Configuring ILM
in the flash driver is confusing because it is used by other SoC code as
well, currently in code that cannot depend on the Flash being functional
or in hand-selected functions that seem performance-critical.
This change moves ILM configuration to a new driver and dynamically
allocates RAM to ILM in the linker script, allowing software use of the
entire 64k RAM depending on configuration. This makes ILM configuration
more discoverable and makes it much easier to correctly support the
CODE_DATA_RELOCATION feature on this SoC.
Signed-off-by: Peter Marheine <pmarheine@chromium.org>
ADC comparator driver submits notifications into system work queue, this
change will make driver to use dedicated work queue instead by using
`CONFIG_ADC_CMP_NPCX_WORKQUEUE`.
Dedicated work queue and priority are configurable as well.
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
If we are dropping packets, then drop then early without the clone, this
improves zperf performance.
Signed-off-by: Krishna T <krishna.t@nordicsemi.no>
Change for loops of the form:
for (i = 0; i < CONFIG_MP_NUM_CPUS; i++)
...
to
unsigned int num_cpus = arch_num_cpus();
for (i = 0; i < num_cpus; i++)
...
We do the call outside of the for loop so that it only happens once,
rather than on every iteration.
Signed-off-by: Kumar Gala <kumar.gala@intel.com>
Possibility to configure i2c speed through I2C_SHELL
command `i2c speed`.
Signed-off-by: Andrzej Kuros <andrzej.kuros@nordicsemi.no>
Signed-off-by: Jędrzej Ciupis <jedrzej.ciupis@nordicsemi.no>
Some files were using definitions from sys_clock.h, e.g. MSEC_PER_SEC
without including the header.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Currently, uart_npcx_pm_policy_state_lock* functions are guarded by
CONFIG_UART_INTERRUPT_DRIVEN && CONFIG_PM. However, it is unnecessary to
guard them with CONFIG_UART_INTERRUPT_DRIVEN as the polling mode UART
driver also uses these functions.
This commit removes it and leaves those functions guarded by CONFIG_PM
only.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
