Add Driver for KSZ8081 Ethernet PHY. The Generic MII Driver
is not sufficient to use for this PHY chip which has special
vendor implemented behaviors.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Add a property to the ethernet controller binding
indicating what type of connection the MAC has with
the PHY device.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
The Device Multiplexer (devmux) is a pseudo-device that can
be used to select between multiple included sub-devices.
It is experimental, but its current use is in system
remediation. Take for example, the scenario where the
system console and log subsystem both have the uart backend
enabled. The case may arise, where the chosen backing uart
could be an abstraction of another very high-bandwidth bus
- such as a PCIe BAR, a UDP socket, or even even just memory.
If the "service" (for lack of a better term) that backs this
abstract "uart" experiences an error, it is of critical
importance to be able to switch the system console, uart log
backend, or whatever to another uart (semi-transparently) in
order to bring up a shell, continue to view system logs, or
even just support user console I/O.
Signed-off-by: Christopher Friedt <cfriedt@meta.com>
Adds the tja1103 enet phy for setting phy options on the mr_canhubk3.
Co-authored-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Co-authored-by: Peter van der Perk <peter.vanderperk@nxp.com>
Signed-off-by: Benjamin Perseghetti <bperseghetti@rudislabs.com>
MDIO controller is part of GMAC and it requires GMAC ethernet driver to
initialize first because it will reset the whole GMAC hw block during
initialization. Both C22 and C45 APIs are supported.
Co-authored-by: Benjamin Perseghetti <bperseghetti@rudislabs.com>
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Signed-off-by: Benjamin Perseghetti <bperseghetti@rudislabs.com>
specific to platform, watchdog reset line can be connected either to
CPU, SOC or none of the entity. These resets cannot be configured from the
application. So added a warning message when application configures this
option
Signed-off-by: Balsundar Ponnusamy <balsundar.ponnusamy@intel.com>
added support for watchdog enable/disable at boot
Pausing watchdog timer when CPU is halted by the debugger and
pausing watchdog timer when CPU is in sleep state is not
configurable through application, so added warning log with return success
Signed-off-by: Balsundar Ponnusamy <balsundar.ponnusamy@intel.com>
clearing interrupt flag will not assert the system reset as per IP spec,
so interrupt flag should not be cleared in isr
use #if macro check directly with DT_ANY_INST_HAS_PROP_STATUS_OKAY for
interrupt
Signed-off-by: Balsundar Ponnusamy <balsundar.ponnusamy@intel.com>
mmu enabled platform needs mapping of physical address ranges to
the virtual address at runtime. So using DEVICE_MMIO_* helper macros to
map physical csr address space to RAM runtime if MMU is enabled
Signed-off-by: Balsundar Ponnusamy <balsundar.ponnusamy@intel.com>
This option let specify at startup the zoom factor to apply on the
SDL window. See CONFIG_SDL_DISPLAY_ZOOM_PCT.
Signed-off-by: Arnaud MAZIN <arnaud.mazin@gmail.com>
SysTick usually has higher measurement resolution than the IDLE timer.
When the time in low power mode is very short or 0, it is possible that
SysTick usually has measures more time since the sys_clock_set_timeout
than the idle timer.
Handle that case to keep uptime correct.
Signed-off-by: Dawid Niedzwiecki <dawidn@google.com>
The idle timer has its max value and can overflow. We measure time passed
since the sys_clock_set_timeout call. Take possibility of the overflow
into account.
Signed-off-by: Dawid Niedzwiecki <dawidn@google.com>
When the idle timer is in use, we calculate number of cycles passed
since the sys_clock_set_timeout call.
The cycle counter can overflow easily, when the counter is 32-bit wide.
Handle that case.
Signed-off-by: Dawid Niedzwiecki <dawidn@google.com>
The code to handle OA TC6 compliant device's status is generic and can
be moved to device agnostic driver (oa_tc6.c).
Moreover, the original code has been augmented with LOG_WRN() messages.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
This change fixes semaphores' definition. To be more specific - the
limit was wrongly set to UINT_MAX. With those changes - the 'tx_rx_sem'
now assures that only one execution path (i.e. receiving or sending
data) is executed at a time.
Moreover, the change in 'int_sem' now assures that this semaphore limit,
when reached, is saturated.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
This commit ensures that whole receive function (called from interrupt
handler) is protected by the RX/TX semaphore.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
The oa_tc6_update_buf_info() function returns error code when read
(protected or not) of OA_BUFSTS has been detected.
In that situation - one shall re-start the interrupt thread handling
(and hence correctly re-read value of this register) than use old
(stalled) RCA(RBA) data to read chunks (which may result in lockup).
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Current code sends extra, last chunk, when packet's size is a multiple
of chunk size (i.e. 64 bytes).
This patch fixes this issue by checking this corner case - i.e. if
the modulo division equals to zero.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
The RCA and RBA fields in OA_BUFSTS register are stored with 8 bits each.
On the other hand, when one receives those values in footer, the value
is saturated to 5 bits due to 32 bit size constrain of the footer itself.
To avoid any mismatches - the values read from OA_BUFSTS are saturated
as well.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Zephyr's network stack has issues with network IP header split across
fragments.
To alleviate this problem, the frame would be now aligned to first byte
of the chunk. This would ensure that the header is stored at one network
buffer fragment (as we explicitly set its size to 64B).
Signed-off-by: Lukasz Majewski <lukma@denx.de>
The OA TC6 driver requires some bits manipulations in control registers.
Up till now - it has been implemented as an explicit set of read and write
registers' operations.
One good example would be the oa_tc6_set_protected_ctrl() implementation,
which used such scheme.
This patch brings dedicated function for this operation; oa_tc6_reg_rmw().
The aforementioned oa_tc6_set_protected_ctrl() function now uses it
internally.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Add the missing dependency of the node status value
and enable the driver by default when they are met.
Signed-off-by: Bartosz Bilas <bartosz.bilas@hotmail.com>
Revert "drivers: timer: lptim timer clock on stm32u5 has a prescaler"
This reverts commit c14670abea.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Fixes the routing of the events associated with a secondary
i2c target address being routed to the primary config. The
i2c_target_config/slave_cfg was being selected from the
driver address match but then over written by the primary.
This change fully implements the if/else of 10bit addressing
and includes a assert if the slave_cfg is NULL, and explains
why dual 10bit addresses on STM32 won't work.
Signed-off-by: Tim Woolliscroft <tim@opteran.com>
alarm setting function checks channel callback and it returns -EBUSY
if callback is registered. but alarm cancel function doesn't clear
callback function. this prevents from alarm setting after alarm cancel
Signed-off-by: Minho Jin <kilejin@gmail.com>
This driver assumed the ivshmem-v2 output sections would be mapped
contiguously, which is no longer true.
Modify eth_ivshmem to treat each output section independently
Signed-off-by: Grant Ramsay <gramsay@enphaseenergy.com>
Recent changes to the arm64 MMU code mean that you can no longer map
R/O memory as R/W. Mapping R/W memory now causes a cache invalidation
instruction (DC IVAC) that requires write permissions or else a fault
is generated.
Modify ivshmem-v2 to map each R/O and R/W section individually
Signed-off-by: Grant Ramsay <gramsay@enphaseenergy.com>
Drops calling the UART FIFO read function during the setup
function (when not in async mode) which could cause issues on
some devices since this function is not called in an ISR.
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
The parity, stop bits and data bits config was hard-coded instead of
taken from the device tree.
Signed-off-by: Marco Widmer <marco.widmer@bytesatwork.ch>
Increase the SPI RX driver stack size by 128 bytes. Overflows have
previously been observed on real hardware at the default stack size of
512.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
The `riscv_plic_irq_enable` & `riscv_plic_irq_disable` are very
similar, refactor them out into `plic_irq_enable_set_state`.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Add support of r8a779f0 cpg driver.
r8a779f0 soc has its own clock tree.
Gen4 SoCs common registers addresses have been added in header.
Signed-off-by: Mykola Kvach <mykola_kvach@epam.com>
Signed-off-by: Aymeric Aillet <aymeric.aillet@iot.bzh>
Renesas R-Car Gen4 is different from Gen3 regarding pinmux.
While Gen3 had only one base address to manage all pins,
Gen4 has one set of pinmux registers per GPIO banks.
We could expose one pinmux register per GPIO controllers,
but that would break potential compatibility with Linux
Device tree.
Instead create a reg_base array to parse all reg base from
device tree and identify proper base address based on the pin
definition.
This imply to add a pfc_base parameter to most of the pfc_rcar
function.
Signed-off-by: Julien Massot <julien.massot@iot.bzh>
Signed-off-by: Pierre Marzin <pierre.marzin@iot.bzh>
Signed-off-by: Aymeric Aillet <aymeric.aillet@iot.bzh>
Renesas Gen4 SoCs GPIO IPs are using one more
register comparing to Gen3 SoCs.
The new "INEN" register is used to enable general input.
Signed-off-by: Aymeric Aillet <aymeric.aillet@iot.bzh>
In the case where a transaction is spilt due to the rx buff len
being longer than the tx or the transaction buffer exceeding the
size of the requested buffer with non gpio CS, the chip select
would be de-asserted/asserted in the middle of the transaction.
Fixes: #57577
Signed-off-by: Dean Sellers <dsellers@evos.com.au>
When CONFIG_IEEE802154_RAW_MODE is set there is no network interface
that could provide pointer to the device the interface is running on top
of. The current implementation of nRF5 ieee802154 driver implicitly
assumes that such an interface is always present, which leads to crashes
when raw mode is enabled.
This commit adds support for IEEE802154_RAW_MODE in nRF5 ieee802154
driver by latching pointer to the ieee802154 device on initialization if
needed so that it doesn't have to be retrieved using the network
interface in run-time.
Signed-off-by: Jędrzej Ciupis <jedrzej.ciupis@nordicsemi.no>
