Switching from write to read on EP0 is done when data is
transmitted.
Additionally receiver is enabled when NAK is created in
response to OUT token. This may happen when host sent
ZLP before everything was transmitted.
This case flushed receiver FIFO which could lead to
setup packet corruption.
Signed-off-by: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
Add support for automatic control of PLL for USB subsystem.
This utilized virtual USB clock present in clock control.
USB driver enables PLL when device is attached or USB
sends resume signaling.
PLL can be turned off (if application does not requested it)
when device is detached (application request)
or USB host sends suspend request.
When VBUS is not present or application did not started USB yet
PD_DOMAIN_SYS is also not acquired that allows for deep
sleep. When USB is active deep sleep will never be activated.
Signed-off-by: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
When EP0 was disabled EP0 was setup to ignore setup and
out packets.
In usb_dc_ep_enable() function mask was never cleared.
It resulted in USB stop functioning after application
disabled endpoint (usb_disable()) and then tried
to enable usb again.
Signed-off-by: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
Smartbodn does not have dedicated USB clock.
For USB to work PLL needs to be turned on.
To allow for flexible configuration artificial USB clock
is added that can be operated via clock_control subsystem.
This new clock turns on PLL when USB subsystem is enabled.
PLL can also be request in DT if application requires
more speed.
PLL can be automatically turned off when USB enters suspend
state and application did not requested it.
Signed-off-by: Jerzy Kasenberg <jerzy.kasenberg@codecoup.pl>
The documentation recommends to read and then write-back the entire
register, when ending interrupts.
Signed-off-by: Mateusz Karlic <mkarlic@antmicro.com>
Validate the contents of `struct rtc_time` against the provided mask
when setting time or alarm.
Use the same names of function parameters as those in the RTC Interface.
Signed-off-by: Jakub Topic <jakub.topic@anitra.cz>
The shell tries to decode all channel types and sequential channel
indexes. Unfortunately when swapping to channel specs we forgot to reset
the channel index for the next channel type to look at.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
Removed PM device runtime support from drivers in PD_SYS domain.
Update the rest device drivers to call pm_device_runtime_get/put()
functions when CONFIG_PM_DEVICE_RUNTIME is enabled.
Signed-off-by: Ioannis Damigos <ioannis.damigos.uj@renesas.com>
The following Kconfigs have been deprecated for more than 2
releases, remove them:
- `IEEE802154_CC13XX_CC26XX_SUB_GHZ_RADIO_TX_RETRIES`
- `CONFIG_IEEE802154_2015`
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Selection of these GIC Kconfigs have been deprecated
for more than 2 releases, users should use the devicetree
method instead, update the Kconfigs.
The SOCs below have been updated to not select `GIC_V3`, since
their devicetree already have the required compatible:
- fvp_aemv8r
- rzt2m
- rk3658
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
The following Kconfigs:
- `CONFIG_ETH_STM32_HAL_RANDOM_MAC`
- `CONFIG_ETH_STM32_HAL_USER_STATIC_MAC`
- `CONFIG_ETH_STM32_HAL_MAC3`
- `CONFIG_ETH_STM32_HAL_MAC4`
- `CONFIG_ETH_STM32_HAL_MAC5`
have been deprecated for more than 2 releases, user should
have switched to the devicetree method now, remove them.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
These clock selection Kconfigs should have been deprecated for
more than 2 releases, remove them:
- `CONFIG_COUNTER_RTC_STM32_CLOCK_SRC`
- `CONFIG_COUNTER_RTC_STM32_CLOCK_LSI`
- `CONFIG_COUNTER_RTC_STM32_CLOCK_LSE`
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Update airoc_wifi_host_buffer_get function to set final
buff size based on input “size” param.
Update airoc_mgmt_send to use airoc_wifi_host_buffer_get
instead net_buf_alloc_len.
Signed-off-by: Nazar Palamar <nazar.palamar@infineon.com>
Fixed#74370, the issue is caused by the update to introduce MMIO
mapping, after MMIO mapping, should use data->base for device
base memory address.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
The current atmel,sam-tc-qdec sensor implementation shared the timer
counter node. This create issues when users wants define both modes.
The current proposal changes the qdec dedinition to be a child of
tc and refactor all the chain of definitions.
Fixes#71312
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Replaced the software `reverse` function, used for bit reversal, with
the intrinsic `__RBIT` function.
This utilizes the hardware bit-reversal instruction for improved
efficiency.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
Implementation erroneously used a mask from the ROUTEPEN register
when writing the ROUTELOC register.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Series 2 uses DBUS for alternate function control, which directly uses
port and pin numbers for location selection. Configure pinout as part
of the I2C_SDA/I2C_SCL case, rather than the separate _LOC case,
as the port and pin are not available at this point.
Configure route register prior to enabling the route, to ensure that
the wrong pin is not temporarily claimed.
Fixes an issue where DBUS was always configured to port A and
pin given by the GECKO_LOC() macro, rather than the correct port/pin
pair.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
This commit addresses the issue related to the rtc.h API returning ENOSYS
for a driver not implementing alarm_set_callback when the ALARM
functionality is enabled but interrupts, and thus alarm callbacks, are not
supported by the current configuration.
The following drivers have been modified to return correct code:
- rtc_pcf8523
- rtc_pcf8563
- rtc_rv3028
Signed-off-by: Jakub Topic <jakub.topic@anitra.cz>
Use CAN_CALC_TDCO() macro to set TDCO. There is a minor change how the
tdco is calculated. In the macro the SYNC segement is taken into
account while it wasn't used before.
Fixes#73821.
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
Fill-in the mode field of the fd_entry so that the
implementation can be made aware that the specific file
descriptors created are sockets.
Signed-off-by: Chris Friedt <cfriedt@tenstorrent.com>
Implement absolute minimum necessary to get Buffer DMA working. Require
Data Cache to be disabled if DWC2 OTG has DMA enabled because the stack
does not currently guarantee cache line alignment for allocated buffers.
Set EPENA bit before disabling IN endpoints because it seems to be
necessary in Buffer DMA mode (without EPENA the wait for INEPNAKEFF does
time out). Setting EPENA should have no impact on Completer mode
operation (where EPENA is not necessary for INEPNAKEFF to trigger).
Programming Guide recommends programming SUPCnt to 3, but the only
advantage would be to be able to tell how many back-to-back SETUP packets
were received if there was no more than 3 back-to-back SETUPs. This
information doesn't seem to be useful. The disadvantage is that the
buffer needed for receiving SETUP packet must be able to hold SUPCnt
multiple of 8 bytes. Use SUPCnt 1 so the 8 bytes buffer is enough.
Make sure to clear StsPhseRcvd interrupt bit in Buffer DMA mode because
the DMA seems to prevent the SETUP Phase Done interrupt from triggering
if StsPhseRcvd is set. Clearing this bit doesn't seem to be necessary in
Completer mode. This bit is set on control transfers with data stage
from host to device.
Both Buffer DMA and Completer mode operation on nRF54H20DK was verified
using USB2CV Chapter 9 Tests and MSC Tests with Mass Storage sample.
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
Do not use sys_clear_bits() followed by sys_set_bits() on DCTL register
to avoid writing to DCTL register twice - first with zeroed out address,
and then with the new address. Change the code to write the address in
one DCTL register write.
Do not use sys_set_bits() to set test mode, but rather prepare the
correct value first.
Set DCFG and GUSBCFG registers in one go. There is no point in reading
back the value or doing multiple subsequent writes to these registers.
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
This driver could end up doing a great deal of work inside the ISR when
large SPI transfers were in use, which could cause significant IRQ
latency. For the normal, non-async SPI transfer case, use events to
signal the calling thread to complete the work rather than performing
FIFO transfers inside the ISR.
Signed-off-by: Robert Hancock <robert.hancock@calian.com>
Add an optional DT property to specify the size of the RX/TX FIFO
implemented within the SPI core. The property name used is the same one
used by Xilinx's device tree generator.
When the FIFO is known to exist, we can use the RX FIFO occupancy register
to determine how many words can be read from the RX FIFO without checking
the RX FIFO empty flag after every read. Likewise with the TX FIFO, we can
use the FIFO size to avoid checking the FIFO full flag after every write.
This can increase overall throughput.
Signed-off-by: Robert Hancock <robert.hancock@calian.com>
Add support for a workaround required when using the Xilinx Quad SPI core
with the USE_STARTUP option, which routes the core's SPI clock to the
FPGA's dedicated CCLK pin rather than a normal I/O pin. This is typically
used when interfacing with the same SPI flash device used for FPGA
configuration. In this mode, the SPI core cannot actually take control
of the CCLK pin until a few clock cycles are issued, which would break
the first transfer issued by the core. This workaround applies a dummy
command to the connected device to ensure that the clock signal is in the
correct state for subsequent commands.
See Xilinx answer record at:
https://support.xilinx.com/s/article/52626?language=en_US
Signed-off-by: Robert Hancock <robert.hancock@calian.com>
LPTIM is not available in STOP3 mode, so RTC needs to be used instead.
This code usese similar approach as STM32WBAx for suspend to ram.
The STOP3 is disabled by default in device tree.
Signed-off-by: Adam Berlinger <adam.berlinger@st.com>
Fix timing in suspend-to-ram when using STM32WBA.
Switch to use RTC timer should be done only when idle is set
and LPTIM clocks should be switched off
Signed-off-by: Adam Berlinger <adam.berlinger@st.com>
This style is used in sensor drivers. It's more complicated than the
other way, which is used in different drivers that are not sensor
drivers.
Signed-off-by: Trent Piepho <tpiepho@gmail.com>
The existing code rounded the result to an integer, then multiplied that
integer by 1000000 to get micro-degrees or micro-percent, and then
divided by 1000000 to get whole degrees/percent and took the modulus to
get fractional degrees/percent.
Obviously, multiplying and then dividing an integer by the same value
has no effect!
The result is the humidity and temperature were always rounded down to
the nearest integer.
Fix this to properly keep the fractional component. This is done in a
way that avoids any integer divisions, which are slow on all CPUs, but
especially most microcontrollers, e.g. Cortex-M, lack any integer
division instruction.
Avoiding the base 10 math does not require more code. One just needs to
think in binary and use binary fractions instead of base 10 fractions.
Signed-off-by: Trent Piepho <tpiepho@gmail.com>
The low two bits are not part of the data, but rather "status" bits that
should be masked off.
This is documented in the HTU21D datasheet Edition 8, date 05/2017, pp.
15, and Sensirion SHT21 datasheet version 6, date 10/2022, §6 (wording
exactly the same):
"The two status bits, the last bits of LSB, must be set to ‘0’ before
calculating physical values."
Also Silicon Labs Si7006 example driver code:
/* Swap the bytes and clear the status bits */
return ((data.byte[0] * 256) + data.byte[1]) & ~3;
Since these are the LSBs, it has only a small effect and might not have
been noticed despite being wrong.
While editing this code, switch to using the Zephyr endian conversion
functions intead of a written out conversion.
Add error code to error log message.
Signed-off-by: Trent Piepho <tpiepho@gmail.com>
These three sensor types are all largely compatible. The SHT21 and
HTU21D can be supported by this driver by sending command 0xE3 instead
of 0xE0 to read the temperature.
Mention the sensor names in bindings and Kconfig to help those looking
for support to find it. There have been at least five PRs attempting to
add SHT21 and/or HTU21D support that did not realize the Si7006 is the
same.
As mentioned in PR #22862, the Sensirion SH21 is the original. The dts
bindings are adjusted (in a backward compatible way!) to make the sht21
the base binding and si7006 is derived from that.
Examples of dts compatibles:
TE Connectivity née Measurement Sepcialties HTU21D:
compatible = "meas,htu21d", "sensirion,sht21";
Sensirion SHT21:
compatible = "sensirion,sht21";
Silicon Labs Si7006
compatible = "silabs,si7006";
Silicon Labs Si7021
compatible = "silabs,si7021", "silabs,si7006";
Signed-off-by: Trent Piepho <tpiepho@gmail.com>
Renaming 'LOCAL' to 'RX' and 'REMOTE' to 'TX'.
This seems more descriptive and intuitive to use.
Signed-off-by: Jakub Zymelka <jakub.zymelka@nordicsemi.no>
Add a mailbox driver for VEVIF events (VPR irq).
The driver can be built in either 'rx' or 'tx' configuration.
The VPR sends the event, so it uses the 'tx' configuration,
while the master core uses the 'rx' configuration of the driver
to receive the VPR events.
Signed-off-by: Jakub Zymelka <jakub.zymelka@nordicsemi.no>
The ATXP032 is a NOR flash device that supports up to ~100MHz
octal SDR/DDR with 4MB nonvolatile memory.
The device driver uses MSPI bus API and could be used across different
SoC controllers that implement the MSPI bus API.
Signed-off-by: Swift Tian <swift.tian@ambiq.com>
The APS6404L psram is a quad SDR SPI device that runs up to 100MHz.
It can provide 8MB of external RAM for SoCs that supports XIP feature.
The device driver uses MSPI bus API and could be used across
different controllers that implement the MSPI bus API.
Signed-off-by: Swift Tian <swift.tian@ambiq.com>
