Commit graph

1933 commits

Author SHA1 Message Date
Gerard Marull-Paretas
c66f594c41 drivers: all: rv32m1: remove conditional support for pinctrl
The rvm32m1 platform always uses pinctrl, there's no need to keep
extra macrology around pinctrl. Also updated driver's Kconfig to `select
PINCTRL`.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2023-04-24 13:34:22 +02:00
Gerard Marull-Paretas
989d103d53 drivers: all: mcux: remove conditional support for pinctrl
The MCUX platform always uses pinctrl, there's no need to keep extra
macrology around pinctrl. Also updated driver's Kconfig options to
`select PINCTRL` (note that some already did).

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2023-04-24 13:34:22 +02:00
Francois Ramu
1b2942ffee drivers: serial: stm32U5 uart driver do not toggle the DMA Tx request
Errata sheet of the stm32U5 (ES0499) recommends to avoid clearing
the DMAT bit with LL_USART_DisableDMAReq_TX to re-start
a DMA transfer on the UART Tx block. The function becomes empty.
This is also seen for stm32H5.

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2023-04-20 10:44:07 +02:00
Gerard Marull-Paretas
1eb683a514 device: remove redundant init functions
Remove all init functions that do nothing, and provide a `NULL` to
*DEVICE*DEFINE* macros.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2023-04-19 10:00:25 +02:00
Anisetti Avinash Krishna
79f2b5471c drivers: serial: ns16550: Fixed a bug related to shell failure
Updated boot priority to PRE_KERNEL_1 for all instances
and removed dependency on PCIe. As shell is not working
in a situation where console is using a UART instance
under PCIe and boot priority set to POST_KERNEL.

Signed-off-by: Anisetti Avinash Krishna <anisetti.avinash.krishna@intel.com>
2023-04-13 20:50:41 -04:00
Alberto Escolar Piedras
659e2292a5 soc_inf: Refactor native tasks into own header
The native_tasks definition was directly in the soc_inf soc.h
header. But soc.h pulls a lot of other headers.
Some of those could cause conflicts, say with application
headers, for users who only wanted the be able to register
native tasks in a module.

Let's refactor the native tasks definitions into their own header
and include that header from soc_inf's soc.h.
In this way users who need only need to register a native tasks
can just include posix_native_tasks.h, and all previous users
see no change.

Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
2023-04-13 13:35:20 +02:00
Gerard Marull-Paretas
a5fd0d184a init: remove the need for a dummy device pointer in SYS_INIT functions
The init infrastructure, found in `init.h`, is currently used by:

- `SYS_INIT`: to call functions before `main`
- `DEVICE_*`: to initialize devices

They are all sorted according to an initialization level + a priority.
`SYS_INIT` calls are really orthogonal to devices, however, the required
function signature requires a `const struct device *dev` as a first
argument. The only reason for that is because the same init machinery is
used by devices, so we have something like:

```c
struct init_entry {
	int (*init)(const struct device *dev);
	/* only set by DEVICE_*, otherwise NULL */
	const struct device *dev;
}
```

As a result, we end up with such weird/ugly pattern:

```c
static int my_init(const struct device *dev)
{
	/* always NULL! add ARG_UNUSED to avoid compiler warning */
	ARG_UNUSED(dev);
	...
}
```

This is really a result of poor internals isolation. This patch proposes
a to make init entries more flexible so that they can accept sytem
initialization calls like this:

```c
static int my_init(void)
{
	...
}
```

This is achieved using a union:

```c
union init_function {
	/* for SYS_INIT, used when init_entry.dev == NULL */
	int (*sys)(void);
	/* for DEVICE*, used when init_entry.dev != NULL */
	int (*dev)(const struct device *dev);
};

struct init_entry {
	/* stores init function (either for SYS_INIT or DEVICE*)
	union init_function init_fn;
	/* stores device pointer for DEVICE*, NULL for SYS_INIT. Allows
	 * to know which union entry to call.
	 */
	const struct device *dev;
}
```

This solution **does not increase ROM usage**, and allows to offer clean
public APIs for both SYS_INIT and DEVICE*. Note that however, init
machinery keeps a coupling with devices.

**NOTE**: This is a breaking change! All `SYS_INIT` functions will need
to be converted to the new signature. See the script offered in the
following commit.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>

init: convert SYS_INIT functions to the new signature

Conversion scripted using scripts/utils/migrate_sys_init.py.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>

manifest: update projects for SYS_INIT changes

Update modules with updated SYS_INIT calls:

- hal_ti
- lvgl
- sof
- TraceRecorderSource

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>

tests: devicetree: devices: adjust test

Adjust test according to the recently introduced SYS_INIT
infrastructure.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>

tests: kernel: threads: adjust SYS_INIT call

Adjust to the new signature: int (*init_fn)(void);

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2023-04-12 14:28:07 +00:00
Andriy Gelman
e537410a74 drivers: serial: uart_xmc4xxx: Minor cleanups
Forward return of dma_start() instead of assigning to ret.

Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
2023-04-12 08:59:20 +02:00
Andriy Gelman
321254f433 drivers: serial: uart_xmc4xxx: Fix race condition
Fixes a race condition between uart_xmc4xxx_dma_rx_cb() and rx timeout.
Although uart_xmc4xxx_dma_rx_cb() called k_work_cancel_delayable()
to cancel the timeout callback, it would not actually be cancelled if
the callback was already in a running state.

Fix the race condition by checking if dma transaction is already
completed in the timeout callback.

This also fixes unit test tests/drivers/uart/uart_async_api on
xmc45_relax_kit which started to fail after commit
f3afd5a4c9.

Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
2023-04-12 08:59:20 +02:00
Anisetti Avinash Krishna
2d03aaf99f drivers: serial: ns16550: Add support for Async APIs
Added support for async APIs for ns16550. This will be
enabled by kconfig CONFIG_UART_ASYNC_API.

Signed-off-by: Anisetti Avinash Krishna <anisetti.avinash.krishna@intel.com>
2023-04-06 07:50:42 +00:00
Pieter De Gendt
6b532ff43e treewide: Update clock control API usage
Replace all (clock_control_subsys_t *) casts with (clock_control_subsys_t)

Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
2023-04-05 10:55:46 +02:00
Sylvio Alves
4c86a44bcd driver: usb_serial: esp32c3: fix USB port behavior
- Fixes missing poll out events when UART interrupt is enabled
- Fixes blocking USB interface during board start up.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2023-04-04 14:30:15 +02:00
Andrzej Głąbek
7058f3722e drivers: uart_nrfx_uarte: Revert workaround for bytes dropping
This effectively reverts the following three commits:
- 0f9f18843f
- 6812441099
- 326f7bd450
and also the changes that got copied to the nrf5340_audio_dk_nrf5340
board.

The workaround brings more harm than good. It already required many
tweaks in various tests to make them pass (because it introduced
a significant overhead in processing of the console UART interrupt)
and now it makes the I2S driver tests to fail. It's not reasonable
to add more tweaks in Zephyr tests just to keep this workaround in
the tree. Instead the root cause should be fixed (if the original
problem still occurs).

Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
2023-04-04 13:45:17 +02:00
Pawel Czarnecki
9f10881f1d drivers: uart: gecko: add support for efr32xg24
Add missing case when there is only one USART

Signed-off-by: Pawel Czarnecki <pczarnecki@antmicro.com>
2023-04-04 13:34:45 +02:00
Anisetti Avinash Krishna
26133e995d drivers: serial: ns16550: Enable simultaneous support of IO, MMIO and PCIe
Enabled simultaneous support by adding a DTS variable named “io-mapped”.
There are 3 possibilities through instance in dtsi file.
Under PCIe, PCIe ns16550.
Under soc and has a variable io-mapped, legacy(IO mapped).
Under soc and don’t have a variable io-mapped, MMIO mapped.
Simultaneous access can be enabled by a Kconfig.
For PCIe instances UART initialization should be done post-kernel as it
depends on PCIe initialization.

Co-authored-by: Najumon BA <najumon.ba@intel.com>
Signed-off-by: Anisetti Avinash Krishna <anisetti.avinash.krishna@intel.com>
2023-03-30 09:43:29 -04:00
Jordan Yates
f423ec255f serial: rtt: select SERIAL_SUPPORT_ASYNC
The RTT serial drivers support the async API, so select the approriate
symbol.

Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
2023-03-30 09:51:18 +02:00
Henrik Brix Andersen
c41dd36de2 drivers: kconfig: unify menuconfig title strings
Unify the drivers/*/Kconfig menuconfig title strings to the format
"<class> [(acronym)] [bus] drivers".

Including both the full name of the driver class and an acronym makes
menuconfig more user friendly as some of the acronyms are less well-known
than others. It also improves Kconfig search, both via menuconfig and via
the generated Kconfig documentation.

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
2023-03-28 15:06:06 +02:00
Romain Mahoux
b096e092fa drivers/apbuart: correct the baud formula
The formula of set_baud first function was not consistent with the get_baud
one.

Signed-off-by: Romain Mahoux <romain@mahoux.fr>
2023-03-27 22:15:33 +00:00
Fabian Blatz
6180f96799 serial: Add driver for emulated UART
The emulated UART controller will aid in automated
integration testing.

Signed-off-by: Fabian Blatz <fabianblatz@gmail.com>
2023-03-27 09:50:44 +02:00
Dean Sellers
8eddd48615 drivers: uart: esp32: Add RS485 half duplex hardware mode
Support for the hardware mode where pin configured as DTR
is asserterted when UART transmits.

Signed-off-by: Dean Sellers <dsellers@evos.com.au>
2023-03-22 13:52:25 +01:00
Gerson Fernando Budke
f21c936d49 drivers: serial: sam: Update to use clock control
This update Atmel SAM uart and usart  drivers to use clock control
drivers.

Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
2023-03-21 14:12:25 -07:00
Anisetti Avinash Krishna
00991e4720 drivers: serial: ns16550: Moved PCIe probe to init function
Moved PCIe probe from configure function to init function
because whenever uart_configure api is called MMIO address
is getting updated.

Signed-off-by: Anisetti Avinash Krishna <anisetti.avinash.krishna@intel.com>
2023-03-21 18:10:12 +00:00
Anisetti Avinash Krishna
712dab4f04 drivers: serial: ns16550: Fixed set_baud_rate usage in line ctrl set
Added pclk parameter to set_baud_rate function in line_ctrl_set api
which was missed during update of set_baud_rate function definition
update.

Signed-off-by: Anisetti Avinash Krishna <anisetti.avinash.krishna@intel.com>
2023-03-21 18:10:12 +00:00
Robert Hancock
86e1740cfc serial: xilinx: uartlite: Fix infinite spin in xlnx_uartlite_fifo_read
The xlnx_uartlite_fifo_read function would spin indefinitely if there
was less data available in the RX FIFO than the size of the passed-in
buffer. This call is supposed to be non-blocking.

Fixed to break out of the loop if there are no more bytes left in the RX
FIFO.

Signed-off-by: Robert Hancock <robert.hancock@calian.com>
2023-03-20 10:21:37 +01:00
Evgeniy Paltsev
56572687c7 drivers: serial: add virtual uart over ARC hostlink channel
Add support for virtual UART device that uses ARC Hostlink channels
for data transfers. Due to the Hostlink principle, this driver
supports only polling API.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Evgeniy Paltsev <PaltsevEvgeniy@gmail.com>
2023-03-17 11:49:02 +01:00
Artur Rojek
14912d241c nxp: imx: Implement iuart clock gating
Add clock control support for UART controllers found in i.MX SoC family.
This change moves clock gating out of respective `soc.c` files and into
clock controller's `clock_control_on`/`_off` methods, allowing for
dynamic clock state control, and setup via Device Tree bindings.

This is especially important on SoCs, where Zephyr is sharing the bus
with cores running other OSes, such as might be the case for i.MX 8MM.

Unfortunately, Zephyr doesn't possess an ability to represent clock
hierarchy (e.g. via DT's `assigned-clocks` property), so clock source
and frequency still need to be hardcoded in aforementioned `soc.c`
files.

Signed-off-by: Artur Rojek <artur@conclusive.pl>
2023-03-15 09:13:10 +01:00
Jeppe Odgaard
c3b6ad07c1 drivers: uart: mcux_lpuart: add parity support
Read and use device tree parity value.
If the property is not set parity none is used.

Signed-off-by: Jeppe Odgaard <jeppe.odgaard@prevas.dk>
2023-03-09 09:20:44 +01:00
Grant Ramsay
9df37fff79 drivers: serial: Add pinctrl support to the NS16550 driver
This enables configuring pins for the UART

Signed-off-by: Grant Ramsay <gramsay@enphaseenergy.com>
2023-03-02 13:50:06 +01:00
Nazar Palamar
f956e81bb6 drivers: serial: Add Infineon CAT1 UART driver
Added initial version of Infineon CAT1 UART driver.
Added initial version of binding file for Infineon CAT1 UART driver.

Signed-off-by: Nazar Palamar <nazar.palamar@infineon.com>
2023-03-01 11:44:57 +01:00
Gerard Marull-Paretas
27b73a116f soc: arm: nordic_nrf: replace NRF_DT_CHECK_PIN_ASSIGNMENTS
Since PINCTRL and pinctrl-0 is now required, there's no point in doing
extra validation at driver level. Modify the macro to just check that
sleep state is present when needed, since it was the only remaining
assertion that was not covered. Renamed the macro to make it more clear
what it does: NRF_DT_CHECK_NODE_HAS_PINCTRL_SLEEP

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2023-02-28 08:42:05 -08:00
Gerard Marull-Paretas
aa9df1abc0 drivers: serial: nrfx_uart/e: drop -pin support
UART/E driver will only support using pinctrl now.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2023-02-28 08:42:05 -08:00
Sylvio Alves
f1cc21a146 driver: uart: esp32s3: enable ESP32S3 uart interface
Includes additional SoC specific headers.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2023-02-27 19:41:33 +01:00
Jordan Yates
b83cf1f1ee drivers: serial: uart_rtt: fix multi-channel
Populate the `channel` index when constructing configuration structs for
secondary RTT channels. Originally missed in #27704.

Fixes #54955.

Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
2023-02-25 06:55:58 -05:00
Grant Ramsay
f92dd6d357 drivers: serial: Name the NS16550 variant Kconfig choice
Naming this choice allows setting a default value in defconfig.

Signed-off-by: Grant Ramsay <gramsay@enphaseenergy.com>
2023-02-24 18:11:56 +01:00
Goh Shun Jing
9ecfa4decc drivers: serial: uart_altera: add driver
Add driver for altera avalon uart core.

Signed-off-by: Goh Shun Jing <shun.jing.goh@intel.com>
2023-02-23 09:26:33 +01:00
Mulin Chao
809e63a91a driver: uart: npcx: add missing tx/rx interrupt enabled checks
When checking if any UART TX/RX IRQs are pending, the driver should also
consider whether these IRQs are enabled. Or we still get pending status
set even if the related interrupts are disabled.

Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
2023-02-22 16:30:08 +01:00
Mulin Chao
dbc614ee10 driver: uart: npcx: avoid concurrency writing UFTCTL register
In order to avoid concurrency situation during writing UFTCTL register,
this CL adds critical sections to prevent the unexpected result if the
driver wants to set/clear bits of this register.

Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
2023-02-22 16:30:08 +01:00
Andriy Gelman
4e13e6ada7 drivers: serial: xmc4xxx: Fix Kconfig help entry
The configurations are no longer hard coded for UART_0.

Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
2023-02-21 21:15:53 +01:00
Andriy Gelman
30b11260be drivers: uart_xmc4xxx: Add async support
Adds async uart for xmc4xxx SoCs.

Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
2023-02-21 21:15:53 +01:00
Andriy Gelman
cfeaada65e drivers: uart_xmc4xxx: Change order of functions
This patch is in preparation of uart async support. There are no
functional changes. The patch changes the ordering of functions to
organize shared functions between async/interrupt driven in the same order.
Also move uart_xmc4xxx_init() so that a forward declaration can be
removed.

Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
2023-02-21 21:15:53 +01:00
Andriy Gelman
3dac715569 drivers: uart_xmc4xxx: Split up tx/rx into separate service requests
In preparation for async support. In async uart, service requests are
forwarded to separate dma lines. This patch splits up tx/rx into
separate service requests to enable this.

Also put service request enable code into a separate function. Before,
the same code was generated for different uart devices.

Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
2023-02-21 21:15:53 +01:00
Muhammed Ahmed
3f0fc7fe6b drivers: serial: Add PM support for UART MCUX
Adding PM support to uart_mcux by gating clock and disabling transmitter

Signed-off-by: Muhammed Ahmed <muhammed.ahmed@intel.com>
2023-02-19 20:56:16 -05:00
Ramon Aerne
a5e04ccd4a drivers: serial: rp2040: fix rpi pico address mapping
Address map used for config item `uart_dev` and `uart_regs` is
currently derived using the rpi hal macros `uart0` and `uart1`
which map to the same register address as given in the `reg` property
of the devicetree.

However, the sdk macro is generated using `uart##idx` which zephyr does
not necessarily map to uart0 or uart1.
This is, for example, the case when disabling uart0 with the devicetree
status "disabled"
and enabling uart1 for which then the idx==0 and not 1 which therefore
maps to the wrong controller address space.

This can simply be fixed by deriving the base address from
`DT_INST_REG_ADDR(idx)` instead

Signed-off-by: Ramon Aerne <ramon.aerne@axelera.ai>
2023-02-09 23:40:38 +01:00
Francois Ramu
7dff172519 drivers: serial: stm32 uart driver avoid LOG_WRN when going to sleep
When the LOG_WRN is used on stm32 uart driver it could block
execution : when pin state for sleep mode is not defined by the DTS
even if no error is raised, LOG_ msg is crashing when entering sleep mode.

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2023-02-09 13:14:46 +01:00
Fabio Baltieri
20644536b9 uart: microchip: fix build error with PM_DEVICE=n
Fix a build error when the driver is built with:

CONFIG_PM=y
CONFIG_PM_DEVICE=n
CONFIG_UART_INTERRUPT_DRIVEN=y
CONFIG_UART_CONSOLE_INPUT_EXPIRED=y

due to uart_xec_pm_policy_state_lock_get() and rx_refresh_timeout_work()
declared under different configuration options.

Fixes: 343d1919f1 "uart: microchip: add low power & wake support"
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
2023-01-30 18:54:59 +00:00
Jay Vasanth
343d1919f1 uart: microchip: add low power & wake support
changes to support low power and wake support in microchip xec uart
driver. Add support for wakerx_gpio config in dts to select the wake gpio.
Configure for wake in PM_DEVICE_ACTION_SUSPEND state and clear
interrupt in wake isr. Also added support for
CONFIG_UART_CONSOLE_INPUT_EXPIRED

Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
2023-01-27 14:25:58 -05:00
Goh Shun Jing
5858cca8b8 drivers: serial: uart_altera_jtag: enhancement
implement uart poll in and interrupt driven api.

Signed-off-by: Goh Shun Jing <shun.jing.goh@intel.com>
2023-01-27 14:24:43 -05:00
Shawn Nematbakhsh
1d3fb5490f drivers: serial: Add support for OpenTitan serial UART
UART output confirmed to work in simulation.

Signed-off-by: Shawn Nematbakhsh <shawn@rivosinc.com>
2023-01-27 19:25:26 +09:00
Cyril Fougeray
51fa86bb98 drivers: exti: stm32: expose STM32_EXTI_LINE_NONE
Common STM32_EXTI_LINE_NONE for declaration and setting
of wakeup EXTI line when configured.

Signed-off-by: Cyril Fougeray <cyril.fougeray@worldcoin.org>
2023-01-27 01:02:08 +09:00
Mulin Chao
5973a944af Revert "driver: uart: npcx: add missing tx/rx interrupt enabled checks"
This reverts commit 271b306.

In rare conditions, this commit causes the uart shell mechanism to
corrupt on Cros ec system. Revert this commit on upstream repo first to
avoid blocking the development. Will dig out why this symptom occurs
later.

Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
2023-01-18 16:08:49 +01:00