Fix missing last period when running samples/drivers/pwm/event. The last
period was incomplete because it is stopped immediately before the new
period became effective.
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
Fix misaligned break statements in pwm_xec_pm_action() switch-case
block to match the case indentation level.
Signed-off-by: Srinivas Edireswarapu <srinivas.edireswarapu@microchip.com>
Refactor the Microchip XEC PWM driver to use DTS-encoded PCR
property via soc_xec_pcr_sleep_en_clear(), replacing per-SoC
ifdefs for PCR init. Move PCR enable before pinctrl apply in
the init sequence.
Signed-off-by: Srinivas Edireswarapu <srinivas.edireswarapu@microchip.com>
If first PWM sequence is set to 100% glitch free duty
cycle, period_cycles will remain uninitialized while
all used channels will use PWM. If following
sequences request non-100% duty cycle, period
cycles will have to be changed. Improve error
condition to allow changing period cycles for
running PWM if these are equal to 0.
Signed-off-by: Michał Stasiak <michal.stasiak@nordicsemi.no>
When the following conditions are met:
- center aligned mode
- trigger generation on update event
an additional update event is avoided during channel activation.
This may cause (depending on the up/down counting direction) a
de-synchronisation between pwm polarity and generated trigger.
Problematic when e.g. the adc should trigger during high- and
low phase of a pwm signal.
Signed-off-by: Matthias Plöger <matthias.ploeger@phoenixcontact.com>
Add PWM driver support for Realtek Bee series SoCs,
including RTL87x2G and RTL8752H.
This driver supports:
- Pulse width modulation output
- Period and pulse width configuration
- Polarity inversion
Signed-off-by: Yuzhuo Liu <yuzhuo_liu@realsil.com.cn>
Add a generic software PWM driver as a fallback
when no dedicated hardware PWM pins are available.
This implementation leverages a single hardware
timer interrupt as a time base to derive an
arbitrary number of software-controlled PWM channels.
The period is the same for all channels.
This enables use of LED brightness and blink APIs.
Tested on Nucleo H563ZI with this overlay:
/ {
status_leds: status_leds {
compatible = "pwm-leds";
status_led_1: status_led_1 {
pwms = <&soft_pwm 0 PWM_MSEC(10) PWM_POLARITY_NORMAL>;
label = "1";
};
};
soft_pwm: soft_pwm {
compatible = "zephyr,pwm-bitbang";
#pwm-cells = <3>;
timer = <&tim6_counter>;
pwm-gpios = <&gpiob 0 GPIO_ACTIVE_HIGH>;
};
};
&timers6 {
status = "okay";
st,prescaler = <24999>;
tim6_counter: counter {
status = "okay";
};
};
Assisted-by: GitHub Copilot:claude-opus-4.6
Signed-off-by: Stefan Gloor <stefan.gloor@siemens.com>
This reverts commit 311a841620.
+ related changes done in 841e4d4597
Proposed API change result in vendor specific details of the DMA leaking
into application code, which prevents usage with portable code.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
Adds implementation of the PWM_EVENT api options. The Infineon TCPWM
Module supports the PWM_EVENT_TYPE_COMPARE_CAPTURE and
PWM_EVENT_TYPE_PERIOD events.
Assisted-by: GitHub Copilot:claude-opus-4.6
Signed-off-by: John Batch <john.batch@infineon.com>
Extend the ESP32 LEDC PWM driver to support ESP32-C5. Clear the
gamma RAM fade function on SoCs that have it to prevent stale
fade parameters from affecting duty cycle output.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
The ESP32 MCPWM driver does not initialize the pinctrl configuration if
only the capture units of MCPWM are used and no other MCPWM outputs are
used. This leads to pwm capture requests timing out. Fix this by applying
the pinctrl configuration during module initialization.
Signed-off-by: Christopher Smith <christophersmith107@gmail.com>
Refactor the PWM capture interrupt handler to properly support all
three capture channels (A, B, and X).
Clear capture FIFOs by reading CVAL registers during enable_capture
Signed-off-by: Felix Wang <fei.wang_3@nxp.com>
Add feature check to ensure these functions are only called when the
hardware supports input filter capture registers.
Update device tree binding documentation to clarify that the
input-filter-count and input-filter-period properties only take
effect when the capture input filter register is available.
Signed-off-by: Felix Wang <fei.wang_3@nxp.com>
Apply PINCTRL_STATE_SLEEP on suspend and PINCTRL_STATE_DEFAULT
on resume. If a sleep pinctrl state is defined in the board DTS,
pins will be reconfigured on suspend. If not defined, the call
is a no-op.
Signed-off-by: Jacob Wienecke <jacob.wienecke@nxp.com>
Implements PWM driver support for the MAX22216/MAX22217 device.
This driver integrates with the Zephyr PWM API and uses the parent
MFD device to perform register access.
Signed-off-by: Cherrence Sarip <cherrence.sarip@analog.com>
Max32 PWM already has built-in support for interrupts at the end of
each PWM period so added baseline support for the PERIOD event type
in CONFIG_PWM_EVENT. Updated PWM Event sample to support
Max32672EvKit.
Signed-off-by: Ryan Wiebe <ryan.wiebe@analog.com>
Adapt all Espressif SoC and driver code to the updated
hal_espressif module synced with IDF master branch.
Main changes:
- clock control: delegate peripheral clock gating to HAL
layer using new clock/reset APIs
- SPI/GDMA: adapt to restructured DMA HAL with new channel
allocation and configuration interfaces
- ethernet: add RMII clock configuration and PHY management
- GPIO: simplify using direct HAL function calls
- flash: adapt to updated SPI flash HAL interfaces
- linker scripts: update IRAM/DRAM mappings for new HAL
object files
- DTS: fix ESP32-S2 PSRAM dcache1 address to match actual
MMU mapping region (0x3f800000 DRAM1 instead of 0x3f500000
DPORT which lacks 8-bit access capability)
- west.yml: update hal_espressif revision
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Extend the PWM API with optional API functions for enabling DMA requests
Possible solution for #88670
Signed-off-by: Vincent Surkijn <vincent.surkijn@siemens.com>
Correct an #if which otherwise is always true, so we do not
refer to a function which does not exist otherwise.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Add PWM driver for the Infineon PSoC4 family.
This includes SoC-specific register configurations, API calls,
and hardware instance mapping required for PSoC4 compatibility.
Signed-off-by: Surya Prakash T <suryat@aerlync.com>
Signed-off-by: Manojkumar Konisetty <manoj@aerlync.com>
Signed-off-by: Sayooj K Karun <sayooj@aerlync.com>
If the clock device (i.e., RCC) failed to initialize, we have bigger
problems than trying to call clock_control_{off,on,configure} on it.
Don't bother checking to save some footprint.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
1.Extend the NXP MCUX PWM driver to support three channels (A, B, and X)
instead of two.
2.Add special handling for channel X polarity control via the OCTRL
register, as it uses VAL0 for pulse width instead of the VAL2/VAL3 pair
used by channels A and B.
3.Restore VAL0 when configuring channels A/B to preserve channel X pulse
4.Adjust LDOK timeout to one PWM period
5.Get clock frequency in init function
Signed-off-by: Felix Wang <fei.wang_3@nxp.com>
As per Zephyr coding guideline #59, "operands shall not be of an
inappropriate essential type". This makes sure boolean variables are
assigned true/false values, not 1/0.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Add explicit clock configuration and enable calls during driver
initialization.
Note: -ENOSYS is temporarily ignored as not all clock control
drivers currently implement the configure API. This handling
should be removed once all clock drivers support configure.
Signed-off-by: Albort Xue <yao.xue@nxp.com>
Initialize p_reg with the register base address from devicetree.
Signed-off-by: Hoang Nguyen <hoang.nguyen.jx@bp.renesas.com>
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
pwm_mcux_sctimer driver doesn't support power management actions.
PM Actions added, as well support to save/restore for pwm channels
configurations after exitig from PM3.
Signed-off-by: Missael Maciel <davidmissael.maciel@nxp.com>
Fixes the Kconfig name of this so that it matches the value from
soc.yml, and deprecates the old name - this is required to support
future build system features. Additionally, it fixes an issue in
Kconfigs of this SoC of duplicating existing symbols
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
The settings and calculations are often done in micro or nano seconds
and the result is not always shown. So, just add the period cycles as
part of the error message to get the calculated value.
Signed-off-by: Charles Hardin <ckhardin@gmail.com>
Add support for center-aligned PWM mode in addition to the existing
edge-aligned mode. When center-aligned mode is configured, adjust
pulse and period cycles by dividing by 2 to maintain correct timing.
Add validation checks in PWM capture functionality to edge-aligned
mode only, as capture is not supported in center-aligned mode.
Assign the value directly to avoid re-calculating period_cycles
based on pwm_freq in TPM_SetupPwm, which could lead to precision loss.
Signed-off-by: Felix Wang <fei.wang_3@nxp.com>
Replace interrupt register checks with explicit capture_active flag
to track capture state. This provides more reliable state management
and fixes potential race conditions when checking if capture is active.
Also optimize TPM_SetupPwm call to only configure the specific channel
being set instead of all channels, improving efficiency.
Signed-off-by: Felix Wang <fei.wang_3@nxp.com>
Updates the Infineon Counter and PWM drivers based on the TCPWM device
to connect with a clock. This update allows multiple devices to connect
to the same peripheral clock, and supports the TCPWM architecture of the
PSC3 device family.
Corrects initialization of the PWM on the PSC3 family to select the
correct output type.
Signed-off-by: John Batch <john.batch@infineon.com>
Add clock_control_configure() call during initialization to properly
configure the TPM clock. The driver now attempts to configure the
clock and handles cases where configuration is not supported by the
platform (-ENOTSUP/-ENOSYS) by continuing with default settings.
Real configuration errors are logged and cause initialization to fail.
Note: -ENOSYS is temporarily ignored as not all clock control
drivers currently implement the configure API. This handling
should be removed once all clock drivers support configure.
Signed-off-by: Albort Xue <yao.xue@nxp.com>
Fix formatting of the __ASSERT message in
mcux_ctimer_pwm_get_cycles_per_sec to properly concatenate the
string across multiple lines.
Signed-off-by: Felix Wang <fei.wang_3@nxp.com>
Implement interrupt settings to expand the driver to RZ/V2H, V2N SoCs
Signed-off-by: Hieu Nguyen <hieu.nguyen.ym@bp.renesas.com>
Signed-off-by: Tien Nguyen <tien.nguyen.zg@renesas.com>
Implement PWM input capture functionality for the NXP SCTimer
driver with support for both pulse width and period measurement
in single-shot and continuous modes.
Signed-off-by: Felix Wang <fei.wang_3@nxp.com>
1.Add mcux_sctimer_pwm_update_polarity() function to properly
reconfigure PWM output polarity when duty cycle is updated.
2.Update Match Reload Value register when Match register is
set.
3.Stop timer before update to prevent bus error
Signed-off-by: Felix Wang <fei.wang_3@nxp.com>
The prescaler divides the clock by (prescaler + 1), not by the prescaler
value directly. Update the calculation to correctly account for this.
Signed-off-by: Felix Wang <fei.wang_3@nxp.com>
Add support for PWM input capture functionality to the NXP MCUX PWM
driver. This enables measurement of pulse width and period of external
PWM signals.
Key features added:
- PWM capture configuration and control APIs
- Interrupt-driven capture with overflow handling
- Support for both pulse width and period measurement
- Configurable input filtering
- Support for continuous and one-shot capture modes
The implementation uses FlexPWM channel X as the dedicated input
capture channel, while channels 0 and 1 remain available for PWM
output. Capture functionality is conditionally compiled based on
CONFIG_PWM_CAPTURE configuration option.
Signed-off-by: Felix Wang <fei.wang_3@nxp.com>
