This change makes improvements and bug fixes for the Infineon PWM
driver. These include:
* Removes hard coded register addresss from driver.
* Addresses issues causing pwm_api and pwm_gpio_loopback tests to
fail, as well as functional failures.
* Restructures device tree file to better represent the hardware
architecture of the tcpwm module.
* Allows configuration of hardware behavior when PWM is disabled.
Signed-off-by: Bill Waters <bill.waters@infineon.com>
* Changes driver naming to reflect hardware IP being used (TCPWM)
instead of referencing cat1. Cat1 is an internal infineon
reference which has little meaning to users and is being phased
phased out.
Signed-off-by: Bill Waters <bill.waters@infineon.com>
This commit fixes the bug in the prescaler configuration formula.
Prescaler enumarations values are not consecutive numbers, so this
formula does not work correctly. This commit adds prescaler enums into
an array and sets PWM prescaler from this array with using
prescaler_index parameter.
Signed-off-by: Furkan Akkiz <hasanfurkan.akkiz@analog.com>
Duty value in the driver is calculated from timer cycles, which
can introduce precision loss when converting from pwm_set() to
pwm_set_cycles(). To avoid truncating values with a fractional
part ≥ 0.5 and further drifting the effective duty, round the
computed duty to the nearest integer.
Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
RP2350 adds four more PWM slices from the eight available on RP2040,
which are only broken out to package pins on RP2350B. This change fixes
the driver to support the correct number of slices on RP2350.
Tested by confirming that PWM can correctly be configured on GPIO 44 of
RP2350B.
Signed-off-by: Peter Marheine <peter@taricorp.net>
Now that the timer kernel clocks are defined in device tree, use the
clock get API to fetch the clock frequency instead of calculating the
value in the driver.
Removes the now unused function get_tim_clk.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Add PWM driver support for Renesas RZ/A3UL
Signed-off-by: Hieu Nguyen <hieu.nguyen.ym@bp.renesas.com>
Signed-off-by: Tien Nguyen <tien.nguyen.zg@renesas.com>
The p_context no longer has the const type, so all
Renesas-supported drivers need to be updated accordingly.
Signed-off-by: Khoa Nguyen <khoa.nguyen.xh@renesas.com>
Updated the nxp flexio pwm driver to account
for when the duty cycle is 100% or 0%.
We switch off the counter of the flexio and
manually set the GPIO High or Low. Otherwise
Flexio Peripheral with default to a 50% duty
cycle behavior.
Factored out timerOutput variable.
Signed-off-by: Emilio Benavente <emilio.benavente@nxp.com>
Depending on clock config init, some devices might be initialized
with RC_FAST clock enabled but not calibrated. Logic to detect if
clock is calibrated was fixed for this reason. Also, logic to set
RC_FAST and REF_TICK for devices with timer specific clocks (ESP32
and ESP32-S2) was also fixed.
Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
Transition nrf54h away from the soc specific gpd
(global power domain) driver which mixed power domains, pinctrl
and gpio pin retention into a non scalable solution, forcing soc
specific logic to bleed into nrf drivers.
The new solution uses zephyrs PM_DEVICE based power domains to
properly model the hardware layout of device and pin power domains,
and moves pin retention logic out of drivers into pinctrl and
gpio, which are the components which manage pins (pads).
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Add build asserts for "memory-regions" property in nrf drivers which is
required on targets with DMM for saadc, pdm, pwm, twim, twim_rtio, twis,
tdm, uarte, spim and spis. On targets where the property is not required
the assertion macro expands to nothing.
Signed-off-by: Michał Bainczyk <michal.bainczyk@nordicsemi.no>
TI MSPM0 timer module has capture block used to capture timings of input
signal. Add a support for TI MSPM0 PWM capture.
Signed-off-by: Saravanan Sekar <saravanan@linumiz.com>
Restructured counter and timer.
CTimer/Timer is now parent to pwm and counter.
Created PWM driver and tied to pwm and pwm-led
Signed-off-by: Richard Wheatley <richard.wheatley@ambiq.com>
With the four-channel-capture-support property enabled, the STM32 PWM
driver was missing every other frames during PWM capture.
The counter values are now reset just after getting the pulse and the
period of the cycle, instead of waiting the next interrupt to do so, and
thus missing a cycle.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
The clock tree of the STM32H7RS series uses the ppre1
and ppre2 naming convention instead of apb1_prescaler
and apb2_prescaler for bus prescaler.
Signed-off-by: Fabrice DJIATSA <fabrice.djiatsa-ext@st.com>
TI MSPM0 SoC series has General Purpose Timer and Advanced control timers
with Compare block which is used to generate time expiry and output
waveform like PWM. Add driver support for MSPM0 PWM output.
Signed-off-by: Saravanan Sekar <saravanan@linumiz.com>
Add PWM driver for the Timer peripheral on Series 2.
The TIMER uses the high-frequency EM01 Group A clock, and has
a 16- or 32-bit counter. It supports PWM period and pulse capture
on channel 0, and PWM output on all channels.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Add PWM driver for the Low Energy Timer peripheral on Series 2.
The LETIMER runs at up to 32 kHz and has a 24-bit counter. It
only supports PWM output, it does not support input capture.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Currently there is a mismatch between the naming of the hardware and
the drivers targetting the hardware. nrf2_ is used instead of
the actual bindings names, like nrf2_audiopll instead of
nrfs_audiopll. This makes it hard to map drivers to the hardware
they are targetting.
There is historical reason for some of this, namely the same binding
name was used for different hardware, which is why nrf2_ was used
on newer platforms. This is no longer the case though, so drivers
and configs can be named according to the hardware without conflict.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
IDLEOUT presence in PWM means that there are 3 sources from which
PWM pin can be driven:
- GPIO setting when PWM peripheral is disabled.
- IDLEOUT setting when PWM is enabled.
- PWM Sequence when it is in use.
IDLEOUT setting cannot be changed after enabling PWM so it is
configured to the initial state of the pin. It means that if duty
cycle is 100%, GPIO output is set to 1 but initial pin state was 0
(IDLEOUT setting) there will be a glitch between disabling a PWM
sequence and disabling a PWM peripheral.
By default, PWM driver tries to disable PWM peripheral if all channels
are 0% or 100% duty cycle to safe power. When IDLEOUT feature is
present there will be a short glitch on channels with 100% duty cycle.
In order to avoid that CONFIG_PWM_NRFX_NO_GLITCH_DUTY_100 option is
added (enabled by default). When option is enabled 100% duty cycle
is achieved by PWM sequence and not by driving a GPIO pin. It will
consume more power in cases where all channels are 0% or 100% with
at least one channel set to 100% duty cycle.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
The period is the reload register plus 1. Adjust. Note that the
earlier code handles the cases where the pulse time is zero or equal
to the period.
Signed-off-by: Michael Hope <michaelh@juju.nz>
RC_FAST needs to be enabled and calibrated in order to be used
as clock source. Otherwise, clock source is selected but no
PWM is generated.
Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
Add a workaround for NRF52 anomaly 78: "High current consumption when
using timer STOP task only. Use the SHUTDOWN task instead."
Signed-off-by: Sven Depoorter <svndepoorter@gmail.com>
eMios_Icu_Ip_IndexInChState is changed to
eMios_Icu_Ip_u8IndexInChState and EMIOS_ICU_BUS_F
is removed in RTD 2.0.1
Signed-off-by: Tu Nguyen Van <tu.nguyenvan@nxp.com>
Change PWM to use buffers registers instead of writing period
and compare directly. This addressses an issue when updating
period to a value less than current counter, as demonstrated
in the blinky_pwm sample running on the CYW920829M2EVK_02
board.
Signed-off-by: John Batch <john.batch@infineon.com>
The GPTM is a general purpose module with a 16 bit prescaler, 16 bit
counter, and 4 compare units that can be used for PWM generation.
Use the same style as gd32 where the timer is a counter and the PWM
mode is a child node.
Signed-off-by: Michael Hope <michaelh@juju.nz>
