Combine mode is not for all TPM IP depneds
on IP version, which is necessary for PWM capture feature.
Add pre-process check and wrap
mcux_tpm_capture_data with CONFIG_PWM_CAPTURE macro.
Signed-off-by: Felix Wang <fei.wang_3@nxp.com>
Usage of stm32xxxx_ll_tim.c has been removed so we can also remove the
selection of USE_STM32_LL_TIM from the Kconfig.
Also remove the LL_RCC that plays no part in the driver.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Invert property was not implemented and is now redundant with the flag
pwm-cell which is more flexible in case you want some IO to be inverted
and some not
Signed-off-by: Franck Duriez <franck.lucien.duriez@gmail.com>
# Conflicts:
# doc/releases/migration-guide-4.3.rst
Because the PWM module mixes byte and word register together, the driver
adds an assertion check by writing a pattern to the 2-byte register
`PRSC`, reading it back, and performing a comparison. However,
the `PRSC` register cannot be written when the bit 7 (the PWR bit) in
register `PMWCTLn` is set to 1. This commit moves the assertion check to
a proper place to ensure the write is valid.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
If two pwm_set_pulse_dt calls are put consecutive to each other,
the period has already been configured and they refer to the same module
but different submodule (PWM A & B), the second call fails.
LDOK with ReloadImmediate should result in immediate change of the
buffered registers, but it doesn't seem like that's the case.
To fix this, we busywait on LDOK clearance before setting new pulse values.
Fixeszephyrproject-rtos/zephyr#95653
Signed-off-by: Alejandro Perea <alejandro.perea@classified-cycling.cc>
Align the definition of the complementary channels to the normal channels.
That way, it is consistent for all arrays, we use channel-1 as index, and
no other operation is necessary.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
This change reduces the level of pointer indirection, which minimizes
repeated dereferencing and helps reduce the overall code size, in the same
way as commit 48e326a5520ec884f38f6a7ac4e88c59a01ceb95 for UART.
This also fixes the type complimentary -> complementary.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Remove the calls to LL_TIM_xx_StructInit and LL_TIM_xx_Init in the PWM
driver. This avoids calling functions from stm32xxxx_ll_tim.c.
They are replaced by a set of simpler functions from the header file.
OC Init in particular is much simpler now. The init structure needed to be
filled out with the complementary channel (if it existed), even though its
configuration didn't change.
The new init is much more direct and only touches what needs to be
modified.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
On MMU-based systems, the address space of the IP needs to be mapped
before it can be used, otherwise the system will fault. Furthermore,
since the HAL driver uses the base address of the IP to perform various
operations (e.g. clock ungating), the map between the physical and
virtual addresses needs to be 1:1.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
This change makes improvements and bug fixes for the Infineon PWM
driver. These include:
* Removes hard coded register addresss from driver.
* Addresses issues causing pwm_api and pwm_gpio_loopback tests to
fail, as well as functional failures.
* Restructures device tree file to better represent the hardware
architecture of the tcpwm module.
* Allows configuration of hardware behavior when PWM is disabled.
Signed-off-by: Bill Waters <bill.waters@infineon.com>
* Changes driver naming to reflect hardware IP being used (TCPWM)
instead of referencing cat1. Cat1 is an internal infineon
reference which has little meaning to users and is being phased
phased out.
Signed-off-by: Bill Waters <bill.waters@infineon.com>
This commit fixes the bug in the prescaler configuration formula.
Prescaler enumarations values are not consecutive numbers, so this
formula does not work correctly. This commit adds prescaler enums into
an array and sets PWM prescaler from this array with using
prescaler_index parameter.
Signed-off-by: Furkan Akkiz <hasanfurkan.akkiz@analog.com>
Duty value in the driver is calculated from timer cycles, which
can introduce precision loss when converting from pwm_set() to
pwm_set_cycles(). To avoid truncating values with a fractional
part ≥ 0.5 and further drifting the effective duty, round the
computed duty to the nearest integer.
Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
RP2350 adds four more PWM slices from the eight available on RP2040,
which are only broken out to package pins on RP2350B. This change fixes
the driver to support the correct number of slices on RP2350.
Tested by confirming that PWM can correctly be configured on GPIO 44 of
RP2350B.
Signed-off-by: Peter Marheine <peter@taricorp.net>
Now that the timer kernel clocks are defined in device tree, use the
clock get API to fetch the clock frequency instead of calculating the
value in the driver.
Removes the now unused function get_tim_clk.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Add PWM driver support for Renesas RZ/A3UL
Signed-off-by: Hieu Nguyen <hieu.nguyen.ym@bp.renesas.com>
Signed-off-by: Tien Nguyen <tien.nguyen.zg@renesas.com>
The p_context no longer has the const type, so all
Renesas-supported drivers need to be updated accordingly.
Signed-off-by: Khoa Nguyen <khoa.nguyen.xh@renesas.com>
Updated the nxp flexio pwm driver to account
for when the duty cycle is 100% or 0%.
We switch off the counter of the flexio and
manually set the GPIO High or Low. Otherwise
Flexio Peripheral with default to a 50% duty
cycle behavior.
Factored out timerOutput variable.
Signed-off-by: Emilio Benavente <emilio.benavente@nxp.com>
Depending on clock config init, some devices might be initialized
with RC_FAST clock enabled but not calibrated. Logic to detect if
clock is calibrated was fixed for this reason. Also, logic to set
RC_FAST and REF_TICK for devices with timer specific clocks (ESP32
and ESP32-S2) was also fixed.
Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
Transition nrf54h away from the soc specific gpd
(global power domain) driver which mixed power domains, pinctrl
and gpio pin retention into a non scalable solution, forcing soc
specific logic to bleed into nrf drivers.
The new solution uses zephyrs PM_DEVICE based power domains to
properly model the hardware layout of device and pin power domains,
and moves pin retention logic out of drivers into pinctrl and
gpio, which are the components which manage pins (pads).
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Add build asserts for "memory-regions" property in nrf drivers which is
required on targets with DMM for saadc, pdm, pwm, twim, twim_rtio, twis,
tdm, uarte, spim and spis. On targets where the property is not required
the assertion macro expands to nothing.
Signed-off-by: Michał Bainczyk <michal.bainczyk@nordicsemi.no>
TI MSPM0 timer module has capture block used to capture timings of input
signal. Add a support for TI MSPM0 PWM capture.
Signed-off-by: Saravanan Sekar <saravanan@linumiz.com>
Restructured counter and timer.
CTimer/Timer is now parent to pwm and counter.
Created PWM driver and tied to pwm and pwm-led
Signed-off-by: Richard Wheatley <richard.wheatley@ambiq.com>
With the four-channel-capture-support property enabled, the STM32 PWM
driver was missing every other frames during PWM capture.
The counter values are now reset just after getting the pulse and the
period of the cycle, instead of waiting the next interrupt to do so, and
thus missing a cycle.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
The clock tree of the STM32H7RS series uses the ppre1
and ppre2 naming convention instead of apb1_prescaler
and apb2_prescaler for bus prescaler.
Signed-off-by: Fabrice DJIATSA <fabrice.djiatsa-ext@st.com>
TI MSPM0 SoC series has General Purpose Timer and Advanced control timers
with Compare block which is used to generate time expiry and output
waveform like PWM. Add driver support for MSPM0 PWM output.
Signed-off-by: Saravanan Sekar <saravanan@linumiz.com>
Add PWM driver for the Timer peripheral on Series 2.
The TIMER uses the high-frequency EM01 Group A clock, and has
a 16- or 32-bit counter. It supports PWM period and pulse capture
on channel 0, and PWM output on all channels.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Add PWM driver for the Low Energy Timer peripheral on Series 2.
The LETIMER runs at up to 32 kHz and has a 24-bit counter. It
only supports PWM output, it does not support input capture.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Currently there is a mismatch between the naming of the hardware and
the drivers targetting the hardware. nrf2_ is used instead of
the actual bindings names, like nrf2_audiopll instead of
nrfs_audiopll. This makes it hard to map drivers to the hardware
they are targetting.
There is historical reason for some of this, namely the same binding
name was used for different hardware, which is why nrf2_ was used
on newer platforms. This is no longer the case though, so drivers
and configs can be named according to the hardware without conflict.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
