1.Extend the NXP MCUX PWM driver to support three channels (A, B, and X)
instead of two.
2.Add special handling for channel X polarity control via the OCTRL
register, as it uses VAL0 for pulse width instead of the VAL2/VAL3 pair
used by channels A and B.
3.Restore VAL0 when configuring channels A/B to preserve channel X pulse
4.Adjust LDOK timeout to one PWM period
5.Get clock frequency in init function
Signed-off-by: Felix Wang <fei.wang_3@nxp.com>
As per Zephyr coding guideline #59, "operands shall not be of an
inappropriate essential type". This makes sure boolean variables are
assigned true/false values, not 1/0.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Add explicit clock configuration and enable calls during driver
initialization.
Note: -ENOSYS is temporarily ignored as not all clock control
drivers currently implement the configure API. This handling
should be removed once all clock drivers support configure.
Signed-off-by: Albort Xue <yao.xue@nxp.com>
Initialize p_reg with the register base address from devicetree.
Signed-off-by: Hoang Nguyen <hoang.nguyen.jx@bp.renesas.com>
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
pwm_mcux_sctimer driver doesn't support power management actions.
PM Actions added, as well support to save/restore for pwm channels
configurations after exitig from PM3.
Signed-off-by: Missael Maciel <davidmissael.maciel@nxp.com>
Fixes the Kconfig name of this so that it matches the value from
soc.yml, and deprecates the old name - this is required to support
future build system features. Additionally, it fixes an issue in
Kconfigs of this SoC of duplicating existing symbols
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
The settings and calculations are often done in micro or nano seconds
and the result is not always shown. So, just add the period cycles as
part of the error message to get the calculated value.
Signed-off-by: Charles Hardin <ckhardin@gmail.com>
Add support for center-aligned PWM mode in addition to the existing
edge-aligned mode. When center-aligned mode is configured, adjust
pulse and period cycles by dividing by 2 to maintain correct timing.
Add validation checks in PWM capture functionality to edge-aligned
mode only, as capture is not supported in center-aligned mode.
Assign the value directly to avoid re-calculating period_cycles
based on pwm_freq in TPM_SetupPwm, which could lead to precision loss.
Signed-off-by: Felix Wang <fei.wang_3@nxp.com>
Replace interrupt register checks with explicit capture_active flag
to track capture state. This provides more reliable state management
and fixes potential race conditions when checking if capture is active.
Also optimize TPM_SetupPwm call to only configure the specific channel
being set instead of all channels, improving efficiency.
Signed-off-by: Felix Wang <fei.wang_3@nxp.com>
Updates the Infineon Counter and PWM drivers based on the TCPWM device
to connect with a clock. This update allows multiple devices to connect
to the same peripheral clock, and supports the TCPWM architecture of the
PSC3 device family.
Corrects initialization of the PWM on the PSC3 family to select the
correct output type.
Signed-off-by: John Batch <john.batch@infineon.com>
Add clock_control_configure() call during initialization to properly
configure the TPM clock. The driver now attempts to configure the
clock and handles cases where configuration is not supported by the
platform (-ENOTSUP/-ENOSYS) by continuing with default settings.
Real configuration errors are logged and cause initialization to fail.
Note: -ENOSYS is temporarily ignored as not all clock control
drivers currently implement the configure API. This handling
should be removed once all clock drivers support configure.
Signed-off-by: Albort Xue <yao.xue@nxp.com>
Fix formatting of the __ASSERT message in
mcux_ctimer_pwm_get_cycles_per_sec to properly concatenate the
string across multiple lines.
Signed-off-by: Felix Wang <fei.wang_3@nxp.com>
Implement interrupt settings to expand the driver to RZ/V2H, V2N SoCs
Signed-off-by: Hieu Nguyen <hieu.nguyen.ym@bp.renesas.com>
Signed-off-by: Tien Nguyen <tien.nguyen.zg@renesas.com>
Implement PWM input capture functionality for the NXP SCTimer
driver with support for both pulse width and period measurement
in single-shot and continuous modes.
Signed-off-by: Felix Wang <fei.wang_3@nxp.com>
1.Add mcux_sctimer_pwm_update_polarity() function to properly
reconfigure PWM output polarity when duty cycle is updated.
2.Update Match Reload Value register when Match register is
set.
3.Stop timer before update to prevent bus error
Signed-off-by: Felix Wang <fei.wang_3@nxp.com>
The prescaler divides the clock by (prescaler + 1), not by the prescaler
value directly. Update the calculation to correctly account for this.
Signed-off-by: Felix Wang <fei.wang_3@nxp.com>
Add support for PWM input capture functionality to the NXP MCUX PWM
driver. This enables measurement of pulse width and period of external
PWM signals.
Key features added:
- PWM capture configuration and control APIs
- Interrupt-driven capture with overflow handling
- Support for both pulse width and period measurement
- Configurable input filtering
- Support for continuous and one-shot capture modes
The implementation uses FlexPWM channel X as the dedicated input
capture channel, while channels 0 and 1 remain available for PWM
output. Capture functionality is conditionally compiled based on
CONFIG_PWM_CAPTURE configuration option.
Signed-off-by: Felix Wang <fei.wang_3@nxp.com>
In PWM_SetupPwm implementation, there is a check:
temp = pwmClock / pwmFreq_Hz;
assert(temp <= 0xFFFFU);
Currently pwmFreq_Hz is 1, makes assert failed with
high frequency pwmClock. Since VALx values is set
directly for edge aligned PWM, the pwmFreq_Hz here is
a dummy value, set pwmFreq_Hz equal to pwmClock
frequency to pass assert check.
Signed-off-by: Felix Wang <fei.wang_3@nxp.com>
Add PWM shell command for getting the number of cycles per second for a
given PWM controller/channel.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Add PWM driver support for Renesas RZ/A2M
Signed-off-by: Hieu Nguyen <hieu.nguyen.ym@bp.renesas.com>
Signed-off-by: Tien Nguyen <tien.nguyen.zg@renesas.com>
PWM driver clears its runtime state on each suspend event.
However, since nrfx 4.0 integration nrfx driver instance is part
of the runtime state structure, so clear action must be limited.
Signed-off-by: Nikodem Kastelik <nikodem.kastelik@nordicsemi.no>
- Update the driver to support the kit_pse84_eval board
- Update to new peripheral clock allocation scheme
Signed-off-by: McAtee Maxwell <maxwell.mcatee@infineon.com>
Add pwm driver using tc g1 peripheral.
Adds the support for generating pwm output.
Supports 8-bit, 16-bit and 32-bit mode of tc peripheral
Signed-off-by: Muhammed Asif <muhammed.asif@microchip.com>
When EC reboot, pwm pins go back to default GPI mode.
After we set pin mode to pwm mode at init(), it would
output low, so LED will be light (LED is low-activated).
And until set_cycles() is called to set output high,
then LED will be turn off the light (PWM-LED flicker).
So add the property to set PWM channel init output level.
Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Setting a prescaler of 256 would overflow the uint8_t.
Also get cycles calculation was wrong.
Signed-off-by: Peter van der Perk <peter.vanderperk@nxp.com>
For stm32h7 the order matters to get the pwm to output the values as
expected. As reported for the the H730 doesn't produce PWM output when
the LL_TIM_OC_SetDeadTime is called after LL_TIM_EnableAllOutputs. So,
switch the order of the calls and this doesn't impact the stm32f413zh
boards.
Signed-off-by: Charles Hardin <ckhardin@gmail.com>
The SAM4S pwm supports several events. This commit
implements the events when a channel period has ended
or a fault event has occured.
Signed-off-by: Jaro Van Landschoot <jaro.vanlandschoot@basalte.be>
Extend the PWM API to support events, as some
controllers allow interrupts if e.g., a pwm period
has ended or a fault occured.
Signed-off-by: Jaro Van Landschoot <jaro.vanlandschoot@basalte.be>
Enable clock control by default for siwx91x SoCs. Moreover, most
drivers for siwx91x soc depend on clock control, but didn't declare
it.
Signed-off-by: Martin Hoff <martin.hoff@silabs.com>
Most drivers for Series 2 depend on clock control, but didn't
declare it. Enable clock control by default for Series 2 SoCs.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
New nrfx release contains major rework of nrfx drivers
instantiation making it easier to integrate with dts nodes.
Now, nrfx driver instances can no longer be `const`
because they contain driver runtime state.
Additionally, all nrfx drivers return `errno` error codes
instead of deprecated `nrfx_err_t`.
Signed-off-by: Nikodem Kastelik <nikodem.kastelik@nordicsemi.no>
Clean indentation in IRQ_CONNECT_AND_ENABLE_BY_NAME(), IRQ_CONFIG_FUNC()
and IRQ_CONNECT_AND_ENABLE_DEFAULT() macros of STM32 PWM driver.
Remove a useless trailing semi column character in the interrupt function
defined with IRQ_CONFIG_FUNC() macro.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
When using an stm32 in a bridge circuit with complementary outputs,
the deadtime needs to be configurable to avoid shoot-thru current
on the circuit. So, the HAL has the configuration in the BDTR init
and use that api access to set the configuration.
Signed-off-by: Charles Hardin <ckhardin@gmail.com>
Use the "zephyr-keep-sorted-start/stop" comment to have CI check
the alphabetical order of includes, to help reducing the chance
of conflicts while contributing drivers.
Signed-off-by: Josuah Demangeon <me@josuah.net>
This fix addresses the issue encountered when power management (pm)
is enabled, as the PWM test suites utilize the GPIO driver, which
now incorporates the latest power domain enhancements and requires
CONFIG_POWER_DOMAIN to be enabled. Power domain functionality
manages device power actions such as turning on and off.
Accordingly, the pm device support for the pwm_silabs_siwx91x
driver has been updated to align with the recent power domain
improvements.
Signed-off-by: S Mohamed Fiaz <Fiaz.Mohamed@silabs.com>
Clocks are requested automatically by hardware on the nRF54H.
Remove additional handling from device drivers, and disable
the now unmanaged clocks in the devicetree.
Updates:
- can_nrf
- counter_nrfx_timer
- uart_nrfx_uarte
- spi_nrfx_spim
- spi_nrfx_spis
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
The mcux_qtmr_pwm_set_cycles can not set 100% and 0%
duty cycle PWM wave.
Set output compare setting based on pulse_cycles and
period_cycles:
1. If pulse_cycles is 0, generate 0% duty cycle wave.
2. If pulse_cycles equals period_cycles but not 0,
generate 100% duty cycle wave.
3. Otherwise toggle output when compare value matched.
Signed-off-by: Felix Wang <fei.wang_3@nxp.com>
Add pwm driver using tcc g1 peripheral.
Adds the support for generating pwm output.
Supports both 16-bit and 24bit mode of tcc peripheral
Signed-off-by: Muhammed Asif <muhammed.asif@microchip.com>
Redefine some macros due to different naming scheme in the header file.
Get the clock rate from the device tree when 'SOC_ATMEL_SAM_MCK_FREQ_HZ'
is not defined.
Signed-off-by: Tony Han <tony.han@microchip.com>
Replace the look-up table used to obtain the prescaler enumeration with
a simple multiplication.
Signed-off-by: Tahsin Mutlugun <Tahsin.Mutlugun@analog.com>
Combine mode is not for all TPM IP depneds
on IP version, which is necessary for PWM capture feature.
Add pre-process check and wrap
mcux_tpm_capture_data with CONFIG_PWM_CAPTURE macro.
Signed-off-by: Felix Wang <fei.wang_3@nxp.com>
