The comma was removed during the migration in commit ad1e5ac253. All
usages of this driver inside the Zephyr tree use only one channel,
which doesn't trigger the issue.
Signed-off-by: Marek Maškarinec <marek@mrms.cz>
The ADTM is a superset of the GPTM and has the same core register
layout. See section 11.2.2 of the CH32V003RM for details on the
differences.
Use the same technique as the GD32 driver, i.e. use the same basic
driver with tweaks based on the features.
Add the common 3x GTPM and 1x ADTM Devicetree and pinctrl entries for
the 20x and 30x series and the extra 1x GPTM for the CH32V208 used in
linkw. I can follow up with the other chips in a separate PR.
Tested on the ch32v006evt and linkw by running
`samples/basic/blinky_pwm` and `tests/drivers/pwm/pwm_api` and
checking the output with a logic analyser.
Signed-off-by: Michael Hope <michaelh@juju.nz>
The low-speed channel update latches the preceding register writes and
can stall for milliseconds if an interrupt preempts the sequence. Lock
interrupts around the start and stop sequences to keep them atomic.
Signed-off-by: Sylvio Alves <sylviojalves@gmail.com>
Some STM32 series (e.g. WB0) do not provide all LL_TIM_TS_ITRx macros,
causing build failures when the timer is configured in disabled slave
mode. Introduce PWM_SLAVE_TRIGGER() which conditionally expands to the
LL_TIM_TS_* token only when slave mode is actually enabled, and falls
back to 0 otherwise.
Signed-off-by: Fabrice DJIATSA <fabrice.djiatsa-ext@st.com>
- Only modify salve mode registers when not in 4-channel capture mode
- Add compile time check for not compatible configuration.
Capture support is only allowed if:
- No slave mode is selected
- or capture runs in four_channel_capture_support mode
Signed-off-by: Matthias Plöger <matthias.ploeger@phoenixcontact.com>
The PM_DEVICE_ACTION_RESUME handler started the SCT counter
unconditionally. When RESUME runs before the first pwm_set_cycles()
no period match or counter limit event exists yet, so the counter
free-runs across its full 32-bit range. By the time a channel is
configured, COUNT has climbed past the period match installed as the
counter limit; since the limit only fires on COUNT == match, the
counter never resets and the output is stranded until a full 32-bit
wrap. Guard the start with pwm_channel_active so the counter is only
started once at least one channel has been configured.
Signed-off-by: Jacob Wienecke <jacob.wienecke@nxp.com>
- Kconfigs in modules/ should not define configs with an SOC_ prefix.
Furthermore, these options are SDK specific, not SoC specific.
- The simplicity_sdk configs do the same.
Signed-off-by: Michael Zimmermann <michael.zimmermann@sevenlab.de>
Adopt the new HAL/LL interfaces: ADC_LL_* macros,
esp_clk_tree_* clock helpers, and rng_ll_* entropy reads
across the adc, i2c, pwm, mdio and entropy drivers.
Update the Radio blobs to latest version.
Update linkers to include new sleep cache calls.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
The NXP SCTimer's outInitState field defines the output levels applied at
initialization, before any PWM channel is configured. Needed for active
low loads to not flicker at startup
Signed-off-by: Johan Eklund <Johan@meck.se>
The capture-related code in the FlexPWM driver unconditionally
references kPWM_CaptureA*Flag / kPWM_CaptureB*Flag and CVAL2..CVAL5
registers, which do not exist on SoCs whose FlexPWM only supports input
capture on the X channel (for example MCXA153, where
FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELA/B are 0 and only CHANNELX is 1).
This caused a build failure as soon as CONFIG_PWM_CAPTURE was enabled
on such SoCs.
Signed-off-by: Felix Wang <fei.wang_3@nxp.com>
Implement the Zephyr PWM capture API using the CTIMER
capture-clears-timer feature.
One capture channel is configured to fire an IRQ on the active
edge while ENCC/SELCC clears TC+PC on the opposite (or same) edge so
that CR latches the period or pulse width directly with no software
subtraction. The INPUTMUX is configured at driver init from a new
inputmux-connections DT property that lists <captsel-index, connection>
pairs.
Signed-off-by: Felix Wang <fei.wang_3@nxp.com>
CTIMER PWM mode emits LOW for MR[pulse_channel] ticks then HIGH for the
remainder of the period, so PWM_POLARITY_NORMAL must map pulse_cycles to
(period - pulse_cycles), not pass it through unchanged.
Signed-off-by: Felix Wang <fei.wang_3@nxp.com>
Add sleep retention support for LEDC PWM driver. When peripheral
power down is enabled for light sleep, register data is lost,
so REGDMA backup is needed to mantein peripheral operational.
Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
LL_TIM_TRGO_UPDATE isn't yet implemented on STM32WB0x series.
Exclude WB0x series from using LL_TIM_TRGO_UPDATE.
This is addressed by testing HAS_MASTERMODE_SUPPORT that is disabled
for platforms not defining LL_TIM_TRGO_UPDATE.
Signed-off-by: Fabrice DJIATSA <fabrice.djiatsa-ext@st.com>
Fix missing last period when running samples/drivers/pwm/event. The last
period was incomplete because it is stopped immediately before the new
period became effective.
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
Fix misaligned break statements in pwm_xec_pm_action() switch-case
block to match the case indentation level.
Signed-off-by: Srinivas Edireswarapu <srinivas.edireswarapu@microchip.com>
Refactor the Microchip XEC PWM driver to use DTS-encoded PCR
property via soc_xec_pcr_sleep_en_clear(), replacing per-SoC
ifdefs for PCR init. Move PCR enable before pinctrl apply in
the init sequence.
Signed-off-by: Srinivas Edireswarapu <srinivas.edireswarapu@microchip.com>
If first PWM sequence is set to 100% glitch free duty
cycle, period_cycles will remain uninitialized while
all used channels will use PWM. If following
sequences request non-100% duty cycle, period
cycles will have to be changed. Improve error
condition to allow changing period cycles for
running PWM if these are equal to 0.
Signed-off-by: Michał Stasiak <michal.stasiak@nordicsemi.no>
When the following conditions are met:
- center aligned mode
- trigger generation on update event
an additional update event is avoided during channel activation.
This may cause (depending on the up/down counting direction) a
de-synchronisation between pwm polarity and generated trigger.
Problematic when e.g. the adc should trigger during high- and
low phase of a pwm signal.
Signed-off-by: Matthias Plöger <matthias.ploeger@phoenixcontact.com>
Add PWM driver support for Realtek Bee series SoCs,
including RTL87x2G and RTL8752H.
This driver supports:
- Pulse width modulation output
- Period and pulse width configuration
- Polarity inversion
Signed-off-by: Yuzhuo Liu <yuzhuo_liu@realsil.com.cn>
Add a generic software PWM driver as a fallback
when no dedicated hardware PWM pins are available.
This implementation leverages a single hardware
timer interrupt as a time base to derive an
arbitrary number of software-controlled PWM channels.
The period is the same for all channels.
This enables use of LED brightness and blink APIs.
Tested on Nucleo H563ZI with this overlay:
/ {
status_leds: status_leds {
compatible = "pwm-leds";
status_led_1: status_led_1 {
pwms = <&soft_pwm 0 PWM_MSEC(10) PWM_POLARITY_NORMAL>;
label = "1";
};
};
soft_pwm: soft_pwm {
compatible = "zephyr,pwm-bitbang";
#pwm-cells = <3>;
timer = <&tim6_counter>;
pwm-gpios = <&gpiob 0 GPIO_ACTIVE_HIGH>;
};
};
&timers6 {
status = "okay";
st,prescaler = <24999>;
tim6_counter: counter {
status = "okay";
};
};
Assisted-by: GitHub Copilot:claude-opus-4.6
Signed-off-by: Stefan Gloor <stefan.gloor@siemens.com>
This reverts commit 311a841620.
+ related changes done in 841e4d4597
Proposed API change result in vendor specific details of the DMA leaking
into application code, which prevents usage with portable code.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
Adds implementation of the PWM_EVENT api options. The Infineon TCPWM
Module supports the PWM_EVENT_TYPE_COMPARE_CAPTURE and
PWM_EVENT_TYPE_PERIOD events.
Assisted-by: GitHub Copilot:claude-opus-4.6
Signed-off-by: John Batch <john.batch@infineon.com>
Extend the ESP32 LEDC PWM driver to support ESP32-C5. Clear the
gamma RAM fade function on SoCs that have it to prevent stale
fade parameters from affecting duty cycle output.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
The ESP32 MCPWM driver does not initialize the pinctrl configuration if
only the capture units of MCPWM are used and no other MCPWM outputs are
used. This leads to pwm capture requests timing out. Fix this by applying
the pinctrl configuration during module initialization.
Signed-off-by: Christopher Smith <christophersmith107@gmail.com>
Refactor the PWM capture interrupt handler to properly support all
three capture channels (A, B, and X).
Clear capture FIFOs by reading CVAL registers during enable_capture
Signed-off-by: Felix Wang <fei.wang_3@nxp.com>
Add feature check to ensure these functions are only called when the
hardware supports input filter capture registers.
Update device tree binding documentation to clarify that the
input-filter-count and input-filter-period properties only take
effect when the capture input filter register is available.
Signed-off-by: Felix Wang <fei.wang_3@nxp.com>
Apply PINCTRL_STATE_SLEEP on suspend and PINCTRL_STATE_DEFAULT
on resume. If a sleep pinctrl state is defined in the board DTS,
pins will be reconfigured on suspend. If not defined, the call
is a no-op.
Signed-off-by: Jacob Wienecke <jacob.wienecke@nxp.com>
Implements PWM driver support for the MAX22216/MAX22217 device.
This driver integrates with the Zephyr PWM API and uses the parent
MFD device to perform register access.
Signed-off-by: Cherrence Sarip <cherrence.sarip@analog.com>
Max32 PWM already has built-in support for interrupts at the end of
each PWM period so added baseline support for the PERIOD event type
in CONFIG_PWM_EVENT. Updated PWM Event sample to support
Max32672EvKit.
Signed-off-by: Ryan Wiebe <ryan.wiebe@analog.com>
Adapt all Espressif SoC and driver code to the updated
hal_espressif module synced with IDF master branch.
Main changes:
- clock control: delegate peripheral clock gating to HAL
layer using new clock/reset APIs
- SPI/GDMA: adapt to restructured DMA HAL with new channel
allocation and configuration interfaces
- ethernet: add RMII clock configuration and PHY management
- GPIO: simplify using direct HAL function calls
- flash: adapt to updated SPI flash HAL interfaces
- linker scripts: update IRAM/DRAM mappings for new HAL
object files
- DTS: fix ESP32-S2 PSRAM dcache1 address to match actual
MMU mapping region (0x3f800000 DRAM1 instead of 0x3f500000
DPORT which lacks 8-bit access capability)
- west.yml: update hal_espressif revision
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Extend the PWM API with optional API functions for enabling DMA requests
Possible solution for #88670
Signed-off-by: Vincent Surkijn <vincent.surkijn@siemens.com>
Correct an #if which otherwise is always true, so we do not
refer to a function which does not exist otherwise.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Add PWM driver for the Infineon PSoC4 family.
This includes SoC-specific register configurations, API calls,
and hardware instance mapping required for PSoC4 compatibility.
Signed-off-by: Surya Prakash T <suryat@aerlync.com>
Signed-off-by: Manojkumar Konisetty <manoj@aerlync.com>
Signed-off-by: Sayooj K Karun <sayooj@aerlync.com>
If the clock device (i.e., RCC) failed to initialize, we have bigger
problems than trying to call clock_control_{off,on,configure} on it.
Don't bother checking to save some footprint.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
