Separate the current driver for the FPGA iCE40 into two different ones.
One implements only the SPI load mode, the other one only the GPIO
bitbang mode.
Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
Replace the DT_INST_PROP_OR statements with defaults
in the devicetree binding of the iCE40.
Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
The datasheet of the iCE40 specifies that there should be a leading and
trailing clocks phase during its configuration with SPI. Due to the
limitations of the SPI interface, and probably also due to a lock of
support for such a feature for instance in the STM32 SPI peripheral,
this is achieved with additional SPI transfers before and after the
actual image. Unfortunately, this by default also affects the slave
select GPIO, which has to stay high during these phases.
This fixes this behaviour via not passing the slave select GPIO
to the SPI driver and manipulating this GPIO manually.
Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
Replace NULL checks for the set and clear registers with BUILD_ASSERTs
in the iCE40 device instantiation.
Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
Replace the enum for load modes for the iCE40 with a boolean flag,
as there are only two options:
- SPI: default, which should be used whenever possible
- GPIO bitbang: workarorund, in case a low-end microcontroller is used
Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
Turn the assert into an if-statement to ensure that CDONE is always
checked during the configuration of an iCE40.
Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
Add checks in the GPIO bitbang mode to avoid a fault for missing
configuration in the devicetree.
Fixes#80850
Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
The `<zephyr/posix/time.h>` header was unused in `fpga_ice40.c`
so remove it.
This fixes an error about `pthread_attr_t` not being defined.
Signed-off-by: Christopher Friedt <cfriedt@meta.com>
As of today it is not possible to use SPI dt-spec macros in C++,
something known and documented. The main reason is because `cs` property
is initialized using a compound literal, something not supported in C++.
This PR takes another approach, that is to not make `cs` a pointer but a
struct member. This way, we can perform a regular initialization, at the
cost of using extra memory for unused delay/pin/flags if `cs` is not
used.
Fixes#56572
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The 200ns reset time specified in the datasheet are a minimum time; and the
nanoseconds were being rounded to whole microseconds anyway.
Also make it the same type as `config_delay_us` (`uint16_t`).
Signed-off-by: Armin Brauns <armin.brauns@embedded-solutions.at>
The 200ns reset time are a minimum value, there is no need to enforce
precise timing (and thus manual per-device calibration) here.
Signed-off-by: Armin Brauns <armin.brauns@embedded-solutions.at>
From FPGA-TN-02001-3.3 "iCE40 Programming and Configuration":
> After driving CRESET_B High or allowing it to float High, the AP must
> wait a minimum of 1200 µs, allowing the iCE40 FPGA to clear its internal
> configuration memory.
Signed-off-by: Armin Brauns <armin.brauns@embedded-solutions.at>
