Remove the redundant default n from the STM32 RTC counter Kconfig.
Boolean Kconfig symbols already default to n when no default is set.
Signed-off-by: Yiming Sun <ys160@rice.edu>
Replace direct NVIC pending-state calls with k_irq_set_pending()/
k_irq_is_pending()/k_irq_clear_pending(), dropping the dependency on
cmsis_core.h where nothing else needed it.
Assisted-by: Claude:claude-opus-5
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Two-line copyright notices were wrapped in the SPDX "<text>...</text>"
construct, which is only valid in an SPDX document, not a file header.
The REUSE tool then folds the literal "<text>" into the holder name
and drops the second line from the SBOM.
Remove the markers and tag the continuation line. Holder, year and
e-mail are left unchanged; only the syntax is fixed.
Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com>
The Basic Timer PRE_SCALE field divides the input clock by
(prescaler + 1) per the datasheets, not by the raw prescaler value.
Update the frequency calculation to divide by (prescaler + 1) and
correct the binding description to match.
Signed-off-by: Manimaran A <manimaran.a@microchip.com>
The driver calls IRQ_CONNECT() and irq_enable() but never includes
zephyr/irq.h, relying on it arriving indirectly. That does not always
hold: building samples/drivers/counter/alarm for an Arm Cortex-M
target fails with implicit declarations of both. Fix this.
Signed-off-by: Silesh C V <silesh@alifsemi.com>
counter_dw_timer_init() reads the timer clock rate from the clock
controller but never requests the clock, so it relies on the clock
already being enabled by other means. clock_control_get_rate() is
documented to return -EAGAIN when a driver cannot report the rate of a
clock that is off.
Request the clock with clock_control_on() before reading its rate.
-ENOSYS is tolerated so that clock controllers implementing only
.get_rate keep working, and -EALREADY for controllers that report an
already-enabled clock that way.
Signed-off-by: Silesh C V <silesh@alifsemi.com>
Replace direct NVIC_SetPendingIRQ()/NVIC_ClearPendingIRQ() calls with
k_irq_set_pending()/k_irq_clear_pending(), dropping the dependency on
cmsis_core.h where nothing else needed it. These platforms are
plain-NVIC Cortex-M, so the pending-state capabilities are always
available where this code builds.
Assisted-by: Claude:claude-opus-5
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Replace direct NVIC pending-state calls with k_irq_set_pending()/
k_irq_is_pending()/k_irq_clear_pending(), dropping the dependency on
cmsis_core.h where nothing else needed it.
Assisted-by: Claude:claude-opus-5
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Replace direct NVIC_SetPendingIRQ()/NVIC_ClearPendingIRQ()/
NVIC_EnableIRQ() calls with the portable k_irq_set_pending()/
k_irq_clear_pending()/irq_enable() equivalents. The Smartbond DA1469x
is a plain-NVIC Cortex-M33, so the pending-state capabilities are
always available where this code builds.
Assisted-by: Claude:claude-opus-5
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Replace direct NVIC_SetPendingIRQ()/NVIC_ClearPendingIRQ() calls with
k_irq_set_pending()/k_irq_clear_pending().
This also deletes the driver's private counter_stm32_set_pending()
helper, which hand-dispatched between the ARM GIC and the NVIC --
exactly what the portable API now does -- along with its conditional
gic.h include.
Assisted-by: Claude:claude-opus-5
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Replace direct NVIC_SetPendingIRQ()/NVIC_ClearPendingIRQ() calls with
k_irq_set_pending()/k_irq_clear_pending().
Assisted-by: Claude:claude-opus-5
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The late-alarm comment still referred to NVIC_SetPendingIRQ() after
the code moved to k_irq_set_pending(); make it match.
Assisted-by: Claude:claude-opus-5
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Replace direct NVIC pending-state calls with k_irq_set_pending()/
k_irq_is_pending()/k_irq_clear_pending().
This also deletes the driver's private GIC-or-NVIC dispatch helper,
which is exactly what the portable API now provides.
Assisted-by: Claude:claude-opus-5
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Replace direct NVIC pending-state calls with k_irq_set_pending()/
k_irq_is_pending()/k_irq_clear_pending().
This also deletes the driver's private GIC-or-NVIC dispatch helpers,
which are exactly what the portable API now provides.
Assisted-by: Claude:claude-opus-5
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Replace direct NVIC pending-state calls with k_irq_set_pending()/
k_irq_is_pending()/k_irq_clear_pending().
Assisted-by: Claude:claude-opus-5
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Replace direct NVIC pending-state calls with k_irq_set_pending()/
k_irq_is_pending()/k_irq_clear_pending().
Assisted-by: Claude:claude-opus-5
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Replace direct NVIC pending-state calls with k_irq_set_pending()/
k_irq_is_pending()/k_irq_clear_pending().
Assisted-by: Claude:claude-opus-5
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Replace direct NVIC pending-state calls with k_irq_set_pending()/
k_irq_is_pending()/k_irq_clear_pending(), dropping the dependency on
cmsis_core.h where nothing else needed it.
Assisted-by: Claude:claude-opus-5
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Replace direct NVIC pending-state calls with k_irq_set_pending()/
k_irq_is_pending()/k_irq_clear_pending(), dropping the dependency on
cmsis_core.h where nothing else needed it.
This driver called the arm_gic_irq_* pending helpers directly; the
portable API removes the GIC-specific dependency. The gic.h include
stays for GIC_SPI_INT_BASE.
Assisted-by: Claude:claude-opus-5
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Without this esp_clk_tree_enable_src() is a no-op, so the pll
reference branches keep their cold-boot state. On esp32p4 the
80 MHz branch comes up gated and the timers never tick. Run it
from the clock driver rather than early boot, where gating the
branches stalls the flash bus.
Assisted-by: Claude:opus-4-8
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Added pm_action suspend/resume/turn_on routine for Counter
Assisted-by: Claude:claude-opus-4.8
Signed-off-by: Richard Mc Sweeney <Richard.McSweeney@infineon.com>
The LP_TIMER_INT_ST_ALARM macro special-cases only ESP32-C5 to read
int_st.soc_wakeup_int_st. ESP32-P4 has the same LP timer register
layout: its int_st register has no alarm field, only
soc_wakeup_int_st, so enabling the rtc_timer node on ESP32-P4 fails
to compile.
Extend the condition to cover ESP32-P4.
Signed-off-by: Hongquan Li <hongquan.li@processmission.com>
This commit enables power management support for the MAX32 timer counter
driver. It allows the driver to enter low-power states when the counter
is not in use, improving energy efficiency.
Signed-off-by: Furkan Akkiz <hasanfurkan.akkiz@analog.com>
The QTMR counter driver only programmed the COMP1 compare register and
relied on the hardware compare match. An alarm set too late therefore
did not fire until the 16-bit counter wrapped all the way around (up to
65536 ticks later), violating the counter API contract for short
relative alarms and for absolute alarms using
COUNTER_ALARM_CFG_EXPIRE_WHEN_LATE.
Add guard-period support (get/set_guard_period) and late detection:
after programming COMP1 the driver re-reads the counter and, if it has
already advanced past the target within the guard window, treats the
alarm as late. Late relative alarms and late absolute alarms with
EXPIRE_WHEN_LATE now expire immediately, and late absolute alarms
return -ETIME.
The QTMR ISR is driven purely by hardware status flags and the module
IRQ is shared across all four channels, so immediate expiry is
delivered by marking the channel software-pending, forcing the IRQ
with NVIC_SetPendingIRQ, and synthesizing the compare event in the
ISR. The IRQ number is taken from the parent qtmr node.
Verified on mimxrt1180_evk/mimxrt1189/cm33 with counter_basic_api:
test_short_relative_alarm, test_late_alarm and test_late_alarm_error
now pass on the QTMR instance.
Signed-off-by: Felix Wang <fei.wang_3@nxp.com>
The TSTMR is a read-only timestamp counter, but its clock source is
SoC-specific: on some SoCs (e.g. i.MX RT118x) it is a read-only view of
the System Counter (SYS_CTR) and depends on it being enabled, while on
others (e.g. MCXW or i.MX8ULP) it is a standalone counter that free-runs
from reset and has no SYS_CTR dependency at all.
On i.MX RT118x, where the TSTMR is backed by the SYS_CTR, the driver
reported a hard-coded 1 MHz rate and never enabled the SYS_CTR, so
counter_get_value() returned a frozen or wrongly-scaled count and
tests/drivers/counter/counter_basic_api (test_valid_function_without_
alarm) failed. On RT118x the SYS_CTR (and thus the TSTMR) runs at a
fixed 24 MHz.
Gate the SYS_CTR handling behind a new hidden Kconfig,
COUNTER_MCUX_TSTMR_SYSCTR_BACKEND, selected automatically when the TSTMR
driver is built on a SoC that also has an nxp,sysctr node enabled. On
those SoCs the TSTMR shares the SYS_CTR hardware, so the driver drives
the SYS_CTR_CONTROL registers directly:
- start() sets the count-enable bit (CNTCR.EN) when the counter is off;
- get_freq() returns 0 while the SYS_CTR is disabled so callers can tell
the counter is not yet running;
- the register accesses are compiled out entirely on standalone TSTMR
SoCs (e.g. MCXW or i.MX8ULP), which free-run from reset and do not
depend on SYS_CTR.
In the CCM rev2 clock driver, the IMX_CCM_SYSCTR_BASE_CLK case now also
covers the TSTMR backend and reports the fixed 24 MHz rate, while
IMX_CCM_SYSCTR_SLOW_CLK returns -ENOTSUP for the TSTMR backend: the
SYS_CTR slow-clock path is unreliable for timestamp reads on
RT1180/RT1189, so surfacing the error at init time is safer than
silently producing inaccurate timestamps.
The counter_basic_api test now treats a reported frequency of 0 as
"cannot set a millisecond period", so a not-yet-running counter is
skipped rather than mis-evaluated.
Signed-off-by: Felix Wang <fei.wang_3@nxp.com>
mcux_lpc_ctimer_cancel_alarm() only disabled the channel's match
interrupt; it left the match value programmed and the callback pointer
cleared without dropping the latched status flag. If the free-running
counter reached that stale match value while the interrupt was disabled,
the channel's status flag was still latched on this SoC. A subsequent
mcux_lpc_ctimer_set_alarm() re-registers the callback, so the latched
flag could be delivered to the new callback as a spurious expiry.
Clear the channel status flag in cancel_alarm() so a cancelled match can
no longer be latched into a later alarm. In set_alarm(), mask only this
channel's interrupt and clear its flag before registering the callback,
then let CTIMER_SetupMatch() re-enable the interrupt on the freshly armed
match. Masking a single channel this way is cheaper than taking irq_lock()
across the whole sequence, and a one-tick relative alarm is unaffected
because the callback is registered before the interrupt is re-enabled.
Found with tests/drivers/counter/counter_basic_api on frdm_mcxa366,
where test_cancelled_alarm_does_not_expire intermittently observed one
spurious callback on ctimer@40004000 ("Expected 0 callbacks, got 1").
With this change the test passes.
Signed-off-by: Felix Wang <fei.wang_3@nxp.com>
The mux subsystem rework converted the PWM and qdec INPUTMUX consumers
to mux-states and deleted the #inputmux-cells specifier space, but this
driver was left behind on inputmux-connections, so enabling capture now
fails at devicetree parse time (counter_capture on frdm_mcxa153).
Convert it the same way as pwm_mcux_ctimer: mux-states in the binding
and test overlay (same cells, renamed), a mux_state_apply() loop in the
driver with its error propagated out of init, select MUX in Kconfig,
and the missing Counter entry in the 4.5 migration guide.
Fixes#115616
Signed-off-by: Benjamin Perseghetti <bperseghetti@rudislabs.com>
This adds support for ARM Corstone System Architecture Specification Ma2
(ARM CRSAS-MA2) System Counter and System Timer.
The HW consists of one 64-byt System Counter, and any number
of System Timers that have match registers to generate interrupts
based on the value of the System Counter.
The timers don't have any counter/timer of their own, meaning that
System Counter can't be started or stopped independently if there is an
enabled System Timer.
Add the crsas-ma2 timer to the test for counters.
Signed-off-by: Mike J. Chen <mjchen@google.com>
Signed-off-by: Krystian Hebel <khebel@antmicro.com>
Fix build error on the ace_v1x_{art,rtc} drivers where compiler
cannot find the register header files. Since those header files
reside at the same directory, convert it to local include.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Fixes#113852
Updating the top value on the RPi Pico timer was causing a hardware
glitch that resulted in unusual PWM behavior and frequency spikes.
This patch removes the pwm_init() call and instead uses
pwm_set_wrap() to directly update the hardware slice on the fly.
Signed-off-by: Sudharsan Bakthavatchalam <appubaktha@gmail.com>
Header file include/zephyr/sys_clock.h is deprecated and will be removed
someday. Update the whole file tree to include zephyr/sys/clock.h
straight instead of zephyr/sys_clock.h.
This change was made running the sed shell command below:
$ sed -i 's/zephyr\/sys_clock\.h/zephyr\/sys\/clock\.h/' \
`grep -rsl "zephyr/sys_clock\.h" drivers/`
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Use #include <> instead of #include "" to include a header file which path
is not relative to the directory path of the file emitting the #include
directive.
This change was made running scripts/check_quoted_includes.py script
proposed in https://github.com/zephyrproject-rtos/zephyr/pull/112135
with Linux shell commands like the one below and manually selecting the
applicable changes: only those located in drivers/ since soc/, boards/,
samples/ and tests/ content related to Espressif is addressed in
pull request https://github.com/zephyrproject-rtos/zephyr/pull/112190.
$ ./scripts/check_quoted_includes.py -w \
`./scripts/get_maintainer.py list "Espressif Platforms"`
Also update drivers/clock_control/clock_control_esp32_priv.h that was
not listed by './scripts/get_maintainer.py list "Espressif Platforms"'.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
A plain LPTMR counter that is not the system-timer companion can also
serve as a wakeup source - for example an application arming an alarm
before entering a deep low-power state - but whether it should wake the
SoC is a run-time decision, not a fixed role.
In addition to the companion path, arm the wakeup controller when the
instance has been enabled as a wakeup source at run time
(pm_device_wakeup_enable(), PM_DEVICE_FLAG_WS_ENABLED); the device
declares the capability in devicetree (wakeup-source) and the
application enables it. Register a pm_device so the device can carry the
flag; the action callback has no device power state to manage, so it
accepts suspend/resume and returns -ENOTSUP for anything else. The
registration and the flag check are a no-op unless CONFIG_PM_DEVICE is
enabled, so the companion path stays free of any PM_DEVICE dependency.
Disarming still keys off the static "is a wakeup source" condition and
deliberately does not re-check WS_ENABLED: the run-time flag can be
cleared between arming the alarm and its firing or cancellation, and a
disarm gated on WS_ENABLED would then be skipped, leaving a stale entry
armed in the controller. Because the static condition is a superset of
the arm condition, whatever armed the WUU is always disarmed, and
disarming an instance that never armed is an idempotent no-op.
Build-tested tests/subsys/pm/power_mgmt_soc on frdm_mcxn947.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
When the LPTMR is the system-timer low-power companion, the main system
timer is stopped in deep low-power states and the LPTMR alarm is what
wakes the core. On SoCs that gate the alarm interrupt behind a wakeup
controller (the NXP WUU) the alarm only wakes the SoC once the LPTMR is
armed as a wakeup source, which the driver never did.
Arm the wakeup controller in set_alarm() and disarm it in
cancel_alarm() and the ISR when the LPTMR is a wakeup source -
devicetree both declares it one (wakeup-source) and routes it to a
controller (wakeup-ctrls) - and it is the chosen system-timer companion
(zephyr,system-timer-companion), whose alarm is intrinsically a wake
event. Keying the companion off the devicetree chosen keeps it
independent of the system-timer implementation and needs no device-PM
state; it also covers an application that drives the companion instance
directly (e.g. a system-off wake timer).
The controller is armed and disarmed under the alarm spinlock so a
concurrent set_alarm()/cancel_alarm() pair cannot leave it armed with no
pending alarm (or vice versa); the WUC calls only write registers, so
they are safe under the spinlock and in the ISR. Arming happens before
the alarm is committed and a failure propagates as the set_alarm()
return value rather than a log: on the companion path the console may
already be suspended when this runs, and if the arm failed the SoC would
sleep without waking to flush a deferred message, so only the return
value can act before the sleep. The ISR ignores the disarm result for
the same reason; disarming a devicetree-defined source does not fail.
The companion arms only when it has a deadline to wake for, which falls
out of the alarm lifecycle with no extra check:
- no finite timeout (K_TICKS_FOREVER): the PM core does not hand the
deadline to the companion, set_alarm() is never called and the WUU
stays unarmed, so the SoC waits for another wakeup source;
- finite timeout: the companion is given an alarm, set_alarm() arms
the WUU so the alarm wakes the core.
Disarming keys off the static "is a wakeup source" condition, not on
whether it armed: for the companion this condition never changes, so
arm and disarm always agree and no stale WUU entry is left behind.
Build-tested tests/subsys/pm/power_mgmt_soc and the s2ram / system_off
samples on frdm_mcxn947.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
counter_config_info.freq is uint64_t when COUNTER_64BITS_FREQ is
selected, but counter_mcux_gpt logs it with %u and the ITE it51xxx,
ITE it8xxx2 and Xilinx AXI timer drivers with %d. Any build that
compiles one of these drivers with COUNTER_64BITS_FREQ enabled fails
under -Werror=format=.
Log the frequency with %llu and an explicit cast, which is correct
for both the 32-bit and the 64-bit layout of the field.
Signed-off-by: Holt Sun <holt.sun@nxp.com>
In order to prepare the Timers integration of STM32MP13,
this driver needs to be changed a bit.
Indeed, NVIC functions are called by default at some places but
MP13 is cortex A and uses GIC as interrupt controller.
Get inspired by renesas and nxp drivers to add GIC support
in STM32 one.
Signed-off-by: Erwan SZYMANSKI <erwan.szymanski@st.com>
Commit bbda65a ("drivers: counter: increase COUNTER_INIT_PRIORITY")
raised COUNTER_INIT_PRIORITY from KERNEL_INIT_PRIORITY_DEVICE (50) to
60 to guarantee counter devices initialize before bus-dependent devices
sharing the same default priority.
Revert to KERNEL_INIT_PRIORITY_DEVICE and remove the BUILD_ASSERT in
the RTC counter driver that enforced RTC_INIT_PRIORITY >
COUNTER_INIT_PRIORITY, as both now default to the same value with
ordering guaranteed by DT sub-priority.
Signed-off-by: Soumya Tripathy <s-tripathy@ti.com>
Implement the counter capture API (capture_configure, enable_capture,
disable_capture) for both GPT input capture channels (CAPTURE1 and
CAPTURE2).
Supported trigger modes: rising edge, falling edge, both edges.
Single-shot capture disables the interrupt and resets the channel
after the first event; continuous capture leaves it armed.
Select COUNTER_SUPPORTS_CAPTURE in Kconfig so the generic counter
layer exposes the capture API to applications.
Signed-off-by: Jaro Van Landschoot <jaro.vanlandschoot@basalte.be>
Add optional pinctrl support so board files can mux GPT_CLK,
GPT_CAPTUREn, and GPT_COMPAREn pins via the standard pinctrl-0
property. The default state is applied early in driver init, before
GPT_Init. A missing pinctrl state (-ENOENT) is treated as optional
and silently ignored.
Signed-off-by: Jaro Van Landschoot <jaro.vanlandschoot@basalte.be>
Allow selecting from all five GPT clock sources (off, periph,
high-freq, ext, low-freq, osc) via a new clock-source DT property.
The ext source fixes the prescaler at 1 since the frequency
is unknown to software.
gptfreq is no longer required when clock-source = "ext", in which
case counter_get_freq() returns 0 and callers work in raw ticks.
Signed-off-by: Jaro Van Landschoot <jaro.vanlandschoot@basalte.be>
Let the IRTC wake-timer wake the CPU from deep sleep on SoCs where its
wake path is gated by a WUC (e.g. the i.MX RT700 SLEEPCON). Arm the WUC
line when a one-shot alarm is pending on a wakeup source, and disarm it
when the alarm fires or is cancelled.
The wake-timer is a wakeup source when devicetree declares it one
(wakeup-source) and routes it to a controller (wakeup-ctrls). An armed
alarm then wakes the SoC in two cases: the wake-timer is the chosen
system-timer low-power companion (zephyr,system-timer-companion), whose
alarm arms via the tickless idle path with no run-time enable; or an
application enabled it as a wakeup source at run time
(pm_device_wakeup_enable(), PM_DEVICE_FLAG_WS_ENABLED).
Disarming keys off the static "is a wakeup source" condition, not on the
companion role or the run-time enable: the companion arms without ever
setting WS_ENABLED, and the run-time enable may be cleared while an alarm
is pending, so gating disarm on either would leave a stale entry armed.
Disarming an instance that never armed is an idempotent no-op.
All WUC access is gated by IS_ENABLED(CONFIG_WUC) and a NULL wuc.dev, so
builds and SoCs without WUC are unaffected.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
Give the IRTC wake-timer a PM device with a stub action, initialised via
pm_device_driver_init(). It gates no clocks or state on suspend or resume,
but having a pm_base lets the device be selected as a wakeup source with
pm_device_wakeup_enable(), which sets the WS_ENABLED flag. No functional
change to counter behaviour.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
The counter API declares optional clock calibration ops in signed
parts-per-billion, but the Kinetis RTC counter driver did not
implement them, so counter_set/get_calibration returned -ENOSYS.
Implement them using the RTC Time Compensation Register. TCR[7:0]
configures the number of 32.768 kHz cycles per second as
(32768 - value) with value a two's-complement -128..+127, so a
positive value shortens the second and speeds the counter up,
matching the counter API sign convention. TCR[15:8] (CIR, interval
minus one) is kept at 0 to compensate every second, giving
ppb = value * 1e9 / 32768 (~30518 ppb per LSB, range ~+/-3.9M ppb).
set() rejects out-of-range values with -EINVAL and get() reports the
programmed (quantized) TCR/CIR value so a set()/get() round-trips at
the hardware resolution. The register is double buffered and safe to
write while the counter runs. Compensation counts oscillator cycles,
so the ops return -ENOTSUP when the prescaler runs from the LPO
clock.
Validated on frdm_k64f with tests/drivers/counter/counter_basic_api
(CONFIG_COUNTER_CALIBRATION=y): suite passes including the new
set/get calibration case sweeping +/-200000 ppb.
Link: K64 Sub-Family Reference Manual Rev.2 - ch44 RTC_TCR (44.2.4)
Signed-off-by: Holt Sun <holt.sun@nxp.com>
- Updates the driver to support families which have only one
IRQ line for all the channel interrupts and overflow interrupt
- Adds single ISR for handling the interrupts for such cases.
- Updates custom return values to standard return values
Signed-off-by: Muhammed Asif <asifp3104@gmail.com>
Adopt gptimer retention API and attach sleep retention modules
to effectively enable TOP PD power down.
Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
The async-prescaler default referenced _HSE_ASYNC_PRESCALER, a
truncated spelling of RTC_HSE_ASYNC_PRESCALER that is defined
nowhere, breaking the build for HSE-clocked RTC configurations
without the async-prescaler property.
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
