Define symbolic constants for watchdog timer registers.
Provides the necessary interface to configure or disable
the watchdog timer.
Change-Id: I80002a843361569fdd78b725fc3f68e65195d02e
Signed-off-by: Dmitriy Korovkin <dmitriy.korovkin@windriver.com>
The ARC side should use the same console UART as x86 by default if we
want identical behavior.
Change-Id: I067860581cfd93d97ffad3d8f0bc5591f555e3ce
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
There is a total of 39 IRQs defined at nrf52/soc_irq.h.
Change-Id: Id478fb15a07cfdecaa6cc136730d20017b8752c5
Signed-off-by: Ricardo Salveti <ricardo.salveti@linaro.org>
Quark D2000 and SE based boards (but Arduino 101) use QMSI bootloader
by default. QMSI bootloader sets up GDT in the so-called 'basic flat
model' just like Zephyr does by default.
This patch changes Quark D2000 and SE boards default configuration
so they rely on QMSI bootloader and we don't sets up GDT twice.
Change-Id: Ic6e520148b732bd48c00657c6c8138a8d865faef
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
Zephyr uses the last priority level for the PendSV exception, but
sharing prio can still be useful on systems with a reduced set of
priorities, like Cortex-M0/M0+.
Change-Id: I767527419dcd8f67c2b406756b9208afd3b96de0
Signed-off-by: Ricardo Salveti <ricardo.salveti@linaro.org>
_irq_controller_isr_vector_get() now returns -1 if it couldn't
determine which vector was activated.
Issue: ZEP-602
Change-Id: Ib0f5dbc3b68cc5e2c3a23121530e178aede20d06
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Change the signal ramp up/down config parameters in i2c driver
module to SoC specific.
Jira: ZEP-753
Change-Id: Ie01f1d890a7133d30ea53eee07f60354734a8571
Signed-off-by: Baohong Liu <baohong.liu@intel.com>
Add a shim layer around the ksdk I2C driver to adapt it to the Zephyr
I2C interface. Currently only supports master mode.
Jira: ZEP-717
Change-Id: I704b8c38e22e456bb9fa4325682b2a354a27a7ba
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Since nrf.h abstracts the differences between the nRF51 and nRF52
architectures and chooses the right headers to include, it is
safer to use that instead of directly including the soc-specific
headers.
Jira: ZEP-702
Change-Id: I0e1758ede48f3422a41d226b0eab008e4ba2c77c
Signed-off-by: Vinayak Chettimada <vinayak.kariappa.chettimada@nordicsemi.no>
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
Originally, x86 just supported APIC. Then later support
for the Mint Valley Interrupt Controller was added. This
controller is mostly similar to the APIC with some differences,
but was integrated in a somewhat hacked-up fashion.
Now we define irq_controller.h, which is a layer of abstraction
between the core arch code and the interrupt controller
implementation.
Contents of the API:
- Controllers with a fixed irq-to-vector mapping define
_IRQ_CONTROLLER_VECTOR_MAPPING(irq) to obtain a compile-time
map between the two.
- _irq_controller_program() notifies the interrupt controller
what vector will be used for a particular IRQ along with triggering
flags
- _irq_controller_isr_vector_get() reports the vector number of
the IRQ currently being serviced
- In assembly language domain, _irq_controller_eoi implements
EOI handling.
- Since triggering options can vary, some common defines for
triggering IRQ_TRIGGER_EDGE, IRQ_TRIGGER_LEVEL, IRQ_POLARITY_HIGH,
IRQ_POLARITY_LOW introduced.
Specific changes made:
- New Kconfig X86_FIXED_IRQ_MAPPING for those interrupt controllers
that have a fixed relationship between IRQ lines and IDT vectors.
- MVIC driver rewritten per the HAS instead of the tortuous methods
used to get it to behave like LOAPIC. We are no longer writing values
to reserved registers. Additional assertions added.
- Some cleanup in the loapic_timer driver to make the MVIC differences
clearer.
- Unused APIs removed, or folded into calling code when used just once.
- MVIC doesn't bother to write a -1 to the intList priority field since
it gets ignored anyway
Issue: ZEP-48
Change-Id: I071a477ea68c36e00c3d0653ce74b3583454154d
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Treat the sensor subsystem as an independent board that can send
messages to UART and disable IPM and the messaging interface. IPM
can be enabled by applications that require such interface.
Fix all samples that are affected by this change to make sanitycheck
pass.
Jira: ZEP-451
Change-Id: I3df6af16adefaefec02b97778d6c68ffc920ac35
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The ksdk provides a clock driver, fsl_clock.c, for the K64F and an
example usage of that driver, clock_config.c, for the Freedom board.
See ext/hal/ksdk/devices/MK64F12/
Leverage parts of clock_config.c to configure the clocks (specifically,
the sequence in BOARD_BootClockRUN()), but use the new Kconfig options
to set up the configuration structure. This will allow support for new
boards that may have a different external oscillator frequency or type.
Jira: ZEP-715
Change-Id: I3f0c75e6236f57600cd8b7f06f4482b13026fc10
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Many Kinetis SoCs contain an Oscillator (OSC) module and a Multipurpose
Clock Generator (MCG) module to configure clocks. Adding options to
configure these modules for PLL operation with different external
oscillator frequencies, which can vary across boards. More options may
be added later to support other clocking modes such as FLL.
Jira: ZEP-715
Change-Id: Ia121cc5b464d7e681883507bd756d331a8abd6ef
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
The toolchain headers included an abstraction for defining symbol
names in assembly context in the situation where we're using a
DOS-style assembler that automatically prepends an underscore to
symbol names.
We aren't. Zephyr is an ELF platform. None of our toolchains do
this. Nothing sets the "TOOL_PREPENDS_UNDERSCORE" macro from within
the project, and it surely isn't an industry standard. Yank it out.
Now we can write assembler labels in natural syntax, and a few other
things fall out to simplify too.
(NOTE: these headers contain assembly code and will fail checkpatch.
That is an expected false positive.)
Change-Id: Ic89e74422b52fe50b3b7306a0347d7a560259581
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
These files were almost exactly the same and had already started
bit-rotting (note the missing net_l2 section in linker_harvard.ld)
Issue: ZEP-528
Change-Id: I5039a2c1b86c5764a361b268c33ae8b17da1a9e0
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Defined in all SoCs, but never referenced anywhere. That definition has
been replaced by CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC.
Change-Id: I1801f72a03925717ded6fbfdef22b1993f843461
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
Completing the terminology change started with change 4008
by updating the Kconfig files processed to produce the
online documentation, plus header files processed by
doxygen. References to 'platform' are change to 'board'
Change-Id: Id0ed3dc1439a0ea0a4bd19d4904889cf79bec33e
Jira: ZEP-534
Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
A previous re-work of IRQ priorities was led astray by an incorrect
comment. Priority level 1 is not a non-maskable interrupt priority.
In addition, zero latency IRQs are not implemented on ARC.
Timer driver now doesn't specify IRQ_ZERO_LATENCY (as that wouldn't be
correct) and its IRQ priority is now tunable in Kconfig. The default is 0.
IPM driver on both ARC and x86 side were being configured with hard-coded
priority of 2, which wasn't valid for ARC and caused an assertion failure.
The priority level is now tunable with Kconfig and defaults to 1 for ARC.
Issue: ZEP-693
Change-Id: If76dbfee214be7630d787be0bce4549a1ecbcb5b
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
0 should be fine; no need to make this an FIRQ or non-maskable
Change-Id: Ifdf89a72e4864a2c2bbd83752cd814e2cb9aa16e
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
The GPIO and UART drivers were failing to build due to some
missing soc.h defines.
Change-Id: I6811e3699449da0a61ccc8376a8e11b96ad7a4e5
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Add a Kconfig option to select between the Hard and Soft Float ABIs. We
also default to the Hard Float ABI as this is what older SDK versions
supported.
JIRA: ZEP-555
Change-Id: I2180c98cd7556ab49f5ca9b46b31add2c11bd07b
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
QMSI boot loader uses GPS0. power.c should use GPS1 for its
purpose because GPS1 is reserved for PM use. Switched to
use GPS1 instead.
Jira: ZEP-647
Change-Id: I653450cd0b42aa80bef21c8a42f4aa39cdaef2ed
Signed-off-by: Ramesh Thomas <ramesh.thomas@intel.com>
The K64F SoC initialization previously used macros and structs
custom-defined in Zephyr in order to access peripheral registers.
Refactored it to use CMSIS-style register accesses from the ksdk
instead.
Change-Id: I80975c62de07ec95cf830e99cd5b0abb9623acd0
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
The boot initialization and boot process of the sensor sub systems
is now using the new system log macros and updated the Kconfig
variable to be a level rather than a bool.
Change-Id: I098143684f8e7077a525e7fcbc93b42b22d427ac
Signed-off-by: Genaro Saucedo Tejada <genaro.saucedo.tejada@intel.com>
Reflects RAM increase that we get with SDK 0.8.2.
Change-Id: I5d7157834e29bb56864e81fedfb9766d5e4a24f8
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Previously, exception stubs had to be declared in assembly
language files. Now we have two new APIs to regsiter exception
handlers at C toplevel:
_EXCEPTION_CONNECT_CODE(handler, vector)
_EXCEPTION_CONNECT_NOCODE(handler, vector)
For x86 exceptions that do and do not push error codes onto
the stack respectively.
In addition, it's now no longer necessary to #define around
exception registration. We now use .gnu.linkonce magic such that
the first _EXCEPTION_CONNECT_*() that the linker finds is used
for the specified vector. Applications are free to install their
own exception handlers which will take precedence over default
handlers such as installed by arch/x86/core/fatal.c
Some Makefiles have been adjusted so that the default exception
handlers in arch/x86/core/fatal.c are linked last. The code has
been tested that the right order of precedence is taken for
exceptions overridden in the floating point, gdb debug, or
application code. The asm SYS_NANO_CPU_EXC_CONNECT API has been
removed; it was ill- conceived as it only worked for exceptions
that didn't push error codes. All the asm NANO_CPU_EXC_CONNECT_*
APIs are gone as well in favor of the new _EXCEPTION_CONNNECT_*()
APIs.
CONFIG_EXCEPTION_DEBUG no longer needs to be disabled for test
cases that define their own exception handlers.
Issue: ZEP-203
Change-Id: I782e0143fba832d18cdf4daaa7e47820595fe041
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
CONFIG_SOC_GENERIC_ARC doesn't exist so remove it.
Change-Id: Idecfd27684b5fd83b7b296daa46a1a21a0ae4d95
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
We have already done this on x86 and ARM. The policy is as follows:
* IRQ priority levels starting at 0 all have the same semantics and
do not have special properties. The priority level is either ignored
on arches which do not support programmable priority levels, or lower
priority levels take precedence over higher ones.
* Special-case priorty levels are specified via flags, in which case
the supplied priority level is ignored.
Issue: ZEP-60
Change-Id: Ic603f49299ee1426fb9350ca29d0b8ef96a1d53a
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Created set of functions that was designed in the original RFC to
contain arch and soc specific code. This makes the interface to
the OS PM infrastructure cleaner and makes it easier to understand
the flow in the sample app. Also it makes code reuse easier across
soc/arch implementations. These are open to change in future if
other means to achieve the same goals are in place.
Jira: ZEP-227 ZEP-225
Change-Id: Ief57871c370341c55009ad4f456b7f71f2c2a3c6
Signed-off-by: Ramesh Thomas <ramesh.thomas@intel.com>
The interrupt stack wasn't being initialized at boot.
Change-Id: Iec3e770d385643415641e15906c3a53f7c74a2e9
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Utilize the gcc -print-libgcc-file-name to determine the path to
libgcc.a. Using this also resolve issues if we are building with
floating point and the various ABIs to pickup the right lib.
We can also simply a few Makefiles and remove the need to export
_CROSS_COMPILE_arm_isa.
Change-Id: I293394c921c18fa4984173ba51825d6f9a333697
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Until now, EOI had always been sent out to the APIC with interrupts
unlocked. Depending on timing, there is a race where the next interrupt
on the same line could arrive before _IntExit disables interrupts
and pops context. If this happens consecutively enough times, the
interrupt stack will overflow.
Now we disable interrupts at the beginning of _IntExitWithEoi and they
remain that way until 'iret'.
Change-Id: Ibb28e0db902ff483d7a885389f231ac2d1864657
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Arches now select whether they want to use the GCC built-ins,
their own assembly implementation, or the generic C code.
At the moment, the SDK compilers only support builtins for ARM
and X86. ZEP-557 opened to investigate further.
Change-Id: I53e411b4967d87f737338379bd482bd653f19422
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This is at the expense of code size. The QEMU and MAX10
targets have plenty of space so enable it for these boards,
but leave off by default for others.
Change-Id: I93fdb7db14232727e9953b22490d8869ff3b60e7
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
The comments for INT_ACTIVE and EXC_ACTIVE now refer to
"executing context ..." for all architectures.
Change-Id: Ib868958639a3b30e1814fcaa4d1f0651d3b2561e
Signed-off-by: Peter Mitsis <peter.mitsis@windriver.com>
When CONFIG_SYS_POWER_DEEP_SLEEP is enabled, the _sys_soc_resume
function is called and the 'ZF' bit from EFLAGS register may be set
to 1. In that case, we end up wrongly jumping into 'copyDataDone'
label and no data is copied from ROM to RAM.
It seems this 'je' instruction is used without any previous comparison
operation which properly sets the ZF flag. Since 'ZF' initial value is
0, we never jump into 'copyDataDone' label. Also, this 'je' instruction
doesn't seem to be really required since, if %ecx is zero, no data will
be copied anyway.
That being said, this patch removes the 'je' instruction since it fixes
the bug described in the first paragraph and it doesn't affect the rest
of the crt0 execution.
Also, removes outdated information about section size and alignment.
Change-Id: Ia062b78247c4059009193a53f879aa1ebe80881d
Signed-off-by: Andre Guedes <andre.guedes@intel.com>
Signed-off-by: Iván Briano <ivan.briano@intel.com>
The 16550 will now be the default console device.
Change-Id: I92a6b49984b055e7d5f5c97e5192150be0d5c5c7
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
