arc: RGF_NUM_BANKS is another configurable option for ARCs
In order to add the EM7D SOC, I will be implementing a version of the FIRQ interrupt handler that saves and restores registers on the stack when RGF_NUM_BANKS==1. All other ARC SOCs at this time have RGF_NUM_BANKS==2, allowing for a faster handler that can use the registers in the 2nd register bank. But EM7D doesn't have this 2nd bank, hence the need for this new configurable choice. (See ZEP-966) Change-Id: Ie089f1f079902552cf279c2cda23ee0805b01eed Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
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@ -112,6 +112,20 @@ config NUM_IRQS
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The BSP must provide a valid default. This drives the size of the
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vector table.
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config RGF_NUM_BANKS
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int
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prompt "Number of General Purpose Register Banks"
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depends on CPU_ARCV2
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range 1 2
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default 2
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help
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The ARC CPU can be configured to have more than one register
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bank. If fast interrupts are supported (FIRQ), the 2nd
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register bank, in the set, will be used by FIRQ interrupts.
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If fast interrupts are supported but there is only 1
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register bank, the fast interrupt handler must save
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and restore general purpose regsiters.
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config FIRQ_STACK_SIZE
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int
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prompt "Size of stack for FIRQs (in bytes)"
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@ -36,6 +36,9 @@ config NUM_IRQS
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# must be > the highest interrupt number used
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default 36
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config RGF_NUM_BANKS
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default 2
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config SYS_CLOCK_HW_CYCLES_PER_SEC
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default 20000000
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@ -36,6 +36,9 @@ config NUM_IRQS
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# must be > the highest interrupt number used
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default 36
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config RGF_NUM_BANKS
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default 2
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config SYS_CLOCK_HW_CYCLES_PER_SEC
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default 20000000
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@ -33,6 +33,9 @@ config NUM_IRQS
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# must be > the highest interrupt number used
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default 68
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config RGF_NUM_BANKS
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default 2
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config SYS_CLOCK_HW_CYCLES_PER_SEC
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default 32000000
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