Commit graph

5896 commits

Author SHA1 Message Date
Daniel Leung
8fbb14ef50 coredump: add support for x86 and x86_64
This adds the necessary bits to enable coredump for x86
and x86_64.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2020-08-24 20:28:24 -04:00
Daniel Leung
49206a86ff debug/coredump: add a primitive coredump mechanism
This adds a very primitive coredump mechanism under subsys/debug
where during fatal error, register and memory content can be
dumped to coredump backend. One such backend utilizing log
module for output is included. Once the coredump log is converted
to a binary file, it can be used with the ELF output file as
inputs to an overly simplified implementation of a GDB server.
This GDB server can be attached via the target remote command of
GDB and will be serving register and memory content. This allows
using GDB to examine stack and memory where the fatal error
occurred.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2020-08-24 20:28:24 -04:00
Anas Nashif
0be0743144 tracing: x86: trace isr_exit
We were missing exit from ISR..

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2020-08-24 13:21:12 +02:00
Anas Nashif
e5e6ba240d tracing: posix_arch: trace swap
Moving trace points to the architecture code.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2020-08-24 13:21:12 +02:00
Anas Nashif
caa348034f tracing: riscv: fix tracing of context switch
We had switched_in and switched_out mixed up.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2020-08-24 13:21:12 +02:00
Anas Nashif
b234660f4f tracing: cortex_a53: fix order of swap tracing
We had switched_in and switched_out mixed up.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2020-08-24 13:21:12 +02:00
Anas Nashif
c1a2c7992b tracing: nios2: fix swap tracing
Fixed ordering of tracepoints for the nios2 architecture.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2020-08-24 13:21:12 +02:00
Anas Nashif
a45c403c56 tracing: arc: depend on CONFIG_TRACING_ISR for ISRs
Use CONFIG_TRACING_ISR to exclude tracing ISRs just like other
architectures.

Also, z_sys_trace_isr_exit was not defined (It was renamed some time ago
and this was forgotten...)

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2020-08-24 13:21:12 +02:00
Anas Nashif
d1049dc258 tracing: swap: cleanup trace points and their location
Move tracing switched_in and switched_out to the architecture code and
remove duplications. This changes swap tracing for x86, xtensa.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2020-08-24 13:21:12 +02:00
Andrew Boie
44ed730724 x86: static scope for exception handlers
These just need `__used` to avoid compiler warnings.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2020-08-20 10:19:41 +02:00
Anas Nashif
bc40cbc9b4 arch: x86: guard some functions based on usage
Found when building with clang..

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2020-08-19 06:57:40 -04:00
Carlo Caione
310057d641 arch: arm64: Parametrize registers usage for z_arm64_{enter,exit}_exc
Make explicit what registers we are going to be touched / modified when
using z_arm64_enter_exc and z_arm64_exit_exc.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2020-08-18 15:17:39 +02:00
Carlo Caione
d187830929 arch: arm64: Rework registers allocation
Rationalize the registers usage trying to reuse the smallest set of
registers possible.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2020-08-18 15:17:39 +02:00
Andrew Boie
ed972b9582 arm: remove custom k_thread_abort() for Cortex-R
The default implementation is the same as this custom
one now, as the assertion that the context switch occurs
at the end of the ISR is true for all arches.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2020-08-18 08:36:35 +02:00
Andrew Boie
be0d69f1e6 arch: posix: don't exit ISR on thread abort
If a thread is running, an ISR fires, and the ISR
itself calls k_thread_abort() on the thread, the ISR
was being unexpectedly terminated.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2020-08-18 08:36:35 +02:00
Henrik Brix Andersen
e7f51fa918 arch: arm: aarch32: add support for Cortex-M1
Add support for the ARM Cortex-M1 CPU.

Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
2020-08-14 13:35:39 -05:00
Andrew Boie
83aedb2377 x86: increment default page pool pages
With the current identity mapping scheme a new test requires
some more memory to be set aside here.

In production this parameter gets turned per-board, and
the pending paging code overhaul in #27001 significantly
relaxes this as driver I/O mappings are no longer sparse.

Fixes a runtime failure in tests/kernel/device on
qemu_x86_64 that somehow slipped past CI.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2020-08-12 16:13:19 -05:00
Anas Nashif
ce59510127 arch: xip: cleanup XIP Kconfig
unify how XIP is configured across architectures. Use imply instead of
setting defaults per architecture and imply XIP on riscv arch and remove
XIP configuration from individual defconfig files to match other
architectures.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2020-08-07 09:50:22 -04:00
Ioannis Glaropoulos
fa04bf615c arch: arm: cortex-m: hw stack protection under no multi-threading
This commit adds the support for HW Stack Protection when
building Zephyr without support for multi-threading. The
single MPU guard (if the feature is enabled) is set to
guard the Main stack area. The stack fail check is also
updated.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2020-08-07 13:06:04 +02:00
Ioannis Glaropoulos
4338552175 arch: arm: cortex-m: introduce custom switch to main function
For the case of building Zephy with no-multithreading
support (CONFIG_MULTITHREADING=n) we introduce a
custom (ARCH-specific) function to switch to main()
from cstart(). This is required, since the Cortex-M
initialization code is temporarily using the interrupt
stack and main() should be using the z_main_stack,
instead. The function performs the PSP switching,
the PSPLIM setting (for ARMv8-M), FPU initialization
and static memory region initialization, to mimic
what the normal (CONFIG_MULTITHREADING=y) case does.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2020-08-07 13:06:04 +02:00
Ioannis Glaropoulos
e9a85eec28 arch: arm: cortex-m: extract common code block into a static function
We extract the common code for both multithreading and
non-multithreading cases into a common static function
which will get called in Cortex-M archictecture initialization.
This commit does not introduce behavioral changes.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2020-08-07 13:06:04 +02:00
Ioannis Glaropoulos
1a5390f438 arch: arm: cortex-m: fix the accounted size of IRQ stack in reset.S
This patch is simply adding the guard area (if applicable) to
the calculations for the size of the interrupt stack in reset.S
for ARM Cortex-M architecture. If exists, the GUARD area is
always reserved aside from CONFIG_ISR_STACK_SIZE, since the
interrupt stack is defined using the K_KERNEL_STACK_DEFINE.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2020-08-07 13:06:04 +02:00
Torsten Rasmussen
bb3946666f cmake: fix include directories to work with out-of-tree arch
Include directories for ${ARCH} is not specified correctly.
Several places in Zephyr, the include directories are specified as:
${ZEPHYR_BASE}/arch/${ARCH}/include
the correct line is:
${ARCH_DIR}/${ARCH}/include
to correctly support out of tree archs.

Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
2020-08-05 08:06:07 -04:00
Carles Cufi
244f826e3c cmake: remove _if_kconfig() functions
This set of functions seem to be there just because of historical
reasons, stemming from Kbuild. They are non-obvious and prone to errors,
so remove them in favor of the `_ifdef()` ones with an explicit
`CONFIG_` condition.

Script used:

git grep -l _if_kconfig | xargs sed -E -i
"s/_if_kconfig\(\s*(\w*)/_ifdef(CONFIG_\U\1\E \1/g"

Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
2020-08-01 12:35:20 +02:00
Andrew Boie
8b4b0d6264 kernel: z_interrupt_stacks are now kernel stacks
This will save memory on many platforms that enable
user mode.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2020-07-30 21:11:14 -04:00
Andrew Boie
8ce260d8df kernel: introduce supervisor-only stacks
These stacks are appropriate for threads that run purely in
supervisor mode, and also as stacks for interrupt and exception
handling.

Two new arch defines are introduced:

- ARCH_KERNEL_STACK_GUARD_SIZE
- ARCH_KERNEL_STACK_OBJ_ALIGN

New public declaration macros:

- K_KERNEL_STACK_RESERVED
- K_KERNEL_STACK_EXTERN
- K_KERNEL_STACK_DEFINE
- K_KERNEL_STACK_ARRAY_DEFINE
- K_KERNEL_STACK_MEMBER
- K_KERNEL_STACK_SIZEOF

If user mode is not enabled, K_KERNEL_STACK_* and K_THREAD_STACK_*
are equivalent.

Separately generated privilege elevation stacks are now declared
like kernel stacks, removing the need for K_PRIVILEGE_STACK_ALIGN.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2020-07-30 21:11:14 -04:00
Andrew Boie
e4cc84a537 kernel: update arch_switch_to_main_thread()
This now takes a stack pointer as an argument with TLS
and random offsets accounted for properly.

Based on #24467 authored by Flavio Ceolin.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2020-07-30 21:11:14 -04:00
Andrew Boie
b0c155f3ca kernel: overhaul stack specification
The core kernel computes the initial stack pointer
for a thread, properly aligning it and subtracting out
any random offsets or thread-local storage areas.
arch_new_thread() no longer needs to make any calculations,
an initial stack frame may be placed at the bounds of
the new 'stack_ptr' parameter passed in. This parameter
replaces 'stack_size'.

thread->stack_info is now set before arch_new_thread()
is invoked, z_new_thread_init() has been removed.
The values populated may need to be adjusted on arches
which carve-out MPU guard space from the actual stack
buffer.

thread->stack_info now has a new member 'delta' which
indicates any offset applied for TLS or random offset.
It's used so the calculations don't need to be repeated
if the thread later drops to user mode.

CONFIG_INIT_STACKS logic is now performed inside
z_setup_new_thread(), before arch_new_thread() is called.

thread->stack_info is now defined as the canonical
user-accessible area within the stack object, including
random offsets and TLS. It will never include any
carved-out memory for MPU guards and must be updated at
runtime if guards are removed.

Available stack space is now optimized. Some arches may
need to significantly round up the buffer size to account
for page-level granularity or MPU power-of-two requirements.
This space is now accounted for and used by virtue of
the Z_THREAD_STACK_SIZE_ADJUST() call in z_setup_new_thread.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2020-07-30 21:11:14 -04:00
Andrew Boie
24825c8667 arches: fix arch_new_thread param names
MISRA-C wants the parameter names in a function implementaion
to match the names used by the header prototype.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2020-07-30 21:11:14 -04:00
Andrew Boie
0c69561469 arch: remove duplicate docs for arch_new_thread
This interface is documented already in
kernel/include/kernel_arch_interface.h

Other architectural notes were left in place except where
they were incorrect (like the thread struct
being in the low stack addresses)

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2020-07-30 21:11:14 -04:00
Andrew Boie
62eb7d99dc arch_interface: remove unnecessary params
arch_new_thread() passes along the thread priority and option
flags, but these are already initialized in thread->base and
can be accessed there if needed.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2020-07-30 21:11:14 -04:00
Ioannis Glaropoulos
b0c5e6335a arch: arm: cortex-m: move the relay table section after vector table
In CPUs with VTOR we are free to place the relay vector table
section anywhere inside ROM_START section (as long as we respect
alignment requirements). This PR moves the relay table towards
the end of ROM_START. This leaves sufficient area for placing
some SoC-specific sections inside ROM_START that need to start
at a fixed address.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2020-07-27 13:23:36 +02:00
David Leach
565a61dd79 arch/x86: zefi: Fix mismatch in printf with args
printf function didn't have enough specifiers for the
number of arguments in the command line (Coverity warning).

Fixes #26985
Fixes #26986

Signed-off-by: David Leach <david.leach@nxp.com>
2020-07-24 21:51:14 -04:00
Eugeniy Paltsev
9cb9906418 ARC: cleanup exit_tickless_idle
Rewrite 'exit_tickless_idle' macro to make code more readable.
No functional changes intended.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
2020-07-24 12:05:12 +02:00
Eugeniy Paltsev
3f544ca5b2 ARC: replace NOP ASM inlines with builtin
NOP instruction is available via builtin for ARC so get rid of all
ASM inlines with NOP/NOP_S instructions.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
2020-07-24 12:05:12 +02:00
Andrzej Głąbek
ec8cb07da2 arch: arm: Export vector table symbols with GDATA instead of GTEXT
_vector_table and __vector_relay_table symbols were exported with GTEXT
(i.e. as functions). That resulted in bit[0] being incorrectly set in
the addresses they represent (for functions this bit set to 1 specifies
execution in Thumb state).
This commit corrects this by switching to exporting these objects as
objects, i.e. with GDATA.

Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
2020-07-24 12:04:28 +02:00
Daniel Leung
3f6ac9fdfd arm: add include guard for offset files
MISRA-C directive 4.10 requires that files being included must
prevent itself from being included more than once. So add
include guards to the offset files, even though they are C
source files.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2020-07-24 10:01:12 +02:00
Daniel Leung
49199641b9 x86: add include guard for offset files
MISRA-C directive 4.10 requires that files being included must
prevent itself from being included more than once. So add
include guards to the offset files, even though they are C
source files.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2020-07-24 10:01:12 +02:00
David Leach
5803ec1bf0 arch: arm: mpu: Use temporary MPU mapping while reprogramming NXP MPU
Race conditions exist when remapping the NXP MPU. When writing the
start, end, or attribute registers of a MPU descriptor, the hardware
will automatically clear the region's valid bit. If that region gets
accessed before the code is able to set the valid bit, the core will
fault.

Issue #20595 revealled this problem with the code in region_init()
when the compiler options are set to no optimizations. The code
generated by the compiler put local variables on the stack and then
read those stack based variables when writing the MPU descriptor
registers. If that region mapped the stack a memory fault would occur.
Higher compiler optimizations would store these local variables in
CPU registers which avoided the memory access when programming the
MPU descriptor.

Because the NXP MPU uses a logic OR operation of the MPU descriptors,
the fix uses the last descriptor in the MPU hardware to remap all of
dynamic memory for access instead of the first of the dynamic memory
descriptors as was occuring before. This allows reprogramming of the
primary discriptor blocks without having a memory fault. After all
the dynamic memory blocks are mapped, the unused blocks will have
their valid bits cleared including this temporary one, if it wasn't
alread changed during the mapping of the current set.

Fixes #20595

Signed-off-by: David Leach <david.leach@nxp.com>
2020-07-22 11:27:40 +02:00
Eugeniy Paltsev
3eee762e08 ARC: NSIM: switch to ns16550 UART model
Switch nSIM from custom ARC UART to ns16550 model. That will
allow us to use zephyr images built for nSIM on other platforms
like HAPS, QEMU, etc...

This patch do:
 * switch nSIM board to ns16550 UART usage
 * change nSIM simulator configuration to use ns16550 UART model
 * drop checks for CONFIG_UART_NSIM in ARC code
 * update nSIM documentation

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
2020-07-20 13:34:34 -04:00
Andrew Boie
98bcc51b09 x86: gen_gdt: improve docstring
Describe what info we're snarfing out of the prebuilt kernel.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2020-07-19 08:50:52 -04:00
Johan Hedberg
38333afe0e arch: x86: zefi: Reduce data section alignment requirement from 8 to 4
It's not safe to assume that the data section is 8-byte aligned.
Assuming 4-byte alignment seems to work however, and results in
simpler code than arbitrary alignment support.

Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2020-07-18 08:44:31 -04:00
Anas Nashif
4382532fd3 x86: zefi: support arguments and make compatible with windows
Add argument parsing and use os.path.join where possible to support
building on windows.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2020-07-18 08:44:31 -04:00
Andrew Boie
4df734683e x86: 32-bit: enable thread stack info
The hardware stack overflow feature requires
CONFIG_THREAD_STACK_INFO enabled in order to distingush
stack overflows from other causes when we get an exception.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2020-07-18 07:21:53 -04:00
Andrew Boie
aec607cc67 x86: remove memory mapping SOC code
This isn't needed any more, all of these directives were
for drivers which use device_map() now.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2020-07-17 11:38:18 +02:00
Andrew Boie
c802cc8920 x86: pcie: use device_map() for MMIO config access
Replaces custom runtime calls to map memory.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2020-07-17 11:38:18 +02:00
Andrew Boie
ee3c50ba6d x86: apic: use device MMIO APIs
A hack was required for the loapic code due to the address
range not being in DTS. A bug was filed.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2020-07-17 11:38:18 +02:00
Andrew Boie
a810c7b5a0 x86: early_serial: use device_map()
This driver code uses PCIe and doesn't use Zephyr's
device model, so we can't use the nice DEVICE_MMIO macros.
Set stuff up manually instead using device_map().

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2020-07-17 11:38:18 +02:00
Andrew Boie
e7376057ca x86: add arch_mem_map()
This currently only supports identity paging; there's just
enough here for device_map() calls to work.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2020-07-17 11:38:18 +02:00
Andrew Boie
542dcae0c7 arch: add CONFIG_MMU
This config indicates that a memory management unit is present
and enabled, which will in turn allow arch APIs to allow
mapping memory to be used.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2020-07-17 11:38:18 +02:00