arch: arm: aarch32: add support for Cortex-M1
Add support for the ARM Cortex-M1 CPU. Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
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4 changed files with 20 additions and 8 deletions
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@ -23,6 +23,13 @@ config CPU_CORTEX_M0PLUS
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help
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This option signifies the use of a Cortex-M0+ CPU
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config CPU_CORTEX_M1
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bool
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select CPU_CORTEX_M
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select ARMV6_M_ARMV8_M_BASELINE
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help
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This option signifies the use of a Cortex-M1 CPU
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config CPU_CORTEX_M3
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bool
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select CPU_CORTEX_M
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@ -72,7 +79,7 @@ config CPU_CORTEX_M_HAS_SYSTICK
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config CPU_CORTEX_M_HAS_DWT
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bool
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depends on !CPU_CORTEX_M0 && !CPU_CORTEX_M0PLUS
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depends on !CPU_CORTEX_M0 && !CPU_CORTEX_M0PLUS && !CPU_CORTEX_M1
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help
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This option signifies that the CPU implements the Data Watchpoint and
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Trace (DWT) unit specified by the ARMv7-M and above.
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@ -96,14 +103,14 @@ config CPU_CORTEX_M_HAS_BASEPRI
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config CPU_CORTEX_M_HAS_VTOR
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bool
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depends on !CPU_CORTEX_M0
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depends on !CPU_CORTEX_M0 && !CPU_CORTEX_M1
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help
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This option signifies the CPU has the VTOR register.
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The VTOR indicates the offset of the vector table base
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address from memory address 0x00000000. Always present
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in CPUs implementing the ARMv7-M or ARMv8-M architectures.
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Optional in CPUs implementing ARMv6-M, ARMv8-M Baseline
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architectures (except for Cortex-M0, where it is never
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architectures (except for Cortex-M0/M1, where it is never
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implemented).
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config CPU_CORTEX_M_HAS_SPLIM
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@ -229,7 +236,7 @@ config ARMV8_M_DSP
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This option signifies the use of an ARMv8-M processor
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implementation supporting the DSP Extension.
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menu "ARM Cortex-M0/M0+/M3/M4/M7/M23/M33 options"
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menu "ARM Cortex-M0/M0+/M1/M3/M4/M7/M23/M33 options"
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depends on ARMV6_M_ARMV8_M_BASELINE || ARMV7_M_ARMV8_M_MAINLINE
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config GEN_ISR_TABLES
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@ -170,8 +170,8 @@ out_fp_endif:
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/* Restore previous interrupt disable state (irq_lock key)
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* (We clear the arch.basepri field after restoring state)
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*/
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#if (defined(CONFIG_CPU_CORTEX_M0PLUS) || defined(CONFIG_CPU_CORTEX_M0)) && \
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_thread_offset_to_basepri > 124
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#if (defined(CONFIG_CPU_CORTEX_M0PLUS) || defined(CONFIG_CPU_CORTEX_M0) || \
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defined(CONFIG_CPU_CORTEX_M1)) && _thread_offset_to_basepri > 124
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/* Doing it this way since the offset to thread->arch.basepri can in
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* some configurations be larger than the maximum of 124 for ldr/str
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* immediate offsets.
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@ -70,6 +70,8 @@ typedef enum {
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#define __CM0_REV 0
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#elif defined(CONFIG_CPU_CORTEX_M0PLUS)
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#define __CM0PLUS_REV 0
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#elif defined(CONFIG_CPU_CORTEX_M1)
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#define __CM1_REV 0
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#elif defined(CONFIG_CPU_CORTEX_M3)
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#define __CM3_REV 0
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#elif defined(CONFIG_CPU_CORTEX_M4)
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@ -103,6 +105,8 @@ typedef enum {
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#include <core_cm0.h>
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#elif defined(CONFIG_CPU_CORTEX_M0PLUS)
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#include <core_cm0plus.h>
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#elif defined(CONFIG_CPU_CORTEX_M1)
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#include <core_cm1.h>
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#elif defined(CONFIG_CPU_CORTEX_M3)
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#include <core_cm3.h>
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#elif defined(CONFIG_CPU_CORTEX_M4)
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@ -50,7 +50,8 @@
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/* 0xe0000000 -> 0xe00fffff: private peripheral bus */
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/* 0xe0000000 -> 0xe003ffff: internal [256KB] */
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#define _PPB_INT_BASE_ADDR 0xE0000000
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#if defined(CONFIG_CPU_CORTEX_M0) || defined(CONFIG_CPU_CORTEX_M0PLUS)
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#if defined(CONFIG_CPU_CORTEX_M0) || defined(CONFIG_CPU_CORTEX_M0PLUS) || \
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defined(CONFIG_CPU_CORTEX_M1)
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#define _PPB_INT_RSVD_0 0xE0000000
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#define _PPB_INT_DWT 0xE0001000
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#define _PPB_INT_BPU 0xE0002000
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@ -78,7 +79,7 @@
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/* 0xe0040000 -> 0xe00fffff: external [768K] */
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#define _PPB_EXT_BASE_ADDR 0xE0040000
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#if defined(CONFIG_CPU_CORTEX_M0) || defined(CONFIG_CPU_CORTEX_M0PLUS) \
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|| defined(CONFIG_CPU_CORTEX_M23)
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|| defined(CONFIG_CPU_CORTEX_M1) || defined(CONFIG_CPU_CORTEX_M23)
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#elif defined(CONFIG_CPU_CORTEX_M3) || defined(CONFIG_CPU_CORTEX_M4)
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#define _PPB_EXT_TPIU 0xE0040000
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#define _PPB_EXT_ETM 0xE0041000
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