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arch: arm: aarch32: add support for Cortex-M1

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Add support for the ARM Cortex-M1 CPU.

Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
This commit is contained in:
Henrik Brix Andersen 2020-07-26 22:30:30 +02:00 • committed by Maureen Helm
commit e7f51fa918
4 changed files with 20 additions and 8 deletions
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15
arch/arm/core/aarch32/cortex_m/Kconfig
View file

@ -23,6 +23,13 @@ config CPU_CORTEX_M0PLUS
help
This option signifies the use of a Cortex-M0+ CPU
config CPU_CORTEX_M1
bool
select CPU_CORTEX_M
select ARMV6_M_ARMV8_M_BASELINE
help
This option signifies the use of a Cortex-M1 CPU
config CPU_CORTEX_M3
bool
select CPU_CORTEX_M
@ -72,7 +79,7 @@ config CPU_CORTEX_M_HAS_SYSTICK
config CPU_CORTEX_M_HAS_DWT
bool
depends on !CPU_CORTEX_M0 && !CPU_CORTEX_M0PLUS
depends on !CPU_CORTEX_M0 && !CPU_CORTEX_M0PLUS && !CPU_CORTEX_M1
help
This option signifies that the CPU implements the Data Watchpoint and
Trace (DWT) unit specified by the ARMv7-M and above.
@ -96,14 +103,14 @@ config CPU_CORTEX_M_HAS_BASEPRI
config CPU_CORTEX_M_HAS_VTOR
bool
depends on !CPU_CORTEX_M0
depends on !CPU_CORTEX_M0 && !CPU_CORTEX_M1
help
This option signifies the CPU has the VTOR register.
The VTOR indicates the offset of the vector table base
address from memory address 0x00000000. Always present
in CPUs implementing the ARMv7-M or ARMv8-M architectures.
Optional in CPUs implementing ARMv6-M, ARMv8-M Baseline
architectures (except for Cortex-M0, where it is never
architectures (except for Cortex-M0/M1, where it is never
implemented).
config CPU_CORTEX_M_HAS_SPLIM
@ -229,7 +236,7 @@ config ARMV8_M_DSP
This option signifies the use of an ARMv8-M processor
implementation supporting the DSP Extension.
menu "ARM Cortex-M0/M0+/M3/M4/M7/M23/M33 options"
menu "ARM Cortex-M0/M0+/M1/M3/M4/M7/M23/M33 options"
depends on ARMV6_M_ARMV8_M_BASELINE || ARMV7_M_ARMV8_M_MAINLINE
config GEN_ISR_TABLES

4
arch/arm/core/aarch32/swap_helper.S
View file

@ -170,8 +170,8 @@ out_fp_endif:
/* Restore previous interrupt disable state (irq_lock key)
* (We clear the arch.basepri field after restoring state)
*/
#if (defined(CONFIG_CPU_CORTEX_M0PLUS) || defined(CONFIG_CPU_CORTEX_M0)) && \
_thread_offset_to_basepri > 124
#if (defined(CONFIG_CPU_CORTEX_M0PLUS) || defined(CONFIG_CPU_CORTEX_M0) || \
defined(CONFIG_CPU_CORTEX_M1)) && _thread_offset_to_basepri > 124
/* Doing it this way since the offset to thread->arch.basepri can in
* some configurations be larger than the maximum of 124 for ldr/str
* immediate offsets.

4
include/arch/arm/aarch32/cortex_m/cmsis.h
View file

@ -70,6 +70,8 @@ typedef enum {
#define __CM0_REV 0
#elif defined(CONFIG_CPU_CORTEX_M0PLUS)
#define __CM0PLUS_REV 0
#elif defined(CONFIG_CPU_CORTEX_M1)
#define __CM1_REV 0
#elif defined(CONFIG_CPU_CORTEX_M3)
#define __CM3_REV 0
#elif defined(CONFIG_CPU_CORTEX_M4)
@ -103,6 +105,8 @@ typedef enum {
#include <core_cm0.h>
#elif defined(CONFIG_CPU_CORTEX_M0PLUS)
#include <core_cm0plus.h>
#elif defined(CONFIG_CPU_CORTEX_M1)
#include <core_cm1.h>
#elif defined(CONFIG_CPU_CORTEX_M3)
#include <core_cm3.h>
#elif defined(CONFIG_CPU_CORTEX_M4)

5
include/arch/arm/aarch32/cortex_m/memory_map.h
View file

@ -50,7 +50,8 @@
/* 0xe0000000 -> 0xe00fffff: private peripheral bus */
/* 0xe0000000 -> 0xe003ffff: internal [256KB] */
#define _PPB_INT_BASE_ADDR 0xE0000000
#if defined(CONFIG_CPU_CORTEX_M0) || defined(CONFIG_CPU_CORTEX_M0PLUS)
#if defined(CONFIG_CPU_CORTEX_M0) || defined(CONFIG_CPU_CORTEX_M0PLUS) || \
defined(CONFIG_CPU_CORTEX_M1)
#define _PPB_INT_RSVD_0 0xE0000000
#define _PPB_INT_DWT 0xE0001000
#define _PPB_INT_BPU 0xE0002000
@ -78,7 +79,7 @@
/* 0xe0040000 -> 0xe00fffff: external [768K] */
#define _PPB_EXT_BASE_ADDR 0xE0040000
#if defined(CONFIG_CPU_CORTEX_M0) || defined(CONFIG_CPU_CORTEX_M0PLUS) \
|| defined(CONFIG_CPU_CORTEX_M23)
|| defined(CONFIG_CPU_CORTEX_M1) || defined(CONFIG_CPU_CORTEX_M23)
#elif defined(CONFIG_CPU_CORTEX_M3) || defined(CONFIG_CPU_CORTEX_M4)
#define _PPB_EXT_TPIU 0xE0040000
#define _PPB_EXT_ETM 0xE0041000