Commit graph

1061 commits

Author SHA1 Message Date
Andrew Boie
ea201b206f x86: add debug functions for dumping page tables
These turned out to be quite useful when debugging MMU
issues, commit them to the tree. The output format is
virtually the same as gen_mmu_x86.py's verbose output.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2019-08-05 13:25:50 +02:00
Andrew Boie
26dccaabcb x86: reserve room for per-thread page tables
Currently page tables have to be re-computed in
an expensive operation on context switch. Here we
reserve some room in the page tables such that
we can have per-thread page table data, which will
be much simpler to update on context switch at
the expense of memory.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2019-08-05 13:25:50 +02:00
Andrew Boie
76310f6896 x86: make guard pages ro instead of non-present
Has the same effect of catching stack overflows, but
makes debugging with GDB simpler since we won't get
errors when inspecting such regions. Making these
areas non-present was more than we needed, read-only
is sufficient.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2019-08-05 13:25:50 +02:00
Andrew Boie
bd709c7322 x86: support very early printk() if desired
Adapted from similar code in the x86_64 port.
Useful when debugging boot problems on actual x86
hardware if a JTAG isn't handy or feasible.

Turn this on for qemu_x86.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2019-08-02 00:29:21 -07:00
Charles E. Youse
8e437adc42 thread.c: remove vestigial CONFIG_INIT_STACKS cruft
It looks like, at some point in the past, initializing thread stacks
was the responsibility of the arch layer. After that was centralized,
we forgot to remove the related conditional header inclusion. Fixed.

Signed-off-by: Charles E. Youse <charles.youse@intel.com>
2019-07-31 09:15:45 +03:00
Anas Nashif
cb412df725 x86: remove code for interrupt forwarding bug
This only applied to quark_se, so removing it.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2019-07-29 21:30:25 -07:00
Charles E. Youse
f7a0dce636 arch/x86: remove support for CONFIG_REALMODE
We no longer support any platforms that bootstrap from real mode.

Fixes: #17166

Signed-off-by: Charles E. Youse <charles.youse@intel.com>
2019-07-29 21:29:38 -07:00
Andrew Boie
96571a8c40 kernel: rename NANO_ESF
This is now called z_arch_esf_t, conforming to our naming
convention.

This needs to remain a typedef due to how our offset generation
header mechanism works.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2019-07-25 15:06:58 -07:00
Andrew Boie
8a9e8e0cd7 kernel: support log system for fatal errors
We introduce a new z_fatal_print() API and replace all
occurrences of exception handling code to use it.
This routes messages to the logging subsystem if enabled.
Otherwise, messages are sent to printk().

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2019-07-25 15:06:58 -07:00
Andrew Boie
5623637a48 kernel: abolish _default_esf
NANO_ESF parameters may now be NULL, indicating that no
exception frame is available.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2019-07-25 15:06:58 -07:00
Andrew Boie
71ce8ceb18 kernel: consolidate error handling code
* z_NanoFatalErrorHandler() is now moved to common kernel code
  and renamed z_fatal_error(). Arches dump arch-specific info
  before calling.
* z_SysFatalErrorHandler() is now moved to common kernel code
  and renamed k_sys_fatal_error_handler(). It is now much simpler;
  the default policy is simply to lock interrupts and halt the system.
  If an implementation of this function returns, then the currently
  running thread is aborted.
* New arch-specific APIs introduced:
  - z_arch_system_halt() simply powers off or halts the system.
* We now have a standard set of fatal exception reason codes,
  namespaced under K_ERR_*
* CONFIG_SIMPLE_FATAL_ERROR_HANDLER deleted
* LOG_PANIC() calls moved to k_sys_fatal_error_handler()

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2019-07-25 15:06:58 -07:00
Andrew Boie
caa47e6c97 x86: allow user mode to induce kernel oops
Before, attempting to induce a kernel oops would instead
lead to a general protection fault as the interrupt vector
was at DPL=0.

Now we allow by setting DPL=3. We restrict the allowable
reason codes to either stack overflows or kernel oops; we
don't want user mode to be able to create a kernel panic,
or fake some other kind of exception.

Fixes an issue where the stack canary test case was triggering
a GPF instead of a stack check exception on x86.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2019-07-16 18:09:49 -07:00
Ioannis Glaropoulos
85f7aeeced arch: x86: make z_arch_float_disable return -ENOSYS if not supported
For the x86 architecture the z_arch_float_disable() is only
implemented when building with CONFIG_LAZY_FP_SHARING, so we
make z_arch_float_disable() return -ENOSYS when we build with
FLOAT and FP_SHARING but on an x86 platform where
LAZY_FP_SHARING is not supported.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2019-07-10 13:44:02 -07:00
Charles E. Youse
0fb9d3450b arch/x86: move exception.h to ia32/exception.h
This file is currently 32-bit specific. Move it and references to it.

Signed-off-by: Charles E. Youse <charles.youse@intel.com>
2019-07-03 20:01:17 -04:00
Charles E. Youse
3ff2746857 arch/x86: eliminate cache_private.h
This file merely declares external functions referenced only
by ia32/cache.c, so the declarations are inlined instead.

Signed-off-by: Charles E. Youse <charles.youse@intel.com>
2019-07-03 20:01:17 -04:00
Charles E. Youse
589b86f534 arch/x86: remove swapstk.h and references to it
This file was used to generate offsets for host tools that are no
longer in use, so it's removed and the offsets are no longer generated.

Signed-off-by: Charles E. Youse <charles.youse@intel.com>
2019-07-03 20:01:17 -04:00
Charles E. Youse
b4316fef48 arch/x86: eliminate arch/x86/include/asm_inline.h
Over time, this has been reduced to a few functions dealing solely
with floating-point support, referenced only from core/ia32/float.c.
Thus they are moved into that file and the header is eliminated.

Signed-off-by: Charles E. Youse <charles.youse@intel.com>
2019-07-03 20:01:17 -04:00
Charles E. Youse
7c2d7d7b69 arch/x86: move arch/x86/include/mmustructs.h to ia32/mmustructs.h
For now, only the 32-bit subarchitecture supports memory protection.

Signed-off-by: Charles E. Youse <charles.youse@intel.com>
2019-07-03 20:01:17 -04:00
Charles E. Youse
0325a3d972 arch/x86: eliminate include/arch/x86/irq_controller.h
The MVIC is no longer supported, and only the APIC-based interrupt
subsystem remains. Thus this layer of indirection is unnecessary.

This also corrects an oversight left over from the Jailhouse x2APIC
implementation affecting EOI delivery for direct ISRs only.

Signed-off-by: Charles E. Youse <charles.youse@intel.com>
2019-07-02 19:30:00 -04:00
Charles E. Youse
930e6af999 arch/x86: move include/arch/x86/segmentation.h to ia32/segmentation.h
This header is currently IA32-specific, so move it into the subarch
directory and update references to it.

Signed-off-by: Charles E. Youse <charles.youse@intel.com>
2019-07-02 19:30:00 -04:00
Charles E. Youse
dff016b53c arch/x86: move include/arch/x86/arch.h to ia32/arch.h
Making room for the Intel64 subarch in this tree. This header is
32-bit specific and so it's relocated, and references rewritten
to find it in its new location.

Signed-off-by: Charles E. Youse <charles.youse@intel.com>
2019-07-02 19:30:00 -04:00
Charles E. Youse
6f3009ecf0 arch/x86: move include/arch/x86/asm.h to include/arch/x86/ia32/asm.h
This file is 32-bit specific, so it is moved into the ia32/ directory
and references to it are updated accordingly.

Also, SP_ARG* definitions are no longer used, so they are removed.

Signed-off-by: Charles E. Youse <charles.youse@intel.com>
2019-07-02 19:30:00 -04:00
Charles E. Youse
c7bc7a8c86 arch/x86: clean up model-specific register definitions in msr.h
Eliminate definitions for MSRs that we don't use. Centralize the
definitions for the MSRs that we do use, including their fields.

Signed-off-by: Charles E. Youse <charles.youse@intel.com>
2019-07-02 19:30:00 -04:00
Andrew Boie
a3a89ed9d5 x86: only use lfence if x86 bcb config enabled
Work around a testcase problem, where we want to check some
logic for the bounds check bypass mitigation in the common
kernel code. By changing the ifdef to the x86-specific option
for these lfence instructions, we avoid IAMCU build errors
but still test the common code.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2019-06-30 09:22:09 -04:00
Anas Nashif
5b0aa794b2 cleanup: include/: move misc/reboot.h to power/reboot.h
move misc/reboot.h to power/reboot.h and
create a shim for backward-compatibility.

No functional changes to the headers.
A warning in the shim can be controlled with CONFIG_COMPAT_INCLUDES.

Related to #16539

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2019-06-27 22:55:49 -04:00
Anas Nashif
a2fd7d70ec cleanup: include/: move misc/util.h to sys/util.h
move misc/util.h to sys/util.h and
create a shim for backward-compatibility.

No functional changes to the headers.
A warning in the shim can be controlled with CONFIG_COMPAT_INCLUDES.

Related to #16539

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2019-06-27 22:55:49 -04:00
Anas Nashif
9ab2a56751 cleanup: include/: move misc/printk.h to sys/printk.h
move misc/printk.h to sys/printk.h and
create a shim for backward-compatibility.

No functional changes to the headers.
A warning in the shim can be controlled with CONFIG_COMPAT_INCLUDES.

Related to #16539

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2019-06-27 22:55:49 -04:00
Anas Nashif
5eb90ec169 cleanup: include/: move misc/__assert.h to sys/__assert.h
move misc/__assert.h to sys/__assert.h and
create a shim for backward-compatibility.

No functional changes to the headers.
A warning in the shim can be controlled with CONFIG_COMPAT_INCLUDES.

Related to #16539

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2019-06-27 22:55:49 -04:00
Anas Nashif
10291a0789 cleanup: include/: move tracing.h to debug/tracing.h
move tracing.h to debug/tracing.h and
create a shim for backward-compatibility.

No functional changes to the headers.
A warning in the shim can be controlled with CONFIG_COMPAT_INCLUDES.

Related to #16539

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2019-06-27 22:55:49 -04:00
Charles E. Youse
a506aa3dfb arch/x86: remove CONFIG_X86_FIXED_IRQ_MAPPING support
This was only enabled by the MVIC, which in turn was only used
by the Quark D2000, which has been removed.

Signed-off-by: Charles E. Youse <charles.youse@intel.com>
2019-06-25 08:06:43 -04:00
Charles E. Youse
3dc7c7a6ea drivers/interrupt_controller/mvic.c: remove MVIC interrupt controller
The Quark D2000 is the only x86 with an MVIC, and since support for
it has been dropped, the interrupt controller is orphaned. Removed.

Signed-off-by: Charles E. Youse <charles.youse@intel.com>
2019-06-25 08:06:43 -04:00
Charles E. Youse
ef736f77c2 arch/x86: relocate and rename SYS_X86_RST_* constants
These constants do not need global exposure, as they're only
referenced in the reboot API implementation. Also their names
are trimmed to fit into the X86-arch-specific namespace.

Signed-off-by: Charles E. Youse <charles.youse@intel.com>
2019-06-24 07:46:24 -07:00
Charles E. Youse
4bdbd879ef arch/x86: remove old PRINTK() debugging macro
This appears to date all the way back to the initial import
and is used in exactly one place if DEBUG is on. Removed.

Signed-off-by: Charles E. Youse <charles.youse@intel.com>
2019-06-24 07:46:24 -07:00
Charles E. Youse
2835c22985 arch/x86: used fixed initial EFLAGS on thread creation
Previously the existing EFLAGS was used as a base which was
then manipulated accordingly. This is unnecessary as the bits
preserved contain no useful state related to the new thread.

Signed-off-by: Charles E. Youse <charles.youse@intel.com>
2019-06-24 07:46:24 -07:00
Anas Nashif
f2cb20c772 docs: fix misspelling across the tree
Found a few annoying typos and figured I better run script and
fix anything it can find, here are the results...

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2019-06-19 15:34:13 -05:00
David B. Kinder
2aebc980e2 doc: fix Kconfig misspellings
Fix misspellings in Kconfig files missed during regular reviews.

Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
2019-06-18 15:07:52 -04:00
Charles E. Youse
1444ee970e arch/x86: reorganize core source files
Create source directory for IA32-subarch specific files, and move
qualifying files to that subdirectory.

Signed-off-by: Charles E. Youse <charles.youse@intel.com>
2019-06-17 16:31:37 -04:00
Charles E. Youse
8f14b2ed86 arch/x86: split CMakeLists.txt into subarch-specific files
Separate common, ia32-specific, and x64-specific into separate files.

Signed-off-by: Charles E. Youse <charles.youse@intel.com>
2019-06-17 16:31:37 -04:00
Charles E. Youse
d2b33a486b arch/x86: split Kconfig files by sub-architecture
Separate common, ia32 (32-bit) and x64 (64-bit long mode) options.

Signed-off-by: Charles E. Youse <charles.youse@intel.com>
2019-06-17 16:31:37 -04:00
Ioannis Glaropoulos
d840d1cbb5 arch: implement arch-specific float disable routines
This commit adds the architecture-specific implementation
of k_float_disable() for ARM and x86.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2019-06-12 09:17:45 -07:00
Charles E. Youse
ba516e8ea8 arch/x86: do not redefine MSR regs in crt0.S
The real-mode startup code is trivially changed to refer to MSR
definitions in include/arch/x86/msr.h, rather than its ad-hoc ones.

Signed-off-by: Charles E. Youse <charles.youse@intel.com>
2019-06-08 15:41:36 -04:00
Charles E. Youse
0e166fa2a8 arch/x86: move MSR definitions to include/arch/x86/msr.h
Light reorganization. All MSR definitions and manipulation functions
are consolidated into one header. The names are changed to use an
X86_* prefix instead of IA32_* which is misleading/incorrect.

Signed-off-by: Charles E. Youse <charles.youse@intel.com>
2019-06-08 15:41:36 -04:00
Charles E. Youse
6aedb6ff1a arch/x86: disable i8259 in crt0.S
drivers/interrupt_controller/i8259.c is not a driver; it exists
solely to disable the i8259s when the configuration calls for it.
The six-byte sequence to mask the controllers is moved to crt0.S
and the pseudo-driver is removed.

Signed-off-by: Charles E. Youse <charles.youse@intel.com>
2019-06-08 15:41:36 -04:00
Charles E. Youse
4c63e29aec arch/x86: drivers/display: add framebuffer driver w/ multiboot support
A basic display driver is added for a generic 32-bpp framebuffer.
Glue logic is added to the x86 arch to request the intitialization
of a linear framebuffer by the Multiboot loader (GRUB) and connect
it to this generic driver.

Signed-off-by: Charles E. Youse <charles.youse@intel.com>
2019-06-06 10:47:29 -07:00
Charles E. Youse
a1a3a4fced arch/x86: add support for Multiboot boot information structure
When booting using GRUB, some useful information about the environment
is given to us via a boot information structure. We've not made any
use of this information so far, but the x86 framebuffer driver will.

A skeletal definition of the structure is given, and provisions are
made to preserve its contents at boot if the configuration requires it.

Signed-off-by: Charles E. Youse <charles.youse@intel.com>
2019-06-06 10:47:29 -07:00
Anas Nashif
76d9d7806d x86: remove unused and x86 only latency benchmark
We do have a multi-architecture latency benchmark now, this one was x86
only, was never used or compiled in and is out-dated.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2019-06-03 09:42:00 -07:00
Charles E. Youse
50c71e6043 arch/x86: CONFIG_BOOTLOADER_UNKNOWN renamed to CONFIG_X86_MULTIBOOT
The only use of the BOOTLOADER_UNKNOWN config option is on x86, where
it controls whether a multiboot header is embedded in the output.
This patch renames the option to be more descriptive, and makes it
an x86-specific option, rather than a Zephyr top-level option.

This also enables X86_MULTIBOOT by default, since the header only
occupies 12-16 bytes of memory and is (almost always) harmless.

Signed-off-by: Charles E. Youse <charles.youse@intel.com>
2019-05-08 14:49:19 -04:00
Ioannis Glaropoulos
873dd10ea4 kernel: mem_domain: update name/doc of API function for partition add
Update the name of mem-domain API function to add a partition
so that it complies with the 'z_' prefix convention. Correct
the function documentation.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2019-05-02 11:37:38 -04:00
Ioannis Glaropoulos
53f0f277b0 arch: x86: mmu: typo fixes
Typo fixes in functions' documentation.

Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
2019-05-02 11:37:38 -04:00
Paul Sokolovsky
ec1ffc8bcf arch: x86: fatal: If possible, print thread name in crash dump
It's relatively hard to figure out what thread a crash happens in
from the crash dump. E.g, it's usually not immediately possible to
find it out from linker map due to the fact that static symbols are
not there (https://sourceware.org/bugzilla/show_bug.cgi?id=16566).

So, try to do it as easy if possible, by just printing thread name
in a dump, if thread names are enabled at all.

Signed-off-by: Paul Sokolovsky <paul.sokolovsky@linaro.org>
2019-04-24 09:01:07 -07:00