move misc/__assert.h to sys/__assert.h and
create a shim for backward-compatibility.
No functional changes to the headers.
A warning in the shim can be controlled with CONFIG_COMPAT_INCLUDES.
Related to #16539
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
move atomic.h to sys/atomic.h and
create a shim for backward-compatibility.
No functional changes to the headers.
A warning in the shim can be controlled with CONFIG_COMPAT_INCLUDES.
Related to #16539
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
move tracing.h to debug/tracing.h and
create a shim for backward-compatibility.
No functional changes to the headers.
A warning in the shim can be controlled with CONFIG_COMPAT_INCLUDES.
Related to #16539
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Under FP shared registers mode (CONFIG_FP_SHARING=y),
a thread's user_options flag is checked during swap and
during stack fail check. Therefore, in k_float_disable()
we want to ensure that a thread won't be swapped-out with
K_FP_REGS flag cleared but still FP-active (CONTROL.FPCA
being not zero). To ensure that we temporarily disable
interrupts.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit reworks the ARM stack fail checking, under FP
Sharing registers mode, to account for the right width of
the MPU stack guard.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
For threads that appear to be FP-capable (i.e. with K_FP_REGS
option flag set), we configure a wide MPU stack guard, if we
build with stack protection enabled (CONFIG_MPU_STACK_GUARD=y).
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
When an FP capable thread (i.e. with K_FP_REGS option)
transitions into user mode, we want to allocate a wider
MPU stack guard region, to be able to successfully detect
overflows of the privilege stack during system calls. For
that we also need to re-adjust the .priv_stack_start pointer,
which denotes the start of the writable area of the privilege
stack buffer.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
When an FP capable thread is created (i.e. with K_FP_REGS
option) we want to allocate a wider MPU stack guard region,
to be able to successfully detect stack overflows. For that
we also need to re-adjust the values that will be passed to
the thread's stack_info .start and .size parameters.
applicable) for a thread which intends to use the FP services.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Compilers (at least gcc and clang) already provide definitions to
create standard types and their range. For example, __INT16_TYPE__ is
normally defined as a short to be used with the int16_t typedef, and
__INT16_MAX__ is defined as 32767. So it makes sense to rely on them
rather than hardcoding our own, especially for the fast types where
the compiler itself knows what basic type is best.
Using compiler provided definitions makes even more sense when dealing
with 64-bit targets where some types such as intptr_t and size_t must
have a different size and range. Those definitions are then adjusted
by the compiler directly.
However there are two cases for which we should override those
definitions:
* The __INT32_TYPE__ definition on 32-bit targets vary between an int
and a long int depending on the architecture and configuration.
Notably, all compilers shipped with the Zephyr SDK, except for the
i586-zephyr-elfiamcu variant, define __INT32_TYPE__ to a long int.
Whereas, all Linux configurations for gcc, both 32-bit and 64-bit,
always define __INT32_TYPE__ as an int. Having variability here is
not welcome as pointers to a long int and to an int are not deemed
compatible by the compiler, and printing an int32_t defined with a
long using %d makes the compiler to complain, even if they're the
same size on 32-bit targets. Given that an int is always 32 bits
on all targets we might care about, and given that Zephyr hardcoded
int32_t to an int before, then we just redefine __INT32_TYPE__ and
derrivatives to an int to keep the peace in the code.
* The confusion also exists with __INTPTR_TYPE__. Looking again at the
Zephyr SDK, it is defined as an int, even even when __INT32_TYPE__ is
initially a long int. One notable exception is i586-zephyr-elf where
__INTPTR_TYPE__ is a long int even when using -m32. On 64-bit targets
this is always a long int. So let's redefine __INTPTR_TYPE__ to always
be a long int on Zephyr which simplifies the code, works for both
32-bit and 64-bit targets, and mimics what the Linux kernel does.
Only a few print format strings needed adjustment.
In those two cases, there is a safeguard to ensure the type we're
enforcing has the right size and fail the build otherwise.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
This commit aligns the programming of the privileged stack MPU
guard with that of the default stack guard (i.e of supervisor
threads). In particular:
- the guard is programmed BELOW the address indicated in
arch.priv_stack_start; it is, therefore, similar to the
default guard that is programmed BELOW stack_info.start.
An ASSERT is added to confirm that the guard is programmed
inside the thread privilege stack area.
- the stack fail check is updated accordningly
- arch.priv_stack_start is adjusted in arch_userspace_enter(),
to make sure we account for a (possible) guard requirement,
that is, if building with CONFIG_MPU_STACK_GUARD=y.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit re-organizes the macro definitions in arch.h for
the ARM architecture. In particular, the commit:
- defines the minimum alignment requirement for thread stacks,
that is, excluding alignment requirement for (possible)
MPU stack guards.
- defines convenience macros for the MPU stack guard align and
size for threads using the FP services under Shared registers
mode (CONFIG_FP_SHARING=y). For that, a hidden Kconfig option
is defined in arch/arm/core/cortex_m/mpu/Kconfig.
- enforces stack alignment with a wide MPU stack guard (128
bytes) under CONFIG_FP_SHARING=y for the ARMv7-M architecture,
which requires start address alignment with power-of-two and
region size.
The commit does not change the amount of stack that is reserved
with K_THREAD_STACK_DEFINE; it only determines the stack buffer
alignment as explained above.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Found a few annoying typos and figured I better run script and
fix anything it can find, here are the results...
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This commit adds the architecture-specific implementation
of k_float_disable() for ARM and x86.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
When building without support for user mode (CONFIG_USERSPACE=n)
we need to correct the starting address of the MPU Guard, before
passing it to the function that evaluates whether a stack
corruption has occurred. The bug was introduced by commit
(60bae5de38) in
PR-13619, where the start address of the MPU guard was properly
corrected, but the guard start at the corresponding stack-fail
check was not adjusted accordingly.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Change removes tracing hooks before threads are initialized
and thread switched out hook for ARM before first time switching
to main thread.
Signed-off-by: Marek Pieta <Marek.Pieta@nordicsemi.no>
ip register holds the stack_info.size (it is passed as argument
into z_arch_user_mode_enter(.)). We trust that the value of
stack_info.size contains the accurate size of the writable
stack buffer, above stack_info.start (as specified in kernel.h).
Therefore, we do not need to subtract any bytes for the MPU
stack guard. This allows us to clean-up one more occurrence of
CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT in userspace.S.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
arm_core_mpu_enable() and arm_core_mpu_disable() functions are
effectively static functions, only used in the drivers for ARM
and NXP MPU, therefore, we do not need to expose them in the
arm_core_mpu_dev.h header.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
arm_core_mpu_dev.h is an internal API, and is not supposed to
be directly called by kernel / application functions, therefore,
we can move it inside arch/arm/core/cortex_m/mpu directory.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Add Kconfig options:
- ARM_FIRMWARE_USES_SECURE_ENTRY_FUNCS
- ARM_ENTRY_VENEERS_LIB_NAME
Use these to link the veneers lib into the Non-Secure Firmware when
needed.
Also, make the path passed to the linker absolute to make it work with
makefiles.
Signed-off-by: Øyvind Rønningstad <oyvind.ronningstad@nordicsemi.no>
Rename function _PlatformInit() to z_platform_init() to
comply with naming conventions.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT is taken into
account when allocating the area for the interrupt stack
using the K_THREAD_STACK_DEFINE macro. Therefore, we can
simplify how the top of the stack is derived during the
initialization of the system, by removing one more
occurrence of CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
For architectures with custom swap to main, currently:
- arm
- posix
we are now using K_THREAD_STACK_SIZEOF macro to pass the
main thread stack size to z_arch_switch_to_main_thread().
This does not introduce any behavioral changes for posix;
the K_THREAD_STACK_SIZEOF() simply returns the sizeof()
the stack object. For Arm, this allows us to clean-up one
more occurence of CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT
in kernel_arch_func.h.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
When in Sharing Floating Point Services mode we want to
dynamically save and restore the FP registers in thread
context switch, depending on whether the swapped-in and
swapped-out threads are currently using the FP registers.
This commit adds this functionality to the ARM context
switch mechanism. The logic consists of inspecting the
corresponding status flag (present in thread.arch.mode)
to decide whether to save or restore the FP registers.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Only a single bit of the 4-byte internal (thread.arch) status
variable 'mode' is currently used, when we build with User mode
support (CONFIG_USERSPACE=y). In this commit we extend the usage
of 'mode' variable, adding an additional bit-flag to track the
status of the floating point context in a particular thread,
i.e. to track whether FP context is active or not. The status
bit is meant to be used in context-switch, to restore the FP
register context when required.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
The initial carved stack frame only needs to contain the basic
stack frame (state context), because:
- under No/Unshared FP Services mode no FP context is stacked.
- under FP Sharing mode FP context is cleared upon thread
creation.
This commit removes the unnecessary stacking of the FP context
during thread initialization. This results in reduced stack
usage under the Shared FP Services mode (CONFIG_FP_SHARING=y).
Also, we do not need to initialize the FPSCR, because there is
no FP stack frame carved.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
In FP Sharing mode we enable both automatic and lazy state
preservation of the FP context. This configuration improves
interrupt latency. Under this configuration the FP registers
will only be stacked when the thread is swapped out during
context-switch. Before jumping to main() we clear the FPCA
flag of the CONTROL register, so the FP context can be used
by the main thread.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
The compiler generates errors of the form
error: "CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT" is not defined,
evaluates to 0 [-Werror=undef]
when -Wundef is used and the config option was turned off. Change
check to if defined().
Signed-off-by: Bradley Bolen <bbolen@lexmark.com>
The compiler generates errors of the form
error: "CONFIG_ZERO_LATENCY_IRQS" is not defined, evaluates to 0
[-Werror=undef]
when -Wundef is used and the config option was turned off. Change
check to if defined().
Signed-off-by: Bradley Bolen <bbolen@lexmark.com>
The compiler generates errors of the form
error: "CONFIG_IRQ_OFFLOAD" is not defined, evaluates to 0
[-Werror=undef]
when -Wundef is used and the config option was turned off. Change
check to if defined().
Signed-off-by: Bradley Bolen <bbolen@lexmark.com>
The compiler generates errors of the form
error: "CONFIG_USERSPACE" is not defined, evaluates to 0 [-Werror=undef]
when -Wundef is used and the config option was turned off. Change
check to if defined().
Signed-off-by: Bradley Bolen <bbolen@lexmark.com>
Make _get_num_regions() return a constant representing the
number of HW MPU regions, defined in DTS, if such define
is available. This removes the need of evaluating the
number of regions at run-time. The ASSERT in arm_mpu_init()
is expanded, to cover that case, where the number of
regions is taken from DTS.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
In z_NanoFatalErrorHandler() we want to print the name
of the thread that has faulted, when building with
CONFIG_THREAD_NAME. This commit adds this functionality
for the Arm architecture.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
The typeof definitions in tz.h and cmse.h are not required
any more, as the ARM GCC toolchain intrinsics have been
modified to use __typeof__ directly.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
In kernel_arch_init() we initialize the ARM core (interrupt
setup, fault init, etc.) so we can also move z_clearfaults()
in the same function and skip invoking it in the SoC init
functions.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
With -O0 optimizion, gcc compiler doesn't inline "static inline"
marked function. So when function call return from function
set_and_switch_to_psp which is to switch sp from MSP to PSP, the
ending "mov sp, r7" instruction will overwrite the just updated
sp value(PSP) with the beginning stack pointer(should be MSP)
stored in r7 register, so the switch doesn't happen. And it causes
unpredictable problems in the initialization process, the backward
analysis for this problem can be found on Github issue #15794.
Fixes: #15794.
Signed-off-by: Wentong Wu <wentong.wu@intel.com>
This commit fixes a build error, when building with
CONFIG_ARM_SECURE_FIRMWARE=y. The error was introduced
in #15930 (6f19d0), where we added internal structure
to the exception stack frame struct.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
When compiling the kernel with CONFIG_SYS_CLOCK_TICKS_PER_SEC=0,
the CONFIG_SYS_CLOCK_EXISTS internal variable is unset.
This completely disables timer handling in the kernel, but a couple of
spots missed the required conditional compilation.
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
The ARM Cortex-M Exception Stack Frame (ESF) may consist of
several stack frame contexts (basic state context, additional
state context, FP context, etc.). To reflect these structural
properties, this commit re-factors the ESF, splitting out the
basic stack frame, holding the state context, into its own
struct container. The commit does not introduce behavioral
changes.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
When some header are included into C++ source file, this kind of
compilations errors are generated:
error: invalid conversion from 'void*'
to 'u32_t*' {aka 'unsigned int*'} [-fpermissive]
Signed-off-by: Benoit Leforestier <benoit.leforestier@gmail.com>
Initialize the Floating Point Status and Control Register when in
Unshared FP Registers mode (In Shared FP Registers mode, FPSCR is
initialized at thread creation for threads that make use of the FP).
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit removes the activation of the FP context
in ARM system boot. There is no need to do this, since
the FP context will be activated in the presence of
floating point instructions. We update the reference
documentation accordingly.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Under Unshared FP register mode we are not sharing the
FP context among different threads, so we do not need to
include the FP high registers bank in the thread.arch
container.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Under Unshared FP register mode we are not stacking the
FP context in exception entries, so we do not need to
include the FP registers bank in the exception stack
frame structure.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Under unshared FP registers mode the FP register bank is
meant to be used by a single thread context. Therefore,
there is no need for automatic stacking of the FP register
bank at exception entries, or context switch, as the
registers are not expected to be shared among multiple
contexts.
Under unshared FP registers mode we only need to clear the
FPSCR register once, before jumping to main(). However, we
initialize the FPSCR already at boot in case FP operations
need to be performed during boot.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
In ARM builds with FP services (CONFIG_FLOAT=y) but without user
mode support (CONFIG_USERSPACE=n) we do not need and should not
enable full-access to the FP co-processor. Instead, we should
enabled access by privileged code only.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Update the name of mem-domain API function to add a partition
so that it complies with the 'z_' prefix convention. Correct
the function documentation.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
When performing thread context-switch it is not necessary to
have IRQs locked while saving the current thread's callee-saved
(and possibly floating point) registers. We only need to lock
the interrupts when accessing the thread ready queue cache.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit renames the symbol CPU_HAS_SYSTICK to
CPU_CORTEX_M_HAS_SYSTICK, to look similar to all
other CPU_CORTEX_M_HAS_ options, and moves the
K-config symbol definition from arm/core/Kconfig to
arm/core/cortex_m/Kconfig.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
ARM SysTick timer is implemented by default in ARMv7-M
and Mainline ARMv8-M processors, so we include the
corresponding Kconfig symbol in arch/arm/core/cortex-M/Kconfig
and remove the selections from the Cortex-M SOCs.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
The struct _caller_saved is not used. Most architectures put
automatically the registers onto stack, in others architectures the
exception code does it.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
The struct _kernel_ach exists only because ARC' s port needed it, in
all other ports this was defined as an empty struct. Turns out that
this struct is not required even for ARC anymore, this is a legacy
code from nanokernel time.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
The nxp mpu uses the logical OR of access permissions when multiple
region descriptors apply to a given memory access. This means that we
must partition the sram into two non-overlapping regions to implement
the mpu stack guard. This partitioning gets reconfigured at every
context switch, and if an interrupt occurs during this time, it can
cause a fault because we do not have a valid mpu region descriptor for
the sram.
This scenario was observed on frdm_k64f in tests/posix/common before
commit 2895da02a4, which changed timing.
In this case, we couldn't even print fault information to the console
and the hardware would reset. It looked a lot like a watchdog reset,
unless you attached a debugger to see the fault.
A similar problem was fixed in commit
ec424b7a45, but this change temporarily
disabled the mpu.
Fix both cases by locking interrupts during the critical sections, as
this is more secure than disabling the mpu.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Update the files which contain no license information with the
'Apache-2.0' SPDX license identifier. Many source files in the tree are
missing licensing information, which makes it harder for compliance
tools to determine the correct license.
By default all files without license information are under the default
license of Zephyr, which is Apache version 2.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This macro is slated for complete removal, as it's not possible
on arches with an MPU stack guard to know the true buffer bounds
without also knowing the runtime state of its associated thread.
As removing this completely would be invasive to where we are
in the 1.14 release, demote to a private kernel Z_ API instead.
The current way that the macro is being used internally will
not cause any undue harm, we just don't want any external code
depending on it.
The final work to remove this (and overhaul stack specification in
general) will take place in 1.15 in the context of #14269Fixes: #14766
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Rename reserved function names in arch/ subdirectory. The Python
script gen_priv_stacks.py was updated to follow the 'z_' prefix
naming.
Signed-off-by: Patrik Flykt <patrik.flykt@intel.com>
Rename reserved function names in drivers/ subdirectory. Update
function macros concatenatenating function names with '##'. As
there is a conflict between the existing gpio_sch_manage_callback()
and _gpio_sch_manage_callback() names, leave the latter unmodified.
Signed-off-by: Patrik Flykt <patrik.flykt@intel.com>
This commit initializes the thread.mode variable, right before
dropping thread privilege level to user mode. This is required,
as we need to know the privilege level of the thread, in case
we need to context-switch it -out and -in again (e.g. in case
an interrupt triggers a context-switch).
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
The arch.mode status flag is always inline with the actual
thread execution privilege leve. Therefore, we do not need
to be saving-off the thread's mode every time we intend to
context switch-out the thread.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit updates the thread.mode variable, in system
calls, whenever we modify the execution privilege level.
We need to do this, in order to be able to properly handle
context-switching triggered by ISRs, while doing the system
calls. The commit ensures that a context-switch, triggered
by an ISR during or after,a system call will preserve the
right privilege level.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
MISRA defines a serie of essential types, boolean, signed/unsigned
integers, float, ... and operations must respect these essential types.
MISRA-C rule 10.1
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
BIT macro uses an unsigned int avoiding implementation-defined behavior
when shifting signed types.
MISRA-C rule 10.1
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
This adds a compiler option -fno-inline for code coverage on
architectures which supports doing code coverage. This also
modifies the ALWAYS_INLINE macro to not do any inlining. This
needs to be done so code coverage can count the number of
executions to the correct lines.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Field stack_info.size is supposed to hold the actual writable
thread stack area, above what is pointed to by stack_info.start.
Therefore, in all MPU architectures we can program the Thread
Stack MPU region as starting from thread->stack_obj and with
size equal to stack_info.size plus the (possible) difference
between stack_obj and stack_info.start.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Consider a stack buffer at address 0x10000 with size 1024.
If a thread is created with this stack object, the resulting
fields in thread.stack_info ended up being a base address of
0x10020 with size 1024. The guard size needed to be subtracted
from the size in order for the bounds to be correct.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
FPU's control and status register (FPCSR) for a thread is not
initialized. Random values are written to this register and this leads
to failure on fp_sharing test.
FPCSR register is set to 0 according to the value of FPDSCR.
Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
Fix the type of struct field index to int, to avoid
loss of precision, in case the variable holds the value
-EINVAL (in the case of errors in MPU configuration).
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
In arm_core_mpu_mem_partition_config_update() we must fix the
index value of the start of the for loop, to address the case
when dynamic MPU regions are programmed in index values lower
than static_regions_num. (This might occur in ARMv8-M MPU,
depending on the order of programming the map of the
dynamic regions in run-time). We introduce function
_get_dyn_region_min_index(), and provide the implementation in
arm_mpu_v8_internal.h and arm_mpu_v7_internal.h (trivial).
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
In this commit we fix the implementation of internal function
_mpu_buffer_validate(), so it can work in the presence of a
security attribution unit (SAU, or IDAU). The fast validation
based on the CMSE address range check intrinsic is performed
first: if it fails, then a second, MPU-only check is performed
for ARMV8-M platforms that have TEE capabilities (i.e. SAU/IDAU
units).
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Enhance the documentation for internal ARMv8-M MPU
function _mpu_buffer_validate().
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit adds an explanatory comment in ARM __swap()
function, stressing when, exactly, context-switch is
expected to occur, when we pend the PendSV exception.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
The ARM Cortex-M 321 application note is stressing that if
we disable interrupts by executing CPSID i(f), or by MSR
instructions (on PRIMASK, FAULTMASK registers), there is no
requirement to add barrier instructions after disabling
interupts. However, in ARMv7-M (and ARMv8-M Mainline) we use
BASEPRI, instead. Therefore, if we need the effect of disabling
interrupts to be recongnized immediately we should add barrier
instructions. This commit adds DSB and ISB barriers when
disabling interrupt using BASEPRI in the generic
arm _irq_lock() function as well as in the PendSV handler,
where we need to access kernel globals right after the interrups
are disabled.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
The clang ARM assembler is a bit stricter than GNU as. Change mov to
movs for ARMv6 case of z_arch_switch_to_main_thread.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit partially reverts the changes introduced in
(bbe1a19786), where the PSP
modification, the interrupt enabling, and the branch to main
thread were refactored in C functions. This introduced an issue
with stack usage when compiling without any optimization.
Reverting to use assembly functions to jump to main thread
ensures, now, that the pointer to main() is preserved intact
while changing the PSP and passed correctly to z_thread_entry().
Fixes#14471.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit simply moves the MPU re-programming of
dynamic regions during initialization to occur right
before switching PSP to the main thread stack. As a
result, the MPU re-programming will execute using
the interrupt stack. No functional changes are
introduced.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
The clang ARM assembler is a bit stricter than GNU as, make a few
changes so things build with both
Signed-off-by: Peter Smith <peter.smith@linaro.org>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Architecture defconfigs are not used anymore and are stale. Remove them
to avoid confusion.
Related to #14442
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Update reserved function names starting with one underscore, replacing
them as follows:
'_k_' with 'z_'
'_K_' with 'Z_'
'_handler_' with 'z_handl_'
'_Cstart' with 'z_cstart'
'_Swap' with 'z_swap'
This renaming is done on both global and those static function names
in kernel/include and include/. Other static function names in kernel/
are renamed by removing the leading underscore. Other function names
not starting with any prefix listed above are renamed starting with
a 'z_' or 'Z_' prefix.
Function names starting with two or three leading underscores are not
automatcally renamed since these names will collide with the variants
with two or three leading underscores.
Various generator scripts have also been updated as well as perf,
linker and usb files. These are
drivers/serial/uart_handlers.c
include/linker/kobject-text.ld
kernel/include/syscall_handler.h
scripts/gen_kobject_list.py
scripts/gen_syscall_header.py
Signed-off-by: Patrik Flykt <patrik.flykt@intel.com>
The commit adds an __ASSERT statement when configuring
the ARMv8-M build-in stack guard for supervisor thread
stack overflow protection, to catch the case when the
stack_info.start does not point to the beginning of the
thread stack allocated area, pointed by stack_obj.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit does the following:
- moves the reservation of the area for local thread data
inside the arch-specific _new_thread() function,
- aligns the end of the thread's stack with the granularity
of the MPU, already at thread's initialization, moving it
out of userspace_enter() function. In this way, the local
thread data are stored inside the thread stack area that
is, later, assigned unprivileged RW permissions (if thread
enters user mode).
- passes the right thread stack size information to function
_new_thread_init(), which stores it into stack_info.start.
As a result, the whole usable User Thread stack area (i.e.
excluding a possible guard area) falls inside the region
programmed as unprivileged RW, during context-switch.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Appears within a menu that already has 'depends on ARM_SECURE_FIRMWARE'.
'depends on FOO' on a menu will add 'depends on FOO' to each item within
it. 'if FOO' work similarly.
Tip: When adding a symbol, check its dependencies in the menuconfig
('ninja menuconfig', then / to jump to the symbol). The menuconfig also
shows how the file with the symbol got included, so if you see
duplicated dependencies, it's easy to hunt down where they come from.
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
- The ARC CPU_HAS_MPU dependencies were added within the menu
menu "ARCH MPU Options"
depends on CPU_HAS_MPU
(arch/arc/core/mpu/Kconfig is source'd within it).
- The ARM CPU_HAS_MPU dependencies were redundantly added by
if CPU_HAS_MPU
source "arch/arm/core/cortex_m/mpu/Kconfig"
endif
and by some 'depends on CPU_HAS_MPU' within that file. Remove the
'depends on' and move the 'if' into the file instead.
Tip: Jump to symbols with '/' in the menuconfig and press '?' to check
their dependencies. If there are duplicated dependencies, the
'included via ...' path can be handy to discover where they are added.
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
Refactor internal ARM v7m and v8m MPU region re-programming
functions to take as argument a pointer to k_mem_partition
objects, instead of the object itself.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Refactor internal NXP MPU region re-programming functions
to take as argument a pointer to k_mem_partition objects,
instead of the object itself.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit refactors the MPU region re-programming functions,
to take as argument an array of pointers to memory partition
structures, instead of the whole array of the partitions. In
this way the stack usage can be minimized, if the actual
partition information is kept in statically allocated memory.
instead of the map itself.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
The "ARM Cortex-M options" menu is already within a 'if CPU_CORTEX_M',
so no need to put 'depends on CPU_CORTEX_M' on it.
Tip: Jump to symbols with '/' in the menuconfig and press '?' to check
their dependencies. If there are duplicated dependencies, the
'included via ...' path can be handy to discover where they are added.
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
Based on the definition of _ARCH_THREAD_STACK_DEFINE() macro
for ARM, the MPU Stack Guard region is placed inside the
allocated stack object, only if
CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT and CONFIG_USERSPACE
are both set. For ARM stack objects, allocated using the
_ARCH_THREAD_STACK_DEFINE() macro, such as the threads' stacks
and the interrupt stack, the above must be reflected on how we
set the initial start of the stacks.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
On x86, if a supervisor thread belonging to a memory domain
adds a new partition to that domain, subsequent context switches
to another thread in the same domain, or dropping itself to user
mode, does not have the correct setup in the page tables.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This commit introduces a generic arch/arm function to evaluate
thread stack corruption. The function shall be used upon
occurrence of MemManage and Bus Faults.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit adds an explanatory note in the places
where we manually adjust the PSP after stacking Bus
and MemManage errors, stressing that this is due to
the fact that interrupt tail-chaining cannot always
be guaranteed by the processor.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
The commit removes a redundant check for imprecise bus fault,
when a precise bus fault has occurred, now that we have
re-worked the BusFault handler to iterate through all possible
bus errors.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit reworks the logic, based on which we assess
thread stack corruptions upon BusFault exceptions triggered
by the NXP MPU module. BusFaults rely on calling external
function to assess whether a thread stack corruption due to
overflow has occurred. Upon detection of stack corruption,
the current stack pointer is manually adjusted upwards, to
prevent un-stacking errors from firing up upon returning from
the exception.
Additionally, the commit allows to be checking for all different
types of BusFault occurrences that are reported through BFSR,
without stopping after having spotted the first BusFault type.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit reworks the logic, based on which we assess
thread stack corruptions upon MemManageFault exceptions.
Furthermore, it takes out all kernel-related logic and relies
on calling external function 'evaluate_thread_stack_corruption'
to assess whether a thread stack overflow has occurred. Upon
detection of stack corruption, the current stack pointer is
manually adjusted upwards, to prevent un-stacking errors from
firing up upon returning from the exception.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit improves the debug message on UsageFaults
related to Stack overflow, stating that the context
area is not valid. An inline comment is added, with
more detailed explanation.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit fixes two Constant Expression Result errors,
in the NXP MPU driver due to incompatible integer types.
Fixes#13836.
Fixes#13865.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit fixes several essential inline comments in the
core assembly code for ARM, improving code readability.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit applies the same fixes, concering the Constant
Expression Result errors identified in the ARMv7-M and the
NXP MPU drivers, into the ARMv8-M MPU implementation.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit fixes two Constant Expression Result errors,
in the ARMv7-M MPU driver due to incompatible integer types.
Fixes#13844.
Fixes#13854.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit aligns the implementation of arm_core_mpu_disable()
function in NXP MPU with the implementation in the ARM MPU
module, by introducing a Data Memory Barrier, (DMB) instead of
a DSB instruction. This is in accordance with the ARM guidelines
of using the memory protection unit.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This is an integral part of userspace and cannot be used
on its own. Fold into the main userspace configuration.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Instead of having to enable ramfunc support manually, just make it
transparently available to users, keeping the MPU region disabled if not
used to not waste a MPU region. This however wastes 24 bytes of code
area when the MPU is disabled and 48 bytes when it is enabled, and
probably a dozen of CPU cycles during boot. I believe it is something
acceptable.
Note that when XIP is used, code is already in RAM, so the __ramfunc
keyword does nothing, but does not generate an error.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
The linker file defines the __ramfunc_ram_size symbols to get the size
of the __ramfunc_ram section. Use that instead of computing the value at
runtime from the start and end symbols. This saves 16 bytes of code with
CONFIG_RAM_FUNCTION=y.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Using __ramfunc to places a function in RAM instead of Flash.
Code that for example reprograms flash at runtime can't execute
from flash, in that case must placing code into RAM.
This commit create a new section named '.ramfunc' in link scripts,
all functions has __ramfunc keyword saved in thats sections and
will load from flash to sram after the system booted.
Fixes: #10253
Signed-off-by: qianfan Zhao <qianfanguijin@163.com>
This commit fixes a bug that was always propagating the
default error reason (_NANO_ERR_HW_EXCEPTION) to the
system fatal error handler for (strictly) Secure and
for Non-Secure FW builds on ARMv8-M.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Include the EXC_RETURN payload flag macro definitions into
compilation when building for Non-Secure firmware, too.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit fixes a bug for ARM builds with no USERSPACE support
where the MPU stack guard had been erroneously placed, i.e. not
at the beginning of the stack object. This was eating 32-bytes
off of the thread stack. In addition to that, the commit adds a
usefull ASSERT statement for builds with USERSPACE, which checks
that the start of the guard matches the beginning of the entire
stack object.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Its possible that memcpy is marked to check that a NULL value is passed
to it. The instance of memcpy in relocate_vector_table its valid that
we're are copying to 0/NULL. So supress the possible warning generated
by gcc -Wnonnull.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
With this commit we clear the BusFault Status Register error
bits, after processing the fault, for all ARM architecture
variants and implementations (not only for ARMv8-M mainline).
That is a fix, since the bits are sticky in the ARMv7-M
variants, as well. The commit fixes, additionally, a typo
in the spelling of BFSR.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit adds the logic to indicate that a Non-Secure fault
exception has been triggered due to a processor fault that has,
in fact, occurred in the Secure state.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit fixes the way we determine where the stacked
frame lies for (strictly) ARMv8-M Non-Secure firmware. It
introduces no changes to the default ARMv8-M behavior (i.e.
ARMv7-M compatible).
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This is needed, because an interrupt can happen after the main/static
MPU region is disabled and before it is re-enabled.
This region gets implicitly disabled inside the _region_init call, when
its configuration registers change:
SYSMPU->WORD[index][0] = region_base;
SYSMPU->WORD[index][1] = region_end;
SYSMPU->WORD[index][2] = region_attr;
SYSMPU->WORD[index][3] = SYSMPU_WORD_VLD_MASK;
The TRM says this about the WORD0, WORD1 and WORD2 registers:
Writes to this register clear the region descriptor’s valid bit
(RGDn_WORD3[VLD]).
And thus if an interrupt happens after writing to WORD0 and before
writing VLD to WORD3 again, the code executes with enabled and yet
misconfigured MPU.
Fixes#13482
Signed-off-by: Tomasz Gorochowik <tgorochowik@antmicro.com>
The linker file defines the __gcov_bss_size and _nocache_ram_size
symbols to get the size of the __gcov_bss and _nocache_ram section. Use
that instead of computing the value at runtime from the start and end
symbols.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
_arch_configure_dynamic_mpu_regions() may re-program the MPU
Stack Guard, to guard the privilege stack for overflows,
(if building with option CONFIG_MPU_STACK_GUARD). There is a
risk of actually overflowing the stack while doing the
re-programming. We minimize the risk by placing the
re-programming function immediately after we have switched to
the privileged stack so that the whole privilege stack area is
available for this critical operation.
Note that the risk for overflow is higher if using the normal
thread stack, since we do not control how much stack is actually
left, when user invokes _arm_userspace_enter().
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit moves the clearing of PSPLIM before determining the
privilege stack start and size. In this way the clearing can be
done without unnecessary pushing and popping r3 core register.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit provides two fixes for the ARMv8-M built-in stack
protection in userspace.S. First, it clears the PSPLIM register
before setting the PSP to the privileged stack. In the wake of
this, the privilege stack area can now be positioned enywhere,
i.e. does not have to be above the user stack area. Second, it
removes unncessary push/pop when clearing the PSPLIM register,
upon returning from the system call, since the r3 register is
not used anymore in this routine.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Fixing the documentation for ARM core __svc function, which was
outdated and present only for the ARMv7-M version.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Stacking r3 at this point is not required as the register value
is not used afterwards, therefore, it does not need to be
retained.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Due to code re-organization inside __pendSV(), the stacking
and unstacking of scratch registers around the invocation of
read_timer_end_of_swap() is no longer required.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Just like with _Swap(), we need two variants of these utilities which
can atomically release a lock and context switch. The naming shifts
(for byte count reasons) to _reschedule/_pend_curr, and both have an
_irqlock variant which takes the traditional locking.
Just refactoring. No logic changes.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
We want a _Swap() variant that can atomically release/restore a
spinlock state in addition to the legacy irqlock. The function as it
was is now named "_Swap_irqlock()", while _Swap() now refers to a
spinlock and takes two arguments. The former will be going away once
existing users (not that many! Swap() is an internal API, and the
long port away from legacy irqlocking is going to be happening mostly
in drivers) are ported to spinlocks.
Obviously on uniprocessor setups, these produce identical code. But
SMP requires that the correct API be used to maintain the global lock.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
This was never a long-term solution, more of a gross hack
to get test cases working until we could figure out a good
end-to-end solution for memory domains that generated
appropriate linker sections. Now that we have this with
the app shared memory feature, and have converted all tests
to remove it, delete this feature.
To date all userspace APIs have been tagged as 'experimental'
which sidesteps deprecation policies.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Replace Cortex-M3 with Cortex-M architecture family
in the header documentation of kernel_arch_data.h and
kernel_arch_func.h, which are generic header files for
the entire familty of ARM Cortex-M CPUs. The commit
adds some more minor style fixes in functions'
documentation.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit enforces default double-word stack alignmnet
on exception entry for Cortex-M3 and Cortex-M4 MCUs. The
patch ensures that we have consistent behavior in all
Cortex-M MCUs (double-world stack alignment on exception
entry is enforced by default in ARMv6, ARMv8, and Cortex-M7
processors).
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit updates the documentation of Kconfig option:
STACK_ALIGN_DOUBLE_WORD for Cortex-M microprocessors, stating
that the option is used in ARMv7-M MCUs to enforce 8-byte
stack alignment upon exception entry.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
use cmsis functions to avoid using direct assembly for main thread
switching.
This patch uses cmsis functions to:
- set PSP(process stack pointer) to main stack
- enable interrupts
Fixes#12878
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
The selection of the Cortex M systick driver to be used
as a system clock driver is controlled by
CONFIG_CORTEX_M_SYSTICK.
To replace it by another driver CONFIG_CORTEX_M_SYSTICK
must be set to 'n'. Unfortunately this also controls
the interrupt vector for the systick interrupt. It is
now routed to __reserved. More bad the interrupt vector
can not be set by IRQ_CONNECT as it is one of the hard
coded interrupts in the interrupt table.
Route the hard coded systick interrupt to z_clock_isr
and make z_clock_isr a weak symbol that can be overwritten
by an alternative systick system clock driver.
Signed-off-by: Bobby Noelte <b0661n0e17e@gmail.com>
This patch adjusts the way we are doing push/pop operations before
making function calls inside of assembly routines. ARM requires 8
byte aligned stack operations across public interfaces. This means
that we need to be sure to push multiples of 2 registers.
Fixes#2108
Signed-off-by: Andy Gross <andy.gross@linaro.org>
If you enable HW_STACK_PROTECTION, DEBUG_OPTIMIZATIONS, and
CPU_STATS, you can get a crash when switching to the main thread
due to the r3 getting munged during a inline ASM call. This patch
fixes that by adding r3 to the clobber list.
Fixes#12821
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This commit re-works the NXP MPU driver implementation so that
it aligns with the implementation for ARMv7-M and ARMv8-M MPU
architectures.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit removes obsolete ARM CORE MPU API definitions
and related implementation from arm_mpu.c, in the wake of
the transition to the new ARM MPU design.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit moves all internal implementation, relevant for
User mode, in a single place in the arm_mpu_v7_internal.h,
arm_mpu_v8_internal, and in arm_mpu.c. Additionally, the
commit cleans up internal function _get_region_attr() that
is not used any more.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit updates the ARM Core MPU API for memory domains,
to align with the principle of de-coupling the partitioning
and the access attribution with the architecture-specific
MPU driver implementation.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit adds the implementation of internal ARM MPU
function, arm_core_mpu_get_max_available_dyn_regions(),
required by _arch_mem_domain_max_partitions_get(),
according to the new architecture. The function returns
the number of the available partitions for memory domains
based on the total amount of HW regions and the
actual number of statically configured MPU regions.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit implements the internal (ARMv7-M and ARMv8-M)
API, which allows to user to (re)configure a memory partition
at run-time.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit contains the added functionality to program the
ARM8-M MPU so it can configure the dynamic memory regions at
run-time.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit contains the added functionality to program the
ARM7-M MPU so it can configure the dynamic memory regions at
run-time.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit introduces an ARM API that allows the user to
program a set of dynamic MPU regions at run-time. The API
function is invoked every time the memory map needs to be
re-programmed (for example at thread context-switch). The
functionality is implementated in arm_core_mpu.c.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit implements the common ARMv7-M and ARMv8-M internal
shim for configuring dynamic memory regions at run-time.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit contains the added functionality to program the
ARM8-M MPU, so it can configure the static memory regions at
boot time, as well as mark the areas, inside which dynamic MPU
region configuration at run-time will be allowed.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit contains the added functionality to program the
ARM7-M MPU, so it can configure the static memory regions at
boot time.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit removes the initialization of static memory regions
from arm_mpu_init(), since they are now initialized, directly,
by the kernel. The programming of MPU regions configured in SOC
definition is kept here.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit implements the common ARMv7-M and ARMv8-M internal
shim for configuring static memory regions at boot time. It also
adds LOG error messages, and ASSERTS, which fire if the static
MPU region configuration is not performed successfully.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit introduces the generic ARM (core) API, which allows
the user to program a set of static (fixed) MPU regions at boot
time. The API function is invoked upon initialization, in the
ARM-specific call of _arch_switch_to_main_thread(). The API
implementation is provided in arm_core_mpu.c.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit introduces a new Kconfig option symbol,
MPU_REQUIRES_NON_OVERLAPPING_REGIONS, to signify the use of an
MPU architecture that requires the active MPU regions be
non-overlapping. This requirement concerns the standard
(unmodified) ARMv8-M MPU implementation. For that, we select
the option in the definition of ARM_MPU, if the CPU architecture
is ARMv8-M (Baseline or Mainline).
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
cmsis provides intrinsic functions to configure processor special
function register like control, psp(process stack pointer). Let's use
these functions which are maintained in cmsis repository.
This patch uses cmsis function to:
- set process stack pointer(PSP)
- switch SP to PSP
- disable interrupts
It also moves stack initialization from assembly to C
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
This commit removes the local state variable nxp_mpu_enabled,
defined and used in NXP MPU driver, as it is not useful.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This patch adds all the required hooks needed in the kernel to
get the coverage reports from ARM SoCs.
Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
This patch adds a required cast for the size calculation utilizing
pointer arithmetic. The stack_obj needs a cast to u32_t. This was
caught using a newer compiler.
Signed-off-by: Andy Gross <andy.gross@linaro.org>
On ARM, _Swap() isn't atomic and a hardware interrupt can land after
the (irq_locked) caller has entered _Swap() but before the context
switch actually happens. This will require some platform-specific
workarounds in a few places in the scheduler.
This commit is just the Kconfig and selection on ARM.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Fix misspellings in documentation (.rst, Kconfig help text, and .h
doxygen API comments), missed during regular reviews.
Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
LTO is not supported yet, but there are a handful of references to the
flag '-flto' and the non-existent Kconfig option 'LTO'. To not confuse
users about whether LTO is supported or not, we should remove this
dead code.
As an aside, prototyping has shown that supporting LTO will give
signicant (10%) code size improvments, but will not be trivial to
support due to how we process object files with python.
Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
According with MISRA-C the value returned by a non-void function has
to be used. As memcpy return is almost useless, we are explicitly
ignoring it.
MISRA-C rule 17.7
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
This commit removes the priv_stack_size field from the _thread_arch
on arm architecture as there is no code using value stored in this
variable.
Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
arm_core_mpu.h and arm_core_mpu.c defined and implement kernel
APIs for memory protection, respectively. Therefore, they do not
need to directly include ARM CMSIS headers, or arm_mpu.h (or
nxp_mpu.h) which are supposed to define MPU-related kernel types
and convenience macros for the specific MPU architecture. These
headers are indirectly included by including kernel.h.
Similarly, arm_mpu.h shall not need to include internal/external
headers of memory protection APIs.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit does the following:
- it introduces additional convenience macros for representing
MPU attributions for no-cacheability, in both ARMv7-M and
ARMv8-M MPU architectures,
- it adds documentation in K_MEM_PARTITION_IS_WRITABLE/CACHEABLE
macros in all macro definitions in the different MPU variants
- it moves the type definition of k_mem_partition_attr_t inside
the architecture-specific MPU headers, so it can be defined
per-architecture. It generalizes app_mem_domain.h, to be able
to work with _any_ (struct) type of k_mem_partition_attr_t.
- it refactors the type of k_mem_partition_attr_t for ARMv8-M
to comply with the MPU register API.
- for NXP MPU, the commit moves the macros for region access
permissions' attributes inside nxp_mpu.h, to align with what
we do for ARM MPU.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit exposes k_mem_partition_attr_t outside User Mode, so
we can use struct k_mem_partition for defining memory partitions
outside the scope of user space (for example, to describe thread
stack guards or no-cacheable MPU regions). A requirement is that
the Zephyr build supports Memory protection. To signify this, a
new hidden, all-architecture Kconfig symbol is defined (MPU). In
the wake of exposing k_mem_partition_attr_t, the commit exposes
the MPU architecture-specific access permission attribute macros
outside the User space context (for all ARCHs), so they can be
used in a more generic way.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Some toolchains are built with multilib enabled in order to provide
multiple versions of the same library, optimized for different ABI
or architecture. They require the -march= and -mabi= options to be
passed at link time. This is important for example when linking with
newlib.
We do that by passing zephyr_ld_options the same arguments than
zephyr_compile_options. The -mabi option is passed directly while the
-march option, if defined, is passed through ${ARCH_FLAG}.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Add a "nocache" read-write memory section that is configured to
not be cached. This memory section can be used to perform DMA
transfers when cache coherence issues are not optimal or can not
be solved using cache maintenance operations.
This is currently only supported on ARM Cortex M7 with MPU.
Fixes#2927
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
The commit enforces the use of ARM_MPU_REGION_MIN_ALIGN_AND_SIZE
in include/arch/arm/arch.h, instead of using 32 as a hard-coded
value. The symbol is also used in arm/thread.c to truncate the
thread stack size to satisfy MPU granularity. The commit does
not introduce behavioral changes.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
The commit introduces a Kconfig option to define the minimum MPU
region size and alignment for ARM Cortex-M MCU architecture. The
hidden option is used by the linker to properly align linker
sections respecting the MPU requirements. Additionally, it is
used to define MPU Guard size and minimum stack alignment for
ARM Cortex-M MCUs in include/arch/arm/arch.h .
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
There were many platforms where this function was doing nothing. Just
merging its functionality with _PrepC function.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Declare and define arm_mpu_config and arm_mpu_regions
structs as const, as they are not modified in run-time.
Fixes#10320
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Avoid nested C++ comments inside the C comment block due to MISRA-C
rule 3.1. Keep the variables documenting possible caller saved
registers.
Signed-off-by: Patrik Flykt <patrik.flykt@intel.com>
These changes were obtained by running a script created by
Ulf Magnusson <Ulf.Magnusson@nordicsemi.no> for the following
specification:
1. Read the contents of all dts_fixup.h files in Zephyr
2. Check the left-hand side of the #define macros (i.e. the X in
#define X Y)
3. Check if that name is also the name of a Kconfig option
3.a If it is, then do nothing
3.b If it is not, then replace CONFIG_ with DT_ or add DT_ if it
has neither of these two prefixes
4. Replace the use of the changed #define in the code itself
(.c, .h, .ld)
Additionally, some tweaks had to be added to this script to catch some
of the macros used in the code in a parameterized form, e.g.:
- CONFIG_GPIO_STM32_GPIO##__SUFFIX##_BASE_ADDRESS
- CONFIG_UART_##idx##_TX_PIN
- I2C_SBCON_##_num##_BASE_ADDR
and to prevent adding DT_ prefix to the following symbols:
- FLASH_START
- FLASH_SIZE
- SRAM_START
- SRAM_SIZE
- _ROM_ADDR
- _ROM_SIZE
- _RAM_ADDR
- _RAM_SIZE
which are surprisingly also defined in some dts_fixup.h files.
Finally, some manual corrections had to be done as well:
- name##_IRQ -> DT_##name##_IRQ in uart_stm32.c
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
The ARMv8-M Memory Protection Unit document indicates that a DMB
instruction must be used before disabling the MPU in order to force
outstanding memory transactions.
The ARMv7-M documentation is less clear about that, and only specifies
that a DSB instruction followed by a ISB instruction must be used
before enabling the MPU, which is already the case. The ARMv7-M and
ARMv8-M MPU are relatively similar to believe the same sequence should
be used for disabling it.
This patch therefore adds a DMB instruction before disabling the MPU.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
In Zephyr on Cortex-M SoCs with both the ARM MPU and the cache enabled,
there are 3 possible states and associated configuration for the RAM
cache attributes:
- MPU disabled WBWA non-shareable
- MPU enabled, background RAM region WBWA non-shareable
- MPU enabled, thread RAM region WBWA shareable
In practice this means than the thread RAM region toggles from
shareable to non-shareable on each context change.
However the Cortex-M7 SoC does not support the WBWA shareable
configuration and fallback to simpler caching configuration. The
Technical Reference Manual states:
"By default, only Normal, Non-shareable memory regions can be cached
in the RAMs. Caching only takes place if the appropriate cache is
enabled and the memory type is cacheable. Shared cacheable memory
regions can be cached if CACR.SIWT is set to 1."
Similar indications can be found in the documentation from various
vendors: ST (AN4838), NXP (AN12042) and Atmel (AN15679).
It means that the thread RAM regions are either not cached (CACR.SIWT=0,
default) or WBWT cached (CACR.SIWT=1). This causes a performance issue.
In addition before switching a region from cached to non-cached and
vice-versa, the existing MPU code does not perform cache clean and/or
invalidate operations. This might cause data loss or corruption.
We should therefore change the RAM cache attributes to make them always
consistent. This patches change the thread/application RAM region from
WBWA shareable to WBWA non-shareable. This is done for all ARMv7-M SoCs
with an ARM MPU, however other SoCs (M0+, M3, M4) do not have cache, so
their behaviour should be unchanged.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
'b' can't jump very far on Cortex-M0 and will cause linker issues when
isr_wrapper and _IntExit are placed far away from each other.
To resolve this we use the 'bx' instruction, as it can jump much
further. Using 'bx' is not dangerous because we are jumping to thumb
mode code.
Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
Remove either duplicate settings between arch & board, or just set
HAS_DTS at the arch level since all the boards for a given arch support
DTS now.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit moves the block of the early return before
the derivation of the stack size, to avoid unnecessary
operations if this is not a user thread.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
In user mode a thread stack will include the optional
stack guard area (present if MPU_STACK_GUARD is defined.
The guard area has been originally take out of the thread
stack size calculation. For MPUs with no power-of-two size
requirement, we need to increase the size of the MPU region
for user-mode, to account for the additional guard region.
MPUs with power-of-two size requirement will, anyway, round
up the region size to the next power of two.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit introduces and implements an internal ARM
TrustZone-M API to allow the Non-Secure firmware to use
the Floating Point Unit (FPU).
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit contributes a Kconfig symbol hierarchy which allows
the user to build Zephyr Secure and Non-Secure images on ARMv8-M
MCUs with support for Trusted Execution. However, the high-level
configuration structure is generic, thus, can be potentially
used for any platform that supports Trusted Execution.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit extends the support of built-in thread stack
protection (i.e. based on the stack pointer limit registers)
in ARMv8-M, so that it works with user mode. The commit
does the following:
- enables and disables the stack limit checking on the
privileged stack, inside thread system calls, and upon
entering user mode,
- does not enable stack limit checking in context switch,
if the thread is in user mode.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
The function _IsInIsr computes a Boolean value but the function
returns a integer value. Fix the return type of the function.
This makes the zephyr api _is_in_isr() return a boolean type.
Thereby making it consistent across all the architectures.
Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
Instead of checking every time we hit the low-level context switch
path to see if the new thread has a "partner" with which it needs to
share time, just run the slice timer always and reset it from the
scheduler at the points where it has already decided a switch needs to
happen. In TICKLESS_KERNEL situations, we pay the cost of extra timer
interrupts at ~10Hz or whatever, which is low (note also that this
kind of regular wakeup architecture is required on SMP anyway so the
scheduler can "notice" threads scheduled by other CPUs). Advantages:
1. Much simpler logic. Significantly smaller code. No variance or
dependence on tickless modes or timer driver (beyond setting a
simple timeout).
2. No arch-specific assembly integration with _Swap() needed
3. Better performance on many workloads, as the accounting now happens
at most once per timer interrupt (~5 Hz) and true rescheduling and
not on every unrelated context switch and interrupt return.
4. It's SMP-safe. The previous scheme kept the slice ticks as a
global variable, which was an unnoticed bug.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Before entering userspace, the MPU stack guard is
configured to guard the default (i.e. afterwards, the "user")
thread stack, as the privileged stack has not yet been set. Upon
entering userspace the MPU stack guard needs to be re-programmed
to the privileged stack, otherwise, there is a risk that the
first system call might be serviced without privileged stack
protection, if it occurs before any context-switch. This commit
fixes this issue, by calling configure_mpu_stack_guard(..) upon
userspace entering.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
MISRA-C requires that all declarations of a specific function, or
object, use the same names and type qualifiers.
MISRA-C rule 8.3
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Added LOG_PANIC to fault handlers to ensure that log is flush and
logger processes messages in a blocking way in fault handler.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
Remove the inclusion of <string.h>, if CONFIG_INIT_STACKS
is defined, because it is not required anywhere in thread.c.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Several style and typo fixes in inline comments of arm kernel
files and thread.c.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit adds an inline explanatory comment in the API
for setting the non-secure stack-pointer limit registers, to
stress that the API is only applicable to Mainline ARMv8-M MCUs.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit fixes a minor bug by setting the error reason
(to, default, _NANO_ERR_HW_EXCEPTION) for errors detected
during Secure/Non-Secure stack inspection. Applicable only
to Secure firmware.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit removes all MPU-related (ARM_CORE_MPU and NXP_MPU)
options exept ARM_MPU, which becomes master switch controlling
MPU support on ARM.
Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
This commit introduces CPU_HAS_ARM_MPU and CPU_HAS_NXP_MPU options,
which indicate which flavour of MPU is supported by given SoC family.
Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
The __reset vector is using the 'b' instruction to jump to _PrepC. 'b'
can only jump 2KB on Cortex-M0 platforms so this causes build failures
when _PrepC happens to be too far away from __reset.
To resolve this we use 'bl' instead as it can jump two thousand times
further[0].
This can also be resolved by porting the reset vector to C or by
placing the _PrepC function in a dedicated section that the linker
places next to __reset.
[0] http://infocenter.arm.com/help/topic/com.arm.doc.dui0489e/Cihfddaf.html
Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
Any word started with underscore followed by and uppercase letter or a
second underscore is a reserved word according with C99.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
The ARMv8-m Memory Protection Unit does not require MPU regions
to be power-of-two aligned and sized. This commit removes this
requirement when building for ARMv8-m MCUs.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
__swap function was returning -EAGAIN in some case, though its return
value was declared as unsigned int.
This commit changes this function to return int since it can return a
negative value and its return was already been propagate as int.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
As far as possible SoC-specific code should be contained to it's
directory and core systems should not be referencing specific
SoCs. This keeps the common code clean and makes it easier to maintain
out-of-tree SoCs.
To this end we move CONFIG_SOC_TI_LM3S6965_QEMU's soft-reset related
code out of arch/arm/core/cortex_m and into arch/arm/soc/ti_lm3s6965.
Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Rather than do that for each architecture, source SoC Kconfigs where the
code is maintained, under ZEPHYR_BASE/soc.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Move the SoC outside of the architecture tree and put them at the same
level as boards and architectures allowing both SoCs and boards to be
maintained outside the tree.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
UART pins (TX, RX, RTS, CTS) are now configured in DTS files.
RTS and CTS definitions are optional. If flow control is enabled
and RTS/CTS pins are not defined, then compiler will issue
an error message.
Signed-off-by: Paweł Zadrożniak <pawel.zadrozniak@nordicsemi.no>
A bootloader may leave primask or faultmask set, so clear them during
startup when we enable interrupts and switch to the main thread.
Previously we only cleared primask for architecture variants which don't
support basepri, but now we do it for all architecture variants.
Fixes a failure on mimxrt1050_evk with the latency_measure test and
shell_module sample when using an nxp internal bootloader.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
This change adds DTS definition of SPI device for nRF chips.
It also removes SPI pin configuration from Kconfig and moves it to
chip DTS.
Signed-off-by: Filip Kubicz <filip.kubicz@nordicsemi.no>
This commit adds ADC nodes to DTS files for nRF SoCs and introduces
corresponding bindings for these nodes.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Remove I2C and SPI instances when enabling I2C_STM32 and
SPI_STM32 drivers.
It allows to enable the drivers if ports I2C_4, SPI_4,
SPI_5, SPI_6 are selected.
Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
One can enable I2C_3 in kconfig and set status = "ok" in dts, but
the driver expects to find the config as fixed up with this
addition.
Signed-off-by: Kiril Zyapkov <k.zyapkov@allterco.com>
The Cortex-M7 CPU included in the SAM e70 SoCs has instruction and data
caches that significantly boost the performances. Enable them during the
SoC initialization.
Fixes#8138
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
_k_syscall_table is an array of function pointers and is declared as
such in C sources, this makes it an STT_OBJECT[0] in the symbol
table. But when the same symbol is declared in assembly, it is
declared to be a function, which would make the symbol an STT_FUNC.
When linking with LTO this type inconsistency results in the warning:
real-ld: Warning: type of symbol `_k_syscall_table' changed from 2 to
1 in /tmp/cc84ofK0.ltrans8.ltrans.o
To fix this warning we declare the table with GDATA instead of GTEXT,
which will change the type from 'function' to 'object'.
[0]
https://docs.oracle.com/cd/E19455-01/816-0559/chapter6-79797/index.html
Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
The Cortex-M7 CPU included in the STM32F7 SoCs has instruction and data
caches that significantly boost the performances. Enable them during the
SoC initialization. Note that the D-cache should only be enabled if it
is disabled, to workaround CMSIS issue #331.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
This patch changes clock initialization sequence to initialize external
cristal oscillators only if it was not done before. Initialization of
external cristal oscillators may be performed by the bootloader.
Tested on BRD4250B evaluation board.
Fixes#9471
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
Move to more generic tracing hooks that can be implemented in different
ways and do not interfere with the kernel.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Define generic interface and hooks for tracing to replace
kernel_event_logger and existing tracing facilities with something more
common.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This commit adds an __ASSERT line in _get_region_attr_by_type,
to signal an error if the supplied MPU region type is not valid.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit adds a UL suffix after numerical digits to ensure
the correctness of certain shift operations.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit implements and integrates the ARMv8-M MPU driver
into the memory protection system for ARM.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit refactors arm_mpu.c by moving all internal function
implementation that is specific to ARMv7-M architecture to a
separate internal header file. This allows to easily extend
arm_mpu.c to support ARMv8-M by including all ARMv8-M-specific
implementation in a similar internal header.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit refactors the _get_region_attr_by_conf(.) function,
so it does the following:
- it is renamed to _get_ram_region_attr_by_conf(), to reflect
that it is only used to configure RAM MPU regions.
- it gets an arm_mpu_region_attr_t object structure pointer
to fill-in with the derived region attributes.
- it takes an additional argument (the region base address),
which allows the function to have a common signature with the
ARMv8-M version of it (where the attribute derivation needs
the base address).
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit refactors the _get_region_attr_by_type(.) function,
so it does the following:
- it takes an arm_mpu_region_attr_t object pointer and use it
to fill-in the derived region attributes.
- it performs only the distinguishing between the different MPU
region types, hiding the actual MPU-specific implementation
in internal functions.
- it takes an additional argument (the region base address),
which allows the function to have a common signature with the
ARMv8-M version of it (where the attribute derivation needs
the base address).
- it returs 0 or succes and a negative non-zero integer
to indicate an error.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit adapts the _region_init(.) function so it can use
the rasr field of the arm_mpu_region_attr structure, when it
configures the RASR register.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
The choice that contains FP_HARDAPI and FP_SOFTAPI already depends on
FLOAT, so the choice symbols don't have to.
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
I removed GPIO configuration from board files and enabled them
as default in driver Kconfig file. All boards had GPIO ports
enabled that is why I decided to enable it by default.
Power management example was changed to use new driver.
Signed-off-by: Mieszko Mierunski <mieszko.mierunski@nordicsemi.no>
irq_lock returns an unsigned int, though, several places was using
signed int. This commit fix this behaviour.
In order to avoid this error happens again, a coccinelle script was
added and can be used to check violations.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Add support for the STM32 Real-Time-Clock leveraging the LL APIs
Signed-off-by: Johannes Hutter <johannes@proglove.de>
Signed-off-by: Kiril Zyapkov <k.zyapkov@allterco.com>
Add support for usbotg_fs, by adding the DT fixup, pinmux macros,
and the DT entries in stm32f2.dtsi.
Signed-off-by: Istvan Bisz <istvan.bisz@t-online.hu>
There exist two symbols that became equivalent when PR #9383 was
merged; _SYSCALL_LIMIT and K_SYSCALL_LIMIT. This patch deprecates the
redundant _SYSCALL_LIMIT symbol.
_SYSCALL_LIMIT was initally introduced because before PR #9383 was
merged K_SYSCALL_LIMIT was an enum, which couldn't be included into
assembly files. PR #9383 converted it into a define, which can be
included into assembly files, making _SYSCALL_LIMIT redundant.
Likewise for _SYSCALL_BAD.
Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
Consistently use
config FOO
bool/int/hex/string "Prompt text"
instead of
config FOO
bool/int/hex/string
prompt "Prompt text"
(...and a bunch of other variations that e.g. swapped the order of the
type and the 'prompt', or put other properties between them).
The shorthand is fully equivalent to using 'prompt'. It saves lines and
avoids tricking people into thinking there is some semantic difference.
Most of the grunt work was done by a modified version of
https://unix.stackexchange.com/questions/26284/how-can-i-use-sed-to-replace-a-multi-line-string/26290#26290, but some
of the rarer variations had to be converted manually.
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
This commit removes the depreciated "default n" entries from
boolean K-config options in arch/arm.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
A design flaw of 'gsource' is that there's no way to require at least
one file to match the glob pattern. This could lead to silent errors.
Switch to a new design, where a plain 'source' is globbing and requires
at least one file to match. A separate 'osource' (optional source)
statement is available for cases where it's okay for a pattern (or plain
filename) to not match any files.
'orsource' combines 'osource' and 'rsource' (relative source).
This commit search-replaces 'gsource' with 'source', but backwards
compatibility with 'gsource' is still maintained by making it an alias
for 'osource' (and by making 'grsource' an alias for 'orsource').
The three Kconfig files arch/{nios2,posix,xtensa}/Kconfig source
arch/{nios2,posix,xtensa}/soc/*/Kconfig, which doesn't match any files.
Use 'osource' for those. The soc/*/Kconfig files seem to be for
additional SoC-specific symbols, only none exist yet on those ARCHes.
Also use 'osource' for the source of $ENV_VAR_BOARD_DIR/Kconfig in
boards/Kconfig, which doesn't exist for all boards.
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
The L433 chip is a superset of the L432, just grabbing a few additional
interfaces (LCD, I2C2, USART3, SPI2, SDMMC). All the support/HAL files
are already there, so enabling these is just a matter of build system
setup.
Tested on an application specific board (builds correctly and I2C2
works.) I unfortunately don't have a nucleo/discovery board to create a
reference board for.
Signed-off-by: David Lamparter <equinox@diac24.net>
When building a Secure firmware image, instruct the linker to
generate a symbol table with the entry veneers, to allow a Non
Secure firmware image to access Secure Entry functions via the
entry veneers.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit adds K-config options that allow the user to
signify an ARM Secure Firmware that contains Secure Entry
functions and to define the starting address of the linker
section that will contain the Secure Entry functions. It
also instructs the linker to append the NSC section if
instructed so by the user.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit contribute an internal ARM API that enables the
user to confgure an ARM Security Attribution Unit region. It
also defines ARM_SAU as a K-config option to indicate that
an MCU implements the ARM SAU.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit contributes a simple API to allow the TrustZone
user to block or permit Non-Secure System Reset requests.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit introduces an internal ARM macro API to allow the
TrustZone user to define Non-Secure entry functions.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit defines and implements and internal ARM macro API
that allows the TrustZone user to declare, define, and evaluate
pointers of non-secure function type.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Make GCC compile with the -mcmse compile option, if we are
building a Secure firmware. The option will make Security
Extensions for secure executables available, and will set
the corresponding compile-time indicator flag, accordingly:
(i.e. __ARM_FEATURE_CMSE=3).
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Define and implement a function to read the number of
SAU regions configued for the MCU.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit defines and implements an internal ARMv8-M TrustZone
API to allow the user to select whether Secure exceptions will
have priority boosting over Non-Secure exceptions.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit defines and implements an internal ARMv8-M TrustZone
API to allow the user to configure the target state of fault
exceptions that are not banked between security states.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit adds a macro definition for the Vector Key value of
AIRCR register that permits the accompanying writes. The macro
is then used instead of the hard-coded numerical value.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit adds and implements an ARM internal API function
to configure the Non-Secure instance of MSPLIM or PSPLIM.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit defines and implements the internal ARM TrustZone
API to enable or disable the Security Attribution Unit.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Define and implement an API to configure the Non-Secure instances
of core registers in ARM Cortex-M23 and Cortex-M33.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This finishes refactor of splitting off net_config library name from
net_app library, started in c60df1311, c89a06dbc. This commit makes
sure that Kconfig options are prefixed with CONFIG_NET_CONFIG_
instead of CONFIG_NET_APP_, and propagates these changes thru the
app configs in the tree.
Also, minor dependency, etc. tweaks are made.
Signed-off-by: Paul Sokolovsky <paul.sokolovsky@linaro.org>
This commit optimizes _size_to_mpu_rasr_size(.) in the ARMv7-M
MPU driver, so it makes use of a single _builtin_clz() function
call, instead of two.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Up until now, Zephyr has patched Kconfig to use the last 'default' with
a satisfied condition, instead of the first one. I'm not sure why the
patch was added (it predates Kconfiglib), but I suspect it's related to
Kconfig.defconfig files.
There are at least three problems with the patch:
1. It's inconsistent with how Kconfig works in other projects, which
might confuse newcomers.
2. Due to oversights, earlier 'range' properties are still preferred,
as well as earlier 'default' properties on choices.
In addition to being inconsistent, this makes it impossible to
override 'range' properties and choice 'default' properties if the
base definition of the symbol/choice already has 'range'/'default'
properties.
I've seen errors caused by the inconsistency, and I suspect there
are more.
3. A fork of Kconfiglib that adds the patch needs to be maintained.
Get rid of the patch and go back to standard Kconfig behavior, as
follows:
1. Include the Kconfig.defconfig files first instead of last in
Kconfig.zephyr.
2. Include boards/Kconfig and arch/<arch>/Kconfig first instead of
last in arch/Kconfig.
3. Include arch/<arch>/soc/*/Kconfig first instead of last in
arch/<arch>/Kconfig.
4. Swap a few other 'source's to preserve behavior for some scattered
symbols with multiple definitions.
Swap 'source's in some no-op cases too, where it might match the
intent.
5. Reverse the defaults on symbol definitions that have more than one
default.
Skip defaults that are mutually exclusive, e.g. where each default
has an 'if <some board>' condition. They are already safe.
6. Remove the prefer-later-defaults patch from Kconfiglib.
Testing was done with a Python script that lists all Kconfig
symbols/choices with multiple defaults, along with a whitelist of fixed
symbols. The script also verifies that there are no "unreachable"
defaults hidden by defaults without conditions
As an additional test, zephyr/.config was generated before and after the
change for several samples and checked to be identical (after sorting).
This commit includes some default-related cleanups as well:
- Simplify some symbol definitions, e.g. where a default has 'if FOO'
when the symbol already has 'depends on FOO'.
- Remove some redundant 'default ""' for string symbols. This is the
implicit default.
Piggyback fixes for swapped ranges on BT_L2CAP_RX_MTU and
BT_L2CAP_TX_MTU (caused by confusing inconsistency).
Piggyback some fixes for style nits too, e.g. unindented help texts.
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
This patch adds the RDC (Resource Domain Controller) peripheral
permissions settings for the i.MX applications cores (Cortex A9 on
i.MX6 and Cortex A7 on i.MX7).
This will enable both Linux (on application's core) and Zephyr (on M4
core) to share the peripherals and coexist.
The settings are defined at devicetree level and applied in the soc.c.
A complete solution should involve the SEMA4 to control the peripherals
access and prevent resource deadlocking and misusage.
Signed-off-by: Diego Sueiro <diego.sueiro@gmail.com>
These settings enable use of the WNC-M14A2A LTE-M modem as the default
network interface for the nRF52840-DK board (nrf52840_pca10056).
They include the following settings when MODEM_WNCM14A2A is selected:
- UARTE1 pin setup
- DTS / DTS fixup additions for WNC-M14A2A
- Kconfig settings for modem driver
Signed-off-by: Michael Scott <mike@foundries.io>
Uses fixup infrastructure to safely abort if we get an MPU
fault when examining a string passed in from user mode.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
It corrects the IRQs number of various SoCs.
IRQs number is in conformity with the IRQn_Type
enumeration in SoC header files of STM32Cube
HAL.
Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
In some kernel configurations, the offset can be greater
than the maximum of 124 for ldr/str immediate offsets.
Fixes: #9113
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
The STM32F7 uses the V2 version of the STM32 I2C controller. Add the
corresponding Kconfig, DTS, DTS fixup and pinmux entries.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
This commit adds the implementation that allows the ARM CPU
to recover from (otherwise fatal) MPU faults. A new error
reason, _NANO_ERR_RECOVERABLE, is introduced. The error
reason is used to suppress fault dump information, if the
error is actually recoverable.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit does several things:
- It unifies the way the fault inspection is implemented,
irrespective of the selected fault dumping level.
- It removes the dumping of the Thread ID and faulting
instruction address, as these are now displayed by
_NanoFatalErrorHandler.
- It introduces a new debug print directive, to be used
for the highest dumping level (2).
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit implements two changes.
- It splits out the dumping of the Secure stack information to a
separate function. Dumping will only occur if the highest dump
level has been selected.
- Forces _Fault() to invoke _NanoFatalErrorHandler, instead of
_SysFatalErrorHandler. In addition, early return statemets are
implemented in _Fault(), so the fatal error handler is only
invoked once.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit improves the documentation of function _Fault(.),
in order to better describe the actual implementation and the
use of the function arguments.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit forces arm_mpu_init() to use the provided API
functions to enable and disable the MPU. Besides the clean-up
the commit enforces the MPU driver to use data and instruction
synchronization barriers every time the MPU is enabled. This
is aligned with the programming recommendations by ARM.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
1. dts.fixup files updated with peripheral address and IRQ NUMBER.
2. Peripheral address is taken from DT.
3. IRQ number is taken from DT.
Signed-off-by: Jakub Rzeszutko <jakub.rzeszutko@nordicsemi.no>
This commit fixes a bug in _get_region_ap(.) by adding
parentheses to enforce the correct operator precedence.
Fixes#8864.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
The STM32F7 uses the same USB OTG FS controller than the STM32F4 series.
It is therefore trivial to add support for it, by adding the DT fixup
and pinmux macros, and the DT entries in stm32f7.dtsi. Keep it disabled,
it should be enabled at the board level.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Update _get_region_attr_by_type used to set up the user regions
on a per thread basis to match the REGION_USER_RAM_ATTR macro. Caching
attributes were set "Outer and inner write-through. No write allocate.",
this patch changes it to "Outer and inner write-back. Write and read
allocate.".
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
The SAMD0 Family have almost the same clock options.
The samd20 and samd21 only clocks is not implemented yet.
Signed-off-by: Sean Nyekjaer <sean@nyekjaer.dk>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This keeps the efm32wg soc.h in sync with the efr32fg1p soc.h.
This include is currently not necessary, but will be for further
peripheral drivers.
Signed-off-by: Christian Taedcke <hacking@taedcke.com>
The Silicon Labs EFR32FG1 Flex Gecko MCU includes:
* Cortex-M4F core at 40MHz
* up to 256KB of flash and 32KB of RAM
* integrated Sub-GHz and/or 2.4GHz radio
* multiple low power peripherals
Signed-off-by: Christian Taedcke <hacking@taedcke.com>
Reduces the number of mpu regions statically reserved at boot time by
one, giving a total of five. We originally sought to reduce the total to
three: 1 background region with lowest precendence for supervisor r/w, 1
flash region, and 1 sram region. However, the nxp mpu hardware does not
give precedence to any region over another, and thus we cannot revoke
access from the background region with a higher priority region. This
means we cannot support hardware stack protection with a single
background region.
Instead, create two background regions that cover the entire address
space, except for sram.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
If we select UART0 as UARTE we will get different defines from the
generation script. Support both UART and UARTE for UART0. Also fixup
UART1 defines since this will always be UARTE.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The STM32F769 has more interrupts and features than the STM32F746,
but the basic support is similar with STM32F746
Signed-off-by: Yong Jin <jinyong.iot@foxmail.com>
The stm32f2 version of soc.h misses the changes done in commit
aee97be ("arch: arm: soc: remove core zephyr header inclusions
from soc.h").
Signed-off-by: Istvan Bisz <istvan.bisz@t-online.hu>
The NXP MPU triggers a bus fault when a memory access error occurs. Add
support in the bus fault handler to dump error details from the NXP MPU,
including the port number, mode (supervisor or user), address, bus
master number, and regions.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Pulled CMSDK_BEETLE.h from mbed-os as a starting point to enable CMSIS
support on Beetle. Trimed the file down that what we need on Zephyr
(dropped Device Specific Peripheral Section and system_CMSDK_BEETLE.h).
This lets us drop soc_mpu.h which duplicates MPU info that is defined in
CMSIS headers.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
clear RXNE flag in fifo_read, remove TEACK and REACK
check when uart_stm32_init because stm32f2 doesn't
has those flags.
Signed-off-by: qianfan Zhao <qianfanguijin@163.com>
This commit refactors internal functions in arm_mpu.c to use
bitsets and functions taken directly from ARM CMSIS instead of
hardcoded arithmetic literals. In several internal functions
some part of the implementation is abstracted further in inline
functions or convenience macros, to facilitate extending the
arm_mpu.c for ARMv8-M. In addition, the commit adds minor
improvements in internal function documentation.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit abstracts the attribution generation for an MPU
region, determined based on a supplied configuration and the
given size, from the actual implementation, which is placed
in a separate inline function. This allows to have multiple
implementations of attribution generation for different ARM
MPU drivers.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit refactors the _region_init(..) internal MPU driver
function so it gets the region index and a struct arm_mpu_region
as aruments. The latter holds the MPU region configuration that
is to be applied to the region determined by the index argument.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit enforces conditional compilation of mpu_regions.c
in nrf52/CMakeLists.txt depending on whether ARM_MPU_NRF52X
K-option is defined.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
All the STM32F7 SoCs have a TRNG. Adding support for it is just a matter
of tweaking the #ifdef and including the right file from HAL.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Duplicate the ARM MPU-related registers' definitions
specifically for Beetle SOC which is not compliant with
ARM CMSIS and does not include the ARM CMSIS headers.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit removes the redundant HAL definition for the ARM
Cortex-M MPU registers, and modifies the ARM MPU driver
implementation to directly use the provided HAL from CMSIS.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
The entry point can and therefore should be set by linker
scripts. Whenever possible one should express things in the source
language, be it .c or .ld, and not in code generators or in the build
system.
This patch removes the flag -eCONFIG_KERNEL_ENTRY from the linker's
command line and replaces it with the linker script command
ENTRY(CONFIG_KERNEL_ENTRY)
Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
This commit refactors arm_core_mpu_configure_user_context() so
it can use directly arm_core_mpu_configure().
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit places all the implementation in arm_mpu.c within
build-time guards, ensuring that it is compiled-in only if the
kernel features requiring MPU are present (i.e. USERSPACE,
APPLICATION_MEMORY, or MPU_STACK_GUARDS). An exception to that
is the code required for MPU initialization, which is left out,
as MPU initialization occurs always if MPU is present.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
The STM32F723 has more interrupts than the STM32F746 due to the
additional SDMMC controller. Besides that the changes are very
similar to the ones of the STM32F746.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
This commit updates the compile options in cmake to distinguish
between ARMv8-M Mainline MCUs with or withouth the optional DSP
extension. A new Kconfig option: ARMV8_M_DSP, is introduced, to
signify the use of an ARMv8-M MCU with DSP support.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
All chips from nRF51 and nRF52 series support Segger RTT,
so we can enable it if given series is used.
Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
This commit cleans up source files in soc/nrf51 soc/nrf52
folders by removing unnecessary header inclusions.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit removes the inclusion of kernel_includes.h from
the nRF51 and nRF52 soc.h headers. This prevents from an
inclusion cycle formation on soc.h. In the wake of
kernel_includes.h removal, necessary header files have been
added in several source files to be able to compile Zephyr for
nRF5x SOCs.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit adds an explanatory comment in all soc.h headers,
where kernel_includes.h header has been included, to stress out
that this header must be included after SOC-specific headers are
brought in. The reason is the fact that kernel_includes.h needs
the ARM CMSIS definitions, which are brought in by the
SOC-specific header inclusions.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
The stm32f7 version of soc.h misses the changes done in commit
aee97be710 ("arch: arm: soc: remove core zephyr header inclusions
from soc.h") as it was not merged at that time. Fix that.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
This reverts commit 30529da0e4.
We should include SoC headers from HALs before we include
kernel_includes.h. On ARM this is needed because we tend to get CMSIS
related defines setup by the HAL headers.
Fixes: #8593
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The patch adds serial driver support for STM32F7 family
microcontrollers, includes pinmux definitions and DTS fixup file.
Signed-off-by: Yurii Hamann <yurii@hamann.site>
Enable HAS_SEGGER_RTT to allow user to select use of SEGGER RTT
and SystemView solution.
SEGGER provide a firmware that can convent ST-Link to J-Link,
And RTT is supports all stm32 SoCs, so lets enable RTT default
Signed-off-by: qianfan Zhao <qianfanguijin@163.com>
* We are now *much* better at not reserving unnecessary
system MPU regions based on configuration. The #defines
for intent are now an enumerated type. As a bonus, the
implementation of _get_region_index_by_type() is much
simpler. Previously we were wasting regions for stack guard
and application memory if they were not configured.
* NXP MPU doesn't reserve the last region if HW stack
protection isn't enabled.
* Certain parts of the MPU code are now properly ifdef'd
based on configuration.
* THREAD_STACK_REGION and THREAD_STACK_USER_REGION was a
confusing construction and has now been replaced with
just THREAD_STACK_REGION, which represents the MPU region
for a user mode thread stack. Supervisor mode stacks
do not require an MPU region.
* The bounds of CONFIG_APPLICATION_MEMORY never changes
and we just do it once during initialization instead of
every context switch.
* Assertions have been added to catch out-of-bounds cases.
Fixes: #7384
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This commit correct the issue introduce by aee97be which
changed the order of header inclusion that lead
to warning generation at compilation, that truend into errors
in CI.
This commit reinstantiate the initial header inclusion order.
Fixes#8563
Signed-off-by: Christophe Priouzeau <christophe.priouzeau@st.com>
Bool symbols implicitly default to 'n'.
A 'default n' can make sense e.g. in a Kconfig.defconfig file, if you
want to override a 'default y' on the base definition of the symbol. It
isn't used like that on any of these symbols though.
Also simplify the definition of CC3220SF_DEBUG. 'default's can be other
symbols too, not just literal values. The condition for the symbol to be
visible (user-configurable) can be put directly on the prompt as well.
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
The nRF52810 is a low-cost variant of the nRF52832, with a reduced set
of peripherals and memory. This commit adds basic support for it in the
arch SoC and dts folders.
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
Signed-off-by: Ioannis Glaropoulos <ioannis.glaropoulos@nordicsemi.no>
The imxrt1050 is configured to use SYSTICK for the kernel timer, but
SYSTICK cannot wake up the soc from low-power modes. Disable low-power
modes on this soc until we have support for an alternative timer.
This fixes k_sleep on the EVKB version of the mimxrt1050_evk board. An
earlier version of the board (EVK, not EVKB), had A0 silicon which
by default did not enter low-power mode on a wfi.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Remove all CONFIG_*_EP_ADDR options but keep the default
values for it, as they are necessary to find ep_addr in
usb_ep_cfg_data associated with bEndpointAddress in
interface descriptor.
Signed-off-by: Johann Fischer <j.fischer@phytec.de>
This commit removes the direct inclusions of device.h or gpio.h
from soc.h header files in ARM SOCs, to avoid soc.h include
kernel.h.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Set Zero Latency IRQ to priority level zero and SVCs to priority level
one when Zero Latency IRQ is enabled.
This makes Zero Zatency truly zero latency when the kernel has been
configured with userspace enabled, or when IRQ offloading is used.
Exceptions can still delay Zero Latency IRQ, but this is considered
ok since exceptions indicate a serious error, and the system needs to
recover.
Fixes: #7869
Signed-off-by: Joakim Andersson <joakim.andersson@nordicsemi.no>
SDA and SCL pins can now be configured through DTS.
Pins on development kits have been assigned according to arduino
headers.
Signed-off-by: Mieszko Mierunski <mieszko.mierunski@nordicsemi.no>
The i.MX 6SoloX SoC is a hybrid multi-core processor composed by one
Cortex A9 core and one Cortex M4 core.
Zephyr was ported to run on the M4 core. In a later release, it will
also communicate with the A9 core (running Linux) via RPMsg.
The low level drivers come from NXP FreeRTOS BSP and are located at
ext/hal/nxp/imx. More details can be found at ext/hal/nxp/imx/README
The A9 core is responsible to load the M4 binary application into the
RAM, put the M4 in reset, set the M4 Program Counter and Stack Pointer,
and get the M4 out of reset.
The A9 can perform these steps at bootloader level after the Linux
system has booted.
Signed-off-by: Stanislav Poboril <stanislav.poboril@nxp.com>
Duplicate the CMSIS MPU-related macro definitions specifically
for Beetle SOC which is is not compliant with ARM CMSIS and
does not include the ARM CMSIS headers.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit removes the macro definitions for MPU_RASR register
bitmasks, defined in arm_mpu.h, and modifies the MPU driver to
directly use the equivalent macros defined in ARM CMSIS.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit removes the macro definitions for MPU_RBAR register
bitmasks, defined in arm_mpu.h, and modifies the MPU driver to
directly use the equivalent macros defined in ARM CMSIS.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit removes the macro definitions for MPU_CTRL register
bitmasks, defined in arm_mpu.h, and modifies the MPU driver to
directly use the equivalent macros defined in ARM CMSIS.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Configuration parameter SOC_SERIES_NRF52X is common for all NRF5X SoCs.
Due to that it cannot select: CPU_HAS_FPU because not all Nordic
microcontrollers supports that. Selection of this parameter was moved
to configuration of each SoC in Kconfig.soc file.
Signed-off-by: Jakub Rzeszutko <jakub.rzeszutko@nordicsemi.no>
Created NRF5x peripheral list that can be used to describe each
NRF5x SoC. Basing on this description Kconfig file can display
and allow to configure only these drivers that are available
for particular SoC.
Signed-off-by: Jakub Rzeszutko <jakub.rzeszutko@nordicsemi.no>
Replace code that handles erratas and performs other SoC-specific
initialization, that was actually copied from SystemInit() provided
in MDK for particular SoCs, with a call to SystemInit().
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
The various STM32 reference manuals sometimes define the USB endpoints
as IN or OUT only and sometimes as bidirectional, even in the same
manual. This is likely because the OTG implementation has one set of
registers for the IN endpoints and one other set for OUT endpoints.
However at the end a given endpoint address can both transmit and
receive data.
This causes some confusion how to declare the endpoints in the device
tree, and depending on the SoC, they are either the same number of IN
and OUT endpoints declared, or they are declared as bidirectional. At
the end it doesn't really matter given how the driver uses those values:
#define NUM_IN_EP (CONFIG_USB_NUM_BIDIR_ENDPOINTS + \
CONFIG_USB_NUM_IN_ENDPOINTS)
#define NUM_OUT_EP (CONFIG_USB_NUM_BIDIR_ENDPOINTS + \
CONFIG_USB_NUM_OUT_ENDPOINTS)
#define NUM_BIDIR_EP NUM_OUT_EP
This patch therefore cleanup the driver, the DTS, and the DTS fixups to
only define the number of bidirectional endpoints.
In addition to the cleanup, that fixes a regression introduced by commit
52eacf16a2 ("driver: usb: add check for endpoint capabilities"), which
introduced a wrong check for SoC only defining the number of
bidirectional endpoints.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
This commit enables CAN on the STM32L432.
Tested on nucleo l432ck with external transceiver and loopback mode.
Signed-off-by: Alexander Wachter <alexander.wachter@student.tugraz.at>
The prepended 0x causes DTC warnings and shouldn't be there.
Tested by compiling hello_world for nrf52840_pca10056 before and after.
Fixes#8334.
Signed-off-by: Alex Tereschenko <alext.mkrs@gmail.com>
This commit contributes the definition and the implementation
of an API for ARM MCUs to configure and get the configuration
of the security state targeted by a given external IRQ line.
The API is only available in Secure ARM Firmware.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Declare and implement convenience wrappers to evaluate Non-Secure
read and write permissions of C variables using the cmse address
range intrinsics.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit contributes the implementation of the CMSE
address range permission checks based on the ARMv8-M
address range check intrinsics exlusicely for Secure state.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Refactor arm_cmse_mpu_region_get(.) function, so its signature,
documentation, and implementation align with the rest of functions
for obtaining MPU, SAU and IDAU region numbers via the TT instruction.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit defines and implements an internal ARMv8-M API
that allows the user to evaluate access permissions of memory
locations, based on the ARMv8-M Tests Target (TT, TTA)
instruction support (for Secure requests).
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit introduces additional dependencies and selection
scheme for CPU_CORTEX_M_HAS_SPLIM, for Zephyr Non-Secure builds
on ARMv8-M MCUs with Security Extensions.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit introduces the ARMV8_M_SE K-config option
to signify the use of an ARMv8-M MCU with support for
Security Extensions. It also introduces dependences of
ARM_(NON)SECURE_FIRMWARE on ARMV8_M_SE.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit introduces the K-config option
ARM_NONSECURE_FIRMWARE, to indicate a Zephyr firmware image
that is intended to execute in Non-Secure state.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit improves the help text description for K-config
option: ARM_SECURE_FIRMWARE.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
On Cortex-M7 CPU (at least on STM32F723), the dummy move FPU instruction
is executed before the FPU lazy state preservation is disabled. Add an
instruction synchronization barrier before it to avoid that.
At the same time, remove the data synchronization barrier after the
dummy move as it does not have any effect on RAM or registers.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
This adds basic support for declaring gpio nodes in dts for nrf52.
The dts.fixup provides mapping for the generated defines to the config
defines currently used by the nrf gpio driver.
Existing boards that use nrf52 are updated.
Signed-off-by: Marc Reilly <marc@cpdesign.com.au>
The extra region is wrapped in an "ifdef" as two MPU regions are used
only if the total memory size is not a power of two.
Signed-off-by: Tomasz Gorochowik <tgorochowik@antmicro.com>
There is no need for two RAM regions when the total amount of memory is
a power of two. With this change it will be possible to map the whole
memory and save one MPU region for such cases.
Signed-off-by: Tomasz Gorochowik <tgorochowik@antmicro.com>
Added a hidden Kconfig option in arch/arm/soc/nordic_nrf
which is selected by selecting DC/DC circuitry being present
in the board.
Signed-off-by: Vinayak Kariappa Chettimada <vich@nordicsemi.no>
Since they are not used anymore because can be replaced
by CMSIS definition or generated from device tree,
remove IRQ definition file soc_irq.h
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This commit sets VECTOR_ADDRESS in prep_c.c directly to the
value of _vector_start for XIP images for MCUs which have the
VTOR register.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
UART driver renamed to keep the same convention as SPI and TWI drivers.
All substrings: "UART_NRF5" in defines renamed to "UART_NRFX_UART".
Signed-off-by: Jakub Rzeszutko <jakub.rzeszutko@nordicsemi.no>
Replace all register defines and calls with Nordic nrfx HAL.
Simplification of uart shim - assumed only one uart instance.
Added parity bit to configuration options.
Signed-off-by: Jakub Rzeszutko <jakub.rzeszutko@nordicsemi.no>
Add fixup info for PWM nodes on STM32F0/F1/F3/F4/L4 and remove the
conflicting Kconfig symbols to fully switch STM32 PWM to device tree.
Signed-off-by: Florian Vaussard <florian.vaussard@gmail.com>
The PendSV handler sits below the priority of other OS interrupts, but
it was inspecting kernel state before masking those interrupts out!
Move the locking to the top.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
This commit removes the arm_mpu_enabled status flag in the ARM
MPU driver. This flag is not needed, because the value of the
MPU_CTRL register stays the same while the MPU is enabled, and
is cleared to 0 when the MPU is disabled. Therefore, we do not
need to prevent from having the enable or the disable operation
to be called multiple times.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
In _arm_mpu_config provide a more detailed description of the
effect of MPU PRIVDEFENA flag when enabling the ARM MPU.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
ARM Cortex-M0+, M3, and M4 MCUs have a fixed number of 8 MPU
regions, if MPU support is implemented. Therefore, we can
implement _get_num_regions() to return a constant, if CPU
is one of the above Cortex variants. _get_num_regions() is
invoked often in the code, so this solution increases processing
efficiency. A sanity check is implemented in arm_mpu_init(), to
ASSERT if the number of regions provided by hardware does not
match the expected (default) value.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commits adds a dependency for ARM_MPU on !CPU_CORTEX_M0,
so an accidental selection or ARM_MPU in ARM Cortex-M0 MCUs
will signal a K-config warning.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
The original implementation of CONFIG_THREAD_MONITOR would
try to leverage a thread's initial stack layout to provide
the entry function with arguments for any given thread.
This is problematic:
- Some arches do not have a initial stack layout suitable for
this
- Some arches never enabled this at all (riscv32, nios2)
- Some arches did not enable this properly
- Dropping to user mode would erase or provide incorrect
information.
Just spend a few extra bytes to store this stuff directly
in the k_thread struct and get rid of all the arch-specific
code for this.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
BUILD_OUTPUT_HEX was enabled by default for stm32 SoCs.
This should not be the default setting and besides it has no
effect because of 'default n' in misc/Kconfig that seems to
prevail.
Removing the 'default y' for stm32 to avoid confusion.
Fixes#8193
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
On ARM, the __thread_entry struct pointer used when
CONFIG_THREAD_MONITOR is enabled was pointing to the initial exception
stack frame. That's not right: even though this contains all the same
info, it's not layout-compatible with the API struct. And once the
thread starts running, the ESF gets unwound and the memory recliamed
for the stack frame of the entry function!
Stuff the __thread_entry struct into its own memory at the bottom of
the stack like the other architectures do. Fixes#7541
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
PLL configuration options for i.MX RT SoCs were added in commit
3fd25c64c7, but the selects were
incorrectly added to the SoC defconfig rather than Kconfig.soc. This
resulted in the PLL options not being configured and the part not
booting properly.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
An issue has been confirmed in CMSIS core header file in
SCB_EnableDCache when stack is in cacheable memory.
Issue report: https://github.com/ARM-software/CMSIS_5/issues/331
To workaround this issue by checking if Dcache's been enabled before
trying to enable it.
Signed-off-by: Ryan QIAN <jianghao.qian@nxp.com>
- Remove clock gating code to be compatible with A1 silicon
- Remove PLL deinitialization code out of soc file
Signed-off-by: Ryan QIAN <jianghao.qian@nxp.com>
This commit moves the bit timing (PROP, BS1, BS2 segments and SWJ)
from Kconfig to the device-tree and fixes issue #7933
Signed-off-by: Alexander Wachter <alexander.wachter@student.tugraz.at>
The r7 register is used as a frame pointer on ARM Thumb. As result, it
cannot be modified by the assembly code in functions using stack frame.
This commit replaces r7 by r8, which is a general purpose register.
Also it fixes#7704.
Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
This commit fixes some minor function documentation issues
and comments' style in the NXP_MPU driver.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit inserts sanity checks every time we are performing
a (re)-configuration of one or multiple MPU regions, ensuring
that we do not attempt to configure an invalid region number.
Particulary for arm_mpu_config(), called during pre-kernel
initialization phase, we add a system ASSERT if we attempt
to initialize more regions that what is supported by hardware.
We do this to ensure the misconfiguration is detected early and
the system boot is aborted.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit adds an internal function to disable an MPU region.
The function includes an assert that the requested MPU region
number is a valid one. arm_mpu.c is refactor to use this
function in all cases where an MPU region needs to be disabled.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit enhaces the documentation of internal functions
in arm_mpu.c by explicitly stating that the caller needs to
ensure the validity of the supplied MPU region index. The
warning is required as these functions modify the ARM MPU_RNR
register, without checking themselves the validity of the
provided region number.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit fixes some minor issues with coding style
and comment syntax in arm_mpu.c
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Change the zero latency interrupt priority level from 2 to 1.
This is the priority level that the kernel has reserved for the
zero latency IRQ feature by the _IRQ_PRIO_OFFSET constant.
The zero latency IRQ will now not be masked by the irq_lock function.
Update comments to reflect the priority levels reserved by the kernel.
Fixes: #8073
Signed-off-by: Joakim Andersson <joakim.andersson@nordicsemi.no>
Upon MemManage Exception, multiple status bits of MMFSR may be
set. This commit modifies the MPU Fault Handler, so that it can
inspect and display information from all error conditions,
instead of just the first error condition that is true.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Make MPU stack guard checks use the previously stored value
of the MemManage Fault Address Register, to ensure that the
address-under-check is valid.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Remove the dead code that was guarded by previously removed
Kconfig symbols for the sensortag board.
With b028a51542,
this fixes#7873
Signed-off-by: Gil Pitney <gil.pitney@linaro.org>
In some STM32 series, SPI LL headers where included under
CONFIG_CLOCK_CONTROL_STM32_CUBE flag definition.
Fix this and use CONFIG_SPI_STM32 instead.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Previously the directory core/cortex/mpu/ was getting included
on a hidden kconfig. Now this has been replaced with the Kconfig
CONFIG_ARM_CORE_MPU.
Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
Enable the instruction cache by default in order to achieve a speedup of
up to 20% in code execution.
Cache can be disabled by setting the new NRF_ENABLE_ICACHE Kconfig
option.
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
All the STM32L4 SoCs have a Cortex-M4F CPU, and thus have a FPU. Update
stm32l4/Kconfig.series to select CPU_HAS_FPU.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
In preparation for introducing a warning.
Unquoted string defaults work through a quirk of Kconfig (undefined
symbols get their name as their string value), but look confusing. It's
done inconsistently now too.
Suggested by Kumar Gala.
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
In preparation for introducing a warning.
Unquoted string defaults work through a quirk of Kconfig (undefined
symbols get their name as their string value), but look confusing. It's
done inconsistently now too.
Suggested by Kumar Gala.
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
In preparation for introducing a warning.
Unquoted string defaults work through a quirk of Kconfig (undefined
symbols get their name as their string value), but look confusing. It's
done inconsistently now too.
Suggested by Kumar Gala.
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
This commit fixes a compilation bug for an undefined variable
(mmfar), which is only conditionally defined. Instead of mmfar
we use the ARM register value directly.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Previously, there was no easy command-line solution for loading
a Zephyr program to (internal) flash.
So, the default development method was to load via gdb/openocd
to SRAM and debug from there, thus making the cc3220sf platform
non-XIP (CONFIG_XIP=n) by default.
With new openocd v 1.10 updates from TI (git.ti.com/sdo-emu),
the image can now be flashed and debugged via gdb/openocd,
so the default will be changed to XIP (CONFIG_XIP=y).
Signed-off-by: Gil Pitney <gil.pitney@linaro.org>
Enable supporting UART4 on STM32F107 and STM32F103Xe SoCs.
Modified stm32f1/dts.fixup for replacing USART with UART.
Signed-off-by: Jun Li <jun.r.li@intel.com>
LPUART (Low-power UART) peripheral is just like ordinary U(S)ART
which lives in a separate clock/power domain.
Therefore already existing code could be reused as is
almost entirely.
Signed-off-by: Ilya Tagunov <tagunil@gmail.com>
STM32Lx LPUART peripherals do not fit well into existing U(S)ART
port numbering scheme, so there will be two separate namespaces
in Kconfig: one for U(S)ARTs and one for LPUARTs.
Signed-off-by: Ilya Tagunov <tagunil@gmail.com>
The metairq feature exposed the fact that all of our arch code (and a
few mistaken spots in the scheduler too) was trying to interpret
"preemptible" threads independently.
As of the scheduler rewrite, that logic is entirely within sched.c and
doing it externally is redundant. And now that "cooperative" threads
can be preempted, it's wrong and produces test failures when used with
metairq threads.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Refactor the _FaultDump of the default debug-level (2) to
provide the error code that indicates the fatal error reason.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Refactor FAULT_DUMP macro to obtain and store the fatal error
reason. Make non-default version of FAULT_DUMP (i.e. with
CONFIG_FAULT_DUMP level 1) to retrieve the default reason
for fatal errors (_NANO_ERR_HW_EXCEPTION).
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Document that execution does not return from
_NanoFatalErrorHandler and _SysFatalErrorHandler.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
The PPB, Peripheral, and any other I/O regions have been
removed, the Shareable options are only important with
unlocked dual cores. Just use the background mapping,
which is RWX for supervisor and no access for user mode.
The flash region needs to be kept to indicate read-only
policy. The RAM regions need to be kept to disable execution.
Fixes#6896
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
The PPB and Peripheral regions have been removed,
the Shareable options are only important with unlocked
dual cores. Just use the background mapping.
The flash region needs to be kept to indicate read-only
policy. The RAM regions need to be kept to disable execution.
Related to #6896 and #7877
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
The STM32L432 SoC has a standard non-OTG USB controller. Add an entry
for it in stm32l432.dtsi and add the corresponding DTS fixup entries.
The controller is kept disabled and should be enabled at the board
level.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
USB OTG is currently enable for the whole STM32L4 family, while only a
few of them actually support it:
- STM32L475, STM32L476 and STM32L496 have an OTG controller
- STM32L432, STM32L433 and STM32L452 have an USB controller
- STM32L431, STM32L451 and STM32L471 do not have any USB controller
Fix that by moving the DT entry from stm32l4.dtsi to stm32l475.dtsi
and by adding a #ifdef #endif around the corresponding DTS fixup
entries.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
When the RTC support get added we had a select on HAS_RTC, however this
Kconfig symbol didn't exist. Clean this up to match the pattern of
HAS_MCUX_RTC. The driver now depends on that and the SoC selects it.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Some code was developped around MPU support in ealy stage
of feature introduction. This code was gated under MPU_ENABLE
flag which does not exist and hence code has never been
enabled nor tested.
Since there has been futher MPU development since then, it seems
safer to simply remove that code and associated Kconfig symbols
to avoid that someone starts using it while it was not part of
MPU development track.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Remove unused context switch code from the helper assembly file that
manages the SuperVisor Call invocations (SVCs). This is no longer in use
in the code, since all calls to __swap() now go through PendSV directly.
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
The initial user stack pointer gets rounded to STACK_ALIGN_SIZE,
which can be much finer granularity than MPU regions. With
certain stack size values passed to k_thread_create(), the stack
pointer can be set past the defined region for the user thread's
stack, causing an immediate MPU fault.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Upon return from a syscall handlers, the r1, r2, and r3 registers
could contain random kernel data that should not be leaked to user
mode. Zero these out before returning from _arm_do_syscall().
Fixes#7753.
The invocation macros need a clobber if r1, r2, or r3 are not used
to carry syscall arguments. This is a partial fix for #7754 but
there appear to be other issues.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Recent change to RTC core now gets CONFIG_RTC_0_NAME from device tree.
So we need a fixup for KW41Z for that.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The kl25z does not have the same spi hardware as the k64f and therefore
cannot use the same spi driver. Remove all references to spi for the
kl25z soc and frdm_kl25z board until we have a valid spi driver.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Add driver for MCUX mailbox which can be used for lpcxpresso54114
and other lpc and kinetis socs.
Origin: Original
Signed-off-by: Stanislav Poboril <stanislav.poboril@nxp.com>
Added ability to load and bootup the slave (Cortex-M0+) core on the
LPC54xxx SoC. Currently we expect a binary image to be specified via
Kconfig for the code that will run on the slave core. We also specify
via Kconfig the boot/load address for the slave core.
Origin: Original
Signed-off-by: Stanislav Poboril <stanislav.poboril@nxp.com>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add soc configuration support and dts files for nxp_lpc54xxx_m0.
Adjusted nxp_lpc54xxx soc, configuration and dts files for the
presence of slave core.
Origin: Original
Signed-off-by: Stanislav Poboril <stanislav.poboril@nxp.com>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This patch adds the configuration, driver, and HAL changes required
to implement a MCUX based RTC driver for the NXP Kinetis KW41Z.
Signed-off-by: Andy Gross <agross@kernel.org>
This patch adds some DTS information to flesh out the NXP Kinetis
based RTC blocks. DTS fixups were added as well to match up the driver
usage to the DTS output.
Signed-off-by: Andy Gross <agross@kernel.org>
Declare and implement convenience wrappers to evaluate read and
write permissions of C variables using the cmse address range
intrinsics.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit contributes the implementation of the
CMSE address range permission checks based on the
ARMv8-M address range check intrinsics.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Select CPU_CORTEX_M_HAS_CMSE in ARMV8_M arhitectures.
Option ARMV8_M_BASELINE is introduced for this purpose,
so that CMSE API is enabled for both Cortex-M23 and
Cortex-M33 MCUs.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit defines and implements an internal ARMv8-M API
that allows the user to evaluate access permissions of memory
locations, based on the ARMv8-M Test Target (TT) instruction
support.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Kconfig keyword GPIO_AS_PINRESET is common for whole nrf52 series.
This patch move it to the series Kconfig.soc file.
Signed-off-by: Andrzej Puzdrowski <andrzej.puzdrowski@nordicsemi.no>
It is possible to use NFCT pins as regular GPIOs.
This patch introduce option for enabling this feature.
Signed-off-by: Andrzej Puzdrowski <andrzej.puzdrowski@nordicsemi.no>
Enabling the driver on board level is sufficient. We need to find a
better way for selecting random drivers on SoC level, this is currently
not possible due to how Kconfig works.
Fixes#7097
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The instructions performed by standard Zephyr startup files are removed
from the file startup_LPC54114_cm4.S. Introduced the section
_PlatformInit which will be called when platform specific initialization
is needed.
Signed-off-by: Stanislav Poboril <stanislav.poboril@nxp.com>
Rename various SoC related defines and files from just being LPC54114
to LPC54114_M4. This is in prep for supporting a build for the second
core on the LPC54114 (the Cortex-M0+).
* Renamed Kconfig SOC_LPC54114 to SOC_LPC54114_M4
* Renamed Kconfig.defconfig.lpc54114 to Kconfig.defconfig.lpc54114_m4
* Introduced nxp_lpc54xxx_m4.dtsi based on nxp_lpc54xxx.dtsi
* Moved some pinmux related defines into SoC code.
Signed-off-by: Stanislav Poboril <stanislav.poboril@nxp.com>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add the ability to call platform specific code as the first thing we do.
This is needed because on some platforms we might have to figure out how
to deal with starting up secondary cores and need to do that as the
first thing we do.
Signed-off-by: Stanislav Poboril <stanislav.poboril@nxp.com>
Normally a syscall would check the current privilege level and then
decide to go to _impl_<syscall> directly or go through a
_handler_<syscall>.
__ZEPHYR_SUPERVISOR__ is a compiler optimization flag which will
make all the system calls from the arch files directly link
to the _impl_<syscall>. Thereby reducing the overhead of checking the
privileges.
In the previous implementation all the source files would be compiled
by zephyr_source() rule. This means that zephyr_* is a catchall CMake
library for source files that can be built purely with the include
paths, defines, and other compiler flags that all zephyr source
files uses. This states that adding one extra compiler flag for only
one complete directory would fail.
This limitation can be overcome by using zephyr_libray* APIs. This
creates a library for the required directories and it also supports
directory level properties.
Hence we use zephyr_library* to create a new library with
macro _ZEPHYR_SUPERVISOR_ for the optimization.
Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
Distinguish between the integrity signatures depending on whether the
ARM MCU implements the Floating-Point Extension or not.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit partially reworks the fault dump implementation
of faults in non-secure state that target Secure state. In
particular, the return address to secure state is logged along
with the non-secure address which caused the non-secure fault
(that targets the Secure state).
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Fix bug when setting SCB_AIRCR during initialization; add
Vector Key to permit write to AIRCR fields.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit contributes the Secure fault handling for ARMv8-m
implementations, that do not support the Main Extension, such
as the (Baseline) Cortex-M23 processor.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Commit introduces support for watchdog configuration for Nordic
Semiconductor nRF SoCs in device tree.
Signed-off-by: Karol Lasończyk <karol.lasonczyk@nordicsemi.no>
Enable System Configuration Controller clock in clock_control
instead of gpio controller when we set a gpio as interrupt.
We use System Configuration Controller to manage external
interrupts and enable PIN pair PA11/12, used in USB device,
mapped instead of PA9/10.
Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
Enable System Configuration Controller clock in clock_control
instead of gpio controller when we set a gpio as interrupt.
We use System Configuration Controller to manage external
interrupts and internal voltage reference for 48 MHz HSI
used in USB device.
Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
STM32Cube HAL core initialization functions HAL_GetTick()
and HAL_Delay() are implemented in all STM32 series. This
patch moves these functions in file stm32cube_hal.c under
"common" folder to reduce code duplication.
Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
Adds dts bindings for the mcr20a wireless transceiver. The frdm_k64f
board supports the mcr20a via an Arduino shield, therefore the dts node
is added to the board dts. The kw2xd is a SiP and thus the mcr20a dts
node is added to the soc dts.
The networking samples using prj_frdm_k64f_mcr20a.conf have been broken
since the refactoring of the mcux gpio driver to dts in commit
4e8f29f319. The sample is now fixed.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
The kw40z and kw41z socs have the same dspi peripheral as the k64 and
kw2xd, so we can reuse the existing mcux dspi shim driver.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
With recent dts script change we dropped _0 from define names if there
is only a single one. So for the MPU we need to use
CONFIG_SRAM_BASE_ADDRESS instead of CONFIG_SRAM_BASE_ADDRESS_0.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
When we included SoC specific Kconfig files we do something like:
gsource "arch/arm/soc/arm/*/Kconfig.soc"
However, we should do that inside an if block for that SoC family so as
to limit SoC family specific options to only being visible when that SoC
family is selected. So we simply move the gsource and related items
inside the if SOC_FAMILY_<SOC> block.
Fixes: #7452
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
In order to disable the execution of code from the RAM region
we need to declare it in arm_mpu_regions.c file.
Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
In dts.fixup files for used for NXP SoCs, IP clock name was
bound to SIM clock label. This is correct but would require
manual change if IP clock controller was changed in device tree.
Use reference to IP generated define "_CLOCK_CONTROLLER" to get
this value.
Besides, having all IP related values starting with the same prefix
will be easier for possible macro preprocessing (if required one day).
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
'cell_string' yaml attribute has been introduced in order to
help enforcement of specific string during defines generation.
This adds complexity in understanding script behavior as a black
box and create additional dependency which is not strictly required.
For node specific generation functions (pinctrl and interrupts),
this could be replaced directly by an hardcoded version
(as everyone used the same 'cell_string' anyway).
For extract_cells functions, string could be replaced by extracted
property name. As a consequence, we're now able to generate defines
for properties refering to these controllers via phandle.
For instance, in following node
spbtle-rf@0 {
compatible = "st,spbtle-rf";
reg = <0>;
reset-gpios = <&gpioa 8 0>;
};
We'll be able to generate:
#define ST_STM32_SPI_...LE_RF_0_RESET_GPIOS_CONTROLLER "GPIOA"
#define ST_STM32_SPI_...PBTLE_RF_0_RESET_GPIOS_FLAGS_0 0
#define ST_STM32_SPI_..._SPBTLE_RF_0_RESET_GPIOS_PIN_0 8
Only impact for this whole change is for NXP clocks which were the
only ones using 'cell_string' attribute with a value different than
the default one.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Indexed defines were systematically generated even when there
was only one element to generate.
So we ended up generated a lot of _0 defines.
Then we needed to generate aliases to these _0 indexed defines,
in order to get useful defines.
For instance:
#define GPIO_LEDS_0_GPIO_FLAGS_0 4
#define GPIO_LEDS_0_GPIO_PIN_0 5
#define GPIO_LEDS_0_GPIO_FLAGS GPIO_LEDS_0_GPIO_FLAGS_0
#define GPIO_LEDS_0_GPIO_PIN GPIO_LEDS_0_GPIO_PIN_0
This commit allows to generate _0 indexed define only if a
property has more than one elements to define.
Aliases generation to _0 indexed defines are also removed.
Note: IRQ are left untouched since this is frequent to handle
multiple IRQs in a driver
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This commit implements consistency checks for the core registers
in ARMv6-M, ARMv7-M, and ARMv8-M architectures, ensuring that
the user cannot accidentally select registers that are not
implemented by the selected Cortex-M processor.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
The commit improves the help text of the ARMV7_M_ARMV8_M_MAINLINE
K-config option.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit adds a Context Synchronization Point immediately
after the reset handler switches to use the Process Stack
Pointer, during initialization.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Adds 8 MB and 64 MB flash size options, which correspond to the two
external flashes (qspi flash and hyperflash) on the mimxrt1050_evk
board. Adds a 32 MB SRAM size option, which corresponds to the external
sdram on the board.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
The API in the current SDK version is rom-patched, and uses
prcm.c code in the driverlib directory.
But, the PRCMMCU3200Init() API call should be prefixed by MAP_
to allow the option to use the ROM API in a future TI SDK version.
Signed-off-by: Gil Pitney <gil.pitney@linaro.org>
The loop that checks the MPU region permissions incorrectly
iterates from (num_region + 1) to 1. This should be
(num_region - 1) to 0. This results in the wrong regions
being checked and possible overflow for any implementation
that uses the max region value of 0xFF.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Until now, Zephyr has used a patched Kconfiglib that turns 'source' into
a globbing source (by replacing 'source' with 'gsource' at the token
level). There's two problems with this:
- The patch needs to be maintained separately
- Misspelled filenames are silently ignored, as they look like glob
patterns that don't match anything
Fix it as follows:
1. Replace all 'source' statements that use wildcards with 'gsource'
2. Remove the custom Kconfiglib patch so that 'source' no longer globs
The sed pattern '/source.*[*?]/s/source/gsource/' was run over all
Kconfig* files to do the replacement.
source's that use environment variables that might contain glob patterns
were manually changed to gsource.
Building the docs in doc/ is a good test, as doc/Makefile deliberately
sets the environment variables to glob up as many Kconfig files as
possible.
Signed-off-by: Ulf Magnusson <ulfalizer@gmail.com>
This commit activates the built-in stack guard on the main_thread
before jumping to it upon system initialization. Stack guard is
activated if BUILTIN_STACK_GUARD is enabled by the user. The
commit also activates built-in thread stack guards at every
context switch, if BUILTIN_STACK_GUARD enabled by the user.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Ignore stack pointer limit checking during a HardFault or NMI
exception, to allow for the Fault handling function to execute
properly.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit implements the build-in interrupt stack protection
via the native MSPLIM register in ARMv8-M MCUs that support the
Main Extension. Main stack pointer overflows will cause Stack
Overflow UsageFaults. In addition, the commit introduces a new
config option, BUILTIN_STACK_GUARD, allowing the user to enable
and use the built-in stack protection in ARMv8-M firmware.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This patchset provides Xtensa's xcc compiler support for Xtensa
projects in Cmake. This requires the below environment variables
to be defined aptly. The appropriate xcc license information also
need to be supplied.
ZEPHYR_GCC_VARIANT=xcc
TOOLCHAIN_VER=RF-2015.3-linux
XTENSA_CORE=cavs21_LX6HiFi3_RF3_WB16
XTENSA_SYSTEM=/opt/xtensa/XtDevTools/install/tools/
RF-2015.3-linux/XtensaTools/config/
XTENSA_BUILD_PATHS=/opt/xtensa/XtDevTools/install/builds/
Change-Id: Ib3c10e8095439b0e32276ff37c00eca8420773ec
Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Some of the SoCs specify "Enable MPU" in Kconfig for enabling MPU
support. This will create ambiguity while selecting options via
menuconfig. Hence, append SoC family name to the selection strings
to looks more elaborative.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
The title for selecting the configuration options for SoC's should be
"SoC Configuration" not "Board Configuration".
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Improve the help text of ARM k-config option
CPU_CORTEX_M_HAS_PROGRAMMABLE_FAULT_PRIOS.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
It seems like SEGGER is supported across all the NXP SoC families so
lets enable it across all of them.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
We have been combining imported mcux drivers into a flattened directory
structure to maximize driver reuse, but the introduction of additional
nxp soc families (lpc and imx) to zephyr has introduced driver naming
conflicts. This caused us to rename and modify imported files, such as
fsl_gpio.c/h, to make them unique across all three nxp soc families.
This makes updating the the mcux drivers complicated, especially for the
lpc family.
Reoganize the mcux drivers into soc family subfolders, so we can just
copy all the drivers from an mcux distribution (which is done on an
soc-basis) into the appropriate soc family folder. Undo all of the
naming changes that occurred when lpc and imx drivers were originally
imported. Undo the accidental squashing of the kinetis watchdog and dcdc
drivers that occurred when the imx drivers were introduced.
The drawback to this approach is that we have duplicate files when the
same hw ip modules exist in multiple soc families, however there are
only few cases where this occurs, such as fsl_lpuart and fsl_trng.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Now that other work has eliminated the two cases where we had to do a
reschedule "but yield even if we are cooperative", we can squash both
down to a single _reschedule() function which does almost exactly what
legacy _Swap() did, but wrapped as a proper scheduler API.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
There was a somewhat promiscuous pattern in the kernel where IPC
mechanisms would do something that might effect the current thread
choice, then check _must_switch_threads() (or occasionally
__must_switch_threads -- don't ask, the distinction is being replaced
by real English words), sometimes _is_in_isr() (but not always, even
in contexts where that looks like it would be a mistake), and then
call _Swap() if everything is OK, otherwise releasing the irq_lock().
Sometimes this was done directly, sometimes via the inverted test,
sometimes (poll, heh) by doing the test when the thread state was
modified and then needlessly passing the result up the call stack to
the point of the _Swap().
And some places were just calling _reschedule_threads(), which did all
this already.
Unify all this madness. The old _reschedule_threads() function has
split into two variants: _reschedule_yield() and
_reschedule_noyield(). The latter is the "normal" one that respects
the cooperative priority of the current thread (i.e. it won't switch
out even if there is a higher priority thread ready -- the current
thread has to pend itself first), the former is used in the handful of
places where code was doing a swap unconditionally, just to preserve
precise behavior across the refactor. I'm not at all convinced it
should exist...
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Contrary to ARMv7-M, in ARMv8-M MCUs with the Main Extension,
BusFault Status Register bits are sticky and must be cleared.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This patch changes the ARM system calls to use registers for passing
or arguments. This removes the possibility of stack issues when
callers do not adhere to the AAPCS.
Fixes#6802
Signed-off-by: Andy Gross <andy.gross@linaro.org>
During the transition of privilege levels while performing syscalls,
the ARM documentation recommends flushing the pipeline to avoid
pre-fetched instructions from being executed with the previous
privilege level.
The manual says:
4.16 CONTROL register
(...) after programming the CONTROL register, an ISB instruction
should be used.
(...) This is not implemented in the Cortex M0 processor.
Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
The TRNG IP block in the KW41Z is really an entropy source and not
intended to be used as a general purpose random number generator
source. The block has 15 slots to read from and when the last slot
is read it has to regenerate the 15 numbers. This process takes
3-5 seconds and is blocking. The change here is to use the TRNG as
an entropy source to the XOROSHIRO pseudo random number function
and then have the KW41Z use XOROSHIRO for random number generation.
Signed-off-by: David Leach <david.leach@nxp.com>
- Removed OT_PLAT_RADIO_DEVICE_NAME
- Changed OpenThread binding to use NET_AP_IEEE802154_DEV_NAME
- Modified Kconfig chain to ensure NET_AP_IEEE802154_DEV_NAME
is enabled for both native 802.15.4 and OpenThread configurations
- Changed default setting of NET_L2_IEEE802154 in defconfig for mkw41z4.
- Fixed OpenThread api support code to use the state of mIsCcaEnabled
in the transmit frame to conditionally invoke radio_api->cc() on
transmits.
Signed-off-by: David Leach <david.leach@nxp.com>
The i.MX7 SoC is a Hybrid multi-core processor composed by Single/Dual
Cortex A7 core and Single Cortex M4 core.
Zephyr was ported to run on the M4 core. In a later release, it will
also communicate with the A7 core (running Linux) via RPmsg.
The low level drivers come from NXP FreeRTOS BSP and are located at
ext/hal/nxp/imx. More details can be found at ext/hal/nxp/imx/README
The A7 core is responsible to load the M4 binary application into the
RAM, put the M4 in reset, set the M4 Program Counter and Stack Pointer,
and get the M4 out of reset.
The A7 can perform these steps at bootloader level after the Linux
system has booted.
The M4 can use up to 5 different RAMs. These are the memory mapping for
A7 and M4:
+---------------+-----------------+---------------------------+
| Memory Name | Start Address | Size |
+===============+=================+===========================+
| TCML | 0x007F8000 | 32KB |
+---------------+-----------------+---------------------------+
| TCMU | 0x20000000 | 32KB |
+---------------+-----------------+---------------------------+
| OCRAM_S | 0x20180000 | 32KB |
+---------------+-----------------+---------------------------+
| OCRAM | 0x00900000 | 128KB |
+---------------+-----------------+---------------------------+
| DDR | 0x10000000 | 256MB |
+---------------+-----------------+---------------------------+
Signed-off-by: Diego Sueiro <diego.sueiro@gmail.com>
All boards based on STM32 should use dts for I2C and SPI.
Move CONFIG flags selection from boards to arch and select them
for all STM32 SoCs.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
srd bits start at bit 8, not bit 5.
To date we are not using sub-regions so this problem was
undetected.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Ports F and G are not present on some STM32L0 parts, so
for these parts port H external interrupt should be enabled
by writing value 0x5 instead of 0x7 to SYSCFG_EXTICRn registers
(see e.g. RM0367, 10.2.4).
Signed-off-by: Ilya Tagunov <tagunil@gmail.com>
Removing ${} variable evaluation fixes the issue.
For sam4s_xplained:
Before:
/repos/zephyr/samples/hello_world/build$ make VERBOSE=1 | grep march
/repos/zephyr/samples/hello_world/build$
After:
/repos/zephyr/samples/hello_world/build$ make VERBOSE=1 | grep march
...
-mthumb -mcpu=cortex-m4 -march=armv7e-m
...
Signed-off-by: Paolo Teti <paolo.teti@gmail.com>
Move driver specific to dedicated file when relevant (i.e.: more than
1-2 options), use if/endif also.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
A previous commit had mistakenly overwritten the copyright years instead
of extending the range. Fix this mistake so that the proper range is
recorded.
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
The existing nrf5_common.h now applies to other Nordic ICs that are not
part of the "5" family. Instead rename this to nrf_common.h to cover the
upcoming ICs that belong to other families.
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
Upcoming Nordic ICs that share many of the peripherals and architecture
with the currently supported nRF5x ones are no longer part of the nRF5
family. In order to accomodate that, rename the SoC family from nrf5 to
nrf, so that it can contain all of the members of the wider Nordic
family.
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
Use HAS_ Kconfig option as intended, those are invisible option that
signify support of a certain feature that can be selected by a hardware
or platform.
For RTT and system view this was not dont in an inconsistent way.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
STM32F0 flash driver already uses FLASH_PAGE_SIZE from HAL
in flash layout part, so CONFIG_FLASH_PAGE_SIZE is redundant
and confusing.
Signed-off-by: Ilya Tagunov <tagunil@gmail.com>
Move the dts.fixup back to board dir in prep for support mps2_an521.
The memory maps between the two mps2_an385 and mps2_an521 differ greatly
so its easier to just keep the fixup files with the board.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Kconfiglib does not support UTF-8 properly yet, so avoid issues by
removing the UTF-8 character from the name until this is fixed.
See https://github.com/ulfalizer/Kconfiglib/pull/41
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
This commit introduces the ARM_SECURE_FIRMWARE k-option,
which indicates that we are building an ARM Secure application.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit contributes the implementation of the SecureFault
handling for ARMv8-M-based Cortex-M33. The implementation is
compiled conditionally with compile-time directive
CONFIG_ARM_SECURE_FIRMWARE, which is to signify the intention to
build a Secure image on ARMv8-M with Security Extensions.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Add initial support for STM32L073xZ SOC which is not very different
from already supported STM32L072xZ.
Signed-off-by: Ilya Tagunov <tagunil@gmail.com>
SoC dts fixups are added and the i2c_nrf5 driver is modified to use
the values generated from the device tree.
The I2C_*_DEFAULT_CFG and I2C_*_IRQ_PRI options are removed from board
defconfigs. Bitrate and IRQ priority are configured using using the
device tree instead.
HAS_DTS_I2C is selected on all nrf5 boards to prevent generation of
conflicting defines from Kconfig.
Signed-off-by: Aapo Vienamo <aapo.vienamo@iki.fi>
This commit removes the unnecessary asm inline header for ARM.
It also adapts the stack.h and exc.h to use the ARM CMSIS inline
functions to access the IPSR and MSP registers.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit conditionally selects the ARMV7_M_ARMV8_M_FP option
in ARMv7-M/ARMv8-M Mainline processors, when the Floating Point
Extension is implemented (CPU_HAS_FPU is selected).
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit contributes the Stack Overflow UsageFault dumping
for ARMv8-M implementations that support the Main Extension.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit introduces the ARMV8_M_MAINLINE K-config option. The
option signifies the use of an ARMv8-M CPU supporting the Main
Extension. ARMv8-M Main Extension includes additional features
that are not present in the ARMv7-M architecture.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit forces CPU_CORTEX_M_HAS_PROGRAMMABLE_FAULT_PRIOS to
depend on ARMV7_M_ARMV8_M_MAINLINE. This allows the user to get
a build warning if he manually selects
CPU_CORTEX_M_HAS_PROGRAMMABLE_FAULT_PRIOS for a CPU that does
not implement either ARMv7-M or ARMv8-M Mainline.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Move IRQ numbers into device tree so we can remove soc_irq.h. We are
already using IRQ defines generated form the DTS so no point in having
soc_irq.h
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Further simplify the mps2 SoC code by removing soc_memory_map.h which
now only contains one define for the FPGAIO_BASE_ADDR. We can just move
this to the once place its used.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Added device tree support to the ARM SBCon I2C controller. We utilize
the compatiable "arm,versatile-i2c" the binding from Linux for the some
peripheral block.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Clean up Kconfig so each SoC just selects the specific Cortex-M
implementaiton rather than having to select both CORTEX_M and
CORTEX_{M0, M3, M4, etc.}.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit adds the missing fault dumping for MemManage or Bus
fault occuring during floating-point lazy state preservation. In
addition, it introduces a Kconfig option for the ARMv7-M/ARMv8-M
Floating Point Extension.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This commit removes the macros for ARM fault flags from
include/arch/arm/cortex_m/cmsis.h header, since they are
defined in the respective core_cmXX.h header files. It also
modifies fault.c to use the updated fault macros taken directly
from ARM CMSIS headers.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Switch the SoC device tree to define a single entry per SERCOM instead
of one per mode.
Define a Device Tree binding for the SAM0 SPI and use it instead of
Kconfig for enabling / disabaling instances
Switch the Arduino Zero, Adafruit Feather M0 Basic Proto, and
Trinket M0 to use the new defintion.
Add the APA102 LED that's on the Trinket as a test.
Signed-off-by: Michael Hope <mlhx@google.com>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This patch reworks the current ARM __swap() function into a C function.
Due to some issues with using svc calls withing fault handlers, we
needed to change the way we initiate a swap by removing the dependence
on svc #0.
Before __swap() is called, the system has already done an irq_lock().
Upon return from __swap(), the equivalent of an irq_lock() is done due
to restoration of the key value from the irq_lock preceeding the call.
For ARM V6M (M0/M0+), the pendsv bit is toggled and the irqs are
enabled. There is no priority masking in v6m, so it's just a global
enable. For ARM V7M, the priority mask has to be set to 0x0 to allow
for the pendsv IRQ to be taken. This is done for both via a call to
irq_unlock(0).
After this unlock, a pendsv irq will be taken, either at the tail end
of the current irq handling if we are in handler mode, or immediately
due to the pendsv being asserted (no other outstanding irqs). The next
thread will be scheduled.
Upon return from the context switch to the original
thread, the priority mask will already be correct due to the pendsv
processing.
Signed-off-by: Andy Gross <andy.gross@linaro.org>
MPU_STACK_GUARD option has a direct dependence on ARM_CORE_MPU.
Therefore, it is not required to have a conditional selection
of the option (if ARM_CORE_MPU) in ARM_STACK_PROTECTION.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
In ARMv7-M (and ARMv8-M) architecture it is
implementation defined whether separate MMFAR and BFAR are
implemented. This commit ensures that we always get the true
faulting address displayed in case of MemManage- or BusFault.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Move common SoC dts.fixup defines into arch/arm/soc/<SOC>/dts.fixup so
we remove duplication in the boards and only have board specific
defines in boards/arm/<FOO>/dts.fixup.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Move common SoC dts.fixup defines into
arch/arm/soc/atmel_sam/<BAR>/dts.fixup so we remove duplication in the
boards and only have board specific defines in
boards/arm/<FOO>/dts.fixup.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Move common SoC dts.fixup defines into arch/arm/soc/nxp_imx/rt/dts.fixup
so we remove duplication in the boards and only have board specific
defines in boards/arm/<FOO>/dts.fixup.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Move common SoC dts.fixup defines into
arch/arm/soc/nxp_kinetis/kwx/dts.fixup so we remove duplication in
the boards and only have board specific defines in
boards/arm/<FOO>/dts.fixup.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Move common SoC dts.fixup defines into
arch/arm/soc/nxp_kinetis/kl2x/dts.fixup so we remove duplication in
the boards and only have board specific defines in
boards/arm/<FOO>/dts.fixup.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Move common SoC dts.fixup defines into
arch/arm/soc/nxp_lpc/lpc54xxx/dts.fixup so we remove duplication in
the boards and only have board specific defines in
boards/arm/<FOO>/dts.fixup.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Move common SoC dts.fixup defines into
arch/arm/soc/nxp_kinetis/k6x/dts.fixup so we remove duplication in the
boards and only have board specific defines in
boards/arm/<FOO>/dts.fixup.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Move common SoC dts.fixup defines into
arch/arm/soc/ti_simplelink/<BAR>/dts.fixup so we remove duplication in
the boards and only have board specific defines in
boards/arm/<FOO>/dts.fixup.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Add SPI fixup defines on STM32 SoC family level for all SPIs that
are supported on one or more SOCs of that SoC family.
Signed-off-by: Daniel Wagenknecht <wagenknecht.daniel@gmail.com>
The xtensa-asm2 work included a patch that added nano_internal.h
includes in lots of places that needed to have _Swap defined, because
it had to break a cycle and this no longer got pulled in from the arch
headers.
Unfortunately those new includes created new and more amusing cycles
elsewhere which led to breakage on other platforms.
Break out the _Swap definition (only) into a separate header and use
that instead. Cleaner. Seems not to have any more hidden gotchas.
Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
Fix Kconfig help sections and add spacing to be consistent across all
Kconfig file. In a previous run we missed a few.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The old ARMV6_M Kconfig option has been removed, and so to correctly set
the dependencies for SW_VECTOR_RELAY we need to use the new
ARMV6_M_ARMV8_M_BASELINE.
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
This patch fixes a hole in the stack guard configuration. The initial
branch to main is missing the stack guard configuration.
Fixes: Issue #3718
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This patch fixes calculations for the top of the interrupt and main
stacks. Due to power of two alignment requirements for certain MPUs,
the guard size must be taken into account due to the guard being
counted against the initial stack size.
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This patch adds support for userspace on ARM architectures. Arch
specific calls for transitioning threads to user mode, system calls,
and associated handlers.
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This patch adds a configure_mpu_user_context API and implements
the required function placeholders in the NXP and ARM MPU files.
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Atmel SAMD21 series was classified too broadly as SAMD.
This patch names it correctly to make room,
for other members of SAMD series
Signed-off-by: Sean Nyekjaer <sean@nyekjaer.dk>
Also pull out the SERCOM pads configuration to defines. Note that the
SAM0 has a two level configuration - a signal (like TX) is mapped to a
pad, and then a pad is mapped to a function on a pin.
Signed-off-by: Michael Hope <mlhx@google.com>
This commit defines the Kconfig options for
ARM Cortex-M23 and Cortex-M33 CPUs. It also
udpates the generic memory map for M23 and M33
implementations.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
This PR includes the required changes in order to support
conditional compilation for Armv8-M architecture. Two
variants of the Armv8-M architecture are defined:
- the Armv8-M Baseline (backwards compatible with ARMv6-M),
- the Armv8-M Mainline (backwards compatible with ARMv7-M).
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Whenever a Cortex-M0+ supports the VTOR register it makes no sense to
use the software vector relay mechanism. Therefore change the logic so
that SW_VECTOR_RELAY does not get enabled whenever a VTOR register is
present, but enable it if an M0+ has no VTOR.
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
This patch adds the generation and incorporation of privileged stack
regions that are used by ARM user mode threads. This patch adds the
infrastructure for privileged stacks. Later patches will utilize the
generated stacks and helper functions.
Signed-off-by: Chunlin Han <chunlin.han@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Replace seldom occurrences of FLASH_DRIVER_NAME by equivalent
and commonly used FLASH_DEV_NAME.
Fixes#5919.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Some ARMv6-M Cortex-M0+-based SOCs have VTOR register
and can relocate vector table just as ARMv7-M ones.
Vector table relocation path should be choosed
by VTOR presence, not by arch.
Signed-off-by: Ilya Tagunov <tagunil@gmail.com>
Defines the FLASH_DRIVER_NAME macro in soc.h for kinetis kl2x and kwx
SoC series. This macro is used by the storage and dfu subsystems, as
well as the flash_shell sample.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Rename the nano_internal.h to kernel_internal.h and modify the
header file name accordingly wherever it is used.
Signed-off-by: Ramakrishna Pallala <ramakrishna.pallala@intel.com>
Currently in zephyr the support for the arm userspace has not be
merged. But the Kconfig always sets the userspace flag and causes a
build failure. This is blocking the test cases for userspace.
Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
Add a new Kconfig option, BOOTLOADER_MCUBOOT, that automatically sets
the required options necessary to make the resulting image bootable by
the MCUboot open source bootloader. This includes the text section
offset and the vector relay table for Cortex-M0, and in the future it
might also add the DTS overlay required to link at slot0 offset in
flash.
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
Add device tree support for the "nxp,kinetis-ftfa" flash controller used
on the NXP KL2X and KW4xZ SoCs.
Fixes: #5788
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Convert NXP k6x and kw2xd flash driver to use device tree to get the
flash controller name from device tree. We introduce yaml bindings for
the "nxp,kinetis-ftfe" and "nxp,kinetis-ftfl" devices.
Fixes: #5788
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
The old HAL and MDK have been removed from the source tree.
Since RADIO HAL is not yet present in nrfx, the "nrf_radio.h" file
was temporarily moved to "nrfx/hal" folder. It will be replaced with
the proper file from nrfx in its next update.
Signed-off-by: Michał Kruszewski <michal.kruszewski@nordicsemi.no>
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
This commit adds a glue layer that adapts nrfx to be usable in Zephyr
as a host environment and files with static configuration of nrfx
drivers for several supported SoCs.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
This moves and merges the existing board-level dts.fixup files
for STM32 L4 SOC family into one soc family level dts.fixup file.
No new fixup blocks have been added, only fixup blocks, that were
part of at least one board level dts.fixup file are present in
soc family level dts.fixup file.
disco_l475_iot1 boards fixup blocks for devices connected via SPI
and I2C stay in board level dts.fixup file, because they are board
specific.
Contributes to #5707
Signed-off-by: Daniel Wagenknecht <wagenknecht.daniel@gmail.com>
This moves and merges the existing board-level dts.fixup files
for STM32 F3 SOC family into one soc family level dts.fixup file.
No new fixup blocks have been added, only fixup blocks, that were
part of at least one board level dts.fixup file are present in
soc family level dts.fixup file.
Contributes to #5707
Signed-off-by: Daniel Wagenknecht <wagenknecht.daniel@gmail.com>
This moves and merges the existing board-level dts.fixup files
for STM32 F1 SOC family into one soc family level dts.fixup file.
No new fixup blocks have been added, only fixup blocks, that were
part of at least one board level dts.fixup file are present in
soc family level dts.fixup file.
Contributes to #5707
Signed-off-by: Daniel Wagenknecht <wagenknecht.daniel@gmail.com>
This moves and merges the existing board-level dts.fixup files
for STM32 F4 SOC family into one soc family level dts.fixup file.
No new fixup blocks have been added, only fixup blocks, that were
part of at least one board level dts.fixup file are present in
soc family level dts.fixup file.
96b_carbon boards fixup block for Bluetooth HCI device via SPI
stays in board level dts.fixup file, because it is board specific.
Contributes to #5707
Signed-off-by: Daniel Wagenknecht <wagenknecht.daniel@gmail.com>
This moves and merges the existing board-level dts.fixup files
for STM32 F0 SOC family into one soc family level dts.fixup file.
No new fixup blocks have been added, only fixup blocks, that were
part of at least one board level dts.fixup file are present in
soc family level dts.fixup file.
Contributes to #5707
Signed-off-by: Daniel Wagenknecht <wagenknecht.daniel@gmail.com>
Convert Atmel SAM0 flash driver to use device tree to get the flash
controller name and base address.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
For SoCs that don't support vector table relocation in hardware, may not
support bootloader like mcuboot.
We introduce a way to relocate vector table in software by forwarding
the control of incoming IRQs to a new vector table which address is save
at fixed SRAM address.
User can change the data in that fixed SRAM address in order to relocate
vector table in software way.
Signed-off-by: Ding Tao <miyatsu@qq.com>
Cortex-M0 do not have the Vector Table Base Address Offset Register, so
Cortex-M0 vector table address can not be changed.
But in some Cortex-M0 SoCs like STM32F0 series, they have some mechanism
that can remap the vector table address to the start address of SRAM.
Use this flag to indicates whether current Cortex-M0 SoC support such a
remap or not.
Signed-off-by: Ding Tao <miyatsu@qq.com>
In order to be able to build MCUboot for nRF51 we require the flash
driver name in the nRF51 soc.h header.
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
So far, DT did not support the flash driver name.
Any flash-controller should have the appropriate
flash driver that should be identified by its name.
This path adds generic support for extract the description
from the flash-controller node,
adds implementation of this property for all nrf5x targets.
Signed-off-by: Andrzej Puzdrowski <andrzej.puzdrowski@nordicsemi.no>
It appears the STM32F411XE doesn't support RNG so remove enabling it
from the SoC defconfig and flag an error if attempting to build the
driver on that SoC.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
In STM32 family, RNG IP is available only on F4 and L4 series.
Besides STM32F401 does not support is neither.
Get entropy driver available on STM32 devices supporting it and
generate a compilation issue on STM32 devices that do not own
the RNG IP.
Solves #5448
Signed-Off-By: Erwan Gouriou <erwan.gouriou@linaro.org>
When asserts are enabled we run into an issue with newlib and types of
printf style formatters not matching. The easy fix to this is to cast
the uint32_t to u32_t to make things consistent with or without newlib
enabled.
This fixes#5645
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Instead of accessing the environment variable ZEPHYR_BASE every time we
require accessing the source code root, use an intermediate variable
that has OS path separators correctly set to '/' to avoid issues on
Windows.
Note: This removes the ZEPHYR_SOURCE_DIR CMake variable. External
applications using that will need to change to use the new ZEPHYR_BASE
variable.
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
Current STM32 SoC initialization code sets really weird startup values
to SystemCoreClock. It should be consistent with Reference Manuals after
this change.
Signed-off-by: Ilya Tagunov <tagunil@gmail.com>
Include low level random generator header in case stm32 random number
generator should be used by entropy driver
Signed-off-by: Jan Van Winkel <jan.van_winkel@dxplore.eu>
Was ARM specific and could not be used by other architectures.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Signed-off-by: Alberto Escolar Piedras <alpi@oticon.com>
Add an architecure specfic code for the memory domain
configuration. This is needed to support a memory domain API
k_mem_domain_add_thread.
Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
Enable USB OTG support for olimex stm32-e407 and stm32f407g_disc1
boards by adding USB OTG to the pinmux table. Also, fix out of
range endpoint addresses in CDC ACM case for STM32F4 based boards.
Signed-off-by: Sudarsana Nagineni <sudarsana.nagineni@intel.com>
The exticrX registers were shifted by a word, so configuring
an EXTI line on a port different of PA misconfigured the EXTI line
source and could flood with unwanted events.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Added Inter-IC Sound driver (based on SSC module) for Atmel
SAM MCU family.
Tested on Atmel SMART SAM E70 Xplained board
Origin: Original
Jira: ZEP-2509
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
Added DMA (XDMAC) driver for Atmel SAM MCU family. The driver provides
private DMA API to be used by the SAM family device drivers. Public
DMA API to be used by user space programs is currently missing.
Tested on Atmel SMART SAM E70 Xplained board
Origin: Original
Jira: ZEP-1609
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
Not all boards require the various binary formats zephyr generates. So
be selective based on the arch, SoC or board and only geenrate the
binaries actually needed.
Fixes#5009
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Implement API to validate user buffer. This API will iterate
all MPU regions to check if the given buffer is user accessible
or not. For #3832.
Signed-off-by: Chunlin Han <chunlin.han@linaro.org>
Unlike other NXP SoCs currently in Zephyr, the mimxrt1052 has the ARM
MPU rather than the NXP MPU. Start out by enabling it with a simple set
of memory regions for "flash" (ITCM), "ram" (DTCM), and the peripheral
buses. More regions will need to be added when we implement support for
external memories.
Tested with:
- samples/mpu/mpu_stack_guard_test
- tests/kernel/mem_protect/protection
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Adds the mimxrt1052 SoC, which belongs to a new family (nxp_imx) and
series (rt) of SoCs. The mimxrt1052 integrates an Arm Cortex-M7 core,
512 KB TCM, and many peripherals including 2D graphics, an LCD display
controller, camera interface, SPDIF and I2S. Unlike other SoCs in
Zephyr, the mimxrt1052 has no internal flash.
This initial port to mimxrt1052 configures the system clock to operate
at 528 MHz, and enables the serial/uart and gpio interfaces to support
the hello_world and blinky samples. Support for additional Zephyr driver
interfaces will come later.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Introducing CMake is an important step in a larger effort to make
Zephyr easy to use for application developers working on different
platforms with different development environment needs.
Simplified, this change retains Kconfig as-is, and replaces all
Makefiles with CMakeLists.txt. The DSL-like Make language that KBuild
offers is replaced by a set of CMake extentions. These extentions have
either provided simple one-to-one translations of KBuild features or
introduced new concepts that replace KBuild concepts.
This is a breaking change for existing test infrastructure and build
scripts that are maintained out-of-tree. But for FW itself, no porting
should be necessary.
For users that just want to continue their work with minimal
disruption the following should suffice:
Install CMake 3.8.2+
Port any out-of-tree Makefiles to CMake.
Learn the absolute minimum about the new command line interface:
$ cd samples/hello_world
$ mkdir build && cd build
$ cmake -DBOARD=nrf52_pca10040 ..
$ cd build
$ make
PR: zephyrproject-rtos#4692
docs: http://docs.zephyrproject.org/getting_started/getting_started.html
Signed-off-by: Sebastian Boe <sebastian.boe@nordicsemi.no>
Added architecture specific support for memory domain destroy
and remove partition for arm and nxp. An optimized version of
remove partition was also added.
Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
Add support for nrf52 series SOC. This patch Adds :-
1. Architecture specific Power Management APIs.
2. APIs for invoking various Power Management tasks into nrf52.
Signed-off-by: Youvedeep Singh <youvedeep.singh@intel.com>
Remove defines for IRQs we don't use. We should be getting this from DT
so this gives us a list of what we need to cleanup. Remove various
memory address offset defines to the ones we actually use.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This adds CONFIG_EXECUTE_XOR_WRITE, which is enabled by default on
systems that support controlling whether a page can contain executable
code. This is also known as W^X[1].
Trying to add a memory domain with a page that is both executable and
writable, either for supervisor mode threads, or for user mode threads,
will result in a kernel panic.
There are few cases where a writable page should also be executable
(JIT compilers, which are most likely out of scope for Zephyr), so an
option is provided to disable the check.
Since the memory domain APIs are executed in supervisor mode, a
determined person could bypass these checks with ease. This is seen
more as a way to avoid people shooting themselves in the foot.
[1] https://en.wikipedia.org/wiki/W%5EX
Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
This should clear up some of the confusion with random number
generators and drivers that obtain entropy from the hardware. Also,
many hardware number generators have limited bandwidth, so it's natural
for their output to be only used for seeding a random number generator.
Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
Some "random" drivers are not drivers at all: they just implement the
function `sys_rand32_get()`. Move those to a random subsystem in
preparation for a reorganization.
Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>
The CLOCK_CONTROL config option is already defined in
drivers/clock_control, so there's no need to redefine it in arch/.
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
Some SOCs (e.g. STM32F0) can map the flash to address 0 and
the flash base address at the same time. Prevent writing to
duplicate flash address which stops the SOC.
Allow Cortex M SOCs to create their own vector table relocation
function.
Provide a relocation function for STM32F0x SOCs.
Fixes#3923
Signed-off-by: Bobby Noelte <b0661n0e17e@gmail.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Added I2C bus (TWI) driver for Atmel SAM MCU family. Only
I2C Master Mode with 7 bit addressing is currently supported.
Tested on Arduino Due board.
Origin: Original
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
Match change we made to how I2C is enabled for other stm32 platforms:
Right now we allow for the I2C subsystem to be built without any drivers
enabled that utilize it. When we added support for the new STM32 I2C
driver we forced the I2C driver to be enabled if the I2C subsystem was
enabled. While this makes a reasonable amount of sense, it breaks
current assumptions for various testcases that we need to cleanup.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Added architecture specific support for memory domain destroy
and remove partition for arm and nxp. An optimized version of
remove partition was also added.
Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
STM32 UART driver was using a mix of LL/HAL APIs. This commit removes
calls to HAL API and replaces them with LL APIs. No functional change
have been seen during non regression testing.
But we could note a direct gain of 1Kb of ROM
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Because the mcux shim drivers will soon depend on a clock control
interface, enable the mcux sim clock control driver by default on all
Kinetis SoCs.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Currently this is defined as a k_thread_stack_t pointer.
However this isn't correct, stacks are defined as arrays. Extern
references to k_thread_stack_t doesn't work properly as the compiler
treats it as a pointer to the stack array and not the array itself.
Declaring as an unsized array of k_thread_stack_t doesn't work
well either. The least amount of confusion is to leave out the
pointer/array status completely, use pointers for function prototypes,
and define K_THREAD_STACK_EXTERN() to properly create an extern
reference.
The definitions for all functions and struct that use
k_thread_stack_t need to be updated, but code that uses them should
be unchanged.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This is a USB controller driver for STM32F4xx devices using
the STM32 Cube HAL_PCD framework. This has been tested with
the cdc_acm driver on a 96b_carbon board (STM32F401RE).
This is a refactoring of:
usb: usb_dc_stm: Add support for STM32Cube HAL_PCD USB driver
Signed-off-by: Christer Weinigel <christer@weinigel.se>
[daniel.thompson@linaro.org: Removed STM32F40(157) defconfig changes
together with STM32F4Discovery pinmux and defconfig changes, updated
clock settings and pad configuration to match latest mainline]
Signed-off-by: Daniel Thompson <daniel.thompson@linaro.org>
[giannis.damigos@gmail.com: Change uint*_t types to u*_t types,
change SYS_LOG_USB_DC_STM_LEVEL to SYS_LOG_USB_DRIVER_LEVEL and
update pinmux to match latest arm branch]
Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
The Silicon Labs EFM32 Wonder Gecko MCU includes:
* Cortex-M4F core at 48MHz
* up to 256KB of flash and 32KB of RAM
* USB with host and OTG support
* multiple low power peripherals
Signed-off-by: Christian Taedcke <hacking@taedcke.com>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Use the define generated by the DTS instead of using the FLASH_ALIGN
alias. The latter is an internal mcuboot name. We shouldn't need it in
Zephyr itself.
Signed-off-by: Marti Bolivar <marti.bolivar@linaro.org>
This workaround fixes the issue that, after pin reset, RESETREAS bits
other than RESETPIN might also be set.
The workaround was added to both nRF52832 and nRF52840 SoCs.
Signed-off-by: Thiago Silveira <thiago@exati.com.br>
802.15.4 is the networking hardware available in KW41Z SoC (and
supported by Zephyr). So, if networking in enabled, automatically
select the corresponding driver. This is similar to how frdm_k64f
automatically selects Ethernet driver, 96b_carbon selects BLE/IPSP
drivers, etc. (But we apply it on SoC level to reuse across the
boards.)
Signed-off-by: Paul Sokolovsky <paul.sokolovsky@linaro.org>
Some our Zephyr tools don't like seeing UTF-8 characters, as reported in
issue #4131) so a quick scan and replace for UTF-8 characters in .rst,
.h, and Kconfig files using "file --mime-encoding" (excluding the /ext
folders) finds these files to tweak.
Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
Add the following application-facing memory domain APIs:
k_mem_domain_init() - to initialize a memory domain
k_mem_domain_destroy() - to destroy a memory domain
k_mem_domain_add_partition() - to add a partition into a domain
k_mem_domain_remove_partition() - to remove a partition from a domain
k_mem_domain_add_thread() - to add a thread into a domain
k_mem_domain_remove_thread() - to remove a thread from a domain
A memory domain would contain some number of memory partitions.
A memory partition is a memory region (might be RAM, peripheral
registers, flash...) with specific attributes (access permission,
e.g. privileged read/write, unprivileged read-only, execute never...).
Memory partitions would be defined by set of MPU regions or MMU tables
underneath.
A thread could only belong to a single memory domain any point in time
but a memory domain could contain multiple threads.
Threads in the same memory domain would have the same access permission
to the memory partitions belong to the memory domain.
The memory domain APIs are used by unprivileged threads to share data
to the threads in the same memory and protect sensitive data from
threads outside their domain. It is not only for improving the security
but also useful for debugging (unexpected access would cause exception).
Jira: ZEP-2281
Signed-off-by: Chunlin Han <chunlin.han@linaro.org>
SoCs outside the Kinetis family can have the TRNG module, so move the
HAS_TRNG config from arch/arm/soc/nxp_kinetis to ext/hal/nxp/mcux
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
SoCs outside the Kinetis family can have the RNGA module, so move the
HAS_RNGA config from arch/arm/soc/nxp_kinetis to ext/hal/nxp/mcux
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
SoCs outside the Kinetis family can have the FTM module, so move the
HAS_FTM config from arch/arm/soc/nxp_kinetis to ext/hal/nxp/mcux
Note that 'select HAS_FTM' was previously missing from Kconfig.soc and
is now fixed.
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
SoCs outside the Kinetis family can have the ADC16 module, so move the
HAS_ADC16 config from arch/arm/soc/nxp_kinetis to ext/hal/nxp/mcux
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
SoCs outside the Kinetis family can have the LPSCI module, so move the
HAS_LPSCI config from arch/arm/soc/nxp_kinetis to ext/hal/nxp/mcux
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
SoCs outside the Kinetis family can have the LPUART module, so move the
HAS_LPUART config from arch/arm/soc/nxp_kinetis to ext/hal/nxp/mcux
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
mcuboot_constraints.h had FLASH information related to the SoC that
should be maintained as part of the SoC and not in the subsystem. Also
fixed Makefiles to check for IMG_UTIL Kconfig and not MCUBOOT.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
stm32f417xe and stm32f417xg have been introduced with 2
different defconfig files. Since same code is declared
in both files, mutualize declarations in a single file.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
The enumerations stm32{f3,f4}x_pin_config_mode aren't used any
more. This patch removes them.
Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
In various places, a private _thread_entry_t, or the full prototype
were being used. Be consistent and use the same typedef everywhere.
Signen-off-by: Andrew Boie <andrew.p.boie@intel.com>
Indenting preprocessor directives reduces the code readability, because
it make preprocessor directives harder to spot.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Add flash page layout support for STM32F4 SoCs.
This almost eliminates the need for flash_map.h, except for
STM32F4X_SECTOR_MASK, so delete the file and move the define into the
F4 implementation, to keep things simple.
Signed-off-by: Marti Bolivar <marti.bolivar@linaro.org>
Previously, this was only done if an essential thread self-exited,
and was a runtime check that generated a kernel panic.
Now if any thread has k_thread_abort() called on it, and that thread
is essential to the system operation, this check is made. It is now
an assertion.
_NANO_ERR_INVALID_TASK_EXIT checks and printouts removed since this
is now an assertion.
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
In benchmark test (test_info) while making function call regs
r0 - r4 are modified into called function. Due to this value
inside r3 is getting lost.
This patch saves and restore the value in r0-r4 regs while making
function calls from assembly language.
Jira: ZEP-2314
Signed-off-by: Youvedeep Singh <youvedeep.singh@intel.com>
The API/Variable names in timing_info looks very speicific to
platform (like systick etc), whereas these variabled are used
across platforms (nrf/arm/quark).
So this patch :-
1. changing API/Variable names to generic one.
2. Creating some of Macros whose implimentation is platform
depenent.
Jira: ZEP-2314
Signed-off-by: Youvedeep Singh <youvedeep.singh@intel.com>
This patch fixes a couple of issues with the stack guard size and
properly constructs the STACK_ALIGN and STACK_ALIGN_SIZE definitions.
The ARM AAPCS requires that the stack pointers be 8 byte aligned. The
STACK_ALIGN_SIZE definition is meant to contain the stack pointer
alignment requirements. This is the required alignment at public API
boundaries (ie stack frames).
The STACK_ALIGN definition is the required alignment for the start
address for stack buffer storage. STACK_ALIGN is used to validate
the allocation sizes for stack buffers.
The MPU_GUARD_ALIGN_AND_SIZE definition is the minimum alignment and
size for the MPU. The minimum size and alignment just so happen to be
32 bytes for vanilla ARM MPU implementations.
When defining stack buffers, the stack guard alignment requirements
must be taken into consideration when allocating the stack memory.
The __align() must be filled in with either STACK_ALIGN_SIZE or the
align/size of the MPU stack guard. The align/size for the guard region
will be 0 when CONFIG_MPU_STACK_GUARD is not set, and 32 bytes when it
is.
The _ARCH_THREAD_STACK_XXXXXX APIs need to know the minimum alignment
requirements for the stack buffer memory and the stack guard size to
correctly allocate and reference the stack memory. This is reflected
in the macros with the use of the STACK_ALIGN definition and the
MPU_GUARD_ALIGN_AND_SIZE definition.
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This patch removes the redundant stack alignment check being done. The
stack definition macros enforce the alignment requirements via the
__align() directives.
In addition, fix the rounding down of the psp to be correct. The
actual initial stack pointer is the end of the stack minus the size of
the __esf structure. Rounding down after the subtraction will get us
to the correct offset.
Signed-off-by: Andy Gross <andy.gross@linaro.org>
When we mask out the GPIO High impedance/Pull-up/Pull-down field we
should be shifting the mask file, not shifting the field. This is
because all the other defines already assume the shift.
Coverity-CID: 173640
Jira: ZEP-2538
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Per ZEP-1958, Phase 2 of adding CC3220sf LaunchXL support,
was to "deprecate the CC3200 launchxl support in Zephyr
(redundant to the CC3220)."
Effectively, the CC3220 SOC replaces the CC3200.
This patch removes the following:
* the imported CC3200 SDK
* CC3200 SOC, board, DTS files.
* adjusts other files where cc3200 was mentioned.
Also, it fixes explicit references to CC3200 in generic
CC32xx driver files.
Jira: ZEP-1958
Signed-off-by: Gil Pitney <gil.pitney@linaro.org>
Previously, calling NVIC_SetPriority(IRQn_Type irqn, ....) with
the NWP interrupt number of 171 caused a hard fault during a
subsequent svc #0 instruction during _Swap().
GNU compiler is generating a bit extension instruction (sxtb) which
converts a positive IRQ value argument to a negative value when
casting to the CMSIS IRQn_Type enum parameter type.
This generates a negative index, which then writes to an SCB
control register instead of NVIC register, causing a hard
fault later on.
This issue only occurs when passing interrupt numbers > 0x80
(eg: 171 (0xab) for the NWP) to the CMSIS NVIC apis.
The solution here is simply to redefine IRQn_Type to be an
unsigned 32 bit integer, while redefining the CMSIS IRQn_Type
enum definitions for interrupts less than zero.
Jira: ZEP-1958
Signed-off-by: Gil Pitney <gil.pitney@linaro.org>
An abnormal crash was encountered in ARMv6-M SoCs that don't have flash
starting at 0. With Zephyr OS the reason for this crash is that, on
ARMv6-M the system requires an exception vector table at the 0 address.
We implement the relocate_vector_table function to move the vector table
code to address 0 on systems which don't have the start of code already
at 0.
[kumar.gala: reworderd commit message, tweaked how we check if we need
to copy vector table]
Signed-off-by: Xiaorui Hu <xiaorui.hu@linaro.org>
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
Now that we have an mcux shim driver, remove the old k64-specific
driver. Also remove include/drivers/k20_sim.h, since the old
k64-specific driver was the only thing left using it.
Jira: ZEP-2025
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Switches the default pwm driver from the k64-specific driver to the
mcux shim, which can be used on other SoCs with the ftm peripheral.
Jira: ZEP-2025
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Adds a shim layer around the mcux ftm driver to adapt it to the Zephyr
pwm interface.
Jira: ZEP-2025
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
This patch adjusts the ARM MPU implementation to be compliant to the
recent changes that introduced the opaque kernel data types.
Signed-off-by: Andy Gross <andy.gross@linaro.org>
The mimimum mpu size is 32 bytes, but requires mpu base address to be
aligned on 32 bytes to work. Define architecture thread macro when
MPU_STACK_GUARD config to allocate stack with 32 more bytes.
Signed-off-by: Michel Jaouen <michel.jaouen@st.com>
In the stm32_gpio_flags_to_conf function the configuration
values of the GPIO pin are shifted two times. One in the
stm32-pinctrlf1 header and one in the function. This patch
removes one of those shifts.
Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
This patch adds the allow flash write CONFIG option to the ARM MPU
configuration in privileged mode.
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@linaro.org>
Signed-off-by: Michael Scott <michael.scott@linaro.org>
Signed-off-by: David Brown <david.brown@linaro.org>
This patch adds the allow flash write CONFIG option to the NXP MPU
configuration in privileged mode.
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@linaro.org>
Signed-off-by: David Brown <david.brown@linaro.org>
Currently Thread time slice is getting reset at end of timer
interrupt. Due to which equal priority threads behind current thread
in ready_q are not getting chance to run and leading to starvation.
This patch handles time slice in _ExcExit section context switch is
required.
Jira: ZEP-2444
Signed-off-by: Youvedeep Singh <youvedeep.singh@intel.com>
Signed-off-by: Ramesh Thomas <ramesh.thomas@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The ouput speed of the gpio pins passed via the 'conf' argument was
ignored, causing the speed to always be in its reset state (lowest
possible speed for most pins). This was causing problems for pins that
actually need a speed faster than the default, like the ethernet
controller pins.
Combined with the correct pinmux configuration this fixes problems
of the olimex_stm32_e407 board not being able to send ethernet data.
Signed-off-by: Erwin Rol <erwin@erwinrol.com>
Historically, stacks were just character buffers and could be treated
as such if the user wanted to look inside the stack data, and also
declared as an array of the desired stack size.
This is no longer the case. Certain architectures will create a memory
region much larger to account for MPU/MMU guard pages. Unfortunately,
the kernel interfaces treat both the declared stack, and the valid
stack buffer within it as the same char * data type, even though these
absolutely cannot be used interchangeably.
We introduce an opaque k_thread_stack_t which gets instantiated by
K_THREAD_STACK_DECLARE(), this is no longer treated by the compiler
as a character pointer, even though it really is.
To access the real stack buffer within, the result of
K_THREAD_STACK_BUFFER() can be used, which will return a char * type.
This should catch a bunch of programming mistakes at build time:
- Declaring a character array outside of K_THREAD_STACK_DECLARE() and
passing it to K_THREAD_CREATE
- Directly examining the stack created by K_THREAD_STACK_DECLARE()
which is not actually the memory desired and may trigger a CPU
exception
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Move to using the generated IRQ defines from the DTS instead of soc.h.
This change also fixes a minor bug in that the error irq priority wasn't
getting correctly picked up from device tree.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
STM32F3 pinmux handler is reworked to support future pinmux dts
generation.
Preliminary change is done to move pin configuration
informations in a {pin, conf} structure closer to dts fields
"pins" array is removed as information is transfered to
"pinconf" array
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
STM32F4 pinmux handler is reworked to support future pinmux dts
generation.
Preliminary change is done to move pin configuration
informations in a {pin, conf} structure closer to dts fields
"pins" array is removed as information is transfered to
"pinconf" array
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Rework stm32f1 pinmux code for future dts based pinmux code
generation.
Pin configuration is now done directly thanks to gpio port
configuration. Reference to pseudo alternate functions are
now removed same as the use of pins[] array.
Pins function (uart tx for instance) is set implicitly by
defining gpio mode and configuration.
This behavior is specific to stm32f10x series.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
STM32L4 pinmux handler is reworked to support future pinmux dts
generation.
Preliminary change is done to move pin configuration
informations in a {pin, conf} structure closer to dts fields
"pins" array is removed and information is transferred to
"pinconf" array
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
In L4 series, select HAS_STM32CUBE is done per soc.
This could be factorized in Kconfig.series.
Aim is to lower the steps to add a new SoC.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Now that we generate BLUETOOTH_UART_ON_DEV_NAME, UART_PIPE_ON_DEV_NAME,
and BLUETOOTH_MONITOR_ON_DEV_NAME Kconfig defines for dts enabled
platforms add those into the appropriate dts files and remove from the
various board/Kconfig.defconfig files.
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
With introduction of commit "pinmux: stm32: directly return error if
stm32_get_pin_config fails", pin configuration fails when
pins are not configured in pins[] array.
This was the case for configuration UART1 assigned on PB6/PB7.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
If the adc driver configuration is enabled (CONFIG_ADC=y), then enable
the mcux shim driver by default for all Kinetis SoCs.
Jira: ZEP-1396
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
Adds a shim layer around the mcux adc16 driver to adapt it to the Zephyr
adc interface.
Jira: ZEP-1396
Signed-off-by: Maureen Helm <maureen.helm@nxp.com>