arch: arm: Fix Cortex-R power management interrupt handling
The system power management handling code in the '_isr_wrapper' enables interrupts by executing the 'cpsie i' instruction, which causes a system crash on the Cortex-R devices because the Cortex-R arch port does not support nested interrupts at this time. This commit restricts the interrupt state manipulations in the system power management code to the Cortex-M arch, in order to prevent interrupt nesting on other AArch32 family archs (only Cortex-R for now). Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
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1 changed files with 11 additions and 0 deletions
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@ -77,7 +77,15 @@ SECTION_FUNC(TEXT, _isr_wrapper)
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* state is not interrupted. In each case, z_sys_power_save_idle_exit
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* is called with interrupts disabled.
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*/
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/*
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* FIXME: Remove the Cortex-M conditional compilation checks for `cpsid i`
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* and `cpsie i` after the Cortex-R port is updated to support
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* interrupt nesting. For more details, refer to the issue #21758.
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*/
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#if defined(CONFIG_CPU_CORTEX_M)
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cpsid i /* PRIMASK = 1 */
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#endif
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/* is this a wakeup from idle ? */
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ldr r2, =_kernel
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@ -110,9 +118,12 @@ _idle_state_cleared:
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#error Unknown ARM architecture
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#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
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#if defined(CONFIG_CPU_CORTEX_M)
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cpsie i /* re-enable interrupts (PRIMASK = 0) */
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#endif
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#endif /* CONFIG_SYS_POWER_MANAGEMENT */
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#if defined(CONFIG_CPU_CORTEX_M)
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mrs r0, IPSR /* get exception number */
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#endif
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