Configure the LPSPI PCSx pins as GPIO if not dedicated to SPI CS. This
allows using them for SPI GPIO CS.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
This commit changes zassert_mem_equal as a macro instead
of a function implementation.
In the previous implementation when an assertion fails
the location inside ztest_assert.h file was displayed.
This modification displays the location where zassert_mem_equal
was used.
Signed-off-by: Radoslaw Koppel <radoslaw.koppel@nordicsemi.no>
stm32wb55rg is a dual core SoC (M4/M0) with a radio/protocol stack
running on M0 core. M0 FW starts at flash address 0x80CB000.
So flash size available to zephyr is 812K instead of 1M.
Configure package size to reflect this (flash size is now 812K)
and update MPU setting to exclude M0 FW. From MPU point of view,
we set flash size to 512K since we should chose a size being a power
of 2.
If we consider there will be 2 images partitions in a FOTA scheme,
512 K is beyond image-0 and hence is sufficient to cover application
image.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
sram2a and sram2b where defined in the prospect of defining
HCI shared memory sections from device tree.
Remove them, since this is not the case anymore.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
STM32WB HCI driver requires definition of 2 RAM regions to support
use of 3 shared memory sections: MAPPING_TABLE, MB_MEM1 and MB_MEM2.
In linker.ld, under conditions of HCI driver to be enabled,
define SRAM1 and SRAM2 based on input defined in stm32wb linker.
Then define the 3 sections MAPPING_TABLE, MB_MEM1 and MB_MEM
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Implement HCI driver for STM32WB. It allows host to controller.
It is based on ST library allowing communication over RAM shared
bewteen chip's C-M4 and C-M0 cores.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This commit removes redundant checks if the module
was already initialized.
The variable to mark the fact of initialization is
moved as a global module variable.
This allows creating more sophisticated unit tests
of the settings subsystem by giving a possibility to modify
the internal mark of the fact the system was initialized.
Signed-off-by: Radoslaw Koppel <radoslaw.koppel@nordicsemi.no>
Casting the tid variable from a void* into an u32_t just to cast it
back to a pointer is pointless. Let's make it a osThreadId variable
upfront and get rid of those casts around it. This also makes it
64-bit compatible.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
The Apollo Lake SoC no longer uses the legacy PCI driver, so remove
references and supporting code.
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
While enabling specific I2C ports does indeed belong at the board
level Kconfig, the selection of driver (I2C_DW) is an SoC-level
choice, so it is moved accordingly.
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
Which UARTs are broken out from the SoC on a particular board is
board-specific; don't enable UARTs blindly in the SoC Kconfig.
Also, the default UART options are specified in the driver Kconfig, so
the same defaults specified in the SoC Kconfig are redundant. Removed.
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
Since Kconfig is responsible for enabling/disabling devices at build,
the devices in dt are defaulted to status="ok" to keep the output in
generated_dts_board.conf the same across configurations and simplify
the board-level dts files.
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
The UART references in dts_fixup.h are actually SoC-specific, not
board-specific, so they are moved. Since this leaves the board fixups
empty, the file is removed.
The SoC fixups are expanded to include the additional two ports that
are present on some revisions of the Apollo Lake.
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
Some firmwares (looking at you, slimbootloader) don't set the registers
in PCI configuration space to indicate the IRQ routing, so we remove
the check that verifies that the user and firmware agree on IRQ number.
Also eliminate the return value of pcie_irq_enable() since no one uses
it and we can't return a meaningful value any longer.
Signed-off-by: Charles Youse <charles.youse@intel.com>
Use a system clock tick of 0.1 sec when running on the NXP TWR-KE18F
development board.
Fixes#16234.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Add SPI support to the NXP TWR-KE18F development board. There are no
onboard SPI devices, but both SPI busses are available on the primary
Tower System elevator connector.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Offloaded `fcntl` implementation should be available for all offloaded
implementations, not specific for TI. `socket_offload.c` is already
conditionally compiled based on `CONFIG_NET_SOCKETS_OFFLOAD` option, so
there should not be conflicts for non-offloaded interfaces.
Signed-off-by: Robert Lubos <robert.lubos@nordicsemi.no>