cypress: move HAL to external repo
This HAL is now in its own repository on https://github.com/zephyrproject-rtos/hal_cypress Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This commit is contained in:
Anas Nashif
parent
7ae4180265
commit
0b2bb32cb4
257 changed files with 3 additions and 199383 deletions
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@ -1,6 +1,5 @@
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add_subdirectory(atmel)
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add_subdirectory(cmsis)
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add_subdirectory(cypress)
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add_subdirectory_if_kconfig(libmetal)
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add_subdirectory(nordic)
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add_subdirectory(nxp)
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@ -16,8 +16,6 @@ source "ext/hal/altera/Kconfig"
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source "ext/hal/cmsis/Kconfig"
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source "ext/hal/cypress/Kconfig"
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source "ext/hal/libmetal/Kconfig"
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source "ext/hal/microchip/Kconfig"
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@ -1,10 +0,0 @@
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#
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# Copyright (c) 2018, Cypress
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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add_subdirectory_ifdef(
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CONFIG_HAS_CYPRESS_DRIVERS
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PDL
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)
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@ -1,9 +0,0 @@
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#
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# Copyright (c) 2018 Cypress Semiconductor
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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config HAS_CYPRESS_DRIVERS
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bool
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select HAS_CMSIS
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@ -1,45 +0,0 @@
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#
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# Copyright (c) 2018, Cypress
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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zephyr_compile_definitions(${CONFIG_SOC_PART_NUMBER})
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# Workaround to fix absence of four defines in PDL
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# The values don't matter
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zephyr_compile_definitions(
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__copy_table_start__=0
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)
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zephyr_compile_definitions(
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__copy_table_end__=0
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)
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zephyr_compile_definitions(
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__bss_start__=0
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)
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zephyr_compile_definitions(
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__bss_end__=0
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)
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zephyr_include_directories(drivers/include)
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zephyr_sources(drivers/source/cy_sysclk.c)
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zephyr_include_directories(devices/psoc6/include)
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zephyr_include_directories(devices/psoc6/include/ip)
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zephyr_sources(devices/psoc6/startup/system_psoc6_cm0plus.c)
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zephyr_sources(devices/psoc6/startup/gcc/startup_psoc62_cm0plus.S)
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zephyr_sources(drivers/source/cy_device.c)
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zephyr_sources(drivers/source/cy_syslib.c)
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zephyr_sources(drivers/source/cy_sysint.c)
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zephyr_sources(drivers/source/gcc/cy_syslib_gcc.S)
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zephyr_sources(drivers/source/cy_gpio.c)
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zephyr_sources(drivers/source/cy_prot.c)
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zephyr_sources(drivers/source/cy_syspm.c)
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zephyr_sources(drivers/source/cy_sysclk.c)
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zephyr_sources(drivers/source/cy_flash.c)
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zephyr_sources(drivers/source/cy_ipc_drv.c)
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zephyr_sources(drivers/source/cy_ipc_config.c)
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zephyr_sources(drivers/source/cy_ipc_sema.c)
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zephyr_sources(drivers/source/cy_ipc_pipe.c)
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zephyr_sources(drivers/source/cy_scb_uart.c)
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zephyr_sources(drivers/source/cy_scb_common.c)
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@ -1,933 +0,0 @@
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/***************************************************************************//**
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* \file cy8c6016bzi_f04.h
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*
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* \brief
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* CY8C6016BZI-F04 device header
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*
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* \note
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* Generator version: 1.3.0.1146
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* Database revision: rev#1050929
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*
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********************************************************************************
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* \copyright
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* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
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* SPDX-License-Identifier: Apache-2.0
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*******************************************************************************/
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#ifndef _CY8C6016BZI_F04_H_
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#define _CY8C6016BZI_F04_H_
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/**
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* \addtogroup group_device CY8C6016BZI-F04
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* \{
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*/
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/**
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* \addtogroup Configuration_of_CMSIS
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* \{
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*/
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/*******************************************************************************
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* Interrupt Number Definition
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*******************************************************************************/
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typedef enum {
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/* ARM Cortex-M4 Core Interrupt Numbers */
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Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */
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NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */
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HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */
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MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */
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BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */
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UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
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SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */
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DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */
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PendSV_IRQn = -2, /*!< -2 Pendable request for system service */
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SysTick_IRQn = -1, /*!< -1 System Tick Timer */
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/* CY8C6016BZI-F04 Peripheral Interrupt Numbers */
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ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */
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ioss_interrupts_gpio_1_IRQn = 1, /*!< 1 [DeepSleep] GPIO Port Interrupt #1 */
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ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */
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ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */
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ioss_interrupts_gpio_4_IRQn = 4, /*!< 4 [DeepSleep] GPIO Port Interrupt #4 */
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ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */
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ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */
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ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */
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ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */
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ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */
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ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */
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ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */
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ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */
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ioss_interrupts_gpio_13_IRQn = 13, /*!< 13 [DeepSleep] GPIO Port Interrupt #13 */
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ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */
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ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */
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ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */
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lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */
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scb_8_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #8 (DeepSleep capable) */
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srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */
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srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */
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srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */
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srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */
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pass_interrupt_ctbs_IRQn = 23, /*!< 23 [DeepSleep] CTBm Interrupt (all CTBms) */
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bless_interrupt_IRQn = 24, /*!< 24 [DeepSleep] Bluetooth Radio interrupt */
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cpuss_interrupts_ipc_0_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */
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cpuss_interrupts_ipc_1_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */
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cpuss_interrupts_ipc_2_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */
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cpuss_interrupts_ipc_3_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */
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cpuss_interrupts_ipc_4_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */
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cpuss_interrupts_ipc_5_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */
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cpuss_interrupts_ipc_6_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */
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cpuss_interrupts_ipc_7_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */
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cpuss_interrupts_ipc_8_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */
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cpuss_interrupts_ipc_9_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */
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cpuss_interrupts_ipc_10_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */
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cpuss_interrupts_ipc_11_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */
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cpuss_interrupts_ipc_12_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */
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cpuss_interrupts_ipc_13_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */
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cpuss_interrupts_ipc_14_IRQn = 39, /*!< 39 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */
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cpuss_interrupts_ipc_15_IRQn = 40, /*!< 40 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */
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scb_0_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #0 */
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scb_1_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #1 */
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scb_2_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #2 */
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scb_3_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #3 */
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scb_4_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #4 */
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scb_5_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #5 */
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scb_6_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #6 */
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scb_7_interrupt_IRQn = 48, /*!< 48 [Active] Serial Communication Block #7 */
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csd_interrupt_IRQn = 49, /*!< 49 [Active] CSD (Capsense) interrupt */
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cpuss_interrupts_dw0_0_IRQn = 50, /*!< 50 [Active] CPUSS DataWire #0, Channel #0 */
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cpuss_interrupts_dw0_1_IRQn = 51, /*!< 51 [Active] CPUSS DataWire #0, Channel #1 */
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cpuss_interrupts_dw0_2_IRQn = 52, /*!< 52 [Active] CPUSS DataWire #0, Channel #2 */
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cpuss_interrupts_dw0_3_IRQn = 53, /*!< 53 [Active] CPUSS DataWire #0, Channel #3 */
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cpuss_interrupts_dw0_4_IRQn = 54, /*!< 54 [Active] CPUSS DataWire #0, Channel #4 */
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cpuss_interrupts_dw0_5_IRQn = 55, /*!< 55 [Active] CPUSS DataWire #0, Channel #5 */
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cpuss_interrupts_dw0_6_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #6 */
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cpuss_interrupts_dw0_7_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #7 */
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cpuss_interrupts_dw0_8_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #8 */
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cpuss_interrupts_dw0_9_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #9 */
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cpuss_interrupts_dw0_10_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #10 */
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cpuss_interrupts_dw0_11_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #11 */
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cpuss_interrupts_dw0_12_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #12 */
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cpuss_interrupts_dw0_13_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #13 */
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cpuss_interrupts_dw0_14_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #14 */
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cpuss_interrupts_dw0_15_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #15 */
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cpuss_interrupts_dw1_0_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #1, Channel #0 */
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cpuss_interrupts_dw1_1_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #1, Channel #1 */
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cpuss_interrupts_dw1_2_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #1, Channel #2 */
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cpuss_interrupts_dw1_3_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #1, Channel #3 */
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cpuss_interrupts_dw1_4_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #1, Channel #4 */
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cpuss_interrupts_dw1_5_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #1, Channel #5 */
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cpuss_interrupts_dw1_6_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #1, Channel #6 */
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cpuss_interrupts_dw1_7_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #1, Channel #7 */
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cpuss_interrupts_dw1_8_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #1, Channel #8 */
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cpuss_interrupts_dw1_9_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #1, Channel #9 */
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cpuss_interrupts_dw1_10_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #1, Channel #10 */
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cpuss_interrupts_dw1_11_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #1, Channel #11 */
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cpuss_interrupts_dw1_12_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #1, Channel #12 */
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cpuss_interrupts_dw1_13_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #1, Channel #13 */
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cpuss_interrupts_dw1_14_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #1, Channel #14 */
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cpuss_interrupts_dw1_15_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #1, Channel #15 */
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cpuss_interrupts_fault_0_IRQn = 82, /*!< 82 [Active] CPUSS Fault Structure Interrupt #0 */
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cpuss_interrupts_fault_1_IRQn = 83, /*!< 83 [Active] CPUSS Fault Structure Interrupt #1 */
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cpuss_interrupt_crypto_IRQn = 84, /*!< 84 [Active] CRYPTO Accelerator Interrupt */
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cpuss_interrupt_fm_IRQn = 85, /*!< 85 [Active] FLASH Macro Interrupt */
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cpuss_interrupts_cm0_cti_0_IRQn = 86, /*!< 86 [Active] CM0+ CTI #0 */
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cpuss_interrupts_cm0_cti_1_IRQn = 87, /*!< 87 [Active] CM0+ CTI #1 */
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cpuss_interrupts_cm4_cti_0_IRQn = 88, /*!< 88 [Active] CM4 CTI #0 */
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cpuss_interrupts_cm4_cti_1_IRQn = 89, /*!< 89 [Active] CM4 CTI #1 */
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tcpwm_0_interrupts_0_IRQn = 90, /*!< 90 [Active] TCPWM #0, Counter #0 */
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tcpwm_0_interrupts_1_IRQn = 91, /*!< 91 [Active] TCPWM #0, Counter #1 */
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tcpwm_0_interrupts_2_IRQn = 92, /*!< 92 [Active] TCPWM #0, Counter #2 */
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tcpwm_0_interrupts_3_IRQn = 93, /*!< 93 [Active] TCPWM #0, Counter #3 */
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tcpwm_0_interrupts_4_IRQn = 94, /*!< 94 [Active] TCPWM #0, Counter #4 */
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tcpwm_0_interrupts_5_IRQn = 95, /*!< 95 [Active] TCPWM #0, Counter #5 */
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tcpwm_0_interrupts_6_IRQn = 96, /*!< 96 [Active] TCPWM #0, Counter #6 */
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tcpwm_0_interrupts_7_IRQn = 97, /*!< 97 [Active] TCPWM #0, Counter #7 */
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tcpwm_1_interrupts_0_IRQn = 98, /*!< 98 [Active] TCPWM #1, Counter #0 */
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tcpwm_1_interrupts_1_IRQn = 99, /*!< 99 [Active] TCPWM #1, Counter #1 */
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tcpwm_1_interrupts_2_IRQn = 100, /*!< 100 [Active] TCPWM #1, Counter #2 */
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tcpwm_1_interrupts_3_IRQn = 101, /*!< 101 [Active] TCPWM #1, Counter #3 */
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tcpwm_1_interrupts_4_IRQn = 102, /*!< 102 [Active] TCPWM #1, Counter #4 */
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tcpwm_1_interrupts_5_IRQn = 103, /*!< 103 [Active] TCPWM #1, Counter #5 */
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tcpwm_1_interrupts_6_IRQn = 104, /*!< 104 [Active] TCPWM #1, Counter #6 */
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tcpwm_1_interrupts_7_IRQn = 105, /*!< 105 [Active] TCPWM #1, Counter #7 */
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tcpwm_1_interrupts_8_IRQn = 106, /*!< 106 [Active] TCPWM #1, Counter #8 */
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tcpwm_1_interrupts_9_IRQn = 107, /*!< 107 [Active] TCPWM #1, Counter #9 */
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tcpwm_1_interrupts_10_IRQn = 108, /*!< 108 [Active] TCPWM #1, Counter #10 */
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tcpwm_1_interrupts_11_IRQn = 109, /*!< 109 [Active] TCPWM #1, Counter #11 */
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tcpwm_1_interrupts_12_IRQn = 110, /*!< 110 [Active] TCPWM #1, Counter #12 */
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tcpwm_1_interrupts_13_IRQn = 111, /*!< 111 [Active] TCPWM #1, Counter #13 */
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tcpwm_1_interrupts_14_IRQn = 112, /*!< 112 [Active] TCPWM #1, Counter #14 */
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tcpwm_1_interrupts_15_IRQn = 113, /*!< 113 [Active] TCPWM #1, Counter #15 */
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tcpwm_1_interrupts_16_IRQn = 114, /*!< 114 [Active] TCPWM #1, Counter #16 */
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tcpwm_1_interrupts_17_IRQn = 115, /*!< 115 [Active] TCPWM #1, Counter #17 */
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tcpwm_1_interrupts_18_IRQn = 116, /*!< 116 [Active] TCPWM #1, Counter #18 */
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tcpwm_1_interrupts_19_IRQn = 117, /*!< 117 [Active] TCPWM #1, Counter #19 */
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tcpwm_1_interrupts_20_IRQn = 118, /*!< 118 [Active] TCPWM #1, Counter #20 */
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tcpwm_1_interrupts_21_IRQn = 119, /*!< 119 [Active] TCPWM #1, Counter #21 */
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tcpwm_1_interrupts_22_IRQn = 120, /*!< 120 [Active] TCPWM #1, Counter #22 */
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tcpwm_1_interrupts_23_IRQn = 121, /*!< 121 [Active] TCPWM #1, Counter #23 */
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udb_interrupts_0_IRQn = 122, /*!< 122 [Active] UDB Interrupt #0 */
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udb_interrupts_1_IRQn = 123, /*!< 123 [Active] UDB Interrupt #1 */
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udb_interrupts_2_IRQn = 124, /*!< 124 [Active] UDB Interrupt #2 */
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udb_interrupts_3_IRQn = 125, /*!< 125 [Active] UDB Interrupt #3 */
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udb_interrupts_4_IRQn = 126, /*!< 126 [Active] UDB Interrupt #4 */
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udb_interrupts_5_IRQn = 127, /*!< 127 [Active] UDB Interrupt #5 */
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udb_interrupts_6_IRQn = 128, /*!< 128 [Active] UDB Interrupt #6 */
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udb_interrupts_7_IRQn = 129, /*!< 129 [Active] UDB Interrupt #7 */
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udb_interrupts_8_IRQn = 130, /*!< 130 [Active] UDB Interrupt #8 */
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udb_interrupts_9_IRQn = 131, /*!< 131 [Active] UDB Interrupt #9 */
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udb_interrupts_10_IRQn = 132, /*!< 132 [Active] UDB Interrupt #10 */
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udb_interrupts_11_IRQn = 133, /*!< 133 [Active] UDB Interrupt #11 */
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udb_interrupts_12_IRQn = 134, /*!< 134 [Active] UDB Interrupt #12 */
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udb_interrupts_13_IRQn = 135, /*!< 135 [Active] UDB Interrupt #13 */
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udb_interrupts_14_IRQn = 136, /*!< 136 [Active] UDB Interrupt #14 */
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udb_interrupts_15_IRQn = 137, /*!< 137 [Active] UDB Interrupt #15 */
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pass_interrupt_sar_IRQn = 138, /*!< 138 [Active] SAR ADC interrupt */
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audioss_interrupt_i2s_IRQn = 139, /*!< 139 [Active] I2S Audio interrupt */
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audioss_interrupt_pdm_IRQn = 140, /*!< 140 [Active] PDM/PCM Audio interrupt */
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profile_interrupt_IRQn = 141, /*!< 141 [Active] Energy Profiler interrupt */
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smif_interrupt_IRQn = 142, /*!< 142 [Active] Serial Memory Interface interrupt */
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usb_interrupt_hi_IRQn = 143, /*!< 143 [Active] USB Interrupt */
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usb_interrupt_med_IRQn = 144, /*!< 144 [Active] USB Interrupt */
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usb_interrupt_lo_IRQn = 145, /*!< 145 [Active] USB Interrupt */
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pass_interrupt_dacs_IRQn = 146, /*!< 146 [Active] Consolidated interrrupt for all DACs */
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unconnected_IRQn = 240 /*!< 240 Unconnected */
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} IRQn_Type;
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/*******************************************************************************
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* Processor and Core Peripheral Section
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*******************************************************************************/
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/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */
|
||||
#define __CM4_REV 0x0001U /*!< CM4 Core Revision */
|
||||
#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
|
||||
#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */
|
||||
#define __MPU_PRESENT 1 /*!< MPU present or not */
|
||||
#define __FPU_PRESENT 1 /*!< FPU present or not */
|
||||
#define __CM0P_PRESENT 0 /*!< CM0P present or not */
|
||||
|
||||
/** \} Configuration_of_CMSIS */
|
||||
|
||||
/* Memory Blocks */
|
||||
#define CY_ROM_BASE 0x00000000UL
|
||||
#define CY_ROM_SIZE 0x00020000UL
|
||||
#define CY_SRAM0_BASE 0x08000000UL
|
||||
#define CY_SRAM0_SIZE 0x00020000UL
|
||||
#define CY_FLASH_BASE 0x10000000UL
|
||||
#define CY_FLASH_SIZE 0x00080000UL
|
||||
#define CY_EM_EEPROM_BASE 0x14000000UL
|
||||
#define CY_EM_EEPROM_SIZE 0x00008000UL
|
||||
#define CY_XIP_BASE 0x18000000UL
|
||||
#define CY_XIP_SIZE 0x08000000UL
|
||||
#define CY_SFLASH_BASE 0x16000000UL
|
||||
#define CY_SFLASH_SIZE 0x00008000UL
|
||||
#define CY_EFUSE_BASE 0x402C0800UL
|
||||
#define CY_EFUSE_SIZE 0x00000200UL
|
||||
|
||||
#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */
|
||||
#include "system_psoc6.h" /*!< PSoC 6 System */
|
||||
|
||||
/* IP List */
|
||||
#define CY_IP_MXTCPWM 1u
|
||||
#define CY_IP_MXTCPWM_INSTANCES 2u
|
||||
#define CY_IP_MXTCPWM_VERSION 1u
|
||||
#define CY_IP_MXCSDV2 1u
|
||||
#define CY_IP_MXCSDV2_INSTANCES 1u
|
||||
#define CY_IP_MXCSDV2_VERSION 1u
|
||||
#define CY_IP_MXLCD 1u
|
||||
#define CY_IP_MXLCD_INSTANCES 1u
|
||||
#define CY_IP_MXLCD_VERSION 1u
|
||||
#define CY_IP_MXS40SRSS 1u
|
||||
#define CY_IP_MXS40SRSS_INSTANCES 1u
|
||||
#define CY_IP_MXS40SRSS_VERSION 1u
|
||||
#define CY_IP_MXS40SRSS_RTC 1u
|
||||
#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u
|
||||
#define CY_IP_MXS40SRSS_RTC_VERSION 1u
|
||||
#define CY_IP_MXS40SRSS_MCWDT 1u
|
||||
#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u
|
||||
#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u
|
||||
#define CY_IP_MXSCB 1u
|
||||
#define CY_IP_MXSCB_INSTANCES 9u
|
||||
#define CY_IP_MXSCB_VERSION 1u
|
||||
#define CY_IP_MXPERI 1u
|
||||
#define CY_IP_MXPERI_INSTANCES 1u
|
||||
#define CY_IP_MXPERI_VERSION 1u
|
||||
#define CY_IP_MXPERI_TR 1u
|
||||
#define CY_IP_MXPERI_TR_INSTANCES 1u
|
||||
#define CY_IP_MXPERI_TR_VERSION 1u
|
||||
#define CY_IP_M4CPUSS 1u
|
||||
#define CY_IP_M4CPUSS_INSTANCES 1u
|
||||
#define CY_IP_M4CPUSS_VERSION 1u
|
||||
#define CY_IP_M4CPUSS_DMA 1u
|
||||
#define CY_IP_M4CPUSS_DMA_INSTANCES 2u
|
||||
#define CY_IP_M4CPUSS_DMA_VERSION 1u
|
||||
#define CY_IP_MXAUDIOSS 1u
|
||||
#define CY_IP_MXAUDIOSS_INSTANCES 1u
|
||||
#define CY_IP_MXAUDIOSS_VERSION 1u
|
||||
#define CY_IP_MXLPCOMP 1u
|
||||
#define CY_IP_MXLPCOMP_INSTANCES 1u
|
||||
#define CY_IP_MXLPCOMP_VERSION 1u
|
||||
#define CY_IP_MXS40PASS 1u
|
||||
#define CY_IP_MXS40PASS_INSTANCES 1u
|
||||
#define CY_IP_MXS40PASS_VERSION 1u
|
||||
#define CY_IP_MXS40PASS_SAR 1u
|
||||
#define CY_IP_MXS40PASS_SAR_INSTANCES 16u
|
||||
#define CY_IP_MXS40PASS_SAR_VERSION 1u
|
||||
#define CY_IP_MXS40PASS_CTDAC 1u
|
||||
#define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u
|
||||
#define CY_IP_MXS40PASS_CTDAC_VERSION 1u
|
||||
#define CY_IP_MXSMIF 1u
|
||||
#define CY_IP_MXSMIF_INSTANCES 1u
|
||||
#define CY_IP_MXSMIF_VERSION 1u
|
||||
#define CY_IP_MXUSBFS 1u
|
||||
#define CY_IP_MXUSBFS_INSTANCES 1u
|
||||
#define CY_IP_MXUSBFS_VERSION 1u
|
||||
#define CY_IP_MXS40IOSS 1u
|
||||
#define CY_IP_MXS40IOSS_INSTANCES 1u
|
||||
#define CY_IP_MXS40IOSS_VERSION 1u
|
||||
#define CY_IP_MXEFUSE 1u
|
||||
#define CY_IP_MXEFUSE_INSTANCES 1u
|
||||
#define CY_IP_MXEFUSE_VERSION 1u
|
||||
#define CY_IP_MXPROFILE 1u
|
||||
#define CY_IP_MXPROFILE_INSTANCES 1u
|
||||
#define CY_IP_MXPROFILE_VERSION 1u
|
||||
|
||||
#include "psoc6able2_config.h"
|
||||
#include "gpio_psoc6able2_124_bga.h"
|
||||
|
||||
#define CY_DEVICE_PSOC6ABLE2
|
||||
#define CY_SILICON_ID 0xE2112100UL
|
||||
#define CY_HF_CLK_MAX_FREQ 50000000UL
|
||||
|
||||
#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL
|
||||
|
||||
/*******************************************************************************
|
||||
* SFLASH
|
||||
*******************************************************************************/
|
||||
|
||||
#define SFLASH_BASE 0x16000000UL
|
||||
#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* PERI
|
||||
*******************************************************************************/
|
||||
|
||||
#define PERI_BASE 0x40010000UL
|
||||
#define PERI_PPU_GR_MMIO0_BASE 0x40015000UL
|
||||
#define PERI_PPU_GR_MMIO1_BASE 0x40015040UL
|
||||
#define PERI_PPU_GR_MMIO2_BASE 0x40015080UL
|
||||
#define PERI_PPU_GR_MMIO3_BASE 0x400150C0UL
|
||||
#define PERI_PPU_GR_MMIO4_BASE 0x40015100UL
|
||||
#define PERI_PPU_GR_MMIO6_BASE 0x40015180UL
|
||||
#define PERI_PPU_GR_MMIO9_BASE 0x40015240UL
|
||||
#define PERI_PPU_GR_MMIO10_BASE 0x40015280UL
|
||||
#define PERI_GR_PPU_SL_PERI_GR1_BASE 0x40100000UL
|
||||
#define PERI_GR_PPU_SL_CRYPTO_BASE 0x40100040UL
|
||||
#define PERI_GR_PPU_SL_PERI_GR2_BASE 0x40200000UL
|
||||
#define PERI_GR_PPU_SL_CPUSS_BASE 0x40200040UL
|
||||
#define PERI_GR_PPU_SL_FAULT_BASE 0x40200080UL
|
||||
#define PERI_GR_PPU_SL_IPC_BASE 0x402000C0UL
|
||||
#define PERI_GR_PPU_SL_PROT_BASE 0x40200100UL
|
||||
#define PERI_GR_PPU_SL_FLASHC_BASE 0x40200140UL
|
||||
#define PERI_GR_PPU_SL_SRSS_BASE 0x40200180UL
|
||||
#define PERI_GR_PPU_SL_BACKUP_BASE 0x402001C0UL
|
||||
#define PERI_GR_PPU_SL_DW0_BASE 0x40200200UL
|
||||
#define PERI_GR_PPU_SL_DW1_BASE 0x40200240UL
|
||||
#define PERI_GR_PPU_SL_EFUSE_BASE 0x40200300UL
|
||||
#define PERI_GR_PPU_SL_PROFILE_BASE 0x40200340UL
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT0_BASE 0x40201000UL
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT1_BASE 0x40201040UL
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT2_BASE 0x40201080UL
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT3_BASE 0x402010C0UL
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT4_BASE 0x40201100UL
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT5_BASE 0x40201140UL
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT6_BASE 0x40201180UL
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT7_BASE 0x402011C0UL
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT0_BASE 0x40201200UL
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT1_BASE 0x40201240UL
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT2_BASE 0x40201280UL
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT3_BASE 0x402012C0UL
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT4_BASE 0x40201300UL
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT5_BASE 0x40201340UL
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT6_BASE 0x40201380UL
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT7_BASE 0x402013C0UL
|
||||
#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT0_BASE 0x40201400UL
|
||||
#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT1_BASE 0x40201440UL
|
||||
#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT2_BASE 0x40201480UL
|
||||
#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT3_BASE 0x402014C0UL
|
||||
#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT0_BASE 0x40201500UL
|
||||
#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT1_BASE 0x40201540UL
|
||||
#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT2_BASE 0x40201580UL
|
||||
#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT3_BASE 0x402015C0UL
|
||||
#define PERI_GR_PPU_RG_SMPU_BASE 0x40201600UL
|
||||
#define PERI_GR_PPU_RG_MPU_CM0P_BASE 0x40201640UL
|
||||
#define PERI_GR_PPU_RG_MPU_CRYPTO_BASE 0x40201680UL
|
||||
#define PERI_GR_PPU_RG_MPU_CM4_BASE 0x402016C0UL
|
||||
#define PERI_GR_PPU_RG_MPU_TC_BASE 0x40201700UL
|
||||
#define PERI_GR_PPU_SL_PERI_GR3_BASE 0x40300000UL
|
||||
#define PERI_GR_PPU_SL_HSIOM_BASE 0x40300040UL
|
||||
#define PERI_GR_PPU_SL_GPIO_BASE 0x40300080UL
|
||||
#define PERI_GR_PPU_SL_SMARTIO_BASE 0x403000C0UL
|
||||
#define PERI_GR_PPU_SL_UDB_BASE 0x40300100UL
|
||||
#define PERI_GR_PPU_SL_LPCOMP_BASE 0x40300140UL
|
||||
#define PERI_GR_PPU_SL_CSD_BASE 0x40300180UL
|
||||
#define PERI_GR_PPU_SL_TCPWM0_BASE 0x40300200UL
|
||||
#define PERI_GR_PPU_SL_TCPWM1_BASE 0x40300240UL
|
||||
#define PERI_GR_PPU_SL_LCD_BASE 0x40300280UL
|
||||
#define PERI_GR_PPU_SL_BLE_BASE 0x403002C0UL
|
||||
#define PERI_GR_PPU_SL_USBFS_BASE 0x40300300UL
|
||||
#define PERI_GR_PPU_SL_PERI_GR4_BASE 0x40400000UL
|
||||
#define PERI_GR_PPU_SL_SMIF_BASE 0x40400080UL
|
||||
#define PERI_GR_PPU_SL_PERI_GR6_BASE 0x40600000UL
|
||||
#define PERI_GR_PPU_SL_SCB0_BASE 0x40600040UL
|
||||
#define PERI_GR_PPU_SL_SCB1_BASE 0x40600080UL
|
||||
#define PERI_GR_PPU_SL_SCB2_BASE 0x406000C0UL
|
||||
#define PERI_GR_PPU_SL_SCB3_BASE 0x40600100UL
|
||||
#define PERI_GR_PPU_SL_SCB4_BASE 0x40600140UL
|
||||
#define PERI_GR_PPU_SL_SCB5_BASE 0x40600180UL
|
||||
#define PERI_GR_PPU_SL_SCB6_BASE 0x406001C0UL
|
||||
#define PERI_GR_PPU_SL_SCB7_BASE 0x40600200UL
|
||||
#define PERI_GR_PPU_SL_SCB8_BASE 0x40600240UL
|
||||
#define PERI_GR_PPU_SL_PERI_GR9_BASE 0x41000000UL
|
||||
#define PERI_GR_PPU_SL_PASS_BASE 0x41000040UL
|
||||
#define PERI_GR_PPU_SL_PERI_GR10_BASE 0x42A00000UL
|
||||
#define PERI_GR_PPU_SL_I2S_BASE 0x42A00040UL
|
||||
#define PERI_GR_PPU_SL_PDM_BASE 0x42A00080UL
|
||||
#define PERI ((PERI_Type*) PERI_BASE) /* 0x40010000 */
|
||||
#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40010000 */
|
||||
#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40010040 */
|
||||
#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40010080 */
|
||||
#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x400100C0 */
|
||||
#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40010100 */
|
||||
#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x40010180 */
|
||||
#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40010240 */
|
||||
#define PERI_GR10 ((PERI_GR_Type*) &PERI->GR[10]) /* 0x40010280 */
|
||||
#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40012000 */
|
||||
#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40012200 */
|
||||
#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40012400 */
|
||||
#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40012600 */
|
||||
#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40012800 */
|
||||
#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40012A00 */
|
||||
#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40012C00 */
|
||||
#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40012E00 */
|
||||
#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x40013000 */
|
||||
#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x40013200 */
|
||||
#define PERI_TR_GR10 ((PERI_TR_GR_Type*) &PERI->TR_GR[10]) /* 0x40013400 */
|
||||
#define PERI_TR_GR11 ((PERI_TR_GR_Type*) &PERI->TR_GR[11]) /* 0x40013600 */
|
||||
#define PERI_TR_GR12 ((PERI_TR_GR_Type*) &PERI->TR_GR[12]) /* 0x40013800 */
|
||||
#define PERI_TR_GR13 ((PERI_TR_GR_Type*) &PERI->TR_GR[13]) /* 0x40013A00 */
|
||||
#define PERI_TR_GR14 ((PERI_TR_GR_Type*) &PERI->TR_GR[14]) /* 0x40013C00 */
|
||||
#define PERI_PPU_PR0 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[0]) /* 0x40014000 */
|
||||
#define PERI_PPU_PR1 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[1]) /* 0x40014040 */
|
||||
#define PERI_PPU_PR2 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[2]) /* 0x40014080 */
|
||||
#define PERI_PPU_PR3 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[3]) /* 0x400140C0 */
|
||||
#define PERI_PPU_PR4 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[4]) /* 0x40014100 */
|
||||
#define PERI_PPU_PR5 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[5]) /* 0x40014140 */
|
||||
#define PERI_PPU_PR6 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[6]) /* 0x40014180 */
|
||||
#define PERI_PPU_PR7 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[7]) /* 0x400141C0 */
|
||||
#define PERI_PPU_PR8 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[8]) /* 0x40014200 */
|
||||
#define PERI_PPU_PR9 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[9]) /* 0x40014240 */
|
||||
#define PERI_PPU_PR10 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[10]) /* 0x40014280 */
|
||||
#define PERI_PPU_PR11 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[11]) /* 0x400142C0 */
|
||||
#define PERI_PPU_PR12 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[12]) /* 0x40014300 */
|
||||
#define PERI_PPU_PR13 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[13]) /* 0x40014340 */
|
||||
#define PERI_PPU_PR14 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[14]) /* 0x40014380 */
|
||||
#define PERI_PPU_PR15 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[15]) /* 0x400143C0 */
|
||||
#define PERI_PPU_GR0 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[0]) /* 0x40015000 */
|
||||
#define PERI_PPU_GR1 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[1]) /* 0x40015040 */
|
||||
#define PERI_PPU_GR2 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[2]) /* 0x40015080 */
|
||||
#define PERI_PPU_GR3 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[3]) /* 0x400150C0 */
|
||||
#define PERI_PPU_GR4 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[4]) /* 0x40015100 */
|
||||
#define PERI_PPU_GR6 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[6]) /* 0x40015180 */
|
||||
#define PERI_PPU_GR9 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[9]) /* 0x40015240 */
|
||||
#define PERI_PPU_GR10 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[10]) /* 0x40015280 */
|
||||
#define PERI_PPU_GR_MMIO0 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO0_BASE) /* 0x40015000 */
|
||||
#define PERI_PPU_GR_MMIO1 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO1_BASE) /* 0x40015040 */
|
||||
#define PERI_PPU_GR_MMIO2 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO2_BASE) /* 0x40015080 */
|
||||
#define PERI_PPU_GR_MMIO3 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO3_BASE) /* 0x400150C0 */
|
||||
#define PERI_PPU_GR_MMIO4 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO4_BASE) /* 0x40015100 */
|
||||
#define PERI_PPU_GR_MMIO6 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO6_BASE) /* 0x40015180 */
|
||||
#define PERI_PPU_GR_MMIO9 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO9_BASE) /* 0x40015240 */
|
||||
#define PERI_PPU_GR_MMIO10 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO10_BASE) /* 0x40015280 */
|
||||
#define PERI_GR_PPU_SL_PERI_GR1 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR1_BASE) /* 0x40100000 */
|
||||
#define PERI_GR_PPU_SL_CRYPTO ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_CRYPTO_BASE) /* 0x40100040 */
|
||||
#define PERI_GR_PPU_SL_PERI_GR2 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR2_BASE) /* 0x40200000 */
|
||||
#define PERI_GR_PPU_SL_CPUSS ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_CPUSS_BASE) /* 0x40200040 */
|
||||
#define PERI_GR_PPU_SL_FAULT ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_FAULT_BASE) /* 0x40200080 */
|
||||
#define PERI_GR_PPU_SL_IPC ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_IPC_BASE) /* 0x402000C0 */
|
||||
#define PERI_GR_PPU_SL_PROT ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PROT_BASE) /* 0x40200100 */
|
||||
#define PERI_GR_PPU_SL_FLASHC ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_FLASHC_BASE) /* 0x40200140 */
|
||||
#define PERI_GR_PPU_SL_SRSS ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SRSS_BASE) /* 0x40200180 */
|
||||
#define PERI_GR_PPU_SL_BACKUP ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_BACKUP_BASE) /* 0x402001C0 */
|
||||
#define PERI_GR_PPU_SL_DW0 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_DW0_BASE) /* 0x40200200 */
|
||||
#define PERI_GR_PPU_SL_DW1 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_DW1_BASE) /* 0x40200240 */
|
||||
#define PERI_GR_PPU_SL_EFUSE ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_EFUSE_BASE) /* 0x40200300 */
|
||||
#define PERI_GR_PPU_SL_PROFILE ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PROFILE_BASE) /* 0x40200340 */
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT0 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT0_BASE) /* 0x40201000 */
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT1 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT1_BASE) /* 0x40201040 */
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT2 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT2_BASE) /* 0x40201080 */
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT3 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT3_BASE) /* 0x402010C0 */
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT4 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT4_BASE) /* 0x40201100 */
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT5 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT5_BASE) /* 0x40201140 */
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT6 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT6_BASE) /* 0x40201180 */
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT7 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT7_BASE) /* 0x402011C0 */
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT0 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT0_BASE) /* 0x40201200 */
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT1 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT1_BASE) /* 0x40201240 */
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT2 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT2_BASE) /* 0x40201280 */
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT3 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT3_BASE) /* 0x402012C0 */
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT4 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT4_BASE) /* 0x40201300 */
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT5 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT5_BASE) /* 0x40201340 */
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT6 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT6_BASE) /* 0x40201380 */
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT7 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT7_BASE) /* 0x402013C0 */
|
||||
#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT0 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW0_DW_CH_STRUCT0_BASE) /* 0x40201400 */
|
||||
#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT1 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW0_DW_CH_STRUCT1_BASE) /* 0x40201440 */
|
||||
#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT2 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW0_DW_CH_STRUCT2_BASE) /* 0x40201480 */
|
||||
#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT3 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW0_DW_CH_STRUCT3_BASE) /* 0x402014C0 */
|
||||
#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT0 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW1_DW_CH_STRUCT0_BASE) /* 0x40201500 */
|
||||
#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT1 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW1_DW_CH_STRUCT1_BASE) /* 0x40201540 */
|
||||
#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT2 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW1_DW_CH_STRUCT2_BASE) /* 0x40201580 */
|
||||
#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT3 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW1_DW_CH_STRUCT3_BASE) /* 0x402015C0 */
|
||||
#define PERI_GR_PPU_RG_SMPU ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_SMPU_BASE) /* 0x40201600 */
|
||||
#define PERI_GR_PPU_RG_MPU_CM0P ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_MPU_CM0P_BASE) /* 0x40201640 */
|
||||
#define PERI_GR_PPU_RG_MPU_CRYPTO ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_MPU_CRYPTO_BASE) /* 0x40201680 */
|
||||
#define PERI_GR_PPU_RG_MPU_CM4 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_MPU_CM4_BASE) /* 0x402016C0 */
|
||||
#define PERI_GR_PPU_RG_MPU_TC ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_MPU_TC_BASE) /* 0x40201700 */
|
||||
#define PERI_GR_PPU_SL_PERI_GR3 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR3_BASE) /* 0x40300000 */
|
||||
#define PERI_GR_PPU_SL_HSIOM ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_HSIOM_BASE) /* 0x40300040 */
|
||||
#define PERI_GR_PPU_SL_GPIO ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_GPIO_BASE) /* 0x40300080 */
|
||||
#define PERI_GR_PPU_SL_SMARTIO ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SMARTIO_BASE) /* 0x403000C0 */
|
||||
#define PERI_GR_PPU_SL_UDB ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_UDB_BASE) /* 0x40300100 */
|
||||
#define PERI_GR_PPU_SL_LPCOMP ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_LPCOMP_BASE) /* 0x40300140 */
|
||||
#define PERI_GR_PPU_SL_CSD ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_CSD_BASE) /* 0x40300180 */
|
||||
#define PERI_GR_PPU_SL_TCPWM0 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_TCPWM0_BASE) /* 0x40300200 */
|
||||
#define PERI_GR_PPU_SL_TCPWM1 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_TCPWM1_BASE) /* 0x40300240 */
|
||||
#define PERI_GR_PPU_SL_LCD ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_LCD_BASE) /* 0x40300280 */
|
||||
#define PERI_GR_PPU_SL_BLE ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_BLE_BASE) /* 0x403002C0 */
|
||||
#define PERI_GR_PPU_SL_USBFS ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_USBFS_BASE) /* 0x40300300 */
|
||||
#define PERI_GR_PPU_SL_PERI_GR4 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR4_BASE) /* 0x40400000 */
|
||||
#define PERI_GR_PPU_SL_SMIF ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SMIF_BASE) /* 0x40400080 */
|
||||
#define PERI_GR_PPU_SL_PERI_GR6 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR6_BASE) /* 0x40600000 */
|
||||
#define PERI_GR_PPU_SL_SCB0 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB0_BASE) /* 0x40600040 */
|
||||
#define PERI_GR_PPU_SL_SCB1 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB1_BASE) /* 0x40600080 */
|
||||
#define PERI_GR_PPU_SL_SCB2 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB2_BASE) /* 0x406000C0 */
|
||||
#define PERI_GR_PPU_SL_SCB3 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB3_BASE) /* 0x40600100 */
|
||||
#define PERI_GR_PPU_SL_SCB4 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB4_BASE) /* 0x40600140 */
|
||||
#define PERI_GR_PPU_SL_SCB5 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB5_BASE) /* 0x40600180 */
|
||||
#define PERI_GR_PPU_SL_SCB6 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB6_BASE) /* 0x406001C0 */
|
||||
#define PERI_GR_PPU_SL_SCB7 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB7_BASE) /* 0x40600200 */
|
||||
#define PERI_GR_PPU_SL_SCB8 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB8_BASE) /* 0x40600240 */
|
||||
#define PERI_GR_PPU_SL_PERI_GR9 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR9_BASE) /* 0x41000000 */
|
||||
#define PERI_GR_PPU_SL_PASS ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PASS_BASE) /* 0x41000040 */
|
||||
#define PERI_GR_PPU_SL_PERI_GR10 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR10_BASE) /* 0x42A00000 */
|
||||
#define PERI_GR_PPU_SL_I2S ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_I2S_BASE) /* 0x42A00040 */
|
||||
#define PERI_GR_PPU_SL_PDM ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PDM_BASE) /* 0x42A00080 */
|
||||
|
||||
/*******************************************************************************
|
||||
* CPUSS
|
||||
*******************************************************************************/
|
||||
|
||||
#define CPUSS_BASE 0x40210000UL
|
||||
#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40210000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* FAULT
|
||||
*******************************************************************************/
|
||||
|
||||
#define FAULT_BASE 0x40220000UL
|
||||
#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40220000 */
|
||||
#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40220000 */
|
||||
#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40220100 */
|
||||
|
||||
/*******************************************************************************
|
||||
* IPC
|
||||
*******************************************************************************/
|
||||
|
||||
#define IPC_BASE 0x40230000UL
|
||||
#define IPC ((IPC_Type*) IPC_BASE) /* 0x40230000 */
|
||||
#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40230000 */
|
||||
#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40230020 */
|
||||
#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40230040 */
|
||||
#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40230060 */
|
||||
#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40230080 */
|
||||
#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402300A0 */
|
||||
#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402300C0 */
|
||||
#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402300E0 */
|
||||
#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40230100 */
|
||||
#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40230120 */
|
||||
#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40230140 */
|
||||
#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40230160 */
|
||||
#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40230180 */
|
||||
#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402301A0 */
|
||||
#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402301C0 */
|
||||
#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402301E0 */
|
||||
#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40231000 */
|
||||
#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40231020 */
|
||||
#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40231040 */
|
||||
#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40231060 */
|
||||
#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40231080 */
|
||||
#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402310A0 */
|
||||
#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402310C0 */
|
||||
#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402310E0 */
|
||||
#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40231100 */
|
||||
#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40231120 */
|
||||
#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40231140 */
|
||||
#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40231160 */
|
||||
#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40231180 */
|
||||
#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402311A0 */
|
||||
#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402311C0 */
|
||||
#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402311E0 */
|
||||
|
||||
/*******************************************************************************
|
||||
* PROT
|
||||
*******************************************************************************/
|
||||
|
||||
#define PROT_BASE 0x40240000UL
|
||||
#define PROT ((PROT_Type*) PROT_BASE) /* 0x40240000 */
|
||||
#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40242000 */
|
||||
#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40242040 */
|
||||
#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40242080 */
|
||||
#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402420C0 */
|
||||
#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40242100 */
|
||||
#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40242140 */
|
||||
#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40242180 */
|
||||
#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402421C0 */
|
||||
#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40242200 */
|
||||
#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40242240 */
|
||||
#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40242280 */
|
||||
#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402422C0 */
|
||||
#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40242300 */
|
||||
#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40242340 */
|
||||
#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40242380 */
|
||||
#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402423C0 */
|
||||
#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */
|
||||
#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */
|
||||
#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */
|
||||
#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */
|
||||
#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */
|
||||
#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */
|
||||
#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */
|
||||
#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */
|
||||
#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */
|
||||
#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */
|
||||
#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */
|
||||
#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */
|
||||
#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */
|
||||
#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */
|
||||
#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */
|
||||
#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */
|
||||
#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */
|
||||
#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40244000 */
|
||||
#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40244400 */
|
||||
#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40244800 */
|
||||
#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40244C00 */
|
||||
#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40245000 */
|
||||
#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40245400 */
|
||||
#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40245800 */
|
||||
#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40245C00 */
|
||||
#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40246000 */
|
||||
#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40246400 */
|
||||
#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40246800 */
|
||||
#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40246C00 */
|
||||
#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40247000 */
|
||||
#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40247400 */
|
||||
#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40247800 */
|
||||
#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40247C00 */
|
||||
|
||||
/*******************************************************************************
|
||||
* FLASHC
|
||||
*******************************************************************************/
|
||||
|
||||
#define FLASHC_BASE 0x40250000UL
|
||||
#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40250000 */
|
||||
#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4025F000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* SRSS
|
||||
*******************************************************************************/
|
||||
|
||||
#define SRSS_BASE 0x40260000UL
|
||||
#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */
|
||||
#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */
|
||||
#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */
|
||||
|
||||
/*******************************************************************************
|
||||
* BACKUP
|
||||
*******************************************************************************/
|
||||
|
||||
#define BACKUP_BASE 0x40270000UL
|
||||
#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* DW
|
||||
*******************************************************************************/
|
||||
|
||||
#define DW0_BASE 0x40280000UL
|
||||
#define DW1_BASE 0x40281000UL
|
||||
#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */
|
||||
#define DW1 ((DW_Type*) DW1_BASE) /* 0x40281000 */
|
||||
#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40280800 */
|
||||
#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40280820 */
|
||||
#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40280840 */
|
||||
#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x40280860 */
|
||||
#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40280880 */
|
||||
#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x402808A0 */
|
||||
#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x402808C0 */
|
||||
#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402808E0 */
|
||||
#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40280900 */
|
||||
#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40280920 */
|
||||
#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40280940 */
|
||||
#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x40280960 */
|
||||
#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40280980 */
|
||||
#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x402809A0 */
|
||||
#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x402809C0 */
|
||||
#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402809E0 */
|
||||
#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40281800 */
|
||||
#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40281820 */
|
||||
#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40281840 */
|
||||
#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x40281860 */
|
||||
#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40281880 */
|
||||
#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x402818A0 */
|
||||
#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x402818C0 */
|
||||
#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402818E0 */
|
||||
#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40281900 */
|
||||
#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40281920 */
|
||||
#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40281940 */
|
||||
#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x40281960 */
|
||||
#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40281980 */
|
||||
#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x402819A0 */
|
||||
#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x402819C0 */
|
||||
#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402819E0 */
|
||||
|
||||
/*******************************************************************************
|
||||
* EFUSE
|
||||
*******************************************************************************/
|
||||
|
||||
#define EFUSE_BASE 0x402C0000UL
|
||||
#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* PROFILE
|
||||
*******************************************************************************/
|
||||
|
||||
#define PROFILE_BASE 0x402D0000UL
|
||||
#define PROFILE ((PROFILE_Type*) PROFILE_BASE) /* 0x402D0000 */
|
||||
#define PROFILE_CNT_STRUCT0 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[0]) /* 0x402D0800 */
|
||||
#define PROFILE_CNT_STRUCT1 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[1]) /* 0x402D0810 */
|
||||
#define PROFILE_CNT_STRUCT2 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[2]) /* 0x402D0820 */
|
||||
#define PROFILE_CNT_STRUCT3 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[3]) /* 0x402D0830 */
|
||||
#define PROFILE_CNT_STRUCT4 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[4]) /* 0x402D0840 */
|
||||
#define PROFILE_CNT_STRUCT5 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[5]) /* 0x402D0850 */
|
||||
#define PROFILE_CNT_STRUCT6 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[6]) /* 0x402D0860 */
|
||||
#define PROFILE_CNT_STRUCT7 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[7]) /* 0x402D0870 */
|
||||
|
||||
/*******************************************************************************
|
||||
* HSIOM
|
||||
*******************************************************************************/
|
||||
|
||||
#define HSIOM_BASE 0x40310000UL
|
||||
#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40310000 */
|
||||
#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40310000 */
|
||||
#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40310010 */
|
||||
#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40310020 */
|
||||
#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40310030 */
|
||||
#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40310040 */
|
||||
#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40310050 */
|
||||
#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40310060 */
|
||||
#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40310070 */
|
||||
#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40310080 */
|
||||
#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40310090 */
|
||||
#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403100A0 */
|
||||
#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403100B0 */
|
||||
#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403100C0 */
|
||||
#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403100D0 */
|
||||
#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403100E0 */
|
||||
|
||||
/*******************************************************************************
|
||||
* GPIO
|
||||
*******************************************************************************/
|
||||
|
||||
#define GPIO_BASE 0x40320000UL
|
||||
#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40320000 */
|
||||
#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40320000 */
|
||||
#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40320080 */
|
||||
#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40320100 */
|
||||
#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40320180 */
|
||||
#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40320200 */
|
||||
#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40320280 */
|
||||
#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40320300 */
|
||||
#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40320380 */
|
||||
#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40320400 */
|
||||
#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40320480 */
|
||||
#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40320500 */
|
||||
#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40320580 */
|
||||
#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40320600 */
|
||||
#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40320680 */
|
||||
#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40320700 */
|
||||
|
||||
/*******************************************************************************
|
||||
* SMARTIO
|
||||
*******************************************************************************/
|
||||
|
||||
#define SMARTIO_BASE 0x40330000UL
|
||||
#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40330000 */
|
||||
#define SMARTIO_PRT8 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[8]) /* 0x40330800 */
|
||||
#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40330900 */
|
||||
|
||||
/*******************************************************************************
|
||||
* LPCOMP
|
||||
*******************************************************************************/
|
||||
|
||||
#define LPCOMP_BASE 0x40350000UL
|
||||
#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* CSD
|
||||
*******************************************************************************/
|
||||
|
||||
#define CSD0_BASE 0x40360000UL
|
||||
#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* TCPWM
|
||||
*******************************************************************************/
|
||||
|
||||
#define TCPWM0_BASE 0x40380000UL
|
||||
#define TCPWM1_BASE 0x40390000UL
|
||||
#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */
|
||||
#define TCPWM1 ((TCPWM_Type*) TCPWM1_BASE) /* 0x40390000 */
|
||||
#define TCPWM0_CNT0 ((TCPWM_CNT_Type*) &TCPWM0->CNT[0]) /* 0x40380100 */
|
||||
#define TCPWM0_CNT1 ((TCPWM_CNT_Type*) &TCPWM0->CNT[1]) /* 0x40380140 */
|
||||
#define TCPWM0_CNT2 ((TCPWM_CNT_Type*) &TCPWM0->CNT[2]) /* 0x40380180 */
|
||||
#define TCPWM0_CNT3 ((TCPWM_CNT_Type*) &TCPWM0->CNT[3]) /* 0x403801C0 */
|
||||
#define TCPWM0_CNT4 ((TCPWM_CNT_Type*) &TCPWM0->CNT[4]) /* 0x40380200 */
|
||||
#define TCPWM0_CNT5 ((TCPWM_CNT_Type*) &TCPWM0->CNT[5]) /* 0x40380240 */
|
||||
#define TCPWM0_CNT6 ((TCPWM_CNT_Type*) &TCPWM0->CNT[6]) /* 0x40380280 */
|
||||
#define TCPWM0_CNT7 ((TCPWM_CNT_Type*) &TCPWM0->CNT[7]) /* 0x403802C0 */
|
||||
#define TCPWM1_CNT0 ((TCPWM_CNT_Type*) &TCPWM1->CNT[0]) /* 0x40390100 */
|
||||
#define TCPWM1_CNT1 ((TCPWM_CNT_Type*) &TCPWM1->CNT[1]) /* 0x40390140 */
|
||||
#define TCPWM1_CNT2 ((TCPWM_CNT_Type*) &TCPWM1->CNT[2]) /* 0x40390180 */
|
||||
#define TCPWM1_CNT3 ((TCPWM_CNT_Type*) &TCPWM1->CNT[3]) /* 0x403901C0 */
|
||||
#define TCPWM1_CNT4 ((TCPWM_CNT_Type*) &TCPWM1->CNT[4]) /* 0x40390200 */
|
||||
#define TCPWM1_CNT5 ((TCPWM_CNT_Type*) &TCPWM1->CNT[5]) /* 0x40390240 */
|
||||
#define TCPWM1_CNT6 ((TCPWM_CNT_Type*) &TCPWM1->CNT[6]) /* 0x40390280 */
|
||||
#define TCPWM1_CNT7 ((TCPWM_CNT_Type*) &TCPWM1->CNT[7]) /* 0x403902C0 */
|
||||
#define TCPWM1_CNT8 ((TCPWM_CNT_Type*) &TCPWM1->CNT[8]) /* 0x40390300 */
|
||||
#define TCPWM1_CNT9 ((TCPWM_CNT_Type*) &TCPWM1->CNT[9]) /* 0x40390340 */
|
||||
#define TCPWM1_CNT10 ((TCPWM_CNT_Type*) &TCPWM1->CNT[10]) /* 0x40390380 */
|
||||
#define TCPWM1_CNT11 ((TCPWM_CNT_Type*) &TCPWM1->CNT[11]) /* 0x403903C0 */
|
||||
#define TCPWM1_CNT12 ((TCPWM_CNT_Type*) &TCPWM1->CNT[12]) /* 0x40390400 */
|
||||
#define TCPWM1_CNT13 ((TCPWM_CNT_Type*) &TCPWM1->CNT[13]) /* 0x40390440 */
|
||||
#define TCPWM1_CNT14 ((TCPWM_CNT_Type*) &TCPWM1->CNT[14]) /* 0x40390480 */
|
||||
#define TCPWM1_CNT15 ((TCPWM_CNT_Type*) &TCPWM1->CNT[15]) /* 0x403904C0 */
|
||||
#define TCPWM1_CNT16 ((TCPWM_CNT_Type*) &TCPWM1->CNT[16]) /* 0x40390500 */
|
||||
#define TCPWM1_CNT17 ((TCPWM_CNT_Type*) &TCPWM1->CNT[17]) /* 0x40390540 */
|
||||
#define TCPWM1_CNT18 ((TCPWM_CNT_Type*) &TCPWM1->CNT[18]) /* 0x40390580 */
|
||||
#define TCPWM1_CNT19 ((TCPWM_CNT_Type*) &TCPWM1->CNT[19]) /* 0x403905C0 */
|
||||
#define TCPWM1_CNT20 ((TCPWM_CNT_Type*) &TCPWM1->CNT[20]) /* 0x40390600 */
|
||||
#define TCPWM1_CNT21 ((TCPWM_CNT_Type*) &TCPWM1->CNT[21]) /* 0x40390640 */
|
||||
#define TCPWM1_CNT22 ((TCPWM_CNT_Type*) &TCPWM1->CNT[22]) /* 0x40390680 */
|
||||
#define TCPWM1_CNT23 ((TCPWM_CNT_Type*) &TCPWM1->CNT[23]) /* 0x403906C0 */
|
||||
|
||||
/*******************************************************************************
|
||||
* LCD
|
||||
*******************************************************************************/
|
||||
|
||||
#define LCD0_BASE 0x403B0000UL
|
||||
#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* USBFS
|
||||
*******************************************************************************/
|
||||
|
||||
#define USBFS0_BASE 0x403F0000UL
|
||||
#define USBFS0 ((USBFS_Type*) USBFS0_BASE) /* 0x403F0000 */
|
||||
#define USBFS0_USBDEV ((USBFS_USBDEV_Type*) &USBFS0->USBDEV) /* 0x403F0000 */
|
||||
#define USBFS0_USBLPM ((USBFS_USBLPM_Type*) &USBFS0->USBLPM) /* 0x403F2000 */
|
||||
#define USBFS0_USBHOST ((USBFS_USBHOST_Type*) &USBFS0->USBHOST) /* 0x403F4000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* SMIF
|
||||
*******************************************************************************/
|
||||
|
||||
#define SMIF0_BASE 0x40420000UL
|
||||
#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */
|
||||
#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */
|
||||
#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */
|
||||
#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */
|
||||
#define SMIF0_DEVICE3 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[3]) /* 0x40420980 */
|
||||
|
||||
/*******************************************************************************
|
||||
* SCB
|
||||
*******************************************************************************/
|
||||
|
||||
#define SCB0_BASE 0x40610000UL
|
||||
#define SCB1_BASE 0x40620000UL
|
||||
#define SCB2_BASE 0x40630000UL
|
||||
#define SCB3_BASE 0x40640000UL
|
||||
#define SCB4_BASE 0x40650000UL
|
||||
#define SCB5_BASE 0x40660000UL
|
||||
#define SCB6_BASE 0x40670000UL
|
||||
#define SCB7_BASE 0x40680000UL
|
||||
#define SCB8_BASE 0x40690000UL
|
||||
#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40610000 */
|
||||
#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40620000 */
|
||||
#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40630000 */
|
||||
#define SCB3 ((CySCB_Type*) SCB3_BASE) /* 0x40640000 */
|
||||
#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40650000 */
|
||||
#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40660000 */
|
||||
#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40670000 */
|
||||
#define SCB7 ((CySCB_Type*) SCB7_BASE) /* 0x40680000 */
|
||||
#define SCB8 ((CySCB_Type*) SCB8_BASE) /* 0x40690000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* CTDAC
|
||||
*******************************************************************************/
|
||||
|
||||
#define CTDAC0_BASE 0x41140000UL
|
||||
#define CTDAC0 ((CTDAC_Type*) CTDAC0_BASE) /* 0x41140000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* SAR
|
||||
*******************************************************************************/
|
||||
|
||||
#define SAR_BASE 0x411D0000UL
|
||||
#define SAR ((SAR_Type*) SAR_BASE) /* 0x411D0000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* PASS
|
||||
*******************************************************************************/
|
||||
|
||||
#define PASS_BASE 0x411F0000UL
|
||||
#define PASS ((PASS_Type*) PASS_BASE) /* 0x411F0000 */
|
||||
#define PASS_AREF ((PASS_AREF_Type*) &PASS->AREF) /* 0x411F0E00 */
|
||||
|
||||
/*******************************************************************************
|
||||
* I2S
|
||||
*******************************************************************************/
|
||||
|
||||
#define I2S0_BASE 0x42A10000UL
|
||||
#define I2S0 ((I2S_Type*) I2S0_BASE) /* 0x42A10000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* PDM
|
||||
*******************************************************************************/
|
||||
|
||||
#define PDM0_BASE 0x42A20000UL
|
||||
#define PDM0 ((PDM_Type*) PDM0_BASE) /* 0x42A20000 */
|
||||
|
||||
|
||||
/* Backward compabitility definitions */
|
||||
#define I2S I2S0
|
||||
#define PDM PDM0
|
||||
|
||||
/** \} CY8C6016BZI-F04 */
|
||||
|
||||
#endif /* _CY8C6016BZI_F04_H_ */
|
||||
|
||||
|
||||
/* [] END OF FILE */
|
||||
|
|
@ -1,933 +0,0 @@
|
|||
/***************************************************************************//**
|
||||
* \file cy8c6036bzi_f04.h
|
||||
*
|
||||
* \brief
|
||||
* CY8C6036BZI-F04 device header
|
||||
*
|
||||
* \note
|
||||
* Generator version: 1.3.0.1146
|
||||
* Database revision: rev#1050929
|
||||
*
|
||||
********************************************************************************
|
||||
* \copyright
|
||||
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
|
||||
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _CY8C6036BZI_F04_H_
|
||||
#define _CY8C6036BZI_F04_H_
|
||||
|
||||
/**
|
||||
* \addtogroup group_device CY8C6036BZI-F04
|
||||
* \{
|
||||
*/
|
||||
|
||||
/**
|
||||
* \addtogroup Configuration_of_CMSIS
|
||||
* \{
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Interrupt Number Definition
|
||||
*******************************************************************************/
|
||||
|
||||
typedef enum {
|
||||
/* ARM Cortex-M4 Core Interrupt Numbers */
|
||||
Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */
|
||||
NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */
|
||||
HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */
|
||||
MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */
|
||||
BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */
|
||||
UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
|
||||
SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */
|
||||
DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */
|
||||
PendSV_IRQn = -2, /*!< -2 Pendable request for system service */
|
||||
SysTick_IRQn = -1, /*!< -1 System Tick Timer */
|
||||
/* CY8C6036BZI-F04 Peripheral Interrupt Numbers */
|
||||
ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */
|
||||
ioss_interrupts_gpio_1_IRQn = 1, /*!< 1 [DeepSleep] GPIO Port Interrupt #1 */
|
||||
ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */
|
||||
ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */
|
||||
ioss_interrupts_gpio_4_IRQn = 4, /*!< 4 [DeepSleep] GPIO Port Interrupt #4 */
|
||||
ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */
|
||||
ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */
|
||||
ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */
|
||||
ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */
|
||||
ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */
|
||||
ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */
|
||||
ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */
|
||||
ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */
|
||||
ioss_interrupts_gpio_13_IRQn = 13, /*!< 13 [DeepSleep] GPIO Port Interrupt #13 */
|
||||
ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */
|
||||
ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */
|
||||
ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */
|
||||
lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */
|
||||
scb_8_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #8 (DeepSleep capable) */
|
||||
srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */
|
||||
srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */
|
||||
srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */
|
||||
srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */
|
||||
pass_interrupt_ctbs_IRQn = 23, /*!< 23 [DeepSleep] CTBm Interrupt (all CTBms) */
|
||||
bless_interrupt_IRQn = 24, /*!< 24 [DeepSleep] Bluetooth Radio interrupt */
|
||||
cpuss_interrupts_ipc_0_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */
|
||||
cpuss_interrupts_ipc_1_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */
|
||||
cpuss_interrupts_ipc_2_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */
|
||||
cpuss_interrupts_ipc_3_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */
|
||||
cpuss_interrupts_ipc_4_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */
|
||||
cpuss_interrupts_ipc_5_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */
|
||||
cpuss_interrupts_ipc_6_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */
|
||||
cpuss_interrupts_ipc_7_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */
|
||||
cpuss_interrupts_ipc_8_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */
|
||||
cpuss_interrupts_ipc_9_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */
|
||||
cpuss_interrupts_ipc_10_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */
|
||||
cpuss_interrupts_ipc_11_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */
|
||||
cpuss_interrupts_ipc_12_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */
|
||||
cpuss_interrupts_ipc_13_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */
|
||||
cpuss_interrupts_ipc_14_IRQn = 39, /*!< 39 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */
|
||||
cpuss_interrupts_ipc_15_IRQn = 40, /*!< 40 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */
|
||||
scb_0_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #0 */
|
||||
scb_1_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #1 */
|
||||
scb_2_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #2 */
|
||||
scb_3_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #3 */
|
||||
scb_4_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #4 */
|
||||
scb_5_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #5 */
|
||||
scb_6_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #6 */
|
||||
scb_7_interrupt_IRQn = 48, /*!< 48 [Active] Serial Communication Block #7 */
|
||||
csd_interrupt_IRQn = 49, /*!< 49 [Active] CSD (Capsense) interrupt */
|
||||
cpuss_interrupts_dw0_0_IRQn = 50, /*!< 50 [Active] CPUSS DataWire #0, Channel #0 */
|
||||
cpuss_interrupts_dw0_1_IRQn = 51, /*!< 51 [Active] CPUSS DataWire #0, Channel #1 */
|
||||
cpuss_interrupts_dw0_2_IRQn = 52, /*!< 52 [Active] CPUSS DataWire #0, Channel #2 */
|
||||
cpuss_interrupts_dw0_3_IRQn = 53, /*!< 53 [Active] CPUSS DataWire #0, Channel #3 */
|
||||
cpuss_interrupts_dw0_4_IRQn = 54, /*!< 54 [Active] CPUSS DataWire #0, Channel #4 */
|
||||
cpuss_interrupts_dw0_5_IRQn = 55, /*!< 55 [Active] CPUSS DataWire #0, Channel #5 */
|
||||
cpuss_interrupts_dw0_6_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #6 */
|
||||
cpuss_interrupts_dw0_7_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #7 */
|
||||
cpuss_interrupts_dw0_8_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #8 */
|
||||
cpuss_interrupts_dw0_9_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #9 */
|
||||
cpuss_interrupts_dw0_10_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #10 */
|
||||
cpuss_interrupts_dw0_11_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #11 */
|
||||
cpuss_interrupts_dw0_12_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #12 */
|
||||
cpuss_interrupts_dw0_13_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #13 */
|
||||
cpuss_interrupts_dw0_14_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #14 */
|
||||
cpuss_interrupts_dw0_15_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #15 */
|
||||
cpuss_interrupts_dw1_0_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #1, Channel #0 */
|
||||
cpuss_interrupts_dw1_1_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #1, Channel #1 */
|
||||
cpuss_interrupts_dw1_2_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #1, Channel #2 */
|
||||
cpuss_interrupts_dw1_3_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #1, Channel #3 */
|
||||
cpuss_interrupts_dw1_4_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #1, Channel #4 */
|
||||
cpuss_interrupts_dw1_5_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #1, Channel #5 */
|
||||
cpuss_interrupts_dw1_6_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #1, Channel #6 */
|
||||
cpuss_interrupts_dw1_7_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #1, Channel #7 */
|
||||
cpuss_interrupts_dw1_8_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #1, Channel #8 */
|
||||
cpuss_interrupts_dw1_9_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #1, Channel #9 */
|
||||
cpuss_interrupts_dw1_10_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #1, Channel #10 */
|
||||
cpuss_interrupts_dw1_11_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #1, Channel #11 */
|
||||
cpuss_interrupts_dw1_12_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #1, Channel #12 */
|
||||
cpuss_interrupts_dw1_13_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #1, Channel #13 */
|
||||
cpuss_interrupts_dw1_14_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #1, Channel #14 */
|
||||
cpuss_interrupts_dw1_15_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #1, Channel #15 */
|
||||
cpuss_interrupts_fault_0_IRQn = 82, /*!< 82 [Active] CPUSS Fault Structure Interrupt #0 */
|
||||
cpuss_interrupts_fault_1_IRQn = 83, /*!< 83 [Active] CPUSS Fault Structure Interrupt #1 */
|
||||
cpuss_interrupt_crypto_IRQn = 84, /*!< 84 [Active] CRYPTO Accelerator Interrupt */
|
||||
cpuss_interrupt_fm_IRQn = 85, /*!< 85 [Active] FLASH Macro Interrupt */
|
||||
cpuss_interrupts_cm0_cti_0_IRQn = 86, /*!< 86 [Active] CM0+ CTI #0 */
|
||||
cpuss_interrupts_cm0_cti_1_IRQn = 87, /*!< 87 [Active] CM0+ CTI #1 */
|
||||
cpuss_interrupts_cm4_cti_0_IRQn = 88, /*!< 88 [Active] CM4 CTI #0 */
|
||||
cpuss_interrupts_cm4_cti_1_IRQn = 89, /*!< 89 [Active] CM4 CTI #1 */
|
||||
tcpwm_0_interrupts_0_IRQn = 90, /*!< 90 [Active] TCPWM #0, Counter #0 */
|
||||
tcpwm_0_interrupts_1_IRQn = 91, /*!< 91 [Active] TCPWM #0, Counter #1 */
|
||||
tcpwm_0_interrupts_2_IRQn = 92, /*!< 92 [Active] TCPWM #0, Counter #2 */
|
||||
tcpwm_0_interrupts_3_IRQn = 93, /*!< 93 [Active] TCPWM #0, Counter #3 */
|
||||
tcpwm_0_interrupts_4_IRQn = 94, /*!< 94 [Active] TCPWM #0, Counter #4 */
|
||||
tcpwm_0_interrupts_5_IRQn = 95, /*!< 95 [Active] TCPWM #0, Counter #5 */
|
||||
tcpwm_0_interrupts_6_IRQn = 96, /*!< 96 [Active] TCPWM #0, Counter #6 */
|
||||
tcpwm_0_interrupts_7_IRQn = 97, /*!< 97 [Active] TCPWM #0, Counter #7 */
|
||||
tcpwm_1_interrupts_0_IRQn = 98, /*!< 98 [Active] TCPWM #1, Counter #0 */
|
||||
tcpwm_1_interrupts_1_IRQn = 99, /*!< 99 [Active] TCPWM #1, Counter #1 */
|
||||
tcpwm_1_interrupts_2_IRQn = 100, /*!< 100 [Active] TCPWM #1, Counter #2 */
|
||||
tcpwm_1_interrupts_3_IRQn = 101, /*!< 101 [Active] TCPWM #1, Counter #3 */
|
||||
tcpwm_1_interrupts_4_IRQn = 102, /*!< 102 [Active] TCPWM #1, Counter #4 */
|
||||
tcpwm_1_interrupts_5_IRQn = 103, /*!< 103 [Active] TCPWM #1, Counter #5 */
|
||||
tcpwm_1_interrupts_6_IRQn = 104, /*!< 104 [Active] TCPWM #1, Counter #6 */
|
||||
tcpwm_1_interrupts_7_IRQn = 105, /*!< 105 [Active] TCPWM #1, Counter #7 */
|
||||
tcpwm_1_interrupts_8_IRQn = 106, /*!< 106 [Active] TCPWM #1, Counter #8 */
|
||||
tcpwm_1_interrupts_9_IRQn = 107, /*!< 107 [Active] TCPWM #1, Counter #9 */
|
||||
tcpwm_1_interrupts_10_IRQn = 108, /*!< 108 [Active] TCPWM #1, Counter #10 */
|
||||
tcpwm_1_interrupts_11_IRQn = 109, /*!< 109 [Active] TCPWM #1, Counter #11 */
|
||||
tcpwm_1_interrupts_12_IRQn = 110, /*!< 110 [Active] TCPWM #1, Counter #12 */
|
||||
tcpwm_1_interrupts_13_IRQn = 111, /*!< 111 [Active] TCPWM #1, Counter #13 */
|
||||
tcpwm_1_interrupts_14_IRQn = 112, /*!< 112 [Active] TCPWM #1, Counter #14 */
|
||||
tcpwm_1_interrupts_15_IRQn = 113, /*!< 113 [Active] TCPWM #1, Counter #15 */
|
||||
tcpwm_1_interrupts_16_IRQn = 114, /*!< 114 [Active] TCPWM #1, Counter #16 */
|
||||
tcpwm_1_interrupts_17_IRQn = 115, /*!< 115 [Active] TCPWM #1, Counter #17 */
|
||||
tcpwm_1_interrupts_18_IRQn = 116, /*!< 116 [Active] TCPWM #1, Counter #18 */
|
||||
tcpwm_1_interrupts_19_IRQn = 117, /*!< 117 [Active] TCPWM #1, Counter #19 */
|
||||
tcpwm_1_interrupts_20_IRQn = 118, /*!< 118 [Active] TCPWM #1, Counter #20 */
|
||||
tcpwm_1_interrupts_21_IRQn = 119, /*!< 119 [Active] TCPWM #1, Counter #21 */
|
||||
tcpwm_1_interrupts_22_IRQn = 120, /*!< 120 [Active] TCPWM #1, Counter #22 */
|
||||
tcpwm_1_interrupts_23_IRQn = 121, /*!< 121 [Active] TCPWM #1, Counter #23 */
|
||||
udb_interrupts_0_IRQn = 122, /*!< 122 [Active] UDB Interrupt #0 */
|
||||
udb_interrupts_1_IRQn = 123, /*!< 123 [Active] UDB Interrupt #1 */
|
||||
udb_interrupts_2_IRQn = 124, /*!< 124 [Active] UDB Interrupt #2 */
|
||||
udb_interrupts_3_IRQn = 125, /*!< 125 [Active] UDB Interrupt #3 */
|
||||
udb_interrupts_4_IRQn = 126, /*!< 126 [Active] UDB Interrupt #4 */
|
||||
udb_interrupts_5_IRQn = 127, /*!< 127 [Active] UDB Interrupt #5 */
|
||||
udb_interrupts_6_IRQn = 128, /*!< 128 [Active] UDB Interrupt #6 */
|
||||
udb_interrupts_7_IRQn = 129, /*!< 129 [Active] UDB Interrupt #7 */
|
||||
udb_interrupts_8_IRQn = 130, /*!< 130 [Active] UDB Interrupt #8 */
|
||||
udb_interrupts_9_IRQn = 131, /*!< 131 [Active] UDB Interrupt #9 */
|
||||
udb_interrupts_10_IRQn = 132, /*!< 132 [Active] UDB Interrupt #10 */
|
||||
udb_interrupts_11_IRQn = 133, /*!< 133 [Active] UDB Interrupt #11 */
|
||||
udb_interrupts_12_IRQn = 134, /*!< 134 [Active] UDB Interrupt #12 */
|
||||
udb_interrupts_13_IRQn = 135, /*!< 135 [Active] UDB Interrupt #13 */
|
||||
udb_interrupts_14_IRQn = 136, /*!< 136 [Active] UDB Interrupt #14 */
|
||||
udb_interrupts_15_IRQn = 137, /*!< 137 [Active] UDB Interrupt #15 */
|
||||
pass_interrupt_sar_IRQn = 138, /*!< 138 [Active] SAR ADC interrupt */
|
||||
audioss_interrupt_i2s_IRQn = 139, /*!< 139 [Active] I2S Audio interrupt */
|
||||
audioss_interrupt_pdm_IRQn = 140, /*!< 140 [Active] PDM/PCM Audio interrupt */
|
||||
profile_interrupt_IRQn = 141, /*!< 141 [Active] Energy Profiler interrupt */
|
||||
smif_interrupt_IRQn = 142, /*!< 142 [Active] Serial Memory Interface interrupt */
|
||||
usb_interrupt_hi_IRQn = 143, /*!< 143 [Active] USB Interrupt */
|
||||
usb_interrupt_med_IRQn = 144, /*!< 144 [Active] USB Interrupt */
|
||||
usb_interrupt_lo_IRQn = 145, /*!< 145 [Active] USB Interrupt */
|
||||
pass_interrupt_dacs_IRQn = 146, /*!< 146 [Active] Consolidated interrrupt for all DACs */
|
||||
unconnected_IRQn = 240 /*!< 240 Unconnected */
|
||||
} IRQn_Type;
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Processor and Core Peripheral Section
|
||||
*******************************************************************************/
|
||||
|
||||
/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */
|
||||
#define __CM4_REV 0x0001U /*!< CM4 Core Revision */
|
||||
#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
|
||||
#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */
|
||||
#define __MPU_PRESENT 1 /*!< MPU present or not */
|
||||
#define __FPU_PRESENT 1 /*!< FPU present or not */
|
||||
#define __CM0P_PRESENT 0 /*!< CM0P present or not */
|
||||
|
||||
/** \} Configuration_of_CMSIS */
|
||||
|
||||
/* Memory Blocks */
|
||||
#define CY_ROM_BASE 0x00000000UL
|
||||
#define CY_ROM_SIZE 0x00020000UL
|
||||
#define CY_SRAM0_BASE 0x08000000UL
|
||||
#define CY_SRAM0_SIZE 0x00020000UL
|
||||
#define CY_FLASH_BASE 0x10000000UL
|
||||
#define CY_FLASH_SIZE 0x00080000UL
|
||||
#define CY_EM_EEPROM_BASE 0x14000000UL
|
||||
#define CY_EM_EEPROM_SIZE 0x00008000UL
|
||||
#define CY_XIP_BASE 0x18000000UL
|
||||
#define CY_XIP_SIZE 0x08000000UL
|
||||
#define CY_SFLASH_BASE 0x16000000UL
|
||||
#define CY_SFLASH_SIZE 0x00008000UL
|
||||
#define CY_EFUSE_BASE 0x402C0800UL
|
||||
#define CY_EFUSE_SIZE 0x00000200UL
|
||||
|
||||
#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */
|
||||
#include "system_psoc6.h" /*!< PSoC 6 System */
|
||||
|
||||
/* IP List */
|
||||
#define CY_IP_MXTCPWM 1u
|
||||
#define CY_IP_MXTCPWM_INSTANCES 2u
|
||||
#define CY_IP_MXTCPWM_VERSION 1u
|
||||
#define CY_IP_MXCSDV2 1u
|
||||
#define CY_IP_MXCSDV2_INSTANCES 1u
|
||||
#define CY_IP_MXCSDV2_VERSION 1u
|
||||
#define CY_IP_MXLCD 1u
|
||||
#define CY_IP_MXLCD_INSTANCES 1u
|
||||
#define CY_IP_MXLCD_VERSION 1u
|
||||
#define CY_IP_MXS40SRSS 1u
|
||||
#define CY_IP_MXS40SRSS_INSTANCES 1u
|
||||
#define CY_IP_MXS40SRSS_VERSION 1u
|
||||
#define CY_IP_MXS40SRSS_RTC 1u
|
||||
#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u
|
||||
#define CY_IP_MXS40SRSS_RTC_VERSION 1u
|
||||
#define CY_IP_MXS40SRSS_MCWDT 1u
|
||||
#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u
|
||||
#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u
|
||||
#define CY_IP_MXSCB 1u
|
||||
#define CY_IP_MXSCB_INSTANCES 9u
|
||||
#define CY_IP_MXSCB_VERSION 1u
|
||||
#define CY_IP_MXPERI 1u
|
||||
#define CY_IP_MXPERI_INSTANCES 1u
|
||||
#define CY_IP_MXPERI_VERSION 1u
|
||||
#define CY_IP_MXPERI_TR 1u
|
||||
#define CY_IP_MXPERI_TR_INSTANCES 1u
|
||||
#define CY_IP_MXPERI_TR_VERSION 1u
|
||||
#define CY_IP_M4CPUSS 1u
|
||||
#define CY_IP_M4CPUSS_INSTANCES 1u
|
||||
#define CY_IP_M4CPUSS_VERSION 1u
|
||||
#define CY_IP_M4CPUSS_DMA 1u
|
||||
#define CY_IP_M4CPUSS_DMA_INSTANCES 2u
|
||||
#define CY_IP_M4CPUSS_DMA_VERSION 1u
|
||||
#define CY_IP_MXAUDIOSS 1u
|
||||
#define CY_IP_MXAUDIOSS_INSTANCES 1u
|
||||
#define CY_IP_MXAUDIOSS_VERSION 1u
|
||||
#define CY_IP_MXLPCOMP 1u
|
||||
#define CY_IP_MXLPCOMP_INSTANCES 1u
|
||||
#define CY_IP_MXLPCOMP_VERSION 1u
|
||||
#define CY_IP_MXS40PASS 1u
|
||||
#define CY_IP_MXS40PASS_INSTANCES 1u
|
||||
#define CY_IP_MXS40PASS_VERSION 1u
|
||||
#define CY_IP_MXS40PASS_SAR 1u
|
||||
#define CY_IP_MXS40PASS_SAR_INSTANCES 16u
|
||||
#define CY_IP_MXS40PASS_SAR_VERSION 1u
|
||||
#define CY_IP_MXS40PASS_CTDAC 1u
|
||||
#define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u
|
||||
#define CY_IP_MXS40PASS_CTDAC_VERSION 1u
|
||||
#define CY_IP_MXSMIF 1u
|
||||
#define CY_IP_MXSMIF_INSTANCES 1u
|
||||
#define CY_IP_MXSMIF_VERSION 1u
|
||||
#define CY_IP_MXUSBFS 1u
|
||||
#define CY_IP_MXUSBFS_INSTANCES 1u
|
||||
#define CY_IP_MXUSBFS_VERSION 1u
|
||||
#define CY_IP_MXS40IOSS 1u
|
||||
#define CY_IP_MXS40IOSS_INSTANCES 1u
|
||||
#define CY_IP_MXS40IOSS_VERSION 1u
|
||||
#define CY_IP_MXEFUSE 1u
|
||||
#define CY_IP_MXEFUSE_INSTANCES 1u
|
||||
#define CY_IP_MXEFUSE_VERSION 1u
|
||||
#define CY_IP_MXPROFILE 1u
|
||||
#define CY_IP_MXPROFILE_INSTANCES 1u
|
||||
#define CY_IP_MXPROFILE_VERSION 1u
|
||||
|
||||
#include "psoc6able2_config.h"
|
||||
#include "gpio_psoc6able2_124_bga.h"
|
||||
|
||||
#define CY_DEVICE_PSOC6ABLE2
|
||||
#define CY_SILICON_ID 0xE2102100UL
|
||||
#define CY_HF_CLK_MAX_FREQ 150000000UL
|
||||
|
||||
#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL
|
||||
|
||||
/*******************************************************************************
|
||||
* SFLASH
|
||||
*******************************************************************************/
|
||||
|
||||
#define SFLASH_BASE 0x16000000UL
|
||||
#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* PERI
|
||||
*******************************************************************************/
|
||||
|
||||
#define PERI_BASE 0x40010000UL
|
||||
#define PERI_PPU_GR_MMIO0_BASE 0x40015000UL
|
||||
#define PERI_PPU_GR_MMIO1_BASE 0x40015040UL
|
||||
#define PERI_PPU_GR_MMIO2_BASE 0x40015080UL
|
||||
#define PERI_PPU_GR_MMIO3_BASE 0x400150C0UL
|
||||
#define PERI_PPU_GR_MMIO4_BASE 0x40015100UL
|
||||
#define PERI_PPU_GR_MMIO6_BASE 0x40015180UL
|
||||
#define PERI_PPU_GR_MMIO9_BASE 0x40015240UL
|
||||
#define PERI_PPU_GR_MMIO10_BASE 0x40015280UL
|
||||
#define PERI_GR_PPU_SL_PERI_GR1_BASE 0x40100000UL
|
||||
#define PERI_GR_PPU_SL_CRYPTO_BASE 0x40100040UL
|
||||
#define PERI_GR_PPU_SL_PERI_GR2_BASE 0x40200000UL
|
||||
#define PERI_GR_PPU_SL_CPUSS_BASE 0x40200040UL
|
||||
#define PERI_GR_PPU_SL_FAULT_BASE 0x40200080UL
|
||||
#define PERI_GR_PPU_SL_IPC_BASE 0x402000C0UL
|
||||
#define PERI_GR_PPU_SL_PROT_BASE 0x40200100UL
|
||||
#define PERI_GR_PPU_SL_FLASHC_BASE 0x40200140UL
|
||||
#define PERI_GR_PPU_SL_SRSS_BASE 0x40200180UL
|
||||
#define PERI_GR_PPU_SL_BACKUP_BASE 0x402001C0UL
|
||||
#define PERI_GR_PPU_SL_DW0_BASE 0x40200200UL
|
||||
#define PERI_GR_PPU_SL_DW1_BASE 0x40200240UL
|
||||
#define PERI_GR_PPU_SL_EFUSE_BASE 0x40200300UL
|
||||
#define PERI_GR_PPU_SL_PROFILE_BASE 0x40200340UL
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT0_BASE 0x40201000UL
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT1_BASE 0x40201040UL
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT2_BASE 0x40201080UL
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT3_BASE 0x402010C0UL
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT4_BASE 0x40201100UL
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT5_BASE 0x40201140UL
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT6_BASE 0x40201180UL
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT7_BASE 0x402011C0UL
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT0_BASE 0x40201200UL
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT1_BASE 0x40201240UL
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT2_BASE 0x40201280UL
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT3_BASE 0x402012C0UL
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT4_BASE 0x40201300UL
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT5_BASE 0x40201340UL
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT6_BASE 0x40201380UL
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT7_BASE 0x402013C0UL
|
||||
#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT0_BASE 0x40201400UL
|
||||
#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT1_BASE 0x40201440UL
|
||||
#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT2_BASE 0x40201480UL
|
||||
#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT3_BASE 0x402014C0UL
|
||||
#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT0_BASE 0x40201500UL
|
||||
#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT1_BASE 0x40201540UL
|
||||
#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT2_BASE 0x40201580UL
|
||||
#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT3_BASE 0x402015C0UL
|
||||
#define PERI_GR_PPU_RG_SMPU_BASE 0x40201600UL
|
||||
#define PERI_GR_PPU_RG_MPU_CM0P_BASE 0x40201640UL
|
||||
#define PERI_GR_PPU_RG_MPU_CRYPTO_BASE 0x40201680UL
|
||||
#define PERI_GR_PPU_RG_MPU_CM4_BASE 0x402016C0UL
|
||||
#define PERI_GR_PPU_RG_MPU_TC_BASE 0x40201700UL
|
||||
#define PERI_GR_PPU_SL_PERI_GR3_BASE 0x40300000UL
|
||||
#define PERI_GR_PPU_SL_HSIOM_BASE 0x40300040UL
|
||||
#define PERI_GR_PPU_SL_GPIO_BASE 0x40300080UL
|
||||
#define PERI_GR_PPU_SL_SMARTIO_BASE 0x403000C0UL
|
||||
#define PERI_GR_PPU_SL_UDB_BASE 0x40300100UL
|
||||
#define PERI_GR_PPU_SL_LPCOMP_BASE 0x40300140UL
|
||||
#define PERI_GR_PPU_SL_CSD_BASE 0x40300180UL
|
||||
#define PERI_GR_PPU_SL_TCPWM0_BASE 0x40300200UL
|
||||
#define PERI_GR_PPU_SL_TCPWM1_BASE 0x40300240UL
|
||||
#define PERI_GR_PPU_SL_LCD_BASE 0x40300280UL
|
||||
#define PERI_GR_PPU_SL_BLE_BASE 0x403002C0UL
|
||||
#define PERI_GR_PPU_SL_USBFS_BASE 0x40300300UL
|
||||
#define PERI_GR_PPU_SL_PERI_GR4_BASE 0x40400000UL
|
||||
#define PERI_GR_PPU_SL_SMIF_BASE 0x40400080UL
|
||||
#define PERI_GR_PPU_SL_PERI_GR6_BASE 0x40600000UL
|
||||
#define PERI_GR_PPU_SL_SCB0_BASE 0x40600040UL
|
||||
#define PERI_GR_PPU_SL_SCB1_BASE 0x40600080UL
|
||||
#define PERI_GR_PPU_SL_SCB2_BASE 0x406000C0UL
|
||||
#define PERI_GR_PPU_SL_SCB3_BASE 0x40600100UL
|
||||
#define PERI_GR_PPU_SL_SCB4_BASE 0x40600140UL
|
||||
#define PERI_GR_PPU_SL_SCB5_BASE 0x40600180UL
|
||||
#define PERI_GR_PPU_SL_SCB6_BASE 0x406001C0UL
|
||||
#define PERI_GR_PPU_SL_SCB7_BASE 0x40600200UL
|
||||
#define PERI_GR_PPU_SL_SCB8_BASE 0x40600240UL
|
||||
#define PERI_GR_PPU_SL_PERI_GR9_BASE 0x41000000UL
|
||||
#define PERI_GR_PPU_SL_PASS_BASE 0x41000040UL
|
||||
#define PERI_GR_PPU_SL_PERI_GR10_BASE 0x42A00000UL
|
||||
#define PERI_GR_PPU_SL_I2S_BASE 0x42A00040UL
|
||||
#define PERI_GR_PPU_SL_PDM_BASE 0x42A00080UL
|
||||
#define PERI ((PERI_Type*) PERI_BASE) /* 0x40010000 */
|
||||
#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40010000 */
|
||||
#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40010040 */
|
||||
#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40010080 */
|
||||
#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x400100C0 */
|
||||
#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40010100 */
|
||||
#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x40010180 */
|
||||
#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40010240 */
|
||||
#define PERI_GR10 ((PERI_GR_Type*) &PERI->GR[10]) /* 0x40010280 */
|
||||
#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40012000 */
|
||||
#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40012200 */
|
||||
#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40012400 */
|
||||
#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40012600 */
|
||||
#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40012800 */
|
||||
#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40012A00 */
|
||||
#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40012C00 */
|
||||
#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40012E00 */
|
||||
#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x40013000 */
|
||||
#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x40013200 */
|
||||
#define PERI_TR_GR10 ((PERI_TR_GR_Type*) &PERI->TR_GR[10]) /* 0x40013400 */
|
||||
#define PERI_TR_GR11 ((PERI_TR_GR_Type*) &PERI->TR_GR[11]) /* 0x40013600 */
|
||||
#define PERI_TR_GR12 ((PERI_TR_GR_Type*) &PERI->TR_GR[12]) /* 0x40013800 */
|
||||
#define PERI_TR_GR13 ((PERI_TR_GR_Type*) &PERI->TR_GR[13]) /* 0x40013A00 */
|
||||
#define PERI_TR_GR14 ((PERI_TR_GR_Type*) &PERI->TR_GR[14]) /* 0x40013C00 */
|
||||
#define PERI_PPU_PR0 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[0]) /* 0x40014000 */
|
||||
#define PERI_PPU_PR1 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[1]) /* 0x40014040 */
|
||||
#define PERI_PPU_PR2 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[2]) /* 0x40014080 */
|
||||
#define PERI_PPU_PR3 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[3]) /* 0x400140C0 */
|
||||
#define PERI_PPU_PR4 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[4]) /* 0x40014100 */
|
||||
#define PERI_PPU_PR5 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[5]) /* 0x40014140 */
|
||||
#define PERI_PPU_PR6 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[6]) /* 0x40014180 */
|
||||
#define PERI_PPU_PR7 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[7]) /* 0x400141C0 */
|
||||
#define PERI_PPU_PR8 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[8]) /* 0x40014200 */
|
||||
#define PERI_PPU_PR9 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[9]) /* 0x40014240 */
|
||||
#define PERI_PPU_PR10 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[10]) /* 0x40014280 */
|
||||
#define PERI_PPU_PR11 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[11]) /* 0x400142C0 */
|
||||
#define PERI_PPU_PR12 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[12]) /* 0x40014300 */
|
||||
#define PERI_PPU_PR13 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[13]) /* 0x40014340 */
|
||||
#define PERI_PPU_PR14 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[14]) /* 0x40014380 */
|
||||
#define PERI_PPU_PR15 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[15]) /* 0x400143C0 */
|
||||
#define PERI_PPU_GR0 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[0]) /* 0x40015000 */
|
||||
#define PERI_PPU_GR1 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[1]) /* 0x40015040 */
|
||||
#define PERI_PPU_GR2 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[2]) /* 0x40015080 */
|
||||
#define PERI_PPU_GR3 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[3]) /* 0x400150C0 */
|
||||
#define PERI_PPU_GR4 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[4]) /* 0x40015100 */
|
||||
#define PERI_PPU_GR6 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[6]) /* 0x40015180 */
|
||||
#define PERI_PPU_GR9 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[9]) /* 0x40015240 */
|
||||
#define PERI_PPU_GR10 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[10]) /* 0x40015280 */
|
||||
#define PERI_PPU_GR_MMIO0 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO0_BASE) /* 0x40015000 */
|
||||
#define PERI_PPU_GR_MMIO1 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO1_BASE) /* 0x40015040 */
|
||||
#define PERI_PPU_GR_MMIO2 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO2_BASE) /* 0x40015080 */
|
||||
#define PERI_PPU_GR_MMIO3 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO3_BASE) /* 0x400150C0 */
|
||||
#define PERI_PPU_GR_MMIO4 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO4_BASE) /* 0x40015100 */
|
||||
#define PERI_PPU_GR_MMIO6 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO6_BASE) /* 0x40015180 */
|
||||
#define PERI_PPU_GR_MMIO9 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO9_BASE) /* 0x40015240 */
|
||||
#define PERI_PPU_GR_MMIO10 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO10_BASE) /* 0x40015280 */
|
||||
#define PERI_GR_PPU_SL_PERI_GR1 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR1_BASE) /* 0x40100000 */
|
||||
#define PERI_GR_PPU_SL_CRYPTO ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_CRYPTO_BASE) /* 0x40100040 */
|
||||
#define PERI_GR_PPU_SL_PERI_GR2 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR2_BASE) /* 0x40200000 */
|
||||
#define PERI_GR_PPU_SL_CPUSS ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_CPUSS_BASE) /* 0x40200040 */
|
||||
#define PERI_GR_PPU_SL_FAULT ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_FAULT_BASE) /* 0x40200080 */
|
||||
#define PERI_GR_PPU_SL_IPC ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_IPC_BASE) /* 0x402000C0 */
|
||||
#define PERI_GR_PPU_SL_PROT ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PROT_BASE) /* 0x40200100 */
|
||||
#define PERI_GR_PPU_SL_FLASHC ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_FLASHC_BASE) /* 0x40200140 */
|
||||
#define PERI_GR_PPU_SL_SRSS ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SRSS_BASE) /* 0x40200180 */
|
||||
#define PERI_GR_PPU_SL_BACKUP ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_BACKUP_BASE) /* 0x402001C0 */
|
||||
#define PERI_GR_PPU_SL_DW0 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_DW0_BASE) /* 0x40200200 */
|
||||
#define PERI_GR_PPU_SL_DW1 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_DW1_BASE) /* 0x40200240 */
|
||||
#define PERI_GR_PPU_SL_EFUSE ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_EFUSE_BASE) /* 0x40200300 */
|
||||
#define PERI_GR_PPU_SL_PROFILE ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PROFILE_BASE) /* 0x40200340 */
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT0 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT0_BASE) /* 0x40201000 */
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT1 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT1_BASE) /* 0x40201040 */
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT2 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT2_BASE) /* 0x40201080 */
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT3 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT3_BASE) /* 0x402010C0 */
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT4 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT4_BASE) /* 0x40201100 */
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT5 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT5_BASE) /* 0x40201140 */
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT6 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT6_BASE) /* 0x40201180 */
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT7 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT7_BASE) /* 0x402011C0 */
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT0 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT0_BASE) /* 0x40201200 */
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT1 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT1_BASE) /* 0x40201240 */
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT2 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT2_BASE) /* 0x40201280 */
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT3 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT3_BASE) /* 0x402012C0 */
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT4 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT4_BASE) /* 0x40201300 */
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT5 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT5_BASE) /* 0x40201340 */
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT6 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT6_BASE) /* 0x40201380 */
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT7 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT7_BASE) /* 0x402013C0 */
|
||||
#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT0 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW0_DW_CH_STRUCT0_BASE) /* 0x40201400 */
|
||||
#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT1 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW0_DW_CH_STRUCT1_BASE) /* 0x40201440 */
|
||||
#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT2 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW0_DW_CH_STRUCT2_BASE) /* 0x40201480 */
|
||||
#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT3 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW0_DW_CH_STRUCT3_BASE) /* 0x402014C0 */
|
||||
#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT0 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW1_DW_CH_STRUCT0_BASE) /* 0x40201500 */
|
||||
#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT1 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW1_DW_CH_STRUCT1_BASE) /* 0x40201540 */
|
||||
#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT2 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW1_DW_CH_STRUCT2_BASE) /* 0x40201580 */
|
||||
#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT3 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW1_DW_CH_STRUCT3_BASE) /* 0x402015C0 */
|
||||
#define PERI_GR_PPU_RG_SMPU ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_SMPU_BASE) /* 0x40201600 */
|
||||
#define PERI_GR_PPU_RG_MPU_CM0P ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_MPU_CM0P_BASE) /* 0x40201640 */
|
||||
#define PERI_GR_PPU_RG_MPU_CRYPTO ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_MPU_CRYPTO_BASE) /* 0x40201680 */
|
||||
#define PERI_GR_PPU_RG_MPU_CM4 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_MPU_CM4_BASE) /* 0x402016C0 */
|
||||
#define PERI_GR_PPU_RG_MPU_TC ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_MPU_TC_BASE) /* 0x40201700 */
|
||||
#define PERI_GR_PPU_SL_PERI_GR3 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR3_BASE) /* 0x40300000 */
|
||||
#define PERI_GR_PPU_SL_HSIOM ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_HSIOM_BASE) /* 0x40300040 */
|
||||
#define PERI_GR_PPU_SL_GPIO ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_GPIO_BASE) /* 0x40300080 */
|
||||
#define PERI_GR_PPU_SL_SMARTIO ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SMARTIO_BASE) /* 0x403000C0 */
|
||||
#define PERI_GR_PPU_SL_UDB ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_UDB_BASE) /* 0x40300100 */
|
||||
#define PERI_GR_PPU_SL_LPCOMP ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_LPCOMP_BASE) /* 0x40300140 */
|
||||
#define PERI_GR_PPU_SL_CSD ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_CSD_BASE) /* 0x40300180 */
|
||||
#define PERI_GR_PPU_SL_TCPWM0 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_TCPWM0_BASE) /* 0x40300200 */
|
||||
#define PERI_GR_PPU_SL_TCPWM1 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_TCPWM1_BASE) /* 0x40300240 */
|
||||
#define PERI_GR_PPU_SL_LCD ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_LCD_BASE) /* 0x40300280 */
|
||||
#define PERI_GR_PPU_SL_BLE ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_BLE_BASE) /* 0x403002C0 */
|
||||
#define PERI_GR_PPU_SL_USBFS ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_USBFS_BASE) /* 0x40300300 */
|
||||
#define PERI_GR_PPU_SL_PERI_GR4 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR4_BASE) /* 0x40400000 */
|
||||
#define PERI_GR_PPU_SL_SMIF ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SMIF_BASE) /* 0x40400080 */
|
||||
#define PERI_GR_PPU_SL_PERI_GR6 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR6_BASE) /* 0x40600000 */
|
||||
#define PERI_GR_PPU_SL_SCB0 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB0_BASE) /* 0x40600040 */
|
||||
#define PERI_GR_PPU_SL_SCB1 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB1_BASE) /* 0x40600080 */
|
||||
#define PERI_GR_PPU_SL_SCB2 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB2_BASE) /* 0x406000C0 */
|
||||
#define PERI_GR_PPU_SL_SCB3 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB3_BASE) /* 0x40600100 */
|
||||
#define PERI_GR_PPU_SL_SCB4 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB4_BASE) /* 0x40600140 */
|
||||
#define PERI_GR_PPU_SL_SCB5 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB5_BASE) /* 0x40600180 */
|
||||
#define PERI_GR_PPU_SL_SCB6 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB6_BASE) /* 0x406001C0 */
|
||||
#define PERI_GR_PPU_SL_SCB7 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB7_BASE) /* 0x40600200 */
|
||||
#define PERI_GR_PPU_SL_SCB8 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB8_BASE) /* 0x40600240 */
|
||||
#define PERI_GR_PPU_SL_PERI_GR9 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR9_BASE) /* 0x41000000 */
|
||||
#define PERI_GR_PPU_SL_PASS ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PASS_BASE) /* 0x41000040 */
|
||||
#define PERI_GR_PPU_SL_PERI_GR10 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR10_BASE) /* 0x42A00000 */
|
||||
#define PERI_GR_PPU_SL_I2S ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_I2S_BASE) /* 0x42A00040 */
|
||||
#define PERI_GR_PPU_SL_PDM ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PDM_BASE) /* 0x42A00080 */
|
||||
|
||||
/*******************************************************************************
|
||||
* CPUSS
|
||||
*******************************************************************************/
|
||||
|
||||
#define CPUSS_BASE 0x40210000UL
|
||||
#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40210000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* FAULT
|
||||
*******************************************************************************/
|
||||
|
||||
#define FAULT_BASE 0x40220000UL
|
||||
#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40220000 */
|
||||
#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40220000 */
|
||||
#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40220100 */
|
||||
|
||||
/*******************************************************************************
|
||||
* IPC
|
||||
*******************************************************************************/
|
||||
|
||||
#define IPC_BASE 0x40230000UL
|
||||
#define IPC ((IPC_Type*) IPC_BASE) /* 0x40230000 */
|
||||
#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40230000 */
|
||||
#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40230020 */
|
||||
#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40230040 */
|
||||
#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40230060 */
|
||||
#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40230080 */
|
||||
#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402300A0 */
|
||||
#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402300C0 */
|
||||
#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402300E0 */
|
||||
#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40230100 */
|
||||
#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40230120 */
|
||||
#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40230140 */
|
||||
#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40230160 */
|
||||
#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40230180 */
|
||||
#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402301A0 */
|
||||
#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402301C0 */
|
||||
#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402301E0 */
|
||||
#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40231000 */
|
||||
#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40231020 */
|
||||
#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40231040 */
|
||||
#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40231060 */
|
||||
#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40231080 */
|
||||
#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402310A0 */
|
||||
#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402310C0 */
|
||||
#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402310E0 */
|
||||
#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40231100 */
|
||||
#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40231120 */
|
||||
#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40231140 */
|
||||
#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40231160 */
|
||||
#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40231180 */
|
||||
#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402311A0 */
|
||||
#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402311C0 */
|
||||
#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402311E0 */
|
||||
|
||||
/*******************************************************************************
|
||||
* PROT
|
||||
*******************************************************************************/
|
||||
|
||||
#define PROT_BASE 0x40240000UL
|
||||
#define PROT ((PROT_Type*) PROT_BASE) /* 0x40240000 */
|
||||
#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40242000 */
|
||||
#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40242040 */
|
||||
#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40242080 */
|
||||
#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402420C0 */
|
||||
#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40242100 */
|
||||
#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40242140 */
|
||||
#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40242180 */
|
||||
#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402421C0 */
|
||||
#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40242200 */
|
||||
#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40242240 */
|
||||
#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40242280 */
|
||||
#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402422C0 */
|
||||
#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40242300 */
|
||||
#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40242340 */
|
||||
#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40242380 */
|
||||
#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402423C0 */
|
||||
#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */
|
||||
#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */
|
||||
#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */
|
||||
#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */
|
||||
#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */
|
||||
#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */
|
||||
#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */
|
||||
#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */
|
||||
#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */
|
||||
#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */
|
||||
#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */
|
||||
#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */
|
||||
#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */
|
||||
#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */
|
||||
#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */
|
||||
#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */
|
||||
#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */
|
||||
#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40244000 */
|
||||
#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40244400 */
|
||||
#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40244800 */
|
||||
#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40244C00 */
|
||||
#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40245000 */
|
||||
#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40245400 */
|
||||
#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40245800 */
|
||||
#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40245C00 */
|
||||
#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40246000 */
|
||||
#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40246400 */
|
||||
#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40246800 */
|
||||
#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40246C00 */
|
||||
#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40247000 */
|
||||
#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40247400 */
|
||||
#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40247800 */
|
||||
#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40247C00 */
|
||||
|
||||
/*******************************************************************************
|
||||
* FLASHC
|
||||
*******************************************************************************/
|
||||
|
||||
#define FLASHC_BASE 0x40250000UL
|
||||
#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40250000 */
|
||||
#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4025F000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* SRSS
|
||||
*******************************************************************************/
|
||||
|
||||
#define SRSS_BASE 0x40260000UL
|
||||
#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */
|
||||
#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */
|
||||
#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */
|
||||
|
||||
/*******************************************************************************
|
||||
* BACKUP
|
||||
*******************************************************************************/
|
||||
|
||||
#define BACKUP_BASE 0x40270000UL
|
||||
#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* DW
|
||||
*******************************************************************************/
|
||||
|
||||
#define DW0_BASE 0x40280000UL
|
||||
#define DW1_BASE 0x40281000UL
|
||||
#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */
|
||||
#define DW1 ((DW_Type*) DW1_BASE) /* 0x40281000 */
|
||||
#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40280800 */
|
||||
#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40280820 */
|
||||
#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40280840 */
|
||||
#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x40280860 */
|
||||
#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40280880 */
|
||||
#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x402808A0 */
|
||||
#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x402808C0 */
|
||||
#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402808E0 */
|
||||
#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40280900 */
|
||||
#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40280920 */
|
||||
#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40280940 */
|
||||
#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x40280960 */
|
||||
#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40280980 */
|
||||
#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x402809A0 */
|
||||
#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x402809C0 */
|
||||
#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402809E0 */
|
||||
#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40281800 */
|
||||
#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40281820 */
|
||||
#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40281840 */
|
||||
#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x40281860 */
|
||||
#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40281880 */
|
||||
#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x402818A0 */
|
||||
#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x402818C0 */
|
||||
#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402818E0 */
|
||||
#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40281900 */
|
||||
#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40281920 */
|
||||
#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40281940 */
|
||||
#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x40281960 */
|
||||
#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40281980 */
|
||||
#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x402819A0 */
|
||||
#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x402819C0 */
|
||||
#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402819E0 */
|
||||
|
||||
/*******************************************************************************
|
||||
* EFUSE
|
||||
*******************************************************************************/
|
||||
|
||||
#define EFUSE_BASE 0x402C0000UL
|
||||
#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* PROFILE
|
||||
*******************************************************************************/
|
||||
|
||||
#define PROFILE_BASE 0x402D0000UL
|
||||
#define PROFILE ((PROFILE_Type*) PROFILE_BASE) /* 0x402D0000 */
|
||||
#define PROFILE_CNT_STRUCT0 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[0]) /* 0x402D0800 */
|
||||
#define PROFILE_CNT_STRUCT1 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[1]) /* 0x402D0810 */
|
||||
#define PROFILE_CNT_STRUCT2 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[2]) /* 0x402D0820 */
|
||||
#define PROFILE_CNT_STRUCT3 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[3]) /* 0x402D0830 */
|
||||
#define PROFILE_CNT_STRUCT4 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[4]) /* 0x402D0840 */
|
||||
#define PROFILE_CNT_STRUCT5 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[5]) /* 0x402D0850 */
|
||||
#define PROFILE_CNT_STRUCT6 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[6]) /* 0x402D0860 */
|
||||
#define PROFILE_CNT_STRUCT7 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[7]) /* 0x402D0870 */
|
||||
|
||||
/*******************************************************************************
|
||||
* HSIOM
|
||||
*******************************************************************************/
|
||||
|
||||
#define HSIOM_BASE 0x40310000UL
|
||||
#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40310000 */
|
||||
#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40310000 */
|
||||
#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40310010 */
|
||||
#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40310020 */
|
||||
#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40310030 */
|
||||
#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40310040 */
|
||||
#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40310050 */
|
||||
#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40310060 */
|
||||
#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40310070 */
|
||||
#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40310080 */
|
||||
#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40310090 */
|
||||
#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403100A0 */
|
||||
#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403100B0 */
|
||||
#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403100C0 */
|
||||
#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403100D0 */
|
||||
#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403100E0 */
|
||||
|
||||
/*******************************************************************************
|
||||
* GPIO
|
||||
*******************************************************************************/
|
||||
|
||||
#define GPIO_BASE 0x40320000UL
|
||||
#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40320000 */
|
||||
#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40320000 */
|
||||
#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40320080 */
|
||||
#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40320100 */
|
||||
#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40320180 */
|
||||
#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40320200 */
|
||||
#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40320280 */
|
||||
#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40320300 */
|
||||
#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40320380 */
|
||||
#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40320400 */
|
||||
#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40320480 */
|
||||
#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40320500 */
|
||||
#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40320580 */
|
||||
#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40320600 */
|
||||
#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40320680 */
|
||||
#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40320700 */
|
||||
|
||||
/*******************************************************************************
|
||||
* SMARTIO
|
||||
*******************************************************************************/
|
||||
|
||||
#define SMARTIO_BASE 0x40330000UL
|
||||
#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40330000 */
|
||||
#define SMARTIO_PRT8 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[8]) /* 0x40330800 */
|
||||
#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40330900 */
|
||||
|
||||
/*******************************************************************************
|
||||
* LPCOMP
|
||||
*******************************************************************************/
|
||||
|
||||
#define LPCOMP_BASE 0x40350000UL
|
||||
#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* CSD
|
||||
*******************************************************************************/
|
||||
|
||||
#define CSD0_BASE 0x40360000UL
|
||||
#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* TCPWM
|
||||
*******************************************************************************/
|
||||
|
||||
#define TCPWM0_BASE 0x40380000UL
|
||||
#define TCPWM1_BASE 0x40390000UL
|
||||
#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */
|
||||
#define TCPWM1 ((TCPWM_Type*) TCPWM1_BASE) /* 0x40390000 */
|
||||
#define TCPWM0_CNT0 ((TCPWM_CNT_Type*) &TCPWM0->CNT[0]) /* 0x40380100 */
|
||||
#define TCPWM0_CNT1 ((TCPWM_CNT_Type*) &TCPWM0->CNT[1]) /* 0x40380140 */
|
||||
#define TCPWM0_CNT2 ((TCPWM_CNT_Type*) &TCPWM0->CNT[2]) /* 0x40380180 */
|
||||
#define TCPWM0_CNT3 ((TCPWM_CNT_Type*) &TCPWM0->CNT[3]) /* 0x403801C0 */
|
||||
#define TCPWM0_CNT4 ((TCPWM_CNT_Type*) &TCPWM0->CNT[4]) /* 0x40380200 */
|
||||
#define TCPWM0_CNT5 ((TCPWM_CNT_Type*) &TCPWM0->CNT[5]) /* 0x40380240 */
|
||||
#define TCPWM0_CNT6 ((TCPWM_CNT_Type*) &TCPWM0->CNT[6]) /* 0x40380280 */
|
||||
#define TCPWM0_CNT7 ((TCPWM_CNT_Type*) &TCPWM0->CNT[7]) /* 0x403802C0 */
|
||||
#define TCPWM1_CNT0 ((TCPWM_CNT_Type*) &TCPWM1->CNT[0]) /* 0x40390100 */
|
||||
#define TCPWM1_CNT1 ((TCPWM_CNT_Type*) &TCPWM1->CNT[1]) /* 0x40390140 */
|
||||
#define TCPWM1_CNT2 ((TCPWM_CNT_Type*) &TCPWM1->CNT[2]) /* 0x40390180 */
|
||||
#define TCPWM1_CNT3 ((TCPWM_CNT_Type*) &TCPWM1->CNT[3]) /* 0x403901C0 */
|
||||
#define TCPWM1_CNT4 ((TCPWM_CNT_Type*) &TCPWM1->CNT[4]) /* 0x40390200 */
|
||||
#define TCPWM1_CNT5 ((TCPWM_CNT_Type*) &TCPWM1->CNT[5]) /* 0x40390240 */
|
||||
#define TCPWM1_CNT6 ((TCPWM_CNT_Type*) &TCPWM1->CNT[6]) /* 0x40390280 */
|
||||
#define TCPWM1_CNT7 ((TCPWM_CNT_Type*) &TCPWM1->CNT[7]) /* 0x403902C0 */
|
||||
#define TCPWM1_CNT8 ((TCPWM_CNT_Type*) &TCPWM1->CNT[8]) /* 0x40390300 */
|
||||
#define TCPWM1_CNT9 ((TCPWM_CNT_Type*) &TCPWM1->CNT[9]) /* 0x40390340 */
|
||||
#define TCPWM1_CNT10 ((TCPWM_CNT_Type*) &TCPWM1->CNT[10]) /* 0x40390380 */
|
||||
#define TCPWM1_CNT11 ((TCPWM_CNT_Type*) &TCPWM1->CNT[11]) /* 0x403903C0 */
|
||||
#define TCPWM1_CNT12 ((TCPWM_CNT_Type*) &TCPWM1->CNT[12]) /* 0x40390400 */
|
||||
#define TCPWM1_CNT13 ((TCPWM_CNT_Type*) &TCPWM1->CNT[13]) /* 0x40390440 */
|
||||
#define TCPWM1_CNT14 ((TCPWM_CNT_Type*) &TCPWM1->CNT[14]) /* 0x40390480 */
|
||||
#define TCPWM1_CNT15 ((TCPWM_CNT_Type*) &TCPWM1->CNT[15]) /* 0x403904C0 */
|
||||
#define TCPWM1_CNT16 ((TCPWM_CNT_Type*) &TCPWM1->CNT[16]) /* 0x40390500 */
|
||||
#define TCPWM1_CNT17 ((TCPWM_CNT_Type*) &TCPWM1->CNT[17]) /* 0x40390540 */
|
||||
#define TCPWM1_CNT18 ((TCPWM_CNT_Type*) &TCPWM1->CNT[18]) /* 0x40390580 */
|
||||
#define TCPWM1_CNT19 ((TCPWM_CNT_Type*) &TCPWM1->CNT[19]) /* 0x403905C0 */
|
||||
#define TCPWM1_CNT20 ((TCPWM_CNT_Type*) &TCPWM1->CNT[20]) /* 0x40390600 */
|
||||
#define TCPWM1_CNT21 ((TCPWM_CNT_Type*) &TCPWM1->CNT[21]) /* 0x40390640 */
|
||||
#define TCPWM1_CNT22 ((TCPWM_CNT_Type*) &TCPWM1->CNT[22]) /* 0x40390680 */
|
||||
#define TCPWM1_CNT23 ((TCPWM_CNT_Type*) &TCPWM1->CNT[23]) /* 0x403906C0 */
|
||||
|
||||
/*******************************************************************************
|
||||
* LCD
|
||||
*******************************************************************************/
|
||||
|
||||
#define LCD0_BASE 0x403B0000UL
|
||||
#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* USBFS
|
||||
*******************************************************************************/
|
||||
|
||||
#define USBFS0_BASE 0x403F0000UL
|
||||
#define USBFS0 ((USBFS_Type*) USBFS0_BASE) /* 0x403F0000 */
|
||||
#define USBFS0_USBDEV ((USBFS_USBDEV_Type*) &USBFS0->USBDEV) /* 0x403F0000 */
|
||||
#define USBFS0_USBLPM ((USBFS_USBLPM_Type*) &USBFS0->USBLPM) /* 0x403F2000 */
|
||||
#define USBFS0_USBHOST ((USBFS_USBHOST_Type*) &USBFS0->USBHOST) /* 0x403F4000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* SMIF
|
||||
*******************************************************************************/
|
||||
|
||||
#define SMIF0_BASE 0x40420000UL
|
||||
#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */
|
||||
#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */
|
||||
#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */
|
||||
#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */
|
||||
#define SMIF0_DEVICE3 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[3]) /* 0x40420980 */
|
||||
|
||||
/*******************************************************************************
|
||||
* SCB
|
||||
*******************************************************************************/
|
||||
|
||||
#define SCB0_BASE 0x40610000UL
|
||||
#define SCB1_BASE 0x40620000UL
|
||||
#define SCB2_BASE 0x40630000UL
|
||||
#define SCB3_BASE 0x40640000UL
|
||||
#define SCB4_BASE 0x40650000UL
|
||||
#define SCB5_BASE 0x40660000UL
|
||||
#define SCB6_BASE 0x40670000UL
|
||||
#define SCB7_BASE 0x40680000UL
|
||||
#define SCB8_BASE 0x40690000UL
|
||||
#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40610000 */
|
||||
#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40620000 */
|
||||
#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40630000 */
|
||||
#define SCB3 ((CySCB_Type*) SCB3_BASE) /* 0x40640000 */
|
||||
#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40650000 */
|
||||
#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40660000 */
|
||||
#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40670000 */
|
||||
#define SCB7 ((CySCB_Type*) SCB7_BASE) /* 0x40680000 */
|
||||
#define SCB8 ((CySCB_Type*) SCB8_BASE) /* 0x40690000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* CTDAC
|
||||
*******************************************************************************/
|
||||
|
||||
#define CTDAC0_BASE 0x41140000UL
|
||||
#define CTDAC0 ((CTDAC_Type*) CTDAC0_BASE) /* 0x41140000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* SAR
|
||||
*******************************************************************************/
|
||||
|
||||
#define SAR_BASE 0x411D0000UL
|
||||
#define SAR ((SAR_Type*) SAR_BASE) /* 0x411D0000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* PASS
|
||||
*******************************************************************************/
|
||||
|
||||
#define PASS_BASE 0x411F0000UL
|
||||
#define PASS ((PASS_Type*) PASS_BASE) /* 0x411F0000 */
|
||||
#define PASS_AREF ((PASS_AREF_Type*) &PASS->AREF) /* 0x411F0E00 */
|
||||
|
||||
/*******************************************************************************
|
||||
* I2S
|
||||
*******************************************************************************/
|
||||
|
||||
#define I2S0_BASE 0x42A10000UL
|
||||
#define I2S0 ((I2S_Type*) I2S0_BASE) /* 0x42A10000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* PDM
|
||||
*******************************************************************************/
|
||||
|
||||
#define PDM0_BASE 0x42A20000UL
|
||||
#define PDM0 ((PDM_Type*) PDM0_BASE) /* 0x42A20000 */
|
||||
|
||||
|
||||
/* Backward compabitility definitions */
|
||||
#define I2S I2S0
|
||||
#define PDM PDM0
|
||||
|
||||
/** \} CY8C6036BZI-F04 */
|
||||
|
||||
#endif /* _CY8C6036BZI_F04_H_ */
|
||||
|
||||
|
||||
/* [] END OF FILE */
|
||||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -1,933 +0,0 @@
|
|||
/***************************************************************************//**
|
||||
* \file cy8c6117fdi_f02.h
|
||||
*
|
||||
* \brief
|
||||
* CY8C6117FDI-F02 device header
|
||||
*
|
||||
* \note
|
||||
* Generator version: 1.3.0.1146
|
||||
* Database revision: rev#1050929
|
||||
*
|
||||
********************************************************************************
|
||||
* \copyright
|
||||
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
|
||||
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _CY8C6117FDI_F02_H_
|
||||
#define _CY8C6117FDI_F02_H_
|
||||
|
||||
/**
|
||||
* \addtogroup group_device CY8C6117FDI-F02
|
||||
* \{
|
||||
*/
|
||||
|
||||
/**
|
||||
* \addtogroup Configuration_of_CMSIS
|
||||
* \{
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Interrupt Number Definition
|
||||
*******************************************************************************/
|
||||
|
||||
typedef enum {
|
||||
/* ARM Cortex-M4 Core Interrupt Numbers */
|
||||
Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */
|
||||
NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */
|
||||
HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */
|
||||
MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */
|
||||
BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */
|
||||
UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
|
||||
SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */
|
||||
DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */
|
||||
PendSV_IRQn = -2, /*!< -2 Pendable request for system service */
|
||||
SysTick_IRQn = -1, /*!< -1 System Tick Timer */
|
||||
/* CY8C6117FDI-F02 Peripheral Interrupt Numbers */
|
||||
ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */
|
||||
ioss_interrupts_gpio_1_IRQn = 1, /*!< 1 [DeepSleep] GPIO Port Interrupt #1 */
|
||||
ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */
|
||||
ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */
|
||||
ioss_interrupts_gpio_4_IRQn = 4, /*!< 4 [DeepSleep] GPIO Port Interrupt #4 */
|
||||
ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */
|
||||
ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */
|
||||
ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */
|
||||
ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */
|
||||
ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */
|
||||
ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */
|
||||
ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */
|
||||
ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */
|
||||
ioss_interrupts_gpio_13_IRQn = 13, /*!< 13 [DeepSleep] GPIO Port Interrupt #13 */
|
||||
ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */
|
||||
ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */
|
||||
ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */
|
||||
lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */
|
||||
scb_8_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #8 (DeepSleep capable) */
|
||||
srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */
|
||||
srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */
|
||||
srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */
|
||||
srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */
|
||||
pass_interrupt_ctbs_IRQn = 23, /*!< 23 [DeepSleep] CTBm Interrupt (all CTBms) */
|
||||
bless_interrupt_IRQn = 24, /*!< 24 [DeepSleep] Bluetooth Radio interrupt */
|
||||
cpuss_interrupts_ipc_0_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */
|
||||
cpuss_interrupts_ipc_1_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */
|
||||
cpuss_interrupts_ipc_2_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */
|
||||
cpuss_interrupts_ipc_3_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */
|
||||
cpuss_interrupts_ipc_4_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */
|
||||
cpuss_interrupts_ipc_5_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */
|
||||
cpuss_interrupts_ipc_6_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */
|
||||
cpuss_interrupts_ipc_7_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */
|
||||
cpuss_interrupts_ipc_8_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */
|
||||
cpuss_interrupts_ipc_9_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */
|
||||
cpuss_interrupts_ipc_10_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */
|
||||
cpuss_interrupts_ipc_11_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */
|
||||
cpuss_interrupts_ipc_12_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */
|
||||
cpuss_interrupts_ipc_13_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */
|
||||
cpuss_interrupts_ipc_14_IRQn = 39, /*!< 39 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */
|
||||
cpuss_interrupts_ipc_15_IRQn = 40, /*!< 40 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */
|
||||
scb_0_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #0 */
|
||||
scb_1_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #1 */
|
||||
scb_2_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #2 */
|
||||
scb_3_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #3 */
|
||||
scb_4_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #4 */
|
||||
scb_5_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #5 */
|
||||
scb_6_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #6 */
|
||||
scb_7_interrupt_IRQn = 48, /*!< 48 [Active] Serial Communication Block #7 */
|
||||
csd_interrupt_IRQn = 49, /*!< 49 [Active] CSD (Capsense) interrupt */
|
||||
cpuss_interrupts_dw0_0_IRQn = 50, /*!< 50 [Active] CPUSS DataWire #0, Channel #0 */
|
||||
cpuss_interrupts_dw0_1_IRQn = 51, /*!< 51 [Active] CPUSS DataWire #0, Channel #1 */
|
||||
cpuss_interrupts_dw0_2_IRQn = 52, /*!< 52 [Active] CPUSS DataWire #0, Channel #2 */
|
||||
cpuss_interrupts_dw0_3_IRQn = 53, /*!< 53 [Active] CPUSS DataWire #0, Channel #3 */
|
||||
cpuss_interrupts_dw0_4_IRQn = 54, /*!< 54 [Active] CPUSS DataWire #0, Channel #4 */
|
||||
cpuss_interrupts_dw0_5_IRQn = 55, /*!< 55 [Active] CPUSS DataWire #0, Channel #5 */
|
||||
cpuss_interrupts_dw0_6_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #6 */
|
||||
cpuss_interrupts_dw0_7_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #7 */
|
||||
cpuss_interrupts_dw0_8_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #8 */
|
||||
cpuss_interrupts_dw0_9_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #9 */
|
||||
cpuss_interrupts_dw0_10_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #10 */
|
||||
cpuss_interrupts_dw0_11_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #11 */
|
||||
cpuss_interrupts_dw0_12_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #12 */
|
||||
cpuss_interrupts_dw0_13_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #13 */
|
||||
cpuss_interrupts_dw0_14_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #14 */
|
||||
cpuss_interrupts_dw0_15_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #15 */
|
||||
cpuss_interrupts_dw1_0_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #1, Channel #0 */
|
||||
cpuss_interrupts_dw1_1_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #1, Channel #1 */
|
||||
cpuss_interrupts_dw1_2_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #1, Channel #2 */
|
||||
cpuss_interrupts_dw1_3_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #1, Channel #3 */
|
||||
cpuss_interrupts_dw1_4_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #1, Channel #4 */
|
||||
cpuss_interrupts_dw1_5_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #1, Channel #5 */
|
||||
cpuss_interrupts_dw1_6_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #1, Channel #6 */
|
||||
cpuss_interrupts_dw1_7_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #1, Channel #7 */
|
||||
cpuss_interrupts_dw1_8_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #1, Channel #8 */
|
||||
cpuss_interrupts_dw1_9_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #1, Channel #9 */
|
||||
cpuss_interrupts_dw1_10_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #1, Channel #10 */
|
||||
cpuss_interrupts_dw1_11_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #1, Channel #11 */
|
||||
cpuss_interrupts_dw1_12_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #1, Channel #12 */
|
||||
cpuss_interrupts_dw1_13_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #1, Channel #13 */
|
||||
cpuss_interrupts_dw1_14_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #1, Channel #14 */
|
||||
cpuss_interrupts_dw1_15_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #1, Channel #15 */
|
||||
cpuss_interrupts_fault_0_IRQn = 82, /*!< 82 [Active] CPUSS Fault Structure Interrupt #0 */
|
||||
cpuss_interrupts_fault_1_IRQn = 83, /*!< 83 [Active] CPUSS Fault Structure Interrupt #1 */
|
||||
cpuss_interrupt_crypto_IRQn = 84, /*!< 84 [Active] CRYPTO Accelerator Interrupt */
|
||||
cpuss_interrupt_fm_IRQn = 85, /*!< 85 [Active] FLASH Macro Interrupt */
|
||||
cpuss_interrupts_cm0_cti_0_IRQn = 86, /*!< 86 [Active] CM0+ CTI #0 */
|
||||
cpuss_interrupts_cm0_cti_1_IRQn = 87, /*!< 87 [Active] CM0+ CTI #1 */
|
||||
cpuss_interrupts_cm4_cti_0_IRQn = 88, /*!< 88 [Active] CM4 CTI #0 */
|
||||
cpuss_interrupts_cm4_cti_1_IRQn = 89, /*!< 89 [Active] CM4 CTI #1 */
|
||||
tcpwm_0_interrupts_0_IRQn = 90, /*!< 90 [Active] TCPWM #0, Counter #0 */
|
||||
tcpwm_0_interrupts_1_IRQn = 91, /*!< 91 [Active] TCPWM #0, Counter #1 */
|
||||
tcpwm_0_interrupts_2_IRQn = 92, /*!< 92 [Active] TCPWM #0, Counter #2 */
|
||||
tcpwm_0_interrupts_3_IRQn = 93, /*!< 93 [Active] TCPWM #0, Counter #3 */
|
||||
tcpwm_0_interrupts_4_IRQn = 94, /*!< 94 [Active] TCPWM #0, Counter #4 */
|
||||
tcpwm_0_interrupts_5_IRQn = 95, /*!< 95 [Active] TCPWM #0, Counter #5 */
|
||||
tcpwm_0_interrupts_6_IRQn = 96, /*!< 96 [Active] TCPWM #0, Counter #6 */
|
||||
tcpwm_0_interrupts_7_IRQn = 97, /*!< 97 [Active] TCPWM #0, Counter #7 */
|
||||
tcpwm_1_interrupts_0_IRQn = 98, /*!< 98 [Active] TCPWM #1, Counter #0 */
|
||||
tcpwm_1_interrupts_1_IRQn = 99, /*!< 99 [Active] TCPWM #1, Counter #1 */
|
||||
tcpwm_1_interrupts_2_IRQn = 100, /*!< 100 [Active] TCPWM #1, Counter #2 */
|
||||
tcpwm_1_interrupts_3_IRQn = 101, /*!< 101 [Active] TCPWM #1, Counter #3 */
|
||||
tcpwm_1_interrupts_4_IRQn = 102, /*!< 102 [Active] TCPWM #1, Counter #4 */
|
||||
tcpwm_1_interrupts_5_IRQn = 103, /*!< 103 [Active] TCPWM #1, Counter #5 */
|
||||
tcpwm_1_interrupts_6_IRQn = 104, /*!< 104 [Active] TCPWM #1, Counter #6 */
|
||||
tcpwm_1_interrupts_7_IRQn = 105, /*!< 105 [Active] TCPWM #1, Counter #7 */
|
||||
tcpwm_1_interrupts_8_IRQn = 106, /*!< 106 [Active] TCPWM #1, Counter #8 */
|
||||
tcpwm_1_interrupts_9_IRQn = 107, /*!< 107 [Active] TCPWM #1, Counter #9 */
|
||||
tcpwm_1_interrupts_10_IRQn = 108, /*!< 108 [Active] TCPWM #1, Counter #10 */
|
||||
tcpwm_1_interrupts_11_IRQn = 109, /*!< 109 [Active] TCPWM #1, Counter #11 */
|
||||
tcpwm_1_interrupts_12_IRQn = 110, /*!< 110 [Active] TCPWM #1, Counter #12 */
|
||||
tcpwm_1_interrupts_13_IRQn = 111, /*!< 111 [Active] TCPWM #1, Counter #13 */
|
||||
tcpwm_1_interrupts_14_IRQn = 112, /*!< 112 [Active] TCPWM #1, Counter #14 */
|
||||
tcpwm_1_interrupts_15_IRQn = 113, /*!< 113 [Active] TCPWM #1, Counter #15 */
|
||||
tcpwm_1_interrupts_16_IRQn = 114, /*!< 114 [Active] TCPWM #1, Counter #16 */
|
||||
tcpwm_1_interrupts_17_IRQn = 115, /*!< 115 [Active] TCPWM #1, Counter #17 */
|
||||
tcpwm_1_interrupts_18_IRQn = 116, /*!< 116 [Active] TCPWM #1, Counter #18 */
|
||||
tcpwm_1_interrupts_19_IRQn = 117, /*!< 117 [Active] TCPWM #1, Counter #19 */
|
||||
tcpwm_1_interrupts_20_IRQn = 118, /*!< 118 [Active] TCPWM #1, Counter #20 */
|
||||
tcpwm_1_interrupts_21_IRQn = 119, /*!< 119 [Active] TCPWM #1, Counter #21 */
|
||||
tcpwm_1_interrupts_22_IRQn = 120, /*!< 120 [Active] TCPWM #1, Counter #22 */
|
||||
tcpwm_1_interrupts_23_IRQn = 121, /*!< 121 [Active] TCPWM #1, Counter #23 */
|
||||
udb_interrupts_0_IRQn = 122, /*!< 122 [Active] UDB Interrupt #0 */
|
||||
udb_interrupts_1_IRQn = 123, /*!< 123 [Active] UDB Interrupt #1 */
|
||||
udb_interrupts_2_IRQn = 124, /*!< 124 [Active] UDB Interrupt #2 */
|
||||
udb_interrupts_3_IRQn = 125, /*!< 125 [Active] UDB Interrupt #3 */
|
||||
udb_interrupts_4_IRQn = 126, /*!< 126 [Active] UDB Interrupt #4 */
|
||||
udb_interrupts_5_IRQn = 127, /*!< 127 [Active] UDB Interrupt #5 */
|
||||
udb_interrupts_6_IRQn = 128, /*!< 128 [Active] UDB Interrupt #6 */
|
||||
udb_interrupts_7_IRQn = 129, /*!< 129 [Active] UDB Interrupt #7 */
|
||||
udb_interrupts_8_IRQn = 130, /*!< 130 [Active] UDB Interrupt #8 */
|
||||
udb_interrupts_9_IRQn = 131, /*!< 131 [Active] UDB Interrupt #9 */
|
||||
udb_interrupts_10_IRQn = 132, /*!< 132 [Active] UDB Interrupt #10 */
|
||||
udb_interrupts_11_IRQn = 133, /*!< 133 [Active] UDB Interrupt #11 */
|
||||
udb_interrupts_12_IRQn = 134, /*!< 134 [Active] UDB Interrupt #12 */
|
||||
udb_interrupts_13_IRQn = 135, /*!< 135 [Active] UDB Interrupt #13 */
|
||||
udb_interrupts_14_IRQn = 136, /*!< 136 [Active] UDB Interrupt #14 */
|
||||
udb_interrupts_15_IRQn = 137, /*!< 137 [Active] UDB Interrupt #15 */
|
||||
pass_interrupt_sar_IRQn = 138, /*!< 138 [Active] SAR ADC interrupt */
|
||||
audioss_interrupt_i2s_IRQn = 139, /*!< 139 [Active] I2S Audio interrupt */
|
||||
audioss_interrupt_pdm_IRQn = 140, /*!< 140 [Active] PDM/PCM Audio interrupt */
|
||||
profile_interrupt_IRQn = 141, /*!< 141 [Active] Energy Profiler interrupt */
|
||||
smif_interrupt_IRQn = 142, /*!< 142 [Active] Serial Memory Interface interrupt */
|
||||
usb_interrupt_hi_IRQn = 143, /*!< 143 [Active] USB Interrupt */
|
||||
usb_interrupt_med_IRQn = 144, /*!< 144 [Active] USB Interrupt */
|
||||
usb_interrupt_lo_IRQn = 145, /*!< 145 [Active] USB Interrupt */
|
||||
pass_interrupt_dacs_IRQn = 146, /*!< 146 [Active] Consolidated interrrupt for all DACs */
|
||||
unconnected_IRQn = 240 /*!< 240 Unconnected */
|
||||
} IRQn_Type;
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Processor and Core Peripheral Section
|
||||
*******************************************************************************/
|
||||
|
||||
/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */
|
||||
#define __CM4_REV 0x0001U /*!< CM4 Core Revision */
|
||||
#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
|
||||
#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */
|
||||
#define __MPU_PRESENT 1 /*!< MPU present or not */
|
||||
#define __FPU_PRESENT 1 /*!< FPU present or not */
|
||||
#define __CM0P_PRESENT 0 /*!< CM0P present or not */
|
||||
|
||||
/** \} Configuration_of_CMSIS */
|
||||
|
||||
/* Memory Blocks */
|
||||
#define CY_ROM_BASE 0x00000000UL
|
||||
#define CY_ROM_SIZE 0x00020000UL
|
||||
#define CY_SRAM0_BASE 0x08000000UL
|
||||
#define CY_SRAM0_SIZE 0x00048000UL
|
||||
#define CY_FLASH_BASE 0x10000000UL
|
||||
#define CY_FLASH_SIZE 0x00100000UL
|
||||
#define CY_EM_EEPROM_BASE 0x14000000UL
|
||||
#define CY_EM_EEPROM_SIZE 0x00008000UL
|
||||
#define CY_XIP_BASE 0x18000000UL
|
||||
#define CY_XIP_SIZE 0x08000000UL
|
||||
#define CY_SFLASH_BASE 0x16000000UL
|
||||
#define CY_SFLASH_SIZE 0x00008000UL
|
||||
#define CY_EFUSE_BASE 0x402C0800UL
|
||||
#define CY_EFUSE_SIZE 0x00000200UL
|
||||
|
||||
#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */
|
||||
#include "system_psoc6.h" /*!< PSoC 6 System */
|
||||
|
||||
/* IP List */
|
||||
#define CY_IP_MXTCPWM 1u
|
||||
#define CY_IP_MXTCPWM_INSTANCES 2u
|
||||
#define CY_IP_MXTCPWM_VERSION 1u
|
||||
#define CY_IP_MXCSDV2 1u
|
||||
#define CY_IP_MXCSDV2_INSTANCES 1u
|
||||
#define CY_IP_MXCSDV2_VERSION 1u
|
||||
#define CY_IP_MXLCD 1u
|
||||
#define CY_IP_MXLCD_INSTANCES 1u
|
||||
#define CY_IP_MXLCD_VERSION 1u
|
||||
#define CY_IP_MXS40SRSS 1u
|
||||
#define CY_IP_MXS40SRSS_INSTANCES 1u
|
||||
#define CY_IP_MXS40SRSS_VERSION 1u
|
||||
#define CY_IP_MXS40SRSS_RTC 1u
|
||||
#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u
|
||||
#define CY_IP_MXS40SRSS_RTC_VERSION 1u
|
||||
#define CY_IP_MXS40SRSS_MCWDT 1u
|
||||
#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u
|
||||
#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u
|
||||
#define CY_IP_MXSCB 1u
|
||||
#define CY_IP_MXSCB_INSTANCES 9u
|
||||
#define CY_IP_MXSCB_VERSION 1u
|
||||
#define CY_IP_MXPERI 1u
|
||||
#define CY_IP_MXPERI_INSTANCES 1u
|
||||
#define CY_IP_MXPERI_VERSION 1u
|
||||
#define CY_IP_MXPERI_TR 1u
|
||||
#define CY_IP_MXPERI_TR_INSTANCES 1u
|
||||
#define CY_IP_MXPERI_TR_VERSION 1u
|
||||
#define CY_IP_M4CPUSS 1u
|
||||
#define CY_IP_M4CPUSS_INSTANCES 1u
|
||||
#define CY_IP_M4CPUSS_VERSION 1u
|
||||
#define CY_IP_M4CPUSS_DMA 1u
|
||||
#define CY_IP_M4CPUSS_DMA_INSTANCES 2u
|
||||
#define CY_IP_M4CPUSS_DMA_VERSION 1u
|
||||
#define CY_IP_MXAUDIOSS 1u
|
||||
#define CY_IP_MXAUDIOSS_INSTANCES 1u
|
||||
#define CY_IP_MXAUDIOSS_VERSION 1u
|
||||
#define CY_IP_MXLPCOMP 1u
|
||||
#define CY_IP_MXLPCOMP_INSTANCES 1u
|
||||
#define CY_IP_MXLPCOMP_VERSION 1u
|
||||
#define CY_IP_MXS40PASS 1u
|
||||
#define CY_IP_MXS40PASS_INSTANCES 1u
|
||||
#define CY_IP_MXS40PASS_VERSION 1u
|
||||
#define CY_IP_MXS40PASS_SAR 1u
|
||||
#define CY_IP_MXS40PASS_SAR_INSTANCES 16u
|
||||
#define CY_IP_MXS40PASS_SAR_VERSION 1u
|
||||
#define CY_IP_MXS40PASS_CTDAC 1u
|
||||
#define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u
|
||||
#define CY_IP_MXS40PASS_CTDAC_VERSION 1u
|
||||
#define CY_IP_MXSMIF 1u
|
||||
#define CY_IP_MXSMIF_INSTANCES 1u
|
||||
#define CY_IP_MXSMIF_VERSION 1u
|
||||
#define CY_IP_MXUSBFS 1u
|
||||
#define CY_IP_MXUSBFS_INSTANCES 1u
|
||||
#define CY_IP_MXUSBFS_VERSION 1u
|
||||
#define CY_IP_MXS40IOSS 1u
|
||||
#define CY_IP_MXS40IOSS_INSTANCES 1u
|
||||
#define CY_IP_MXS40IOSS_VERSION 1u
|
||||
#define CY_IP_MXEFUSE 1u
|
||||
#define CY_IP_MXEFUSE_INSTANCES 1u
|
||||
#define CY_IP_MXEFUSE_VERSION 1u
|
||||
#define CY_IP_MXPROFILE 1u
|
||||
#define CY_IP_MXPROFILE_INSTANCES 1u
|
||||
#define CY_IP_MXPROFILE_VERSION 1u
|
||||
|
||||
#include "psoc6able2_config.h"
|
||||
#include "gpio_psoc6able2_80_wlcsp.h"
|
||||
|
||||
#define CY_DEVICE_PSOC6ABLE2
|
||||
#define CY_SILICON_ID 0xE2312100UL
|
||||
#define CY_HF_CLK_MAX_FREQ 50000000UL
|
||||
|
||||
#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL
|
||||
|
||||
/*******************************************************************************
|
||||
* SFLASH
|
||||
*******************************************************************************/
|
||||
|
||||
#define SFLASH_BASE 0x16000000UL
|
||||
#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* PERI
|
||||
*******************************************************************************/
|
||||
|
||||
#define PERI_BASE 0x40010000UL
|
||||
#define PERI_PPU_GR_MMIO0_BASE 0x40015000UL
|
||||
#define PERI_PPU_GR_MMIO1_BASE 0x40015040UL
|
||||
#define PERI_PPU_GR_MMIO2_BASE 0x40015080UL
|
||||
#define PERI_PPU_GR_MMIO3_BASE 0x400150C0UL
|
||||
#define PERI_PPU_GR_MMIO4_BASE 0x40015100UL
|
||||
#define PERI_PPU_GR_MMIO6_BASE 0x40015180UL
|
||||
#define PERI_PPU_GR_MMIO9_BASE 0x40015240UL
|
||||
#define PERI_PPU_GR_MMIO10_BASE 0x40015280UL
|
||||
#define PERI_GR_PPU_SL_PERI_GR1_BASE 0x40100000UL
|
||||
#define PERI_GR_PPU_SL_CRYPTO_BASE 0x40100040UL
|
||||
#define PERI_GR_PPU_SL_PERI_GR2_BASE 0x40200000UL
|
||||
#define PERI_GR_PPU_SL_CPUSS_BASE 0x40200040UL
|
||||
#define PERI_GR_PPU_SL_FAULT_BASE 0x40200080UL
|
||||
#define PERI_GR_PPU_SL_IPC_BASE 0x402000C0UL
|
||||
#define PERI_GR_PPU_SL_PROT_BASE 0x40200100UL
|
||||
#define PERI_GR_PPU_SL_FLASHC_BASE 0x40200140UL
|
||||
#define PERI_GR_PPU_SL_SRSS_BASE 0x40200180UL
|
||||
#define PERI_GR_PPU_SL_BACKUP_BASE 0x402001C0UL
|
||||
#define PERI_GR_PPU_SL_DW0_BASE 0x40200200UL
|
||||
#define PERI_GR_PPU_SL_DW1_BASE 0x40200240UL
|
||||
#define PERI_GR_PPU_SL_EFUSE_BASE 0x40200300UL
|
||||
#define PERI_GR_PPU_SL_PROFILE_BASE 0x40200340UL
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT0_BASE 0x40201000UL
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT1_BASE 0x40201040UL
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT2_BASE 0x40201080UL
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT3_BASE 0x402010C0UL
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT4_BASE 0x40201100UL
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT5_BASE 0x40201140UL
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT6_BASE 0x40201180UL
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT7_BASE 0x402011C0UL
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT0_BASE 0x40201200UL
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT1_BASE 0x40201240UL
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT2_BASE 0x40201280UL
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT3_BASE 0x402012C0UL
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT4_BASE 0x40201300UL
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT5_BASE 0x40201340UL
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT6_BASE 0x40201380UL
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT7_BASE 0x402013C0UL
|
||||
#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT0_BASE 0x40201400UL
|
||||
#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT1_BASE 0x40201440UL
|
||||
#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT2_BASE 0x40201480UL
|
||||
#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT3_BASE 0x402014C0UL
|
||||
#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT0_BASE 0x40201500UL
|
||||
#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT1_BASE 0x40201540UL
|
||||
#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT2_BASE 0x40201580UL
|
||||
#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT3_BASE 0x402015C0UL
|
||||
#define PERI_GR_PPU_RG_SMPU_BASE 0x40201600UL
|
||||
#define PERI_GR_PPU_RG_MPU_CM0P_BASE 0x40201640UL
|
||||
#define PERI_GR_PPU_RG_MPU_CRYPTO_BASE 0x40201680UL
|
||||
#define PERI_GR_PPU_RG_MPU_CM4_BASE 0x402016C0UL
|
||||
#define PERI_GR_PPU_RG_MPU_TC_BASE 0x40201700UL
|
||||
#define PERI_GR_PPU_SL_PERI_GR3_BASE 0x40300000UL
|
||||
#define PERI_GR_PPU_SL_HSIOM_BASE 0x40300040UL
|
||||
#define PERI_GR_PPU_SL_GPIO_BASE 0x40300080UL
|
||||
#define PERI_GR_PPU_SL_SMARTIO_BASE 0x403000C0UL
|
||||
#define PERI_GR_PPU_SL_UDB_BASE 0x40300100UL
|
||||
#define PERI_GR_PPU_SL_LPCOMP_BASE 0x40300140UL
|
||||
#define PERI_GR_PPU_SL_CSD_BASE 0x40300180UL
|
||||
#define PERI_GR_PPU_SL_TCPWM0_BASE 0x40300200UL
|
||||
#define PERI_GR_PPU_SL_TCPWM1_BASE 0x40300240UL
|
||||
#define PERI_GR_PPU_SL_LCD_BASE 0x40300280UL
|
||||
#define PERI_GR_PPU_SL_BLE_BASE 0x403002C0UL
|
||||
#define PERI_GR_PPU_SL_USBFS_BASE 0x40300300UL
|
||||
#define PERI_GR_PPU_SL_PERI_GR4_BASE 0x40400000UL
|
||||
#define PERI_GR_PPU_SL_SMIF_BASE 0x40400080UL
|
||||
#define PERI_GR_PPU_SL_PERI_GR6_BASE 0x40600000UL
|
||||
#define PERI_GR_PPU_SL_SCB0_BASE 0x40600040UL
|
||||
#define PERI_GR_PPU_SL_SCB1_BASE 0x40600080UL
|
||||
#define PERI_GR_PPU_SL_SCB2_BASE 0x406000C0UL
|
||||
#define PERI_GR_PPU_SL_SCB3_BASE 0x40600100UL
|
||||
#define PERI_GR_PPU_SL_SCB4_BASE 0x40600140UL
|
||||
#define PERI_GR_PPU_SL_SCB5_BASE 0x40600180UL
|
||||
#define PERI_GR_PPU_SL_SCB6_BASE 0x406001C0UL
|
||||
#define PERI_GR_PPU_SL_SCB7_BASE 0x40600200UL
|
||||
#define PERI_GR_PPU_SL_SCB8_BASE 0x40600240UL
|
||||
#define PERI_GR_PPU_SL_PERI_GR9_BASE 0x41000000UL
|
||||
#define PERI_GR_PPU_SL_PASS_BASE 0x41000040UL
|
||||
#define PERI_GR_PPU_SL_PERI_GR10_BASE 0x42A00000UL
|
||||
#define PERI_GR_PPU_SL_I2S_BASE 0x42A00040UL
|
||||
#define PERI_GR_PPU_SL_PDM_BASE 0x42A00080UL
|
||||
#define PERI ((PERI_Type*) PERI_BASE) /* 0x40010000 */
|
||||
#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40010000 */
|
||||
#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40010040 */
|
||||
#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40010080 */
|
||||
#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x400100C0 */
|
||||
#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40010100 */
|
||||
#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x40010180 */
|
||||
#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40010240 */
|
||||
#define PERI_GR10 ((PERI_GR_Type*) &PERI->GR[10]) /* 0x40010280 */
|
||||
#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40012000 */
|
||||
#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40012200 */
|
||||
#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40012400 */
|
||||
#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40012600 */
|
||||
#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40012800 */
|
||||
#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40012A00 */
|
||||
#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40012C00 */
|
||||
#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40012E00 */
|
||||
#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x40013000 */
|
||||
#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x40013200 */
|
||||
#define PERI_TR_GR10 ((PERI_TR_GR_Type*) &PERI->TR_GR[10]) /* 0x40013400 */
|
||||
#define PERI_TR_GR11 ((PERI_TR_GR_Type*) &PERI->TR_GR[11]) /* 0x40013600 */
|
||||
#define PERI_TR_GR12 ((PERI_TR_GR_Type*) &PERI->TR_GR[12]) /* 0x40013800 */
|
||||
#define PERI_TR_GR13 ((PERI_TR_GR_Type*) &PERI->TR_GR[13]) /* 0x40013A00 */
|
||||
#define PERI_TR_GR14 ((PERI_TR_GR_Type*) &PERI->TR_GR[14]) /* 0x40013C00 */
|
||||
#define PERI_PPU_PR0 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[0]) /* 0x40014000 */
|
||||
#define PERI_PPU_PR1 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[1]) /* 0x40014040 */
|
||||
#define PERI_PPU_PR2 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[2]) /* 0x40014080 */
|
||||
#define PERI_PPU_PR3 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[3]) /* 0x400140C0 */
|
||||
#define PERI_PPU_PR4 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[4]) /* 0x40014100 */
|
||||
#define PERI_PPU_PR5 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[5]) /* 0x40014140 */
|
||||
#define PERI_PPU_PR6 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[6]) /* 0x40014180 */
|
||||
#define PERI_PPU_PR7 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[7]) /* 0x400141C0 */
|
||||
#define PERI_PPU_PR8 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[8]) /* 0x40014200 */
|
||||
#define PERI_PPU_PR9 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[9]) /* 0x40014240 */
|
||||
#define PERI_PPU_PR10 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[10]) /* 0x40014280 */
|
||||
#define PERI_PPU_PR11 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[11]) /* 0x400142C0 */
|
||||
#define PERI_PPU_PR12 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[12]) /* 0x40014300 */
|
||||
#define PERI_PPU_PR13 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[13]) /* 0x40014340 */
|
||||
#define PERI_PPU_PR14 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[14]) /* 0x40014380 */
|
||||
#define PERI_PPU_PR15 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[15]) /* 0x400143C0 */
|
||||
#define PERI_PPU_GR0 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[0]) /* 0x40015000 */
|
||||
#define PERI_PPU_GR1 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[1]) /* 0x40015040 */
|
||||
#define PERI_PPU_GR2 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[2]) /* 0x40015080 */
|
||||
#define PERI_PPU_GR3 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[3]) /* 0x400150C0 */
|
||||
#define PERI_PPU_GR4 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[4]) /* 0x40015100 */
|
||||
#define PERI_PPU_GR6 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[6]) /* 0x40015180 */
|
||||
#define PERI_PPU_GR9 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[9]) /* 0x40015240 */
|
||||
#define PERI_PPU_GR10 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[10]) /* 0x40015280 */
|
||||
#define PERI_PPU_GR_MMIO0 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO0_BASE) /* 0x40015000 */
|
||||
#define PERI_PPU_GR_MMIO1 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO1_BASE) /* 0x40015040 */
|
||||
#define PERI_PPU_GR_MMIO2 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO2_BASE) /* 0x40015080 */
|
||||
#define PERI_PPU_GR_MMIO3 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO3_BASE) /* 0x400150C0 */
|
||||
#define PERI_PPU_GR_MMIO4 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO4_BASE) /* 0x40015100 */
|
||||
#define PERI_PPU_GR_MMIO6 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO6_BASE) /* 0x40015180 */
|
||||
#define PERI_PPU_GR_MMIO9 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO9_BASE) /* 0x40015240 */
|
||||
#define PERI_PPU_GR_MMIO10 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO10_BASE) /* 0x40015280 */
|
||||
#define PERI_GR_PPU_SL_PERI_GR1 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR1_BASE) /* 0x40100000 */
|
||||
#define PERI_GR_PPU_SL_CRYPTO ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_CRYPTO_BASE) /* 0x40100040 */
|
||||
#define PERI_GR_PPU_SL_PERI_GR2 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR2_BASE) /* 0x40200000 */
|
||||
#define PERI_GR_PPU_SL_CPUSS ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_CPUSS_BASE) /* 0x40200040 */
|
||||
#define PERI_GR_PPU_SL_FAULT ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_FAULT_BASE) /* 0x40200080 */
|
||||
#define PERI_GR_PPU_SL_IPC ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_IPC_BASE) /* 0x402000C0 */
|
||||
#define PERI_GR_PPU_SL_PROT ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PROT_BASE) /* 0x40200100 */
|
||||
#define PERI_GR_PPU_SL_FLASHC ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_FLASHC_BASE) /* 0x40200140 */
|
||||
#define PERI_GR_PPU_SL_SRSS ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SRSS_BASE) /* 0x40200180 */
|
||||
#define PERI_GR_PPU_SL_BACKUP ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_BACKUP_BASE) /* 0x402001C0 */
|
||||
#define PERI_GR_PPU_SL_DW0 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_DW0_BASE) /* 0x40200200 */
|
||||
#define PERI_GR_PPU_SL_DW1 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_DW1_BASE) /* 0x40200240 */
|
||||
#define PERI_GR_PPU_SL_EFUSE ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_EFUSE_BASE) /* 0x40200300 */
|
||||
#define PERI_GR_PPU_SL_PROFILE ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PROFILE_BASE) /* 0x40200340 */
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT0 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT0_BASE) /* 0x40201000 */
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT1 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT1_BASE) /* 0x40201040 */
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT2 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT2_BASE) /* 0x40201080 */
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT3 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT3_BASE) /* 0x402010C0 */
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT4 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT4_BASE) /* 0x40201100 */
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT5 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT5_BASE) /* 0x40201140 */
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT6 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT6_BASE) /* 0x40201180 */
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT7 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT7_BASE) /* 0x402011C0 */
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT0 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT0_BASE) /* 0x40201200 */
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT1 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT1_BASE) /* 0x40201240 */
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT2 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT2_BASE) /* 0x40201280 */
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT3 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT3_BASE) /* 0x402012C0 */
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT4 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT4_BASE) /* 0x40201300 */
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT5 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT5_BASE) /* 0x40201340 */
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT6 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT6_BASE) /* 0x40201380 */
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT7 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT7_BASE) /* 0x402013C0 */
|
||||
#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT0 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW0_DW_CH_STRUCT0_BASE) /* 0x40201400 */
|
||||
#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT1 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW0_DW_CH_STRUCT1_BASE) /* 0x40201440 */
|
||||
#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT2 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW0_DW_CH_STRUCT2_BASE) /* 0x40201480 */
|
||||
#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT3 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW0_DW_CH_STRUCT3_BASE) /* 0x402014C0 */
|
||||
#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT0 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW1_DW_CH_STRUCT0_BASE) /* 0x40201500 */
|
||||
#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT1 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW1_DW_CH_STRUCT1_BASE) /* 0x40201540 */
|
||||
#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT2 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW1_DW_CH_STRUCT2_BASE) /* 0x40201580 */
|
||||
#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT3 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW1_DW_CH_STRUCT3_BASE) /* 0x402015C0 */
|
||||
#define PERI_GR_PPU_RG_SMPU ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_SMPU_BASE) /* 0x40201600 */
|
||||
#define PERI_GR_PPU_RG_MPU_CM0P ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_MPU_CM0P_BASE) /* 0x40201640 */
|
||||
#define PERI_GR_PPU_RG_MPU_CRYPTO ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_MPU_CRYPTO_BASE) /* 0x40201680 */
|
||||
#define PERI_GR_PPU_RG_MPU_CM4 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_MPU_CM4_BASE) /* 0x402016C0 */
|
||||
#define PERI_GR_PPU_RG_MPU_TC ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_MPU_TC_BASE) /* 0x40201700 */
|
||||
#define PERI_GR_PPU_SL_PERI_GR3 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR3_BASE) /* 0x40300000 */
|
||||
#define PERI_GR_PPU_SL_HSIOM ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_HSIOM_BASE) /* 0x40300040 */
|
||||
#define PERI_GR_PPU_SL_GPIO ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_GPIO_BASE) /* 0x40300080 */
|
||||
#define PERI_GR_PPU_SL_SMARTIO ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SMARTIO_BASE) /* 0x403000C0 */
|
||||
#define PERI_GR_PPU_SL_UDB ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_UDB_BASE) /* 0x40300100 */
|
||||
#define PERI_GR_PPU_SL_LPCOMP ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_LPCOMP_BASE) /* 0x40300140 */
|
||||
#define PERI_GR_PPU_SL_CSD ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_CSD_BASE) /* 0x40300180 */
|
||||
#define PERI_GR_PPU_SL_TCPWM0 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_TCPWM0_BASE) /* 0x40300200 */
|
||||
#define PERI_GR_PPU_SL_TCPWM1 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_TCPWM1_BASE) /* 0x40300240 */
|
||||
#define PERI_GR_PPU_SL_LCD ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_LCD_BASE) /* 0x40300280 */
|
||||
#define PERI_GR_PPU_SL_BLE ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_BLE_BASE) /* 0x403002C0 */
|
||||
#define PERI_GR_PPU_SL_USBFS ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_USBFS_BASE) /* 0x40300300 */
|
||||
#define PERI_GR_PPU_SL_PERI_GR4 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR4_BASE) /* 0x40400000 */
|
||||
#define PERI_GR_PPU_SL_SMIF ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SMIF_BASE) /* 0x40400080 */
|
||||
#define PERI_GR_PPU_SL_PERI_GR6 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR6_BASE) /* 0x40600000 */
|
||||
#define PERI_GR_PPU_SL_SCB0 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB0_BASE) /* 0x40600040 */
|
||||
#define PERI_GR_PPU_SL_SCB1 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB1_BASE) /* 0x40600080 */
|
||||
#define PERI_GR_PPU_SL_SCB2 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB2_BASE) /* 0x406000C0 */
|
||||
#define PERI_GR_PPU_SL_SCB3 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB3_BASE) /* 0x40600100 */
|
||||
#define PERI_GR_PPU_SL_SCB4 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB4_BASE) /* 0x40600140 */
|
||||
#define PERI_GR_PPU_SL_SCB5 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB5_BASE) /* 0x40600180 */
|
||||
#define PERI_GR_PPU_SL_SCB6 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB6_BASE) /* 0x406001C0 */
|
||||
#define PERI_GR_PPU_SL_SCB7 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB7_BASE) /* 0x40600200 */
|
||||
#define PERI_GR_PPU_SL_SCB8 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB8_BASE) /* 0x40600240 */
|
||||
#define PERI_GR_PPU_SL_PERI_GR9 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR9_BASE) /* 0x41000000 */
|
||||
#define PERI_GR_PPU_SL_PASS ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PASS_BASE) /* 0x41000040 */
|
||||
#define PERI_GR_PPU_SL_PERI_GR10 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR10_BASE) /* 0x42A00000 */
|
||||
#define PERI_GR_PPU_SL_I2S ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_I2S_BASE) /* 0x42A00040 */
|
||||
#define PERI_GR_PPU_SL_PDM ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PDM_BASE) /* 0x42A00080 */
|
||||
|
||||
/*******************************************************************************
|
||||
* CPUSS
|
||||
*******************************************************************************/
|
||||
|
||||
#define CPUSS_BASE 0x40210000UL
|
||||
#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40210000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* FAULT
|
||||
*******************************************************************************/
|
||||
|
||||
#define FAULT_BASE 0x40220000UL
|
||||
#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40220000 */
|
||||
#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40220000 */
|
||||
#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40220100 */
|
||||
|
||||
/*******************************************************************************
|
||||
* IPC
|
||||
*******************************************************************************/
|
||||
|
||||
#define IPC_BASE 0x40230000UL
|
||||
#define IPC ((IPC_Type*) IPC_BASE) /* 0x40230000 */
|
||||
#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40230000 */
|
||||
#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40230020 */
|
||||
#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40230040 */
|
||||
#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40230060 */
|
||||
#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40230080 */
|
||||
#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402300A0 */
|
||||
#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402300C0 */
|
||||
#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402300E0 */
|
||||
#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40230100 */
|
||||
#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40230120 */
|
||||
#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40230140 */
|
||||
#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40230160 */
|
||||
#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40230180 */
|
||||
#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402301A0 */
|
||||
#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402301C0 */
|
||||
#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402301E0 */
|
||||
#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40231000 */
|
||||
#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40231020 */
|
||||
#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40231040 */
|
||||
#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40231060 */
|
||||
#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40231080 */
|
||||
#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402310A0 */
|
||||
#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402310C0 */
|
||||
#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402310E0 */
|
||||
#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40231100 */
|
||||
#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40231120 */
|
||||
#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40231140 */
|
||||
#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40231160 */
|
||||
#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40231180 */
|
||||
#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402311A0 */
|
||||
#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402311C0 */
|
||||
#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402311E0 */
|
||||
|
||||
/*******************************************************************************
|
||||
* PROT
|
||||
*******************************************************************************/
|
||||
|
||||
#define PROT_BASE 0x40240000UL
|
||||
#define PROT ((PROT_Type*) PROT_BASE) /* 0x40240000 */
|
||||
#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40242000 */
|
||||
#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40242040 */
|
||||
#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40242080 */
|
||||
#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402420C0 */
|
||||
#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40242100 */
|
||||
#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40242140 */
|
||||
#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40242180 */
|
||||
#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402421C0 */
|
||||
#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40242200 */
|
||||
#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40242240 */
|
||||
#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40242280 */
|
||||
#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402422C0 */
|
||||
#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40242300 */
|
||||
#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40242340 */
|
||||
#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40242380 */
|
||||
#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402423C0 */
|
||||
#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */
|
||||
#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */
|
||||
#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */
|
||||
#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */
|
||||
#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */
|
||||
#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */
|
||||
#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */
|
||||
#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */
|
||||
#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */
|
||||
#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */
|
||||
#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */
|
||||
#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */
|
||||
#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */
|
||||
#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */
|
||||
#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */
|
||||
#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */
|
||||
#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */
|
||||
#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40244000 */
|
||||
#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40244400 */
|
||||
#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40244800 */
|
||||
#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40244C00 */
|
||||
#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40245000 */
|
||||
#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40245400 */
|
||||
#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40245800 */
|
||||
#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40245C00 */
|
||||
#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40246000 */
|
||||
#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40246400 */
|
||||
#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40246800 */
|
||||
#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40246C00 */
|
||||
#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40247000 */
|
||||
#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40247400 */
|
||||
#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40247800 */
|
||||
#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40247C00 */
|
||||
|
||||
/*******************************************************************************
|
||||
* FLASHC
|
||||
*******************************************************************************/
|
||||
|
||||
#define FLASHC_BASE 0x40250000UL
|
||||
#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40250000 */
|
||||
#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4025F000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* SRSS
|
||||
*******************************************************************************/
|
||||
|
||||
#define SRSS_BASE 0x40260000UL
|
||||
#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */
|
||||
#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */
|
||||
#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */
|
||||
|
||||
/*******************************************************************************
|
||||
* BACKUP
|
||||
*******************************************************************************/
|
||||
|
||||
#define BACKUP_BASE 0x40270000UL
|
||||
#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* DW
|
||||
*******************************************************************************/
|
||||
|
||||
#define DW0_BASE 0x40280000UL
|
||||
#define DW1_BASE 0x40281000UL
|
||||
#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */
|
||||
#define DW1 ((DW_Type*) DW1_BASE) /* 0x40281000 */
|
||||
#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40280800 */
|
||||
#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40280820 */
|
||||
#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40280840 */
|
||||
#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x40280860 */
|
||||
#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40280880 */
|
||||
#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x402808A0 */
|
||||
#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x402808C0 */
|
||||
#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402808E0 */
|
||||
#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40280900 */
|
||||
#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40280920 */
|
||||
#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40280940 */
|
||||
#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x40280960 */
|
||||
#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40280980 */
|
||||
#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x402809A0 */
|
||||
#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x402809C0 */
|
||||
#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402809E0 */
|
||||
#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40281800 */
|
||||
#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40281820 */
|
||||
#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40281840 */
|
||||
#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x40281860 */
|
||||
#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40281880 */
|
||||
#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x402818A0 */
|
||||
#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x402818C0 */
|
||||
#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402818E0 */
|
||||
#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40281900 */
|
||||
#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40281920 */
|
||||
#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40281940 */
|
||||
#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x40281960 */
|
||||
#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40281980 */
|
||||
#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x402819A0 */
|
||||
#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x402819C0 */
|
||||
#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402819E0 */
|
||||
|
||||
/*******************************************************************************
|
||||
* EFUSE
|
||||
*******************************************************************************/
|
||||
|
||||
#define EFUSE_BASE 0x402C0000UL
|
||||
#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* PROFILE
|
||||
*******************************************************************************/
|
||||
|
||||
#define PROFILE_BASE 0x402D0000UL
|
||||
#define PROFILE ((PROFILE_Type*) PROFILE_BASE) /* 0x402D0000 */
|
||||
#define PROFILE_CNT_STRUCT0 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[0]) /* 0x402D0800 */
|
||||
#define PROFILE_CNT_STRUCT1 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[1]) /* 0x402D0810 */
|
||||
#define PROFILE_CNT_STRUCT2 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[2]) /* 0x402D0820 */
|
||||
#define PROFILE_CNT_STRUCT3 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[3]) /* 0x402D0830 */
|
||||
#define PROFILE_CNT_STRUCT4 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[4]) /* 0x402D0840 */
|
||||
#define PROFILE_CNT_STRUCT5 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[5]) /* 0x402D0850 */
|
||||
#define PROFILE_CNT_STRUCT6 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[6]) /* 0x402D0860 */
|
||||
#define PROFILE_CNT_STRUCT7 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[7]) /* 0x402D0870 */
|
||||
|
||||
/*******************************************************************************
|
||||
* HSIOM
|
||||
*******************************************************************************/
|
||||
|
||||
#define HSIOM_BASE 0x40310000UL
|
||||
#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40310000 */
|
||||
#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40310000 */
|
||||
#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40310010 */
|
||||
#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40310020 */
|
||||
#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40310030 */
|
||||
#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40310040 */
|
||||
#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40310050 */
|
||||
#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40310060 */
|
||||
#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40310070 */
|
||||
#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40310080 */
|
||||
#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40310090 */
|
||||
#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403100A0 */
|
||||
#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403100B0 */
|
||||
#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403100C0 */
|
||||
#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403100D0 */
|
||||
#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403100E0 */
|
||||
|
||||
/*******************************************************************************
|
||||
* GPIO
|
||||
*******************************************************************************/
|
||||
|
||||
#define GPIO_BASE 0x40320000UL
|
||||
#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40320000 */
|
||||
#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40320000 */
|
||||
#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40320080 */
|
||||
#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40320100 */
|
||||
#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40320180 */
|
||||
#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40320200 */
|
||||
#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40320280 */
|
||||
#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40320300 */
|
||||
#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40320380 */
|
||||
#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40320400 */
|
||||
#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40320480 */
|
||||
#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40320500 */
|
||||
#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40320580 */
|
||||
#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40320600 */
|
||||
#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40320680 */
|
||||
#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40320700 */
|
||||
|
||||
/*******************************************************************************
|
||||
* SMARTIO
|
||||
*******************************************************************************/
|
||||
|
||||
#define SMARTIO_BASE 0x40330000UL
|
||||
#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40330000 */
|
||||
#define SMARTIO_PRT8 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[8]) /* 0x40330800 */
|
||||
#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40330900 */
|
||||
|
||||
/*******************************************************************************
|
||||
* LPCOMP
|
||||
*******************************************************************************/
|
||||
|
||||
#define LPCOMP_BASE 0x40350000UL
|
||||
#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* CSD
|
||||
*******************************************************************************/
|
||||
|
||||
#define CSD0_BASE 0x40360000UL
|
||||
#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* TCPWM
|
||||
*******************************************************************************/
|
||||
|
||||
#define TCPWM0_BASE 0x40380000UL
|
||||
#define TCPWM1_BASE 0x40390000UL
|
||||
#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */
|
||||
#define TCPWM1 ((TCPWM_Type*) TCPWM1_BASE) /* 0x40390000 */
|
||||
#define TCPWM0_CNT0 ((TCPWM_CNT_Type*) &TCPWM0->CNT[0]) /* 0x40380100 */
|
||||
#define TCPWM0_CNT1 ((TCPWM_CNT_Type*) &TCPWM0->CNT[1]) /* 0x40380140 */
|
||||
#define TCPWM0_CNT2 ((TCPWM_CNT_Type*) &TCPWM0->CNT[2]) /* 0x40380180 */
|
||||
#define TCPWM0_CNT3 ((TCPWM_CNT_Type*) &TCPWM0->CNT[3]) /* 0x403801C0 */
|
||||
#define TCPWM0_CNT4 ((TCPWM_CNT_Type*) &TCPWM0->CNT[4]) /* 0x40380200 */
|
||||
#define TCPWM0_CNT5 ((TCPWM_CNT_Type*) &TCPWM0->CNT[5]) /* 0x40380240 */
|
||||
#define TCPWM0_CNT6 ((TCPWM_CNT_Type*) &TCPWM0->CNT[6]) /* 0x40380280 */
|
||||
#define TCPWM0_CNT7 ((TCPWM_CNT_Type*) &TCPWM0->CNT[7]) /* 0x403802C0 */
|
||||
#define TCPWM1_CNT0 ((TCPWM_CNT_Type*) &TCPWM1->CNT[0]) /* 0x40390100 */
|
||||
#define TCPWM1_CNT1 ((TCPWM_CNT_Type*) &TCPWM1->CNT[1]) /* 0x40390140 */
|
||||
#define TCPWM1_CNT2 ((TCPWM_CNT_Type*) &TCPWM1->CNT[2]) /* 0x40390180 */
|
||||
#define TCPWM1_CNT3 ((TCPWM_CNT_Type*) &TCPWM1->CNT[3]) /* 0x403901C0 */
|
||||
#define TCPWM1_CNT4 ((TCPWM_CNT_Type*) &TCPWM1->CNT[4]) /* 0x40390200 */
|
||||
#define TCPWM1_CNT5 ((TCPWM_CNT_Type*) &TCPWM1->CNT[5]) /* 0x40390240 */
|
||||
#define TCPWM1_CNT6 ((TCPWM_CNT_Type*) &TCPWM1->CNT[6]) /* 0x40390280 */
|
||||
#define TCPWM1_CNT7 ((TCPWM_CNT_Type*) &TCPWM1->CNT[7]) /* 0x403902C0 */
|
||||
#define TCPWM1_CNT8 ((TCPWM_CNT_Type*) &TCPWM1->CNT[8]) /* 0x40390300 */
|
||||
#define TCPWM1_CNT9 ((TCPWM_CNT_Type*) &TCPWM1->CNT[9]) /* 0x40390340 */
|
||||
#define TCPWM1_CNT10 ((TCPWM_CNT_Type*) &TCPWM1->CNT[10]) /* 0x40390380 */
|
||||
#define TCPWM1_CNT11 ((TCPWM_CNT_Type*) &TCPWM1->CNT[11]) /* 0x403903C0 */
|
||||
#define TCPWM1_CNT12 ((TCPWM_CNT_Type*) &TCPWM1->CNT[12]) /* 0x40390400 */
|
||||
#define TCPWM1_CNT13 ((TCPWM_CNT_Type*) &TCPWM1->CNT[13]) /* 0x40390440 */
|
||||
#define TCPWM1_CNT14 ((TCPWM_CNT_Type*) &TCPWM1->CNT[14]) /* 0x40390480 */
|
||||
#define TCPWM1_CNT15 ((TCPWM_CNT_Type*) &TCPWM1->CNT[15]) /* 0x403904C0 */
|
||||
#define TCPWM1_CNT16 ((TCPWM_CNT_Type*) &TCPWM1->CNT[16]) /* 0x40390500 */
|
||||
#define TCPWM1_CNT17 ((TCPWM_CNT_Type*) &TCPWM1->CNT[17]) /* 0x40390540 */
|
||||
#define TCPWM1_CNT18 ((TCPWM_CNT_Type*) &TCPWM1->CNT[18]) /* 0x40390580 */
|
||||
#define TCPWM1_CNT19 ((TCPWM_CNT_Type*) &TCPWM1->CNT[19]) /* 0x403905C0 */
|
||||
#define TCPWM1_CNT20 ((TCPWM_CNT_Type*) &TCPWM1->CNT[20]) /* 0x40390600 */
|
||||
#define TCPWM1_CNT21 ((TCPWM_CNT_Type*) &TCPWM1->CNT[21]) /* 0x40390640 */
|
||||
#define TCPWM1_CNT22 ((TCPWM_CNT_Type*) &TCPWM1->CNT[22]) /* 0x40390680 */
|
||||
#define TCPWM1_CNT23 ((TCPWM_CNT_Type*) &TCPWM1->CNT[23]) /* 0x403906C0 */
|
||||
|
||||
/*******************************************************************************
|
||||
* LCD
|
||||
*******************************************************************************/
|
||||
|
||||
#define LCD0_BASE 0x403B0000UL
|
||||
#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* USBFS
|
||||
*******************************************************************************/
|
||||
|
||||
#define USBFS0_BASE 0x403F0000UL
|
||||
#define USBFS0 ((USBFS_Type*) USBFS0_BASE) /* 0x403F0000 */
|
||||
#define USBFS0_USBDEV ((USBFS_USBDEV_Type*) &USBFS0->USBDEV) /* 0x403F0000 */
|
||||
#define USBFS0_USBLPM ((USBFS_USBLPM_Type*) &USBFS0->USBLPM) /* 0x403F2000 */
|
||||
#define USBFS0_USBHOST ((USBFS_USBHOST_Type*) &USBFS0->USBHOST) /* 0x403F4000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* SMIF
|
||||
*******************************************************************************/
|
||||
|
||||
#define SMIF0_BASE 0x40420000UL
|
||||
#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */
|
||||
#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */
|
||||
#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */
|
||||
#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */
|
||||
#define SMIF0_DEVICE3 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[3]) /* 0x40420980 */
|
||||
|
||||
/*******************************************************************************
|
||||
* SCB
|
||||
*******************************************************************************/
|
||||
|
||||
#define SCB0_BASE 0x40610000UL
|
||||
#define SCB1_BASE 0x40620000UL
|
||||
#define SCB2_BASE 0x40630000UL
|
||||
#define SCB3_BASE 0x40640000UL
|
||||
#define SCB4_BASE 0x40650000UL
|
||||
#define SCB5_BASE 0x40660000UL
|
||||
#define SCB6_BASE 0x40670000UL
|
||||
#define SCB7_BASE 0x40680000UL
|
||||
#define SCB8_BASE 0x40690000UL
|
||||
#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40610000 */
|
||||
#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40620000 */
|
||||
#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40630000 */
|
||||
#define SCB3 ((CySCB_Type*) SCB3_BASE) /* 0x40640000 */
|
||||
#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40650000 */
|
||||
#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40660000 */
|
||||
#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40670000 */
|
||||
#define SCB7 ((CySCB_Type*) SCB7_BASE) /* 0x40680000 */
|
||||
#define SCB8 ((CySCB_Type*) SCB8_BASE) /* 0x40690000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* CTDAC
|
||||
*******************************************************************************/
|
||||
|
||||
#define CTDAC0_BASE 0x41140000UL
|
||||
#define CTDAC0 ((CTDAC_Type*) CTDAC0_BASE) /* 0x41140000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* SAR
|
||||
*******************************************************************************/
|
||||
|
||||
#define SAR_BASE 0x411D0000UL
|
||||
#define SAR ((SAR_Type*) SAR_BASE) /* 0x411D0000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* PASS
|
||||
*******************************************************************************/
|
||||
|
||||
#define PASS_BASE 0x411F0000UL
|
||||
#define PASS ((PASS_Type*) PASS_BASE) /* 0x411F0000 */
|
||||
#define PASS_AREF ((PASS_AREF_Type*) &PASS->AREF) /* 0x411F0E00 */
|
||||
|
||||
/*******************************************************************************
|
||||
* I2S
|
||||
*******************************************************************************/
|
||||
|
||||
#define I2S0_BASE 0x42A10000UL
|
||||
#define I2S0 ((I2S_Type*) I2S0_BASE) /* 0x42A10000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* PDM
|
||||
*******************************************************************************/
|
||||
|
||||
#define PDM0_BASE 0x42A20000UL
|
||||
#define PDM0 ((PDM_Type*) PDM0_BASE) /* 0x42A20000 */
|
||||
|
||||
|
||||
/* Backward compabitility definitions */
|
||||
#define I2S I2S0
|
||||
#define PDM PDM0
|
||||
|
||||
/** \} CY8C6117FDI-F02 */
|
||||
|
||||
#endif /* _CY8C6117FDI_F02_H_ */
|
||||
|
||||
|
||||
/* [] END OF FILE */
|
||||
|
|
@ -1,933 +0,0 @@
|
|||
/***************************************************************************//**
|
||||
* \file cy8c6136bzi_f14.h
|
||||
*
|
||||
* \brief
|
||||
* CY8C6136BZI-F14 device header
|
||||
*
|
||||
* \note
|
||||
* Generator version: 1.3.0.1146
|
||||
* Database revision: rev#1050929
|
||||
*
|
||||
********************************************************************************
|
||||
* \copyright
|
||||
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
|
||||
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _CY8C6136BZI_F14_H_
|
||||
#define _CY8C6136BZI_F14_H_
|
||||
|
||||
/**
|
||||
* \addtogroup group_device CY8C6136BZI-F14
|
||||
* \{
|
||||
*/
|
||||
|
||||
/**
|
||||
* \addtogroup Configuration_of_CMSIS
|
||||
* \{
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Interrupt Number Definition
|
||||
*******************************************************************************/
|
||||
|
||||
typedef enum {
|
||||
/* ARM Cortex-M4 Core Interrupt Numbers */
|
||||
Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */
|
||||
NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */
|
||||
HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */
|
||||
MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */
|
||||
BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */
|
||||
UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
|
||||
SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */
|
||||
DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */
|
||||
PendSV_IRQn = -2, /*!< -2 Pendable request for system service */
|
||||
SysTick_IRQn = -1, /*!< -1 System Tick Timer */
|
||||
/* CY8C6136BZI-F14 Peripheral Interrupt Numbers */
|
||||
ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */
|
||||
ioss_interrupts_gpio_1_IRQn = 1, /*!< 1 [DeepSleep] GPIO Port Interrupt #1 */
|
||||
ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */
|
||||
ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */
|
||||
ioss_interrupts_gpio_4_IRQn = 4, /*!< 4 [DeepSleep] GPIO Port Interrupt #4 */
|
||||
ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */
|
||||
ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */
|
||||
ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */
|
||||
ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */
|
||||
ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */
|
||||
ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */
|
||||
ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */
|
||||
ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */
|
||||
ioss_interrupts_gpio_13_IRQn = 13, /*!< 13 [DeepSleep] GPIO Port Interrupt #13 */
|
||||
ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */
|
||||
ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */
|
||||
ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */
|
||||
lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */
|
||||
scb_8_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #8 (DeepSleep capable) */
|
||||
srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */
|
||||
srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */
|
||||
srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */
|
||||
srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */
|
||||
pass_interrupt_ctbs_IRQn = 23, /*!< 23 [DeepSleep] CTBm Interrupt (all CTBms) */
|
||||
bless_interrupt_IRQn = 24, /*!< 24 [DeepSleep] Bluetooth Radio interrupt */
|
||||
cpuss_interrupts_ipc_0_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */
|
||||
cpuss_interrupts_ipc_1_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */
|
||||
cpuss_interrupts_ipc_2_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */
|
||||
cpuss_interrupts_ipc_3_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */
|
||||
cpuss_interrupts_ipc_4_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */
|
||||
cpuss_interrupts_ipc_5_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */
|
||||
cpuss_interrupts_ipc_6_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */
|
||||
cpuss_interrupts_ipc_7_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */
|
||||
cpuss_interrupts_ipc_8_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */
|
||||
cpuss_interrupts_ipc_9_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */
|
||||
cpuss_interrupts_ipc_10_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */
|
||||
cpuss_interrupts_ipc_11_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */
|
||||
cpuss_interrupts_ipc_12_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */
|
||||
cpuss_interrupts_ipc_13_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */
|
||||
cpuss_interrupts_ipc_14_IRQn = 39, /*!< 39 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */
|
||||
cpuss_interrupts_ipc_15_IRQn = 40, /*!< 40 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */
|
||||
scb_0_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #0 */
|
||||
scb_1_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #1 */
|
||||
scb_2_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #2 */
|
||||
scb_3_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #3 */
|
||||
scb_4_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #4 */
|
||||
scb_5_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #5 */
|
||||
scb_6_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #6 */
|
||||
scb_7_interrupt_IRQn = 48, /*!< 48 [Active] Serial Communication Block #7 */
|
||||
csd_interrupt_IRQn = 49, /*!< 49 [Active] CSD (Capsense) interrupt */
|
||||
cpuss_interrupts_dw0_0_IRQn = 50, /*!< 50 [Active] CPUSS DataWire #0, Channel #0 */
|
||||
cpuss_interrupts_dw0_1_IRQn = 51, /*!< 51 [Active] CPUSS DataWire #0, Channel #1 */
|
||||
cpuss_interrupts_dw0_2_IRQn = 52, /*!< 52 [Active] CPUSS DataWire #0, Channel #2 */
|
||||
cpuss_interrupts_dw0_3_IRQn = 53, /*!< 53 [Active] CPUSS DataWire #0, Channel #3 */
|
||||
cpuss_interrupts_dw0_4_IRQn = 54, /*!< 54 [Active] CPUSS DataWire #0, Channel #4 */
|
||||
cpuss_interrupts_dw0_5_IRQn = 55, /*!< 55 [Active] CPUSS DataWire #0, Channel #5 */
|
||||
cpuss_interrupts_dw0_6_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #6 */
|
||||
cpuss_interrupts_dw0_7_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #7 */
|
||||
cpuss_interrupts_dw0_8_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #8 */
|
||||
cpuss_interrupts_dw0_9_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #9 */
|
||||
cpuss_interrupts_dw0_10_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #10 */
|
||||
cpuss_interrupts_dw0_11_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #11 */
|
||||
cpuss_interrupts_dw0_12_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #12 */
|
||||
cpuss_interrupts_dw0_13_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #13 */
|
||||
cpuss_interrupts_dw0_14_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #14 */
|
||||
cpuss_interrupts_dw0_15_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #15 */
|
||||
cpuss_interrupts_dw1_0_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #1, Channel #0 */
|
||||
cpuss_interrupts_dw1_1_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #1, Channel #1 */
|
||||
cpuss_interrupts_dw1_2_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #1, Channel #2 */
|
||||
cpuss_interrupts_dw1_3_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #1, Channel #3 */
|
||||
cpuss_interrupts_dw1_4_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #1, Channel #4 */
|
||||
cpuss_interrupts_dw1_5_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #1, Channel #5 */
|
||||
cpuss_interrupts_dw1_6_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #1, Channel #6 */
|
||||
cpuss_interrupts_dw1_7_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #1, Channel #7 */
|
||||
cpuss_interrupts_dw1_8_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #1, Channel #8 */
|
||||
cpuss_interrupts_dw1_9_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #1, Channel #9 */
|
||||
cpuss_interrupts_dw1_10_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #1, Channel #10 */
|
||||
cpuss_interrupts_dw1_11_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #1, Channel #11 */
|
||||
cpuss_interrupts_dw1_12_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #1, Channel #12 */
|
||||
cpuss_interrupts_dw1_13_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #1, Channel #13 */
|
||||
cpuss_interrupts_dw1_14_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #1, Channel #14 */
|
||||
cpuss_interrupts_dw1_15_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #1, Channel #15 */
|
||||
cpuss_interrupts_fault_0_IRQn = 82, /*!< 82 [Active] CPUSS Fault Structure Interrupt #0 */
|
||||
cpuss_interrupts_fault_1_IRQn = 83, /*!< 83 [Active] CPUSS Fault Structure Interrupt #1 */
|
||||
cpuss_interrupt_crypto_IRQn = 84, /*!< 84 [Active] CRYPTO Accelerator Interrupt */
|
||||
cpuss_interrupt_fm_IRQn = 85, /*!< 85 [Active] FLASH Macro Interrupt */
|
||||
cpuss_interrupts_cm0_cti_0_IRQn = 86, /*!< 86 [Active] CM0+ CTI #0 */
|
||||
cpuss_interrupts_cm0_cti_1_IRQn = 87, /*!< 87 [Active] CM0+ CTI #1 */
|
||||
cpuss_interrupts_cm4_cti_0_IRQn = 88, /*!< 88 [Active] CM4 CTI #0 */
|
||||
cpuss_interrupts_cm4_cti_1_IRQn = 89, /*!< 89 [Active] CM4 CTI #1 */
|
||||
tcpwm_0_interrupts_0_IRQn = 90, /*!< 90 [Active] TCPWM #0, Counter #0 */
|
||||
tcpwm_0_interrupts_1_IRQn = 91, /*!< 91 [Active] TCPWM #0, Counter #1 */
|
||||
tcpwm_0_interrupts_2_IRQn = 92, /*!< 92 [Active] TCPWM #0, Counter #2 */
|
||||
tcpwm_0_interrupts_3_IRQn = 93, /*!< 93 [Active] TCPWM #0, Counter #3 */
|
||||
tcpwm_0_interrupts_4_IRQn = 94, /*!< 94 [Active] TCPWM #0, Counter #4 */
|
||||
tcpwm_0_interrupts_5_IRQn = 95, /*!< 95 [Active] TCPWM #0, Counter #5 */
|
||||
tcpwm_0_interrupts_6_IRQn = 96, /*!< 96 [Active] TCPWM #0, Counter #6 */
|
||||
tcpwm_0_interrupts_7_IRQn = 97, /*!< 97 [Active] TCPWM #0, Counter #7 */
|
||||
tcpwm_1_interrupts_0_IRQn = 98, /*!< 98 [Active] TCPWM #1, Counter #0 */
|
||||
tcpwm_1_interrupts_1_IRQn = 99, /*!< 99 [Active] TCPWM #1, Counter #1 */
|
||||
tcpwm_1_interrupts_2_IRQn = 100, /*!< 100 [Active] TCPWM #1, Counter #2 */
|
||||
tcpwm_1_interrupts_3_IRQn = 101, /*!< 101 [Active] TCPWM #1, Counter #3 */
|
||||
tcpwm_1_interrupts_4_IRQn = 102, /*!< 102 [Active] TCPWM #1, Counter #4 */
|
||||
tcpwm_1_interrupts_5_IRQn = 103, /*!< 103 [Active] TCPWM #1, Counter #5 */
|
||||
tcpwm_1_interrupts_6_IRQn = 104, /*!< 104 [Active] TCPWM #1, Counter #6 */
|
||||
tcpwm_1_interrupts_7_IRQn = 105, /*!< 105 [Active] TCPWM #1, Counter #7 */
|
||||
tcpwm_1_interrupts_8_IRQn = 106, /*!< 106 [Active] TCPWM #1, Counter #8 */
|
||||
tcpwm_1_interrupts_9_IRQn = 107, /*!< 107 [Active] TCPWM #1, Counter #9 */
|
||||
tcpwm_1_interrupts_10_IRQn = 108, /*!< 108 [Active] TCPWM #1, Counter #10 */
|
||||
tcpwm_1_interrupts_11_IRQn = 109, /*!< 109 [Active] TCPWM #1, Counter #11 */
|
||||
tcpwm_1_interrupts_12_IRQn = 110, /*!< 110 [Active] TCPWM #1, Counter #12 */
|
||||
tcpwm_1_interrupts_13_IRQn = 111, /*!< 111 [Active] TCPWM #1, Counter #13 */
|
||||
tcpwm_1_interrupts_14_IRQn = 112, /*!< 112 [Active] TCPWM #1, Counter #14 */
|
||||
tcpwm_1_interrupts_15_IRQn = 113, /*!< 113 [Active] TCPWM #1, Counter #15 */
|
||||
tcpwm_1_interrupts_16_IRQn = 114, /*!< 114 [Active] TCPWM #1, Counter #16 */
|
||||
tcpwm_1_interrupts_17_IRQn = 115, /*!< 115 [Active] TCPWM #1, Counter #17 */
|
||||
tcpwm_1_interrupts_18_IRQn = 116, /*!< 116 [Active] TCPWM #1, Counter #18 */
|
||||
tcpwm_1_interrupts_19_IRQn = 117, /*!< 117 [Active] TCPWM #1, Counter #19 */
|
||||
tcpwm_1_interrupts_20_IRQn = 118, /*!< 118 [Active] TCPWM #1, Counter #20 */
|
||||
tcpwm_1_interrupts_21_IRQn = 119, /*!< 119 [Active] TCPWM #1, Counter #21 */
|
||||
tcpwm_1_interrupts_22_IRQn = 120, /*!< 120 [Active] TCPWM #1, Counter #22 */
|
||||
tcpwm_1_interrupts_23_IRQn = 121, /*!< 121 [Active] TCPWM #1, Counter #23 */
|
||||
udb_interrupts_0_IRQn = 122, /*!< 122 [Active] UDB Interrupt #0 */
|
||||
udb_interrupts_1_IRQn = 123, /*!< 123 [Active] UDB Interrupt #1 */
|
||||
udb_interrupts_2_IRQn = 124, /*!< 124 [Active] UDB Interrupt #2 */
|
||||
udb_interrupts_3_IRQn = 125, /*!< 125 [Active] UDB Interrupt #3 */
|
||||
udb_interrupts_4_IRQn = 126, /*!< 126 [Active] UDB Interrupt #4 */
|
||||
udb_interrupts_5_IRQn = 127, /*!< 127 [Active] UDB Interrupt #5 */
|
||||
udb_interrupts_6_IRQn = 128, /*!< 128 [Active] UDB Interrupt #6 */
|
||||
udb_interrupts_7_IRQn = 129, /*!< 129 [Active] UDB Interrupt #7 */
|
||||
udb_interrupts_8_IRQn = 130, /*!< 130 [Active] UDB Interrupt #8 */
|
||||
udb_interrupts_9_IRQn = 131, /*!< 131 [Active] UDB Interrupt #9 */
|
||||
udb_interrupts_10_IRQn = 132, /*!< 132 [Active] UDB Interrupt #10 */
|
||||
udb_interrupts_11_IRQn = 133, /*!< 133 [Active] UDB Interrupt #11 */
|
||||
udb_interrupts_12_IRQn = 134, /*!< 134 [Active] UDB Interrupt #12 */
|
||||
udb_interrupts_13_IRQn = 135, /*!< 135 [Active] UDB Interrupt #13 */
|
||||
udb_interrupts_14_IRQn = 136, /*!< 136 [Active] UDB Interrupt #14 */
|
||||
udb_interrupts_15_IRQn = 137, /*!< 137 [Active] UDB Interrupt #15 */
|
||||
pass_interrupt_sar_IRQn = 138, /*!< 138 [Active] SAR ADC interrupt */
|
||||
audioss_interrupt_i2s_IRQn = 139, /*!< 139 [Active] I2S Audio interrupt */
|
||||
audioss_interrupt_pdm_IRQn = 140, /*!< 140 [Active] PDM/PCM Audio interrupt */
|
||||
profile_interrupt_IRQn = 141, /*!< 141 [Active] Energy Profiler interrupt */
|
||||
smif_interrupt_IRQn = 142, /*!< 142 [Active] Serial Memory Interface interrupt */
|
||||
usb_interrupt_hi_IRQn = 143, /*!< 143 [Active] USB Interrupt */
|
||||
usb_interrupt_med_IRQn = 144, /*!< 144 [Active] USB Interrupt */
|
||||
usb_interrupt_lo_IRQn = 145, /*!< 145 [Active] USB Interrupt */
|
||||
pass_interrupt_dacs_IRQn = 146, /*!< 146 [Active] Consolidated interrrupt for all DACs */
|
||||
unconnected_IRQn = 240 /*!< 240 Unconnected */
|
||||
} IRQn_Type;
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Processor and Core Peripheral Section
|
||||
*******************************************************************************/
|
||||
|
||||
/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */
|
||||
#define __CM4_REV 0x0001U /*!< CM4 Core Revision */
|
||||
#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
|
||||
#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */
|
||||
#define __MPU_PRESENT 1 /*!< MPU present or not */
|
||||
#define __FPU_PRESENT 1 /*!< FPU present or not */
|
||||
#define __CM0P_PRESENT 0 /*!< CM0P present or not */
|
||||
|
||||
/** \} Configuration_of_CMSIS */
|
||||
|
||||
/* Memory Blocks */
|
||||
#define CY_ROM_BASE 0x00000000UL
|
||||
#define CY_ROM_SIZE 0x00020000UL
|
||||
#define CY_SRAM0_BASE 0x08000000UL
|
||||
#define CY_SRAM0_SIZE 0x00020000UL
|
||||
#define CY_FLASH_BASE 0x10000000UL
|
||||
#define CY_FLASH_SIZE 0x00080000UL
|
||||
#define CY_EM_EEPROM_BASE 0x14000000UL
|
||||
#define CY_EM_EEPROM_SIZE 0x00008000UL
|
||||
#define CY_XIP_BASE 0x18000000UL
|
||||
#define CY_XIP_SIZE 0x08000000UL
|
||||
#define CY_SFLASH_BASE 0x16000000UL
|
||||
#define CY_SFLASH_SIZE 0x00008000UL
|
||||
#define CY_EFUSE_BASE 0x402C0800UL
|
||||
#define CY_EFUSE_SIZE 0x00000200UL
|
||||
|
||||
#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */
|
||||
#include "system_psoc6.h" /*!< PSoC 6 System */
|
||||
|
||||
/* IP List */
|
||||
#define CY_IP_MXTCPWM 1u
|
||||
#define CY_IP_MXTCPWM_INSTANCES 2u
|
||||
#define CY_IP_MXTCPWM_VERSION 1u
|
||||
#define CY_IP_MXCSDV2 1u
|
||||
#define CY_IP_MXCSDV2_INSTANCES 1u
|
||||
#define CY_IP_MXCSDV2_VERSION 1u
|
||||
#define CY_IP_MXLCD 1u
|
||||
#define CY_IP_MXLCD_INSTANCES 1u
|
||||
#define CY_IP_MXLCD_VERSION 1u
|
||||
#define CY_IP_MXS40SRSS 1u
|
||||
#define CY_IP_MXS40SRSS_INSTANCES 1u
|
||||
#define CY_IP_MXS40SRSS_VERSION 1u
|
||||
#define CY_IP_MXS40SRSS_RTC 1u
|
||||
#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u
|
||||
#define CY_IP_MXS40SRSS_RTC_VERSION 1u
|
||||
#define CY_IP_MXS40SRSS_MCWDT 1u
|
||||
#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u
|
||||
#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u
|
||||
#define CY_IP_MXSCB 1u
|
||||
#define CY_IP_MXSCB_INSTANCES 9u
|
||||
#define CY_IP_MXSCB_VERSION 1u
|
||||
#define CY_IP_MXPERI 1u
|
||||
#define CY_IP_MXPERI_INSTANCES 1u
|
||||
#define CY_IP_MXPERI_VERSION 1u
|
||||
#define CY_IP_MXPERI_TR 1u
|
||||
#define CY_IP_MXPERI_TR_INSTANCES 1u
|
||||
#define CY_IP_MXPERI_TR_VERSION 1u
|
||||
#define CY_IP_M4CPUSS 1u
|
||||
#define CY_IP_M4CPUSS_INSTANCES 1u
|
||||
#define CY_IP_M4CPUSS_VERSION 1u
|
||||
#define CY_IP_M4CPUSS_DMA 1u
|
||||
#define CY_IP_M4CPUSS_DMA_INSTANCES 2u
|
||||
#define CY_IP_M4CPUSS_DMA_VERSION 1u
|
||||
#define CY_IP_MXAUDIOSS 1u
|
||||
#define CY_IP_MXAUDIOSS_INSTANCES 1u
|
||||
#define CY_IP_MXAUDIOSS_VERSION 1u
|
||||
#define CY_IP_MXLPCOMP 1u
|
||||
#define CY_IP_MXLPCOMP_INSTANCES 1u
|
||||
#define CY_IP_MXLPCOMP_VERSION 1u
|
||||
#define CY_IP_MXS40PASS 1u
|
||||
#define CY_IP_MXS40PASS_INSTANCES 1u
|
||||
#define CY_IP_MXS40PASS_VERSION 1u
|
||||
#define CY_IP_MXS40PASS_SAR 1u
|
||||
#define CY_IP_MXS40PASS_SAR_INSTANCES 16u
|
||||
#define CY_IP_MXS40PASS_SAR_VERSION 1u
|
||||
#define CY_IP_MXS40PASS_CTDAC 1u
|
||||
#define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u
|
||||
#define CY_IP_MXS40PASS_CTDAC_VERSION 1u
|
||||
#define CY_IP_MXSMIF 1u
|
||||
#define CY_IP_MXSMIF_INSTANCES 1u
|
||||
#define CY_IP_MXSMIF_VERSION 1u
|
||||
#define CY_IP_MXUSBFS 1u
|
||||
#define CY_IP_MXUSBFS_INSTANCES 1u
|
||||
#define CY_IP_MXUSBFS_VERSION 1u
|
||||
#define CY_IP_MXS40IOSS 1u
|
||||
#define CY_IP_MXS40IOSS_INSTANCES 1u
|
||||
#define CY_IP_MXS40IOSS_VERSION 1u
|
||||
#define CY_IP_MXEFUSE 1u
|
||||
#define CY_IP_MXEFUSE_INSTANCES 1u
|
||||
#define CY_IP_MXEFUSE_VERSION 1u
|
||||
#define CY_IP_MXPROFILE 1u
|
||||
#define CY_IP_MXPROFILE_INSTANCES 1u
|
||||
#define CY_IP_MXPROFILE_VERSION 1u
|
||||
|
||||
#include "psoc6able2_config.h"
|
||||
#include "gpio_psoc6able2_124_bga.h"
|
||||
|
||||
#define CY_DEVICE_PSOC6ABLE2
|
||||
#define CY_SILICON_ID 0xE2132100UL
|
||||
#define CY_HF_CLK_MAX_FREQ 150000000UL
|
||||
|
||||
#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL
|
||||
|
||||
/*******************************************************************************
|
||||
* SFLASH
|
||||
*******************************************************************************/
|
||||
|
||||
#define SFLASH_BASE 0x16000000UL
|
||||
#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* PERI
|
||||
*******************************************************************************/
|
||||
|
||||
#define PERI_BASE 0x40010000UL
|
||||
#define PERI_PPU_GR_MMIO0_BASE 0x40015000UL
|
||||
#define PERI_PPU_GR_MMIO1_BASE 0x40015040UL
|
||||
#define PERI_PPU_GR_MMIO2_BASE 0x40015080UL
|
||||
#define PERI_PPU_GR_MMIO3_BASE 0x400150C0UL
|
||||
#define PERI_PPU_GR_MMIO4_BASE 0x40015100UL
|
||||
#define PERI_PPU_GR_MMIO6_BASE 0x40015180UL
|
||||
#define PERI_PPU_GR_MMIO9_BASE 0x40015240UL
|
||||
#define PERI_PPU_GR_MMIO10_BASE 0x40015280UL
|
||||
#define PERI_GR_PPU_SL_PERI_GR1_BASE 0x40100000UL
|
||||
#define PERI_GR_PPU_SL_CRYPTO_BASE 0x40100040UL
|
||||
#define PERI_GR_PPU_SL_PERI_GR2_BASE 0x40200000UL
|
||||
#define PERI_GR_PPU_SL_CPUSS_BASE 0x40200040UL
|
||||
#define PERI_GR_PPU_SL_FAULT_BASE 0x40200080UL
|
||||
#define PERI_GR_PPU_SL_IPC_BASE 0x402000C0UL
|
||||
#define PERI_GR_PPU_SL_PROT_BASE 0x40200100UL
|
||||
#define PERI_GR_PPU_SL_FLASHC_BASE 0x40200140UL
|
||||
#define PERI_GR_PPU_SL_SRSS_BASE 0x40200180UL
|
||||
#define PERI_GR_PPU_SL_BACKUP_BASE 0x402001C0UL
|
||||
#define PERI_GR_PPU_SL_DW0_BASE 0x40200200UL
|
||||
#define PERI_GR_PPU_SL_DW1_BASE 0x40200240UL
|
||||
#define PERI_GR_PPU_SL_EFUSE_BASE 0x40200300UL
|
||||
#define PERI_GR_PPU_SL_PROFILE_BASE 0x40200340UL
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT0_BASE 0x40201000UL
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT1_BASE 0x40201040UL
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT2_BASE 0x40201080UL
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT3_BASE 0x402010C0UL
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT4_BASE 0x40201100UL
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT5_BASE 0x40201140UL
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT6_BASE 0x40201180UL
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT7_BASE 0x402011C0UL
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT0_BASE 0x40201200UL
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT1_BASE 0x40201240UL
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT2_BASE 0x40201280UL
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT3_BASE 0x402012C0UL
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT4_BASE 0x40201300UL
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT5_BASE 0x40201340UL
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT6_BASE 0x40201380UL
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT7_BASE 0x402013C0UL
|
||||
#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT0_BASE 0x40201400UL
|
||||
#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT1_BASE 0x40201440UL
|
||||
#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT2_BASE 0x40201480UL
|
||||
#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT3_BASE 0x402014C0UL
|
||||
#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT0_BASE 0x40201500UL
|
||||
#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT1_BASE 0x40201540UL
|
||||
#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT2_BASE 0x40201580UL
|
||||
#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT3_BASE 0x402015C0UL
|
||||
#define PERI_GR_PPU_RG_SMPU_BASE 0x40201600UL
|
||||
#define PERI_GR_PPU_RG_MPU_CM0P_BASE 0x40201640UL
|
||||
#define PERI_GR_PPU_RG_MPU_CRYPTO_BASE 0x40201680UL
|
||||
#define PERI_GR_PPU_RG_MPU_CM4_BASE 0x402016C0UL
|
||||
#define PERI_GR_PPU_RG_MPU_TC_BASE 0x40201700UL
|
||||
#define PERI_GR_PPU_SL_PERI_GR3_BASE 0x40300000UL
|
||||
#define PERI_GR_PPU_SL_HSIOM_BASE 0x40300040UL
|
||||
#define PERI_GR_PPU_SL_GPIO_BASE 0x40300080UL
|
||||
#define PERI_GR_PPU_SL_SMARTIO_BASE 0x403000C0UL
|
||||
#define PERI_GR_PPU_SL_UDB_BASE 0x40300100UL
|
||||
#define PERI_GR_PPU_SL_LPCOMP_BASE 0x40300140UL
|
||||
#define PERI_GR_PPU_SL_CSD_BASE 0x40300180UL
|
||||
#define PERI_GR_PPU_SL_TCPWM0_BASE 0x40300200UL
|
||||
#define PERI_GR_PPU_SL_TCPWM1_BASE 0x40300240UL
|
||||
#define PERI_GR_PPU_SL_LCD_BASE 0x40300280UL
|
||||
#define PERI_GR_PPU_SL_BLE_BASE 0x403002C0UL
|
||||
#define PERI_GR_PPU_SL_USBFS_BASE 0x40300300UL
|
||||
#define PERI_GR_PPU_SL_PERI_GR4_BASE 0x40400000UL
|
||||
#define PERI_GR_PPU_SL_SMIF_BASE 0x40400080UL
|
||||
#define PERI_GR_PPU_SL_PERI_GR6_BASE 0x40600000UL
|
||||
#define PERI_GR_PPU_SL_SCB0_BASE 0x40600040UL
|
||||
#define PERI_GR_PPU_SL_SCB1_BASE 0x40600080UL
|
||||
#define PERI_GR_PPU_SL_SCB2_BASE 0x406000C0UL
|
||||
#define PERI_GR_PPU_SL_SCB3_BASE 0x40600100UL
|
||||
#define PERI_GR_PPU_SL_SCB4_BASE 0x40600140UL
|
||||
#define PERI_GR_PPU_SL_SCB5_BASE 0x40600180UL
|
||||
#define PERI_GR_PPU_SL_SCB6_BASE 0x406001C0UL
|
||||
#define PERI_GR_PPU_SL_SCB7_BASE 0x40600200UL
|
||||
#define PERI_GR_PPU_SL_SCB8_BASE 0x40600240UL
|
||||
#define PERI_GR_PPU_SL_PERI_GR9_BASE 0x41000000UL
|
||||
#define PERI_GR_PPU_SL_PASS_BASE 0x41000040UL
|
||||
#define PERI_GR_PPU_SL_PERI_GR10_BASE 0x42A00000UL
|
||||
#define PERI_GR_PPU_SL_I2S_BASE 0x42A00040UL
|
||||
#define PERI_GR_PPU_SL_PDM_BASE 0x42A00080UL
|
||||
#define PERI ((PERI_Type*) PERI_BASE) /* 0x40010000 */
|
||||
#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40010000 */
|
||||
#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40010040 */
|
||||
#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40010080 */
|
||||
#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x400100C0 */
|
||||
#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40010100 */
|
||||
#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x40010180 */
|
||||
#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40010240 */
|
||||
#define PERI_GR10 ((PERI_GR_Type*) &PERI->GR[10]) /* 0x40010280 */
|
||||
#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40012000 */
|
||||
#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40012200 */
|
||||
#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40012400 */
|
||||
#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40012600 */
|
||||
#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40012800 */
|
||||
#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40012A00 */
|
||||
#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40012C00 */
|
||||
#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40012E00 */
|
||||
#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x40013000 */
|
||||
#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x40013200 */
|
||||
#define PERI_TR_GR10 ((PERI_TR_GR_Type*) &PERI->TR_GR[10]) /* 0x40013400 */
|
||||
#define PERI_TR_GR11 ((PERI_TR_GR_Type*) &PERI->TR_GR[11]) /* 0x40013600 */
|
||||
#define PERI_TR_GR12 ((PERI_TR_GR_Type*) &PERI->TR_GR[12]) /* 0x40013800 */
|
||||
#define PERI_TR_GR13 ((PERI_TR_GR_Type*) &PERI->TR_GR[13]) /* 0x40013A00 */
|
||||
#define PERI_TR_GR14 ((PERI_TR_GR_Type*) &PERI->TR_GR[14]) /* 0x40013C00 */
|
||||
#define PERI_PPU_PR0 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[0]) /* 0x40014000 */
|
||||
#define PERI_PPU_PR1 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[1]) /* 0x40014040 */
|
||||
#define PERI_PPU_PR2 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[2]) /* 0x40014080 */
|
||||
#define PERI_PPU_PR3 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[3]) /* 0x400140C0 */
|
||||
#define PERI_PPU_PR4 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[4]) /* 0x40014100 */
|
||||
#define PERI_PPU_PR5 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[5]) /* 0x40014140 */
|
||||
#define PERI_PPU_PR6 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[6]) /* 0x40014180 */
|
||||
#define PERI_PPU_PR7 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[7]) /* 0x400141C0 */
|
||||
#define PERI_PPU_PR8 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[8]) /* 0x40014200 */
|
||||
#define PERI_PPU_PR9 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[9]) /* 0x40014240 */
|
||||
#define PERI_PPU_PR10 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[10]) /* 0x40014280 */
|
||||
#define PERI_PPU_PR11 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[11]) /* 0x400142C0 */
|
||||
#define PERI_PPU_PR12 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[12]) /* 0x40014300 */
|
||||
#define PERI_PPU_PR13 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[13]) /* 0x40014340 */
|
||||
#define PERI_PPU_PR14 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[14]) /* 0x40014380 */
|
||||
#define PERI_PPU_PR15 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[15]) /* 0x400143C0 */
|
||||
#define PERI_PPU_GR0 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[0]) /* 0x40015000 */
|
||||
#define PERI_PPU_GR1 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[1]) /* 0x40015040 */
|
||||
#define PERI_PPU_GR2 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[2]) /* 0x40015080 */
|
||||
#define PERI_PPU_GR3 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[3]) /* 0x400150C0 */
|
||||
#define PERI_PPU_GR4 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[4]) /* 0x40015100 */
|
||||
#define PERI_PPU_GR6 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[6]) /* 0x40015180 */
|
||||
#define PERI_PPU_GR9 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[9]) /* 0x40015240 */
|
||||
#define PERI_PPU_GR10 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[10]) /* 0x40015280 */
|
||||
#define PERI_PPU_GR_MMIO0 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO0_BASE) /* 0x40015000 */
|
||||
#define PERI_PPU_GR_MMIO1 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO1_BASE) /* 0x40015040 */
|
||||
#define PERI_PPU_GR_MMIO2 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO2_BASE) /* 0x40015080 */
|
||||
#define PERI_PPU_GR_MMIO3 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO3_BASE) /* 0x400150C0 */
|
||||
#define PERI_PPU_GR_MMIO4 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO4_BASE) /* 0x40015100 */
|
||||
#define PERI_PPU_GR_MMIO6 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO6_BASE) /* 0x40015180 */
|
||||
#define PERI_PPU_GR_MMIO9 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO9_BASE) /* 0x40015240 */
|
||||
#define PERI_PPU_GR_MMIO10 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO10_BASE) /* 0x40015280 */
|
||||
#define PERI_GR_PPU_SL_PERI_GR1 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR1_BASE) /* 0x40100000 */
|
||||
#define PERI_GR_PPU_SL_CRYPTO ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_CRYPTO_BASE) /* 0x40100040 */
|
||||
#define PERI_GR_PPU_SL_PERI_GR2 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR2_BASE) /* 0x40200000 */
|
||||
#define PERI_GR_PPU_SL_CPUSS ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_CPUSS_BASE) /* 0x40200040 */
|
||||
#define PERI_GR_PPU_SL_FAULT ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_FAULT_BASE) /* 0x40200080 */
|
||||
#define PERI_GR_PPU_SL_IPC ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_IPC_BASE) /* 0x402000C0 */
|
||||
#define PERI_GR_PPU_SL_PROT ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PROT_BASE) /* 0x40200100 */
|
||||
#define PERI_GR_PPU_SL_FLASHC ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_FLASHC_BASE) /* 0x40200140 */
|
||||
#define PERI_GR_PPU_SL_SRSS ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SRSS_BASE) /* 0x40200180 */
|
||||
#define PERI_GR_PPU_SL_BACKUP ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_BACKUP_BASE) /* 0x402001C0 */
|
||||
#define PERI_GR_PPU_SL_DW0 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_DW0_BASE) /* 0x40200200 */
|
||||
#define PERI_GR_PPU_SL_DW1 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_DW1_BASE) /* 0x40200240 */
|
||||
#define PERI_GR_PPU_SL_EFUSE ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_EFUSE_BASE) /* 0x40200300 */
|
||||
#define PERI_GR_PPU_SL_PROFILE ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PROFILE_BASE) /* 0x40200340 */
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT0 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT0_BASE) /* 0x40201000 */
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT1 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT1_BASE) /* 0x40201040 */
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT2 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT2_BASE) /* 0x40201080 */
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT3 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT3_BASE) /* 0x402010C0 */
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT4 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT4_BASE) /* 0x40201100 */
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT5 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT5_BASE) /* 0x40201140 */
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT6 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT6_BASE) /* 0x40201180 */
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT7 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT7_BASE) /* 0x402011C0 */
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT0 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT0_BASE) /* 0x40201200 */
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT1 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT1_BASE) /* 0x40201240 */
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT2 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT2_BASE) /* 0x40201280 */
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT3 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT3_BASE) /* 0x402012C0 */
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT4 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT4_BASE) /* 0x40201300 */
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT5 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT5_BASE) /* 0x40201340 */
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT6 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT6_BASE) /* 0x40201380 */
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT7 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT7_BASE) /* 0x402013C0 */
|
||||
#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT0 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW0_DW_CH_STRUCT0_BASE) /* 0x40201400 */
|
||||
#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT1 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW0_DW_CH_STRUCT1_BASE) /* 0x40201440 */
|
||||
#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT2 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW0_DW_CH_STRUCT2_BASE) /* 0x40201480 */
|
||||
#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT3 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW0_DW_CH_STRUCT3_BASE) /* 0x402014C0 */
|
||||
#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT0 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW1_DW_CH_STRUCT0_BASE) /* 0x40201500 */
|
||||
#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT1 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW1_DW_CH_STRUCT1_BASE) /* 0x40201540 */
|
||||
#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT2 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW1_DW_CH_STRUCT2_BASE) /* 0x40201580 */
|
||||
#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT3 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW1_DW_CH_STRUCT3_BASE) /* 0x402015C0 */
|
||||
#define PERI_GR_PPU_RG_SMPU ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_SMPU_BASE) /* 0x40201600 */
|
||||
#define PERI_GR_PPU_RG_MPU_CM0P ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_MPU_CM0P_BASE) /* 0x40201640 */
|
||||
#define PERI_GR_PPU_RG_MPU_CRYPTO ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_MPU_CRYPTO_BASE) /* 0x40201680 */
|
||||
#define PERI_GR_PPU_RG_MPU_CM4 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_MPU_CM4_BASE) /* 0x402016C0 */
|
||||
#define PERI_GR_PPU_RG_MPU_TC ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_MPU_TC_BASE) /* 0x40201700 */
|
||||
#define PERI_GR_PPU_SL_PERI_GR3 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR3_BASE) /* 0x40300000 */
|
||||
#define PERI_GR_PPU_SL_HSIOM ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_HSIOM_BASE) /* 0x40300040 */
|
||||
#define PERI_GR_PPU_SL_GPIO ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_GPIO_BASE) /* 0x40300080 */
|
||||
#define PERI_GR_PPU_SL_SMARTIO ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SMARTIO_BASE) /* 0x403000C0 */
|
||||
#define PERI_GR_PPU_SL_UDB ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_UDB_BASE) /* 0x40300100 */
|
||||
#define PERI_GR_PPU_SL_LPCOMP ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_LPCOMP_BASE) /* 0x40300140 */
|
||||
#define PERI_GR_PPU_SL_CSD ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_CSD_BASE) /* 0x40300180 */
|
||||
#define PERI_GR_PPU_SL_TCPWM0 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_TCPWM0_BASE) /* 0x40300200 */
|
||||
#define PERI_GR_PPU_SL_TCPWM1 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_TCPWM1_BASE) /* 0x40300240 */
|
||||
#define PERI_GR_PPU_SL_LCD ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_LCD_BASE) /* 0x40300280 */
|
||||
#define PERI_GR_PPU_SL_BLE ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_BLE_BASE) /* 0x403002C0 */
|
||||
#define PERI_GR_PPU_SL_USBFS ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_USBFS_BASE) /* 0x40300300 */
|
||||
#define PERI_GR_PPU_SL_PERI_GR4 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR4_BASE) /* 0x40400000 */
|
||||
#define PERI_GR_PPU_SL_SMIF ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SMIF_BASE) /* 0x40400080 */
|
||||
#define PERI_GR_PPU_SL_PERI_GR6 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR6_BASE) /* 0x40600000 */
|
||||
#define PERI_GR_PPU_SL_SCB0 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB0_BASE) /* 0x40600040 */
|
||||
#define PERI_GR_PPU_SL_SCB1 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB1_BASE) /* 0x40600080 */
|
||||
#define PERI_GR_PPU_SL_SCB2 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB2_BASE) /* 0x406000C0 */
|
||||
#define PERI_GR_PPU_SL_SCB3 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB3_BASE) /* 0x40600100 */
|
||||
#define PERI_GR_PPU_SL_SCB4 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB4_BASE) /* 0x40600140 */
|
||||
#define PERI_GR_PPU_SL_SCB5 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB5_BASE) /* 0x40600180 */
|
||||
#define PERI_GR_PPU_SL_SCB6 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB6_BASE) /* 0x406001C0 */
|
||||
#define PERI_GR_PPU_SL_SCB7 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB7_BASE) /* 0x40600200 */
|
||||
#define PERI_GR_PPU_SL_SCB8 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB8_BASE) /* 0x40600240 */
|
||||
#define PERI_GR_PPU_SL_PERI_GR9 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR9_BASE) /* 0x41000000 */
|
||||
#define PERI_GR_PPU_SL_PASS ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PASS_BASE) /* 0x41000040 */
|
||||
#define PERI_GR_PPU_SL_PERI_GR10 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR10_BASE) /* 0x42A00000 */
|
||||
#define PERI_GR_PPU_SL_I2S ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_I2S_BASE) /* 0x42A00040 */
|
||||
#define PERI_GR_PPU_SL_PDM ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PDM_BASE) /* 0x42A00080 */
|
||||
|
||||
/*******************************************************************************
|
||||
* CPUSS
|
||||
*******************************************************************************/
|
||||
|
||||
#define CPUSS_BASE 0x40210000UL
|
||||
#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40210000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* FAULT
|
||||
*******************************************************************************/
|
||||
|
||||
#define FAULT_BASE 0x40220000UL
|
||||
#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40220000 */
|
||||
#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40220000 */
|
||||
#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40220100 */
|
||||
|
||||
/*******************************************************************************
|
||||
* IPC
|
||||
*******************************************************************************/
|
||||
|
||||
#define IPC_BASE 0x40230000UL
|
||||
#define IPC ((IPC_Type*) IPC_BASE) /* 0x40230000 */
|
||||
#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40230000 */
|
||||
#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40230020 */
|
||||
#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40230040 */
|
||||
#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40230060 */
|
||||
#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40230080 */
|
||||
#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402300A0 */
|
||||
#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402300C0 */
|
||||
#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402300E0 */
|
||||
#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40230100 */
|
||||
#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40230120 */
|
||||
#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40230140 */
|
||||
#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40230160 */
|
||||
#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40230180 */
|
||||
#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402301A0 */
|
||||
#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402301C0 */
|
||||
#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402301E0 */
|
||||
#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40231000 */
|
||||
#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40231020 */
|
||||
#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40231040 */
|
||||
#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40231060 */
|
||||
#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40231080 */
|
||||
#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402310A0 */
|
||||
#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402310C0 */
|
||||
#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402310E0 */
|
||||
#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40231100 */
|
||||
#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40231120 */
|
||||
#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40231140 */
|
||||
#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40231160 */
|
||||
#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40231180 */
|
||||
#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402311A0 */
|
||||
#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402311C0 */
|
||||
#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402311E0 */
|
||||
|
||||
/*******************************************************************************
|
||||
* PROT
|
||||
*******************************************************************************/
|
||||
|
||||
#define PROT_BASE 0x40240000UL
|
||||
#define PROT ((PROT_Type*) PROT_BASE) /* 0x40240000 */
|
||||
#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40242000 */
|
||||
#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40242040 */
|
||||
#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40242080 */
|
||||
#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402420C0 */
|
||||
#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40242100 */
|
||||
#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40242140 */
|
||||
#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40242180 */
|
||||
#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402421C0 */
|
||||
#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40242200 */
|
||||
#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40242240 */
|
||||
#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40242280 */
|
||||
#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402422C0 */
|
||||
#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40242300 */
|
||||
#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40242340 */
|
||||
#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40242380 */
|
||||
#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402423C0 */
|
||||
#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */
|
||||
#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */
|
||||
#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */
|
||||
#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */
|
||||
#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */
|
||||
#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */
|
||||
#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */
|
||||
#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */
|
||||
#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */
|
||||
#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */
|
||||
#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */
|
||||
#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */
|
||||
#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */
|
||||
#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */
|
||||
#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */
|
||||
#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */
|
||||
#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */
|
||||
#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40244000 */
|
||||
#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40244400 */
|
||||
#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40244800 */
|
||||
#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40244C00 */
|
||||
#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40245000 */
|
||||
#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40245400 */
|
||||
#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40245800 */
|
||||
#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40245C00 */
|
||||
#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40246000 */
|
||||
#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40246400 */
|
||||
#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40246800 */
|
||||
#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40246C00 */
|
||||
#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40247000 */
|
||||
#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40247400 */
|
||||
#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40247800 */
|
||||
#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40247C00 */
|
||||
|
||||
/*******************************************************************************
|
||||
* FLASHC
|
||||
*******************************************************************************/
|
||||
|
||||
#define FLASHC_BASE 0x40250000UL
|
||||
#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40250000 */
|
||||
#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4025F000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* SRSS
|
||||
*******************************************************************************/
|
||||
|
||||
#define SRSS_BASE 0x40260000UL
|
||||
#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */
|
||||
#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */
|
||||
#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */
|
||||
|
||||
/*******************************************************************************
|
||||
* BACKUP
|
||||
*******************************************************************************/
|
||||
|
||||
#define BACKUP_BASE 0x40270000UL
|
||||
#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* DW
|
||||
*******************************************************************************/
|
||||
|
||||
#define DW0_BASE 0x40280000UL
|
||||
#define DW1_BASE 0x40281000UL
|
||||
#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */
|
||||
#define DW1 ((DW_Type*) DW1_BASE) /* 0x40281000 */
|
||||
#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40280800 */
|
||||
#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40280820 */
|
||||
#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40280840 */
|
||||
#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x40280860 */
|
||||
#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40280880 */
|
||||
#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x402808A0 */
|
||||
#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x402808C0 */
|
||||
#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402808E0 */
|
||||
#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40280900 */
|
||||
#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40280920 */
|
||||
#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40280940 */
|
||||
#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x40280960 */
|
||||
#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40280980 */
|
||||
#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x402809A0 */
|
||||
#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x402809C0 */
|
||||
#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402809E0 */
|
||||
#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40281800 */
|
||||
#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40281820 */
|
||||
#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40281840 */
|
||||
#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x40281860 */
|
||||
#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40281880 */
|
||||
#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x402818A0 */
|
||||
#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x402818C0 */
|
||||
#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402818E0 */
|
||||
#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40281900 */
|
||||
#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40281920 */
|
||||
#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40281940 */
|
||||
#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x40281960 */
|
||||
#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40281980 */
|
||||
#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x402819A0 */
|
||||
#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x402819C0 */
|
||||
#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402819E0 */
|
||||
|
||||
/*******************************************************************************
|
||||
* EFUSE
|
||||
*******************************************************************************/
|
||||
|
||||
#define EFUSE_BASE 0x402C0000UL
|
||||
#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* PROFILE
|
||||
*******************************************************************************/
|
||||
|
||||
#define PROFILE_BASE 0x402D0000UL
|
||||
#define PROFILE ((PROFILE_Type*) PROFILE_BASE) /* 0x402D0000 */
|
||||
#define PROFILE_CNT_STRUCT0 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[0]) /* 0x402D0800 */
|
||||
#define PROFILE_CNT_STRUCT1 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[1]) /* 0x402D0810 */
|
||||
#define PROFILE_CNT_STRUCT2 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[2]) /* 0x402D0820 */
|
||||
#define PROFILE_CNT_STRUCT3 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[3]) /* 0x402D0830 */
|
||||
#define PROFILE_CNT_STRUCT4 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[4]) /* 0x402D0840 */
|
||||
#define PROFILE_CNT_STRUCT5 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[5]) /* 0x402D0850 */
|
||||
#define PROFILE_CNT_STRUCT6 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[6]) /* 0x402D0860 */
|
||||
#define PROFILE_CNT_STRUCT7 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[7]) /* 0x402D0870 */
|
||||
|
||||
/*******************************************************************************
|
||||
* HSIOM
|
||||
*******************************************************************************/
|
||||
|
||||
#define HSIOM_BASE 0x40310000UL
|
||||
#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40310000 */
|
||||
#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40310000 */
|
||||
#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40310010 */
|
||||
#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40310020 */
|
||||
#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40310030 */
|
||||
#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40310040 */
|
||||
#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40310050 */
|
||||
#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40310060 */
|
||||
#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40310070 */
|
||||
#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40310080 */
|
||||
#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40310090 */
|
||||
#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403100A0 */
|
||||
#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403100B0 */
|
||||
#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403100C0 */
|
||||
#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403100D0 */
|
||||
#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403100E0 */
|
||||
|
||||
/*******************************************************************************
|
||||
* GPIO
|
||||
*******************************************************************************/
|
||||
|
||||
#define GPIO_BASE 0x40320000UL
|
||||
#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40320000 */
|
||||
#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40320000 */
|
||||
#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40320080 */
|
||||
#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40320100 */
|
||||
#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40320180 */
|
||||
#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40320200 */
|
||||
#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40320280 */
|
||||
#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40320300 */
|
||||
#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40320380 */
|
||||
#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40320400 */
|
||||
#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40320480 */
|
||||
#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40320500 */
|
||||
#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40320580 */
|
||||
#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40320600 */
|
||||
#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40320680 */
|
||||
#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40320700 */
|
||||
|
||||
/*******************************************************************************
|
||||
* SMARTIO
|
||||
*******************************************************************************/
|
||||
|
||||
#define SMARTIO_BASE 0x40330000UL
|
||||
#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40330000 */
|
||||
#define SMARTIO_PRT8 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[8]) /* 0x40330800 */
|
||||
#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40330900 */
|
||||
|
||||
/*******************************************************************************
|
||||
* LPCOMP
|
||||
*******************************************************************************/
|
||||
|
||||
#define LPCOMP_BASE 0x40350000UL
|
||||
#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* CSD
|
||||
*******************************************************************************/
|
||||
|
||||
#define CSD0_BASE 0x40360000UL
|
||||
#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* TCPWM
|
||||
*******************************************************************************/
|
||||
|
||||
#define TCPWM0_BASE 0x40380000UL
|
||||
#define TCPWM1_BASE 0x40390000UL
|
||||
#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */
|
||||
#define TCPWM1 ((TCPWM_Type*) TCPWM1_BASE) /* 0x40390000 */
|
||||
#define TCPWM0_CNT0 ((TCPWM_CNT_Type*) &TCPWM0->CNT[0]) /* 0x40380100 */
|
||||
#define TCPWM0_CNT1 ((TCPWM_CNT_Type*) &TCPWM0->CNT[1]) /* 0x40380140 */
|
||||
#define TCPWM0_CNT2 ((TCPWM_CNT_Type*) &TCPWM0->CNT[2]) /* 0x40380180 */
|
||||
#define TCPWM0_CNT3 ((TCPWM_CNT_Type*) &TCPWM0->CNT[3]) /* 0x403801C0 */
|
||||
#define TCPWM0_CNT4 ((TCPWM_CNT_Type*) &TCPWM0->CNT[4]) /* 0x40380200 */
|
||||
#define TCPWM0_CNT5 ((TCPWM_CNT_Type*) &TCPWM0->CNT[5]) /* 0x40380240 */
|
||||
#define TCPWM0_CNT6 ((TCPWM_CNT_Type*) &TCPWM0->CNT[6]) /* 0x40380280 */
|
||||
#define TCPWM0_CNT7 ((TCPWM_CNT_Type*) &TCPWM0->CNT[7]) /* 0x403802C0 */
|
||||
#define TCPWM1_CNT0 ((TCPWM_CNT_Type*) &TCPWM1->CNT[0]) /* 0x40390100 */
|
||||
#define TCPWM1_CNT1 ((TCPWM_CNT_Type*) &TCPWM1->CNT[1]) /* 0x40390140 */
|
||||
#define TCPWM1_CNT2 ((TCPWM_CNT_Type*) &TCPWM1->CNT[2]) /* 0x40390180 */
|
||||
#define TCPWM1_CNT3 ((TCPWM_CNT_Type*) &TCPWM1->CNT[3]) /* 0x403901C0 */
|
||||
#define TCPWM1_CNT4 ((TCPWM_CNT_Type*) &TCPWM1->CNT[4]) /* 0x40390200 */
|
||||
#define TCPWM1_CNT5 ((TCPWM_CNT_Type*) &TCPWM1->CNT[5]) /* 0x40390240 */
|
||||
#define TCPWM1_CNT6 ((TCPWM_CNT_Type*) &TCPWM1->CNT[6]) /* 0x40390280 */
|
||||
#define TCPWM1_CNT7 ((TCPWM_CNT_Type*) &TCPWM1->CNT[7]) /* 0x403902C0 */
|
||||
#define TCPWM1_CNT8 ((TCPWM_CNT_Type*) &TCPWM1->CNT[8]) /* 0x40390300 */
|
||||
#define TCPWM1_CNT9 ((TCPWM_CNT_Type*) &TCPWM1->CNT[9]) /* 0x40390340 */
|
||||
#define TCPWM1_CNT10 ((TCPWM_CNT_Type*) &TCPWM1->CNT[10]) /* 0x40390380 */
|
||||
#define TCPWM1_CNT11 ((TCPWM_CNT_Type*) &TCPWM1->CNT[11]) /* 0x403903C0 */
|
||||
#define TCPWM1_CNT12 ((TCPWM_CNT_Type*) &TCPWM1->CNT[12]) /* 0x40390400 */
|
||||
#define TCPWM1_CNT13 ((TCPWM_CNT_Type*) &TCPWM1->CNT[13]) /* 0x40390440 */
|
||||
#define TCPWM1_CNT14 ((TCPWM_CNT_Type*) &TCPWM1->CNT[14]) /* 0x40390480 */
|
||||
#define TCPWM1_CNT15 ((TCPWM_CNT_Type*) &TCPWM1->CNT[15]) /* 0x403904C0 */
|
||||
#define TCPWM1_CNT16 ((TCPWM_CNT_Type*) &TCPWM1->CNT[16]) /* 0x40390500 */
|
||||
#define TCPWM1_CNT17 ((TCPWM_CNT_Type*) &TCPWM1->CNT[17]) /* 0x40390540 */
|
||||
#define TCPWM1_CNT18 ((TCPWM_CNT_Type*) &TCPWM1->CNT[18]) /* 0x40390580 */
|
||||
#define TCPWM1_CNT19 ((TCPWM_CNT_Type*) &TCPWM1->CNT[19]) /* 0x403905C0 */
|
||||
#define TCPWM1_CNT20 ((TCPWM_CNT_Type*) &TCPWM1->CNT[20]) /* 0x40390600 */
|
||||
#define TCPWM1_CNT21 ((TCPWM_CNT_Type*) &TCPWM1->CNT[21]) /* 0x40390640 */
|
||||
#define TCPWM1_CNT22 ((TCPWM_CNT_Type*) &TCPWM1->CNT[22]) /* 0x40390680 */
|
||||
#define TCPWM1_CNT23 ((TCPWM_CNT_Type*) &TCPWM1->CNT[23]) /* 0x403906C0 */
|
||||
|
||||
/*******************************************************************************
|
||||
* LCD
|
||||
*******************************************************************************/
|
||||
|
||||
#define LCD0_BASE 0x403B0000UL
|
||||
#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* USBFS
|
||||
*******************************************************************************/
|
||||
|
||||
#define USBFS0_BASE 0x403F0000UL
|
||||
#define USBFS0 ((USBFS_Type*) USBFS0_BASE) /* 0x403F0000 */
|
||||
#define USBFS0_USBDEV ((USBFS_USBDEV_Type*) &USBFS0->USBDEV) /* 0x403F0000 */
|
||||
#define USBFS0_USBLPM ((USBFS_USBLPM_Type*) &USBFS0->USBLPM) /* 0x403F2000 */
|
||||
#define USBFS0_USBHOST ((USBFS_USBHOST_Type*) &USBFS0->USBHOST) /* 0x403F4000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* SMIF
|
||||
*******************************************************************************/
|
||||
|
||||
#define SMIF0_BASE 0x40420000UL
|
||||
#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */
|
||||
#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */
|
||||
#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */
|
||||
#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */
|
||||
#define SMIF0_DEVICE3 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[3]) /* 0x40420980 */
|
||||
|
||||
/*******************************************************************************
|
||||
* SCB
|
||||
*******************************************************************************/
|
||||
|
||||
#define SCB0_BASE 0x40610000UL
|
||||
#define SCB1_BASE 0x40620000UL
|
||||
#define SCB2_BASE 0x40630000UL
|
||||
#define SCB3_BASE 0x40640000UL
|
||||
#define SCB4_BASE 0x40650000UL
|
||||
#define SCB5_BASE 0x40660000UL
|
||||
#define SCB6_BASE 0x40670000UL
|
||||
#define SCB7_BASE 0x40680000UL
|
||||
#define SCB8_BASE 0x40690000UL
|
||||
#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40610000 */
|
||||
#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40620000 */
|
||||
#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40630000 */
|
||||
#define SCB3 ((CySCB_Type*) SCB3_BASE) /* 0x40640000 */
|
||||
#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40650000 */
|
||||
#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40660000 */
|
||||
#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40670000 */
|
||||
#define SCB7 ((CySCB_Type*) SCB7_BASE) /* 0x40680000 */
|
||||
#define SCB8 ((CySCB_Type*) SCB8_BASE) /* 0x40690000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* CTDAC
|
||||
*******************************************************************************/
|
||||
|
||||
#define CTDAC0_BASE 0x41140000UL
|
||||
#define CTDAC0 ((CTDAC_Type*) CTDAC0_BASE) /* 0x41140000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* SAR
|
||||
*******************************************************************************/
|
||||
|
||||
#define SAR_BASE 0x411D0000UL
|
||||
#define SAR ((SAR_Type*) SAR_BASE) /* 0x411D0000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* PASS
|
||||
*******************************************************************************/
|
||||
|
||||
#define PASS_BASE 0x411F0000UL
|
||||
#define PASS ((PASS_Type*) PASS_BASE) /* 0x411F0000 */
|
||||
#define PASS_AREF ((PASS_AREF_Type*) &PASS->AREF) /* 0x411F0E00 */
|
||||
|
||||
/*******************************************************************************
|
||||
* I2S
|
||||
*******************************************************************************/
|
||||
|
||||
#define I2S0_BASE 0x42A10000UL
|
||||
#define I2S0 ((I2S_Type*) I2S0_BASE) /* 0x42A10000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* PDM
|
||||
*******************************************************************************/
|
||||
|
||||
#define PDM0_BASE 0x42A20000UL
|
||||
#define PDM0 ((PDM_Type*) PDM0_BASE) /* 0x42A20000 */
|
||||
|
||||
|
||||
/* Backward compabitility definitions */
|
||||
#define I2S I2S0
|
||||
#define PDM PDM0
|
||||
|
||||
/** \} CY8C6136BZI-F14 */
|
||||
|
||||
#endif /* _CY8C6136BZI_F14_H_ */
|
||||
|
||||
|
||||
/* [] END OF FILE */
|
||||
File diff suppressed because it is too large
Load diff
|
|
@ -1,943 +0,0 @@
|
|||
/***************************************************************************//**
|
||||
* \file cy8c6136fdi_f42.h
|
||||
*
|
||||
* \brief
|
||||
* CY8C6136FDI-F42 device header
|
||||
*
|
||||
* \note
|
||||
* Generator version: 1.3.0.1146
|
||||
* Database revision: rev#1050929
|
||||
*
|
||||
********************************************************************************
|
||||
* \copyright
|
||||
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
|
||||
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _CY8C6136FDI_F42_H_
|
||||
#define _CY8C6136FDI_F42_H_
|
||||
|
||||
/**
|
||||
* \addtogroup group_device CY8C6136FDI-F42
|
||||
* \{
|
||||
*/
|
||||
|
||||
/**
|
||||
* \addtogroup Configuration_of_CMSIS
|
||||
* \{
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Interrupt Number Definition
|
||||
*******************************************************************************/
|
||||
|
||||
typedef enum {
|
||||
/* ARM Cortex-M4 Core Interrupt Numbers */
|
||||
Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */
|
||||
NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */
|
||||
HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */
|
||||
MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */
|
||||
BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */
|
||||
UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
|
||||
SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */
|
||||
DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */
|
||||
PendSV_IRQn = -2, /*!< -2 Pendable request for system service */
|
||||
SysTick_IRQn = -1, /*!< -1 System Tick Timer */
|
||||
/* CY8C6136FDI-F42 Peripheral Interrupt Numbers */
|
||||
ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */
|
||||
ioss_interrupts_gpio_1_IRQn = 1, /*!< 1 [DeepSleep] GPIO Port Interrupt #1 */
|
||||
ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */
|
||||
ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */
|
||||
ioss_interrupts_gpio_4_IRQn = 4, /*!< 4 [DeepSleep] GPIO Port Interrupt #4 */
|
||||
ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */
|
||||
ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */
|
||||
ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */
|
||||
ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */
|
||||
ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */
|
||||
ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */
|
||||
ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */
|
||||
ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */
|
||||
ioss_interrupts_gpio_13_IRQn = 13, /*!< 13 [DeepSleep] GPIO Port Interrupt #13 */
|
||||
ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */
|
||||
ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */
|
||||
ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */
|
||||
lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */
|
||||
scb_8_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #8 (DeepSleep capable) */
|
||||
srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */
|
||||
srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */
|
||||
srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */
|
||||
srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */
|
||||
pass_interrupt_ctbs_IRQn = 23, /*!< 23 [DeepSleep] CTBm Interrupt (all CTBms) */
|
||||
bless_interrupt_IRQn = 24, /*!< 24 [DeepSleep] Bluetooth Radio interrupt */
|
||||
cpuss_interrupts_ipc_0_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */
|
||||
cpuss_interrupts_ipc_1_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */
|
||||
cpuss_interrupts_ipc_2_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */
|
||||
cpuss_interrupts_ipc_3_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */
|
||||
cpuss_interrupts_ipc_4_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */
|
||||
cpuss_interrupts_ipc_5_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */
|
||||
cpuss_interrupts_ipc_6_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */
|
||||
cpuss_interrupts_ipc_7_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */
|
||||
cpuss_interrupts_ipc_8_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */
|
||||
cpuss_interrupts_ipc_9_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */
|
||||
cpuss_interrupts_ipc_10_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */
|
||||
cpuss_interrupts_ipc_11_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */
|
||||
cpuss_interrupts_ipc_12_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */
|
||||
cpuss_interrupts_ipc_13_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */
|
||||
cpuss_interrupts_ipc_14_IRQn = 39, /*!< 39 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */
|
||||
cpuss_interrupts_ipc_15_IRQn = 40, /*!< 40 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */
|
||||
scb_0_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #0 */
|
||||
scb_1_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #1 */
|
||||
scb_2_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #2 */
|
||||
scb_3_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #3 */
|
||||
scb_4_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #4 */
|
||||
scb_5_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #5 */
|
||||
scb_6_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #6 */
|
||||
scb_7_interrupt_IRQn = 48, /*!< 48 [Active] Serial Communication Block #7 */
|
||||
csd_interrupt_IRQn = 49, /*!< 49 [Active] CSD (Capsense) interrupt */
|
||||
cpuss_interrupts_dw0_0_IRQn = 50, /*!< 50 [Active] CPUSS DataWire #0, Channel #0 */
|
||||
cpuss_interrupts_dw0_1_IRQn = 51, /*!< 51 [Active] CPUSS DataWire #0, Channel #1 */
|
||||
cpuss_interrupts_dw0_2_IRQn = 52, /*!< 52 [Active] CPUSS DataWire #0, Channel #2 */
|
||||
cpuss_interrupts_dw0_3_IRQn = 53, /*!< 53 [Active] CPUSS DataWire #0, Channel #3 */
|
||||
cpuss_interrupts_dw0_4_IRQn = 54, /*!< 54 [Active] CPUSS DataWire #0, Channel #4 */
|
||||
cpuss_interrupts_dw0_5_IRQn = 55, /*!< 55 [Active] CPUSS DataWire #0, Channel #5 */
|
||||
cpuss_interrupts_dw0_6_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #6 */
|
||||
cpuss_interrupts_dw0_7_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #7 */
|
||||
cpuss_interrupts_dw0_8_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #8 */
|
||||
cpuss_interrupts_dw0_9_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #9 */
|
||||
cpuss_interrupts_dw0_10_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #10 */
|
||||
cpuss_interrupts_dw0_11_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #11 */
|
||||
cpuss_interrupts_dw0_12_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #12 */
|
||||
cpuss_interrupts_dw0_13_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #13 */
|
||||
cpuss_interrupts_dw0_14_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #14 */
|
||||
cpuss_interrupts_dw0_15_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #15 */
|
||||
cpuss_interrupts_dw1_0_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #1, Channel #0 */
|
||||
cpuss_interrupts_dw1_1_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #1, Channel #1 */
|
||||
cpuss_interrupts_dw1_2_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #1, Channel #2 */
|
||||
cpuss_interrupts_dw1_3_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #1, Channel #3 */
|
||||
cpuss_interrupts_dw1_4_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #1, Channel #4 */
|
||||
cpuss_interrupts_dw1_5_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #1, Channel #5 */
|
||||
cpuss_interrupts_dw1_6_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #1, Channel #6 */
|
||||
cpuss_interrupts_dw1_7_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #1, Channel #7 */
|
||||
cpuss_interrupts_dw1_8_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #1, Channel #8 */
|
||||
cpuss_interrupts_dw1_9_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #1, Channel #9 */
|
||||
cpuss_interrupts_dw1_10_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #1, Channel #10 */
|
||||
cpuss_interrupts_dw1_11_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #1, Channel #11 */
|
||||
cpuss_interrupts_dw1_12_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #1, Channel #12 */
|
||||
cpuss_interrupts_dw1_13_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #1, Channel #13 */
|
||||
cpuss_interrupts_dw1_14_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #1, Channel #14 */
|
||||
cpuss_interrupts_dw1_15_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #1, Channel #15 */
|
||||
cpuss_interrupts_fault_0_IRQn = 82, /*!< 82 [Active] CPUSS Fault Structure Interrupt #0 */
|
||||
cpuss_interrupts_fault_1_IRQn = 83, /*!< 83 [Active] CPUSS Fault Structure Interrupt #1 */
|
||||
cpuss_interrupt_crypto_IRQn = 84, /*!< 84 [Active] CRYPTO Accelerator Interrupt */
|
||||
cpuss_interrupt_fm_IRQn = 85, /*!< 85 [Active] FLASH Macro Interrupt */
|
||||
cpuss_interrupts_cm0_cti_0_IRQn = 86, /*!< 86 [Active] CM0+ CTI #0 */
|
||||
cpuss_interrupts_cm0_cti_1_IRQn = 87, /*!< 87 [Active] CM0+ CTI #1 */
|
||||
cpuss_interrupts_cm4_cti_0_IRQn = 88, /*!< 88 [Active] CM4 CTI #0 */
|
||||
cpuss_interrupts_cm4_cti_1_IRQn = 89, /*!< 89 [Active] CM4 CTI #1 */
|
||||
tcpwm_0_interrupts_0_IRQn = 90, /*!< 90 [Active] TCPWM #0, Counter #0 */
|
||||
tcpwm_0_interrupts_1_IRQn = 91, /*!< 91 [Active] TCPWM #0, Counter #1 */
|
||||
tcpwm_0_interrupts_2_IRQn = 92, /*!< 92 [Active] TCPWM #0, Counter #2 */
|
||||
tcpwm_0_interrupts_3_IRQn = 93, /*!< 93 [Active] TCPWM #0, Counter #3 */
|
||||
tcpwm_0_interrupts_4_IRQn = 94, /*!< 94 [Active] TCPWM #0, Counter #4 */
|
||||
tcpwm_0_interrupts_5_IRQn = 95, /*!< 95 [Active] TCPWM #0, Counter #5 */
|
||||
tcpwm_0_interrupts_6_IRQn = 96, /*!< 96 [Active] TCPWM #0, Counter #6 */
|
||||
tcpwm_0_interrupts_7_IRQn = 97, /*!< 97 [Active] TCPWM #0, Counter #7 */
|
||||
tcpwm_1_interrupts_0_IRQn = 98, /*!< 98 [Active] TCPWM #1, Counter #0 */
|
||||
tcpwm_1_interrupts_1_IRQn = 99, /*!< 99 [Active] TCPWM #1, Counter #1 */
|
||||
tcpwm_1_interrupts_2_IRQn = 100, /*!< 100 [Active] TCPWM #1, Counter #2 */
|
||||
tcpwm_1_interrupts_3_IRQn = 101, /*!< 101 [Active] TCPWM #1, Counter #3 */
|
||||
tcpwm_1_interrupts_4_IRQn = 102, /*!< 102 [Active] TCPWM #1, Counter #4 */
|
||||
tcpwm_1_interrupts_5_IRQn = 103, /*!< 103 [Active] TCPWM #1, Counter #5 */
|
||||
tcpwm_1_interrupts_6_IRQn = 104, /*!< 104 [Active] TCPWM #1, Counter #6 */
|
||||
tcpwm_1_interrupts_7_IRQn = 105, /*!< 105 [Active] TCPWM #1, Counter #7 */
|
||||
tcpwm_1_interrupts_8_IRQn = 106, /*!< 106 [Active] TCPWM #1, Counter #8 */
|
||||
tcpwm_1_interrupts_9_IRQn = 107, /*!< 107 [Active] TCPWM #1, Counter #9 */
|
||||
tcpwm_1_interrupts_10_IRQn = 108, /*!< 108 [Active] TCPWM #1, Counter #10 */
|
||||
tcpwm_1_interrupts_11_IRQn = 109, /*!< 109 [Active] TCPWM #1, Counter #11 */
|
||||
tcpwm_1_interrupts_12_IRQn = 110, /*!< 110 [Active] TCPWM #1, Counter #12 */
|
||||
tcpwm_1_interrupts_13_IRQn = 111, /*!< 111 [Active] TCPWM #1, Counter #13 */
|
||||
tcpwm_1_interrupts_14_IRQn = 112, /*!< 112 [Active] TCPWM #1, Counter #14 */
|
||||
tcpwm_1_interrupts_15_IRQn = 113, /*!< 113 [Active] TCPWM #1, Counter #15 */
|
||||
tcpwm_1_interrupts_16_IRQn = 114, /*!< 114 [Active] TCPWM #1, Counter #16 */
|
||||
tcpwm_1_interrupts_17_IRQn = 115, /*!< 115 [Active] TCPWM #1, Counter #17 */
|
||||
tcpwm_1_interrupts_18_IRQn = 116, /*!< 116 [Active] TCPWM #1, Counter #18 */
|
||||
tcpwm_1_interrupts_19_IRQn = 117, /*!< 117 [Active] TCPWM #1, Counter #19 */
|
||||
tcpwm_1_interrupts_20_IRQn = 118, /*!< 118 [Active] TCPWM #1, Counter #20 */
|
||||
tcpwm_1_interrupts_21_IRQn = 119, /*!< 119 [Active] TCPWM #1, Counter #21 */
|
||||
tcpwm_1_interrupts_22_IRQn = 120, /*!< 120 [Active] TCPWM #1, Counter #22 */
|
||||
tcpwm_1_interrupts_23_IRQn = 121, /*!< 121 [Active] TCPWM #1, Counter #23 */
|
||||
udb_interrupts_0_IRQn = 122, /*!< 122 [Active] UDB Interrupt #0 */
|
||||
udb_interrupts_1_IRQn = 123, /*!< 123 [Active] UDB Interrupt #1 */
|
||||
udb_interrupts_2_IRQn = 124, /*!< 124 [Active] UDB Interrupt #2 */
|
||||
udb_interrupts_3_IRQn = 125, /*!< 125 [Active] UDB Interrupt #3 */
|
||||
udb_interrupts_4_IRQn = 126, /*!< 126 [Active] UDB Interrupt #4 */
|
||||
udb_interrupts_5_IRQn = 127, /*!< 127 [Active] UDB Interrupt #5 */
|
||||
udb_interrupts_6_IRQn = 128, /*!< 128 [Active] UDB Interrupt #6 */
|
||||
udb_interrupts_7_IRQn = 129, /*!< 129 [Active] UDB Interrupt #7 */
|
||||
udb_interrupts_8_IRQn = 130, /*!< 130 [Active] UDB Interrupt #8 */
|
||||
udb_interrupts_9_IRQn = 131, /*!< 131 [Active] UDB Interrupt #9 */
|
||||
udb_interrupts_10_IRQn = 132, /*!< 132 [Active] UDB Interrupt #10 */
|
||||
udb_interrupts_11_IRQn = 133, /*!< 133 [Active] UDB Interrupt #11 */
|
||||
udb_interrupts_12_IRQn = 134, /*!< 134 [Active] UDB Interrupt #12 */
|
||||
udb_interrupts_13_IRQn = 135, /*!< 135 [Active] UDB Interrupt #13 */
|
||||
udb_interrupts_14_IRQn = 136, /*!< 136 [Active] UDB Interrupt #14 */
|
||||
udb_interrupts_15_IRQn = 137, /*!< 137 [Active] UDB Interrupt #15 */
|
||||
pass_interrupt_sar_IRQn = 138, /*!< 138 [Active] SAR ADC interrupt */
|
||||
audioss_interrupt_i2s_IRQn = 139, /*!< 139 [Active] I2S Audio interrupt */
|
||||
audioss_interrupt_pdm_IRQn = 140, /*!< 140 [Active] PDM/PCM Audio interrupt */
|
||||
profile_interrupt_IRQn = 141, /*!< 141 [Active] Energy Profiler interrupt */
|
||||
smif_interrupt_IRQn = 142, /*!< 142 [Active] Serial Memory Interface interrupt */
|
||||
usb_interrupt_hi_IRQn = 143, /*!< 143 [Active] USB Interrupt */
|
||||
usb_interrupt_med_IRQn = 144, /*!< 144 [Active] USB Interrupt */
|
||||
usb_interrupt_lo_IRQn = 145, /*!< 145 [Active] USB Interrupt */
|
||||
pass_interrupt_dacs_IRQn = 146, /*!< 146 [Active] Consolidated interrrupt for all DACs */
|
||||
unconnected_IRQn = 240 /*!< 240 Unconnected */
|
||||
} IRQn_Type;
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Processor and Core Peripheral Section
|
||||
*******************************************************************************/
|
||||
|
||||
/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */
|
||||
#define __CM4_REV 0x0001U /*!< CM4 Core Revision */
|
||||
#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
|
||||
#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */
|
||||
#define __MPU_PRESENT 1 /*!< MPU present or not */
|
||||
#define __FPU_PRESENT 1 /*!< FPU present or not */
|
||||
#define __CM0P_PRESENT 0 /*!< CM0P present or not */
|
||||
|
||||
/** \} Configuration_of_CMSIS */
|
||||
|
||||
/* Memory Blocks */
|
||||
#define CY_ROM_BASE 0x00000000UL
|
||||
#define CY_ROM_SIZE 0x00020000UL
|
||||
#define CY_SRAM0_BASE 0x08000000UL
|
||||
#define CY_SRAM0_SIZE 0x00020000UL
|
||||
#define CY_FLASH_BASE 0x10000000UL
|
||||
#define CY_FLASH_SIZE 0x00080000UL
|
||||
#define CY_EM_EEPROM_BASE 0x14000000UL
|
||||
#define CY_EM_EEPROM_SIZE 0x00008000UL
|
||||
#define CY_XIP_BASE 0x18000000UL
|
||||
#define CY_XIP_SIZE 0x08000000UL
|
||||
#define CY_SFLASH_BASE 0x16000000UL
|
||||
#define CY_SFLASH_SIZE 0x00008000UL
|
||||
#define CY_EFUSE_BASE 0x402C0800UL
|
||||
#define CY_EFUSE_SIZE 0x00000200UL
|
||||
|
||||
#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */
|
||||
#include "system_psoc6.h" /*!< PSoC 6 System */
|
||||
|
||||
/* IP List */
|
||||
#define CY_IP_MXTCPWM 1u
|
||||
#define CY_IP_MXTCPWM_INSTANCES 2u
|
||||
#define CY_IP_MXTCPWM_VERSION 1u
|
||||
#define CY_IP_MXCSDV2 1u
|
||||
#define CY_IP_MXCSDV2_INSTANCES 1u
|
||||
#define CY_IP_MXCSDV2_VERSION 1u
|
||||
#define CY_IP_MXLCD 1u
|
||||
#define CY_IP_MXLCD_INSTANCES 1u
|
||||
#define CY_IP_MXLCD_VERSION 1u
|
||||
#define CY_IP_MXS40SRSS 1u
|
||||
#define CY_IP_MXS40SRSS_INSTANCES 1u
|
||||
#define CY_IP_MXS40SRSS_VERSION 1u
|
||||
#define CY_IP_MXS40SRSS_RTC 1u
|
||||
#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u
|
||||
#define CY_IP_MXS40SRSS_RTC_VERSION 1u
|
||||
#define CY_IP_MXS40SRSS_MCWDT 1u
|
||||
#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u
|
||||
#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u
|
||||
#define CY_IP_MXSCB 1u
|
||||
#define CY_IP_MXSCB_INSTANCES 9u
|
||||
#define CY_IP_MXSCB_VERSION 1u
|
||||
#define CY_IP_MXPERI 1u
|
||||
#define CY_IP_MXPERI_INSTANCES 1u
|
||||
#define CY_IP_MXPERI_VERSION 1u
|
||||
#define CY_IP_MXPERI_TR 1u
|
||||
#define CY_IP_MXPERI_TR_INSTANCES 1u
|
||||
#define CY_IP_MXPERI_TR_VERSION 1u
|
||||
#define CY_IP_M4CPUSS 1u
|
||||
#define CY_IP_M4CPUSS_INSTANCES 1u
|
||||
#define CY_IP_M4CPUSS_VERSION 1u
|
||||
#define CY_IP_M4CPUSS_DMA 1u
|
||||
#define CY_IP_M4CPUSS_DMA_INSTANCES 2u
|
||||
#define CY_IP_M4CPUSS_DMA_VERSION 1u
|
||||
#define CY_IP_MXCRYPTO 1u
|
||||
#define CY_IP_MXCRYPTO_INSTANCES 1u
|
||||
#define CY_IP_MXCRYPTO_VERSION 1u
|
||||
#define CY_IP_MXAUDIOSS 1u
|
||||
#define CY_IP_MXAUDIOSS_INSTANCES 1u
|
||||
#define CY_IP_MXAUDIOSS_VERSION 1u
|
||||
#define CY_IP_MXLPCOMP 1u
|
||||
#define CY_IP_MXLPCOMP_INSTANCES 1u
|
||||
#define CY_IP_MXLPCOMP_VERSION 1u
|
||||
#define CY_IP_MXS40PASS 1u
|
||||
#define CY_IP_MXS40PASS_INSTANCES 1u
|
||||
#define CY_IP_MXS40PASS_VERSION 1u
|
||||
#define CY_IP_MXS40PASS_SAR 1u
|
||||
#define CY_IP_MXS40PASS_SAR_INSTANCES 16u
|
||||
#define CY_IP_MXS40PASS_SAR_VERSION 1u
|
||||
#define CY_IP_MXS40PASS_CTDAC 1u
|
||||
#define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u
|
||||
#define CY_IP_MXS40PASS_CTDAC_VERSION 1u
|
||||
#define CY_IP_MXSMIF 1u
|
||||
#define CY_IP_MXSMIF_INSTANCES 1u
|
||||
#define CY_IP_MXSMIF_VERSION 1u
|
||||
#define CY_IP_MXUSBFS 1u
|
||||
#define CY_IP_MXUSBFS_INSTANCES 1u
|
||||
#define CY_IP_MXUSBFS_VERSION 1u
|
||||
#define CY_IP_MXS40IOSS 1u
|
||||
#define CY_IP_MXS40IOSS_INSTANCES 1u
|
||||
#define CY_IP_MXS40IOSS_VERSION 1u
|
||||
#define CY_IP_MXEFUSE 1u
|
||||
#define CY_IP_MXEFUSE_INSTANCES 1u
|
||||
#define CY_IP_MXEFUSE_VERSION 1u
|
||||
#define CY_IP_MXPROFILE 1u
|
||||
#define CY_IP_MXPROFILE_INSTANCES 1u
|
||||
#define CY_IP_MXPROFILE_VERSION 1u
|
||||
|
||||
#include "psoc6able2_config.h"
|
||||
#include "gpio_psoc6able2_80_wlcsp.h"
|
||||
|
||||
#define CY_DEVICE_PSOC6ABLE2
|
||||
#define CY_SILICON_ID 0xE2352100UL
|
||||
#define CY_HF_CLK_MAX_FREQ 150000000UL
|
||||
|
||||
#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL
|
||||
|
||||
/*******************************************************************************
|
||||
* SFLASH
|
||||
*******************************************************************************/
|
||||
|
||||
#define SFLASH_BASE 0x16000000UL
|
||||
#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* PERI
|
||||
*******************************************************************************/
|
||||
|
||||
#define PERI_BASE 0x40010000UL
|
||||
#define PERI_PPU_GR_MMIO0_BASE 0x40015000UL
|
||||
#define PERI_PPU_GR_MMIO1_BASE 0x40015040UL
|
||||
#define PERI_PPU_GR_MMIO2_BASE 0x40015080UL
|
||||
#define PERI_PPU_GR_MMIO3_BASE 0x400150C0UL
|
||||
#define PERI_PPU_GR_MMIO4_BASE 0x40015100UL
|
||||
#define PERI_PPU_GR_MMIO6_BASE 0x40015180UL
|
||||
#define PERI_PPU_GR_MMIO9_BASE 0x40015240UL
|
||||
#define PERI_PPU_GR_MMIO10_BASE 0x40015280UL
|
||||
#define PERI_GR_PPU_SL_PERI_GR1_BASE 0x40100000UL
|
||||
#define PERI_GR_PPU_SL_CRYPTO_BASE 0x40100040UL
|
||||
#define PERI_GR_PPU_SL_PERI_GR2_BASE 0x40200000UL
|
||||
#define PERI_GR_PPU_SL_CPUSS_BASE 0x40200040UL
|
||||
#define PERI_GR_PPU_SL_FAULT_BASE 0x40200080UL
|
||||
#define PERI_GR_PPU_SL_IPC_BASE 0x402000C0UL
|
||||
#define PERI_GR_PPU_SL_PROT_BASE 0x40200100UL
|
||||
#define PERI_GR_PPU_SL_FLASHC_BASE 0x40200140UL
|
||||
#define PERI_GR_PPU_SL_SRSS_BASE 0x40200180UL
|
||||
#define PERI_GR_PPU_SL_BACKUP_BASE 0x402001C0UL
|
||||
#define PERI_GR_PPU_SL_DW0_BASE 0x40200200UL
|
||||
#define PERI_GR_PPU_SL_DW1_BASE 0x40200240UL
|
||||
#define PERI_GR_PPU_SL_EFUSE_BASE 0x40200300UL
|
||||
#define PERI_GR_PPU_SL_PROFILE_BASE 0x40200340UL
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT0_BASE 0x40201000UL
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT1_BASE 0x40201040UL
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT2_BASE 0x40201080UL
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT3_BASE 0x402010C0UL
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT4_BASE 0x40201100UL
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT5_BASE 0x40201140UL
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT6_BASE 0x40201180UL
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT7_BASE 0x402011C0UL
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT0_BASE 0x40201200UL
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT1_BASE 0x40201240UL
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT2_BASE 0x40201280UL
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT3_BASE 0x402012C0UL
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT4_BASE 0x40201300UL
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT5_BASE 0x40201340UL
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT6_BASE 0x40201380UL
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT7_BASE 0x402013C0UL
|
||||
#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT0_BASE 0x40201400UL
|
||||
#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT1_BASE 0x40201440UL
|
||||
#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT2_BASE 0x40201480UL
|
||||
#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT3_BASE 0x402014C0UL
|
||||
#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT0_BASE 0x40201500UL
|
||||
#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT1_BASE 0x40201540UL
|
||||
#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT2_BASE 0x40201580UL
|
||||
#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT3_BASE 0x402015C0UL
|
||||
#define PERI_GR_PPU_RG_SMPU_BASE 0x40201600UL
|
||||
#define PERI_GR_PPU_RG_MPU_CM0P_BASE 0x40201640UL
|
||||
#define PERI_GR_PPU_RG_MPU_CRYPTO_BASE 0x40201680UL
|
||||
#define PERI_GR_PPU_RG_MPU_CM4_BASE 0x402016C0UL
|
||||
#define PERI_GR_PPU_RG_MPU_TC_BASE 0x40201700UL
|
||||
#define PERI_GR_PPU_SL_PERI_GR3_BASE 0x40300000UL
|
||||
#define PERI_GR_PPU_SL_HSIOM_BASE 0x40300040UL
|
||||
#define PERI_GR_PPU_SL_GPIO_BASE 0x40300080UL
|
||||
#define PERI_GR_PPU_SL_SMARTIO_BASE 0x403000C0UL
|
||||
#define PERI_GR_PPU_SL_UDB_BASE 0x40300100UL
|
||||
#define PERI_GR_PPU_SL_LPCOMP_BASE 0x40300140UL
|
||||
#define PERI_GR_PPU_SL_CSD_BASE 0x40300180UL
|
||||
#define PERI_GR_PPU_SL_TCPWM0_BASE 0x40300200UL
|
||||
#define PERI_GR_PPU_SL_TCPWM1_BASE 0x40300240UL
|
||||
#define PERI_GR_PPU_SL_LCD_BASE 0x40300280UL
|
||||
#define PERI_GR_PPU_SL_BLE_BASE 0x403002C0UL
|
||||
#define PERI_GR_PPU_SL_USBFS_BASE 0x40300300UL
|
||||
#define PERI_GR_PPU_SL_PERI_GR4_BASE 0x40400000UL
|
||||
#define PERI_GR_PPU_SL_SMIF_BASE 0x40400080UL
|
||||
#define PERI_GR_PPU_SL_PERI_GR6_BASE 0x40600000UL
|
||||
#define PERI_GR_PPU_SL_SCB0_BASE 0x40600040UL
|
||||
#define PERI_GR_PPU_SL_SCB1_BASE 0x40600080UL
|
||||
#define PERI_GR_PPU_SL_SCB2_BASE 0x406000C0UL
|
||||
#define PERI_GR_PPU_SL_SCB3_BASE 0x40600100UL
|
||||
#define PERI_GR_PPU_SL_SCB4_BASE 0x40600140UL
|
||||
#define PERI_GR_PPU_SL_SCB5_BASE 0x40600180UL
|
||||
#define PERI_GR_PPU_SL_SCB6_BASE 0x406001C0UL
|
||||
#define PERI_GR_PPU_SL_SCB7_BASE 0x40600200UL
|
||||
#define PERI_GR_PPU_SL_SCB8_BASE 0x40600240UL
|
||||
#define PERI_GR_PPU_SL_PERI_GR9_BASE 0x41000000UL
|
||||
#define PERI_GR_PPU_SL_PASS_BASE 0x41000040UL
|
||||
#define PERI_GR_PPU_SL_PERI_GR10_BASE 0x42A00000UL
|
||||
#define PERI_GR_PPU_SL_I2S_BASE 0x42A00040UL
|
||||
#define PERI_GR_PPU_SL_PDM_BASE 0x42A00080UL
|
||||
#define PERI ((PERI_Type*) PERI_BASE) /* 0x40010000 */
|
||||
#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40010000 */
|
||||
#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40010040 */
|
||||
#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40010080 */
|
||||
#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x400100C0 */
|
||||
#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40010100 */
|
||||
#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x40010180 */
|
||||
#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40010240 */
|
||||
#define PERI_GR10 ((PERI_GR_Type*) &PERI->GR[10]) /* 0x40010280 */
|
||||
#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40012000 */
|
||||
#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40012200 */
|
||||
#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40012400 */
|
||||
#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40012600 */
|
||||
#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40012800 */
|
||||
#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40012A00 */
|
||||
#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40012C00 */
|
||||
#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40012E00 */
|
||||
#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x40013000 */
|
||||
#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x40013200 */
|
||||
#define PERI_TR_GR10 ((PERI_TR_GR_Type*) &PERI->TR_GR[10]) /* 0x40013400 */
|
||||
#define PERI_TR_GR11 ((PERI_TR_GR_Type*) &PERI->TR_GR[11]) /* 0x40013600 */
|
||||
#define PERI_TR_GR12 ((PERI_TR_GR_Type*) &PERI->TR_GR[12]) /* 0x40013800 */
|
||||
#define PERI_TR_GR13 ((PERI_TR_GR_Type*) &PERI->TR_GR[13]) /* 0x40013A00 */
|
||||
#define PERI_TR_GR14 ((PERI_TR_GR_Type*) &PERI->TR_GR[14]) /* 0x40013C00 */
|
||||
#define PERI_PPU_PR0 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[0]) /* 0x40014000 */
|
||||
#define PERI_PPU_PR1 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[1]) /* 0x40014040 */
|
||||
#define PERI_PPU_PR2 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[2]) /* 0x40014080 */
|
||||
#define PERI_PPU_PR3 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[3]) /* 0x400140C0 */
|
||||
#define PERI_PPU_PR4 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[4]) /* 0x40014100 */
|
||||
#define PERI_PPU_PR5 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[5]) /* 0x40014140 */
|
||||
#define PERI_PPU_PR6 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[6]) /* 0x40014180 */
|
||||
#define PERI_PPU_PR7 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[7]) /* 0x400141C0 */
|
||||
#define PERI_PPU_PR8 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[8]) /* 0x40014200 */
|
||||
#define PERI_PPU_PR9 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[9]) /* 0x40014240 */
|
||||
#define PERI_PPU_PR10 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[10]) /* 0x40014280 */
|
||||
#define PERI_PPU_PR11 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[11]) /* 0x400142C0 */
|
||||
#define PERI_PPU_PR12 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[12]) /* 0x40014300 */
|
||||
#define PERI_PPU_PR13 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[13]) /* 0x40014340 */
|
||||
#define PERI_PPU_PR14 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[14]) /* 0x40014380 */
|
||||
#define PERI_PPU_PR15 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[15]) /* 0x400143C0 */
|
||||
#define PERI_PPU_GR0 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[0]) /* 0x40015000 */
|
||||
#define PERI_PPU_GR1 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[1]) /* 0x40015040 */
|
||||
#define PERI_PPU_GR2 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[2]) /* 0x40015080 */
|
||||
#define PERI_PPU_GR3 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[3]) /* 0x400150C0 */
|
||||
#define PERI_PPU_GR4 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[4]) /* 0x40015100 */
|
||||
#define PERI_PPU_GR6 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[6]) /* 0x40015180 */
|
||||
#define PERI_PPU_GR9 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[9]) /* 0x40015240 */
|
||||
#define PERI_PPU_GR10 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[10]) /* 0x40015280 */
|
||||
#define PERI_PPU_GR_MMIO0 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO0_BASE) /* 0x40015000 */
|
||||
#define PERI_PPU_GR_MMIO1 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO1_BASE) /* 0x40015040 */
|
||||
#define PERI_PPU_GR_MMIO2 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO2_BASE) /* 0x40015080 */
|
||||
#define PERI_PPU_GR_MMIO3 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO3_BASE) /* 0x400150C0 */
|
||||
#define PERI_PPU_GR_MMIO4 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO4_BASE) /* 0x40015100 */
|
||||
#define PERI_PPU_GR_MMIO6 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO6_BASE) /* 0x40015180 */
|
||||
#define PERI_PPU_GR_MMIO9 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO9_BASE) /* 0x40015240 */
|
||||
#define PERI_PPU_GR_MMIO10 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO10_BASE) /* 0x40015280 */
|
||||
#define PERI_GR_PPU_SL_PERI_GR1 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR1_BASE) /* 0x40100000 */
|
||||
#define PERI_GR_PPU_SL_CRYPTO ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_CRYPTO_BASE) /* 0x40100040 */
|
||||
#define PERI_GR_PPU_SL_PERI_GR2 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR2_BASE) /* 0x40200000 */
|
||||
#define PERI_GR_PPU_SL_CPUSS ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_CPUSS_BASE) /* 0x40200040 */
|
||||
#define PERI_GR_PPU_SL_FAULT ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_FAULT_BASE) /* 0x40200080 */
|
||||
#define PERI_GR_PPU_SL_IPC ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_IPC_BASE) /* 0x402000C0 */
|
||||
#define PERI_GR_PPU_SL_PROT ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PROT_BASE) /* 0x40200100 */
|
||||
#define PERI_GR_PPU_SL_FLASHC ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_FLASHC_BASE) /* 0x40200140 */
|
||||
#define PERI_GR_PPU_SL_SRSS ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SRSS_BASE) /* 0x40200180 */
|
||||
#define PERI_GR_PPU_SL_BACKUP ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_BACKUP_BASE) /* 0x402001C0 */
|
||||
#define PERI_GR_PPU_SL_DW0 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_DW0_BASE) /* 0x40200200 */
|
||||
#define PERI_GR_PPU_SL_DW1 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_DW1_BASE) /* 0x40200240 */
|
||||
#define PERI_GR_PPU_SL_EFUSE ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_EFUSE_BASE) /* 0x40200300 */
|
||||
#define PERI_GR_PPU_SL_PROFILE ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PROFILE_BASE) /* 0x40200340 */
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT0 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT0_BASE) /* 0x40201000 */
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT1 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT1_BASE) /* 0x40201040 */
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT2 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT2_BASE) /* 0x40201080 */
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT3 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT3_BASE) /* 0x402010C0 */
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT4 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT4_BASE) /* 0x40201100 */
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT5 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT5_BASE) /* 0x40201140 */
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT6 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT6_BASE) /* 0x40201180 */
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT7 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT7_BASE) /* 0x402011C0 */
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT0 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT0_BASE) /* 0x40201200 */
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT1 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT1_BASE) /* 0x40201240 */
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT2 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT2_BASE) /* 0x40201280 */
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT3 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT3_BASE) /* 0x402012C0 */
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT4 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT4_BASE) /* 0x40201300 */
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT5 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT5_BASE) /* 0x40201340 */
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT6 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT6_BASE) /* 0x40201380 */
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT7 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT7_BASE) /* 0x402013C0 */
|
||||
#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT0 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW0_DW_CH_STRUCT0_BASE) /* 0x40201400 */
|
||||
#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT1 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW0_DW_CH_STRUCT1_BASE) /* 0x40201440 */
|
||||
#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT2 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW0_DW_CH_STRUCT2_BASE) /* 0x40201480 */
|
||||
#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT3 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW0_DW_CH_STRUCT3_BASE) /* 0x402014C0 */
|
||||
#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT0 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW1_DW_CH_STRUCT0_BASE) /* 0x40201500 */
|
||||
#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT1 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW1_DW_CH_STRUCT1_BASE) /* 0x40201540 */
|
||||
#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT2 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW1_DW_CH_STRUCT2_BASE) /* 0x40201580 */
|
||||
#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT3 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW1_DW_CH_STRUCT3_BASE) /* 0x402015C0 */
|
||||
#define PERI_GR_PPU_RG_SMPU ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_SMPU_BASE) /* 0x40201600 */
|
||||
#define PERI_GR_PPU_RG_MPU_CM0P ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_MPU_CM0P_BASE) /* 0x40201640 */
|
||||
#define PERI_GR_PPU_RG_MPU_CRYPTO ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_MPU_CRYPTO_BASE) /* 0x40201680 */
|
||||
#define PERI_GR_PPU_RG_MPU_CM4 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_MPU_CM4_BASE) /* 0x402016C0 */
|
||||
#define PERI_GR_PPU_RG_MPU_TC ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_MPU_TC_BASE) /* 0x40201700 */
|
||||
#define PERI_GR_PPU_SL_PERI_GR3 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR3_BASE) /* 0x40300000 */
|
||||
#define PERI_GR_PPU_SL_HSIOM ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_HSIOM_BASE) /* 0x40300040 */
|
||||
#define PERI_GR_PPU_SL_GPIO ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_GPIO_BASE) /* 0x40300080 */
|
||||
#define PERI_GR_PPU_SL_SMARTIO ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SMARTIO_BASE) /* 0x403000C0 */
|
||||
#define PERI_GR_PPU_SL_UDB ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_UDB_BASE) /* 0x40300100 */
|
||||
#define PERI_GR_PPU_SL_LPCOMP ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_LPCOMP_BASE) /* 0x40300140 */
|
||||
#define PERI_GR_PPU_SL_CSD ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_CSD_BASE) /* 0x40300180 */
|
||||
#define PERI_GR_PPU_SL_TCPWM0 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_TCPWM0_BASE) /* 0x40300200 */
|
||||
#define PERI_GR_PPU_SL_TCPWM1 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_TCPWM1_BASE) /* 0x40300240 */
|
||||
#define PERI_GR_PPU_SL_LCD ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_LCD_BASE) /* 0x40300280 */
|
||||
#define PERI_GR_PPU_SL_BLE ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_BLE_BASE) /* 0x403002C0 */
|
||||
#define PERI_GR_PPU_SL_USBFS ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_USBFS_BASE) /* 0x40300300 */
|
||||
#define PERI_GR_PPU_SL_PERI_GR4 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR4_BASE) /* 0x40400000 */
|
||||
#define PERI_GR_PPU_SL_SMIF ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SMIF_BASE) /* 0x40400080 */
|
||||
#define PERI_GR_PPU_SL_PERI_GR6 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR6_BASE) /* 0x40600000 */
|
||||
#define PERI_GR_PPU_SL_SCB0 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB0_BASE) /* 0x40600040 */
|
||||
#define PERI_GR_PPU_SL_SCB1 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB1_BASE) /* 0x40600080 */
|
||||
#define PERI_GR_PPU_SL_SCB2 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB2_BASE) /* 0x406000C0 */
|
||||
#define PERI_GR_PPU_SL_SCB3 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB3_BASE) /* 0x40600100 */
|
||||
#define PERI_GR_PPU_SL_SCB4 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB4_BASE) /* 0x40600140 */
|
||||
#define PERI_GR_PPU_SL_SCB5 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB5_BASE) /* 0x40600180 */
|
||||
#define PERI_GR_PPU_SL_SCB6 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB6_BASE) /* 0x406001C0 */
|
||||
#define PERI_GR_PPU_SL_SCB7 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB7_BASE) /* 0x40600200 */
|
||||
#define PERI_GR_PPU_SL_SCB8 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB8_BASE) /* 0x40600240 */
|
||||
#define PERI_GR_PPU_SL_PERI_GR9 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR9_BASE) /* 0x41000000 */
|
||||
#define PERI_GR_PPU_SL_PASS ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PASS_BASE) /* 0x41000040 */
|
||||
#define PERI_GR_PPU_SL_PERI_GR10 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR10_BASE) /* 0x42A00000 */
|
||||
#define PERI_GR_PPU_SL_I2S ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_I2S_BASE) /* 0x42A00040 */
|
||||
#define PERI_GR_PPU_SL_PDM ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PDM_BASE) /* 0x42A00080 */
|
||||
|
||||
/*******************************************************************************
|
||||
* CRYPTO
|
||||
*******************************************************************************/
|
||||
|
||||
#define CRYPTO_BASE 0x40110000UL
|
||||
#define CRYPTO ((CRYPTO_Type*) CRYPTO_BASE) /* 0x40110000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* CPUSS
|
||||
*******************************************************************************/
|
||||
|
||||
#define CPUSS_BASE 0x40210000UL
|
||||
#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40210000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* FAULT
|
||||
*******************************************************************************/
|
||||
|
||||
#define FAULT_BASE 0x40220000UL
|
||||
#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40220000 */
|
||||
#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40220000 */
|
||||
#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40220100 */
|
||||
|
||||
/*******************************************************************************
|
||||
* IPC
|
||||
*******************************************************************************/
|
||||
|
||||
#define IPC_BASE 0x40230000UL
|
||||
#define IPC ((IPC_Type*) IPC_BASE) /* 0x40230000 */
|
||||
#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40230000 */
|
||||
#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40230020 */
|
||||
#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40230040 */
|
||||
#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40230060 */
|
||||
#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40230080 */
|
||||
#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402300A0 */
|
||||
#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402300C0 */
|
||||
#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402300E0 */
|
||||
#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40230100 */
|
||||
#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40230120 */
|
||||
#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40230140 */
|
||||
#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40230160 */
|
||||
#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40230180 */
|
||||
#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402301A0 */
|
||||
#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402301C0 */
|
||||
#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402301E0 */
|
||||
#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40231000 */
|
||||
#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40231020 */
|
||||
#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40231040 */
|
||||
#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40231060 */
|
||||
#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40231080 */
|
||||
#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402310A0 */
|
||||
#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402310C0 */
|
||||
#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402310E0 */
|
||||
#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40231100 */
|
||||
#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40231120 */
|
||||
#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40231140 */
|
||||
#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40231160 */
|
||||
#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40231180 */
|
||||
#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402311A0 */
|
||||
#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402311C0 */
|
||||
#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402311E0 */
|
||||
|
||||
/*******************************************************************************
|
||||
* PROT
|
||||
*******************************************************************************/
|
||||
|
||||
#define PROT_BASE 0x40240000UL
|
||||
#define PROT ((PROT_Type*) PROT_BASE) /* 0x40240000 */
|
||||
#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40242000 */
|
||||
#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40242040 */
|
||||
#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40242080 */
|
||||
#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402420C0 */
|
||||
#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40242100 */
|
||||
#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40242140 */
|
||||
#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40242180 */
|
||||
#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402421C0 */
|
||||
#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40242200 */
|
||||
#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40242240 */
|
||||
#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40242280 */
|
||||
#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402422C0 */
|
||||
#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40242300 */
|
||||
#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40242340 */
|
||||
#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40242380 */
|
||||
#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402423C0 */
|
||||
#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */
|
||||
#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */
|
||||
#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */
|
||||
#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */
|
||||
#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */
|
||||
#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */
|
||||
#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */
|
||||
#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */
|
||||
#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */
|
||||
#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */
|
||||
#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */
|
||||
#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */
|
||||
#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */
|
||||
#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */
|
||||
#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */
|
||||
#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */
|
||||
#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */
|
||||
#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40244000 */
|
||||
#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40244400 */
|
||||
#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40244800 */
|
||||
#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40244C00 */
|
||||
#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40245000 */
|
||||
#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40245400 */
|
||||
#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40245800 */
|
||||
#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40245C00 */
|
||||
#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40246000 */
|
||||
#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40246400 */
|
||||
#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40246800 */
|
||||
#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40246C00 */
|
||||
#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40247000 */
|
||||
#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40247400 */
|
||||
#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40247800 */
|
||||
#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40247C00 */
|
||||
|
||||
/*******************************************************************************
|
||||
* FLASHC
|
||||
*******************************************************************************/
|
||||
|
||||
#define FLASHC_BASE 0x40250000UL
|
||||
#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40250000 */
|
||||
#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4025F000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* SRSS
|
||||
*******************************************************************************/
|
||||
|
||||
#define SRSS_BASE 0x40260000UL
|
||||
#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */
|
||||
#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */
|
||||
#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */
|
||||
|
||||
/*******************************************************************************
|
||||
* BACKUP
|
||||
*******************************************************************************/
|
||||
|
||||
#define BACKUP_BASE 0x40270000UL
|
||||
#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* DW
|
||||
*******************************************************************************/
|
||||
|
||||
#define DW0_BASE 0x40280000UL
|
||||
#define DW1_BASE 0x40281000UL
|
||||
#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */
|
||||
#define DW1 ((DW_Type*) DW1_BASE) /* 0x40281000 */
|
||||
#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40280800 */
|
||||
#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40280820 */
|
||||
#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40280840 */
|
||||
#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x40280860 */
|
||||
#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40280880 */
|
||||
#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x402808A0 */
|
||||
#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x402808C0 */
|
||||
#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402808E0 */
|
||||
#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40280900 */
|
||||
#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40280920 */
|
||||
#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40280940 */
|
||||
#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x40280960 */
|
||||
#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40280980 */
|
||||
#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x402809A0 */
|
||||
#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x402809C0 */
|
||||
#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402809E0 */
|
||||
#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40281800 */
|
||||
#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40281820 */
|
||||
#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40281840 */
|
||||
#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x40281860 */
|
||||
#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40281880 */
|
||||
#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x402818A0 */
|
||||
#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x402818C0 */
|
||||
#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402818E0 */
|
||||
#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40281900 */
|
||||
#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40281920 */
|
||||
#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40281940 */
|
||||
#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x40281960 */
|
||||
#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40281980 */
|
||||
#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x402819A0 */
|
||||
#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x402819C0 */
|
||||
#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402819E0 */
|
||||
|
||||
/*******************************************************************************
|
||||
* EFUSE
|
||||
*******************************************************************************/
|
||||
|
||||
#define EFUSE_BASE 0x402C0000UL
|
||||
#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* PROFILE
|
||||
*******************************************************************************/
|
||||
|
||||
#define PROFILE_BASE 0x402D0000UL
|
||||
#define PROFILE ((PROFILE_Type*) PROFILE_BASE) /* 0x402D0000 */
|
||||
#define PROFILE_CNT_STRUCT0 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[0]) /* 0x402D0800 */
|
||||
#define PROFILE_CNT_STRUCT1 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[1]) /* 0x402D0810 */
|
||||
#define PROFILE_CNT_STRUCT2 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[2]) /* 0x402D0820 */
|
||||
#define PROFILE_CNT_STRUCT3 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[3]) /* 0x402D0830 */
|
||||
#define PROFILE_CNT_STRUCT4 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[4]) /* 0x402D0840 */
|
||||
#define PROFILE_CNT_STRUCT5 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[5]) /* 0x402D0850 */
|
||||
#define PROFILE_CNT_STRUCT6 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[6]) /* 0x402D0860 */
|
||||
#define PROFILE_CNT_STRUCT7 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[7]) /* 0x402D0870 */
|
||||
|
||||
/*******************************************************************************
|
||||
* HSIOM
|
||||
*******************************************************************************/
|
||||
|
||||
#define HSIOM_BASE 0x40310000UL
|
||||
#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40310000 */
|
||||
#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40310000 */
|
||||
#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40310010 */
|
||||
#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40310020 */
|
||||
#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40310030 */
|
||||
#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40310040 */
|
||||
#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40310050 */
|
||||
#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40310060 */
|
||||
#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40310070 */
|
||||
#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40310080 */
|
||||
#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40310090 */
|
||||
#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403100A0 */
|
||||
#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403100B0 */
|
||||
#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403100C0 */
|
||||
#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403100D0 */
|
||||
#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403100E0 */
|
||||
|
||||
/*******************************************************************************
|
||||
* GPIO
|
||||
*******************************************************************************/
|
||||
|
||||
#define GPIO_BASE 0x40320000UL
|
||||
#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40320000 */
|
||||
#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40320000 */
|
||||
#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40320080 */
|
||||
#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40320100 */
|
||||
#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40320180 */
|
||||
#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40320200 */
|
||||
#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40320280 */
|
||||
#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40320300 */
|
||||
#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40320380 */
|
||||
#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40320400 */
|
||||
#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40320480 */
|
||||
#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40320500 */
|
||||
#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40320580 */
|
||||
#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40320600 */
|
||||
#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40320680 */
|
||||
#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40320700 */
|
||||
|
||||
/*******************************************************************************
|
||||
* SMARTIO
|
||||
*******************************************************************************/
|
||||
|
||||
#define SMARTIO_BASE 0x40330000UL
|
||||
#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40330000 */
|
||||
#define SMARTIO_PRT8 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[8]) /* 0x40330800 */
|
||||
#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40330900 */
|
||||
|
||||
/*******************************************************************************
|
||||
* LPCOMP
|
||||
*******************************************************************************/
|
||||
|
||||
#define LPCOMP_BASE 0x40350000UL
|
||||
#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* CSD
|
||||
*******************************************************************************/
|
||||
|
||||
#define CSD0_BASE 0x40360000UL
|
||||
#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* TCPWM
|
||||
*******************************************************************************/
|
||||
|
||||
#define TCPWM0_BASE 0x40380000UL
|
||||
#define TCPWM1_BASE 0x40390000UL
|
||||
#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */
|
||||
#define TCPWM1 ((TCPWM_Type*) TCPWM1_BASE) /* 0x40390000 */
|
||||
#define TCPWM0_CNT0 ((TCPWM_CNT_Type*) &TCPWM0->CNT[0]) /* 0x40380100 */
|
||||
#define TCPWM0_CNT1 ((TCPWM_CNT_Type*) &TCPWM0->CNT[1]) /* 0x40380140 */
|
||||
#define TCPWM0_CNT2 ((TCPWM_CNT_Type*) &TCPWM0->CNT[2]) /* 0x40380180 */
|
||||
#define TCPWM0_CNT3 ((TCPWM_CNT_Type*) &TCPWM0->CNT[3]) /* 0x403801C0 */
|
||||
#define TCPWM0_CNT4 ((TCPWM_CNT_Type*) &TCPWM0->CNT[4]) /* 0x40380200 */
|
||||
#define TCPWM0_CNT5 ((TCPWM_CNT_Type*) &TCPWM0->CNT[5]) /* 0x40380240 */
|
||||
#define TCPWM0_CNT6 ((TCPWM_CNT_Type*) &TCPWM0->CNT[6]) /* 0x40380280 */
|
||||
#define TCPWM0_CNT7 ((TCPWM_CNT_Type*) &TCPWM0->CNT[7]) /* 0x403802C0 */
|
||||
#define TCPWM1_CNT0 ((TCPWM_CNT_Type*) &TCPWM1->CNT[0]) /* 0x40390100 */
|
||||
#define TCPWM1_CNT1 ((TCPWM_CNT_Type*) &TCPWM1->CNT[1]) /* 0x40390140 */
|
||||
#define TCPWM1_CNT2 ((TCPWM_CNT_Type*) &TCPWM1->CNT[2]) /* 0x40390180 */
|
||||
#define TCPWM1_CNT3 ((TCPWM_CNT_Type*) &TCPWM1->CNT[3]) /* 0x403901C0 */
|
||||
#define TCPWM1_CNT4 ((TCPWM_CNT_Type*) &TCPWM1->CNT[4]) /* 0x40390200 */
|
||||
#define TCPWM1_CNT5 ((TCPWM_CNT_Type*) &TCPWM1->CNT[5]) /* 0x40390240 */
|
||||
#define TCPWM1_CNT6 ((TCPWM_CNT_Type*) &TCPWM1->CNT[6]) /* 0x40390280 */
|
||||
#define TCPWM1_CNT7 ((TCPWM_CNT_Type*) &TCPWM1->CNT[7]) /* 0x403902C0 */
|
||||
#define TCPWM1_CNT8 ((TCPWM_CNT_Type*) &TCPWM1->CNT[8]) /* 0x40390300 */
|
||||
#define TCPWM1_CNT9 ((TCPWM_CNT_Type*) &TCPWM1->CNT[9]) /* 0x40390340 */
|
||||
#define TCPWM1_CNT10 ((TCPWM_CNT_Type*) &TCPWM1->CNT[10]) /* 0x40390380 */
|
||||
#define TCPWM1_CNT11 ((TCPWM_CNT_Type*) &TCPWM1->CNT[11]) /* 0x403903C0 */
|
||||
#define TCPWM1_CNT12 ((TCPWM_CNT_Type*) &TCPWM1->CNT[12]) /* 0x40390400 */
|
||||
#define TCPWM1_CNT13 ((TCPWM_CNT_Type*) &TCPWM1->CNT[13]) /* 0x40390440 */
|
||||
#define TCPWM1_CNT14 ((TCPWM_CNT_Type*) &TCPWM1->CNT[14]) /* 0x40390480 */
|
||||
#define TCPWM1_CNT15 ((TCPWM_CNT_Type*) &TCPWM1->CNT[15]) /* 0x403904C0 */
|
||||
#define TCPWM1_CNT16 ((TCPWM_CNT_Type*) &TCPWM1->CNT[16]) /* 0x40390500 */
|
||||
#define TCPWM1_CNT17 ((TCPWM_CNT_Type*) &TCPWM1->CNT[17]) /* 0x40390540 */
|
||||
#define TCPWM1_CNT18 ((TCPWM_CNT_Type*) &TCPWM1->CNT[18]) /* 0x40390580 */
|
||||
#define TCPWM1_CNT19 ((TCPWM_CNT_Type*) &TCPWM1->CNT[19]) /* 0x403905C0 */
|
||||
#define TCPWM1_CNT20 ((TCPWM_CNT_Type*) &TCPWM1->CNT[20]) /* 0x40390600 */
|
||||
#define TCPWM1_CNT21 ((TCPWM_CNT_Type*) &TCPWM1->CNT[21]) /* 0x40390640 */
|
||||
#define TCPWM1_CNT22 ((TCPWM_CNT_Type*) &TCPWM1->CNT[22]) /* 0x40390680 */
|
||||
#define TCPWM1_CNT23 ((TCPWM_CNT_Type*) &TCPWM1->CNT[23]) /* 0x403906C0 */
|
||||
|
||||
/*******************************************************************************
|
||||
* LCD
|
||||
*******************************************************************************/
|
||||
|
||||
#define LCD0_BASE 0x403B0000UL
|
||||
#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* USBFS
|
||||
*******************************************************************************/
|
||||
|
||||
#define USBFS0_BASE 0x403F0000UL
|
||||
#define USBFS0 ((USBFS_Type*) USBFS0_BASE) /* 0x403F0000 */
|
||||
#define USBFS0_USBDEV ((USBFS_USBDEV_Type*) &USBFS0->USBDEV) /* 0x403F0000 */
|
||||
#define USBFS0_USBLPM ((USBFS_USBLPM_Type*) &USBFS0->USBLPM) /* 0x403F2000 */
|
||||
#define USBFS0_USBHOST ((USBFS_USBHOST_Type*) &USBFS0->USBHOST) /* 0x403F4000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* SMIF
|
||||
*******************************************************************************/
|
||||
|
||||
#define SMIF0_BASE 0x40420000UL
|
||||
#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */
|
||||
#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */
|
||||
#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */
|
||||
#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */
|
||||
#define SMIF0_DEVICE3 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[3]) /* 0x40420980 */
|
||||
|
||||
/*******************************************************************************
|
||||
* SCB
|
||||
*******************************************************************************/
|
||||
|
||||
#define SCB0_BASE 0x40610000UL
|
||||
#define SCB1_BASE 0x40620000UL
|
||||
#define SCB2_BASE 0x40630000UL
|
||||
#define SCB3_BASE 0x40640000UL
|
||||
#define SCB4_BASE 0x40650000UL
|
||||
#define SCB5_BASE 0x40660000UL
|
||||
#define SCB6_BASE 0x40670000UL
|
||||
#define SCB7_BASE 0x40680000UL
|
||||
#define SCB8_BASE 0x40690000UL
|
||||
#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40610000 */
|
||||
#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40620000 */
|
||||
#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40630000 */
|
||||
#define SCB3 ((CySCB_Type*) SCB3_BASE) /* 0x40640000 */
|
||||
#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40650000 */
|
||||
#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40660000 */
|
||||
#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40670000 */
|
||||
#define SCB7 ((CySCB_Type*) SCB7_BASE) /* 0x40680000 */
|
||||
#define SCB8 ((CySCB_Type*) SCB8_BASE) /* 0x40690000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* CTDAC
|
||||
*******************************************************************************/
|
||||
|
||||
#define CTDAC0_BASE 0x41140000UL
|
||||
#define CTDAC0 ((CTDAC_Type*) CTDAC0_BASE) /* 0x41140000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* SAR
|
||||
*******************************************************************************/
|
||||
|
||||
#define SAR_BASE 0x411D0000UL
|
||||
#define SAR ((SAR_Type*) SAR_BASE) /* 0x411D0000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* PASS
|
||||
*******************************************************************************/
|
||||
|
||||
#define PASS_BASE 0x411F0000UL
|
||||
#define PASS ((PASS_Type*) PASS_BASE) /* 0x411F0000 */
|
||||
#define PASS_AREF ((PASS_AREF_Type*) &PASS->AREF) /* 0x411F0E00 */
|
||||
|
||||
/*******************************************************************************
|
||||
* I2S
|
||||
*******************************************************************************/
|
||||
|
||||
#define I2S0_BASE 0x42A10000UL
|
||||
#define I2S0 ((I2S_Type*) I2S0_BASE) /* 0x42A10000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* PDM
|
||||
*******************************************************************************/
|
||||
|
||||
#define PDM0_BASE 0x42A20000UL
|
||||
#define PDM0 ((PDM_Type*) PDM0_BASE) /* 0x42A20000 */
|
||||
|
||||
|
||||
/* Backward compabitility definitions */
|
||||
#define I2S I2S0
|
||||
#define PDM PDM0
|
||||
|
||||
/** \} CY8C6136FDI-F42 */
|
||||
|
||||
#endif /* _CY8C6136FDI_F42_H_ */
|
||||
|
||||
|
||||
/* [] END OF FILE */
|
||||
|
|
@ -1,933 +0,0 @@
|
|||
/***************************************************************************//**
|
||||
* \file cy8c6137bzi_f14.h
|
||||
*
|
||||
* \brief
|
||||
* CY8C6137BZI-F14 device header
|
||||
*
|
||||
* \note
|
||||
* Generator version: 1.3.0.1146
|
||||
* Database revision: rev#1050929
|
||||
*
|
||||
********************************************************************************
|
||||
* \copyright
|
||||
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
|
||||
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _CY8C6137BZI_F14_H_
|
||||
#define _CY8C6137BZI_F14_H_
|
||||
|
||||
/**
|
||||
* \addtogroup group_device CY8C6137BZI-F14
|
||||
* \{
|
||||
*/
|
||||
|
||||
/**
|
||||
* \addtogroup Configuration_of_CMSIS
|
||||
* \{
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Interrupt Number Definition
|
||||
*******************************************************************************/
|
||||
|
||||
typedef enum {
|
||||
/* ARM Cortex-M4 Core Interrupt Numbers */
|
||||
Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */
|
||||
NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */
|
||||
HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */
|
||||
MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */
|
||||
BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */
|
||||
UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
|
||||
SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */
|
||||
DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */
|
||||
PendSV_IRQn = -2, /*!< -2 Pendable request for system service */
|
||||
SysTick_IRQn = -1, /*!< -1 System Tick Timer */
|
||||
/* CY8C6137BZI-F14 Peripheral Interrupt Numbers */
|
||||
ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */
|
||||
ioss_interrupts_gpio_1_IRQn = 1, /*!< 1 [DeepSleep] GPIO Port Interrupt #1 */
|
||||
ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */
|
||||
ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */
|
||||
ioss_interrupts_gpio_4_IRQn = 4, /*!< 4 [DeepSleep] GPIO Port Interrupt #4 */
|
||||
ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */
|
||||
ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */
|
||||
ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */
|
||||
ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */
|
||||
ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */
|
||||
ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */
|
||||
ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */
|
||||
ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */
|
||||
ioss_interrupts_gpio_13_IRQn = 13, /*!< 13 [DeepSleep] GPIO Port Interrupt #13 */
|
||||
ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */
|
||||
ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */
|
||||
ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */
|
||||
lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */
|
||||
scb_8_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #8 (DeepSleep capable) */
|
||||
srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */
|
||||
srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */
|
||||
srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */
|
||||
srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */
|
||||
pass_interrupt_ctbs_IRQn = 23, /*!< 23 [DeepSleep] CTBm Interrupt (all CTBms) */
|
||||
bless_interrupt_IRQn = 24, /*!< 24 [DeepSleep] Bluetooth Radio interrupt */
|
||||
cpuss_interrupts_ipc_0_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */
|
||||
cpuss_interrupts_ipc_1_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */
|
||||
cpuss_interrupts_ipc_2_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */
|
||||
cpuss_interrupts_ipc_3_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */
|
||||
cpuss_interrupts_ipc_4_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */
|
||||
cpuss_interrupts_ipc_5_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */
|
||||
cpuss_interrupts_ipc_6_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */
|
||||
cpuss_interrupts_ipc_7_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */
|
||||
cpuss_interrupts_ipc_8_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */
|
||||
cpuss_interrupts_ipc_9_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */
|
||||
cpuss_interrupts_ipc_10_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */
|
||||
cpuss_interrupts_ipc_11_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */
|
||||
cpuss_interrupts_ipc_12_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */
|
||||
cpuss_interrupts_ipc_13_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */
|
||||
cpuss_interrupts_ipc_14_IRQn = 39, /*!< 39 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */
|
||||
cpuss_interrupts_ipc_15_IRQn = 40, /*!< 40 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */
|
||||
scb_0_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #0 */
|
||||
scb_1_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #1 */
|
||||
scb_2_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #2 */
|
||||
scb_3_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #3 */
|
||||
scb_4_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #4 */
|
||||
scb_5_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #5 */
|
||||
scb_6_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #6 */
|
||||
scb_7_interrupt_IRQn = 48, /*!< 48 [Active] Serial Communication Block #7 */
|
||||
csd_interrupt_IRQn = 49, /*!< 49 [Active] CSD (Capsense) interrupt */
|
||||
cpuss_interrupts_dw0_0_IRQn = 50, /*!< 50 [Active] CPUSS DataWire #0, Channel #0 */
|
||||
cpuss_interrupts_dw0_1_IRQn = 51, /*!< 51 [Active] CPUSS DataWire #0, Channel #1 */
|
||||
cpuss_interrupts_dw0_2_IRQn = 52, /*!< 52 [Active] CPUSS DataWire #0, Channel #2 */
|
||||
cpuss_interrupts_dw0_3_IRQn = 53, /*!< 53 [Active] CPUSS DataWire #0, Channel #3 */
|
||||
cpuss_interrupts_dw0_4_IRQn = 54, /*!< 54 [Active] CPUSS DataWire #0, Channel #4 */
|
||||
cpuss_interrupts_dw0_5_IRQn = 55, /*!< 55 [Active] CPUSS DataWire #0, Channel #5 */
|
||||
cpuss_interrupts_dw0_6_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #6 */
|
||||
cpuss_interrupts_dw0_7_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #7 */
|
||||
cpuss_interrupts_dw0_8_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #8 */
|
||||
cpuss_interrupts_dw0_9_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #9 */
|
||||
cpuss_interrupts_dw0_10_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #10 */
|
||||
cpuss_interrupts_dw0_11_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #11 */
|
||||
cpuss_interrupts_dw0_12_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #12 */
|
||||
cpuss_interrupts_dw0_13_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #13 */
|
||||
cpuss_interrupts_dw0_14_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #14 */
|
||||
cpuss_interrupts_dw0_15_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #15 */
|
||||
cpuss_interrupts_dw1_0_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #1, Channel #0 */
|
||||
cpuss_interrupts_dw1_1_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #1, Channel #1 */
|
||||
cpuss_interrupts_dw1_2_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #1, Channel #2 */
|
||||
cpuss_interrupts_dw1_3_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #1, Channel #3 */
|
||||
cpuss_interrupts_dw1_4_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #1, Channel #4 */
|
||||
cpuss_interrupts_dw1_5_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #1, Channel #5 */
|
||||
cpuss_interrupts_dw1_6_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #1, Channel #6 */
|
||||
cpuss_interrupts_dw1_7_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #1, Channel #7 */
|
||||
cpuss_interrupts_dw1_8_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #1, Channel #8 */
|
||||
cpuss_interrupts_dw1_9_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #1, Channel #9 */
|
||||
cpuss_interrupts_dw1_10_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #1, Channel #10 */
|
||||
cpuss_interrupts_dw1_11_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #1, Channel #11 */
|
||||
cpuss_interrupts_dw1_12_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #1, Channel #12 */
|
||||
cpuss_interrupts_dw1_13_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #1, Channel #13 */
|
||||
cpuss_interrupts_dw1_14_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #1, Channel #14 */
|
||||
cpuss_interrupts_dw1_15_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #1, Channel #15 */
|
||||
cpuss_interrupts_fault_0_IRQn = 82, /*!< 82 [Active] CPUSS Fault Structure Interrupt #0 */
|
||||
cpuss_interrupts_fault_1_IRQn = 83, /*!< 83 [Active] CPUSS Fault Structure Interrupt #1 */
|
||||
cpuss_interrupt_crypto_IRQn = 84, /*!< 84 [Active] CRYPTO Accelerator Interrupt */
|
||||
cpuss_interrupt_fm_IRQn = 85, /*!< 85 [Active] FLASH Macro Interrupt */
|
||||
cpuss_interrupts_cm0_cti_0_IRQn = 86, /*!< 86 [Active] CM0+ CTI #0 */
|
||||
cpuss_interrupts_cm0_cti_1_IRQn = 87, /*!< 87 [Active] CM0+ CTI #1 */
|
||||
cpuss_interrupts_cm4_cti_0_IRQn = 88, /*!< 88 [Active] CM4 CTI #0 */
|
||||
cpuss_interrupts_cm4_cti_1_IRQn = 89, /*!< 89 [Active] CM4 CTI #1 */
|
||||
tcpwm_0_interrupts_0_IRQn = 90, /*!< 90 [Active] TCPWM #0, Counter #0 */
|
||||
tcpwm_0_interrupts_1_IRQn = 91, /*!< 91 [Active] TCPWM #0, Counter #1 */
|
||||
tcpwm_0_interrupts_2_IRQn = 92, /*!< 92 [Active] TCPWM #0, Counter #2 */
|
||||
tcpwm_0_interrupts_3_IRQn = 93, /*!< 93 [Active] TCPWM #0, Counter #3 */
|
||||
tcpwm_0_interrupts_4_IRQn = 94, /*!< 94 [Active] TCPWM #0, Counter #4 */
|
||||
tcpwm_0_interrupts_5_IRQn = 95, /*!< 95 [Active] TCPWM #0, Counter #5 */
|
||||
tcpwm_0_interrupts_6_IRQn = 96, /*!< 96 [Active] TCPWM #0, Counter #6 */
|
||||
tcpwm_0_interrupts_7_IRQn = 97, /*!< 97 [Active] TCPWM #0, Counter #7 */
|
||||
tcpwm_1_interrupts_0_IRQn = 98, /*!< 98 [Active] TCPWM #1, Counter #0 */
|
||||
tcpwm_1_interrupts_1_IRQn = 99, /*!< 99 [Active] TCPWM #1, Counter #1 */
|
||||
tcpwm_1_interrupts_2_IRQn = 100, /*!< 100 [Active] TCPWM #1, Counter #2 */
|
||||
tcpwm_1_interrupts_3_IRQn = 101, /*!< 101 [Active] TCPWM #1, Counter #3 */
|
||||
tcpwm_1_interrupts_4_IRQn = 102, /*!< 102 [Active] TCPWM #1, Counter #4 */
|
||||
tcpwm_1_interrupts_5_IRQn = 103, /*!< 103 [Active] TCPWM #1, Counter #5 */
|
||||
tcpwm_1_interrupts_6_IRQn = 104, /*!< 104 [Active] TCPWM #1, Counter #6 */
|
||||
tcpwm_1_interrupts_7_IRQn = 105, /*!< 105 [Active] TCPWM #1, Counter #7 */
|
||||
tcpwm_1_interrupts_8_IRQn = 106, /*!< 106 [Active] TCPWM #1, Counter #8 */
|
||||
tcpwm_1_interrupts_9_IRQn = 107, /*!< 107 [Active] TCPWM #1, Counter #9 */
|
||||
tcpwm_1_interrupts_10_IRQn = 108, /*!< 108 [Active] TCPWM #1, Counter #10 */
|
||||
tcpwm_1_interrupts_11_IRQn = 109, /*!< 109 [Active] TCPWM #1, Counter #11 */
|
||||
tcpwm_1_interrupts_12_IRQn = 110, /*!< 110 [Active] TCPWM #1, Counter #12 */
|
||||
tcpwm_1_interrupts_13_IRQn = 111, /*!< 111 [Active] TCPWM #1, Counter #13 */
|
||||
tcpwm_1_interrupts_14_IRQn = 112, /*!< 112 [Active] TCPWM #1, Counter #14 */
|
||||
tcpwm_1_interrupts_15_IRQn = 113, /*!< 113 [Active] TCPWM #1, Counter #15 */
|
||||
tcpwm_1_interrupts_16_IRQn = 114, /*!< 114 [Active] TCPWM #1, Counter #16 */
|
||||
tcpwm_1_interrupts_17_IRQn = 115, /*!< 115 [Active] TCPWM #1, Counter #17 */
|
||||
tcpwm_1_interrupts_18_IRQn = 116, /*!< 116 [Active] TCPWM #1, Counter #18 */
|
||||
tcpwm_1_interrupts_19_IRQn = 117, /*!< 117 [Active] TCPWM #1, Counter #19 */
|
||||
tcpwm_1_interrupts_20_IRQn = 118, /*!< 118 [Active] TCPWM #1, Counter #20 */
|
||||
tcpwm_1_interrupts_21_IRQn = 119, /*!< 119 [Active] TCPWM #1, Counter #21 */
|
||||
tcpwm_1_interrupts_22_IRQn = 120, /*!< 120 [Active] TCPWM #1, Counter #22 */
|
||||
tcpwm_1_interrupts_23_IRQn = 121, /*!< 121 [Active] TCPWM #1, Counter #23 */
|
||||
udb_interrupts_0_IRQn = 122, /*!< 122 [Active] UDB Interrupt #0 */
|
||||
udb_interrupts_1_IRQn = 123, /*!< 123 [Active] UDB Interrupt #1 */
|
||||
udb_interrupts_2_IRQn = 124, /*!< 124 [Active] UDB Interrupt #2 */
|
||||
udb_interrupts_3_IRQn = 125, /*!< 125 [Active] UDB Interrupt #3 */
|
||||
udb_interrupts_4_IRQn = 126, /*!< 126 [Active] UDB Interrupt #4 */
|
||||
udb_interrupts_5_IRQn = 127, /*!< 127 [Active] UDB Interrupt #5 */
|
||||
udb_interrupts_6_IRQn = 128, /*!< 128 [Active] UDB Interrupt #6 */
|
||||
udb_interrupts_7_IRQn = 129, /*!< 129 [Active] UDB Interrupt #7 */
|
||||
udb_interrupts_8_IRQn = 130, /*!< 130 [Active] UDB Interrupt #8 */
|
||||
udb_interrupts_9_IRQn = 131, /*!< 131 [Active] UDB Interrupt #9 */
|
||||
udb_interrupts_10_IRQn = 132, /*!< 132 [Active] UDB Interrupt #10 */
|
||||
udb_interrupts_11_IRQn = 133, /*!< 133 [Active] UDB Interrupt #11 */
|
||||
udb_interrupts_12_IRQn = 134, /*!< 134 [Active] UDB Interrupt #12 */
|
||||
udb_interrupts_13_IRQn = 135, /*!< 135 [Active] UDB Interrupt #13 */
|
||||
udb_interrupts_14_IRQn = 136, /*!< 136 [Active] UDB Interrupt #14 */
|
||||
udb_interrupts_15_IRQn = 137, /*!< 137 [Active] UDB Interrupt #15 */
|
||||
pass_interrupt_sar_IRQn = 138, /*!< 138 [Active] SAR ADC interrupt */
|
||||
audioss_interrupt_i2s_IRQn = 139, /*!< 139 [Active] I2S Audio interrupt */
|
||||
audioss_interrupt_pdm_IRQn = 140, /*!< 140 [Active] PDM/PCM Audio interrupt */
|
||||
profile_interrupt_IRQn = 141, /*!< 141 [Active] Energy Profiler interrupt */
|
||||
smif_interrupt_IRQn = 142, /*!< 142 [Active] Serial Memory Interface interrupt */
|
||||
usb_interrupt_hi_IRQn = 143, /*!< 143 [Active] USB Interrupt */
|
||||
usb_interrupt_med_IRQn = 144, /*!< 144 [Active] USB Interrupt */
|
||||
usb_interrupt_lo_IRQn = 145, /*!< 145 [Active] USB Interrupt */
|
||||
pass_interrupt_dacs_IRQn = 146, /*!< 146 [Active] Consolidated interrrupt for all DACs */
|
||||
unconnected_IRQn = 240 /*!< 240 Unconnected */
|
||||
} IRQn_Type;
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Processor and Core Peripheral Section
|
||||
*******************************************************************************/
|
||||
|
||||
/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */
|
||||
#define __CM4_REV 0x0001U /*!< CM4 Core Revision */
|
||||
#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
|
||||
#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */
|
||||
#define __MPU_PRESENT 1 /*!< MPU present or not */
|
||||
#define __FPU_PRESENT 1 /*!< FPU present or not */
|
||||
#define __CM0P_PRESENT 0 /*!< CM0P present or not */
|
||||
|
||||
/** \} Configuration_of_CMSIS */
|
||||
|
||||
/* Memory Blocks */
|
||||
#define CY_ROM_BASE 0x00000000UL
|
||||
#define CY_ROM_SIZE 0x00020000UL
|
||||
#define CY_SRAM0_BASE 0x08000000UL
|
||||
#define CY_SRAM0_SIZE 0x00048000UL
|
||||
#define CY_FLASH_BASE 0x10000000UL
|
||||
#define CY_FLASH_SIZE 0x00100000UL
|
||||
#define CY_EM_EEPROM_BASE 0x14000000UL
|
||||
#define CY_EM_EEPROM_SIZE 0x00008000UL
|
||||
#define CY_XIP_BASE 0x18000000UL
|
||||
#define CY_XIP_SIZE 0x08000000UL
|
||||
#define CY_SFLASH_BASE 0x16000000UL
|
||||
#define CY_SFLASH_SIZE 0x00008000UL
|
||||
#define CY_EFUSE_BASE 0x402C0800UL
|
||||
#define CY_EFUSE_SIZE 0x00000200UL
|
||||
|
||||
#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */
|
||||
#include "system_psoc6.h" /*!< PSoC 6 System */
|
||||
|
||||
/* IP List */
|
||||
#define CY_IP_MXTCPWM 1u
|
||||
#define CY_IP_MXTCPWM_INSTANCES 2u
|
||||
#define CY_IP_MXTCPWM_VERSION 1u
|
||||
#define CY_IP_MXCSDV2 1u
|
||||
#define CY_IP_MXCSDV2_INSTANCES 1u
|
||||
#define CY_IP_MXCSDV2_VERSION 1u
|
||||
#define CY_IP_MXLCD 1u
|
||||
#define CY_IP_MXLCD_INSTANCES 1u
|
||||
#define CY_IP_MXLCD_VERSION 1u
|
||||
#define CY_IP_MXS40SRSS 1u
|
||||
#define CY_IP_MXS40SRSS_INSTANCES 1u
|
||||
#define CY_IP_MXS40SRSS_VERSION 1u
|
||||
#define CY_IP_MXS40SRSS_RTC 1u
|
||||
#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u
|
||||
#define CY_IP_MXS40SRSS_RTC_VERSION 1u
|
||||
#define CY_IP_MXS40SRSS_MCWDT 1u
|
||||
#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u
|
||||
#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u
|
||||
#define CY_IP_MXSCB 1u
|
||||
#define CY_IP_MXSCB_INSTANCES 9u
|
||||
#define CY_IP_MXSCB_VERSION 1u
|
||||
#define CY_IP_MXPERI 1u
|
||||
#define CY_IP_MXPERI_INSTANCES 1u
|
||||
#define CY_IP_MXPERI_VERSION 1u
|
||||
#define CY_IP_MXPERI_TR 1u
|
||||
#define CY_IP_MXPERI_TR_INSTANCES 1u
|
||||
#define CY_IP_MXPERI_TR_VERSION 1u
|
||||
#define CY_IP_M4CPUSS 1u
|
||||
#define CY_IP_M4CPUSS_INSTANCES 1u
|
||||
#define CY_IP_M4CPUSS_VERSION 1u
|
||||
#define CY_IP_M4CPUSS_DMA 1u
|
||||
#define CY_IP_M4CPUSS_DMA_INSTANCES 2u
|
||||
#define CY_IP_M4CPUSS_DMA_VERSION 1u
|
||||
#define CY_IP_MXAUDIOSS 1u
|
||||
#define CY_IP_MXAUDIOSS_INSTANCES 1u
|
||||
#define CY_IP_MXAUDIOSS_VERSION 1u
|
||||
#define CY_IP_MXLPCOMP 1u
|
||||
#define CY_IP_MXLPCOMP_INSTANCES 1u
|
||||
#define CY_IP_MXLPCOMP_VERSION 1u
|
||||
#define CY_IP_MXS40PASS 1u
|
||||
#define CY_IP_MXS40PASS_INSTANCES 1u
|
||||
#define CY_IP_MXS40PASS_VERSION 1u
|
||||
#define CY_IP_MXS40PASS_SAR 1u
|
||||
#define CY_IP_MXS40PASS_SAR_INSTANCES 16u
|
||||
#define CY_IP_MXS40PASS_SAR_VERSION 1u
|
||||
#define CY_IP_MXS40PASS_CTDAC 1u
|
||||
#define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u
|
||||
#define CY_IP_MXS40PASS_CTDAC_VERSION 1u
|
||||
#define CY_IP_MXSMIF 1u
|
||||
#define CY_IP_MXSMIF_INSTANCES 1u
|
||||
#define CY_IP_MXSMIF_VERSION 1u
|
||||
#define CY_IP_MXUSBFS 1u
|
||||
#define CY_IP_MXUSBFS_INSTANCES 1u
|
||||
#define CY_IP_MXUSBFS_VERSION 1u
|
||||
#define CY_IP_MXS40IOSS 1u
|
||||
#define CY_IP_MXS40IOSS_INSTANCES 1u
|
||||
#define CY_IP_MXS40IOSS_VERSION 1u
|
||||
#define CY_IP_MXEFUSE 1u
|
||||
#define CY_IP_MXEFUSE_INSTANCES 1u
|
||||
#define CY_IP_MXEFUSE_VERSION 1u
|
||||
#define CY_IP_MXPROFILE 1u
|
||||
#define CY_IP_MXPROFILE_INSTANCES 1u
|
||||
#define CY_IP_MXPROFILE_VERSION 1u
|
||||
|
||||
#include "psoc6able2_config.h"
|
||||
#include "gpio_psoc6able2_124_bga.h"
|
||||
|
||||
#define CY_DEVICE_PSOC6ABLE2
|
||||
#define CY_SILICON_ID 0xE2152100UL
|
||||
#define CY_HF_CLK_MAX_FREQ 150000000UL
|
||||
|
||||
#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL
|
||||
|
||||
/*******************************************************************************
|
||||
* SFLASH
|
||||
*******************************************************************************/
|
||||
|
||||
#define SFLASH_BASE 0x16000000UL
|
||||
#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* PERI
|
||||
*******************************************************************************/
|
||||
|
||||
#define PERI_BASE 0x40010000UL
|
||||
#define PERI_PPU_GR_MMIO0_BASE 0x40015000UL
|
||||
#define PERI_PPU_GR_MMIO1_BASE 0x40015040UL
|
||||
#define PERI_PPU_GR_MMIO2_BASE 0x40015080UL
|
||||
#define PERI_PPU_GR_MMIO3_BASE 0x400150C0UL
|
||||
#define PERI_PPU_GR_MMIO4_BASE 0x40015100UL
|
||||
#define PERI_PPU_GR_MMIO6_BASE 0x40015180UL
|
||||
#define PERI_PPU_GR_MMIO9_BASE 0x40015240UL
|
||||
#define PERI_PPU_GR_MMIO10_BASE 0x40015280UL
|
||||
#define PERI_GR_PPU_SL_PERI_GR1_BASE 0x40100000UL
|
||||
#define PERI_GR_PPU_SL_CRYPTO_BASE 0x40100040UL
|
||||
#define PERI_GR_PPU_SL_PERI_GR2_BASE 0x40200000UL
|
||||
#define PERI_GR_PPU_SL_CPUSS_BASE 0x40200040UL
|
||||
#define PERI_GR_PPU_SL_FAULT_BASE 0x40200080UL
|
||||
#define PERI_GR_PPU_SL_IPC_BASE 0x402000C0UL
|
||||
#define PERI_GR_PPU_SL_PROT_BASE 0x40200100UL
|
||||
#define PERI_GR_PPU_SL_FLASHC_BASE 0x40200140UL
|
||||
#define PERI_GR_PPU_SL_SRSS_BASE 0x40200180UL
|
||||
#define PERI_GR_PPU_SL_BACKUP_BASE 0x402001C0UL
|
||||
#define PERI_GR_PPU_SL_DW0_BASE 0x40200200UL
|
||||
#define PERI_GR_PPU_SL_DW1_BASE 0x40200240UL
|
||||
#define PERI_GR_PPU_SL_EFUSE_BASE 0x40200300UL
|
||||
#define PERI_GR_PPU_SL_PROFILE_BASE 0x40200340UL
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT0_BASE 0x40201000UL
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT1_BASE 0x40201040UL
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT2_BASE 0x40201080UL
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT3_BASE 0x402010C0UL
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT4_BASE 0x40201100UL
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT5_BASE 0x40201140UL
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT6_BASE 0x40201180UL
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT7_BASE 0x402011C0UL
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT0_BASE 0x40201200UL
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT1_BASE 0x40201240UL
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT2_BASE 0x40201280UL
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT3_BASE 0x402012C0UL
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT4_BASE 0x40201300UL
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT5_BASE 0x40201340UL
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT6_BASE 0x40201380UL
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT7_BASE 0x402013C0UL
|
||||
#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT0_BASE 0x40201400UL
|
||||
#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT1_BASE 0x40201440UL
|
||||
#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT2_BASE 0x40201480UL
|
||||
#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT3_BASE 0x402014C0UL
|
||||
#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT0_BASE 0x40201500UL
|
||||
#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT1_BASE 0x40201540UL
|
||||
#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT2_BASE 0x40201580UL
|
||||
#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT3_BASE 0x402015C0UL
|
||||
#define PERI_GR_PPU_RG_SMPU_BASE 0x40201600UL
|
||||
#define PERI_GR_PPU_RG_MPU_CM0P_BASE 0x40201640UL
|
||||
#define PERI_GR_PPU_RG_MPU_CRYPTO_BASE 0x40201680UL
|
||||
#define PERI_GR_PPU_RG_MPU_CM4_BASE 0x402016C0UL
|
||||
#define PERI_GR_PPU_RG_MPU_TC_BASE 0x40201700UL
|
||||
#define PERI_GR_PPU_SL_PERI_GR3_BASE 0x40300000UL
|
||||
#define PERI_GR_PPU_SL_HSIOM_BASE 0x40300040UL
|
||||
#define PERI_GR_PPU_SL_GPIO_BASE 0x40300080UL
|
||||
#define PERI_GR_PPU_SL_SMARTIO_BASE 0x403000C0UL
|
||||
#define PERI_GR_PPU_SL_UDB_BASE 0x40300100UL
|
||||
#define PERI_GR_PPU_SL_LPCOMP_BASE 0x40300140UL
|
||||
#define PERI_GR_PPU_SL_CSD_BASE 0x40300180UL
|
||||
#define PERI_GR_PPU_SL_TCPWM0_BASE 0x40300200UL
|
||||
#define PERI_GR_PPU_SL_TCPWM1_BASE 0x40300240UL
|
||||
#define PERI_GR_PPU_SL_LCD_BASE 0x40300280UL
|
||||
#define PERI_GR_PPU_SL_BLE_BASE 0x403002C0UL
|
||||
#define PERI_GR_PPU_SL_USBFS_BASE 0x40300300UL
|
||||
#define PERI_GR_PPU_SL_PERI_GR4_BASE 0x40400000UL
|
||||
#define PERI_GR_PPU_SL_SMIF_BASE 0x40400080UL
|
||||
#define PERI_GR_PPU_SL_PERI_GR6_BASE 0x40600000UL
|
||||
#define PERI_GR_PPU_SL_SCB0_BASE 0x40600040UL
|
||||
#define PERI_GR_PPU_SL_SCB1_BASE 0x40600080UL
|
||||
#define PERI_GR_PPU_SL_SCB2_BASE 0x406000C0UL
|
||||
#define PERI_GR_PPU_SL_SCB3_BASE 0x40600100UL
|
||||
#define PERI_GR_PPU_SL_SCB4_BASE 0x40600140UL
|
||||
#define PERI_GR_PPU_SL_SCB5_BASE 0x40600180UL
|
||||
#define PERI_GR_PPU_SL_SCB6_BASE 0x406001C0UL
|
||||
#define PERI_GR_PPU_SL_SCB7_BASE 0x40600200UL
|
||||
#define PERI_GR_PPU_SL_SCB8_BASE 0x40600240UL
|
||||
#define PERI_GR_PPU_SL_PERI_GR9_BASE 0x41000000UL
|
||||
#define PERI_GR_PPU_SL_PASS_BASE 0x41000040UL
|
||||
#define PERI_GR_PPU_SL_PERI_GR10_BASE 0x42A00000UL
|
||||
#define PERI_GR_PPU_SL_I2S_BASE 0x42A00040UL
|
||||
#define PERI_GR_PPU_SL_PDM_BASE 0x42A00080UL
|
||||
#define PERI ((PERI_Type*) PERI_BASE) /* 0x40010000 */
|
||||
#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40010000 */
|
||||
#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40010040 */
|
||||
#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40010080 */
|
||||
#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x400100C0 */
|
||||
#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40010100 */
|
||||
#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x40010180 */
|
||||
#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40010240 */
|
||||
#define PERI_GR10 ((PERI_GR_Type*) &PERI->GR[10]) /* 0x40010280 */
|
||||
#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40012000 */
|
||||
#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40012200 */
|
||||
#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40012400 */
|
||||
#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40012600 */
|
||||
#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40012800 */
|
||||
#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40012A00 */
|
||||
#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40012C00 */
|
||||
#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40012E00 */
|
||||
#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x40013000 */
|
||||
#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x40013200 */
|
||||
#define PERI_TR_GR10 ((PERI_TR_GR_Type*) &PERI->TR_GR[10]) /* 0x40013400 */
|
||||
#define PERI_TR_GR11 ((PERI_TR_GR_Type*) &PERI->TR_GR[11]) /* 0x40013600 */
|
||||
#define PERI_TR_GR12 ((PERI_TR_GR_Type*) &PERI->TR_GR[12]) /* 0x40013800 */
|
||||
#define PERI_TR_GR13 ((PERI_TR_GR_Type*) &PERI->TR_GR[13]) /* 0x40013A00 */
|
||||
#define PERI_TR_GR14 ((PERI_TR_GR_Type*) &PERI->TR_GR[14]) /* 0x40013C00 */
|
||||
#define PERI_PPU_PR0 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[0]) /* 0x40014000 */
|
||||
#define PERI_PPU_PR1 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[1]) /* 0x40014040 */
|
||||
#define PERI_PPU_PR2 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[2]) /* 0x40014080 */
|
||||
#define PERI_PPU_PR3 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[3]) /* 0x400140C0 */
|
||||
#define PERI_PPU_PR4 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[4]) /* 0x40014100 */
|
||||
#define PERI_PPU_PR5 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[5]) /* 0x40014140 */
|
||||
#define PERI_PPU_PR6 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[6]) /* 0x40014180 */
|
||||
#define PERI_PPU_PR7 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[7]) /* 0x400141C0 */
|
||||
#define PERI_PPU_PR8 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[8]) /* 0x40014200 */
|
||||
#define PERI_PPU_PR9 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[9]) /* 0x40014240 */
|
||||
#define PERI_PPU_PR10 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[10]) /* 0x40014280 */
|
||||
#define PERI_PPU_PR11 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[11]) /* 0x400142C0 */
|
||||
#define PERI_PPU_PR12 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[12]) /* 0x40014300 */
|
||||
#define PERI_PPU_PR13 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[13]) /* 0x40014340 */
|
||||
#define PERI_PPU_PR14 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[14]) /* 0x40014380 */
|
||||
#define PERI_PPU_PR15 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[15]) /* 0x400143C0 */
|
||||
#define PERI_PPU_GR0 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[0]) /* 0x40015000 */
|
||||
#define PERI_PPU_GR1 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[1]) /* 0x40015040 */
|
||||
#define PERI_PPU_GR2 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[2]) /* 0x40015080 */
|
||||
#define PERI_PPU_GR3 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[3]) /* 0x400150C0 */
|
||||
#define PERI_PPU_GR4 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[4]) /* 0x40015100 */
|
||||
#define PERI_PPU_GR6 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[6]) /* 0x40015180 */
|
||||
#define PERI_PPU_GR9 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[9]) /* 0x40015240 */
|
||||
#define PERI_PPU_GR10 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[10]) /* 0x40015280 */
|
||||
#define PERI_PPU_GR_MMIO0 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO0_BASE) /* 0x40015000 */
|
||||
#define PERI_PPU_GR_MMIO1 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO1_BASE) /* 0x40015040 */
|
||||
#define PERI_PPU_GR_MMIO2 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO2_BASE) /* 0x40015080 */
|
||||
#define PERI_PPU_GR_MMIO3 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO3_BASE) /* 0x400150C0 */
|
||||
#define PERI_PPU_GR_MMIO4 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO4_BASE) /* 0x40015100 */
|
||||
#define PERI_PPU_GR_MMIO6 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO6_BASE) /* 0x40015180 */
|
||||
#define PERI_PPU_GR_MMIO9 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO9_BASE) /* 0x40015240 */
|
||||
#define PERI_PPU_GR_MMIO10 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO10_BASE) /* 0x40015280 */
|
||||
#define PERI_GR_PPU_SL_PERI_GR1 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR1_BASE) /* 0x40100000 */
|
||||
#define PERI_GR_PPU_SL_CRYPTO ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_CRYPTO_BASE) /* 0x40100040 */
|
||||
#define PERI_GR_PPU_SL_PERI_GR2 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR2_BASE) /* 0x40200000 */
|
||||
#define PERI_GR_PPU_SL_CPUSS ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_CPUSS_BASE) /* 0x40200040 */
|
||||
#define PERI_GR_PPU_SL_FAULT ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_FAULT_BASE) /* 0x40200080 */
|
||||
#define PERI_GR_PPU_SL_IPC ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_IPC_BASE) /* 0x402000C0 */
|
||||
#define PERI_GR_PPU_SL_PROT ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PROT_BASE) /* 0x40200100 */
|
||||
#define PERI_GR_PPU_SL_FLASHC ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_FLASHC_BASE) /* 0x40200140 */
|
||||
#define PERI_GR_PPU_SL_SRSS ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SRSS_BASE) /* 0x40200180 */
|
||||
#define PERI_GR_PPU_SL_BACKUP ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_BACKUP_BASE) /* 0x402001C0 */
|
||||
#define PERI_GR_PPU_SL_DW0 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_DW0_BASE) /* 0x40200200 */
|
||||
#define PERI_GR_PPU_SL_DW1 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_DW1_BASE) /* 0x40200240 */
|
||||
#define PERI_GR_PPU_SL_EFUSE ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_EFUSE_BASE) /* 0x40200300 */
|
||||
#define PERI_GR_PPU_SL_PROFILE ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PROFILE_BASE) /* 0x40200340 */
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT0 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT0_BASE) /* 0x40201000 */
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT1 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT1_BASE) /* 0x40201040 */
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT2 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT2_BASE) /* 0x40201080 */
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT3 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT3_BASE) /* 0x402010C0 */
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT4 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT4_BASE) /* 0x40201100 */
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT5 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT5_BASE) /* 0x40201140 */
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT6 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT6_BASE) /* 0x40201180 */
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT7 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT7_BASE) /* 0x402011C0 */
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT0 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT0_BASE) /* 0x40201200 */
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT1 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT1_BASE) /* 0x40201240 */
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT2 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT2_BASE) /* 0x40201280 */
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT3 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT3_BASE) /* 0x402012C0 */
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT4 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT4_BASE) /* 0x40201300 */
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT5 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT5_BASE) /* 0x40201340 */
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT6 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT6_BASE) /* 0x40201380 */
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT7 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT7_BASE) /* 0x402013C0 */
|
||||
#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT0 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW0_DW_CH_STRUCT0_BASE) /* 0x40201400 */
|
||||
#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT1 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW0_DW_CH_STRUCT1_BASE) /* 0x40201440 */
|
||||
#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT2 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW0_DW_CH_STRUCT2_BASE) /* 0x40201480 */
|
||||
#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT3 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW0_DW_CH_STRUCT3_BASE) /* 0x402014C0 */
|
||||
#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT0 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW1_DW_CH_STRUCT0_BASE) /* 0x40201500 */
|
||||
#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT1 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW1_DW_CH_STRUCT1_BASE) /* 0x40201540 */
|
||||
#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT2 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW1_DW_CH_STRUCT2_BASE) /* 0x40201580 */
|
||||
#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT3 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW1_DW_CH_STRUCT3_BASE) /* 0x402015C0 */
|
||||
#define PERI_GR_PPU_RG_SMPU ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_SMPU_BASE) /* 0x40201600 */
|
||||
#define PERI_GR_PPU_RG_MPU_CM0P ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_MPU_CM0P_BASE) /* 0x40201640 */
|
||||
#define PERI_GR_PPU_RG_MPU_CRYPTO ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_MPU_CRYPTO_BASE) /* 0x40201680 */
|
||||
#define PERI_GR_PPU_RG_MPU_CM4 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_MPU_CM4_BASE) /* 0x402016C0 */
|
||||
#define PERI_GR_PPU_RG_MPU_TC ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_MPU_TC_BASE) /* 0x40201700 */
|
||||
#define PERI_GR_PPU_SL_PERI_GR3 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR3_BASE) /* 0x40300000 */
|
||||
#define PERI_GR_PPU_SL_HSIOM ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_HSIOM_BASE) /* 0x40300040 */
|
||||
#define PERI_GR_PPU_SL_GPIO ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_GPIO_BASE) /* 0x40300080 */
|
||||
#define PERI_GR_PPU_SL_SMARTIO ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SMARTIO_BASE) /* 0x403000C0 */
|
||||
#define PERI_GR_PPU_SL_UDB ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_UDB_BASE) /* 0x40300100 */
|
||||
#define PERI_GR_PPU_SL_LPCOMP ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_LPCOMP_BASE) /* 0x40300140 */
|
||||
#define PERI_GR_PPU_SL_CSD ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_CSD_BASE) /* 0x40300180 */
|
||||
#define PERI_GR_PPU_SL_TCPWM0 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_TCPWM0_BASE) /* 0x40300200 */
|
||||
#define PERI_GR_PPU_SL_TCPWM1 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_TCPWM1_BASE) /* 0x40300240 */
|
||||
#define PERI_GR_PPU_SL_LCD ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_LCD_BASE) /* 0x40300280 */
|
||||
#define PERI_GR_PPU_SL_BLE ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_BLE_BASE) /* 0x403002C0 */
|
||||
#define PERI_GR_PPU_SL_USBFS ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_USBFS_BASE) /* 0x40300300 */
|
||||
#define PERI_GR_PPU_SL_PERI_GR4 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR4_BASE) /* 0x40400000 */
|
||||
#define PERI_GR_PPU_SL_SMIF ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SMIF_BASE) /* 0x40400080 */
|
||||
#define PERI_GR_PPU_SL_PERI_GR6 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR6_BASE) /* 0x40600000 */
|
||||
#define PERI_GR_PPU_SL_SCB0 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB0_BASE) /* 0x40600040 */
|
||||
#define PERI_GR_PPU_SL_SCB1 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB1_BASE) /* 0x40600080 */
|
||||
#define PERI_GR_PPU_SL_SCB2 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB2_BASE) /* 0x406000C0 */
|
||||
#define PERI_GR_PPU_SL_SCB3 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB3_BASE) /* 0x40600100 */
|
||||
#define PERI_GR_PPU_SL_SCB4 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB4_BASE) /* 0x40600140 */
|
||||
#define PERI_GR_PPU_SL_SCB5 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB5_BASE) /* 0x40600180 */
|
||||
#define PERI_GR_PPU_SL_SCB6 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB6_BASE) /* 0x406001C0 */
|
||||
#define PERI_GR_PPU_SL_SCB7 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB7_BASE) /* 0x40600200 */
|
||||
#define PERI_GR_PPU_SL_SCB8 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB8_BASE) /* 0x40600240 */
|
||||
#define PERI_GR_PPU_SL_PERI_GR9 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR9_BASE) /* 0x41000000 */
|
||||
#define PERI_GR_PPU_SL_PASS ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PASS_BASE) /* 0x41000040 */
|
||||
#define PERI_GR_PPU_SL_PERI_GR10 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR10_BASE) /* 0x42A00000 */
|
||||
#define PERI_GR_PPU_SL_I2S ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_I2S_BASE) /* 0x42A00040 */
|
||||
#define PERI_GR_PPU_SL_PDM ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PDM_BASE) /* 0x42A00080 */
|
||||
|
||||
/*******************************************************************************
|
||||
* CPUSS
|
||||
*******************************************************************************/
|
||||
|
||||
#define CPUSS_BASE 0x40210000UL
|
||||
#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40210000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* FAULT
|
||||
*******************************************************************************/
|
||||
|
||||
#define FAULT_BASE 0x40220000UL
|
||||
#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40220000 */
|
||||
#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40220000 */
|
||||
#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40220100 */
|
||||
|
||||
/*******************************************************************************
|
||||
* IPC
|
||||
*******************************************************************************/
|
||||
|
||||
#define IPC_BASE 0x40230000UL
|
||||
#define IPC ((IPC_Type*) IPC_BASE) /* 0x40230000 */
|
||||
#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40230000 */
|
||||
#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40230020 */
|
||||
#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40230040 */
|
||||
#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40230060 */
|
||||
#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40230080 */
|
||||
#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402300A0 */
|
||||
#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402300C0 */
|
||||
#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402300E0 */
|
||||
#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40230100 */
|
||||
#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40230120 */
|
||||
#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40230140 */
|
||||
#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40230160 */
|
||||
#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40230180 */
|
||||
#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402301A0 */
|
||||
#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402301C0 */
|
||||
#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402301E0 */
|
||||
#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40231000 */
|
||||
#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40231020 */
|
||||
#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40231040 */
|
||||
#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40231060 */
|
||||
#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40231080 */
|
||||
#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402310A0 */
|
||||
#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402310C0 */
|
||||
#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402310E0 */
|
||||
#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40231100 */
|
||||
#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40231120 */
|
||||
#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40231140 */
|
||||
#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40231160 */
|
||||
#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40231180 */
|
||||
#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402311A0 */
|
||||
#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402311C0 */
|
||||
#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402311E0 */
|
||||
|
||||
/*******************************************************************************
|
||||
* PROT
|
||||
*******************************************************************************/
|
||||
|
||||
#define PROT_BASE 0x40240000UL
|
||||
#define PROT ((PROT_Type*) PROT_BASE) /* 0x40240000 */
|
||||
#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40242000 */
|
||||
#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40242040 */
|
||||
#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40242080 */
|
||||
#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402420C0 */
|
||||
#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40242100 */
|
||||
#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40242140 */
|
||||
#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40242180 */
|
||||
#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402421C0 */
|
||||
#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40242200 */
|
||||
#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40242240 */
|
||||
#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40242280 */
|
||||
#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402422C0 */
|
||||
#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40242300 */
|
||||
#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40242340 */
|
||||
#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40242380 */
|
||||
#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402423C0 */
|
||||
#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */
|
||||
#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */
|
||||
#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */
|
||||
#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */
|
||||
#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */
|
||||
#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */
|
||||
#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */
|
||||
#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */
|
||||
#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */
|
||||
#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */
|
||||
#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */
|
||||
#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */
|
||||
#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */
|
||||
#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */
|
||||
#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */
|
||||
#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */
|
||||
#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */
|
||||
#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40244000 */
|
||||
#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40244400 */
|
||||
#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40244800 */
|
||||
#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40244C00 */
|
||||
#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40245000 */
|
||||
#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40245400 */
|
||||
#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40245800 */
|
||||
#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40245C00 */
|
||||
#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40246000 */
|
||||
#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40246400 */
|
||||
#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40246800 */
|
||||
#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40246C00 */
|
||||
#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40247000 */
|
||||
#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40247400 */
|
||||
#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40247800 */
|
||||
#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40247C00 */
|
||||
|
||||
/*******************************************************************************
|
||||
* FLASHC
|
||||
*******************************************************************************/
|
||||
|
||||
#define FLASHC_BASE 0x40250000UL
|
||||
#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40250000 */
|
||||
#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4025F000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* SRSS
|
||||
*******************************************************************************/
|
||||
|
||||
#define SRSS_BASE 0x40260000UL
|
||||
#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */
|
||||
#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */
|
||||
#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */
|
||||
|
||||
/*******************************************************************************
|
||||
* BACKUP
|
||||
*******************************************************************************/
|
||||
|
||||
#define BACKUP_BASE 0x40270000UL
|
||||
#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* DW
|
||||
*******************************************************************************/
|
||||
|
||||
#define DW0_BASE 0x40280000UL
|
||||
#define DW1_BASE 0x40281000UL
|
||||
#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */
|
||||
#define DW1 ((DW_Type*) DW1_BASE) /* 0x40281000 */
|
||||
#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40280800 */
|
||||
#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40280820 */
|
||||
#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40280840 */
|
||||
#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x40280860 */
|
||||
#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40280880 */
|
||||
#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x402808A0 */
|
||||
#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x402808C0 */
|
||||
#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402808E0 */
|
||||
#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40280900 */
|
||||
#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40280920 */
|
||||
#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40280940 */
|
||||
#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x40280960 */
|
||||
#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40280980 */
|
||||
#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x402809A0 */
|
||||
#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x402809C0 */
|
||||
#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402809E0 */
|
||||
#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40281800 */
|
||||
#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40281820 */
|
||||
#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40281840 */
|
||||
#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x40281860 */
|
||||
#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40281880 */
|
||||
#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x402818A0 */
|
||||
#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x402818C0 */
|
||||
#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402818E0 */
|
||||
#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40281900 */
|
||||
#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40281920 */
|
||||
#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40281940 */
|
||||
#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x40281960 */
|
||||
#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40281980 */
|
||||
#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x402819A0 */
|
||||
#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x402819C0 */
|
||||
#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402819E0 */
|
||||
|
||||
/*******************************************************************************
|
||||
* EFUSE
|
||||
*******************************************************************************/
|
||||
|
||||
#define EFUSE_BASE 0x402C0000UL
|
||||
#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* PROFILE
|
||||
*******************************************************************************/
|
||||
|
||||
#define PROFILE_BASE 0x402D0000UL
|
||||
#define PROFILE ((PROFILE_Type*) PROFILE_BASE) /* 0x402D0000 */
|
||||
#define PROFILE_CNT_STRUCT0 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[0]) /* 0x402D0800 */
|
||||
#define PROFILE_CNT_STRUCT1 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[1]) /* 0x402D0810 */
|
||||
#define PROFILE_CNT_STRUCT2 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[2]) /* 0x402D0820 */
|
||||
#define PROFILE_CNT_STRUCT3 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[3]) /* 0x402D0830 */
|
||||
#define PROFILE_CNT_STRUCT4 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[4]) /* 0x402D0840 */
|
||||
#define PROFILE_CNT_STRUCT5 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[5]) /* 0x402D0850 */
|
||||
#define PROFILE_CNT_STRUCT6 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[6]) /* 0x402D0860 */
|
||||
#define PROFILE_CNT_STRUCT7 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[7]) /* 0x402D0870 */
|
||||
|
||||
/*******************************************************************************
|
||||
* HSIOM
|
||||
*******************************************************************************/
|
||||
|
||||
#define HSIOM_BASE 0x40310000UL
|
||||
#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40310000 */
|
||||
#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40310000 */
|
||||
#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40310010 */
|
||||
#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40310020 */
|
||||
#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40310030 */
|
||||
#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40310040 */
|
||||
#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40310050 */
|
||||
#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40310060 */
|
||||
#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40310070 */
|
||||
#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40310080 */
|
||||
#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40310090 */
|
||||
#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403100A0 */
|
||||
#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403100B0 */
|
||||
#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403100C0 */
|
||||
#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403100D0 */
|
||||
#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403100E0 */
|
||||
|
||||
/*******************************************************************************
|
||||
* GPIO
|
||||
*******************************************************************************/
|
||||
|
||||
#define GPIO_BASE 0x40320000UL
|
||||
#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40320000 */
|
||||
#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40320000 */
|
||||
#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40320080 */
|
||||
#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40320100 */
|
||||
#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40320180 */
|
||||
#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40320200 */
|
||||
#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40320280 */
|
||||
#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40320300 */
|
||||
#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40320380 */
|
||||
#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40320400 */
|
||||
#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40320480 */
|
||||
#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40320500 */
|
||||
#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40320580 */
|
||||
#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40320600 */
|
||||
#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40320680 */
|
||||
#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40320700 */
|
||||
|
||||
/*******************************************************************************
|
||||
* SMARTIO
|
||||
*******************************************************************************/
|
||||
|
||||
#define SMARTIO_BASE 0x40330000UL
|
||||
#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40330000 */
|
||||
#define SMARTIO_PRT8 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[8]) /* 0x40330800 */
|
||||
#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40330900 */
|
||||
|
||||
/*******************************************************************************
|
||||
* LPCOMP
|
||||
*******************************************************************************/
|
||||
|
||||
#define LPCOMP_BASE 0x40350000UL
|
||||
#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* CSD
|
||||
*******************************************************************************/
|
||||
|
||||
#define CSD0_BASE 0x40360000UL
|
||||
#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* TCPWM
|
||||
*******************************************************************************/
|
||||
|
||||
#define TCPWM0_BASE 0x40380000UL
|
||||
#define TCPWM1_BASE 0x40390000UL
|
||||
#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */
|
||||
#define TCPWM1 ((TCPWM_Type*) TCPWM1_BASE) /* 0x40390000 */
|
||||
#define TCPWM0_CNT0 ((TCPWM_CNT_Type*) &TCPWM0->CNT[0]) /* 0x40380100 */
|
||||
#define TCPWM0_CNT1 ((TCPWM_CNT_Type*) &TCPWM0->CNT[1]) /* 0x40380140 */
|
||||
#define TCPWM0_CNT2 ((TCPWM_CNT_Type*) &TCPWM0->CNT[2]) /* 0x40380180 */
|
||||
#define TCPWM0_CNT3 ((TCPWM_CNT_Type*) &TCPWM0->CNT[3]) /* 0x403801C0 */
|
||||
#define TCPWM0_CNT4 ((TCPWM_CNT_Type*) &TCPWM0->CNT[4]) /* 0x40380200 */
|
||||
#define TCPWM0_CNT5 ((TCPWM_CNT_Type*) &TCPWM0->CNT[5]) /* 0x40380240 */
|
||||
#define TCPWM0_CNT6 ((TCPWM_CNT_Type*) &TCPWM0->CNT[6]) /* 0x40380280 */
|
||||
#define TCPWM0_CNT7 ((TCPWM_CNT_Type*) &TCPWM0->CNT[7]) /* 0x403802C0 */
|
||||
#define TCPWM1_CNT0 ((TCPWM_CNT_Type*) &TCPWM1->CNT[0]) /* 0x40390100 */
|
||||
#define TCPWM1_CNT1 ((TCPWM_CNT_Type*) &TCPWM1->CNT[1]) /* 0x40390140 */
|
||||
#define TCPWM1_CNT2 ((TCPWM_CNT_Type*) &TCPWM1->CNT[2]) /* 0x40390180 */
|
||||
#define TCPWM1_CNT3 ((TCPWM_CNT_Type*) &TCPWM1->CNT[3]) /* 0x403901C0 */
|
||||
#define TCPWM1_CNT4 ((TCPWM_CNT_Type*) &TCPWM1->CNT[4]) /* 0x40390200 */
|
||||
#define TCPWM1_CNT5 ((TCPWM_CNT_Type*) &TCPWM1->CNT[5]) /* 0x40390240 */
|
||||
#define TCPWM1_CNT6 ((TCPWM_CNT_Type*) &TCPWM1->CNT[6]) /* 0x40390280 */
|
||||
#define TCPWM1_CNT7 ((TCPWM_CNT_Type*) &TCPWM1->CNT[7]) /* 0x403902C0 */
|
||||
#define TCPWM1_CNT8 ((TCPWM_CNT_Type*) &TCPWM1->CNT[8]) /* 0x40390300 */
|
||||
#define TCPWM1_CNT9 ((TCPWM_CNT_Type*) &TCPWM1->CNT[9]) /* 0x40390340 */
|
||||
#define TCPWM1_CNT10 ((TCPWM_CNT_Type*) &TCPWM1->CNT[10]) /* 0x40390380 */
|
||||
#define TCPWM1_CNT11 ((TCPWM_CNT_Type*) &TCPWM1->CNT[11]) /* 0x403903C0 */
|
||||
#define TCPWM1_CNT12 ((TCPWM_CNT_Type*) &TCPWM1->CNT[12]) /* 0x40390400 */
|
||||
#define TCPWM1_CNT13 ((TCPWM_CNT_Type*) &TCPWM1->CNT[13]) /* 0x40390440 */
|
||||
#define TCPWM1_CNT14 ((TCPWM_CNT_Type*) &TCPWM1->CNT[14]) /* 0x40390480 */
|
||||
#define TCPWM1_CNT15 ((TCPWM_CNT_Type*) &TCPWM1->CNT[15]) /* 0x403904C0 */
|
||||
#define TCPWM1_CNT16 ((TCPWM_CNT_Type*) &TCPWM1->CNT[16]) /* 0x40390500 */
|
||||
#define TCPWM1_CNT17 ((TCPWM_CNT_Type*) &TCPWM1->CNT[17]) /* 0x40390540 */
|
||||
#define TCPWM1_CNT18 ((TCPWM_CNT_Type*) &TCPWM1->CNT[18]) /* 0x40390580 */
|
||||
#define TCPWM1_CNT19 ((TCPWM_CNT_Type*) &TCPWM1->CNT[19]) /* 0x403905C0 */
|
||||
#define TCPWM1_CNT20 ((TCPWM_CNT_Type*) &TCPWM1->CNT[20]) /* 0x40390600 */
|
||||
#define TCPWM1_CNT21 ((TCPWM_CNT_Type*) &TCPWM1->CNT[21]) /* 0x40390640 */
|
||||
#define TCPWM1_CNT22 ((TCPWM_CNT_Type*) &TCPWM1->CNT[22]) /* 0x40390680 */
|
||||
#define TCPWM1_CNT23 ((TCPWM_CNT_Type*) &TCPWM1->CNT[23]) /* 0x403906C0 */
|
||||
|
||||
/*******************************************************************************
|
||||
* LCD
|
||||
*******************************************************************************/
|
||||
|
||||
#define LCD0_BASE 0x403B0000UL
|
||||
#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* USBFS
|
||||
*******************************************************************************/
|
||||
|
||||
#define USBFS0_BASE 0x403F0000UL
|
||||
#define USBFS0 ((USBFS_Type*) USBFS0_BASE) /* 0x403F0000 */
|
||||
#define USBFS0_USBDEV ((USBFS_USBDEV_Type*) &USBFS0->USBDEV) /* 0x403F0000 */
|
||||
#define USBFS0_USBLPM ((USBFS_USBLPM_Type*) &USBFS0->USBLPM) /* 0x403F2000 */
|
||||
#define USBFS0_USBHOST ((USBFS_USBHOST_Type*) &USBFS0->USBHOST) /* 0x403F4000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* SMIF
|
||||
*******************************************************************************/
|
||||
|
||||
#define SMIF0_BASE 0x40420000UL
|
||||
#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */
|
||||
#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */
|
||||
#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */
|
||||
#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */
|
||||
#define SMIF0_DEVICE3 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[3]) /* 0x40420980 */
|
||||
|
||||
/*******************************************************************************
|
||||
* SCB
|
||||
*******************************************************************************/
|
||||
|
||||
#define SCB0_BASE 0x40610000UL
|
||||
#define SCB1_BASE 0x40620000UL
|
||||
#define SCB2_BASE 0x40630000UL
|
||||
#define SCB3_BASE 0x40640000UL
|
||||
#define SCB4_BASE 0x40650000UL
|
||||
#define SCB5_BASE 0x40660000UL
|
||||
#define SCB6_BASE 0x40670000UL
|
||||
#define SCB7_BASE 0x40680000UL
|
||||
#define SCB8_BASE 0x40690000UL
|
||||
#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40610000 */
|
||||
#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40620000 */
|
||||
#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40630000 */
|
||||
#define SCB3 ((CySCB_Type*) SCB3_BASE) /* 0x40640000 */
|
||||
#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40650000 */
|
||||
#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40660000 */
|
||||
#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40670000 */
|
||||
#define SCB7 ((CySCB_Type*) SCB7_BASE) /* 0x40680000 */
|
||||
#define SCB8 ((CySCB_Type*) SCB8_BASE) /* 0x40690000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* CTDAC
|
||||
*******************************************************************************/
|
||||
|
||||
#define CTDAC0_BASE 0x41140000UL
|
||||
#define CTDAC0 ((CTDAC_Type*) CTDAC0_BASE) /* 0x41140000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* SAR
|
||||
*******************************************************************************/
|
||||
|
||||
#define SAR_BASE 0x411D0000UL
|
||||
#define SAR ((SAR_Type*) SAR_BASE) /* 0x411D0000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* PASS
|
||||
*******************************************************************************/
|
||||
|
||||
#define PASS_BASE 0x411F0000UL
|
||||
#define PASS ((PASS_Type*) PASS_BASE) /* 0x411F0000 */
|
||||
#define PASS_AREF ((PASS_AREF_Type*) &PASS->AREF) /* 0x411F0E00 */
|
||||
|
||||
/*******************************************************************************
|
||||
* I2S
|
||||
*******************************************************************************/
|
||||
|
||||
#define I2S0_BASE 0x42A10000UL
|
||||
#define I2S0 ((I2S_Type*) I2S0_BASE) /* 0x42A10000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* PDM
|
||||
*******************************************************************************/
|
||||
|
||||
#define PDM0_BASE 0x42A20000UL
|
||||
#define PDM0 ((PDM_Type*) PDM0_BASE) /* 0x42A20000 */
|
||||
|
||||
|
||||
/* Backward compabitility definitions */
|
||||
#define I2S I2S0
|
||||
#define PDM PDM0
|
||||
|
||||
/** \} CY8C6137BZI-F14 */
|
||||
|
||||
#endif /* _CY8C6137BZI_F14_H_ */
|
||||
|
||||
|
||||
/* [] END OF FILE */
|
||||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -1,933 +0,0 @@
|
|||
/***************************************************************************//**
|
||||
* \file cy8c6137fdi_f02.h
|
||||
*
|
||||
* \brief
|
||||
* CY8C6137FDI-F02 device header
|
||||
*
|
||||
* \note
|
||||
* Generator version: 1.3.0.1146
|
||||
* Database revision: rev#1050929
|
||||
*
|
||||
********************************************************************************
|
||||
* \copyright
|
||||
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
|
||||
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _CY8C6137FDI_F02_H_
|
||||
#define _CY8C6137FDI_F02_H_
|
||||
|
||||
/**
|
||||
* \addtogroup group_device CY8C6137FDI-F02
|
||||
* \{
|
||||
*/
|
||||
|
||||
/**
|
||||
* \addtogroup Configuration_of_CMSIS
|
||||
* \{
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Interrupt Number Definition
|
||||
*******************************************************************************/
|
||||
|
||||
typedef enum {
|
||||
/* ARM Cortex-M4 Core Interrupt Numbers */
|
||||
Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */
|
||||
NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */
|
||||
HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */
|
||||
MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */
|
||||
BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */
|
||||
UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
|
||||
SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */
|
||||
DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */
|
||||
PendSV_IRQn = -2, /*!< -2 Pendable request for system service */
|
||||
SysTick_IRQn = -1, /*!< -1 System Tick Timer */
|
||||
/* CY8C6137FDI-F02 Peripheral Interrupt Numbers */
|
||||
ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */
|
||||
ioss_interrupts_gpio_1_IRQn = 1, /*!< 1 [DeepSleep] GPIO Port Interrupt #1 */
|
||||
ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */
|
||||
ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */
|
||||
ioss_interrupts_gpio_4_IRQn = 4, /*!< 4 [DeepSleep] GPIO Port Interrupt #4 */
|
||||
ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */
|
||||
ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */
|
||||
ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */
|
||||
ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */
|
||||
ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */
|
||||
ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */
|
||||
ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */
|
||||
ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */
|
||||
ioss_interrupts_gpio_13_IRQn = 13, /*!< 13 [DeepSleep] GPIO Port Interrupt #13 */
|
||||
ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */
|
||||
ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */
|
||||
ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */
|
||||
lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */
|
||||
scb_8_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #8 (DeepSleep capable) */
|
||||
srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */
|
||||
srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */
|
||||
srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */
|
||||
srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */
|
||||
pass_interrupt_ctbs_IRQn = 23, /*!< 23 [DeepSleep] CTBm Interrupt (all CTBms) */
|
||||
bless_interrupt_IRQn = 24, /*!< 24 [DeepSleep] Bluetooth Radio interrupt */
|
||||
cpuss_interrupts_ipc_0_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */
|
||||
cpuss_interrupts_ipc_1_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */
|
||||
cpuss_interrupts_ipc_2_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */
|
||||
cpuss_interrupts_ipc_3_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */
|
||||
cpuss_interrupts_ipc_4_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */
|
||||
cpuss_interrupts_ipc_5_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */
|
||||
cpuss_interrupts_ipc_6_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */
|
||||
cpuss_interrupts_ipc_7_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */
|
||||
cpuss_interrupts_ipc_8_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */
|
||||
cpuss_interrupts_ipc_9_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */
|
||||
cpuss_interrupts_ipc_10_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */
|
||||
cpuss_interrupts_ipc_11_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */
|
||||
cpuss_interrupts_ipc_12_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */
|
||||
cpuss_interrupts_ipc_13_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */
|
||||
cpuss_interrupts_ipc_14_IRQn = 39, /*!< 39 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */
|
||||
cpuss_interrupts_ipc_15_IRQn = 40, /*!< 40 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */
|
||||
scb_0_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #0 */
|
||||
scb_1_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #1 */
|
||||
scb_2_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #2 */
|
||||
scb_3_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #3 */
|
||||
scb_4_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #4 */
|
||||
scb_5_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #5 */
|
||||
scb_6_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #6 */
|
||||
scb_7_interrupt_IRQn = 48, /*!< 48 [Active] Serial Communication Block #7 */
|
||||
csd_interrupt_IRQn = 49, /*!< 49 [Active] CSD (Capsense) interrupt */
|
||||
cpuss_interrupts_dw0_0_IRQn = 50, /*!< 50 [Active] CPUSS DataWire #0, Channel #0 */
|
||||
cpuss_interrupts_dw0_1_IRQn = 51, /*!< 51 [Active] CPUSS DataWire #0, Channel #1 */
|
||||
cpuss_interrupts_dw0_2_IRQn = 52, /*!< 52 [Active] CPUSS DataWire #0, Channel #2 */
|
||||
cpuss_interrupts_dw0_3_IRQn = 53, /*!< 53 [Active] CPUSS DataWire #0, Channel #3 */
|
||||
cpuss_interrupts_dw0_4_IRQn = 54, /*!< 54 [Active] CPUSS DataWire #0, Channel #4 */
|
||||
cpuss_interrupts_dw0_5_IRQn = 55, /*!< 55 [Active] CPUSS DataWire #0, Channel #5 */
|
||||
cpuss_interrupts_dw0_6_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #6 */
|
||||
cpuss_interrupts_dw0_7_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #7 */
|
||||
cpuss_interrupts_dw0_8_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #8 */
|
||||
cpuss_interrupts_dw0_9_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #9 */
|
||||
cpuss_interrupts_dw0_10_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #10 */
|
||||
cpuss_interrupts_dw0_11_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #11 */
|
||||
cpuss_interrupts_dw0_12_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #12 */
|
||||
cpuss_interrupts_dw0_13_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #13 */
|
||||
cpuss_interrupts_dw0_14_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #14 */
|
||||
cpuss_interrupts_dw0_15_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #15 */
|
||||
cpuss_interrupts_dw1_0_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #1, Channel #0 */
|
||||
cpuss_interrupts_dw1_1_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #1, Channel #1 */
|
||||
cpuss_interrupts_dw1_2_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #1, Channel #2 */
|
||||
cpuss_interrupts_dw1_3_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #1, Channel #3 */
|
||||
cpuss_interrupts_dw1_4_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #1, Channel #4 */
|
||||
cpuss_interrupts_dw1_5_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #1, Channel #5 */
|
||||
cpuss_interrupts_dw1_6_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #1, Channel #6 */
|
||||
cpuss_interrupts_dw1_7_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #1, Channel #7 */
|
||||
cpuss_interrupts_dw1_8_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #1, Channel #8 */
|
||||
cpuss_interrupts_dw1_9_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #1, Channel #9 */
|
||||
cpuss_interrupts_dw1_10_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #1, Channel #10 */
|
||||
cpuss_interrupts_dw1_11_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #1, Channel #11 */
|
||||
cpuss_interrupts_dw1_12_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #1, Channel #12 */
|
||||
cpuss_interrupts_dw1_13_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #1, Channel #13 */
|
||||
cpuss_interrupts_dw1_14_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #1, Channel #14 */
|
||||
cpuss_interrupts_dw1_15_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #1, Channel #15 */
|
||||
cpuss_interrupts_fault_0_IRQn = 82, /*!< 82 [Active] CPUSS Fault Structure Interrupt #0 */
|
||||
cpuss_interrupts_fault_1_IRQn = 83, /*!< 83 [Active] CPUSS Fault Structure Interrupt #1 */
|
||||
cpuss_interrupt_crypto_IRQn = 84, /*!< 84 [Active] CRYPTO Accelerator Interrupt */
|
||||
cpuss_interrupt_fm_IRQn = 85, /*!< 85 [Active] FLASH Macro Interrupt */
|
||||
cpuss_interrupts_cm0_cti_0_IRQn = 86, /*!< 86 [Active] CM0+ CTI #0 */
|
||||
cpuss_interrupts_cm0_cti_1_IRQn = 87, /*!< 87 [Active] CM0+ CTI #1 */
|
||||
cpuss_interrupts_cm4_cti_0_IRQn = 88, /*!< 88 [Active] CM4 CTI #0 */
|
||||
cpuss_interrupts_cm4_cti_1_IRQn = 89, /*!< 89 [Active] CM4 CTI #1 */
|
||||
tcpwm_0_interrupts_0_IRQn = 90, /*!< 90 [Active] TCPWM #0, Counter #0 */
|
||||
tcpwm_0_interrupts_1_IRQn = 91, /*!< 91 [Active] TCPWM #0, Counter #1 */
|
||||
tcpwm_0_interrupts_2_IRQn = 92, /*!< 92 [Active] TCPWM #0, Counter #2 */
|
||||
tcpwm_0_interrupts_3_IRQn = 93, /*!< 93 [Active] TCPWM #0, Counter #3 */
|
||||
tcpwm_0_interrupts_4_IRQn = 94, /*!< 94 [Active] TCPWM #0, Counter #4 */
|
||||
tcpwm_0_interrupts_5_IRQn = 95, /*!< 95 [Active] TCPWM #0, Counter #5 */
|
||||
tcpwm_0_interrupts_6_IRQn = 96, /*!< 96 [Active] TCPWM #0, Counter #6 */
|
||||
tcpwm_0_interrupts_7_IRQn = 97, /*!< 97 [Active] TCPWM #0, Counter #7 */
|
||||
tcpwm_1_interrupts_0_IRQn = 98, /*!< 98 [Active] TCPWM #1, Counter #0 */
|
||||
tcpwm_1_interrupts_1_IRQn = 99, /*!< 99 [Active] TCPWM #1, Counter #1 */
|
||||
tcpwm_1_interrupts_2_IRQn = 100, /*!< 100 [Active] TCPWM #1, Counter #2 */
|
||||
tcpwm_1_interrupts_3_IRQn = 101, /*!< 101 [Active] TCPWM #1, Counter #3 */
|
||||
tcpwm_1_interrupts_4_IRQn = 102, /*!< 102 [Active] TCPWM #1, Counter #4 */
|
||||
tcpwm_1_interrupts_5_IRQn = 103, /*!< 103 [Active] TCPWM #1, Counter #5 */
|
||||
tcpwm_1_interrupts_6_IRQn = 104, /*!< 104 [Active] TCPWM #1, Counter #6 */
|
||||
tcpwm_1_interrupts_7_IRQn = 105, /*!< 105 [Active] TCPWM #1, Counter #7 */
|
||||
tcpwm_1_interrupts_8_IRQn = 106, /*!< 106 [Active] TCPWM #1, Counter #8 */
|
||||
tcpwm_1_interrupts_9_IRQn = 107, /*!< 107 [Active] TCPWM #1, Counter #9 */
|
||||
tcpwm_1_interrupts_10_IRQn = 108, /*!< 108 [Active] TCPWM #1, Counter #10 */
|
||||
tcpwm_1_interrupts_11_IRQn = 109, /*!< 109 [Active] TCPWM #1, Counter #11 */
|
||||
tcpwm_1_interrupts_12_IRQn = 110, /*!< 110 [Active] TCPWM #1, Counter #12 */
|
||||
tcpwm_1_interrupts_13_IRQn = 111, /*!< 111 [Active] TCPWM #1, Counter #13 */
|
||||
tcpwm_1_interrupts_14_IRQn = 112, /*!< 112 [Active] TCPWM #1, Counter #14 */
|
||||
tcpwm_1_interrupts_15_IRQn = 113, /*!< 113 [Active] TCPWM #1, Counter #15 */
|
||||
tcpwm_1_interrupts_16_IRQn = 114, /*!< 114 [Active] TCPWM #1, Counter #16 */
|
||||
tcpwm_1_interrupts_17_IRQn = 115, /*!< 115 [Active] TCPWM #1, Counter #17 */
|
||||
tcpwm_1_interrupts_18_IRQn = 116, /*!< 116 [Active] TCPWM #1, Counter #18 */
|
||||
tcpwm_1_interrupts_19_IRQn = 117, /*!< 117 [Active] TCPWM #1, Counter #19 */
|
||||
tcpwm_1_interrupts_20_IRQn = 118, /*!< 118 [Active] TCPWM #1, Counter #20 */
|
||||
tcpwm_1_interrupts_21_IRQn = 119, /*!< 119 [Active] TCPWM #1, Counter #21 */
|
||||
tcpwm_1_interrupts_22_IRQn = 120, /*!< 120 [Active] TCPWM #1, Counter #22 */
|
||||
tcpwm_1_interrupts_23_IRQn = 121, /*!< 121 [Active] TCPWM #1, Counter #23 */
|
||||
udb_interrupts_0_IRQn = 122, /*!< 122 [Active] UDB Interrupt #0 */
|
||||
udb_interrupts_1_IRQn = 123, /*!< 123 [Active] UDB Interrupt #1 */
|
||||
udb_interrupts_2_IRQn = 124, /*!< 124 [Active] UDB Interrupt #2 */
|
||||
udb_interrupts_3_IRQn = 125, /*!< 125 [Active] UDB Interrupt #3 */
|
||||
udb_interrupts_4_IRQn = 126, /*!< 126 [Active] UDB Interrupt #4 */
|
||||
udb_interrupts_5_IRQn = 127, /*!< 127 [Active] UDB Interrupt #5 */
|
||||
udb_interrupts_6_IRQn = 128, /*!< 128 [Active] UDB Interrupt #6 */
|
||||
udb_interrupts_7_IRQn = 129, /*!< 129 [Active] UDB Interrupt #7 */
|
||||
udb_interrupts_8_IRQn = 130, /*!< 130 [Active] UDB Interrupt #8 */
|
||||
udb_interrupts_9_IRQn = 131, /*!< 131 [Active] UDB Interrupt #9 */
|
||||
udb_interrupts_10_IRQn = 132, /*!< 132 [Active] UDB Interrupt #10 */
|
||||
udb_interrupts_11_IRQn = 133, /*!< 133 [Active] UDB Interrupt #11 */
|
||||
udb_interrupts_12_IRQn = 134, /*!< 134 [Active] UDB Interrupt #12 */
|
||||
udb_interrupts_13_IRQn = 135, /*!< 135 [Active] UDB Interrupt #13 */
|
||||
udb_interrupts_14_IRQn = 136, /*!< 136 [Active] UDB Interrupt #14 */
|
||||
udb_interrupts_15_IRQn = 137, /*!< 137 [Active] UDB Interrupt #15 */
|
||||
pass_interrupt_sar_IRQn = 138, /*!< 138 [Active] SAR ADC interrupt */
|
||||
audioss_interrupt_i2s_IRQn = 139, /*!< 139 [Active] I2S Audio interrupt */
|
||||
audioss_interrupt_pdm_IRQn = 140, /*!< 140 [Active] PDM/PCM Audio interrupt */
|
||||
profile_interrupt_IRQn = 141, /*!< 141 [Active] Energy Profiler interrupt */
|
||||
smif_interrupt_IRQn = 142, /*!< 142 [Active] Serial Memory Interface interrupt */
|
||||
usb_interrupt_hi_IRQn = 143, /*!< 143 [Active] USB Interrupt */
|
||||
usb_interrupt_med_IRQn = 144, /*!< 144 [Active] USB Interrupt */
|
||||
usb_interrupt_lo_IRQn = 145, /*!< 145 [Active] USB Interrupt */
|
||||
pass_interrupt_dacs_IRQn = 146, /*!< 146 [Active] Consolidated interrrupt for all DACs */
|
||||
unconnected_IRQn = 240 /*!< 240 Unconnected */
|
||||
} IRQn_Type;
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Processor and Core Peripheral Section
|
||||
*******************************************************************************/
|
||||
|
||||
/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */
|
||||
#define __CM4_REV 0x0001U /*!< CM4 Core Revision */
|
||||
#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
|
||||
#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */
|
||||
#define __MPU_PRESENT 1 /*!< MPU present or not */
|
||||
#define __FPU_PRESENT 1 /*!< FPU present or not */
|
||||
#define __CM0P_PRESENT 0 /*!< CM0P present or not */
|
||||
|
||||
/** \} Configuration_of_CMSIS */
|
||||
|
||||
/* Memory Blocks */
|
||||
#define CY_ROM_BASE 0x00000000UL
|
||||
#define CY_ROM_SIZE 0x00020000UL
|
||||
#define CY_SRAM0_BASE 0x08000000UL
|
||||
#define CY_SRAM0_SIZE 0x00048000UL
|
||||
#define CY_FLASH_BASE 0x10000000UL
|
||||
#define CY_FLASH_SIZE 0x00100000UL
|
||||
#define CY_EM_EEPROM_BASE 0x14000000UL
|
||||
#define CY_EM_EEPROM_SIZE 0x00008000UL
|
||||
#define CY_XIP_BASE 0x18000000UL
|
||||
#define CY_XIP_SIZE 0x08000000UL
|
||||
#define CY_SFLASH_BASE 0x16000000UL
|
||||
#define CY_SFLASH_SIZE 0x00008000UL
|
||||
#define CY_EFUSE_BASE 0x402C0800UL
|
||||
#define CY_EFUSE_SIZE 0x00000200UL
|
||||
|
||||
#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */
|
||||
#include "system_psoc6.h" /*!< PSoC 6 System */
|
||||
|
||||
/* IP List */
|
||||
#define CY_IP_MXTCPWM 1u
|
||||
#define CY_IP_MXTCPWM_INSTANCES 2u
|
||||
#define CY_IP_MXTCPWM_VERSION 1u
|
||||
#define CY_IP_MXCSDV2 1u
|
||||
#define CY_IP_MXCSDV2_INSTANCES 1u
|
||||
#define CY_IP_MXCSDV2_VERSION 1u
|
||||
#define CY_IP_MXLCD 1u
|
||||
#define CY_IP_MXLCD_INSTANCES 1u
|
||||
#define CY_IP_MXLCD_VERSION 1u
|
||||
#define CY_IP_MXS40SRSS 1u
|
||||
#define CY_IP_MXS40SRSS_INSTANCES 1u
|
||||
#define CY_IP_MXS40SRSS_VERSION 1u
|
||||
#define CY_IP_MXS40SRSS_RTC 1u
|
||||
#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u
|
||||
#define CY_IP_MXS40SRSS_RTC_VERSION 1u
|
||||
#define CY_IP_MXS40SRSS_MCWDT 1u
|
||||
#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u
|
||||
#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u
|
||||
#define CY_IP_MXSCB 1u
|
||||
#define CY_IP_MXSCB_INSTANCES 9u
|
||||
#define CY_IP_MXSCB_VERSION 1u
|
||||
#define CY_IP_MXPERI 1u
|
||||
#define CY_IP_MXPERI_INSTANCES 1u
|
||||
#define CY_IP_MXPERI_VERSION 1u
|
||||
#define CY_IP_MXPERI_TR 1u
|
||||
#define CY_IP_MXPERI_TR_INSTANCES 1u
|
||||
#define CY_IP_MXPERI_TR_VERSION 1u
|
||||
#define CY_IP_M4CPUSS 1u
|
||||
#define CY_IP_M4CPUSS_INSTANCES 1u
|
||||
#define CY_IP_M4CPUSS_VERSION 1u
|
||||
#define CY_IP_M4CPUSS_DMA 1u
|
||||
#define CY_IP_M4CPUSS_DMA_INSTANCES 2u
|
||||
#define CY_IP_M4CPUSS_DMA_VERSION 1u
|
||||
#define CY_IP_MXAUDIOSS 1u
|
||||
#define CY_IP_MXAUDIOSS_INSTANCES 1u
|
||||
#define CY_IP_MXAUDIOSS_VERSION 1u
|
||||
#define CY_IP_MXLPCOMP 1u
|
||||
#define CY_IP_MXLPCOMP_INSTANCES 1u
|
||||
#define CY_IP_MXLPCOMP_VERSION 1u
|
||||
#define CY_IP_MXS40PASS 1u
|
||||
#define CY_IP_MXS40PASS_INSTANCES 1u
|
||||
#define CY_IP_MXS40PASS_VERSION 1u
|
||||
#define CY_IP_MXS40PASS_SAR 1u
|
||||
#define CY_IP_MXS40PASS_SAR_INSTANCES 16u
|
||||
#define CY_IP_MXS40PASS_SAR_VERSION 1u
|
||||
#define CY_IP_MXS40PASS_CTDAC 1u
|
||||
#define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u
|
||||
#define CY_IP_MXS40PASS_CTDAC_VERSION 1u
|
||||
#define CY_IP_MXSMIF 1u
|
||||
#define CY_IP_MXSMIF_INSTANCES 1u
|
||||
#define CY_IP_MXSMIF_VERSION 1u
|
||||
#define CY_IP_MXUSBFS 1u
|
||||
#define CY_IP_MXUSBFS_INSTANCES 1u
|
||||
#define CY_IP_MXUSBFS_VERSION 1u
|
||||
#define CY_IP_MXS40IOSS 1u
|
||||
#define CY_IP_MXS40IOSS_INSTANCES 1u
|
||||
#define CY_IP_MXS40IOSS_VERSION 1u
|
||||
#define CY_IP_MXEFUSE 1u
|
||||
#define CY_IP_MXEFUSE_INSTANCES 1u
|
||||
#define CY_IP_MXEFUSE_VERSION 1u
|
||||
#define CY_IP_MXPROFILE 1u
|
||||
#define CY_IP_MXPROFILE_INSTANCES 1u
|
||||
#define CY_IP_MXPROFILE_VERSION 1u
|
||||
|
||||
#include "psoc6able2_config.h"
|
||||
#include "gpio_psoc6able2_80_wlcsp.h"
|
||||
|
||||
#define CY_DEVICE_PSOC6ABLE2
|
||||
#define CY_SILICON_ID 0xE2302100UL
|
||||
#define CY_HF_CLK_MAX_FREQ 150000000UL
|
||||
|
||||
#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL
|
||||
|
||||
/*******************************************************************************
|
||||
* SFLASH
|
||||
*******************************************************************************/
|
||||
|
||||
#define SFLASH_BASE 0x16000000UL
|
||||
#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* PERI
|
||||
*******************************************************************************/
|
||||
|
||||
#define PERI_BASE 0x40010000UL
|
||||
#define PERI_PPU_GR_MMIO0_BASE 0x40015000UL
|
||||
#define PERI_PPU_GR_MMIO1_BASE 0x40015040UL
|
||||
#define PERI_PPU_GR_MMIO2_BASE 0x40015080UL
|
||||
#define PERI_PPU_GR_MMIO3_BASE 0x400150C0UL
|
||||
#define PERI_PPU_GR_MMIO4_BASE 0x40015100UL
|
||||
#define PERI_PPU_GR_MMIO6_BASE 0x40015180UL
|
||||
#define PERI_PPU_GR_MMIO9_BASE 0x40015240UL
|
||||
#define PERI_PPU_GR_MMIO10_BASE 0x40015280UL
|
||||
#define PERI_GR_PPU_SL_PERI_GR1_BASE 0x40100000UL
|
||||
#define PERI_GR_PPU_SL_CRYPTO_BASE 0x40100040UL
|
||||
#define PERI_GR_PPU_SL_PERI_GR2_BASE 0x40200000UL
|
||||
#define PERI_GR_PPU_SL_CPUSS_BASE 0x40200040UL
|
||||
#define PERI_GR_PPU_SL_FAULT_BASE 0x40200080UL
|
||||
#define PERI_GR_PPU_SL_IPC_BASE 0x402000C0UL
|
||||
#define PERI_GR_PPU_SL_PROT_BASE 0x40200100UL
|
||||
#define PERI_GR_PPU_SL_FLASHC_BASE 0x40200140UL
|
||||
#define PERI_GR_PPU_SL_SRSS_BASE 0x40200180UL
|
||||
#define PERI_GR_PPU_SL_BACKUP_BASE 0x402001C0UL
|
||||
#define PERI_GR_PPU_SL_DW0_BASE 0x40200200UL
|
||||
#define PERI_GR_PPU_SL_DW1_BASE 0x40200240UL
|
||||
#define PERI_GR_PPU_SL_EFUSE_BASE 0x40200300UL
|
||||
#define PERI_GR_PPU_SL_PROFILE_BASE 0x40200340UL
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT0_BASE 0x40201000UL
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT1_BASE 0x40201040UL
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT2_BASE 0x40201080UL
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT3_BASE 0x402010C0UL
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT4_BASE 0x40201100UL
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT5_BASE 0x40201140UL
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT6_BASE 0x40201180UL
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT7_BASE 0x402011C0UL
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT0_BASE 0x40201200UL
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT1_BASE 0x40201240UL
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT2_BASE 0x40201280UL
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT3_BASE 0x402012C0UL
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT4_BASE 0x40201300UL
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT5_BASE 0x40201340UL
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT6_BASE 0x40201380UL
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT7_BASE 0x402013C0UL
|
||||
#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT0_BASE 0x40201400UL
|
||||
#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT1_BASE 0x40201440UL
|
||||
#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT2_BASE 0x40201480UL
|
||||
#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT3_BASE 0x402014C0UL
|
||||
#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT0_BASE 0x40201500UL
|
||||
#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT1_BASE 0x40201540UL
|
||||
#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT2_BASE 0x40201580UL
|
||||
#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT3_BASE 0x402015C0UL
|
||||
#define PERI_GR_PPU_RG_SMPU_BASE 0x40201600UL
|
||||
#define PERI_GR_PPU_RG_MPU_CM0P_BASE 0x40201640UL
|
||||
#define PERI_GR_PPU_RG_MPU_CRYPTO_BASE 0x40201680UL
|
||||
#define PERI_GR_PPU_RG_MPU_CM4_BASE 0x402016C0UL
|
||||
#define PERI_GR_PPU_RG_MPU_TC_BASE 0x40201700UL
|
||||
#define PERI_GR_PPU_SL_PERI_GR3_BASE 0x40300000UL
|
||||
#define PERI_GR_PPU_SL_HSIOM_BASE 0x40300040UL
|
||||
#define PERI_GR_PPU_SL_GPIO_BASE 0x40300080UL
|
||||
#define PERI_GR_PPU_SL_SMARTIO_BASE 0x403000C0UL
|
||||
#define PERI_GR_PPU_SL_UDB_BASE 0x40300100UL
|
||||
#define PERI_GR_PPU_SL_LPCOMP_BASE 0x40300140UL
|
||||
#define PERI_GR_PPU_SL_CSD_BASE 0x40300180UL
|
||||
#define PERI_GR_PPU_SL_TCPWM0_BASE 0x40300200UL
|
||||
#define PERI_GR_PPU_SL_TCPWM1_BASE 0x40300240UL
|
||||
#define PERI_GR_PPU_SL_LCD_BASE 0x40300280UL
|
||||
#define PERI_GR_PPU_SL_BLE_BASE 0x403002C0UL
|
||||
#define PERI_GR_PPU_SL_USBFS_BASE 0x40300300UL
|
||||
#define PERI_GR_PPU_SL_PERI_GR4_BASE 0x40400000UL
|
||||
#define PERI_GR_PPU_SL_SMIF_BASE 0x40400080UL
|
||||
#define PERI_GR_PPU_SL_PERI_GR6_BASE 0x40600000UL
|
||||
#define PERI_GR_PPU_SL_SCB0_BASE 0x40600040UL
|
||||
#define PERI_GR_PPU_SL_SCB1_BASE 0x40600080UL
|
||||
#define PERI_GR_PPU_SL_SCB2_BASE 0x406000C0UL
|
||||
#define PERI_GR_PPU_SL_SCB3_BASE 0x40600100UL
|
||||
#define PERI_GR_PPU_SL_SCB4_BASE 0x40600140UL
|
||||
#define PERI_GR_PPU_SL_SCB5_BASE 0x40600180UL
|
||||
#define PERI_GR_PPU_SL_SCB6_BASE 0x406001C0UL
|
||||
#define PERI_GR_PPU_SL_SCB7_BASE 0x40600200UL
|
||||
#define PERI_GR_PPU_SL_SCB8_BASE 0x40600240UL
|
||||
#define PERI_GR_PPU_SL_PERI_GR9_BASE 0x41000000UL
|
||||
#define PERI_GR_PPU_SL_PASS_BASE 0x41000040UL
|
||||
#define PERI_GR_PPU_SL_PERI_GR10_BASE 0x42A00000UL
|
||||
#define PERI_GR_PPU_SL_I2S_BASE 0x42A00040UL
|
||||
#define PERI_GR_PPU_SL_PDM_BASE 0x42A00080UL
|
||||
#define PERI ((PERI_Type*) PERI_BASE) /* 0x40010000 */
|
||||
#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40010000 */
|
||||
#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40010040 */
|
||||
#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40010080 */
|
||||
#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x400100C0 */
|
||||
#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40010100 */
|
||||
#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x40010180 */
|
||||
#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40010240 */
|
||||
#define PERI_GR10 ((PERI_GR_Type*) &PERI->GR[10]) /* 0x40010280 */
|
||||
#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40012000 */
|
||||
#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40012200 */
|
||||
#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40012400 */
|
||||
#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40012600 */
|
||||
#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40012800 */
|
||||
#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40012A00 */
|
||||
#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40012C00 */
|
||||
#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40012E00 */
|
||||
#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x40013000 */
|
||||
#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x40013200 */
|
||||
#define PERI_TR_GR10 ((PERI_TR_GR_Type*) &PERI->TR_GR[10]) /* 0x40013400 */
|
||||
#define PERI_TR_GR11 ((PERI_TR_GR_Type*) &PERI->TR_GR[11]) /* 0x40013600 */
|
||||
#define PERI_TR_GR12 ((PERI_TR_GR_Type*) &PERI->TR_GR[12]) /* 0x40013800 */
|
||||
#define PERI_TR_GR13 ((PERI_TR_GR_Type*) &PERI->TR_GR[13]) /* 0x40013A00 */
|
||||
#define PERI_TR_GR14 ((PERI_TR_GR_Type*) &PERI->TR_GR[14]) /* 0x40013C00 */
|
||||
#define PERI_PPU_PR0 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[0]) /* 0x40014000 */
|
||||
#define PERI_PPU_PR1 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[1]) /* 0x40014040 */
|
||||
#define PERI_PPU_PR2 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[2]) /* 0x40014080 */
|
||||
#define PERI_PPU_PR3 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[3]) /* 0x400140C0 */
|
||||
#define PERI_PPU_PR4 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[4]) /* 0x40014100 */
|
||||
#define PERI_PPU_PR5 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[5]) /* 0x40014140 */
|
||||
#define PERI_PPU_PR6 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[6]) /* 0x40014180 */
|
||||
#define PERI_PPU_PR7 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[7]) /* 0x400141C0 */
|
||||
#define PERI_PPU_PR8 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[8]) /* 0x40014200 */
|
||||
#define PERI_PPU_PR9 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[9]) /* 0x40014240 */
|
||||
#define PERI_PPU_PR10 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[10]) /* 0x40014280 */
|
||||
#define PERI_PPU_PR11 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[11]) /* 0x400142C0 */
|
||||
#define PERI_PPU_PR12 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[12]) /* 0x40014300 */
|
||||
#define PERI_PPU_PR13 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[13]) /* 0x40014340 */
|
||||
#define PERI_PPU_PR14 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[14]) /* 0x40014380 */
|
||||
#define PERI_PPU_PR15 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[15]) /* 0x400143C0 */
|
||||
#define PERI_PPU_GR0 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[0]) /* 0x40015000 */
|
||||
#define PERI_PPU_GR1 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[1]) /* 0x40015040 */
|
||||
#define PERI_PPU_GR2 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[2]) /* 0x40015080 */
|
||||
#define PERI_PPU_GR3 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[3]) /* 0x400150C0 */
|
||||
#define PERI_PPU_GR4 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[4]) /* 0x40015100 */
|
||||
#define PERI_PPU_GR6 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[6]) /* 0x40015180 */
|
||||
#define PERI_PPU_GR9 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[9]) /* 0x40015240 */
|
||||
#define PERI_PPU_GR10 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[10]) /* 0x40015280 */
|
||||
#define PERI_PPU_GR_MMIO0 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO0_BASE) /* 0x40015000 */
|
||||
#define PERI_PPU_GR_MMIO1 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO1_BASE) /* 0x40015040 */
|
||||
#define PERI_PPU_GR_MMIO2 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO2_BASE) /* 0x40015080 */
|
||||
#define PERI_PPU_GR_MMIO3 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO3_BASE) /* 0x400150C0 */
|
||||
#define PERI_PPU_GR_MMIO4 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO4_BASE) /* 0x40015100 */
|
||||
#define PERI_PPU_GR_MMIO6 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO6_BASE) /* 0x40015180 */
|
||||
#define PERI_PPU_GR_MMIO9 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO9_BASE) /* 0x40015240 */
|
||||
#define PERI_PPU_GR_MMIO10 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO10_BASE) /* 0x40015280 */
|
||||
#define PERI_GR_PPU_SL_PERI_GR1 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR1_BASE) /* 0x40100000 */
|
||||
#define PERI_GR_PPU_SL_CRYPTO ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_CRYPTO_BASE) /* 0x40100040 */
|
||||
#define PERI_GR_PPU_SL_PERI_GR2 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR2_BASE) /* 0x40200000 */
|
||||
#define PERI_GR_PPU_SL_CPUSS ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_CPUSS_BASE) /* 0x40200040 */
|
||||
#define PERI_GR_PPU_SL_FAULT ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_FAULT_BASE) /* 0x40200080 */
|
||||
#define PERI_GR_PPU_SL_IPC ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_IPC_BASE) /* 0x402000C0 */
|
||||
#define PERI_GR_PPU_SL_PROT ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PROT_BASE) /* 0x40200100 */
|
||||
#define PERI_GR_PPU_SL_FLASHC ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_FLASHC_BASE) /* 0x40200140 */
|
||||
#define PERI_GR_PPU_SL_SRSS ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SRSS_BASE) /* 0x40200180 */
|
||||
#define PERI_GR_PPU_SL_BACKUP ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_BACKUP_BASE) /* 0x402001C0 */
|
||||
#define PERI_GR_PPU_SL_DW0 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_DW0_BASE) /* 0x40200200 */
|
||||
#define PERI_GR_PPU_SL_DW1 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_DW1_BASE) /* 0x40200240 */
|
||||
#define PERI_GR_PPU_SL_EFUSE ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_EFUSE_BASE) /* 0x40200300 */
|
||||
#define PERI_GR_PPU_SL_PROFILE ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PROFILE_BASE) /* 0x40200340 */
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT0 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT0_BASE) /* 0x40201000 */
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT1 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT1_BASE) /* 0x40201040 */
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT2 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT2_BASE) /* 0x40201080 */
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT3 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT3_BASE) /* 0x402010C0 */
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT4 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT4_BASE) /* 0x40201100 */
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT5 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT5_BASE) /* 0x40201140 */
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT6 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT6_BASE) /* 0x40201180 */
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT7 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT7_BASE) /* 0x402011C0 */
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT0 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT0_BASE) /* 0x40201200 */
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT1 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT1_BASE) /* 0x40201240 */
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT2 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT2_BASE) /* 0x40201280 */
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT3 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT3_BASE) /* 0x402012C0 */
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT4 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT4_BASE) /* 0x40201300 */
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT5 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT5_BASE) /* 0x40201340 */
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT6 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT6_BASE) /* 0x40201380 */
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT7 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT7_BASE) /* 0x402013C0 */
|
||||
#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT0 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW0_DW_CH_STRUCT0_BASE) /* 0x40201400 */
|
||||
#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT1 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW0_DW_CH_STRUCT1_BASE) /* 0x40201440 */
|
||||
#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT2 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW0_DW_CH_STRUCT2_BASE) /* 0x40201480 */
|
||||
#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT3 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW0_DW_CH_STRUCT3_BASE) /* 0x402014C0 */
|
||||
#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT0 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW1_DW_CH_STRUCT0_BASE) /* 0x40201500 */
|
||||
#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT1 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW1_DW_CH_STRUCT1_BASE) /* 0x40201540 */
|
||||
#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT2 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW1_DW_CH_STRUCT2_BASE) /* 0x40201580 */
|
||||
#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT3 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW1_DW_CH_STRUCT3_BASE) /* 0x402015C0 */
|
||||
#define PERI_GR_PPU_RG_SMPU ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_SMPU_BASE) /* 0x40201600 */
|
||||
#define PERI_GR_PPU_RG_MPU_CM0P ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_MPU_CM0P_BASE) /* 0x40201640 */
|
||||
#define PERI_GR_PPU_RG_MPU_CRYPTO ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_MPU_CRYPTO_BASE) /* 0x40201680 */
|
||||
#define PERI_GR_PPU_RG_MPU_CM4 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_MPU_CM4_BASE) /* 0x402016C0 */
|
||||
#define PERI_GR_PPU_RG_MPU_TC ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_MPU_TC_BASE) /* 0x40201700 */
|
||||
#define PERI_GR_PPU_SL_PERI_GR3 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR3_BASE) /* 0x40300000 */
|
||||
#define PERI_GR_PPU_SL_HSIOM ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_HSIOM_BASE) /* 0x40300040 */
|
||||
#define PERI_GR_PPU_SL_GPIO ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_GPIO_BASE) /* 0x40300080 */
|
||||
#define PERI_GR_PPU_SL_SMARTIO ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SMARTIO_BASE) /* 0x403000C0 */
|
||||
#define PERI_GR_PPU_SL_UDB ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_UDB_BASE) /* 0x40300100 */
|
||||
#define PERI_GR_PPU_SL_LPCOMP ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_LPCOMP_BASE) /* 0x40300140 */
|
||||
#define PERI_GR_PPU_SL_CSD ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_CSD_BASE) /* 0x40300180 */
|
||||
#define PERI_GR_PPU_SL_TCPWM0 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_TCPWM0_BASE) /* 0x40300200 */
|
||||
#define PERI_GR_PPU_SL_TCPWM1 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_TCPWM1_BASE) /* 0x40300240 */
|
||||
#define PERI_GR_PPU_SL_LCD ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_LCD_BASE) /* 0x40300280 */
|
||||
#define PERI_GR_PPU_SL_BLE ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_BLE_BASE) /* 0x403002C0 */
|
||||
#define PERI_GR_PPU_SL_USBFS ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_USBFS_BASE) /* 0x40300300 */
|
||||
#define PERI_GR_PPU_SL_PERI_GR4 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR4_BASE) /* 0x40400000 */
|
||||
#define PERI_GR_PPU_SL_SMIF ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SMIF_BASE) /* 0x40400080 */
|
||||
#define PERI_GR_PPU_SL_PERI_GR6 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR6_BASE) /* 0x40600000 */
|
||||
#define PERI_GR_PPU_SL_SCB0 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB0_BASE) /* 0x40600040 */
|
||||
#define PERI_GR_PPU_SL_SCB1 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB1_BASE) /* 0x40600080 */
|
||||
#define PERI_GR_PPU_SL_SCB2 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB2_BASE) /* 0x406000C0 */
|
||||
#define PERI_GR_PPU_SL_SCB3 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB3_BASE) /* 0x40600100 */
|
||||
#define PERI_GR_PPU_SL_SCB4 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB4_BASE) /* 0x40600140 */
|
||||
#define PERI_GR_PPU_SL_SCB5 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB5_BASE) /* 0x40600180 */
|
||||
#define PERI_GR_PPU_SL_SCB6 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB6_BASE) /* 0x406001C0 */
|
||||
#define PERI_GR_PPU_SL_SCB7 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB7_BASE) /* 0x40600200 */
|
||||
#define PERI_GR_PPU_SL_SCB8 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB8_BASE) /* 0x40600240 */
|
||||
#define PERI_GR_PPU_SL_PERI_GR9 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR9_BASE) /* 0x41000000 */
|
||||
#define PERI_GR_PPU_SL_PASS ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PASS_BASE) /* 0x41000040 */
|
||||
#define PERI_GR_PPU_SL_PERI_GR10 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR10_BASE) /* 0x42A00000 */
|
||||
#define PERI_GR_PPU_SL_I2S ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_I2S_BASE) /* 0x42A00040 */
|
||||
#define PERI_GR_PPU_SL_PDM ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PDM_BASE) /* 0x42A00080 */
|
||||
|
||||
/*******************************************************************************
|
||||
* CPUSS
|
||||
*******************************************************************************/
|
||||
|
||||
#define CPUSS_BASE 0x40210000UL
|
||||
#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40210000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* FAULT
|
||||
*******************************************************************************/
|
||||
|
||||
#define FAULT_BASE 0x40220000UL
|
||||
#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40220000 */
|
||||
#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40220000 */
|
||||
#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40220100 */
|
||||
|
||||
/*******************************************************************************
|
||||
* IPC
|
||||
*******************************************************************************/
|
||||
|
||||
#define IPC_BASE 0x40230000UL
|
||||
#define IPC ((IPC_Type*) IPC_BASE) /* 0x40230000 */
|
||||
#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40230000 */
|
||||
#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40230020 */
|
||||
#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40230040 */
|
||||
#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40230060 */
|
||||
#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40230080 */
|
||||
#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402300A0 */
|
||||
#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402300C0 */
|
||||
#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402300E0 */
|
||||
#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40230100 */
|
||||
#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40230120 */
|
||||
#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40230140 */
|
||||
#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40230160 */
|
||||
#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40230180 */
|
||||
#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402301A0 */
|
||||
#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402301C0 */
|
||||
#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402301E0 */
|
||||
#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40231000 */
|
||||
#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40231020 */
|
||||
#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40231040 */
|
||||
#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40231060 */
|
||||
#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40231080 */
|
||||
#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402310A0 */
|
||||
#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402310C0 */
|
||||
#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402310E0 */
|
||||
#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40231100 */
|
||||
#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40231120 */
|
||||
#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40231140 */
|
||||
#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40231160 */
|
||||
#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40231180 */
|
||||
#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402311A0 */
|
||||
#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402311C0 */
|
||||
#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402311E0 */
|
||||
|
||||
/*******************************************************************************
|
||||
* PROT
|
||||
*******************************************************************************/
|
||||
|
||||
#define PROT_BASE 0x40240000UL
|
||||
#define PROT ((PROT_Type*) PROT_BASE) /* 0x40240000 */
|
||||
#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40242000 */
|
||||
#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40242040 */
|
||||
#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40242080 */
|
||||
#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402420C0 */
|
||||
#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40242100 */
|
||||
#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40242140 */
|
||||
#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40242180 */
|
||||
#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402421C0 */
|
||||
#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40242200 */
|
||||
#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40242240 */
|
||||
#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40242280 */
|
||||
#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402422C0 */
|
||||
#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40242300 */
|
||||
#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40242340 */
|
||||
#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40242380 */
|
||||
#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402423C0 */
|
||||
#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */
|
||||
#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */
|
||||
#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */
|
||||
#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */
|
||||
#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */
|
||||
#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */
|
||||
#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */
|
||||
#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */
|
||||
#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */
|
||||
#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */
|
||||
#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */
|
||||
#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */
|
||||
#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */
|
||||
#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */
|
||||
#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */
|
||||
#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */
|
||||
#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */
|
||||
#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40244000 */
|
||||
#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40244400 */
|
||||
#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40244800 */
|
||||
#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40244C00 */
|
||||
#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40245000 */
|
||||
#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40245400 */
|
||||
#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40245800 */
|
||||
#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40245C00 */
|
||||
#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40246000 */
|
||||
#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40246400 */
|
||||
#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40246800 */
|
||||
#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40246C00 */
|
||||
#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40247000 */
|
||||
#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40247400 */
|
||||
#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40247800 */
|
||||
#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40247C00 */
|
||||
|
||||
/*******************************************************************************
|
||||
* FLASHC
|
||||
*******************************************************************************/
|
||||
|
||||
#define FLASHC_BASE 0x40250000UL
|
||||
#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40250000 */
|
||||
#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4025F000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* SRSS
|
||||
*******************************************************************************/
|
||||
|
||||
#define SRSS_BASE 0x40260000UL
|
||||
#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */
|
||||
#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */
|
||||
#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */
|
||||
|
||||
/*******************************************************************************
|
||||
* BACKUP
|
||||
*******************************************************************************/
|
||||
|
||||
#define BACKUP_BASE 0x40270000UL
|
||||
#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* DW
|
||||
*******************************************************************************/
|
||||
|
||||
#define DW0_BASE 0x40280000UL
|
||||
#define DW1_BASE 0x40281000UL
|
||||
#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */
|
||||
#define DW1 ((DW_Type*) DW1_BASE) /* 0x40281000 */
|
||||
#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40280800 */
|
||||
#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40280820 */
|
||||
#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40280840 */
|
||||
#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x40280860 */
|
||||
#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40280880 */
|
||||
#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x402808A0 */
|
||||
#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x402808C0 */
|
||||
#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402808E0 */
|
||||
#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40280900 */
|
||||
#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40280920 */
|
||||
#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40280940 */
|
||||
#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x40280960 */
|
||||
#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40280980 */
|
||||
#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x402809A0 */
|
||||
#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x402809C0 */
|
||||
#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402809E0 */
|
||||
#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40281800 */
|
||||
#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40281820 */
|
||||
#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40281840 */
|
||||
#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x40281860 */
|
||||
#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40281880 */
|
||||
#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x402818A0 */
|
||||
#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x402818C0 */
|
||||
#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402818E0 */
|
||||
#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40281900 */
|
||||
#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40281920 */
|
||||
#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40281940 */
|
||||
#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x40281960 */
|
||||
#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40281980 */
|
||||
#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x402819A0 */
|
||||
#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x402819C0 */
|
||||
#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402819E0 */
|
||||
|
||||
/*******************************************************************************
|
||||
* EFUSE
|
||||
*******************************************************************************/
|
||||
|
||||
#define EFUSE_BASE 0x402C0000UL
|
||||
#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* PROFILE
|
||||
*******************************************************************************/
|
||||
|
||||
#define PROFILE_BASE 0x402D0000UL
|
||||
#define PROFILE ((PROFILE_Type*) PROFILE_BASE) /* 0x402D0000 */
|
||||
#define PROFILE_CNT_STRUCT0 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[0]) /* 0x402D0800 */
|
||||
#define PROFILE_CNT_STRUCT1 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[1]) /* 0x402D0810 */
|
||||
#define PROFILE_CNT_STRUCT2 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[2]) /* 0x402D0820 */
|
||||
#define PROFILE_CNT_STRUCT3 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[3]) /* 0x402D0830 */
|
||||
#define PROFILE_CNT_STRUCT4 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[4]) /* 0x402D0840 */
|
||||
#define PROFILE_CNT_STRUCT5 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[5]) /* 0x402D0850 */
|
||||
#define PROFILE_CNT_STRUCT6 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[6]) /* 0x402D0860 */
|
||||
#define PROFILE_CNT_STRUCT7 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[7]) /* 0x402D0870 */
|
||||
|
||||
/*******************************************************************************
|
||||
* HSIOM
|
||||
*******************************************************************************/
|
||||
|
||||
#define HSIOM_BASE 0x40310000UL
|
||||
#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40310000 */
|
||||
#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40310000 */
|
||||
#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40310010 */
|
||||
#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40310020 */
|
||||
#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40310030 */
|
||||
#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40310040 */
|
||||
#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40310050 */
|
||||
#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40310060 */
|
||||
#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40310070 */
|
||||
#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40310080 */
|
||||
#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40310090 */
|
||||
#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403100A0 */
|
||||
#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403100B0 */
|
||||
#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403100C0 */
|
||||
#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403100D0 */
|
||||
#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403100E0 */
|
||||
|
||||
/*******************************************************************************
|
||||
* GPIO
|
||||
*******************************************************************************/
|
||||
|
||||
#define GPIO_BASE 0x40320000UL
|
||||
#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40320000 */
|
||||
#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40320000 */
|
||||
#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40320080 */
|
||||
#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40320100 */
|
||||
#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40320180 */
|
||||
#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40320200 */
|
||||
#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40320280 */
|
||||
#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40320300 */
|
||||
#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40320380 */
|
||||
#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40320400 */
|
||||
#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40320480 */
|
||||
#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40320500 */
|
||||
#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40320580 */
|
||||
#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40320600 */
|
||||
#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40320680 */
|
||||
#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40320700 */
|
||||
|
||||
/*******************************************************************************
|
||||
* SMARTIO
|
||||
*******************************************************************************/
|
||||
|
||||
#define SMARTIO_BASE 0x40330000UL
|
||||
#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40330000 */
|
||||
#define SMARTIO_PRT8 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[8]) /* 0x40330800 */
|
||||
#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40330900 */
|
||||
|
||||
/*******************************************************************************
|
||||
* LPCOMP
|
||||
*******************************************************************************/
|
||||
|
||||
#define LPCOMP_BASE 0x40350000UL
|
||||
#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* CSD
|
||||
*******************************************************************************/
|
||||
|
||||
#define CSD0_BASE 0x40360000UL
|
||||
#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* TCPWM
|
||||
*******************************************************************************/
|
||||
|
||||
#define TCPWM0_BASE 0x40380000UL
|
||||
#define TCPWM1_BASE 0x40390000UL
|
||||
#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */
|
||||
#define TCPWM1 ((TCPWM_Type*) TCPWM1_BASE) /* 0x40390000 */
|
||||
#define TCPWM0_CNT0 ((TCPWM_CNT_Type*) &TCPWM0->CNT[0]) /* 0x40380100 */
|
||||
#define TCPWM0_CNT1 ((TCPWM_CNT_Type*) &TCPWM0->CNT[1]) /* 0x40380140 */
|
||||
#define TCPWM0_CNT2 ((TCPWM_CNT_Type*) &TCPWM0->CNT[2]) /* 0x40380180 */
|
||||
#define TCPWM0_CNT3 ((TCPWM_CNT_Type*) &TCPWM0->CNT[3]) /* 0x403801C0 */
|
||||
#define TCPWM0_CNT4 ((TCPWM_CNT_Type*) &TCPWM0->CNT[4]) /* 0x40380200 */
|
||||
#define TCPWM0_CNT5 ((TCPWM_CNT_Type*) &TCPWM0->CNT[5]) /* 0x40380240 */
|
||||
#define TCPWM0_CNT6 ((TCPWM_CNT_Type*) &TCPWM0->CNT[6]) /* 0x40380280 */
|
||||
#define TCPWM0_CNT7 ((TCPWM_CNT_Type*) &TCPWM0->CNT[7]) /* 0x403802C0 */
|
||||
#define TCPWM1_CNT0 ((TCPWM_CNT_Type*) &TCPWM1->CNT[0]) /* 0x40390100 */
|
||||
#define TCPWM1_CNT1 ((TCPWM_CNT_Type*) &TCPWM1->CNT[1]) /* 0x40390140 */
|
||||
#define TCPWM1_CNT2 ((TCPWM_CNT_Type*) &TCPWM1->CNT[2]) /* 0x40390180 */
|
||||
#define TCPWM1_CNT3 ((TCPWM_CNT_Type*) &TCPWM1->CNT[3]) /* 0x403901C0 */
|
||||
#define TCPWM1_CNT4 ((TCPWM_CNT_Type*) &TCPWM1->CNT[4]) /* 0x40390200 */
|
||||
#define TCPWM1_CNT5 ((TCPWM_CNT_Type*) &TCPWM1->CNT[5]) /* 0x40390240 */
|
||||
#define TCPWM1_CNT6 ((TCPWM_CNT_Type*) &TCPWM1->CNT[6]) /* 0x40390280 */
|
||||
#define TCPWM1_CNT7 ((TCPWM_CNT_Type*) &TCPWM1->CNT[7]) /* 0x403902C0 */
|
||||
#define TCPWM1_CNT8 ((TCPWM_CNT_Type*) &TCPWM1->CNT[8]) /* 0x40390300 */
|
||||
#define TCPWM1_CNT9 ((TCPWM_CNT_Type*) &TCPWM1->CNT[9]) /* 0x40390340 */
|
||||
#define TCPWM1_CNT10 ((TCPWM_CNT_Type*) &TCPWM1->CNT[10]) /* 0x40390380 */
|
||||
#define TCPWM1_CNT11 ((TCPWM_CNT_Type*) &TCPWM1->CNT[11]) /* 0x403903C0 */
|
||||
#define TCPWM1_CNT12 ((TCPWM_CNT_Type*) &TCPWM1->CNT[12]) /* 0x40390400 */
|
||||
#define TCPWM1_CNT13 ((TCPWM_CNT_Type*) &TCPWM1->CNT[13]) /* 0x40390440 */
|
||||
#define TCPWM1_CNT14 ((TCPWM_CNT_Type*) &TCPWM1->CNT[14]) /* 0x40390480 */
|
||||
#define TCPWM1_CNT15 ((TCPWM_CNT_Type*) &TCPWM1->CNT[15]) /* 0x403904C0 */
|
||||
#define TCPWM1_CNT16 ((TCPWM_CNT_Type*) &TCPWM1->CNT[16]) /* 0x40390500 */
|
||||
#define TCPWM1_CNT17 ((TCPWM_CNT_Type*) &TCPWM1->CNT[17]) /* 0x40390540 */
|
||||
#define TCPWM1_CNT18 ((TCPWM_CNT_Type*) &TCPWM1->CNT[18]) /* 0x40390580 */
|
||||
#define TCPWM1_CNT19 ((TCPWM_CNT_Type*) &TCPWM1->CNT[19]) /* 0x403905C0 */
|
||||
#define TCPWM1_CNT20 ((TCPWM_CNT_Type*) &TCPWM1->CNT[20]) /* 0x40390600 */
|
||||
#define TCPWM1_CNT21 ((TCPWM_CNT_Type*) &TCPWM1->CNT[21]) /* 0x40390640 */
|
||||
#define TCPWM1_CNT22 ((TCPWM_CNT_Type*) &TCPWM1->CNT[22]) /* 0x40390680 */
|
||||
#define TCPWM1_CNT23 ((TCPWM_CNT_Type*) &TCPWM1->CNT[23]) /* 0x403906C0 */
|
||||
|
||||
/*******************************************************************************
|
||||
* LCD
|
||||
*******************************************************************************/
|
||||
|
||||
#define LCD0_BASE 0x403B0000UL
|
||||
#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* USBFS
|
||||
*******************************************************************************/
|
||||
|
||||
#define USBFS0_BASE 0x403F0000UL
|
||||
#define USBFS0 ((USBFS_Type*) USBFS0_BASE) /* 0x403F0000 */
|
||||
#define USBFS0_USBDEV ((USBFS_USBDEV_Type*) &USBFS0->USBDEV) /* 0x403F0000 */
|
||||
#define USBFS0_USBLPM ((USBFS_USBLPM_Type*) &USBFS0->USBLPM) /* 0x403F2000 */
|
||||
#define USBFS0_USBHOST ((USBFS_USBHOST_Type*) &USBFS0->USBHOST) /* 0x403F4000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* SMIF
|
||||
*******************************************************************************/
|
||||
|
||||
#define SMIF0_BASE 0x40420000UL
|
||||
#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */
|
||||
#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */
|
||||
#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */
|
||||
#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */
|
||||
#define SMIF0_DEVICE3 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[3]) /* 0x40420980 */
|
||||
|
||||
/*******************************************************************************
|
||||
* SCB
|
||||
*******************************************************************************/
|
||||
|
||||
#define SCB0_BASE 0x40610000UL
|
||||
#define SCB1_BASE 0x40620000UL
|
||||
#define SCB2_BASE 0x40630000UL
|
||||
#define SCB3_BASE 0x40640000UL
|
||||
#define SCB4_BASE 0x40650000UL
|
||||
#define SCB5_BASE 0x40660000UL
|
||||
#define SCB6_BASE 0x40670000UL
|
||||
#define SCB7_BASE 0x40680000UL
|
||||
#define SCB8_BASE 0x40690000UL
|
||||
#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40610000 */
|
||||
#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40620000 */
|
||||
#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40630000 */
|
||||
#define SCB3 ((CySCB_Type*) SCB3_BASE) /* 0x40640000 */
|
||||
#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40650000 */
|
||||
#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40660000 */
|
||||
#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40670000 */
|
||||
#define SCB7 ((CySCB_Type*) SCB7_BASE) /* 0x40680000 */
|
||||
#define SCB8 ((CySCB_Type*) SCB8_BASE) /* 0x40690000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* CTDAC
|
||||
*******************************************************************************/
|
||||
|
||||
#define CTDAC0_BASE 0x41140000UL
|
||||
#define CTDAC0 ((CTDAC_Type*) CTDAC0_BASE) /* 0x41140000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* SAR
|
||||
*******************************************************************************/
|
||||
|
||||
#define SAR_BASE 0x411D0000UL
|
||||
#define SAR ((SAR_Type*) SAR_BASE) /* 0x411D0000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* PASS
|
||||
*******************************************************************************/
|
||||
|
||||
#define PASS_BASE 0x411F0000UL
|
||||
#define PASS ((PASS_Type*) PASS_BASE) /* 0x411F0000 */
|
||||
#define PASS_AREF ((PASS_AREF_Type*) &PASS->AREF) /* 0x411F0E00 */
|
||||
|
||||
/*******************************************************************************
|
||||
* I2S
|
||||
*******************************************************************************/
|
||||
|
||||
#define I2S0_BASE 0x42A10000UL
|
||||
#define I2S0 ((I2S_Type*) I2S0_BASE) /* 0x42A10000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* PDM
|
||||
*******************************************************************************/
|
||||
|
||||
#define PDM0_BASE 0x42A20000UL
|
||||
#define PDM0 ((PDM_Type*) PDM0_BASE) /* 0x42A20000 */
|
||||
|
||||
|
||||
/* Backward compabitility definitions */
|
||||
#define I2S I2S0
|
||||
#define PDM PDM0
|
||||
|
||||
/** \} CY8C6137FDI-F02 */
|
||||
|
||||
#endif /* _CY8C6137FDI_F02_H_ */
|
||||
|
||||
|
||||
/* [] END OF FILE */
|
||||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -1,934 +0,0 @@
|
|||
/***************************************************************************//**
|
||||
* \file cy8c6316bzi_blf03.h
|
||||
*
|
||||
* \brief
|
||||
* CY8C6316BZI-BLF03 device header
|
||||
*
|
||||
* \note
|
||||
* Generator version: 1.3.0.1146
|
||||
* Database revision: rev#1050929
|
||||
*
|
||||
********************************************************************************
|
||||
* \copyright
|
||||
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
|
||||
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _CY8C6316BZI_BLF03_H_
|
||||
#define _CY8C6316BZI_BLF03_H_
|
||||
|
||||
/**
|
||||
* \addtogroup group_device CY8C6316BZI-BLF03
|
||||
* \{
|
||||
*/
|
||||
|
||||
/**
|
||||
* \addtogroup Configuration_of_CMSIS
|
||||
* \{
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Interrupt Number Definition
|
||||
*******************************************************************************/
|
||||
|
||||
typedef enum {
|
||||
/* ARM Cortex-M4 Core Interrupt Numbers */
|
||||
Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */
|
||||
NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */
|
||||
HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */
|
||||
MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */
|
||||
BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */
|
||||
UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
|
||||
SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */
|
||||
DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */
|
||||
PendSV_IRQn = -2, /*!< -2 Pendable request for system service */
|
||||
SysTick_IRQn = -1, /*!< -1 System Tick Timer */
|
||||
/* CY8C6316BZI-BLF03 Peripheral Interrupt Numbers */
|
||||
ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */
|
||||
ioss_interrupts_gpio_1_IRQn = 1, /*!< 1 [DeepSleep] GPIO Port Interrupt #1 */
|
||||
ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */
|
||||
ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */
|
||||
ioss_interrupts_gpio_4_IRQn = 4, /*!< 4 [DeepSleep] GPIO Port Interrupt #4 */
|
||||
ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */
|
||||
ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */
|
||||
ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */
|
||||
ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */
|
||||
ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */
|
||||
ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */
|
||||
ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */
|
||||
ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */
|
||||
ioss_interrupts_gpio_13_IRQn = 13, /*!< 13 [DeepSleep] GPIO Port Interrupt #13 */
|
||||
ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */
|
||||
ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */
|
||||
ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */
|
||||
lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */
|
||||
scb_8_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #8 (DeepSleep capable) */
|
||||
srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */
|
||||
srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */
|
||||
srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */
|
||||
srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */
|
||||
pass_interrupt_ctbs_IRQn = 23, /*!< 23 [DeepSleep] CTBm Interrupt (all CTBms) */
|
||||
bless_interrupt_IRQn = 24, /*!< 24 [DeepSleep] Bluetooth Radio interrupt */
|
||||
cpuss_interrupts_ipc_0_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */
|
||||
cpuss_interrupts_ipc_1_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */
|
||||
cpuss_interrupts_ipc_2_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */
|
||||
cpuss_interrupts_ipc_3_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */
|
||||
cpuss_interrupts_ipc_4_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */
|
||||
cpuss_interrupts_ipc_5_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */
|
||||
cpuss_interrupts_ipc_6_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */
|
||||
cpuss_interrupts_ipc_7_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */
|
||||
cpuss_interrupts_ipc_8_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */
|
||||
cpuss_interrupts_ipc_9_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */
|
||||
cpuss_interrupts_ipc_10_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */
|
||||
cpuss_interrupts_ipc_11_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */
|
||||
cpuss_interrupts_ipc_12_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */
|
||||
cpuss_interrupts_ipc_13_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */
|
||||
cpuss_interrupts_ipc_14_IRQn = 39, /*!< 39 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */
|
||||
cpuss_interrupts_ipc_15_IRQn = 40, /*!< 40 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */
|
||||
scb_0_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #0 */
|
||||
scb_1_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #1 */
|
||||
scb_2_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #2 */
|
||||
scb_3_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #3 */
|
||||
scb_4_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #4 */
|
||||
scb_5_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #5 */
|
||||
scb_6_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #6 */
|
||||
scb_7_interrupt_IRQn = 48, /*!< 48 [Active] Serial Communication Block #7 */
|
||||
csd_interrupt_IRQn = 49, /*!< 49 [Active] CSD (Capsense) interrupt */
|
||||
cpuss_interrupts_dw0_0_IRQn = 50, /*!< 50 [Active] CPUSS DataWire #0, Channel #0 */
|
||||
cpuss_interrupts_dw0_1_IRQn = 51, /*!< 51 [Active] CPUSS DataWire #0, Channel #1 */
|
||||
cpuss_interrupts_dw0_2_IRQn = 52, /*!< 52 [Active] CPUSS DataWire #0, Channel #2 */
|
||||
cpuss_interrupts_dw0_3_IRQn = 53, /*!< 53 [Active] CPUSS DataWire #0, Channel #3 */
|
||||
cpuss_interrupts_dw0_4_IRQn = 54, /*!< 54 [Active] CPUSS DataWire #0, Channel #4 */
|
||||
cpuss_interrupts_dw0_5_IRQn = 55, /*!< 55 [Active] CPUSS DataWire #0, Channel #5 */
|
||||
cpuss_interrupts_dw0_6_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #6 */
|
||||
cpuss_interrupts_dw0_7_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #7 */
|
||||
cpuss_interrupts_dw0_8_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #8 */
|
||||
cpuss_interrupts_dw0_9_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #9 */
|
||||
cpuss_interrupts_dw0_10_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #10 */
|
||||
cpuss_interrupts_dw0_11_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #11 */
|
||||
cpuss_interrupts_dw0_12_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #12 */
|
||||
cpuss_interrupts_dw0_13_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #13 */
|
||||
cpuss_interrupts_dw0_14_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #14 */
|
||||
cpuss_interrupts_dw0_15_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #15 */
|
||||
cpuss_interrupts_dw1_0_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #1, Channel #0 */
|
||||
cpuss_interrupts_dw1_1_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #1, Channel #1 */
|
||||
cpuss_interrupts_dw1_2_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #1, Channel #2 */
|
||||
cpuss_interrupts_dw1_3_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #1, Channel #3 */
|
||||
cpuss_interrupts_dw1_4_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #1, Channel #4 */
|
||||
cpuss_interrupts_dw1_5_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #1, Channel #5 */
|
||||
cpuss_interrupts_dw1_6_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #1, Channel #6 */
|
||||
cpuss_interrupts_dw1_7_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #1, Channel #7 */
|
||||
cpuss_interrupts_dw1_8_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #1, Channel #8 */
|
||||
cpuss_interrupts_dw1_9_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #1, Channel #9 */
|
||||
cpuss_interrupts_dw1_10_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #1, Channel #10 */
|
||||
cpuss_interrupts_dw1_11_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #1, Channel #11 */
|
||||
cpuss_interrupts_dw1_12_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #1, Channel #12 */
|
||||
cpuss_interrupts_dw1_13_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #1, Channel #13 */
|
||||
cpuss_interrupts_dw1_14_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #1, Channel #14 */
|
||||
cpuss_interrupts_dw1_15_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #1, Channel #15 */
|
||||
cpuss_interrupts_fault_0_IRQn = 82, /*!< 82 [Active] CPUSS Fault Structure Interrupt #0 */
|
||||
cpuss_interrupts_fault_1_IRQn = 83, /*!< 83 [Active] CPUSS Fault Structure Interrupt #1 */
|
||||
cpuss_interrupt_crypto_IRQn = 84, /*!< 84 [Active] CRYPTO Accelerator Interrupt */
|
||||
cpuss_interrupt_fm_IRQn = 85, /*!< 85 [Active] FLASH Macro Interrupt */
|
||||
cpuss_interrupts_cm0_cti_0_IRQn = 86, /*!< 86 [Active] CM0+ CTI #0 */
|
||||
cpuss_interrupts_cm0_cti_1_IRQn = 87, /*!< 87 [Active] CM0+ CTI #1 */
|
||||
cpuss_interrupts_cm4_cti_0_IRQn = 88, /*!< 88 [Active] CM4 CTI #0 */
|
||||
cpuss_interrupts_cm4_cti_1_IRQn = 89, /*!< 89 [Active] CM4 CTI #1 */
|
||||
tcpwm_0_interrupts_0_IRQn = 90, /*!< 90 [Active] TCPWM #0, Counter #0 */
|
||||
tcpwm_0_interrupts_1_IRQn = 91, /*!< 91 [Active] TCPWM #0, Counter #1 */
|
||||
tcpwm_0_interrupts_2_IRQn = 92, /*!< 92 [Active] TCPWM #0, Counter #2 */
|
||||
tcpwm_0_interrupts_3_IRQn = 93, /*!< 93 [Active] TCPWM #0, Counter #3 */
|
||||
tcpwm_0_interrupts_4_IRQn = 94, /*!< 94 [Active] TCPWM #0, Counter #4 */
|
||||
tcpwm_0_interrupts_5_IRQn = 95, /*!< 95 [Active] TCPWM #0, Counter #5 */
|
||||
tcpwm_0_interrupts_6_IRQn = 96, /*!< 96 [Active] TCPWM #0, Counter #6 */
|
||||
tcpwm_0_interrupts_7_IRQn = 97, /*!< 97 [Active] TCPWM #0, Counter #7 */
|
||||
tcpwm_1_interrupts_0_IRQn = 98, /*!< 98 [Active] TCPWM #1, Counter #0 */
|
||||
tcpwm_1_interrupts_1_IRQn = 99, /*!< 99 [Active] TCPWM #1, Counter #1 */
|
||||
tcpwm_1_interrupts_2_IRQn = 100, /*!< 100 [Active] TCPWM #1, Counter #2 */
|
||||
tcpwm_1_interrupts_3_IRQn = 101, /*!< 101 [Active] TCPWM #1, Counter #3 */
|
||||
tcpwm_1_interrupts_4_IRQn = 102, /*!< 102 [Active] TCPWM #1, Counter #4 */
|
||||
tcpwm_1_interrupts_5_IRQn = 103, /*!< 103 [Active] TCPWM #1, Counter #5 */
|
||||
tcpwm_1_interrupts_6_IRQn = 104, /*!< 104 [Active] TCPWM #1, Counter #6 */
|
||||
tcpwm_1_interrupts_7_IRQn = 105, /*!< 105 [Active] TCPWM #1, Counter #7 */
|
||||
tcpwm_1_interrupts_8_IRQn = 106, /*!< 106 [Active] TCPWM #1, Counter #8 */
|
||||
tcpwm_1_interrupts_9_IRQn = 107, /*!< 107 [Active] TCPWM #1, Counter #9 */
|
||||
tcpwm_1_interrupts_10_IRQn = 108, /*!< 108 [Active] TCPWM #1, Counter #10 */
|
||||
tcpwm_1_interrupts_11_IRQn = 109, /*!< 109 [Active] TCPWM #1, Counter #11 */
|
||||
tcpwm_1_interrupts_12_IRQn = 110, /*!< 110 [Active] TCPWM #1, Counter #12 */
|
||||
tcpwm_1_interrupts_13_IRQn = 111, /*!< 111 [Active] TCPWM #1, Counter #13 */
|
||||
tcpwm_1_interrupts_14_IRQn = 112, /*!< 112 [Active] TCPWM #1, Counter #14 */
|
||||
tcpwm_1_interrupts_15_IRQn = 113, /*!< 113 [Active] TCPWM #1, Counter #15 */
|
||||
tcpwm_1_interrupts_16_IRQn = 114, /*!< 114 [Active] TCPWM #1, Counter #16 */
|
||||
tcpwm_1_interrupts_17_IRQn = 115, /*!< 115 [Active] TCPWM #1, Counter #17 */
|
||||
tcpwm_1_interrupts_18_IRQn = 116, /*!< 116 [Active] TCPWM #1, Counter #18 */
|
||||
tcpwm_1_interrupts_19_IRQn = 117, /*!< 117 [Active] TCPWM #1, Counter #19 */
|
||||
tcpwm_1_interrupts_20_IRQn = 118, /*!< 118 [Active] TCPWM #1, Counter #20 */
|
||||
tcpwm_1_interrupts_21_IRQn = 119, /*!< 119 [Active] TCPWM #1, Counter #21 */
|
||||
tcpwm_1_interrupts_22_IRQn = 120, /*!< 120 [Active] TCPWM #1, Counter #22 */
|
||||
tcpwm_1_interrupts_23_IRQn = 121, /*!< 121 [Active] TCPWM #1, Counter #23 */
|
||||
udb_interrupts_0_IRQn = 122, /*!< 122 [Active] UDB Interrupt #0 */
|
||||
udb_interrupts_1_IRQn = 123, /*!< 123 [Active] UDB Interrupt #1 */
|
||||
udb_interrupts_2_IRQn = 124, /*!< 124 [Active] UDB Interrupt #2 */
|
||||
udb_interrupts_3_IRQn = 125, /*!< 125 [Active] UDB Interrupt #3 */
|
||||
udb_interrupts_4_IRQn = 126, /*!< 126 [Active] UDB Interrupt #4 */
|
||||
udb_interrupts_5_IRQn = 127, /*!< 127 [Active] UDB Interrupt #5 */
|
||||
udb_interrupts_6_IRQn = 128, /*!< 128 [Active] UDB Interrupt #6 */
|
||||
udb_interrupts_7_IRQn = 129, /*!< 129 [Active] UDB Interrupt #7 */
|
||||
udb_interrupts_8_IRQn = 130, /*!< 130 [Active] UDB Interrupt #8 */
|
||||
udb_interrupts_9_IRQn = 131, /*!< 131 [Active] UDB Interrupt #9 */
|
||||
udb_interrupts_10_IRQn = 132, /*!< 132 [Active] UDB Interrupt #10 */
|
||||
udb_interrupts_11_IRQn = 133, /*!< 133 [Active] UDB Interrupt #11 */
|
||||
udb_interrupts_12_IRQn = 134, /*!< 134 [Active] UDB Interrupt #12 */
|
||||
udb_interrupts_13_IRQn = 135, /*!< 135 [Active] UDB Interrupt #13 */
|
||||
udb_interrupts_14_IRQn = 136, /*!< 136 [Active] UDB Interrupt #14 */
|
||||
udb_interrupts_15_IRQn = 137, /*!< 137 [Active] UDB Interrupt #15 */
|
||||
pass_interrupt_sar_IRQn = 138, /*!< 138 [Active] SAR ADC interrupt */
|
||||
audioss_interrupt_i2s_IRQn = 139, /*!< 139 [Active] I2S Audio interrupt */
|
||||
audioss_interrupt_pdm_IRQn = 140, /*!< 140 [Active] PDM/PCM Audio interrupt */
|
||||
profile_interrupt_IRQn = 141, /*!< 141 [Active] Energy Profiler interrupt */
|
||||
smif_interrupt_IRQn = 142, /*!< 142 [Active] Serial Memory Interface interrupt */
|
||||
usb_interrupt_hi_IRQn = 143, /*!< 143 [Active] USB Interrupt */
|
||||
usb_interrupt_med_IRQn = 144, /*!< 144 [Active] USB Interrupt */
|
||||
usb_interrupt_lo_IRQn = 145, /*!< 145 [Active] USB Interrupt */
|
||||
pass_interrupt_dacs_IRQn = 146, /*!< 146 [Active] Consolidated interrrupt for all DACs */
|
||||
unconnected_IRQn = 240 /*!< 240 Unconnected */
|
||||
} IRQn_Type;
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Processor and Core Peripheral Section
|
||||
*******************************************************************************/
|
||||
|
||||
/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */
|
||||
#define __CM4_REV 0x0001U /*!< CM4 Core Revision */
|
||||
#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
|
||||
#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */
|
||||
#define __MPU_PRESENT 1 /*!< MPU present or not */
|
||||
#define __FPU_PRESENT 1 /*!< FPU present or not */
|
||||
#define __CM0P_PRESENT 0 /*!< CM0P present or not */
|
||||
|
||||
/** \} Configuration_of_CMSIS */
|
||||
|
||||
/* Memory Blocks */
|
||||
#define CY_ROM_BASE 0x00000000UL
|
||||
#define CY_ROM_SIZE 0x00020000UL
|
||||
#define CY_SRAM0_BASE 0x08000000UL
|
||||
#define CY_SRAM0_SIZE 0x00020000UL
|
||||
#define CY_FLASH_BASE 0x10000000UL
|
||||
#define CY_FLASH_SIZE 0x00080000UL
|
||||
#define CY_EM_EEPROM_BASE 0x14000000UL
|
||||
#define CY_EM_EEPROM_SIZE 0x00008000UL
|
||||
#define CY_XIP_BASE 0x18000000UL
|
||||
#define CY_XIP_SIZE 0x08000000UL
|
||||
#define CY_SFLASH_BASE 0x16000000UL
|
||||
#define CY_SFLASH_SIZE 0x00008000UL
|
||||
#define CY_EFUSE_BASE 0x402C0800UL
|
||||
#define CY_EFUSE_SIZE 0x00000200UL
|
||||
|
||||
#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */
|
||||
#include "system_psoc6.h" /*!< PSoC 6 System */
|
||||
|
||||
/* IP List */
|
||||
#define CY_IP_MXTCPWM 1u
|
||||
#define CY_IP_MXTCPWM_INSTANCES 2u
|
||||
#define CY_IP_MXTCPWM_VERSION 1u
|
||||
#define CY_IP_MXCSDV2 1u
|
||||
#define CY_IP_MXCSDV2_INSTANCES 1u
|
||||
#define CY_IP_MXCSDV2_VERSION 1u
|
||||
#define CY_IP_MXLCD 1u
|
||||
#define CY_IP_MXLCD_INSTANCES 1u
|
||||
#define CY_IP_MXLCD_VERSION 1u
|
||||
#define CY_IP_MXS40SRSS 1u
|
||||
#define CY_IP_MXS40SRSS_INSTANCES 1u
|
||||
#define CY_IP_MXS40SRSS_VERSION 1u
|
||||
#define CY_IP_MXS40SRSS_RTC 1u
|
||||
#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u
|
||||
#define CY_IP_MXS40SRSS_RTC_VERSION 1u
|
||||
#define CY_IP_MXS40SRSS_MCWDT 1u
|
||||
#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u
|
||||
#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u
|
||||
#define CY_IP_MXSCB 1u
|
||||
#define CY_IP_MXSCB_INSTANCES 9u
|
||||
#define CY_IP_MXSCB_VERSION 1u
|
||||
#define CY_IP_MXPERI 1u
|
||||
#define CY_IP_MXPERI_INSTANCES 1u
|
||||
#define CY_IP_MXPERI_VERSION 1u
|
||||
#define CY_IP_MXPERI_TR 1u
|
||||
#define CY_IP_MXPERI_TR_INSTANCES 1u
|
||||
#define CY_IP_MXPERI_TR_VERSION 1u
|
||||
#define CY_IP_M4CPUSS 1u
|
||||
#define CY_IP_M4CPUSS_INSTANCES 1u
|
||||
#define CY_IP_M4CPUSS_VERSION 1u
|
||||
#define CY_IP_M4CPUSS_DMA 1u
|
||||
#define CY_IP_M4CPUSS_DMA_INSTANCES 2u
|
||||
#define CY_IP_M4CPUSS_DMA_VERSION 1u
|
||||
#define CY_IP_MXBLESS 1u
|
||||
#define CY_IP_MXBLESS_INSTANCES 1u
|
||||
#define CY_IP_MXBLESS_VERSION 1u
|
||||
#define CY_IP_MXAUDIOSS 1u
|
||||
#define CY_IP_MXAUDIOSS_INSTANCES 1u
|
||||
#define CY_IP_MXAUDIOSS_VERSION 1u
|
||||
#define CY_IP_MXLPCOMP 1u
|
||||
#define CY_IP_MXLPCOMP_INSTANCES 1u
|
||||
#define CY_IP_MXLPCOMP_VERSION 1u
|
||||
#define CY_IP_MXS40PASS 1u
|
||||
#define CY_IP_MXS40PASS_INSTANCES 1u
|
||||
#define CY_IP_MXS40PASS_VERSION 1u
|
||||
#define CY_IP_MXS40PASS_SAR 1u
|
||||
#define CY_IP_MXS40PASS_SAR_INSTANCES 16u
|
||||
#define CY_IP_MXS40PASS_SAR_VERSION 1u
|
||||
#define CY_IP_MXS40PASS_CTDAC 1u
|
||||
#define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u
|
||||
#define CY_IP_MXS40PASS_CTDAC_VERSION 1u
|
||||
#define CY_IP_MXSMIF 1u
|
||||
#define CY_IP_MXSMIF_INSTANCES 1u
|
||||
#define CY_IP_MXSMIF_VERSION 1u
|
||||
#define CY_IP_MXS40IOSS 1u
|
||||
#define CY_IP_MXS40IOSS_INSTANCES 1u
|
||||
#define CY_IP_MXS40IOSS_VERSION 1u
|
||||
#define CY_IP_MXEFUSE 1u
|
||||
#define CY_IP_MXEFUSE_INSTANCES 1u
|
||||
#define CY_IP_MXEFUSE_VERSION 1u
|
||||
#define CY_IP_MXPROFILE 1u
|
||||
#define CY_IP_MXPROFILE_INSTANCES 1u
|
||||
#define CY_IP_MXPROFILE_VERSION 1u
|
||||
|
||||
#include "psoc6able2_config.h"
|
||||
#include "gpio_psoc6able2_116_bga_ble.h"
|
||||
|
||||
#define CY_DEVICE_PSOC6ABLE2
|
||||
#define CY_SILICON_ID 0xE2212100UL
|
||||
#define CY_HF_CLK_MAX_FREQ 50000000UL
|
||||
|
||||
#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL
|
||||
|
||||
/*******************************************************************************
|
||||
* SFLASH
|
||||
*******************************************************************************/
|
||||
|
||||
#define SFLASH_BASE 0x16000000UL
|
||||
#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* PERI
|
||||
*******************************************************************************/
|
||||
|
||||
#define PERI_BASE 0x40010000UL
|
||||
#define PERI_PPU_GR_MMIO0_BASE 0x40015000UL
|
||||
#define PERI_PPU_GR_MMIO1_BASE 0x40015040UL
|
||||
#define PERI_PPU_GR_MMIO2_BASE 0x40015080UL
|
||||
#define PERI_PPU_GR_MMIO3_BASE 0x400150C0UL
|
||||
#define PERI_PPU_GR_MMIO4_BASE 0x40015100UL
|
||||
#define PERI_PPU_GR_MMIO6_BASE 0x40015180UL
|
||||
#define PERI_PPU_GR_MMIO9_BASE 0x40015240UL
|
||||
#define PERI_PPU_GR_MMIO10_BASE 0x40015280UL
|
||||
#define PERI_GR_PPU_SL_PERI_GR1_BASE 0x40100000UL
|
||||
#define PERI_GR_PPU_SL_CRYPTO_BASE 0x40100040UL
|
||||
#define PERI_GR_PPU_SL_PERI_GR2_BASE 0x40200000UL
|
||||
#define PERI_GR_PPU_SL_CPUSS_BASE 0x40200040UL
|
||||
#define PERI_GR_PPU_SL_FAULT_BASE 0x40200080UL
|
||||
#define PERI_GR_PPU_SL_IPC_BASE 0x402000C0UL
|
||||
#define PERI_GR_PPU_SL_PROT_BASE 0x40200100UL
|
||||
#define PERI_GR_PPU_SL_FLASHC_BASE 0x40200140UL
|
||||
#define PERI_GR_PPU_SL_SRSS_BASE 0x40200180UL
|
||||
#define PERI_GR_PPU_SL_BACKUP_BASE 0x402001C0UL
|
||||
#define PERI_GR_PPU_SL_DW0_BASE 0x40200200UL
|
||||
#define PERI_GR_PPU_SL_DW1_BASE 0x40200240UL
|
||||
#define PERI_GR_PPU_SL_EFUSE_BASE 0x40200300UL
|
||||
#define PERI_GR_PPU_SL_PROFILE_BASE 0x40200340UL
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT0_BASE 0x40201000UL
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT1_BASE 0x40201040UL
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT2_BASE 0x40201080UL
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT3_BASE 0x402010C0UL
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT4_BASE 0x40201100UL
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT5_BASE 0x40201140UL
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT6_BASE 0x40201180UL
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT7_BASE 0x402011C0UL
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT0_BASE 0x40201200UL
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT1_BASE 0x40201240UL
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT2_BASE 0x40201280UL
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT3_BASE 0x402012C0UL
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT4_BASE 0x40201300UL
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT5_BASE 0x40201340UL
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT6_BASE 0x40201380UL
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT7_BASE 0x402013C0UL
|
||||
#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT0_BASE 0x40201400UL
|
||||
#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT1_BASE 0x40201440UL
|
||||
#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT2_BASE 0x40201480UL
|
||||
#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT3_BASE 0x402014C0UL
|
||||
#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT0_BASE 0x40201500UL
|
||||
#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT1_BASE 0x40201540UL
|
||||
#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT2_BASE 0x40201580UL
|
||||
#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT3_BASE 0x402015C0UL
|
||||
#define PERI_GR_PPU_RG_SMPU_BASE 0x40201600UL
|
||||
#define PERI_GR_PPU_RG_MPU_CM0P_BASE 0x40201640UL
|
||||
#define PERI_GR_PPU_RG_MPU_CRYPTO_BASE 0x40201680UL
|
||||
#define PERI_GR_PPU_RG_MPU_CM4_BASE 0x402016C0UL
|
||||
#define PERI_GR_PPU_RG_MPU_TC_BASE 0x40201700UL
|
||||
#define PERI_GR_PPU_SL_PERI_GR3_BASE 0x40300000UL
|
||||
#define PERI_GR_PPU_SL_HSIOM_BASE 0x40300040UL
|
||||
#define PERI_GR_PPU_SL_GPIO_BASE 0x40300080UL
|
||||
#define PERI_GR_PPU_SL_SMARTIO_BASE 0x403000C0UL
|
||||
#define PERI_GR_PPU_SL_UDB_BASE 0x40300100UL
|
||||
#define PERI_GR_PPU_SL_LPCOMP_BASE 0x40300140UL
|
||||
#define PERI_GR_PPU_SL_CSD_BASE 0x40300180UL
|
||||
#define PERI_GR_PPU_SL_TCPWM0_BASE 0x40300200UL
|
||||
#define PERI_GR_PPU_SL_TCPWM1_BASE 0x40300240UL
|
||||
#define PERI_GR_PPU_SL_LCD_BASE 0x40300280UL
|
||||
#define PERI_GR_PPU_SL_BLE_BASE 0x403002C0UL
|
||||
#define PERI_GR_PPU_SL_USBFS_BASE 0x40300300UL
|
||||
#define PERI_GR_PPU_SL_PERI_GR4_BASE 0x40400000UL
|
||||
#define PERI_GR_PPU_SL_SMIF_BASE 0x40400080UL
|
||||
#define PERI_GR_PPU_SL_PERI_GR6_BASE 0x40600000UL
|
||||
#define PERI_GR_PPU_SL_SCB0_BASE 0x40600040UL
|
||||
#define PERI_GR_PPU_SL_SCB1_BASE 0x40600080UL
|
||||
#define PERI_GR_PPU_SL_SCB2_BASE 0x406000C0UL
|
||||
#define PERI_GR_PPU_SL_SCB3_BASE 0x40600100UL
|
||||
#define PERI_GR_PPU_SL_SCB4_BASE 0x40600140UL
|
||||
#define PERI_GR_PPU_SL_SCB5_BASE 0x40600180UL
|
||||
#define PERI_GR_PPU_SL_SCB6_BASE 0x406001C0UL
|
||||
#define PERI_GR_PPU_SL_SCB7_BASE 0x40600200UL
|
||||
#define PERI_GR_PPU_SL_SCB8_BASE 0x40600240UL
|
||||
#define PERI_GR_PPU_SL_PERI_GR9_BASE 0x41000000UL
|
||||
#define PERI_GR_PPU_SL_PASS_BASE 0x41000040UL
|
||||
#define PERI_GR_PPU_SL_PERI_GR10_BASE 0x42A00000UL
|
||||
#define PERI_GR_PPU_SL_I2S_BASE 0x42A00040UL
|
||||
#define PERI_GR_PPU_SL_PDM_BASE 0x42A00080UL
|
||||
#define PERI ((PERI_Type*) PERI_BASE) /* 0x40010000 */
|
||||
#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40010000 */
|
||||
#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40010040 */
|
||||
#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40010080 */
|
||||
#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x400100C0 */
|
||||
#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40010100 */
|
||||
#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x40010180 */
|
||||
#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40010240 */
|
||||
#define PERI_GR10 ((PERI_GR_Type*) &PERI->GR[10]) /* 0x40010280 */
|
||||
#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40012000 */
|
||||
#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40012200 */
|
||||
#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40012400 */
|
||||
#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40012600 */
|
||||
#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40012800 */
|
||||
#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40012A00 */
|
||||
#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40012C00 */
|
||||
#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40012E00 */
|
||||
#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x40013000 */
|
||||
#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x40013200 */
|
||||
#define PERI_TR_GR10 ((PERI_TR_GR_Type*) &PERI->TR_GR[10]) /* 0x40013400 */
|
||||
#define PERI_TR_GR11 ((PERI_TR_GR_Type*) &PERI->TR_GR[11]) /* 0x40013600 */
|
||||
#define PERI_TR_GR12 ((PERI_TR_GR_Type*) &PERI->TR_GR[12]) /* 0x40013800 */
|
||||
#define PERI_TR_GR13 ((PERI_TR_GR_Type*) &PERI->TR_GR[13]) /* 0x40013A00 */
|
||||
#define PERI_TR_GR14 ((PERI_TR_GR_Type*) &PERI->TR_GR[14]) /* 0x40013C00 */
|
||||
#define PERI_PPU_PR0 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[0]) /* 0x40014000 */
|
||||
#define PERI_PPU_PR1 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[1]) /* 0x40014040 */
|
||||
#define PERI_PPU_PR2 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[2]) /* 0x40014080 */
|
||||
#define PERI_PPU_PR3 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[3]) /* 0x400140C0 */
|
||||
#define PERI_PPU_PR4 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[4]) /* 0x40014100 */
|
||||
#define PERI_PPU_PR5 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[5]) /* 0x40014140 */
|
||||
#define PERI_PPU_PR6 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[6]) /* 0x40014180 */
|
||||
#define PERI_PPU_PR7 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[7]) /* 0x400141C0 */
|
||||
#define PERI_PPU_PR8 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[8]) /* 0x40014200 */
|
||||
#define PERI_PPU_PR9 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[9]) /* 0x40014240 */
|
||||
#define PERI_PPU_PR10 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[10]) /* 0x40014280 */
|
||||
#define PERI_PPU_PR11 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[11]) /* 0x400142C0 */
|
||||
#define PERI_PPU_PR12 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[12]) /* 0x40014300 */
|
||||
#define PERI_PPU_PR13 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[13]) /* 0x40014340 */
|
||||
#define PERI_PPU_PR14 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[14]) /* 0x40014380 */
|
||||
#define PERI_PPU_PR15 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[15]) /* 0x400143C0 */
|
||||
#define PERI_PPU_GR0 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[0]) /* 0x40015000 */
|
||||
#define PERI_PPU_GR1 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[1]) /* 0x40015040 */
|
||||
#define PERI_PPU_GR2 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[2]) /* 0x40015080 */
|
||||
#define PERI_PPU_GR3 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[3]) /* 0x400150C0 */
|
||||
#define PERI_PPU_GR4 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[4]) /* 0x40015100 */
|
||||
#define PERI_PPU_GR6 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[6]) /* 0x40015180 */
|
||||
#define PERI_PPU_GR9 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[9]) /* 0x40015240 */
|
||||
#define PERI_PPU_GR10 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[10]) /* 0x40015280 */
|
||||
#define PERI_PPU_GR_MMIO0 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO0_BASE) /* 0x40015000 */
|
||||
#define PERI_PPU_GR_MMIO1 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO1_BASE) /* 0x40015040 */
|
||||
#define PERI_PPU_GR_MMIO2 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO2_BASE) /* 0x40015080 */
|
||||
#define PERI_PPU_GR_MMIO3 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO3_BASE) /* 0x400150C0 */
|
||||
#define PERI_PPU_GR_MMIO4 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO4_BASE) /* 0x40015100 */
|
||||
#define PERI_PPU_GR_MMIO6 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO6_BASE) /* 0x40015180 */
|
||||
#define PERI_PPU_GR_MMIO9 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO9_BASE) /* 0x40015240 */
|
||||
#define PERI_PPU_GR_MMIO10 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO10_BASE) /* 0x40015280 */
|
||||
#define PERI_GR_PPU_SL_PERI_GR1 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR1_BASE) /* 0x40100000 */
|
||||
#define PERI_GR_PPU_SL_CRYPTO ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_CRYPTO_BASE) /* 0x40100040 */
|
||||
#define PERI_GR_PPU_SL_PERI_GR2 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR2_BASE) /* 0x40200000 */
|
||||
#define PERI_GR_PPU_SL_CPUSS ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_CPUSS_BASE) /* 0x40200040 */
|
||||
#define PERI_GR_PPU_SL_FAULT ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_FAULT_BASE) /* 0x40200080 */
|
||||
#define PERI_GR_PPU_SL_IPC ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_IPC_BASE) /* 0x402000C0 */
|
||||
#define PERI_GR_PPU_SL_PROT ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PROT_BASE) /* 0x40200100 */
|
||||
#define PERI_GR_PPU_SL_FLASHC ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_FLASHC_BASE) /* 0x40200140 */
|
||||
#define PERI_GR_PPU_SL_SRSS ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SRSS_BASE) /* 0x40200180 */
|
||||
#define PERI_GR_PPU_SL_BACKUP ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_BACKUP_BASE) /* 0x402001C0 */
|
||||
#define PERI_GR_PPU_SL_DW0 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_DW0_BASE) /* 0x40200200 */
|
||||
#define PERI_GR_PPU_SL_DW1 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_DW1_BASE) /* 0x40200240 */
|
||||
#define PERI_GR_PPU_SL_EFUSE ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_EFUSE_BASE) /* 0x40200300 */
|
||||
#define PERI_GR_PPU_SL_PROFILE ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PROFILE_BASE) /* 0x40200340 */
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT0 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT0_BASE) /* 0x40201000 */
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT1 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT1_BASE) /* 0x40201040 */
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT2 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT2_BASE) /* 0x40201080 */
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT3 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT3_BASE) /* 0x402010C0 */
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT4 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT4_BASE) /* 0x40201100 */
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT5 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT5_BASE) /* 0x40201140 */
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT6 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT6_BASE) /* 0x40201180 */
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT7 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT7_BASE) /* 0x402011C0 */
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT0 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT0_BASE) /* 0x40201200 */
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT1 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT1_BASE) /* 0x40201240 */
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT2 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT2_BASE) /* 0x40201280 */
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT3 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT3_BASE) /* 0x402012C0 */
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT4 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT4_BASE) /* 0x40201300 */
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT5 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT5_BASE) /* 0x40201340 */
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT6 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT6_BASE) /* 0x40201380 */
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT7 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT7_BASE) /* 0x402013C0 */
|
||||
#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT0 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW0_DW_CH_STRUCT0_BASE) /* 0x40201400 */
|
||||
#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT1 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW0_DW_CH_STRUCT1_BASE) /* 0x40201440 */
|
||||
#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT2 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW0_DW_CH_STRUCT2_BASE) /* 0x40201480 */
|
||||
#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT3 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW0_DW_CH_STRUCT3_BASE) /* 0x402014C0 */
|
||||
#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT0 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW1_DW_CH_STRUCT0_BASE) /* 0x40201500 */
|
||||
#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT1 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW1_DW_CH_STRUCT1_BASE) /* 0x40201540 */
|
||||
#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT2 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW1_DW_CH_STRUCT2_BASE) /* 0x40201580 */
|
||||
#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT3 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW1_DW_CH_STRUCT3_BASE) /* 0x402015C0 */
|
||||
#define PERI_GR_PPU_RG_SMPU ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_SMPU_BASE) /* 0x40201600 */
|
||||
#define PERI_GR_PPU_RG_MPU_CM0P ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_MPU_CM0P_BASE) /* 0x40201640 */
|
||||
#define PERI_GR_PPU_RG_MPU_CRYPTO ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_MPU_CRYPTO_BASE) /* 0x40201680 */
|
||||
#define PERI_GR_PPU_RG_MPU_CM4 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_MPU_CM4_BASE) /* 0x402016C0 */
|
||||
#define PERI_GR_PPU_RG_MPU_TC ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_MPU_TC_BASE) /* 0x40201700 */
|
||||
#define PERI_GR_PPU_SL_PERI_GR3 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR3_BASE) /* 0x40300000 */
|
||||
#define PERI_GR_PPU_SL_HSIOM ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_HSIOM_BASE) /* 0x40300040 */
|
||||
#define PERI_GR_PPU_SL_GPIO ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_GPIO_BASE) /* 0x40300080 */
|
||||
#define PERI_GR_PPU_SL_SMARTIO ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SMARTIO_BASE) /* 0x403000C0 */
|
||||
#define PERI_GR_PPU_SL_UDB ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_UDB_BASE) /* 0x40300100 */
|
||||
#define PERI_GR_PPU_SL_LPCOMP ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_LPCOMP_BASE) /* 0x40300140 */
|
||||
#define PERI_GR_PPU_SL_CSD ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_CSD_BASE) /* 0x40300180 */
|
||||
#define PERI_GR_PPU_SL_TCPWM0 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_TCPWM0_BASE) /* 0x40300200 */
|
||||
#define PERI_GR_PPU_SL_TCPWM1 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_TCPWM1_BASE) /* 0x40300240 */
|
||||
#define PERI_GR_PPU_SL_LCD ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_LCD_BASE) /* 0x40300280 */
|
||||
#define PERI_GR_PPU_SL_BLE ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_BLE_BASE) /* 0x403002C0 */
|
||||
#define PERI_GR_PPU_SL_USBFS ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_USBFS_BASE) /* 0x40300300 */
|
||||
#define PERI_GR_PPU_SL_PERI_GR4 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR4_BASE) /* 0x40400000 */
|
||||
#define PERI_GR_PPU_SL_SMIF ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SMIF_BASE) /* 0x40400080 */
|
||||
#define PERI_GR_PPU_SL_PERI_GR6 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR6_BASE) /* 0x40600000 */
|
||||
#define PERI_GR_PPU_SL_SCB0 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB0_BASE) /* 0x40600040 */
|
||||
#define PERI_GR_PPU_SL_SCB1 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB1_BASE) /* 0x40600080 */
|
||||
#define PERI_GR_PPU_SL_SCB2 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB2_BASE) /* 0x406000C0 */
|
||||
#define PERI_GR_PPU_SL_SCB3 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB3_BASE) /* 0x40600100 */
|
||||
#define PERI_GR_PPU_SL_SCB4 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB4_BASE) /* 0x40600140 */
|
||||
#define PERI_GR_PPU_SL_SCB5 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB5_BASE) /* 0x40600180 */
|
||||
#define PERI_GR_PPU_SL_SCB6 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB6_BASE) /* 0x406001C0 */
|
||||
#define PERI_GR_PPU_SL_SCB7 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB7_BASE) /* 0x40600200 */
|
||||
#define PERI_GR_PPU_SL_SCB8 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB8_BASE) /* 0x40600240 */
|
||||
#define PERI_GR_PPU_SL_PERI_GR9 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR9_BASE) /* 0x41000000 */
|
||||
#define PERI_GR_PPU_SL_PASS ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PASS_BASE) /* 0x41000040 */
|
||||
#define PERI_GR_PPU_SL_PERI_GR10 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR10_BASE) /* 0x42A00000 */
|
||||
#define PERI_GR_PPU_SL_I2S ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_I2S_BASE) /* 0x42A00040 */
|
||||
#define PERI_GR_PPU_SL_PDM ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PDM_BASE) /* 0x42A00080 */
|
||||
|
||||
/*******************************************************************************
|
||||
* CPUSS
|
||||
*******************************************************************************/
|
||||
|
||||
#define CPUSS_BASE 0x40210000UL
|
||||
#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40210000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* FAULT
|
||||
*******************************************************************************/
|
||||
|
||||
#define FAULT_BASE 0x40220000UL
|
||||
#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40220000 */
|
||||
#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40220000 */
|
||||
#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40220100 */
|
||||
|
||||
/*******************************************************************************
|
||||
* IPC
|
||||
*******************************************************************************/
|
||||
|
||||
#define IPC_BASE 0x40230000UL
|
||||
#define IPC ((IPC_Type*) IPC_BASE) /* 0x40230000 */
|
||||
#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40230000 */
|
||||
#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40230020 */
|
||||
#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40230040 */
|
||||
#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40230060 */
|
||||
#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40230080 */
|
||||
#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402300A0 */
|
||||
#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402300C0 */
|
||||
#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402300E0 */
|
||||
#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40230100 */
|
||||
#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40230120 */
|
||||
#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40230140 */
|
||||
#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40230160 */
|
||||
#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40230180 */
|
||||
#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402301A0 */
|
||||
#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402301C0 */
|
||||
#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402301E0 */
|
||||
#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40231000 */
|
||||
#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40231020 */
|
||||
#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40231040 */
|
||||
#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40231060 */
|
||||
#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40231080 */
|
||||
#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402310A0 */
|
||||
#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402310C0 */
|
||||
#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402310E0 */
|
||||
#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40231100 */
|
||||
#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40231120 */
|
||||
#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40231140 */
|
||||
#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40231160 */
|
||||
#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40231180 */
|
||||
#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402311A0 */
|
||||
#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402311C0 */
|
||||
#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402311E0 */
|
||||
|
||||
/*******************************************************************************
|
||||
* PROT
|
||||
*******************************************************************************/
|
||||
|
||||
#define PROT_BASE 0x40240000UL
|
||||
#define PROT ((PROT_Type*) PROT_BASE) /* 0x40240000 */
|
||||
#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40242000 */
|
||||
#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40242040 */
|
||||
#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40242080 */
|
||||
#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402420C0 */
|
||||
#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40242100 */
|
||||
#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40242140 */
|
||||
#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40242180 */
|
||||
#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402421C0 */
|
||||
#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40242200 */
|
||||
#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40242240 */
|
||||
#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40242280 */
|
||||
#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402422C0 */
|
||||
#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40242300 */
|
||||
#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40242340 */
|
||||
#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40242380 */
|
||||
#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402423C0 */
|
||||
#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */
|
||||
#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */
|
||||
#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */
|
||||
#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */
|
||||
#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */
|
||||
#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */
|
||||
#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */
|
||||
#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */
|
||||
#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */
|
||||
#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */
|
||||
#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */
|
||||
#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */
|
||||
#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */
|
||||
#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */
|
||||
#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */
|
||||
#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */
|
||||
#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */
|
||||
#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40244000 */
|
||||
#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40244400 */
|
||||
#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40244800 */
|
||||
#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40244C00 */
|
||||
#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40245000 */
|
||||
#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40245400 */
|
||||
#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40245800 */
|
||||
#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40245C00 */
|
||||
#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40246000 */
|
||||
#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40246400 */
|
||||
#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40246800 */
|
||||
#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40246C00 */
|
||||
#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40247000 */
|
||||
#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40247400 */
|
||||
#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40247800 */
|
||||
#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40247C00 */
|
||||
|
||||
/*******************************************************************************
|
||||
* FLASHC
|
||||
*******************************************************************************/
|
||||
|
||||
#define FLASHC_BASE 0x40250000UL
|
||||
#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40250000 */
|
||||
#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4025F000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* SRSS
|
||||
*******************************************************************************/
|
||||
|
||||
#define SRSS_BASE 0x40260000UL
|
||||
#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */
|
||||
#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */
|
||||
#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */
|
||||
|
||||
/*******************************************************************************
|
||||
* BACKUP
|
||||
*******************************************************************************/
|
||||
|
||||
#define BACKUP_BASE 0x40270000UL
|
||||
#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* DW
|
||||
*******************************************************************************/
|
||||
|
||||
#define DW0_BASE 0x40280000UL
|
||||
#define DW1_BASE 0x40281000UL
|
||||
#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */
|
||||
#define DW1 ((DW_Type*) DW1_BASE) /* 0x40281000 */
|
||||
#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40280800 */
|
||||
#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40280820 */
|
||||
#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40280840 */
|
||||
#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x40280860 */
|
||||
#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40280880 */
|
||||
#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x402808A0 */
|
||||
#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x402808C0 */
|
||||
#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402808E0 */
|
||||
#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40280900 */
|
||||
#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40280920 */
|
||||
#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40280940 */
|
||||
#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x40280960 */
|
||||
#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40280980 */
|
||||
#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x402809A0 */
|
||||
#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x402809C0 */
|
||||
#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402809E0 */
|
||||
#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40281800 */
|
||||
#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40281820 */
|
||||
#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40281840 */
|
||||
#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x40281860 */
|
||||
#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40281880 */
|
||||
#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x402818A0 */
|
||||
#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x402818C0 */
|
||||
#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402818E0 */
|
||||
#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40281900 */
|
||||
#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40281920 */
|
||||
#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40281940 */
|
||||
#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x40281960 */
|
||||
#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40281980 */
|
||||
#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x402819A0 */
|
||||
#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x402819C0 */
|
||||
#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402819E0 */
|
||||
|
||||
/*******************************************************************************
|
||||
* EFUSE
|
||||
*******************************************************************************/
|
||||
|
||||
#define EFUSE_BASE 0x402C0000UL
|
||||
#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* PROFILE
|
||||
*******************************************************************************/
|
||||
|
||||
#define PROFILE_BASE 0x402D0000UL
|
||||
#define PROFILE ((PROFILE_Type*) PROFILE_BASE) /* 0x402D0000 */
|
||||
#define PROFILE_CNT_STRUCT0 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[0]) /* 0x402D0800 */
|
||||
#define PROFILE_CNT_STRUCT1 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[1]) /* 0x402D0810 */
|
||||
#define PROFILE_CNT_STRUCT2 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[2]) /* 0x402D0820 */
|
||||
#define PROFILE_CNT_STRUCT3 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[3]) /* 0x402D0830 */
|
||||
#define PROFILE_CNT_STRUCT4 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[4]) /* 0x402D0840 */
|
||||
#define PROFILE_CNT_STRUCT5 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[5]) /* 0x402D0850 */
|
||||
#define PROFILE_CNT_STRUCT6 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[6]) /* 0x402D0860 */
|
||||
#define PROFILE_CNT_STRUCT7 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[7]) /* 0x402D0870 */
|
||||
|
||||
/*******************************************************************************
|
||||
* HSIOM
|
||||
*******************************************************************************/
|
||||
|
||||
#define HSIOM_BASE 0x40310000UL
|
||||
#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40310000 */
|
||||
#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40310000 */
|
||||
#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40310010 */
|
||||
#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40310020 */
|
||||
#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40310030 */
|
||||
#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40310040 */
|
||||
#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40310050 */
|
||||
#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40310060 */
|
||||
#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40310070 */
|
||||
#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40310080 */
|
||||
#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40310090 */
|
||||
#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403100A0 */
|
||||
#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403100B0 */
|
||||
#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403100C0 */
|
||||
#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403100D0 */
|
||||
#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403100E0 */
|
||||
|
||||
/*******************************************************************************
|
||||
* GPIO
|
||||
*******************************************************************************/
|
||||
|
||||
#define GPIO_BASE 0x40320000UL
|
||||
#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40320000 */
|
||||
#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40320000 */
|
||||
#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40320080 */
|
||||
#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40320100 */
|
||||
#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40320180 */
|
||||
#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40320200 */
|
||||
#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40320280 */
|
||||
#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40320300 */
|
||||
#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40320380 */
|
||||
#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40320400 */
|
||||
#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40320480 */
|
||||
#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40320500 */
|
||||
#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40320580 */
|
||||
#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40320600 */
|
||||
#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40320680 */
|
||||
#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40320700 */
|
||||
|
||||
/*******************************************************************************
|
||||
* SMARTIO
|
||||
*******************************************************************************/
|
||||
|
||||
#define SMARTIO_BASE 0x40330000UL
|
||||
#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40330000 */
|
||||
#define SMARTIO_PRT8 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[8]) /* 0x40330800 */
|
||||
#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40330900 */
|
||||
|
||||
/*******************************************************************************
|
||||
* LPCOMP
|
||||
*******************************************************************************/
|
||||
|
||||
#define LPCOMP_BASE 0x40350000UL
|
||||
#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* CSD
|
||||
*******************************************************************************/
|
||||
|
||||
#define CSD0_BASE 0x40360000UL
|
||||
#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* TCPWM
|
||||
*******************************************************************************/
|
||||
|
||||
#define TCPWM0_BASE 0x40380000UL
|
||||
#define TCPWM1_BASE 0x40390000UL
|
||||
#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */
|
||||
#define TCPWM1 ((TCPWM_Type*) TCPWM1_BASE) /* 0x40390000 */
|
||||
#define TCPWM0_CNT0 ((TCPWM_CNT_Type*) &TCPWM0->CNT[0]) /* 0x40380100 */
|
||||
#define TCPWM0_CNT1 ((TCPWM_CNT_Type*) &TCPWM0->CNT[1]) /* 0x40380140 */
|
||||
#define TCPWM0_CNT2 ((TCPWM_CNT_Type*) &TCPWM0->CNT[2]) /* 0x40380180 */
|
||||
#define TCPWM0_CNT3 ((TCPWM_CNT_Type*) &TCPWM0->CNT[3]) /* 0x403801C0 */
|
||||
#define TCPWM0_CNT4 ((TCPWM_CNT_Type*) &TCPWM0->CNT[4]) /* 0x40380200 */
|
||||
#define TCPWM0_CNT5 ((TCPWM_CNT_Type*) &TCPWM0->CNT[5]) /* 0x40380240 */
|
||||
#define TCPWM0_CNT6 ((TCPWM_CNT_Type*) &TCPWM0->CNT[6]) /* 0x40380280 */
|
||||
#define TCPWM0_CNT7 ((TCPWM_CNT_Type*) &TCPWM0->CNT[7]) /* 0x403802C0 */
|
||||
#define TCPWM1_CNT0 ((TCPWM_CNT_Type*) &TCPWM1->CNT[0]) /* 0x40390100 */
|
||||
#define TCPWM1_CNT1 ((TCPWM_CNT_Type*) &TCPWM1->CNT[1]) /* 0x40390140 */
|
||||
#define TCPWM1_CNT2 ((TCPWM_CNT_Type*) &TCPWM1->CNT[2]) /* 0x40390180 */
|
||||
#define TCPWM1_CNT3 ((TCPWM_CNT_Type*) &TCPWM1->CNT[3]) /* 0x403901C0 */
|
||||
#define TCPWM1_CNT4 ((TCPWM_CNT_Type*) &TCPWM1->CNT[4]) /* 0x40390200 */
|
||||
#define TCPWM1_CNT5 ((TCPWM_CNT_Type*) &TCPWM1->CNT[5]) /* 0x40390240 */
|
||||
#define TCPWM1_CNT6 ((TCPWM_CNT_Type*) &TCPWM1->CNT[6]) /* 0x40390280 */
|
||||
#define TCPWM1_CNT7 ((TCPWM_CNT_Type*) &TCPWM1->CNT[7]) /* 0x403902C0 */
|
||||
#define TCPWM1_CNT8 ((TCPWM_CNT_Type*) &TCPWM1->CNT[8]) /* 0x40390300 */
|
||||
#define TCPWM1_CNT9 ((TCPWM_CNT_Type*) &TCPWM1->CNT[9]) /* 0x40390340 */
|
||||
#define TCPWM1_CNT10 ((TCPWM_CNT_Type*) &TCPWM1->CNT[10]) /* 0x40390380 */
|
||||
#define TCPWM1_CNT11 ((TCPWM_CNT_Type*) &TCPWM1->CNT[11]) /* 0x403903C0 */
|
||||
#define TCPWM1_CNT12 ((TCPWM_CNT_Type*) &TCPWM1->CNT[12]) /* 0x40390400 */
|
||||
#define TCPWM1_CNT13 ((TCPWM_CNT_Type*) &TCPWM1->CNT[13]) /* 0x40390440 */
|
||||
#define TCPWM1_CNT14 ((TCPWM_CNT_Type*) &TCPWM1->CNT[14]) /* 0x40390480 */
|
||||
#define TCPWM1_CNT15 ((TCPWM_CNT_Type*) &TCPWM1->CNT[15]) /* 0x403904C0 */
|
||||
#define TCPWM1_CNT16 ((TCPWM_CNT_Type*) &TCPWM1->CNT[16]) /* 0x40390500 */
|
||||
#define TCPWM1_CNT17 ((TCPWM_CNT_Type*) &TCPWM1->CNT[17]) /* 0x40390540 */
|
||||
#define TCPWM1_CNT18 ((TCPWM_CNT_Type*) &TCPWM1->CNT[18]) /* 0x40390580 */
|
||||
#define TCPWM1_CNT19 ((TCPWM_CNT_Type*) &TCPWM1->CNT[19]) /* 0x403905C0 */
|
||||
#define TCPWM1_CNT20 ((TCPWM_CNT_Type*) &TCPWM1->CNT[20]) /* 0x40390600 */
|
||||
#define TCPWM1_CNT21 ((TCPWM_CNT_Type*) &TCPWM1->CNT[21]) /* 0x40390640 */
|
||||
#define TCPWM1_CNT22 ((TCPWM_CNT_Type*) &TCPWM1->CNT[22]) /* 0x40390680 */
|
||||
#define TCPWM1_CNT23 ((TCPWM_CNT_Type*) &TCPWM1->CNT[23]) /* 0x403906C0 */
|
||||
|
||||
/*******************************************************************************
|
||||
* LCD
|
||||
*******************************************************************************/
|
||||
|
||||
#define LCD0_BASE 0x403B0000UL
|
||||
#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* BLE
|
||||
*******************************************************************************/
|
||||
|
||||
#define BLE_BASE 0x403C0000UL
|
||||
#define BLE ((BLE_Type*) BLE_BASE) /* 0x403C0000 */
|
||||
#define BLE_RCB_RCBLL ((BLE_RCB_RCBLL_Type*) &BLE->RCB.RCBLL) /* 0x403C0100 */
|
||||
#define BLE_RCB ((BLE_RCB_Type*) &BLE->RCB) /* 0x403C0000 */
|
||||
#define BLE_BLELL ((BLE_BLELL_Type*) &BLE->BLELL) /* 0x403C1000 */
|
||||
#define BLE_BLESS ((BLE_BLESS_Type*) &BLE->BLESS) /* 0x403DF000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* SMIF
|
||||
*******************************************************************************/
|
||||
|
||||
#define SMIF0_BASE 0x40420000UL
|
||||
#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */
|
||||
#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */
|
||||
#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */
|
||||
#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */
|
||||
#define SMIF0_DEVICE3 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[3]) /* 0x40420980 */
|
||||
|
||||
/*******************************************************************************
|
||||
* SCB
|
||||
*******************************************************************************/
|
||||
|
||||
#define SCB0_BASE 0x40610000UL
|
||||
#define SCB1_BASE 0x40620000UL
|
||||
#define SCB2_BASE 0x40630000UL
|
||||
#define SCB3_BASE 0x40640000UL
|
||||
#define SCB4_BASE 0x40650000UL
|
||||
#define SCB5_BASE 0x40660000UL
|
||||
#define SCB6_BASE 0x40670000UL
|
||||
#define SCB7_BASE 0x40680000UL
|
||||
#define SCB8_BASE 0x40690000UL
|
||||
#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40610000 */
|
||||
#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40620000 */
|
||||
#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40630000 */
|
||||
#define SCB3 ((CySCB_Type*) SCB3_BASE) /* 0x40640000 */
|
||||
#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40650000 */
|
||||
#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40660000 */
|
||||
#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40670000 */
|
||||
#define SCB7 ((CySCB_Type*) SCB7_BASE) /* 0x40680000 */
|
||||
#define SCB8 ((CySCB_Type*) SCB8_BASE) /* 0x40690000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* CTDAC
|
||||
*******************************************************************************/
|
||||
|
||||
#define CTDAC0_BASE 0x41140000UL
|
||||
#define CTDAC0 ((CTDAC_Type*) CTDAC0_BASE) /* 0x41140000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* SAR
|
||||
*******************************************************************************/
|
||||
|
||||
#define SAR_BASE 0x411D0000UL
|
||||
#define SAR ((SAR_Type*) SAR_BASE) /* 0x411D0000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* PASS
|
||||
*******************************************************************************/
|
||||
|
||||
#define PASS_BASE 0x411F0000UL
|
||||
#define PASS ((PASS_Type*) PASS_BASE) /* 0x411F0000 */
|
||||
#define PASS_AREF ((PASS_AREF_Type*) &PASS->AREF) /* 0x411F0E00 */
|
||||
|
||||
/*******************************************************************************
|
||||
* I2S
|
||||
*******************************************************************************/
|
||||
|
||||
#define I2S0_BASE 0x42A10000UL
|
||||
#define I2S0 ((I2S_Type*) I2S0_BASE) /* 0x42A10000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* PDM
|
||||
*******************************************************************************/
|
||||
|
||||
#define PDM0_BASE 0x42A20000UL
|
||||
#define PDM0 ((PDM_Type*) PDM0_BASE) /* 0x42A20000 */
|
||||
|
||||
|
||||
/* Backward compabitility definitions */
|
||||
#define I2S I2S0
|
||||
#define PDM PDM0
|
||||
|
||||
/** \} CY8C6316BZI-BLF03 */
|
||||
|
||||
#endif /* _CY8C6316BZI_BLF03_H_ */
|
||||
|
||||
|
||||
/* [] END OF FILE */
|
||||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -1,934 +0,0 @@
|
|||
/***************************************************************************//**
|
||||
* \file cy8c6336bzi_blf03.h
|
||||
*
|
||||
* \brief
|
||||
* CY8C6336BZI-BLF03 device header
|
||||
*
|
||||
* \note
|
||||
* Generator version: 1.3.0.1146
|
||||
* Database revision: rev#1050929
|
||||
*
|
||||
********************************************************************************
|
||||
* \copyright
|
||||
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
|
||||
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _CY8C6336BZI_BLF03_H_
|
||||
#define _CY8C6336BZI_BLF03_H_
|
||||
|
||||
/**
|
||||
* \addtogroup group_device CY8C6336BZI-BLF03
|
||||
* \{
|
||||
*/
|
||||
|
||||
/**
|
||||
* \addtogroup Configuration_of_CMSIS
|
||||
* \{
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Interrupt Number Definition
|
||||
*******************************************************************************/
|
||||
|
||||
typedef enum {
|
||||
/* ARM Cortex-M4 Core Interrupt Numbers */
|
||||
Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */
|
||||
NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */
|
||||
HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */
|
||||
MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */
|
||||
BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */
|
||||
UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
|
||||
SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */
|
||||
DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */
|
||||
PendSV_IRQn = -2, /*!< -2 Pendable request for system service */
|
||||
SysTick_IRQn = -1, /*!< -1 System Tick Timer */
|
||||
/* CY8C6336BZI-BLF03 Peripheral Interrupt Numbers */
|
||||
ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */
|
||||
ioss_interrupts_gpio_1_IRQn = 1, /*!< 1 [DeepSleep] GPIO Port Interrupt #1 */
|
||||
ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */
|
||||
ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */
|
||||
ioss_interrupts_gpio_4_IRQn = 4, /*!< 4 [DeepSleep] GPIO Port Interrupt #4 */
|
||||
ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */
|
||||
ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */
|
||||
ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */
|
||||
ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */
|
||||
ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */
|
||||
ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */
|
||||
ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */
|
||||
ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */
|
||||
ioss_interrupts_gpio_13_IRQn = 13, /*!< 13 [DeepSleep] GPIO Port Interrupt #13 */
|
||||
ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */
|
||||
ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */
|
||||
ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */
|
||||
lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */
|
||||
scb_8_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #8 (DeepSleep capable) */
|
||||
srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */
|
||||
srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */
|
||||
srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */
|
||||
srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */
|
||||
pass_interrupt_ctbs_IRQn = 23, /*!< 23 [DeepSleep] CTBm Interrupt (all CTBms) */
|
||||
bless_interrupt_IRQn = 24, /*!< 24 [DeepSleep] Bluetooth Radio interrupt */
|
||||
cpuss_interrupts_ipc_0_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */
|
||||
cpuss_interrupts_ipc_1_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */
|
||||
cpuss_interrupts_ipc_2_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */
|
||||
cpuss_interrupts_ipc_3_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */
|
||||
cpuss_interrupts_ipc_4_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */
|
||||
cpuss_interrupts_ipc_5_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */
|
||||
cpuss_interrupts_ipc_6_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */
|
||||
cpuss_interrupts_ipc_7_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */
|
||||
cpuss_interrupts_ipc_8_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */
|
||||
cpuss_interrupts_ipc_9_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */
|
||||
cpuss_interrupts_ipc_10_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */
|
||||
cpuss_interrupts_ipc_11_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */
|
||||
cpuss_interrupts_ipc_12_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */
|
||||
cpuss_interrupts_ipc_13_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */
|
||||
cpuss_interrupts_ipc_14_IRQn = 39, /*!< 39 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */
|
||||
cpuss_interrupts_ipc_15_IRQn = 40, /*!< 40 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */
|
||||
scb_0_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #0 */
|
||||
scb_1_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #1 */
|
||||
scb_2_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #2 */
|
||||
scb_3_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #3 */
|
||||
scb_4_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #4 */
|
||||
scb_5_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #5 */
|
||||
scb_6_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #6 */
|
||||
scb_7_interrupt_IRQn = 48, /*!< 48 [Active] Serial Communication Block #7 */
|
||||
csd_interrupt_IRQn = 49, /*!< 49 [Active] CSD (Capsense) interrupt */
|
||||
cpuss_interrupts_dw0_0_IRQn = 50, /*!< 50 [Active] CPUSS DataWire #0, Channel #0 */
|
||||
cpuss_interrupts_dw0_1_IRQn = 51, /*!< 51 [Active] CPUSS DataWire #0, Channel #1 */
|
||||
cpuss_interrupts_dw0_2_IRQn = 52, /*!< 52 [Active] CPUSS DataWire #0, Channel #2 */
|
||||
cpuss_interrupts_dw0_3_IRQn = 53, /*!< 53 [Active] CPUSS DataWire #0, Channel #3 */
|
||||
cpuss_interrupts_dw0_4_IRQn = 54, /*!< 54 [Active] CPUSS DataWire #0, Channel #4 */
|
||||
cpuss_interrupts_dw0_5_IRQn = 55, /*!< 55 [Active] CPUSS DataWire #0, Channel #5 */
|
||||
cpuss_interrupts_dw0_6_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #6 */
|
||||
cpuss_interrupts_dw0_7_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #7 */
|
||||
cpuss_interrupts_dw0_8_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #8 */
|
||||
cpuss_interrupts_dw0_9_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #9 */
|
||||
cpuss_interrupts_dw0_10_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #10 */
|
||||
cpuss_interrupts_dw0_11_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #11 */
|
||||
cpuss_interrupts_dw0_12_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #12 */
|
||||
cpuss_interrupts_dw0_13_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #13 */
|
||||
cpuss_interrupts_dw0_14_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #14 */
|
||||
cpuss_interrupts_dw0_15_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #15 */
|
||||
cpuss_interrupts_dw1_0_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #1, Channel #0 */
|
||||
cpuss_interrupts_dw1_1_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #1, Channel #1 */
|
||||
cpuss_interrupts_dw1_2_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #1, Channel #2 */
|
||||
cpuss_interrupts_dw1_3_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #1, Channel #3 */
|
||||
cpuss_interrupts_dw1_4_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #1, Channel #4 */
|
||||
cpuss_interrupts_dw1_5_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #1, Channel #5 */
|
||||
cpuss_interrupts_dw1_6_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #1, Channel #6 */
|
||||
cpuss_interrupts_dw1_7_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #1, Channel #7 */
|
||||
cpuss_interrupts_dw1_8_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #1, Channel #8 */
|
||||
cpuss_interrupts_dw1_9_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #1, Channel #9 */
|
||||
cpuss_interrupts_dw1_10_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #1, Channel #10 */
|
||||
cpuss_interrupts_dw1_11_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #1, Channel #11 */
|
||||
cpuss_interrupts_dw1_12_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #1, Channel #12 */
|
||||
cpuss_interrupts_dw1_13_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #1, Channel #13 */
|
||||
cpuss_interrupts_dw1_14_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #1, Channel #14 */
|
||||
cpuss_interrupts_dw1_15_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #1, Channel #15 */
|
||||
cpuss_interrupts_fault_0_IRQn = 82, /*!< 82 [Active] CPUSS Fault Structure Interrupt #0 */
|
||||
cpuss_interrupts_fault_1_IRQn = 83, /*!< 83 [Active] CPUSS Fault Structure Interrupt #1 */
|
||||
cpuss_interrupt_crypto_IRQn = 84, /*!< 84 [Active] CRYPTO Accelerator Interrupt */
|
||||
cpuss_interrupt_fm_IRQn = 85, /*!< 85 [Active] FLASH Macro Interrupt */
|
||||
cpuss_interrupts_cm0_cti_0_IRQn = 86, /*!< 86 [Active] CM0+ CTI #0 */
|
||||
cpuss_interrupts_cm0_cti_1_IRQn = 87, /*!< 87 [Active] CM0+ CTI #1 */
|
||||
cpuss_interrupts_cm4_cti_0_IRQn = 88, /*!< 88 [Active] CM4 CTI #0 */
|
||||
cpuss_interrupts_cm4_cti_1_IRQn = 89, /*!< 89 [Active] CM4 CTI #1 */
|
||||
tcpwm_0_interrupts_0_IRQn = 90, /*!< 90 [Active] TCPWM #0, Counter #0 */
|
||||
tcpwm_0_interrupts_1_IRQn = 91, /*!< 91 [Active] TCPWM #0, Counter #1 */
|
||||
tcpwm_0_interrupts_2_IRQn = 92, /*!< 92 [Active] TCPWM #0, Counter #2 */
|
||||
tcpwm_0_interrupts_3_IRQn = 93, /*!< 93 [Active] TCPWM #0, Counter #3 */
|
||||
tcpwm_0_interrupts_4_IRQn = 94, /*!< 94 [Active] TCPWM #0, Counter #4 */
|
||||
tcpwm_0_interrupts_5_IRQn = 95, /*!< 95 [Active] TCPWM #0, Counter #5 */
|
||||
tcpwm_0_interrupts_6_IRQn = 96, /*!< 96 [Active] TCPWM #0, Counter #6 */
|
||||
tcpwm_0_interrupts_7_IRQn = 97, /*!< 97 [Active] TCPWM #0, Counter #7 */
|
||||
tcpwm_1_interrupts_0_IRQn = 98, /*!< 98 [Active] TCPWM #1, Counter #0 */
|
||||
tcpwm_1_interrupts_1_IRQn = 99, /*!< 99 [Active] TCPWM #1, Counter #1 */
|
||||
tcpwm_1_interrupts_2_IRQn = 100, /*!< 100 [Active] TCPWM #1, Counter #2 */
|
||||
tcpwm_1_interrupts_3_IRQn = 101, /*!< 101 [Active] TCPWM #1, Counter #3 */
|
||||
tcpwm_1_interrupts_4_IRQn = 102, /*!< 102 [Active] TCPWM #1, Counter #4 */
|
||||
tcpwm_1_interrupts_5_IRQn = 103, /*!< 103 [Active] TCPWM #1, Counter #5 */
|
||||
tcpwm_1_interrupts_6_IRQn = 104, /*!< 104 [Active] TCPWM #1, Counter #6 */
|
||||
tcpwm_1_interrupts_7_IRQn = 105, /*!< 105 [Active] TCPWM #1, Counter #7 */
|
||||
tcpwm_1_interrupts_8_IRQn = 106, /*!< 106 [Active] TCPWM #1, Counter #8 */
|
||||
tcpwm_1_interrupts_9_IRQn = 107, /*!< 107 [Active] TCPWM #1, Counter #9 */
|
||||
tcpwm_1_interrupts_10_IRQn = 108, /*!< 108 [Active] TCPWM #1, Counter #10 */
|
||||
tcpwm_1_interrupts_11_IRQn = 109, /*!< 109 [Active] TCPWM #1, Counter #11 */
|
||||
tcpwm_1_interrupts_12_IRQn = 110, /*!< 110 [Active] TCPWM #1, Counter #12 */
|
||||
tcpwm_1_interrupts_13_IRQn = 111, /*!< 111 [Active] TCPWM #1, Counter #13 */
|
||||
tcpwm_1_interrupts_14_IRQn = 112, /*!< 112 [Active] TCPWM #1, Counter #14 */
|
||||
tcpwm_1_interrupts_15_IRQn = 113, /*!< 113 [Active] TCPWM #1, Counter #15 */
|
||||
tcpwm_1_interrupts_16_IRQn = 114, /*!< 114 [Active] TCPWM #1, Counter #16 */
|
||||
tcpwm_1_interrupts_17_IRQn = 115, /*!< 115 [Active] TCPWM #1, Counter #17 */
|
||||
tcpwm_1_interrupts_18_IRQn = 116, /*!< 116 [Active] TCPWM #1, Counter #18 */
|
||||
tcpwm_1_interrupts_19_IRQn = 117, /*!< 117 [Active] TCPWM #1, Counter #19 */
|
||||
tcpwm_1_interrupts_20_IRQn = 118, /*!< 118 [Active] TCPWM #1, Counter #20 */
|
||||
tcpwm_1_interrupts_21_IRQn = 119, /*!< 119 [Active] TCPWM #1, Counter #21 */
|
||||
tcpwm_1_interrupts_22_IRQn = 120, /*!< 120 [Active] TCPWM #1, Counter #22 */
|
||||
tcpwm_1_interrupts_23_IRQn = 121, /*!< 121 [Active] TCPWM #1, Counter #23 */
|
||||
udb_interrupts_0_IRQn = 122, /*!< 122 [Active] UDB Interrupt #0 */
|
||||
udb_interrupts_1_IRQn = 123, /*!< 123 [Active] UDB Interrupt #1 */
|
||||
udb_interrupts_2_IRQn = 124, /*!< 124 [Active] UDB Interrupt #2 */
|
||||
udb_interrupts_3_IRQn = 125, /*!< 125 [Active] UDB Interrupt #3 */
|
||||
udb_interrupts_4_IRQn = 126, /*!< 126 [Active] UDB Interrupt #4 */
|
||||
udb_interrupts_5_IRQn = 127, /*!< 127 [Active] UDB Interrupt #5 */
|
||||
udb_interrupts_6_IRQn = 128, /*!< 128 [Active] UDB Interrupt #6 */
|
||||
udb_interrupts_7_IRQn = 129, /*!< 129 [Active] UDB Interrupt #7 */
|
||||
udb_interrupts_8_IRQn = 130, /*!< 130 [Active] UDB Interrupt #8 */
|
||||
udb_interrupts_9_IRQn = 131, /*!< 131 [Active] UDB Interrupt #9 */
|
||||
udb_interrupts_10_IRQn = 132, /*!< 132 [Active] UDB Interrupt #10 */
|
||||
udb_interrupts_11_IRQn = 133, /*!< 133 [Active] UDB Interrupt #11 */
|
||||
udb_interrupts_12_IRQn = 134, /*!< 134 [Active] UDB Interrupt #12 */
|
||||
udb_interrupts_13_IRQn = 135, /*!< 135 [Active] UDB Interrupt #13 */
|
||||
udb_interrupts_14_IRQn = 136, /*!< 136 [Active] UDB Interrupt #14 */
|
||||
udb_interrupts_15_IRQn = 137, /*!< 137 [Active] UDB Interrupt #15 */
|
||||
pass_interrupt_sar_IRQn = 138, /*!< 138 [Active] SAR ADC interrupt */
|
||||
audioss_interrupt_i2s_IRQn = 139, /*!< 139 [Active] I2S Audio interrupt */
|
||||
audioss_interrupt_pdm_IRQn = 140, /*!< 140 [Active] PDM/PCM Audio interrupt */
|
||||
profile_interrupt_IRQn = 141, /*!< 141 [Active] Energy Profiler interrupt */
|
||||
smif_interrupt_IRQn = 142, /*!< 142 [Active] Serial Memory Interface interrupt */
|
||||
usb_interrupt_hi_IRQn = 143, /*!< 143 [Active] USB Interrupt */
|
||||
usb_interrupt_med_IRQn = 144, /*!< 144 [Active] USB Interrupt */
|
||||
usb_interrupt_lo_IRQn = 145, /*!< 145 [Active] USB Interrupt */
|
||||
pass_interrupt_dacs_IRQn = 146, /*!< 146 [Active] Consolidated interrrupt for all DACs */
|
||||
unconnected_IRQn = 240 /*!< 240 Unconnected */
|
||||
} IRQn_Type;
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Processor and Core Peripheral Section
|
||||
*******************************************************************************/
|
||||
|
||||
/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */
|
||||
#define __CM4_REV 0x0001U /*!< CM4 Core Revision */
|
||||
#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
|
||||
#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */
|
||||
#define __MPU_PRESENT 1 /*!< MPU present or not */
|
||||
#define __FPU_PRESENT 1 /*!< FPU present or not */
|
||||
#define __CM0P_PRESENT 0 /*!< CM0P present or not */
|
||||
|
||||
/** \} Configuration_of_CMSIS */
|
||||
|
||||
/* Memory Blocks */
|
||||
#define CY_ROM_BASE 0x00000000UL
|
||||
#define CY_ROM_SIZE 0x00020000UL
|
||||
#define CY_SRAM0_BASE 0x08000000UL
|
||||
#define CY_SRAM0_SIZE 0x00020000UL
|
||||
#define CY_FLASH_BASE 0x10000000UL
|
||||
#define CY_FLASH_SIZE 0x00080000UL
|
||||
#define CY_EM_EEPROM_BASE 0x14000000UL
|
||||
#define CY_EM_EEPROM_SIZE 0x00008000UL
|
||||
#define CY_XIP_BASE 0x18000000UL
|
||||
#define CY_XIP_SIZE 0x08000000UL
|
||||
#define CY_SFLASH_BASE 0x16000000UL
|
||||
#define CY_SFLASH_SIZE 0x00008000UL
|
||||
#define CY_EFUSE_BASE 0x402C0800UL
|
||||
#define CY_EFUSE_SIZE 0x00000200UL
|
||||
|
||||
#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */
|
||||
#include "system_psoc6.h" /*!< PSoC 6 System */
|
||||
|
||||
/* IP List */
|
||||
#define CY_IP_MXTCPWM 1u
|
||||
#define CY_IP_MXTCPWM_INSTANCES 2u
|
||||
#define CY_IP_MXTCPWM_VERSION 1u
|
||||
#define CY_IP_MXCSDV2 1u
|
||||
#define CY_IP_MXCSDV2_INSTANCES 1u
|
||||
#define CY_IP_MXCSDV2_VERSION 1u
|
||||
#define CY_IP_MXLCD 1u
|
||||
#define CY_IP_MXLCD_INSTANCES 1u
|
||||
#define CY_IP_MXLCD_VERSION 1u
|
||||
#define CY_IP_MXS40SRSS 1u
|
||||
#define CY_IP_MXS40SRSS_INSTANCES 1u
|
||||
#define CY_IP_MXS40SRSS_VERSION 1u
|
||||
#define CY_IP_MXS40SRSS_RTC 1u
|
||||
#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u
|
||||
#define CY_IP_MXS40SRSS_RTC_VERSION 1u
|
||||
#define CY_IP_MXS40SRSS_MCWDT 1u
|
||||
#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u
|
||||
#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u
|
||||
#define CY_IP_MXSCB 1u
|
||||
#define CY_IP_MXSCB_INSTANCES 9u
|
||||
#define CY_IP_MXSCB_VERSION 1u
|
||||
#define CY_IP_MXPERI 1u
|
||||
#define CY_IP_MXPERI_INSTANCES 1u
|
||||
#define CY_IP_MXPERI_VERSION 1u
|
||||
#define CY_IP_MXPERI_TR 1u
|
||||
#define CY_IP_MXPERI_TR_INSTANCES 1u
|
||||
#define CY_IP_MXPERI_TR_VERSION 1u
|
||||
#define CY_IP_M4CPUSS 1u
|
||||
#define CY_IP_M4CPUSS_INSTANCES 1u
|
||||
#define CY_IP_M4CPUSS_VERSION 1u
|
||||
#define CY_IP_M4CPUSS_DMA 1u
|
||||
#define CY_IP_M4CPUSS_DMA_INSTANCES 2u
|
||||
#define CY_IP_M4CPUSS_DMA_VERSION 1u
|
||||
#define CY_IP_MXBLESS 1u
|
||||
#define CY_IP_MXBLESS_INSTANCES 1u
|
||||
#define CY_IP_MXBLESS_VERSION 1u
|
||||
#define CY_IP_MXAUDIOSS 1u
|
||||
#define CY_IP_MXAUDIOSS_INSTANCES 1u
|
||||
#define CY_IP_MXAUDIOSS_VERSION 1u
|
||||
#define CY_IP_MXLPCOMP 1u
|
||||
#define CY_IP_MXLPCOMP_INSTANCES 1u
|
||||
#define CY_IP_MXLPCOMP_VERSION 1u
|
||||
#define CY_IP_MXS40PASS 1u
|
||||
#define CY_IP_MXS40PASS_INSTANCES 1u
|
||||
#define CY_IP_MXS40PASS_VERSION 1u
|
||||
#define CY_IP_MXS40PASS_SAR 1u
|
||||
#define CY_IP_MXS40PASS_SAR_INSTANCES 16u
|
||||
#define CY_IP_MXS40PASS_SAR_VERSION 1u
|
||||
#define CY_IP_MXS40PASS_CTDAC 1u
|
||||
#define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u
|
||||
#define CY_IP_MXS40PASS_CTDAC_VERSION 1u
|
||||
#define CY_IP_MXSMIF 1u
|
||||
#define CY_IP_MXSMIF_INSTANCES 1u
|
||||
#define CY_IP_MXSMIF_VERSION 1u
|
||||
#define CY_IP_MXS40IOSS 1u
|
||||
#define CY_IP_MXS40IOSS_INSTANCES 1u
|
||||
#define CY_IP_MXS40IOSS_VERSION 1u
|
||||
#define CY_IP_MXEFUSE 1u
|
||||
#define CY_IP_MXEFUSE_INSTANCES 1u
|
||||
#define CY_IP_MXEFUSE_VERSION 1u
|
||||
#define CY_IP_MXPROFILE 1u
|
||||
#define CY_IP_MXPROFILE_INSTANCES 1u
|
||||
#define CY_IP_MXPROFILE_VERSION 1u
|
||||
|
||||
#include "psoc6able2_config.h"
|
||||
#include "gpio_psoc6able2_116_bga_ble.h"
|
||||
|
||||
#define CY_DEVICE_PSOC6ABLE2
|
||||
#define CY_SILICON_ID 0xE2202100UL
|
||||
#define CY_HF_CLK_MAX_FREQ 150000000UL
|
||||
|
||||
#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL
|
||||
|
||||
/*******************************************************************************
|
||||
* SFLASH
|
||||
*******************************************************************************/
|
||||
|
||||
#define SFLASH_BASE 0x16000000UL
|
||||
#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* PERI
|
||||
*******************************************************************************/
|
||||
|
||||
#define PERI_BASE 0x40010000UL
|
||||
#define PERI_PPU_GR_MMIO0_BASE 0x40015000UL
|
||||
#define PERI_PPU_GR_MMIO1_BASE 0x40015040UL
|
||||
#define PERI_PPU_GR_MMIO2_BASE 0x40015080UL
|
||||
#define PERI_PPU_GR_MMIO3_BASE 0x400150C0UL
|
||||
#define PERI_PPU_GR_MMIO4_BASE 0x40015100UL
|
||||
#define PERI_PPU_GR_MMIO6_BASE 0x40015180UL
|
||||
#define PERI_PPU_GR_MMIO9_BASE 0x40015240UL
|
||||
#define PERI_PPU_GR_MMIO10_BASE 0x40015280UL
|
||||
#define PERI_GR_PPU_SL_PERI_GR1_BASE 0x40100000UL
|
||||
#define PERI_GR_PPU_SL_CRYPTO_BASE 0x40100040UL
|
||||
#define PERI_GR_PPU_SL_PERI_GR2_BASE 0x40200000UL
|
||||
#define PERI_GR_PPU_SL_CPUSS_BASE 0x40200040UL
|
||||
#define PERI_GR_PPU_SL_FAULT_BASE 0x40200080UL
|
||||
#define PERI_GR_PPU_SL_IPC_BASE 0x402000C0UL
|
||||
#define PERI_GR_PPU_SL_PROT_BASE 0x40200100UL
|
||||
#define PERI_GR_PPU_SL_FLASHC_BASE 0x40200140UL
|
||||
#define PERI_GR_PPU_SL_SRSS_BASE 0x40200180UL
|
||||
#define PERI_GR_PPU_SL_BACKUP_BASE 0x402001C0UL
|
||||
#define PERI_GR_PPU_SL_DW0_BASE 0x40200200UL
|
||||
#define PERI_GR_PPU_SL_DW1_BASE 0x40200240UL
|
||||
#define PERI_GR_PPU_SL_EFUSE_BASE 0x40200300UL
|
||||
#define PERI_GR_PPU_SL_PROFILE_BASE 0x40200340UL
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT0_BASE 0x40201000UL
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT1_BASE 0x40201040UL
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT2_BASE 0x40201080UL
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT3_BASE 0x402010C0UL
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT4_BASE 0x40201100UL
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT5_BASE 0x40201140UL
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT6_BASE 0x40201180UL
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT7_BASE 0x402011C0UL
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT0_BASE 0x40201200UL
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT1_BASE 0x40201240UL
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT2_BASE 0x40201280UL
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT3_BASE 0x402012C0UL
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT4_BASE 0x40201300UL
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT5_BASE 0x40201340UL
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT6_BASE 0x40201380UL
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT7_BASE 0x402013C0UL
|
||||
#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT0_BASE 0x40201400UL
|
||||
#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT1_BASE 0x40201440UL
|
||||
#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT2_BASE 0x40201480UL
|
||||
#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT3_BASE 0x402014C0UL
|
||||
#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT0_BASE 0x40201500UL
|
||||
#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT1_BASE 0x40201540UL
|
||||
#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT2_BASE 0x40201580UL
|
||||
#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT3_BASE 0x402015C0UL
|
||||
#define PERI_GR_PPU_RG_SMPU_BASE 0x40201600UL
|
||||
#define PERI_GR_PPU_RG_MPU_CM0P_BASE 0x40201640UL
|
||||
#define PERI_GR_PPU_RG_MPU_CRYPTO_BASE 0x40201680UL
|
||||
#define PERI_GR_PPU_RG_MPU_CM4_BASE 0x402016C0UL
|
||||
#define PERI_GR_PPU_RG_MPU_TC_BASE 0x40201700UL
|
||||
#define PERI_GR_PPU_SL_PERI_GR3_BASE 0x40300000UL
|
||||
#define PERI_GR_PPU_SL_HSIOM_BASE 0x40300040UL
|
||||
#define PERI_GR_PPU_SL_GPIO_BASE 0x40300080UL
|
||||
#define PERI_GR_PPU_SL_SMARTIO_BASE 0x403000C0UL
|
||||
#define PERI_GR_PPU_SL_UDB_BASE 0x40300100UL
|
||||
#define PERI_GR_PPU_SL_LPCOMP_BASE 0x40300140UL
|
||||
#define PERI_GR_PPU_SL_CSD_BASE 0x40300180UL
|
||||
#define PERI_GR_PPU_SL_TCPWM0_BASE 0x40300200UL
|
||||
#define PERI_GR_PPU_SL_TCPWM1_BASE 0x40300240UL
|
||||
#define PERI_GR_PPU_SL_LCD_BASE 0x40300280UL
|
||||
#define PERI_GR_PPU_SL_BLE_BASE 0x403002C0UL
|
||||
#define PERI_GR_PPU_SL_USBFS_BASE 0x40300300UL
|
||||
#define PERI_GR_PPU_SL_PERI_GR4_BASE 0x40400000UL
|
||||
#define PERI_GR_PPU_SL_SMIF_BASE 0x40400080UL
|
||||
#define PERI_GR_PPU_SL_PERI_GR6_BASE 0x40600000UL
|
||||
#define PERI_GR_PPU_SL_SCB0_BASE 0x40600040UL
|
||||
#define PERI_GR_PPU_SL_SCB1_BASE 0x40600080UL
|
||||
#define PERI_GR_PPU_SL_SCB2_BASE 0x406000C0UL
|
||||
#define PERI_GR_PPU_SL_SCB3_BASE 0x40600100UL
|
||||
#define PERI_GR_PPU_SL_SCB4_BASE 0x40600140UL
|
||||
#define PERI_GR_PPU_SL_SCB5_BASE 0x40600180UL
|
||||
#define PERI_GR_PPU_SL_SCB6_BASE 0x406001C0UL
|
||||
#define PERI_GR_PPU_SL_SCB7_BASE 0x40600200UL
|
||||
#define PERI_GR_PPU_SL_SCB8_BASE 0x40600240UL
|
||||
#define PERI_GR_PPU_SL_PERI_GR9_BASE 0x41000000UL
|
||||
#define PERI_GR_PPU_SL_PASS_BASE 0x41000040UL
|
||||
#define PERI_GR_PPU_SL_PERI_GR10_BASE 0x42A00000UL
|
||||
#define PERI_GR_PPU_SL_I2S_BASE 0x42A00040UL
|
||||
#define PERI_GR_PPU_SL_PDM_BASE 0x42A00080UL
|
||||
#define PERI ((PERI_Type*) PERI_BASE) /* 0x40010000 */
|
||||
#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40010000 */
|
||||
#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40010040 */
|
||||
#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40010080 */
|
||||
#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x400100C0 */
|
||||
#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40010100 */
|
||||
#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x40010180 */
|
||||
#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40010240 */
|
||||
#define PERI_GR10 ((PERI_GR_Type*) &PERI->GR[10]) /* 0x40010280 */
|
||||
#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40012000 */
|
||||
#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40012200 */
|
||||
#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40012400 */
|
||||
#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40012600 */
|
||||
#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40012800 */
|
||||
#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40012A00 */
|
||||
#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40012C00 */
|
||||
#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40012E00 */
|
||||
#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x40013000 */
|
||||
#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x40013200 */
|
||||
#define PERI_TR_GR10 ((PERI_TR_GR_Type*) &PERI->TR_GR[10]) /* 0x40013400 */
|
||||
#define PERI_TR_GR11 ((PERI_TR_GR_Type*) &PERI->TR_GR[11]) /* 0x40013600 */
|
||||
#define PERI_TR_GR12 ((PERI_TR_GR_Type*) &PERI->TR_GR[12]) /* 0x40013800 */
|
||||
#define PERI_TR_GR13 ((PERI_TR_GR_Type*) &PERI->TR_GR[13]) /* 0x40013A00 */
|
||||
#define PERI_TR_GR14 ((PERI_TR_GR_Type*) &PERI->TR_GR[14]) /* 0x40013C00 */
|
||||
#define PERI_PPU_PR0 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[0]) /* 0x40014000 */
|
||||
#define PERI_PPU_PR1 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[1]) /* 0x40014040 */
|
||||
#define PERI_PPU_PR2 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[2]) /* 0x40014080 */
|
||||
#define PERI_PPU_PR3 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[3]) /* 0x400140C0 */
|
||||
#define PERI_PPU_PR4 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[4]) /* 0x40014100 */
|
||||
#define PERI_PPU_PR5 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[5]) /* 0x40014140 */
|
||||
#define PERI_PPU_PR6 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[6]) /* 0x40014180 */
|
||||
#define PERI_PPU_PR7 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[7]) /* 0x400141C0 */
|
||||
#define PERI_PPU_PR8 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[8]) /* 0x40014200 */
|
||||
#define PERI_PPU_PR9 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[9]) /* 0x40014240 */
|
||||
#define PERI_PPU_PR10 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[10]) /* 0x40014280 */
|
||||
#define PERI_PPU_PR11 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[11]) /* 0x400142C0 */
|
||||
#define PERI_PPU_PR12 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[12]) /* 0x40014300 */
|
||||
#define PERI_PPU_PR13 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[13]) /* 0x40014340 */
|
||||
#define PERI_PPU_PR14 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[14]) /* 0x40014380 */
|
||||
#define PERI_PPU_PR15 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[15]) /* 0x400143C0 */
|
||||
#define PERI_PPU_GR0 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[0]) /* 0x40015000 */
|
||||
#define PERI_PPU_GR1 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[1]) /* 0x40015040 */
|
||||
#define PERI_PPU_GR2 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[2]) /* 0x40015080 */
|
||||
#define PERI_PPU_GR3 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[3]) /* 0x400150C0 */
|
||||
#define PERI_PPU_GR4 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[4]) /* 0x40015100 */
|
||||
#define PERI_PPU_GR6 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[6]) /* 0x40015180 */
|
||||
#define PERI_PPU_GR9 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[9]) /* 0x40015240 */
|
||||
#define PERI_PPU_GR10 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[10]) /* 0x40015280 */
|
||||
#define PERI_PPU_GR_MMIO0 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO0_BASE) /* 0x40015000 */
|
||||
#define PERI_PPU_GR_MMIO1 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO1_BASE) /* 0x40015040 */
|
||||
#define PERI_PPU_GR_MMIO2 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO2_BASE) /* 0x40015080 */
|
||||
#define PERI_PPU_GR_MMIO3 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO3_BASE) /* 0x400150C0 */
|
||||
#define PERI_PPU_GR_MMIO4 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO4_BASE) /* 0x40015100 */
|
||||
#define PERI_PPU_GR_MMIO6 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO6_BASE) /* 0x40015180 */
|
||||
#define PERI_PPU_GR_MMIO9 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO9_BASE) /* 0x40015240 */
|
||||
#define PERI_PPU_GR_MMIO10 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO10_BASE) /* 0x40015280 */
|
||||
#define PERI_GR_PPU_SL_PERI_GR1 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR1_BASE) /* 0x40100000 */
|
||||
#define PERI_GR_PPU_SL_CRYPTO ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_CRYPTO_BASE) /* 0x40100040 */
|
||||
#define PERI_GR_PPU_SL_PERI_GR2 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR2_BASE) /* 0x40200000 */
|
||||
#define PERI_GR_PPU_SL_CPUSS ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_CPUSS_BASE) /* 0x40200040 */
|
||||
#define PERI_GR_PPU_SL_FAULT ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_FAULT_BASE) /* 0x40200080 */
|
||||
#define PERI_GR_PPU_SL_IPC ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_IPC_BASE) /* 0x402000C0 */
|
||||
#define PERI_GR_PPU_SL_PROT ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PROT_BASE) /* 0x40200100 */
|
||||
#define PERI_GR_PPU_SL_FLASHC ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_FLASHC_BASE) /* 0x40200140 */
|
||||
#define PERI_GR_PPU_SL_SRSS ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SRSS_BASE) /* 0x40200180 */
|
||||
#define PERI_GR_PPU_SL_BACKUP ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_BACKUP_BASE) /* 0x402001C0 */
|
||||
#define PERI_GR_PPU_SL_DW0 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_DW0_BASE) /* 0x40200200 */
|
||||
#define PERI_GR_PPU_SL_DW1 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_DW1_BASE) /* 0x40200240 */
|
||||
#define PERI_GR_PPU_SL_EFUSE ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_EFUSE_BASE) /* 0x40200300 */
|
||||
#define PERI_GR_PPU_SL_PROFILE ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PROFILE_BASE) /* 0x40200340 */
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT0 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT0_BASE) /* 0x40201000 */
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT1 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT1_BASE) /* 0x40201040 */
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT2 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT2_BASE) /* 0x40201080 */
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT3 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT3_BASE) /* 0x402010C0 */
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT4 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT4_BASE) /* 0x40201100 */
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT5 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT5_BASE) /* 0x40201140 */
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT6 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT6_BASE) /* 0x40201180 */
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT7 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT7_BASE) /* 0x402011C0 */
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT0 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT0_BASE) /* 0x40201200 */
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT1 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT1_BASE) /* 0x40201240 */
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT2 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT2_BASE) /* 0x40201280 */
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT3 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT3_BASE) /* 0x402012C0 */
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT4 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT4_BASE) /* 0x40201300 */
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT5 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT5_BASE) /* 0x40201340 */
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT6 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT6_BASE) /* 0x40201380 */
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT7 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT7_BASE) /* 0x402013C0 */
|
||||
#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT0 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW0_DW_CH_STRUCT0_BASE) /* 0x40201400 */
|
||||
#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT1 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW0_DW_CH_STRUCT1_BASE) /* 0x40201440 */
|
||||
#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT2 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW0_DW_CH_STRUCT2_BASE) /* 0x40201480 */
|
||||
#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT3 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW0_DW_CH_STRUCT3_BASE) /* 0x402014C0 */
|
||||
#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT0 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW1_DW_CH_STRUCT0_BASE) /* 0x40201500 */
|
||||
#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT1 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW1_DW_CH_STRUCT1_BASE) /* 0x40201540 */
|
||||
#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT2 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW1_DW_CH_STRUCT2_BASE) /* 0x40201580 */
|
||||
#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT3 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW1_DW_CH_STRUCT3_BASE) /* 0x402015C0 */
|
||||
#define PERI_GR_PPU_RG_SMPU ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_SMPU_BASE) /* 0x40201600 */
|
||||
#define PERI_GR_PPU_RG_MPU_CM0P ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_MPU_CM0P_BASE) /* 0x40201640 */
|
||||
#define PERI_GR_PPU_RG_MPU_CRYPTO ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_MPU_CRYPTO_BASE) /* 0x40201680 */
|
||||
#define PERI_GR_PPU_RG_MPU_CM4 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_MPU_CM4_BASE) /* 0x402016C0 */
|
||||
#define PERI_GR_PPU_RG_MPU_TC ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_MPU_TC_BASE) /* 0x40201700 */
|
||||
#define PERI_GR_PPU_SL_PERI_GR3 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR3_BASE) /* 0x40300000 */
|
||||
#define PERI_GR_PPU_SL_HSIOM ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_HSIOM_BASE) /* 0x40300040 */
|
||||
#define PERI_GR_PPU_SL_GPIO ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_GPIO_BASE) /* 0x40300080 */
|
||||
#define PERI_GR_PPU_SL_SMARTIO ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SMARTIO_BASE) /* 0x403000C0 */
|
||||
#define PERI_GR_PPU_SL_UDB ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_UDB_BASE) /* 0x40300100 */
|
||||
#define PERI_GR_PPU_SL_LPCOMP ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_LPCOMP_BASE) /* 0x40300140 */
|
||||
#define PERI_GR_PPU_SL_CSD ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_CSD_BASE) /* 0x40300180 */
|
||||
#define PERI_GR_PPU_SL_TCPWM0 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_TCPWM0_BASE) /* 0x40300200 */
|
||||
#define PERI_GR_PPU_SL_TCPWM1 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_TCPWM1_BASE) /* 0x40300240 */
|
||||
#define PERI_GR_PPU_SL_LCD ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_LCD_BASE) /* 0x40300280 */
|
||||
#define PERI_GR_PPU_SL_BLE ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_BLE_BASE) /* 0x403002C0 */
|
||||
#define PERI_GR_PPU_SL_USBFS ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_USBFS_BASE) /* 0x40300300 */
|
||||
#define PERI_GR_PPU_SL_PERI_GR4 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR4_BASE) /* 0x40400000 */
|
||||
#define PERI_GR_PPU_SL_SMIF ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SMIF_BASE) /* 0x40400080 */
|
||||
#define PERI_GR_PPU_SL_PERI_GR6 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR6_BASE) /* 0x40600000 */
|
||||
#define PERI_GR_PPU_SL_SCB0 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB0_BASE) /* 0x40600040 */
|
||||
#define PERI_GR_PPU_SL_SCB1 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB1_BASE) /* 0x40600080 */
|
||||
#define PERI_GR_PPU_SL_SCB2 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB2_BASE) /* 0x406000C0 */
|
||||
#define PERI_GR_PPU_SL_SCB3 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB3_BASE) /* 0x40600100 */
|
||||
#define PERI_GR_PPU_SL_SCB4 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB4_BASE) /* 0x40600140 */
|
||||
#define PERI_GR_PPU_SL_SCB5 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB5_BASE) /* 0x40600180 */
|
||||
#define PERI_GR_PPU_SL_SCB6 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB6_BASE) /* 0x406001C0 */
|
||||
#define PERI_GR_PPU_SL_SCB7 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB7_BASE) /* 0x40600200 */
|
||||
#define PERI_GR_PPU_SL_SCB8 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB8_BASE) /* 0x40600240 */
|
||||
#define PERI_GR_PPU_SL_PERI_GR9 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR9_BASE) /* 0x41000000 */
|
||||
#define PERI_GR_PPU_SL_PASS ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PASS_BASE) /* 0x41000040 */
|
||||
#define PERI_GR_PPU_SL_PERI_GR10 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR10_BASE) /* 0x42A00000 */
|
||||
#define PERI_GR_PPU_SL_I2S ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_I2S_BASE) /* 0x42A00040 */
|
||||
#define PERI_GR_PPU_SL_PDM ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PDM_BASE) /* 0x42A00080 */
|
||||
|
||||
/*******************************************************************************
|
||||
* CPUSS
|
||||
*******************************************************************************/
|
||||
|
||||
#define CPUSS_BASE 0x40210000UL
|
||||
#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40210000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* FAULT
|
||||
*******************************************************************************/
|
||||
|
||||
#define FAULT_BASE 0x40220000UL
|
||||
#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40220000 */
|
||||
#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40220000 */
|
||||
#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40220100 */
|
||||
|
||||
/*******************************************************************************
|
||||
* IPC
|
||||
*******************************************************************************/
|
||||
|
||||
#define IPC_BASE 0x40230000UL
|
||||
#define IPC ((IPC_Type*) IPC_BASE) /* 0x40230000 */
|
||||
#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40230000 */
|
||||
#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40230020 */
|
||||
#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40230040 */
|
||||
#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40230060 */
|
||||
#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40230080 */
|
||||
#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402300A0 */
|
||||
#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402300C0 */
|
||||
#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402300E0 */
|
||||
#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40230100 */
|
||||
#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40230120 */
|
||||
#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40230140 */
|
||||
#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40230160 */
|
||||
#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40230180 */
|
||||
#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402301A0 */
|
||||
#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402301C0 */
|
||||
#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402301E0 */
|
||||
#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40231000 */
|
||||
#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40231020 */
|
||||
#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40231040 */
|
||||
#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40231060 */
|
||||
#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40231080 */
|
||||
#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402310A0 */
|
||||
#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402310C0 */
|
||||
#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402310E0 */
|
||||
#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40231100 */
|
||||
#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40231120 */
|
||||
#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40231140 */
|
||||
#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40231160 */
|
||||
#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40231180 */
|
||||
#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402311A0 */
|
||||
#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402311C0 */
|
||||
#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402311E0 */
|
||||
|
||||
/*******************************************************************************
|
||||
* PROT
|
||||
*******************************************************************************/
|
||||
|
||||
#define PROT_BASE 0x40240000UL
|
||||
#define PROT ((PROT_Type*) PROT_BASE) /* 0x40240000 */
|
||||
#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40242000 */
|
||||
#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40242040 */
|
||||
#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40242080 */
|
||||
#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402420C0 */
|
||||
#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40242100 */
|
||||
#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40242140 */
|
||||
#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40242180 */
|
||||
#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402421C0 */
|
||||
#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40242200 */
|
||||
#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40242240 */
|
||||
#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40242280 */
|
||||
#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402422C0 */
|
||||
#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40242300 */
|
||||
#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40242340 */
|
||||
#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40242380 */
|
||||
#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402423C0 */
|
||||
#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */
|
||||
#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */
|
||||
#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */
|
||||
#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */
|
||||
#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */
|
||||
#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */
|
||||
#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */
|
||||
#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */
|
||||
#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */
|
||||
#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */
|
||||
#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */
|
||||
#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */
|
||||
#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */
|
||||
#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */
|
||||
#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */
|
||||
#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */
|
||||
#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */
|
||||
#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40244000 */
|
||||
#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40244400 */
|
||||
#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40244800 */
|
||||
#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40244C00 */
|
||||
#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40245000 */
|
||||
#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40245400 */
|
||||
#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40245800 */
|
||||
#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40245C00 */
|
||||
#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40246000 */
|
||||
#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40246400 */
|
||||
#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40246800 */
|
||||
#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40246C00 */
|
||||
#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40247000 */
|
||||
#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40247400 */
|
||||
#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40247800 */
|
||||
#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40247C00 */
|
||||
|
||||
/*******************************************************************************
|
||||
* FLASHC
|
||||
*******************************************************************************/
|
||||
|
||||
#define FLASHC_BASE 0x40250000UL
|
||||
#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40250000 */
|
||||
#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4025F000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* SRSS
|
||||
*******************************************************************************/
|
||||
|
||||
#define SRSS_BASE 0x40260000UL
|
||||
#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */
|
||||
#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */
|
||||
#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */
|
||||
|
||||
/*******************************************************************************
|
||||
* BACKUP
|
||||
*******************************************************************************/
|
||||
|
||||
#define BACKUP_BASE 0x40270000UL
|
||||
#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* DW
|
||||
*******************************************************************************/
|
||||
|
||||
#define DW0_BASE 0x40280000UL
|
||||
#define DW1_BASE 0x40281000UL
|
||||
#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */
|
||||
#define DW1 ((DW_Type*) DW1_BASE) /* 0x40281000 */
|
||||
#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40280800 */
|
||||
#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40280820 */
|
||||
#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40280840 */
|
||||
#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x40280860 */
|
||||
#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40280880 */
|
||||
#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x402808A0 */
|
||||
#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x402808C0 */
|
||||
#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402808E0 */
|
||||
#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40280900 */
|
||||
#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40280920 */
|
||||
#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40280940 */
|
||||
#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x40280960 */
|
||||
#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40280980 */
|
||||
#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x402809A0 */
|
||||
#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x402809C0 */
|
||||
#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402809E0 */
|
||||
#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40281800 */
|
||||
#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40281820 */
|
||||
#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40281840 */
|
||||
#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x40281860 */
|
||||
#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40281880 */
|
||||
#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x402818A0 */
|
||||
#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x402818C0 */
|
||||
#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402818E0 */
|
||||
#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40281900 */
|
||||
#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40281920 */
|
||||
#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40281940 */
|
||||
#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x40281960 */
|
||||
#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40281980 */
|
||||
#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x402819A0 */
|
||||
#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x402819C0 */
|
||||
#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402819E0 */
|
||||
|
||||
/*******************************************************************************
|
||||
* EFUSE
|
||||
*******************************************************************************/
|
||||
|
||||
#define EFUSE_BASE 0x402C0000UL
|
||||
#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* PROFILE
|
||||
*******************************************************************************/
|
||||
|
||||
#define PROFILE_BASE 0x402D0000UL
|
||||
#define PROFILE ((PROFILE_Type*) PROFILE_BASE) /* 0x402D0000 */
|
||||
#define PROFILE_CNT_STRUCT0 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[0]) /* 0x402D0800 */
|
||||
#define PROFILE_CNT_STRUCT1 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[1]) /* 0x402D0810 */
|
||||
#define PROFILE_CNT_STRUCT2 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[2]) /* 0x402D0820 */
|
||||
#define PROFILE_CNT_STRUCT3 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[3]) /* 0x402D0830 */
|
||||
#define PROFILE_CNT_STRUCT4 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[4]) /* 0x402D0840 */
|
||||
#define PROFILE_CNT_STRUCT5 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[5]) /* 0x402D0850 */
|
||||
#define PROFILE_CNT_STRUCT6 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[6]) /* 0x402D0860 */
|
||||
#define PROFILE_CNT_STRUCT7 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[7]) /* 0x402D0870 */
|
||||
|
||||
/*******************************************************************************
|
||||
* HSIOM
|
||||
*******************************************************************************/
|
||||
|
||||
#define HSIOM_BASE 0x40310000UL
|
||||
#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40310000 */
|
||||
#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40310000 */
|
||||
#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40310010 */
|
||||
#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40310020 */
|
||||
#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40310030 */
|
||||
#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40310040 */
|
||||
#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40310050 */
|
||||
#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40310060 */
|
||||
#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40310070 */
|
||||
#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40310080 */
|
||||
#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40310090 */
|
||||
#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403100A0 */
|
||||
#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403100B0 */
|
||||
#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403100C0 */
|
||||
#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403100D0 */
|
||||
#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403100E0 */
|
||||
|
||||
/*******************************************************************************
|
||||
* GPIO
|
||||
*******************************************************************************/
|
||||
|
||||
#define GPIO_BASE 0x40320000UL
|
||||
#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40320000 */
|
||||
#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40320000 */
|
||||
#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40320080 */
|
||||
#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40320100 */
|
||||
#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40320180 */
|
||||
#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40320200 */
|
||||
#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40320280 */
|
||||
#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40320300 */
|
||||
#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40320380 */
|
||||
#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40320400 */
|
||||
#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40320480 */
|
||||
#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40320500 */
|
||||
#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40320580 */
|
||||
#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40320600 */
|
||||
#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40320680 */
|
||||
#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40320700 */
|
||||
|
||||
/*******************************************************************************
|
||||
* SMARTIO
|
||||
*******************************************************************************/
|
||||
|
||||
#define SMARTIO_BASE 0x40330000UL
|
||||
#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40330000 */
|
||||
#define SMARTIO_PRT8 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[8]) /* 0x40330800 */
|
||||
#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40330900 */
|
||||
|
||||
/*******************************************************************************
|
||||
* LPCOMP
|
||||
*******************************************************************************/
|
||||
|
||||
#define LPCOMP_BASE 0x40350000UL
|
||||
#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* CSD
|
||||
*******************************************************************************/
|
||||
|
||||
#define CSD0_BASE 0x40360000UL
|
||||
#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* TCPWM
|
||||
*******************************************************************************/
|
||||
|
||||
#define TCPWM0_BASE 0x40380000UL
|
||||
#define TCPWM1_BASE 0x40390000UL
|
||||
#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */
|
||||
#define TCPWM1 ((TCPWM_Type*) TCPWM1_BASE) /* 0x40390000 */
|
||||
#define TCPWM0_CNT0 ((TCPWM_CNT_Type*) &TCPWM0->CNT[0]) /* 0x40380100 */
|
||||
#define TCPWM0_CNT1 ((TCPWM_CNT_Type*) &TCPWM0->CNT[1]) /* 0x40380140 */
|
||||
#define TCPWM0_CNT2 ((TCPWM_CNT_Type*) &TCPWM0->CNT[2]) /* 0x40380180 */
|
||||
#define TCPWM0_CNT3 ((TCPWM_CNT_Type*) &TCPWM0->CNT[3]) /* 0x403801C0 */
|
||||
#define TCPWM0_CNT4 ((TCPWM_CNT_Type*) &TCPWM0->CNT[4]) /* 0x40380200 */
|
||||
#define TCPWM0_CNT5 ((TCPWM_CNT_Type*) &TCPWM0->CNT[5]) /* 0x40380240 */
|
||||
#define TCPWM0_CNT6 ((TCPWM_CNT_Type*) &TCPWM0->CNT[6]) /* 0x40380280 */
|
||||
#define TCPWM0_CNT7 ((TCPWM_CNT_Type*) &TCPWM0->CNT[7]) /* 0x403802C0 */
|
||||
#define TCPWM1_CNT0 ((TCPWM_CNT_Type*) &TCPWM1->CNT[0]) /* 0x40390100 */
|
||||
#define TCPWM1_CNT1 ((TCPWM_CNT_Type*) &TCPWM1->CNT[1]) /* 0x40390140 */
|
||||
#define TCPWM1_CNT2 ((TCPWM_CNT_Type*) &TCPWM1->CNT[2]) /* 0x40390180 */
|
||||
#define TCPWM1_CNT3 ((TCPWM_CNT_Type*) &TCPWM1->CNT[3]) /* 0x403901C0 */
|
||||
#define TCPWM1_CNT4 ((TCPWM_CNT_Type*) &TCPWM1->CNT[4]) /* 0x40390200 */
|
||||
#define TCPWM1_CNT5 ((TCPWM_CNT_Type*) &TCPWM1->CNT[5]) /* 0x40390240 */
|
||||
#define TCPWM1_CNT6 ((TCPWM_CNT_Type*) &TCPWM1->CNT[6]) /* 0x40390280 */
|
||||
#define TCPWM1_CNT7 ((TCPWM_CNT_Type*) &TCPWM1->CNT[7]) /* 0x403902C0 */
|
||||
#define TCPWM1_CNT8 ((TCPWM_CNT_Type*) &TCPWM1->CNT[8]) /* 0x40390300 */
|
||||
#define TCPWM1_CNT9 ((TCPWM_CNT_Type*) &TCPWM1->CNT[9]) /* 0x40390340 */
|
||||
#define TCPWM1_CNT10 ((TCPWM_CNT_Type*) &TCPWM1->CNT[10]) /* 0x40390380 */
|
||||
#define TCPWM1_CNT11 ((TCPWM_CNT_Type*) &TCPWM1->CNT[11]) /* 0x403903C0 */
|
||||
#define TCPWM1_CNT12 ((TCPWM_CNT_Type*) &TCPWM1->CNT[12]) /* 0x40390400 */
|
||||
#define TCPWM1_CNT13 ((TCPWM_CNT_Type*) &TCPWM1->CNT[13]) /* 0x40390440 */
|
||||
#define TCPWM1_CNT14 ((TCPWM_CNT_Type*) &TCPWM1->CNT[14]) /* 0x40390480 */
|
||||
#define TCPWM1_CNT15 ((TCPWM_CNT_Type*) &TCPWM1->CNT[15]) /* 0x403904C0 */
|
||||
#define TCPWM1_CNT16 ((TCPWM_CNT_Type*) &TCPWM1->CNT[16]) /* 0x40390500 */
|
||||
#define TCPWM1_CNT17 ((TCPWM_CNT_Type*) &TCPWM1->CNT[17]) /* 0x40390540 */
|
||||
#define TCPWM1_CNT18 ((TCPWM_CNT_Type*) &TCPWM1->CNT[18]) /* 0x40390580 */
|
||||
#define TCPWM1_CNT19 ((TCPWM_CNT_Type*) &TCPWM1->CNT[19]) /* 0x403905C0 */
|
||||
#define TCPWM1_CNT20 ((TCPWM_CNT_Type*) &TCPWM1->CNT[20]) /* 0x40390600 */
|
||||
#define TCPWM1_CNT21 ((TCPWM_CNT_Type*) &TCPWM1->CNT[21]) /* 0x40390640 */
|
||||
#define TCPWM1_CNT22 ((TCPWM_CNT_Type*) &TCPWM1->CNT[22]) /* 0x40390680 */
|
||||
#define TCPWM1_CNT23 ((TCPWM_CNT_Type*) &TCPWM1->CNT[23]) /* 0x403906C0 */
|
||||
|
||||
/*******************************************************************************
|
||||
* LCD
|
||||
*******************************************************************************/
|
||||
|
||||
#define LCD0_BASE 0x403B0000UL
|
||||
#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* BLE
|
||||
*******************************************************************************/
|
||||
|
||||
#define BLE_BASE 0x403C0000UL
|
||||
#define BLE ((BLE_Type*) BLE_BASE) /* 0x403C0000 */
|
||||
#define BLE_RCB_RCBLL ((BLE_RCB_RCBLL_Type*) &BLE->RCB.RCBLL) /* 0x403C0100 */
|
||||
#define BLE_RCB ((BLE_RCB_Type*) &BLE->RCB) /* 0x403C0000 */
|
||||
#define BLE_BLELL ((BLE_BLELL_Type*) &BLE->BLELL) /* 0x403C1000 */
|
||||
#define BLE_BLESS ((BLE_BLESS_Type*) &BLE->BLESS) /* 0x403DF000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* SMIF
|
||||
*******************************************************************************/
|
||||
|
||||
#define SMIF0_BASE 0x40420000UL
|
||||
#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */
|
||||
#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */
|
||||
#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */
|
||||
#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */
|
||||
#define SMIF0_DEVICE3 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[3]) /* 0x40420980 */
|
||||
|
||||
/*******************************************************************************
|
||||
* SCB
|
||||
*******************************************************************************/
|
||||
|
||||
#define SCB0_BASE 0x40610000UL
|
||||
#define SCB1_BASE 0x40620000UL
|
||||
#define SCB2_BASE 0x40630000UL
|
||||
#define SCB3_BASE 0x40640000UL
|
||||
#define SCB4_BASE 0x40650000UL
|
||||
#define SCB5_BASE 0x40660000UL
|
||||
#define SCB6_BASE 0x40670000UL
|
||||
#define SCB7_BASE 0x40680000UL
|
||||
#define SCB8_BASE 0x40690000UL
|
||||
#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40610000 */
|
||||
#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40620000 */
|
||||
#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40630000 */
|
||||
#define SCB3 ((CySCB_Type*) SCB3_BASE) /* 0x40640000 */
|
||||
#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40650000 */
|
||||
#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40660000 */
|
||||
#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40670000 */
|
||||
#define SCB7 ((CySCB_Type*) SCB7_BASE) /* 0x40680000 */
|
||||
#define SCB8 ((CySCB_Type*) SCB8_BASE) /* 0x40690000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* CTDAC
|
||||
*******************************************************************************/
|
||||
|
||||
#define CTDAC0_BASE 0x41140000UL
|
||||
#define CTDAC0 ((CTDAC_Type*) CTDAC0_BASE) /* 0x41140000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* SAR
|
||||
*******************************************************************************/
|
||||
|
||||
#define SAR_BASE 0x411D0000UL
|
||||
#define SAR ((SAR_Type*) SAR_BASE) /* 0x411D0000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* PASS
|
||||
*******************************************************************************/
|
||||
|
||||
#define PASS_BASE 0x411F0000UL
|
||||
#define PASS ((PASS_Type*) PASS_BASE) /* 0x411F0000 */
|
||||
#define PASS_AREF ((PASS_AREF_Type*) &PASS->AREF) /* 0x411F0E00 */
|
||||
|
||||
/*******************************************************************************
|
||||
* I2S
|
||||
*******************************************************************************/
|
||||
|
||||
#define I2S0_BASE 0x42A10000UL
|
||||
#define I2S0 ((I2S_Type*) I2S0_BASE) /* 0x42A10000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* PDM
|
||||
*******************************************************************************/
|
||||
|
||||
#define PDM0_BASE 0x42A20000UL
|
||||
#define PDM0 ((PDM_Type*) PDM0_BASE) /* 0x42A20000 */
|
||||
|
||||
|
||||
/* Backward compabitility definitions */
|
||||
#define I2S I2S0
|
||||
#define PDM PDM0
|
||||
|
||||
/** \} CY8C6336BZI-BLF03 */
|
||||
|
||||
#endif /* _CY8C6336BZI_BLF03_H_ */
|
||||
|
||||
|
||||
/* [] END OF FILE */
|
||||
File diff suppressed because it is too large
Load diff
|
|
@ -1,934 +0,0 @@
|
|||
/***************************************************************************//**
|
||||
* \file cy8c6337bzi_blf13.h
|
||||
*
|
||||
* \brief
|
||||
* CY8C6337BZI-BLF13 device header
|
||||
*
|
||||
* \note
|
||||
* Generator version: 1.3.0.1146
|
||||
* Database revision: rev#1050929
|
||||
*
|
||||
********************************************************************************
|
||||
* \copyright
|
||||
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
|
||||
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _CY8C6337BZI_BLF13_H_
|
||||
#define _CY8C6337BZI_BLF13_H_
|
||||
|
||||
/**
|
||||
* \addtogroup group_device CY8C6337BZI-BLF13
|
||||
* \{
|
||||
*/
|
||||
|
||||
/**
|
||||
* \addtogroup Configuration_of_CMSIS
|
||||
* \{
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
* Interrupt Number Definition
|
||||
*******************************************************************************/
|
||||
|
||||
typedef enum {
|
||||
/* ARM Cortex-M4 Core Interrupt Numbers */
|
||||
Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */
|
||||
NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */
|
||||
HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */
|
||||
MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */
|
||||
BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */
|
||||
UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
|
||||
SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */
|
||||
DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */
|
||||
PendSV_IRQn = -2, /*!< -2 Pendable request for system service */
|
||||
SysTick_IRQn = -1, /*!< -1 System Tick Timer */
|
||||
/* CY8C6337BZI-BLF13 Peripheral Interrupt Numbers */
|
||||
ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */
|
||||
ioss_interrupts_gpio_1_IRQn = 1, /*!< 1 [DeepSleep] GPIO Port Interrupt #1 */
|
||||
ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */
|
||||
ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */
|
||||
ioss_interrupts_gpio_4_IRQn = 4, /*!< 4 [DeepSleep] GPIO Port Interrupt #4 */
|
||||
ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */
|
||||
ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */
|
||||
ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */
|
||||
ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */
|
||||
ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */
|
||||
ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */
|
||||
ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */
|
||||
ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */
|
||||
ioss_interrupts_gpio_13_IRQn = 13, /*!< 13 [DeepSleep] GPIO Port Interrupt #13 */
|
||||
ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */
|
||||
ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */
|
||||
ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */
|
||||
lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */
|
||||
scb_8_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #8 (DeepSleep capable) */
|
||||
srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */
|
||||
srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */
|
||||
srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */
|
||||
srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */
|
||||
pass_interrupt_ctbs_IRQn = 23, /*!< 23 [DeepSleep] CTBm Interrupt (all CTBms) */
|
||||
bless_interrupt_IRQn = 24, /*!< 24 [DeepSleep] Bluetooth Radio interrupt */
|
||||
cpuss_interrupts_ipc_0_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */
|
||||
cpuss_interrupts_ipc_1_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */
|
||||
cpuss_interrupts_ipc_2_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */
|
||||
cpuss_interrupts_ipc_3_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */
|
||||
cpuss_interrupts_ipc_4_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */
|
||||
cpuss_interrupts_ipc_5_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */
|
||||
cpuss_interrupts_ipc_6_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */
|
||||
cpuss_interrupts_ipc_7_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */
|
||||
cpuss_interrupts_ipc_8_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */
|
||||
cpuss_interrupts_ipc_9_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */
|
||||
cpuss_interrupts_ipc_10_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */
|
||||
cpuss_interrupts_ipc_11_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */
|
||||
cpuss_interrupts_ipc_12_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */
|
||||
cpuss_interrupts_ipc_13_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */
|
||||
cpuss_interrupts_ipc_14_IRQn = 39, /*!< 39 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */
|
||||
cpuss_interrupts_ipc_15_IRQn = 40, /*!< 40 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */
|
||||
scb_0_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #0 */
|
||||
scb_1_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #1 */
|
||||
scb_2_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #2 */
|
||||
scb_3_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #3 */
|
||||
scb_4_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #4 */
|
||||
scb_5_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #5 */
|
||||
scb_6_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #6 */
|
||||
scb_7_interrupt_IRQn = 48, /*!< 48 [Active] Serial Communication Block #7 */
|
||||
csd_interrupt_IRQn = 49, /*!< 49 [Active] CSD (Capsense) interrupt */
|
||||
cpuss_interrupts_dw0_0_IRQn = 50, /*!< 50 [Active] CPUSS DataWire #0, Channel #0 */
|
||||
cpuss_interrupts_dw0_1_IRQn = 51, /*!< 51 [Active] CPUSS DataWire #0, Channel #1 */
|
||||
cpuss_interrupts_dw0_2_IRQn = 52, /*!< 52 [Active] CPUSS DataWire #0, Channel #2 */
|
||||
cpuss_interrupts_dw0_3_IRQn = 53, /*!< 53 [Active] CPUSS DataWire #0, Channel #3 */
|
||||
cpuss_interrupts_dw0_4_IRQn = 54, /*!< 54 [Active] CPUSS DataWire #0, Channel #4 */
|
||||
cpuss_interrupts_dw0_5_IRQn = 55, /*!< 55 [Active] CPUSS DataWire #0, Channel #5 */
|
||||
cpuss_interrupts_dw0_6_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #6 */
|
||||
cpuss_interrupts_dw0_7_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #7 */
|
||||
cpuss_interrupts_dw0_8_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #8 */
|
||||
cpuss_interrupts_dw0_9_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #9 */
|
||||
cpuss_interrupts_dw0_10_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #10 */
|
||||
cpuss_interrupts_dw0_11_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #11 */
|
||||
cpuss_interrupts_dw0_12_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #12 */
|
||||
cpuss_interrupts_dw0_13_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #13 */
|
||||
cpuss_interrupts_dw0_14_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #14 */
|
||||
cpuss_interrupts_dw0_15_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #15 */
|
||||
cpuss_interrupts_dw1_0_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #1, Channel #0 */
|
||||
cpuss_interrupts_dw1_1_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #1, Channel #1 */
|
||||
cpuss_interrupts_dw1_2_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #1, Channel #2 */
|
||||
cpuss_interrupts_dw1_3_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #1, Channel #3 */
|
||||
cpuss_interrupts_dw1_4_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #1, Channel #4 */
|
||||
cpuss_interrupts_dw1_5_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #1, Channel #5 */
|
||||
cpuss_interrupts_dw1_6_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #1, Channel #6 */
|
||||
cpuss_interrupts_dw1_7_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #1, Channel #7 */
|
||||
cpuss_interrupts_dw1_8_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #1, Channel #8 */
|
||||
cpuss_interrupts_dw1_9_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #1, Channel #9 */
|
||||
cpuss_interrupts_dw1_10_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #1, Channel #10 */
|
||||
cpuss_interrupts_dw1_11_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #1, Channel #11 */
|
||||
cpuss_interrupts_dw1_12_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #1, Channel #12 */
|
||||
cpuss_interrupts_dw1_13_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #1, Channel #13 */
|
||||
cpuss_interrupts_dw1_14_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #1, Channel #14 */
|
||||
cpuss_interrupts_dw1_15_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #1, Channel #15 */
|
||||
cpuss_interrupts_fault_0_IRQn = 82, /*!< 82 [Active] CPUSS Fault Structure Interrupt #0 */
|
||||
cpuss_interrupts_fault_1_IRQn = 83, /*!< 83 [Active] CPUSS Fault Structure Interrupt #1 */
|
||||
cpuss_interrupt_crypto_IRQn = 84, /*!< 84 [Active] CRYPTO Accelerator Interrupt */
|
||||
cpuss_interrupt_fm_IRQn = 85, /*!< 85 [Active] FLASH Macro Interrupt */
|
||||
cpuss_interrupts_cm0_cti_0_IRQn = 86, /*!< 86 [Active] CM0+ CTI #0 */
|
||||
cpuss_interrupts_cm0_cti_1_IRQn = 87, /*!< 87 [Active] CM0+ CTI #1 */
|
||||
cpuss_interrupts_cm4_cti_0_IRQn = 88, /*!< 88 [Active] CM4 CTI #0 */
|
||||
cpuss_interrupts_cm4_cti_1_IRQn = 89, /*!< 89 [Active] CM4 CTI #1 */
|
||||
tcpwm_0_interrupts_0_IRQn = 90, /*!< 90 [Active] TCPWM #0, Counter #0 */
|
||||
tcpwm_0_interrupts_1_IRQn = 91, /*!< 91 [Active] TCPWM #0, Counter #1 */
|
||||
tcpwm_0_interrupts_2_IRQn = 92, /*!< 92 [Active] TCPWM #0, Counter #2 */
|
||||
tcpwm_0_interrupts_3_IRQn = 93, /*!< 93 [Active] TCPWM #0, Counter #3 */
|
||||
tcpwm_0_interrupts_4_IRQn = 94, /*!< 94 [Active] TCPWM #0, Counter #4 */
|
||||
tcpwm_0_interrupts_5_IRQn = 95, /*!< 95 [Active] TCPWM #0, Counter #5 */
|
||||
tcpwm_0_interrupts_6_IRQn = 96, /*!< 96 [Active] TCPWM #0, Counter #6 */
|
||||
tcpwm_0_interrupts_7_IRQn = 97, /*!< 97 [Active] TCPWM #0, Counter #7 */
|
||||
tcpwm_1_interrupts_0_IRQn = 98, /*!< 98 [Active] TCPWM #1, Counter #0 */
|
||||
tcpwm_1_interrupts_1_IRQn = 99, /*!< 99 [Active] TCPWM #1, Counter #1 */
|
||||
tcpwm_1_interrupts_2_IRQn = 100, /*!< 100 [Active] TCPWM #1, Counter #2 */
|
||||
tcpwm_1_interrupts_3_IRQn = 101, /*!< 101 [Active] TCPWM #1, Counter #3 */
|
||||
tcpwm_1_interrupts_4_IRQn = 102, /*!< 102 [Active] TCPWM #1, Counter #4 */
|
||||
tcpwm_1_interrupts_5_IRQn = 103, /*!< 103 [Active] TCPWM #1, Counter #5 */
|
||||
tcpwm_1_interrupts_6_IRQn = 104, /*!< 104 [Active] TCPWM #1, Counter #6 */
|
||||
tcpwm_1_interrupts_7_IRQn = 105, /*!< 105 [Active] TCPWM #1, Counter #7 */
|
||||
tcpwm_1_interrupts_8_IRQn = 106, /*!< 106 [Active] TCPWM #1, Counter #8 */
|
||||
tcpwm_1_interrupts_9_IRQn = 107, /*!< 107 [Active] TCPWM #1, Counter #9 */
|
||||
tcpwm_1_interrupts_10_IRQn = 108, /*!< 108 [Active] TCPWM #1, Counter #10 */
|
||||
tcpwm_1_interrupts_11_IRQn = 109, /*!< 109 [Active] TCPWM #1, Counter #11 */
|
||||
tcpwm_1_interrupts_12_IRQn = 110, /*!< 110 [Active] TCPWM #1, Counter #12 */
|
||||
tcpwm_1_interrupts_13_IRQn = 111, /*!< 111 [Active] TCPWM #1, Counter #13 */
|
||||
tcpwm_1_interrupts_14_IRQn = 112, /*!< 112 [Active] TCPWM #1, Counter #14 */
|
||||
tcpwm_1_interrupts_15_IRQn = 113, /*!< 113 [Active] TCPWM #1, Counter #15 */
|
||||
tcpwm_1_interrupts_16_IRQn = 114, /*!< 114 [Active] TCPWM #1, Counter #16 */
|
||||
tcpwm_1_interrupts_17_IRQn = 115, /*!< 115 [Active] TCPWM #1, Counter #17 */
|
||||
tcpwm_1_interrupts_18_IRQn = 116, /*!< 116 [Active] TCPWM #1, Counter #18 */
|
||||
tcpwm_1_interrupts_19_IRQn = 117, /*!< 117 [Active] TCPWM #1, Counter #19 */
|
||||
tcpwm_1_interrupts_20_IRQn = 118, /*!< 118 [Active] TCPWM #1, Counter #20 */
|
||||
tcpwm_1_interrupts_21_IRQn = 119, /*!< 119 [Active] TCPWM #1, Counter #21 */
|
||||
tcpwm_1_interrupts_22_IRQn = 120, /*!< 120 [Active] TCPWM #1, Counter #22 */
|
||||
tcpwm_1_interrupts_23_IRQn = 121, /*!< 121 [Active] TCPWM #1, Counter #23 */
|
||||
udb_interrupts_0_IRQn = 122, /*!< 122 [Active] UDB Interrupt #0 */
|
||||
udb_interrupts_1_IRQn = 123, /*!< 123 [Active] UDB Interrupt #1 */
|
||||
udb_interrupts_2_IRQn = 124, /*!< 124 [Active] UDB Interrupt #2 */
|
||||
udb_interrupts_3_IRQn = 125, /*!< 125 [Active] UDB Interrupt #3 */
|
||||
udb_interrupts_4_IRQn = 126, /*!< 126 [Active] UDB Interrupt #4 */
|
||||
udb_interrupts_5_IRQn = 127, /*!< 127 [Active] UDB Interrupt #5 */
|
||||
udb_interrupts_6_IRQn = 128, /*!< 128 [Active] UDB Interrupt #6 */
|
||||
udb_interrupts_7_IRQn = 129, /*!< 129 [Active] UDB Interrupt #7 */
|
||||
udb_interrupts_8_IRQn = 130, /*!< 130 [Active] UDB Interrupt #8 */
|
||||
udb_interrupts_9_IRQn = 131, /*!< 131 [Active] UDB Interrupt #9 */
|
||||
udb_interrupts_10_IRQn = 132, /*!< 132 [Active] UDB Interrupt #10 */
|
||||
udb_interrupts_11_IRQn = 133, /*!< 133 [Active] UDB Interrupt #11 */
|
||||
udb_interrupts_12_IRQn = 134, /*!< 134 [Active] UDB Interrupt #12 */
|
||||
udb_interrupts_13_IRQn = 135, /*!< 135 [Active] UDB Interrupt #13 */
|
||||
udb_interrupts_14_IRQn = 136, /*!< 136 [Active] UDB Interrupt #14 */
|
||||
udb_interrupts_15_IRQn = 137, /*!< 137 [Active] UDB Interrupt #15 */
|
||||
pass_interrupt_sar_IRQn = 138, /*!< 138 [Active] SAR ADC interrupt */
|
||||
audioss_interrupt_i2s_IRQn = 139, /*!< 139 [Active] I2S Audio interrupt */
|
||||
audioss_interrupt_pdm_IRQn = 140, /*!< 140 [Active] PDM/PCM Audio interrupt */
|
||||
profile_interrupt_IRQn = 141, /*!< 141 [Active] Energy Profiler interrupt */
|
||||
smif_interrupt_IRQn = 142, /*!< 142 [Active] Serial Memory Interface interrupt */
|
||||
usb_interrupt_hi_IRQn = 143, /*!< 143 [Active] USB Interrupt */
|
||||
usb_interrupt_med_IRQn = 144, /*!< 144 [Active] USB Interrupt */
|
||||
usb_interrupt_lo_IRQn = 145, /*!< 145 [Active] USB Interrupt */
|
||||
pass_interrupt_dacs_IRQn = 146, /*!< 146 [Active] Consolidated interrrupt for all DACs */
|
||||
unconnected_IRQn = 240 /*!< 240 Unconnected */
|
||||
} IRQn_Type;
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Processor and Core Peripheral Section
|
||||
*******************************************************************************/
|
||||
|
||||
/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */
|
||||
#define __CM4_REV 0x0001U /*!< CM4 Core Revision */
|
||||
#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
|
||||
#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */
|
||||
#define __MPU_PRESENT 1 /*!< MPU present or not */
|
||||
#define __FPU_PRESENT 1 /*!< FPU present or not */
|
||||
#define __CM0P_PRESENT 0 /*!< CM0P present or not */
|
||||
|
||||
/** \} Configuration_of_CMSIS */
|
||||
|
||||
/* Memory Blocks */
|
||||
#define CY_ROM_BASE 0x00000000UL
|
||||
#define CY_ROM_SIZE 0x00020000UL
|
||||
#define CY_SRAM0_BASE 0x08000000UL
|
||||
#define CY_SRAM0_SIZE 0x00048000UL
|
||||
#define CY_FLASH_BASE 0x10000000UL
|
||||
#define CY_FLASH_SIZE 0x00100000UL
|
||||
#define CY_EM_EEPROM_BASE 0x14000000UL
|
||||
#define CY_EM_EEPROM_SIZE 0x00008000UL
|
||||
#define CY_XIP_BASE 0x18000000UL
|
||||
#define CY_XIP_SIZE 0x08000000UL
|
||||
#define CY_SFLASH_BASE 0x16000000UL
|
||||
#define CY_SFLASH_SIZE 0x00008000UL
|
||||
#define CY_EFUSE_BASE 0x402C0800UL
|
||||
#define CY_EFUSE_SIZE 0x00000200UL
|
||||
|
||||
#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */
|
||||
#include "system_psoc6.h" /*!< PSoC 6 System */
|
||||
|
||||
/* IP List */
|
||||
#define CY_IP_MXTCPWM 1u
|
||||
#define CY_IP_MXTCPWM_INSTANCES 2u
|
||||
#define CY_IP_MXTCPWM_VERSION 1u
|
||||
#define CY_IP_MXCSDV2 1u
|
||||
#define CY_IP_MXCSDV2_INSTANCES 1u
|
||||
#define CY_IP_MXCSDV2_VERSION 1u
|
||||
#define CY_IP_MXLCD 1u
|
||||
#define CY_IP_MXLCD_INSTANCES 1u
|
||||
#define CY_IP_MXLCD_VERSION 1u
|
||||
#define CY_IP_MXS40SRSS 1u
|
||||
#define CY_IP_MXS40SRSS_INSTANCES 1u
|
||||
#define CY_IP_MXS40SRSS_VERSION 1u
|
||||
#define CY_IP_MXS40SRSS_RTC 1u
|
||||
#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u
|
||||
#define CY_IP_MXS40SRSS_RTC_VERSION 1u
|
||||
#define CY_IP_MXS40SRSS_MCWDT 1u
|
||||
#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u
|
||||
#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u
|
||||
#define CY_IP_MXSCB 1u
|
||||
#define CY_IP_MXSCB_INSTANCES 9u
|
||||
#define CY_IP_MXSCB_VERSION 1u
|
||||
#define CY_IP_MXPERI 1u
|
||||
#define CY_IP_MXPERI_INSTANCES 1u
|
||||
#define CY_IP_MXPERI_VERSION 1u
|
||||
#define CY_IP_MXPERI_TR 1u
|
||||
#define CY_IP_MXPERI_TR_INSTANCES 1u
|
||||
#define CY_IP_MXPERI_TR_VERSION 1u
|
||||
#define CY_IP_M4CPUSS 1u
|
||||
#define CY_IP_M4CPUSS_INSTANCES 1u
|
||||
#define CY_IP_M4CPUSS_VERSION 1u
|
||||
#define CY_IP_M4CPUSS_DMA 1u
|
||||
#define CY_IP_M4CPUSS_DMA_INSTANCES 2u
|
||||
#define CY_IP_M4CPUSS_DMA_VERSION 1u
|
||||
#define CY_IP_MXBLESS 1u
|
||||
#define CY_IP_MXBLESS_INSTANCES 1u
|
||||
#define CY_IP_MXBLESS_VERSION 1u
|
||||
#define CY_IP_MXAUDIOSS 1u
|
||||
#define CY_IP_MXAUDIOSS_INSTANCES 1u
|
||||
#define CY_IP_MXAUDIOSS_VERSION 1u
|
||||
#define CY_IP_MXLPCOMP 1u
|
||||
#define CY_IP_MXLPCOMP_INSTANCES 1u
|
||||
#define CY_IP_MXLPCOMP_VERSION 1u
|
||||
#define CY_IP_MXS40PASS 1u
|
||||
#define CY_IP_MXS40PASS_INSTANCES 1u
|
||||
#define CY_IP_MXS40PASS_VERSION 1u
|
||||
#define CY_IP_MXS40PASS_SAR 1u
|
||||
#define CY_IP_MXS40PASS_SAR_INSTANCES 16u
|
||||
#define CY_IP_MXS40PASS_SAR_VERSION 1u
|
||||
#define CY_IP_MXS40PASS_CTDAC 1u
|
||||
#define CY_IP_MXS40PASS_CTDAC_INSTANCES 1u
|
||||
#define CY_IP_MXS40PASS_CTDAC_VERSION 1u
|
||||
#define CY_IP_MXSMIF 1u
|
||||
#define CY_IP_MXSMIF_INSTANCES 1u
|
||||
#define CY_IP_MXSMIF_VERSION 1u
|
||||
#define CY_IP_MXS40IOSS 1u
|
||||
#define CY_IP_MXS40IOSS_INSTANCES 1u
|
||||
#define CY_IP_MXS40IOSS_VERSION 1u
|
||||
#define CY_IP_MXEFUSE 1u
|
||||
#define CY_IP_MXEFUSE_INSTANCES 1u
|
||||
#define CY_IP_MXEFUSE_VERSION 1u
|
||||
#define CY_IP_MXPROFILE 1u
|
||||
#define CY_IP_MXPROFILE_INSTANCES 1u
|
||||
#define CY_IP_MXPROFILE_VERSION 1u
|
||||
|
||||
#include "psoc6able2_config.h"
|
||||
#include "gpio_psoc6able2_116_bga_ble.h"
|
||||
|
||||
#define CY_DEVICE_PSOC6ABLE2
|
||||
#define CY_SILICON_ID 0xE2292100UL
|
||||
#define CY_HF_CLK_MAX_FREQ 150000000UL
|
||||
|
||||
#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL
|
||||
|
||||
/*******************************************************************************
|
||||
* SFLASH
|
||||
*******************************************************************************/
|
||||
|
||||
#define SFLASH_BASE 0x16000000UL
|
||||
#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* PERI
|
||||
*******************************************************************************/
|
||||
|
||||
#define PERI_BASE 0x40010000UL
|
||||
#define PERI_PPU_GR_MMIO0_BASE 0x40015000UL
|
||||
#define PERI_PPU_GR_MMIO1_BASE 0x40015040UL
|
||||
#define PERI_PPU_GR_MMIO2_BASE 0x40015080UL
|
||||
#define PERI_PPU_GR_MMIO3_BASE 0x400150C0UL
|
||||
#define PERI_PPU_GR_MMIO4_BASE 0x40015100UL
|
||||
#define PERI_PPU_GR_MMIO6_BASE 0x40015180UL
|
||||
#define PERI_PPU_GR_MMIO9_BASE 0x40015240UL
|
||||
#define PERI_PPU_GR_MMIO10_BASE 0x40015280UL
|
||||
#define PERI_GR_PPU_SL_PERI_GR1_BASE 0x40100000UL
|
||||
#define PERI_GR_PPU_SL_CRYPTO_BASE 0x40100040UL
|
||||
#define PERI_GR_PPU_SL_PERI_GR2_BASE 0x40200000UL
|
||||
#define PERI_GR_PPU_SL_CPUSS_BASE 0x40200040UL
|
||||
#define PERI_GR_PPU_SL_FAULT_BASE 0x40200080UL
|
||||
#define PERI_GR_PPU_SL_IPC_BASE 0x402000C0UL
|
||||
#define PERI_GR_PPU_SL_PROT_BASE 0x40200100UL
|
||||
#define PERI_GR_PPU_SL_FLASHC_BASE 0x40200140UL
|
||||
#define PERI_GR_PPU_SL_SRSS_BASE 0x40200180UL
|
||||
#define PERI_GR_PPU_SL_BACKUP_BASE 0x402001C0UL
|
||||
#define PERI_GR_PPU_SL_DW0_BASE 0x40200200UL
|
||||
#define PERI_GR_PPU_SL_DW1_BASE 0x40200240UL
|
||||
#define PERI_GR_PPU_SL_EFUSE_BASE 0x40200300UL
|
||||
#define PERI_GR_PPU_SL_PROFILE_BASE 0x40200340UL
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT0_BASE 0x40201000UL
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT1_BASE 0x40201040UL
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT2_BASE 0x40201080UL
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT3_BASE 0x402010C0UL
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT4_BASE 0x40201100UL
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT5_BASE 0x40201140UL
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT6_BASE 0x40201180UL
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT7_BASE 0x402011C0UL
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT0_BASE 0x40201200UL
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT1_BASE 0x40201240UL
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT2_BASE 0x40201280UL
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT3_BASE 0x402012C0UL
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT4_BASE 0x40201300UL
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT5_BASE 0x40201340UL
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT6_BASE 0x40201380UL
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT7_BASE 0x402013C0UL
|
||||
#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT0_BASE 0x40201400UL
|
||||
#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT1_BASE 0x40201440UL
|
||||
#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT2_BASE 0x40201480UL
|
||||
#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT3_BASE 0x402014C0UL
|
||||
#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT0_BASE 0x40201500UL
|
||||
#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT1_BASE 0x40201540UL
|
||||
#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT2_BASE 0x40201580UL
|
||||
#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT3_BASE 0x402015C0UL
|
||||
#define PERI_GR_PPU_RG_SMPU_BASE 0x40201600UL
|
||||
#define PERI_GR_PPU_RG_MPU_CM0P_BASE 0x40201640UL
|
||||
#define PERI_GR_PPU_RG_MPU_CRYPTO_BASE 0x40201680UL
|
||||
#define PERI_GR_PPU_RG_MPU_CM4_BASE 0x402016C0UL
|
||||
#define PERI_GR_PPU_RG_MPU_TC_BASE 0x40201700UL
|
||||
#define PERI_GR_PPU_SL_PERI_GR3_BASE 0x40300000UL
|
||||
#define PERI_GR_PPU_SL_HSIOM_BASE 0x40300040UL
|
||||
#define PERI_GR_PPU_SL_GPIO_BASE 0x40300080UL
|
||||
#define PERI_GR_PPU_SL_SMARTIO_BASE 0x403000C0UL
|
||||
#define PERI_GR_PPU_SL_UDB_BASE 0x40300100UL
|
||||
#define PERI_GR_PPU_SL_LPCOMP_BASE 0x40300140UL
|
||||
#define PERI_GR_PPU_SL_CSD_BASE 0x40300180UL
|
||||
#define PERI_GR_PPU_SL_TCPWM0_BASE 0x40300200UL
|
||||
#define PERI_GR_PPU_SL_TCPWM1_BASE 0x40300240UL
|
||||
#define PERI_GR_PPU_SL_LCD_BASE 0x40300280UL
|
||||
#define PERI_GR_PPU_SL_BLE_BASE 0x403002C0UL
|
||||
#define PERI_GR_PPU_SL_USBFS_BASE 0x40300300UL
|
||||
#define PERI_GR_PPU_SL_PERI_GR4_BASE 0x40400000UL
|
||||
#define PERI_GR_PPU_SL_SMIF_BASE 0x40400080UL
|
||||
#define PERI_GR_PPU_SL_PERI_GR6_BASE 0x40600000UL
|
||||
#define PERI_GR_PPU_SL_SCB0_BASE 0x40600040UL
|
||||
#define PERI_GR_PPU_SL_SCB1_BASE 0x40600080UL
|
||||
#define PERI_GR_PPU_SL_SCB2_BASE 0x406000C0UL
|
||||
#define PERI_GR_PPU_SL_SCB3_BASE 0x40600100UL
|
||||
#define PERI_GR_PPU_SL_SCB4_BASE 0x40600140UL
|
||||
#define PERI_GR_PPU_SL_SCB5_BASE 0x40600180UL
|
||||
#define PERI_GR_PPU_SL_SCB6_BASE 0x406001C0UL
|
||||
#define PERI_GR_PPU_SL_SCB7_BASE 0x40600200UL
|
||||
#define PERI_GR_PPU_SL_SCB8_BASE 0x40600240UL
|
||||
#define PERI_GR_PPU_SL_PERI_GR9_BASE 0x41000000UL
|
||||
#define PERI_GR_PPU_SL_PASS_BASE 0x41000040UL
|
||||
#define PERI_GR_PPU_SL_PERI_GR10_BASE 0x42A00000UL
|
||||
#define PERI_GR_PPU_SL_I2S_BASE 0x42A00040UL
|
||||
#define PERI_GR_PPU_SL_PDM_BASE 0x42A00080UL
|
||||
#define PERI ((PERI_Type*) PERI_BASE) /* 0x40010000 */
|
||||
#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40010000 */
|
||||
#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40010040 */
|
||||
#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40010080 */
|
||||
#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x400100C0 */
|
||||
#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40010100 */
|
||||
#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x40010180 */
|
||||
#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40010240 */
|
||||
#define PERI_GR10 ((PERI_GR_Type*) &PERI->GR[10]) /* 0x40010280 */
|
||||
#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40012000 */
|
||||
#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40012200 */
|
||||
#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40012400 */
|
||||
#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40012600 */
|
||||
#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40012800 */
|
||||
#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40012A00 */
|
||||
#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40012C00 */
|
||||
#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40012E00 */
|
||||
#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x40013000 */
|
||||
#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x40013200 */
|
||||
#define PERI_TR_GR10 ((PERI_TR_GR_Type*) &PERI->TR_GR[10]) /* 0x40013400 */
|
||||
#define PERI_TR_GR11 ((PERI_TR_GR_Type*) &PERI->TR_GR[11]) /* 0x40013600 */
|
||||
#define PERI_TR_GR12 ((PERI_TR_GR_Type*) &PERI->TR_GR[12]) /* 0x40013800 */
|
||||
#define PERI_TR_GR13 ((PERI_TR_GR_Type*) &PERI->TR_GR[13]) /* 0x40013A00 */
|
||||
#define PERI_TR_GR14 ((PERI_TR_GR_Type*) &PERI->TR_GR[14]) /* 0x40013C00 */
|
||||
#define PERI_PPU_PR0 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[0]) /* 0x40014000 */
|
||||
#define PERI_PPU_PR1 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[1]) /* 0x40014040 */
|
||||
#define PERI_PPU_PR2 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[2]) /* 0x40014080 */
|
||||
#define PERI_PPU_PR3 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[3]) /* 0x400140C0 */
|
||||
#define PERI_PPU_PR4 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[4]) /* 0x40014100 */
|
||||
#define PERI_PPU_PR5 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[5]) /* 0x40014140 */
|
||||
#define PERI_PPU_PR6 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[6]) /* 0x40014180 */
|
||||
#define PERI_PPU_PR7 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[7]) /* 0x400141C0 */
|
||||
#define PERI_PPU_PR8 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[8]) /* 0x40014200 */
|
||||
#define PERI_PPU_PR9 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[9]) /* 0x40014240 */
|
||||
#define PERI_PPU_PR10 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[10]) /* 0x40014280 */
|
||||
#define PERI_PPU_PR11 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[11]) /* 0x400142C0 */
|
||||
#define PERI_PPU_PR12 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[12]) /* 0x40014300 */
|
||||
#define PERI_PPU_PR13 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[13]) /* 0x40014340 */
|
||||
#define PERI_PPU_PR14 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[14]) /* 0x40014380 */
|
||||
#define PERI_PPU_PR15 ((PERI_PPU_PR_Type*) &PERI->PPU_PR[15]) /* 0x400143C0 */
|
||||
#define PERI_PPU_GR0 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[0]) /* 0x40015000 */
|
||||
#define PERI_PPU_GR1 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[1]) /* 0x40015040 */
|
||||
#define PERI_PPU_GR2 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[2]) /* 0x40015080 */
|
||||
#define PERI_PPU_GR3 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[3]) /* 0x400150C0 */
|
||||
#define PERI_PPU_GR4 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[4]) /* 0x40015100 */
|
||||
#define PERI_PPU_GR6 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[6]) /* 0x40015180 */
|
||||
#define PERI_PPU_GR9 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[9]) /* 0x40015240 */
|
||||
#define PERI_PPU_GR10 ((PERI_PPU_GR_Type*) &PERI->PPU_GR[10]) /* 0x40015280 */
|
||||
#define PERI_PPU_GR_MMIO0 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO0_BASE) /* 0x40015000 */
|
||||
#define PERI_PPU_GR_MMIO1 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO1_BASE) /* 0x40015040 */
|
||||
#define PERI_PPU_GR_MMIO2 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO2_BASE) /* 0x40015080 */
|
||||
#define PERI_PPU_GR_MMIO3 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO3_BASE) /* 0x400150C0 */
|
||||
#define PERI_PPU_GR_MMIO4 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO4_BASE) /* 0x40015100 */
|
||||
#define PERI_PPU_GR_MMIO6 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO6_BASE) /* 0x40015180 */
|
||||
#define PERI_PPU_GR_MMIO9 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO9_BASE) /* 0x40015240 */
|
||||
#define PERI_PPU_GR_MMIO10 ((PERI_PPU_GR_Type*) PERI_PPU_GR_MMIO10_BASE) /* 0x40015280 */
|
||||
#define PERI_GR_PPU_SL_PERI_GR1 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR1_BASE) /* 0x40100000 */
|
||||
#define PERI_GR_PPU_SL_CRYPTO ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_CRYPTO_BASE) /* 0x40100040 */
|
||||
#define PERI_GR_PPU_SL_PERI_GR2 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR2_BASE) /* 0x40200000 */
|
||||
#define PERI_GR_PPU_SL_CPUSS ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_CPUSS_BASE) /* 0x40200040 */
|
||||
#define PERI_GR_PPU_SL_FAULT ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_FAULT_BASE) /* 0x40200080 */
|
||||
#define PERI_GR_PPU_SL_IPC ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_IPC_BASE) /* 0x402000C0 */
|
||||
#define PERI_GR_PPU_SL_PROT ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PROT_BASE) /* 0x40200100 */
|
||||
#define PERI_GR_PPU_SL_FLASHC ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_FLASHC_BASE) /* 0x40200140 */
|
||||
#define PERI_GR_PPU_SL_SRSS ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SRSS_BASE) /* 0x40200180 */
|
||||
#define PERI_GR_PPU_SL_BACKUP ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_BACKUP_BASE) /* 0x402001C0 */
|
||||
#define PERI_GR_PPU_SL_DW0 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_DW0_BASE) /* 0x40200200 */
|
||||
#define PERI_GR_PPU_SL_DW1 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_DW1_BASE) /* 0x40200240 */
|
||||
#define PERI_GR_PPU_SL_EFUSE ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_EFUSE_BASE) /* 0x40200300 */
|
||||
#define PERI_GR_PPU_SL_PROFILE ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PROFILE_BASE) /* 0x40200340 */
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT0 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT0_BASE) /* 0x40201000 */
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT1 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT1_BASE) /* 0x40201040 */
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT2 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT2_BASE) /* 0x40201080 */
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT3 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT3_BASE) /* 0x402010C0 */
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT4 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT4_BASE) /* 0x40201100 */
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT5 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT5_BASE) /* 0x40201140 */
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT6 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT6_BASE) /* 0x40201180 */
|
||||
#define PERI_GR_PPU_RG_IPC_STRUCT7 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_STRUCT7_BASE) /* 0x402011C0 */
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT0 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT0_BASE) /* 0x40201200 */
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT1 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT1_BASE) /* 0x40201240 */
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT2 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT2_BASE) /* 0x40201280 */
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT3 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT3_BASE) /* 0x402012C0 */
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT4 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT4_BASE) /* 0x40201300 */
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT5 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT5_BASE) /* 0x40201340 */
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT6 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT6_BASE) /* 0x40201380 */
|
||||
#define PERI_GR_PPU_RG_IPC_INTR_STRUCT7 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_IPC_INTR_STRUCT7_BASE) /* 0x402013C0 */
|
||||
#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT0 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW0_DW_CH_STRUCT0_BASE) /* 0x40201400 */
|
||||
#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT1 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW0_DW_CH_STRUCT1_BASE) /* 0x40201440 */
|
||||
#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT2 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW0_DW_CH_STRUCT2_BASE) /* 0x40201480 */
|
||||
#define PERI_GR_PPU_RG_DW0_DW_CH_STRUCT3 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW0_DW_CH_STRUCT3_BASE) /* 0x402014C0 */
|
||||
#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT0 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW1_DW_CH_STRUCT0_BASE) /* 0x40201500 */
|
||||
#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT1 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW1_DW_CH_STRUCT1_BASE) /* 0x40201540 */
|
||||
#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT2 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW1_DW_CH_STRUCT2_BASE) /* 0x40201580 */
|
||||
#define PERI_GR_PPU_RG_DW1_DW_CH_STRUCT3 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_DW1_DW_CH_STRUCT3_BASE) /* 0x402015C0 */
|
||||
#define PERI_GR_PPU_RG_SMPU ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_SMPU_BASE) /* 0x40201600 */
|
||||
#define PERI_GR_PPU_RG_MPU_CM0P ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_MPU_CM0P_BASE) /* 0x40201640 */
|
||||
#define PERI_GR_PPU_RG_MPU_CRYPTO ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_MPU_CRYPTO_BASE) /* 0x40201680 */
|
||||
#define PERI_GR_PPU_RG_MPU_CM4 ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_MPU_CM4_BASE) /* 0x402016C0 */
|
||||
#define PERI_GR_PPU_RG_MPU_TC ((PERI_GR_PPU_RG_Type*) PERI_GR_PPU_RG_MPU_TC_BASE) /* 0x40201700 */
|
||||
#define PERI_GR_PPU_SL_PERI_GR3 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR3_BASE) /* 0x40300000 */
|
||||
#define PERI_GR_PPU_SL_HSIOM ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_HSIOM_BASE) /* 0x40300040 */
|
||||
#define PERI_GR_PPU_SL_GPIO ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_GPIO_BASE) /* 0x40300080 */
|
||||
#define PERI_GR_PPU_SL_SMARTIO ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SMARTIO_BASE) /* 0x403000C0 */
|
||||
#define PERI_GR_PPU_SL_UDB ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_UDB_BASE) /* 0x40300100 */
|
||||
#define PERI_GR_PPU_SL_LPCOMP ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_LPCOMP_BASE) /* 0x40300140 */
|
||||
#define PERI_GR_PPU_SL_CSD ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_CSD_BASE) /* 0x40300180 */
|
||||
#define PERI_GR_PPU_SL_TCPWM0 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_TCPWM0_BASE) /* 0x40300200 */
|
||||
#define PERI_GR_PPU_SL_TCPWM1 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_TCPWM1_BASE) /* 0x40300240 */
|
||||
#define PERI_GR_PPU_SL_LCD ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_LCD_BASE) /* 0x40300280 */
|
||||
#define PERI_GR_PPU_SL_BLE ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_BLE_BASE) /* 0x403002C0 */
|
||||
#define PERI_GR_PPU_SL_USBFS ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_USBFS_BASE) /* 0x40300300 */
|
||||
#define PERI_GR_PPU_SL_PERI_GR4 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR4_BASE) /* 0x40400000 */
|
||||
#define PERI_GR_PPU_SL_SMIF ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SMIF_BASE) /* 0x40400080 */
|
||||
#define PERI_GR_PPU_SL_PERI_GR6 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR6_BASE) /* 0x40600000 */
|
||||
#define PERI_GR_PPU_SL_SCB0 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB0_BASE) /* 0x40600040 */
|
||||
#define PERI_GR_PPU_SL_SCB1 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB1_BASE) /* 0x40600080 */
|
||||
#define PERI_GR_PPU_SL_SCB2 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB2_BASE) /* 0x406000C0 */
|
||||
#define PERI_GR_PPU_SL_SCB3 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB3_BASE) /* 0x40600100 */
|
||||
#define PERI_GR_PPU_SL_SCB4 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB4_BASE) /* 0x40600140 */
|
||||
#define PERI_GR_PPU_SL_SCB5 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB5_BASE) /* 0x40600180 */
|
||||
#define PERI_GR_PPU_SL_SCB6 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB6_BASE) /* 0x406001C0 */
|
||||
#define PERI_GR_PPU_SL_SCB7 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB7_BASE) /* 0x40600200 */
|
||||
#define PERI_GR_PPU_SL_SCB8 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_SCB8_BASE) /* 0x40600240 */
|
||||
#define PERI_GR_PPU_SL_PERI_GR9 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR9_BASE) /* 0x41000000 */
|
||||
#define PERI_GR_PPU_SL_PASS ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PASS_BASE) /* 0x41000040 */
|
||||
#define PERI_GR_PPU_SL_PERI_GR10 ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PERI_GR10_BASE) /* 0x42A00000 */
|
||||
#define PERI_GR_PPU_SL_I2S ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_I2S_BASE) /* 0x42A00040 */
|
||||
#define PERI_GR_PPU_SL_PDM ((PERI_GR_PPU_SL_Type*) PERI_GR_PPU_SL_PDM_BASE) /* 0x42A00080 */
|
||||
|
||||
/*******************************************************************************
|
||||
* CPUSS
|
||||
*******************************************************************************/
|
||||
|
||||
#define CPUSS_BASE 0x40210000UL
|
||||
#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40210000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* FAULT
|
||||
*******************************************************************************/
|
||||
|
||||
#define FAULT_BASE 0x40220000UL
|
||||
#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40220000 */
|
||||
#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40220000 */
|
||||
#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40220100 */
|
||||
|
||||
/*******************************************************************************
|
||||
* IPC
|
||||
*******************************************************************************/
|
||||
|
||||
#define IPC_BASE 0x40230000UL
|
||||
#define IPC ((IPC_Type*) IPC_BASE) /* 0x40230000 */
|
||||
#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40230000 */
|
||||
#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40230020 */
|
||||
#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40230040 */
|
||||
#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40230060 */
|
||||
#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40230080 */
|
||||
#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402300A0 */
|
||||
#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402300C0 */
|
||||
#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402300E0 */
|
||||
#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40230100 */
|
||||
#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40230120 */
|
||||
#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40230140 */
|
||||
#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40230160 */
|
||||
#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40230180 */
|
||||
#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402301A0 */
|
||||
#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402301C0 */
|
||||
#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402301E0 */
|
||||
#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40231000 */
|
||||
#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40231020 */
|
||||
#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40231040 */
|
||||
#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40231060 */
|
||||
#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40231080 */
|
||||
#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402310A0 */
|
||||
#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402310C0 */
|
||||
#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402310E0 */
|
||||
#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40231100 */
|
||||
#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40231120 */
|
||||
#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40231140 */
|
||||
#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40231160 */
|
||||
#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40231180 */
|
||||
#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402311A0 */
|
||||
#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402311C0 */
|
||||
#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402311E0 */
|
||||
|
||||
/*******************************************************************************
|
||||
* PROT
|
||||
*******************************************************************************/
|
||||
|
||||
#define PROT_BASE 0x40240000UL
|
||||
#define PROT ((PROT_Type*) PROT_BASE) /* 0x40240000 */
|
||||
#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40242000 */
|
||||
#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40242040 */
|
||||
#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40242080 */
|
||||
#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402420C0 */
|
||||
#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40242100 */
|
||||
#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40242140 */
|
||||
#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40242180 */
|
||||
#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402421C0 */
|
||||
#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40242200 */
|
||||
#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40242240 */
|
||||
#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40242280 */
|
||||
#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402422C0 */
|
||||
#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40242300 */
|
||||
#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40242340 */
|
||||
#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40242380 */
|
||||
#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402423C0 */
|
||||
#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40240000 */
|
||||
#define PROT_MPU1_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[0]) /* 0x40244600 */
|
||||
#define PROT_MPU1_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[1]) /* 0x40244620 */
|
||||
#define PROT_MPU1_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[2]) /* 0x40244640 */
|
||||
#define PROT_MPU1_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[3]) /* 0x40244660 */
|
||||
#define PROT_MPU1_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[4]) /* 0x40244680 */
|
||||
#define PROT_MPU1_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[5]) /* 0x402446A0 */
|
||||
#define PROT_MPU1_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[6]) /* 0x402446C0 */
|
||||
#define PROT_MPU1_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[1].MPU_STRUCT[7]) /* 0x402446E0 */
|
||||
#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40247E00 */
|
||||
#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40247E20 */
|
||||
#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40247E40 */
|
||||
#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40247E60 */
|
||||
#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40247E80 */
|
||||
#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40247EA0 */
|
||||
#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40247EC0 */
|
||||
#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40247EE0 */
|
||||
#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40244000 */
|
||||
#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40244400 */
|
||||
#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40244800 */
|
||||
#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40244C00 */
|
||||
#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40245000 */
|
||||
#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40245400 */
|
||||
#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40245800 */
|
||||
#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40245C00 */
|
||||
#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40246000 */
|
||||
#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40246400 */
|
||||
#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40246800 */
|
||||
#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40246C00 */
|
||||
#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40247000 */
|
||||
#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40247400 */
|
||||
#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40247800 */
|
||||
#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40247C00 */
|
||||
|
||||
/*******************************************************************************
|
||||
* FLASHC
|
||||
*******************************************************************************/
|
||||
|
||||
#define FLASHC_BASE 0x40250000UL
|
||||
#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40250000 */
|
||||
#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4025F000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* SRSS
|
||||
*******************************************************************************/
|
||||
|
||||
#define SRSS_BASE 0x40260000UL
|
||||
#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */
|
||||
#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */
|
||||
#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */
|
||||
|
||||
/*******************************************************************************
|
||||
* BACKUP
|
||||
*******************************************************************************/
|
||||
|
||||
#define BACKUP_BASE 0x40270000UL
|
||||
#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* DW
|
||||
*******************************************************************************/
|
||||
|
||||
#define DW0_BASE 0x40280000UL
|
||||
#define DW1_BASE 0x40281000UL
|
||||
#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */
|
||||
#define DW1 ((DW_Type*) DW1_BASE) /* 0x40281000 */
|
||||
#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40280800 */
|
||||
#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40280820 */
|
||||
#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40280840 */
|
||||
#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x40280860 */
|
||||
#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40280880 */
|
||||
#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x402808A0 */
|
||||
#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x402808C0 */
|
||||
#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402808E0 */
|
||||
#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40280900 */
|
||||
#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40280920 */
|
||||
#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40280940 */
|
||||
#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x40280960 */
|
||||
#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40280980 */
|
||||
#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x402809A0 */
|
||||
#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x402809C0 */
|
||||
#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402809E0 */
|
||||
#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40281800 */
|
||||
#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40281820 */
|
||||
#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40281840 */
|
||||
#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x40281860 */
|
||||
#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40281880 */
|
||||
#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x402818A0 */
|
||||
#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x402818C0 */
|
||||
#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402818E0 */
|
||||
#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40281900 */
|
||||
#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40281920 */
|
||||
#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40281940 */
|
||||
#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x40281960 */
|
||||
#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40281980 */
|
||||
#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x402819A0 */
|
||||
#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x402819C0 */
|
||||
#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402819E0 */
|
||||
|
||||
/*******************************************************************************
|
||||
* EFUSE
|
||||
*******************************************************************************/
|
||||
|
||||
#define EFUSE_BASE 0x402C0000UL
|
||||
#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* PROFILE
|
||||
*******************************************************************************/
|
||||
|
||||
#define PROFILE_BASE 0x402D0000UL
|
||||
#define PROFILE ((PROFILE_Type*) PROFILE_BASE) /* 0x402D0000 */
|
||||
#define PROFILE_CNT_STRUCT0 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[0]) /* 0x402D0800 */
|
||||
#define PROFILE_CNT_STRUCT1 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[1]) /* 0x402D0810 */
|
||||
#define PROFILE_CNT_STRUCT2 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[2]) /* 0x402D0820 */
|
||||
#define PROFILE_CNT_STRUCT3 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[3]) /* 0x402D0830 */
|
||||
#define PROFILE_CNT_STRUCT4 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[4]) /* 0x402D0840 */
|
||||
#define PROFILE_CNT_STRUCT5 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[5]) /* 0x402D0850 */
|
||||
#define PROFILE_CNT_STRUCT6 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[6]) /* 0x402D0860 */
|
||||
#define PROFILE_CNT_STRUCT7 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[7]) /* 0x402D0870 */
|
||||
|
||||
/*******************************************************************************
|
||||
* HSIOM
|
||||
*******************************************************************************/
|
||||
|
||||
#define HSIOM_BASE 0x40310000UL
|
||||
#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40310000 */
|
||||
#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40310000 */
|
||||
#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40310010 */
|
||||
#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40310020 */
|
||||
#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40310030 */
|
||||
#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40310040 */
|
||||
#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40310050 */
|
||||
#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40310060 */
|
||||
#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40310070 */
|
||||
#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40310080 */
|
||||
#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40310090 */
|
||||
#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403100A0 */
|
||||
#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403100B0 */
|
||||
#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403100C0 */
|
||||
#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403100D0 */
|
||||
#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403100E0 */
|
||||
|
||||
/*******************************************************************************
|
||||
* GPIO
|
||||
*******************************************************************************/
|
||||
|
||||
#define GPIO_BASE 0x40320000UL
|
||||
#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40320000 */
|
||||
#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40320000 */
|
||||
#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40320080 */
|
||||
#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40320100 */
|
||||
#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40320180 */
|
||||
#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40320200 */
|
||||
#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40320280 */
|
||||
#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40320300 */
|
||||
#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40320380 */
|
||||
#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40320400 */
|
||||
#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40320480 */
|
||||
#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40320500 */
|
||||
#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40320580 */
|
||||
#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40320600 */
|
||||
#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40320680 */
|
||||
#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40320700 */
|
||||
|
||||
/*******************************************************************************
|
||||
* SMARTIO
|
||||
*******************************************************************************/
|
||||
|
||||
#define SMARTIO_BASE 0x40330000UL
|
||||
#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40330000 */
|
||||
#define SMARTIO_PRT8 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[8]) /* 0x40330800 */
|
||||
#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40330900 */
|
||||
|
||||
/*******************************************************************************
|
||||
* LPCOMP
|
||||
*******************************************************************************/
|
||||
|
||||
#define LPCOMP_BASE 0x40350000UL
|
||||
#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* CSD
|
||||
*******************************************************************************/
|
||||
|
||||
#define CSD0_BASE 0x40360000UL
|
||||
#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* TCPWM
|
||||
*******************************************************************************/
|
||||
|
||||
#define TCPWM0_BASE 0x40380000UL
|
||||
#define TCPWM1_BASE 0x40390000UL
|
||||
#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */
|
||||
#define TCPWM1 ((TCPWM_Type*) TCPWM1_BASE) /* 0x40390000 */
|
||||
#define TCPWM0_CNT0 ((TCPWM_CNT_Type*) &TCPWM0->CNT[0]) /* 0x40380100 */
|
||||
#define TCPWM0_CNT1 ((TCPWM_CNT_Type*) &TCPWM0->CNT[1]) /* 0x40380140 */
|
||||
#define TCPWM0_CNT2 ((TCPWM_CNT_Type*) &TCPWM0->CNT[2]) /* 0x40380180 */
|
||||
#define TCPWM0_CNT3 ((TCPWM_CNT_Type*) &TCPWM0->CNT[3]) /* 0x403801C0 */
|
||||
#define TCPWM0_CNT4 ((TCPWM_CNT_Type*) &TCPWM0->CNT[4]) /* 0x40380200 */
|
||||
#define TCPWM0_CNT5 ((TCPWM_CNT_Type*) &TCPWM0->CNT[5]) /* 0x40380240 */
|
||||
#define TCPWM0_CNT6 ((TCPWM_CNT_Type*) &TCPWM0->CNT[6]) /* 0x40380280 */
|
||||
#define TCPWM0_CNT7 ((TCPWM_CNT_Type*) &TCPWM0->CNT[7]) /* 0x403802C0 */
|
||||
#define TCPWM1_CNT0 ((TCPWM_CNT_Type*) &TCPWM1->CNT[0]) /* 0x40390100 */
|
||||
#define TCPWM1_CNT1 ((TCPWM_CNT_Type*) &TCPWM1->CNT[1]) /* 0x40390140 */
|
||||
#define TCPWM1_CNT2 ((TCPWM_CNT_Type*) &TCPWM1->CNT[2]) /* 0x40390180 */
|
||||
#define TCPWM1_CNT3 ((TCPWM_CNT_Type*) &TCPWM1->CNT[3]) /* 0x403901C0 */
|
||||
#define TCPWM1_CNT4 ((TCPWM_CNT_Type*) &TCPWM1->CNT[4]) /* 0x40390200 */
|
||||
#define TCPWM1_CNT5 ((TCPWM_CNT_Type*) &TCPWM1->CNT[5]) /* 0x40390240 */
|
||||
#define TCPWM1_CNT6 ((TCPWM_CNT_Type*) &TCPWM1->CNT[6]) /* 0x40390280 */
|
||||
#define TCPWM1_CNT7 ((TCPWM_CNT_Type*) &TCPWM1->CNT[7]) /* 0x403902C0 */
|
||||
#define TCPWM1_CNT8 ((TCPWM_CNT_Type*) &TCPWM1->CNT[8]) /* 0x40390300 */
|
||||
#define TCPWM1_CNT9 ((TCPWM_CNT_Type*) &TCPWM1->CNT[9]) /* 0x40390340 */
|
||||
#define TCPWM1_CNT10 ((TCPWM_CNT_Type*) &TCPWM1->CNT[10]) /* 0x40390380 */
|
||||
#define TCPWM1_CNT11 ((TCPWM_CNT_Type*) &TCPWM1->CNT[11]) /* 0x403903C0 */
|
||||
#define TCPWM1_CNT12 ((TCPWM_CNT_Type*) &TCPWM1->CNT[12]) /* 0x40390400 */
|
||||
#define TCPWM1_CNT13 ((TCPWM_CNT_Type*) &TCPWM1->CNT[13]) /* 0x40390440 */
|
||||
#define TCPWM1_CNT14 ((TCPWM_CNT_Type*) &TCPWM1->CNT[14]) /* 0x40390480 */
|
||||
#define TCPWM1_CNT15 ((TCPWM_CNT_Type*) &TCPWM1->CNT[15]) /* 0x403904C0 */
|
||||
#define TCPWM1_CNT16 ((TCPWM_CNT_Type*) &TCPWM1->CNT[16]) /* 0x40390500 */
|
||||
#define TCPWM1_CNT17 ((TCPWM_CNT_Type*) &TCPWM1->CNT[17]) /* 0x40390540 */
|
||||
#define TCPWM1_CNT18 ((TCPWM_CNT_Type*) &TCPWM1->CNT[18]) /* 0x40390580 */
|
||||
#define TCPWM1_CNT19 ((TCPWM_CNT_Type*) &TCPWM1->CNT[19]) /* 0x403905C0 */
|
||||
#define TCPWM1_CNT20 ((TCPWM_CNT_Type*) &TCPWM1->CNT[20]) /* 0x40390600 */
|
||||
#define TCPWM1_CNT21 ((TCPWM_CNT_Type*) &TCPWM1->CNT[21]) /* 0x40390640 */
|
||||
#define TCPWM1_CNT22 ((TCPWM_CNT_Type*) &TCPWM1->CNT[22]) /* 0x40390680 */
|
||||
#define TCPWM1_CNT23 ((TCPWM_CNT_Type*) &TCPWM1->CNT[23]) /* 0x403906C0 */
|
||||
|
||||
/*******************************************************************************
|
||||
* LCD
|
||||
*******************************************************************************/
|
||||
|
||||
#define LCD0_BASE 0x403B0000UL
|
||||
#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* BLE
|
||||
*******************************************************************************/
|
||||
|
||||
#define BLE_BASE 0x403C0000UL
|
||||
#define BLE ((BLE_Type*) BLE_BASE) /* 0x403C0000 */
|
||||
#define BLE_RCB_RCBLL ((BLE_RCB_RCBLL_Type*) &BLE->RCB.RCBLL) /* 0x403C0100 */
|
||||
#define BLE_RCB ((BLE_RCB_Type*) &BLE->RCB) /* 0x403C0000 */
|
||||
#define BLE_BLELL ((BLE_BLELL_Type*) &BLE->BLELL) /* 0x403C1000 */
|
||||
#define BLE_BLESS ((BLE_BLESS_Type*) &BLE->BLESS) /* 0x403DF000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* SMIF
|
||||
*******************************************************************************/
|
||||
|
||||
#define SMIF0_BASE 0x40420000UL
|
||||
#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */
|
||||
#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */
|
||||
#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */
|
||||
#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */
|
||||
#define SMIF0_DEVICE3 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[3]) /* 0x40420980 */
|
||||
|
||||
/*******************************************************************************
|
||||
* SCB
|
||||
*******************************************************************************/
|
||||
|
||||
#define SCB0_BASE 0x40610000UL
|
||||
#define SCB1_BASE 0x40620000UL
|
||||
#define SCB2_BASE 0x40630000UL
|
||||
#define SCB3_BASE 0x40640000UL
|
||||
#define SCB4_BASE 0x40650000UL
|
||||
#define SCB5_BASE 0x40660000UL
|
||||
#define SCB6_BASE 0x40670000UL
|
||||
#define SCB7_BASE 0x40680000UL
|
||||
#define SCB8_BASE 0x40690000UL
|
||||
#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40610000 */
|
||||
#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40620000 */
|
||||
#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40630000 */
|
||||
#define SCB3 ((CySCB_Type*) SCB3_BASE) /* 0x40640000 */
|
||||
#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40650000 */
|
||||
#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40660000 */
|
||||
#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40670000 */
|
||||
#define SCB7 ((CySCB_Type*) SCB7_BASE) /* 0x40680000 */
|
||||
#define SCB8 ((CySCB_Type*) SCB8_BASE) /* 0x40690000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* CTDAC
|
||||
*******************************************************************************/
|
||||
|
||||
#define CTDAC0_BASE 0x41140000UL
|
||||
#define CTDAC0 ((CTDAC_Type*) CTDAC0_BASE) /* 0x41140000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* SAR
|
||||
*******************************************************************************/
|
||||
|
||||
#define SAR_BASE 0x411D0000UL
|
||||
#define SAR ((SAR_Type*) SAR_BASE) /* 0x411D0000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* PASS
|
||||
*******************************************************************************/
|
||||
|
||||
#define PASS_BASE 0x411F0000UL
|
||||
#define PASS ((PASS_Type*) PASS_BASE) /* 0x411F0000 */
|
||||
#define PASS_AREF ((PASS_AREF_Type*) &PASS->AREF) /* 0x411F0E00 */
|
||||
|
||||
/*******************************************************************************
|
||||
* I2S
|
||||
*******************************************************************************/
|
||||
|
||||
#define I2S0_BASE 0x42A10000UL
|
||||
#define I2S0 ((I2S_Type*) I2S0_BASE) /* 0x42A10000 */
|
||||
|
||||
/*******************************************************************************
|
||||
* PDM
|
||||
*******************************************************************************/
|
||||
|
||||
#define PDM0_BASE 0x42A20000UL
|
||||
#define PDM0 ((PDM_Type*) PDM0_BASE) /* 0x42A20000 */
|
||||
|
||||
|
||||
/* Backward compabitility definitions */
|
||||
#define I2S I2S0
|
||||
#define PDM PDM0
|
||||
|
||||
/** \} CY8C6337BZI-BLF13 */
|
||||
|
||||
#endif /* _CY8C6337BZI_BLF13_H_ */
|
||||
|
||||
|
||||
/* [] END OF FILE */
|
||||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -1,667 +0,0 @@
|
|||
/***************************************************************************//**
|
||||
* \file cy_device_common.h
|
||||
*
|
||||
* \brief
|
||||
* This file provides types and common device definitions that do not changed
|
||||
* between different products.
|
||||
*
|
||||
********************************************************************************
|
||||
* \copyright
|
||||
* Copyright 2018, Cypress Semiconductor Corporation. All rights reserved.
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
|
||||
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _CY_DEVICE_COMMON_H_
|
||||
#define _CY_DEVICE_COMMON_H_
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/*******************************************************************************
|
||||
* Interrupt Number Definition
|
||||
*******************************************************************************/
|
||||
|
||||
typedef enum {
|
||||
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
|
||||
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
|
||||
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
|
||||
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
|
||||
/* ARM Cortex-M0+ Core Interrupt Numbers */
|
||||
Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */
|
||||
NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */
|
||||
HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */
|
||||
SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */
|
||||
PendSV_IRQn = -2, /*!< -2 Pendable request for system service */
|
||||
SysTick_IRQn = -1 /*!< -1 System Tick Timer */
|
||||
|
||||
#else
|
||||
/* ARM Cortex-M4 Core Interrupt Numbers */
|
||||
Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */
|
||||
NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */
|
||||
HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */
|
||||
MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */
|
||||
BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */
|
||||
UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
|
||||
SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */
|
||||
DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */
|
||||
PendSV_IRQn = -2, /*!< -2 Pendable request for system service */
|
||||
SysTick_IRQn = -1, /*!< -1 System Tick Timer */
|
||||
|
||||
#endif
|
||||
} IRQn_Type;
|
||||
|
||||
|
||||
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
|
||||
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
|
||||
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
|
||||
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
|
||||
|
||||
typedef enum {
|
||||
disconnected_IRQn = 240 /*!< 240 Disconnected */
|
||||
} cy_en_intr_t;
|
||||
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Processor and Core Peripheral Section
|
||||
*******************************************************************************/
|
||||
|
||||
#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \
|
||||
(defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \
|
||||
(defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \
|
||||
(defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__)))
|
||||
|
||||
/* Configuration of the ARM Cortex-M0+ Processor and Core Peripherals */
|
||||
#define __CM0PLUS_REV 0x0001U /*!< CM0PLUS Core Revision */
|
||||
#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
|
||||
#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */
|
||||
#define __MPU_PRESENT 1 /*!< MPU present or not */
|
||||
|
||||
/** \} Configuration_of_CMSIS */
|
||||
|
||||
#include "core_cm0plus.h" /*!< ARM Cortex-M0+ processor and core peripherals */
|
||||
|
||||
#else
|
||||
|
||||
/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */
|
||||
#define __CM4_REV 0x0001U /*!< CM4 Core Revision */
|
||||
#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
|
||||
#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */
|
||||
#define __MPU_PRESENT 1 /*!< MPU present or not */
|
||||
#define __FPU_PRESENT 1 /*!< FPU present or not */
|
||||
#define __CM0P_PRESENT 1 /*!< CM0P present or not */
|
||||
|
||||
/** \} Configuration_of_CMSIS */
|
||||
|
||||
#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */
|
||||
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Product-specific enums describing platform resources
|
||||
*******************************************************************************/
|
||||
/* For the target device these enums are defined in product-specific
|
||||
* configuration files.
|
||||
*/
|
||||
|
||||
typedef int en_clk_dst_t; /* SysClk */
|
||||
typedef int en_ep_mon_sel_t; /* Profile */
|
||||
typedef int en_hsiom_sel_t; /* GPIO */
|
||||
|
||||
typedef enum
|
||||
{
|
||||
TRIGGER_TYPE_LEVEL = 0u,
|
||||
TRIGGER_TYPE_EDGE = 1u
|
||||
} en_trig_type_t;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
CPUSS_MS_ID_CM0 = 0,
|
||||
CPUSS_MS_ID_CM4 = 14,
|
||||
} en_prot_master_t;
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Platform and peripheral definitions
|
||||
*******************************************************************************/
|
||||
|
||||
#define CY_IP_MXTCPWM 1u
|
||||
#define CY_IP_MXCSDV2 1u
|
||||
#define CY_IP_MXLCD 1u
|
||||
#define CY_IP_MXS40SRSS 1u
|
||||
#define CY_IP_MXS40SRSS_RTC 1u
|
||||
#define CY_IP_MXS40SRSS_MCWDT 1u
|
||||
#define CY_IP_MXSCB 1u
|
||||
#define CY_IP_MXPERI 1u
|
||||
#define CY_IP_MXPERI_TR 1u
|
||||
#define CY_IP_M4CPUSS 1u
|
||||
#define CY_IP_M4CPUSS_DMA 1u
|
||||
#define CY_IP_MXCRYPTO 1u
|
||||
#define CY_IP_MXBLESS 1u
|
||||
#define CY_IP_MXSDHC 1u
|
||||
#define CY_IP_MXAUDIOSS 1u
|
||||
#define CY_IP_MXLPCOMP 1u
|
||||
#define CY_IP_MXS40PASS 1u
|
||||
#define CY_IP_MXS40PASS_SAR 1u
|
||||
#define CY_IP_MXS40PASS_CTDAC 1u
|
||||
#define CY_IP_MXS40PASS_CTB 1u
|
||||
#define CY_IP_MXSMIF 1u
|
||||
#define CY_IP_MXUSBFS 1u
|
||||
#define CY_IP_MXS40IOSS 1u
|
||||
#define CY_IP_MXEFUSE 1u
|
||||
#define CY_IP_MXUDB 1u
|
||||
#define CY_IP_MXPROFILE 1u
|
||||
|
||||
/* Include IP definitions */
|
||||
#include "ip/cyip_sflash.h"
|
||||
#include "ip/cyip_peri.h"
|
||||
#include "ip/cyip_peri_v2.h"
|
||||
#include "ip/cyip_peri_ms_v2.h"
|
||||
#include "ip/cyip_crypto.h"
|
||||
#include "ip/cyip_crypto_v2.h"
|
||||
#include "ip/cyip_cpuss.h"
|
||||
#include "ip/cyip_cpuss_v2.h"
|
||||
#include "ip/cyip_fault.h"
|
||||
#include "ip/cyip_fault_v2.h"
|
||||
#include "ip/cyip_ipc.h"
|
||||
#include "ip/cyip_ipc_v2.h"
|
||||
#include "ip/cyip_prot.h"
|
||||
#include "ip/cyip_prot_v2.h"
|
||||
#include "ip/cyip_flashc.h"
|
||||
#include "ip/cyip_flashc_v2.h"
|
||||
#include "ip/cyip_srss.h"
|
||||
#include "ip/cyip_backup.h"
|
||||
#include "ip/cyip_dw.h"
|
||||
#include "ip/cyip_dw_v2.h"
|
||||
#include "ip/cyip_dmac_v2.h"
|
||||
#include "ip/cyip_efuse.h"
|
||||
#include "ip/cyip_efuse_data.h"
|
||||
#include "ip/cyip_profile.h"
|
||||
#include "ip/cyip_hsiom.h"
|
||||
#include "ip/cyip_hsiom_v2.h"
|
||||
#include "ip/cyip_gpio.h"
|
||||
#include "ip/cyip_gpio_v2.h"
|
||||
#include "ip/cyip_smartio.h"
|
||||
#include "ip/cyip_smartio_v2.h"
|
||||
#include "ip/cyip_udb.h"
|
||||
#include "ip/cyip_lpcomp.h"
|
||||
#include "ip/cyip_csd.h"
|
||||
#include "ip/cyip_tcpwm.h"
|
||||
#include "ip/cyip_lcd.h"
|
||||
#include "ip/cyip_ble.h"
|
||||
#include "ip/cyip_usbfs.h"
|
||||
#include "ip/cyip_smif.h"
|
||||
#include "ip/cyip_sdhc.h"
|
||||
#include "ip/cyip_scb.h"
|
||||
#include "ip/cyip_ctbm.h"
|
||||
#include "ip/cyip_ctdac.h"
|
||||
#include "ip/cyip_sar.h"
|
||||
#include "ip/cyip_pass.h"
|
||||
#include "ip/cyip_i2s.h"
|
||||
#include "ip/cyip_pdm.h"
|
||||
|
||||
/* IP type definitions */
|
||||
typedef SFLASH_V1_Type SFLASH_Type;
|
||||
typedef PERI_GR_V2_Type PERI_GR_Type;
|
||||
typedef PERI_TR_GR_V2_Type PERI_TR_GR_Type;
|
||||
typedef PERI_TR_1TO1_GR_V2_Type PERI_TR_1TO1_GR_Type;
|
||||
typedef PERI_PPU_PR_V1_Type PERI_PPU_PR_Type;
|
||||
typedef PERI_PPU_GR_V1_Type PERI_PPU_GR_Type;
|
||||
typedef PERI_GR_PPU_SL_V1_Type PERI_GR_PPU_SL_Type;
|
||||
typedef PERI_GR_PPU_RG_V1_Type PERI_GR_PPU_RG_Type;
|
||||
typedef PERI_V2_Type PERI_Type;
|
||||
typedef PERI_MS_PPU_PR_V2_Type PERI_MS_PPU_PR_Type;
|
||||
typedef PERI_MS_PPU_FX_V2_Type PERI_MS_PPU_FX_Type;
|
||||
typedef PERI_MS_V2_Type PERI_MS_Type;
|
||||
typedef CRYPTO_V2_Type CRYPTO_Type;
|
||||
typedef CPUSS_V2_Type CPUSS_Type;
|
||||
typedef FAULT_STRUCT_V2_Type FAULT_STRUCT_Type;
|
||||
typedef FAULT_V2_Type FAULT_Type;
|
||||
typedef IPC_STRUCT_V2_Type IPC_STRUCT_Type;
|
||||
typedef IPC_INTR_STRUCT_V2_Type IPC_INTR_STRUCT_Type;
|
||||
typedef IPC_V2_Type IPC_Type;
|
||||
typedef PROT_SMPU_SMPU_STRUCT_V2_Type PROT_SMPU_SMPU_STRUCT_Type;
|
||||
typedef PROT_SMPU_V2_Type PROT_SMPU_Type;
|
||||
typedef PROT_MPU_MPU_STRUCT_V2_Type PROT_MPU_MPU_STRUCT_Type;
|
||||
typedef PROT_MPU_V2_Type PROT_MPU_Type;
|
||||
typedef PROT_V2_Type PROT_Type;
|
||||
typedef FLASHC_FM_CTL_V2_Type FLASHC_FM_CTL_Type;
|
||||
typedef FLASHC_V2_Type FLASHC_Type;
|
||||
typedef MCWDT_STRUCT_V1_Type MCWDT_STRUCT_Type;
|
||||
typedef SRSS_V1_Type SRSS_Type;
|
||||
typedef BACKUP_V1_Type BACKUP_Type;
|
||||
typedef DW_CH_STRUCT_V2_Type DW_CH_STRUCT_Type;
|
||||
typedef DW_V2_Type DW_Type;
|
||||
typedef DMAC_CH_V2_Type DMAC_CH_Type;
|
||||
typedef DMAC_V2_Type DMAC_Type;
|
||||
typedef EFUSE_V1_Type EFUSE_Type;
|
||||
typedef PROFILE_CNT_STRUCT_V1_Type PROFILE_CNT_STRUCT_Type;
|
||||
typedef PROFILE_V1_Type PROFILE_Type;
|
||||
typedef HSIOM_PRT_V2_Type HSIOM_PRT_Type;
|
||||
typedef HSIOM_V2_Type HSIOM_Type;
|
||||
typedef GPIO_PRT_V2_Type GPIO_PRT_Type;
|
||||
typedef GPIO_V2_Type GPIO_Type;
|
||||
typedef SMARTIO_PRT_V2_Type SMARTIO_PRT_Type;
|
||||
typedef SMARTIO_V2_Type SMARTIO_Type;
|
||||
typedef UDB_WRKONE_V1_Type UDB_WRKONE_Type;
|
||||
typedef UDB_WRKMULT_V1_Type UDB_WRKMULT_Type;
|
||||
typedef UDB_UDBPAIR_UDBSNG_V1_Type UDB_UDBPAIR_UDBSNG_Type;
|
||||
typedef UDB_UDBPAIR_ROUTE_V1_Type UDB_UDBPAIR_ROUTE_Type;
|
||||
typedef UDB_UDBPAIR_V1_Type UDB_UDBPAIR_Type;
|
||||
typedef UDB_DSI_V1_Type UDB_DSI_Type;
|
||||
typedef UDB_PA_V1_Type UDB_PA_Type;
|
||||
typedef UDB_BCTL_V1_Type UDB_BCTL_Type;
|
||||
typedef UDB_UDBIF_V1_Type UDB_UDBIF_Type;
|
||||
typedef UDB_V1_Type UDB_Type;
|
||||
typedef LPCOMP_V1_Type LPCOMP_Type;
|
||||
typedef CSD_V1_Type CSD_Type;
|
||||
typedef TCPWM_CNT_V1_Type TCPWM_CNT_Type;
|
||||
typedef TCPWM_V1_Type TCPWM_Type;
|
||||
typedef LCD_V1_Type LCD_Type;
|
||||
typedef BLE_RCB_RCBLL_V1_Type BLE_RCB_RCBLL_Type;
|
||||
typedef BLE_RCB_V1_Type BLE_RCB_Type;
|
||||
typedef BLE_BLELL_V1_Type BLE_BLELL_Type;
|
||||
typedef BLE_BLESS_V1_Type BLE_BLESS_Type;
|
||||
typedef BLE_V1_Type BLE_Type;
|
||||
typedef USBFS_USBDEV_V1_Type USBFS_USBDEV_Type;
|
||||
typedef USBFS_USBLPM_V1_Type USBFS_USBLPM_Type;
|
||||
typedef USBFS_USBHOST_V1_Type USBFS_USBHOST_Type;
|
||||
typedef USBFS_V1_Type USBFS_Type;
|
||||
typedef SMIF_DEVICE_V1_Type SMIF_DEVICE_Type;
|
||||
typedef SMIF_V1_Type SMIF_Type;
|
||||
typedef SDHC_WRAP_V1_Type SDHC_WRAP_Type;
|
||||
typedef SDHC_CORE_V1_Type SDHC_CORE_Type;
|
||||
typedef SDHC_V1_Type SDHC_Type;
|
||||
typedef CySCB_V1_Type CySCB_Type;
|
||||
typedef CTBM_V1_Type CTBM_Type;
|
||||
typedef CTDAC_V1_Type CTDAC_Type;
|
||||
typedef SAR_V1_Type SAR_Type;
|
||||
typedef PASS_AREF_V1_Type PASS_AREF_Type;
|
||||
typedef PASS_V1_Type PASS_Type;
|
||||
typedef PDM_V1_Type PDM_Type;
|
||||
typedef I2S_V1_Type I2S_Type;
|
||||
|
||||
/*******************************************************************************
|
||||
* Symbols with external linkage
|
||||
*******************************************************************************/
|
||||
|
||||
extern uint32_t cy_PeriClkFreqHz;
|
||||
extern uint32_t cy_BleEcoClockFreqHz;
|
||||
|
||||
/*******************************************************************************
|
||||
* The remaining part is temporary here to enable library build and will
|
||||
* go away once all drivers are updated.
|
||||
*******************************************************************************/
|
||||
/* Number of IPC structures. Set the max allowed for platform */
|
||||
#define CPUSS_IPC_IPC_NR 16u
|
||||
/* Number of IPC interrupt structures. Set the max allowed for platform */
|
||||
#define CPUSS_IPC_IPC_IRQ_NR 16u
|
||||
|
||||
/* This is problematic. The drivers MUST NOT access interrupts directly.
|
||||
* cpuss_interrupts_ipc_0_IRQn differs between BLE and 2M and the difference
|
||||
* makes sense. The drivers cannot rely on device interrupt numbers.
|
||||
*
|
||||
* ipc_intr_cypipeConfig.intrSrc = (IRQn_Type)(cpuss_interrupts_ipc_0_IRQn + epConfigDataA.ipcNotifierNumber);
|
||||
*
|
||||
* The driver has to be changed to not access the interrupt vectors directly.
|
||||
* This is a temporary workaround.
|
||||
*/
|
||||
#define cpuss_interrupts_ipc_0_IRQn 23
|
||||
|
||||
/*************** SYSCLK *****************/
|
||||
|
||||
/* Number of clock paths. Must be > 0 */
|
||||
#define SRSS_NUM_CLKPATH 5u
|
||||
/* Number of PLLs present. Must be <= NUM_CLKPATH */
|
||||
#define SRSS_NUM_PLL 1u
|
||||
/* Number of HFCLK roots present. Must be > 0 */
|
||||
#define SRSS_NUM_HFROOT 5u
|
||||
/* Number of 8.0 dividers */
|
||||
#define PERI_DIV_8_NR 8u
|
||||
/* Number of 16.0 dividers */
|
||||
#define PERI_DIV_16_NR 16u
|
||||
/* Number of 16.5 (fractional) dividers */
|
||||
#define PERI_DIV_16_5_NR 4u
|
||||
/* Number of 24.5 (fractional) dividers */
|
||||
#define PERI_DIV_24_5_NR 1u
|
||||
|
||||
|
||||
/**************** SMIF *****************/
|
||||
|
||||
/* SMIF_DEVICE_NR is used by Cy_SMIF_DeInit() to set all device CTL
|
||||
* register to 0. Not sure how it behaves if the FW attempts to access
|
||||
* nonexistent device registers */
|
||||
|
||||
/* Number of external devices supported ([1,4]) */
|
||||
#define SMIF_DEVICE_NR 4u
|
||||
|
||||
/**************** SAR ******************/
|
||||
|
||||
/* Number of SAR channels */
|
||||
#define PASS_SAR_SAR_CHANNELS 16u
|
||||
|
||||
/*************** PROFILE ****************/
|
||||
|
||||
/* This is used to define an internal static variable that keeps
|
||||
* control and status information for each counter.
|
||||
* static cy_stc_profile_ctr_t cy_ep_ctrs[PROFILE_PRFL_CNT_NR];
|
||||
* The size of cy_stc_profile_ctr_t is 36 bytes. To be device
|
||||
* independent the driver must assume the max number of counters
|
||||
* for the platform. This will waste (32-8)*36=864 bytes of RAM.
|
||||
*/
|
||||
|
||||
/* Number of profiling counters. Legal range [1, 32] */
|
||||
#define PROFILE_PRFL_CNT_NR 8u
|
||||
|
||||
/* Total count of Energy Profiler monitor signal connections */
|
||||
#define EP_MONITOR_COUNT 28u
|
||||
|
||||
/**************** GPIO *****************/
|
||||
|
||||
/* Number of ports in device */
|
||||
#define IOSS_GPIO_GPIO_PORT_NR 15u
|
||||
|
||||
/**************** FLASH *****************/
|
||||
|
||||
/* Page size in # of 32-bit words (1: 4 bytes, 2: 8 bytes, ... */
|
||||
#define CPUSS_FLASHC_PA_SIZE 128u
|
||||
|
||||
/* For now this is only used by Flash to update cy_Hfclk0FreqHz
|
||||
* variable in case the system clock settings were changed in FW
|
||||
* after startup.
|
||||
*/
|
||||
extern void SystemCoreClockUpdate(void);
|
||||
|
||||
/* This is frustrating... See Cy_Flash_Init() in cy_flash.c
|
||||
* The flash driver installs ISR into the vector table for silicon workaround.
|
||||
* We need to understand if the workaround is needed for other products
|
||||
* and then define how to handle this.
|
||||
*
|
||||
* This is a temporary hack to get a clean build.
|
||||
*/
|
||||
#define cpuss_interrupt_fm_IRQn ((IRQn_Type)85) /*!< 85 [Active] FLASH Macro Interrupt */
|
||||
|
||||
/* Flash also uses cy_Hfclk0FreqHz variable and SystemCoreClockUpdate()
|
||||
* function defined in system_psoc63_cm0plus.c that is project-specific startup
|
||||
* code.
|
||||
*/
|
||||
extern uint32_t cy_Hfclk0FreqHz;
|
||||
|
||||
#define CY_EM_EEPROM_BASE 0x14000000UL
|
||||
#define CY_EM_EEPROM_SIZE 0x00008000UL
|
||||
#define CY_SFLASH_BASE 0x16000000UL
|
||||
#define CY_SFLASH_SIZE 0x00008000UL
|
||||
|
||||
/* This is from the CM0+ System Startup. Used for flash workaround.
|
||||
* This must be either moved to the library or not used by the drivers. */
|
||||
#define CY_SYS_CM4_STATUS_ENABLED 3U
|
||||
extern uint32_t Cy_SysGetCM4Status(void);
|
||||
|
||||
/**************** CTDAC *****************/
|
||||
|
||||
/* CTDAC uses PCLK_PASS_CLOCK_CTDAC which is the element of a product-specific
|
||||
* enum (en_clk_dst_t) that describes clock connections for the device.
|
||||
* Why does CTDAC attempts to configure clocks? The drivers are not allowed to
|
||||
* configure platform resources!!! */
|
||||
|
||||
#define PCLK_PASS_CLOCK_CTDAC 55
|
||||
|
||||
/*************** CRYPTO *****************/
|
||||
|
||||
/* Crypto uses below defines to conditionally exclude the function
|
||||
* prototypes for unsupported features of the Crypto IP.
|
||||
* (by )of public header files. This check needs to be removed from the driver. */
|
||||
|
||||
/* Cryptography IP present or not (0=No, 1=Yes) */
|
||||
#define CPUSS_CRYPTO_PRESENT 1u/* AES cipher support (0 = no support, 1 = support */
|
||||
/* (Tripple) DES cipher support (0 = no support, 1 = support */
|
||||
#define CPUSS_CRYPTO_DES 1u
|
||||
/* Pseudo random number generation support (0 = no support, 1 = support) */
|
||||
#define CPUSS_CRYPTO_PR 1u
|
||||
/* SHA support included */
|
||||
#define CPUSS_CRYPTO_SHA 1u
|
||||
/* SHA1 hash support (0 = no support, 1 = support) */
|
||||
#define CPUSS_CRYPTO_SHA1 1u
|
||||
/* SHA256 hash support (0 = no support, 1 = support) */
|
||||
#define CPUSS_CRYPTO_SHA256 1u
|
||||
/* SHA512 hash support (0 = no support, 1 = support) */
|
||||
#define CPUSS_CRYPTO_SHA512 1u
|
||||
/* Cyclic Redundancy Check support (0 = no support, 1 = support) */
|
||||
#define CPUSS_CRYPTO_CRC 1u
|
||||
/* Vector unit support (0 = no support, 1 = support) */
|
||||
#define CPUSS_CRYPTO_VU 1u
|
||||
/* True random number generation support (0 = no support, 1 = support) */
|
||||
#define CPUSS_CRYPTO_TR 1u
|
||||
/* String support (0 = no support, 1 = support) */
|
||||
#define CPUSS_CRYPTO_STR 1u
|
||||
|
||||
/* We have to rethink the usage of config files for our drivers and
|
||||
* forbid any LLD to configure platform resources.
|
||||
*/
|
||||
#define cpuss_interrupt_crypto_IRQn 84
|
||||
#define NvicMux2_IRQn 2
|
||||
#define NvicMux30_IRQn 30
|
||||
#define NvicMux31_IRQn 31
|
||||
|
||||
|
||||
/*************** DW *****************/
|
||||
|
||||
/* DataWire 0 present or not (0=No, 1=Yes) */
|
||||
#define CPUSS_DW0_PRESENT 1u
|
||||
/* Number of DataWire 0 channels (8, 16 or 32) */
|
||||
#define CPUSS_DW0_CH_NR 16u
|
||||
/* DataWire 1 present or not (0=No, 1=Yes) */
|
||||
#define CPUSS_DW1_PRESENT 1u
|
||||
/* Number of DataWire 1 channels (8, 16 or 32) */
|
||||
#define CPUSS_DW1_CH_NR 16u
|
||||
|
||||
/*************** SCB *****************/
|
||||
|
||||
/* I don't know what to do about that!!!
|
||||
* Probably generate SCB descriptor structure in Flash
|
||||
* This however will require to convert the SCB address
|
||||
* to index. The SCB base addresses changes between
|
||||
* different products, so we will have to store the address
|
||||
* of SCB0 for each product as well. This is a kind of
|
||||
* overengineering... */
|
||||
|
||||
#define SCB_GET_EZ_DATA_NR(base) 256u
|
||||
#define SCB_IS_I2C_SLAVE_CAPABLE(base) true
|
||||
#define SCB_IS_I2C_MASTER_CAPABLE(base) ((base) != SCB8)
|
||||
#define SCB_IS_I2C_DS_CAPABLE(base) ((base) == SCB8)
|
||||
#define SCB_IS_SPI_SLAVE_CAPABLE(base) true
|
||||
#define SCB_IS_SPI_MASTER_CAPABLE(base) ((base) != SCB8)
|
||||
#define SCB_IS_SPI_DS_CAPABLE(base) ((base) == SCB8)
|
||||
#define SCB_IS_UART_CAPABLE(base) ((base) != SCB8)
|
||||
|
||||
/*************** SYSPM *****************/
|
||||
|
||||
#define CY_MMIO_UDB_GROUP_NR 3u
|
||||
#define CY_MMIO_UDB_SLAVE_NR 4u
|
||||
|
||||
/*************** SYSLIB *****************/
|
||||
|
||||
/* Ideally the SYSLIB must be changed to eliminate the
|
||||
* dependencies on the system startup variables.
|
||||
*/
|
||||
extern uint32_t cy_delayFreqKhz;
|
||||
extern uint8_t cy_delayFreqMhz;
|
||||
extern uint32_t cy_delay32kMs;
|
||||
|
||||
/************** SYSINT ******************/
|
||||
#define CY_IP_M4CPUSS_VERSION 1u
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* MPN-specific parameters
|
||||
*******************************************************************************/
|
||||
/* This comes from 001-91989 Marketing Part Definitions and is SW wounding
|
||||
* thing. Some MPNs have max frequency limit of 50 MHz. I don't think this
|
||||
* can be supported in a reasonable way and should always be set to max
|
||||
* supported by the platform.
|
||||
*/
|
||||
#define CY_HF_CLK_MAX_FREQ 150000000UL
|
||||
|
||||
/* Flash capacity is different per MPN */
|
||||
#define CY_FLASH_BASE 0x10000000UL
|
||||
#define CY_FLASH_SIZE 0x00100000UL
|
||||
|
||||
/* This seems to use wrong assumption. Need to clarify if it makes sense */
|
||||
#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL
|
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* SFLASH
|
||||
*******************************************************************************/
|
||||
|
||||
#define SFLASH_BASE 0x16000000UL
|
||||
#define SFLASH ((SFLASH_Type*) SFLASH_BASE) // Used by syslib, syspm, flash
|
||||
|
||||
/*******************************************************************************
|
||||
* PERI
|
||||
*******************************************************************************/
|
||||
|
||||
#define PERI_BASE 0x40010000UL
|
||||
#define PERI ((PERI_Type*) PERI_BASE) // Used by trigmux, sysclk, sysPm
|
||||
|
||||
/*******************************************************************************
|
||||
* CPUSS
|
||||
*******************************************************************************/
|
||||
|
||||
#define CPUSS_BASE 0x40210000UL
|
||||
#define CPUSS ((CPUSS_Type*) CPUSS_BASE) //Used by systick, syspm, syslib, sysint, sysclk, flash
|
||||
|
||||
/*******************************************************************************
|
||||
* IPC
|
||||
*******************************************************************************/
|
||||
|
||||
#define IPC_BASE 0x40230000UL
|
||||
#define IPC ((IPC_Type*) IPC_BASE)
|
||||
#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) // Used by syslib
|
||||
#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) // Used by syspm
|
||||
|
||||
/*******************************************************************************
|
||||
* PROT
|
||||
*******************************************************************************/
|
||||
|
||||
#define PROT_BASE 0x40240000UL
|
||||
#define PROT ((PROT_Type*) PROT_BASE) //Used by prot
|
||||
|
||||
/*******************************************************************************
|
||||
* FLASHC
|
||||
*******************************************************************************/
|
||||
|
||||
#define FLASHC_BASE 0x40250000UL
|
||||
#define FLASHC ((FLASHC_Type*) FLASHC_BASE) //used by syslib, flash
|
||||
#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) //used by syspm
|
||||
|
||||
/*******************************************************************************
|
||||
* SRSS
|
||||
*******************************************************************************/
|
||||
|
||||
#define SRSS_BASE 0x40260000UL
|
||||
#define SRSS ((SRSS_Type*) SRSS_BASE) //used by wdt, syspm, syslib, sysclk, lvd, lpcomp, flash
|
||||
|
||||
/*******************************************************************************
|
||||
* BACKUP
|
||||
*******************************************************************************/
|
||||
|
||||
#define BACKUP_BASE 0x40270000UL
|
||||
#define BACKUP ((BACKUP_Type*) BACKUP_BASE) //used by syspm, syslib, sysclk, rtc
|
||||
|
||||
/*******************************************************************************
|
||||
* DW
|
||||
*******************************************************************************/
|
||||
|
||||
#define DW0_BASE 0x40280000UL
|
||||
#define DW1_BASE 0x40281000UL
|
||||
#define DW0 ((DW_Type*) DW0_BASE) //used by dma
|
||||
#define DW1 ((DW_Type*) DW1_BASE) //used by dma
|
||||
|
||||
/*******************************************************************************
|
||||
* PROFILE
|
||||
*******************************************************************************/
|
||||
|
||||
#define PROFILE_BASE 0x402D0000UL
|
||||
#define PROFILE ((PROFILE_Type*) PROFILE_BASE) //used by profile
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* HSIOM
|
||||
*******************************************************************************/
|
||||
|
||||
#define HSIOM_BASE 0x40310000UL
|
||||
#define HSIOM ((HSIOM_Type*) HSIOM_BASE) //used by lpcomp, gpio
|
||||
|
||||
/*******************************************************************************
|
||||
* GPIO
|
||||
*******************************************************************************/
|
||||
|
||||
#define GPIO_BASE 0x40320000UL
|
||||
#define GPIO ((GPIO_Type*) GPIO_BASE) //used by GPIO
|
||||
|
||||
#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40320000 */
|
||||
#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40320080 */
|
||||
#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40320100 */
|
||||
#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40320180 */
|
||||
#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40320200 */
|
||||
#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40320280 */
|
||||
#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40320300 */
|
||||
#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40320380 */
|
||||
#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40320400 */
|
||||
#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40320480 */
|
||||
#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40320500 */
|
||||
#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40320580 */
|
||||
#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40320600 */
|
||||
#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40320680 */
|
||||
#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40320700 */
|
||||
|
||||
/*******************************************************************************
|
||||
* UDB
|
||||
*******************************************************************************/
|
||||
|
||||
#define UDB_BASE 0x40340000UL
|
||||
#define UDB ((UDB_Type*) UDB_BASE) //used by syspm
|
||||
|
||||
/*******************************************************************************
|
||||
* LPCOMP
|
||||
*******************************************************************************/
|
||||
|
||||
#define LPCOMP_BASE 0x40350000UL
|
||||
#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) //used by lpcomp (CDT302132)
|
||||
|
||||
/*******************************************************************************
|
||||
* SCB
|
||||
*******************************************************************************/
|
||||
|
||||
#define SCB8_BASE 0x40690000UL
|
||||
#define SCB8 ((CySCB_Type*) SCB8_BASE) //used by scb parameter validation
|
||||
|
||||
/*******************************************************************************
|
||||
* PASS
|
||||
*******************************************************************************/
|
||||
|
||||
#define PASS_BASE 0x411F0000UL
|
||||
#define PASS ((PASS_Type*) PASS_BASE) //used by sysanalog
|
||||
#define PASS_AREF ((PASS_AREF_Type*) &PASS->AREF) //used by sysanalog, CTB
|
||||
|
||||
/*******************************************************************************
|
||||
* BLE
|
||||
*******************************************************************************/
|
||||
|
||||
#define BLE_BASE 0x403C0000UL
|
||||
#define BLE ((BLE_Type*) BLE_BASE) /* 0x403C0000 */
|
||||
#define BLE_RCB_RCBLL ((BLE_RCB_RCBLL_Type*) &BLE->RCB.RCBLL) /* 0x403C0100 */
|
||||
#define BLE_RCB ((BLE_RCB_Type*) &BLE->RCB) /* 0x403C0000 */
|
||||
#define BLE_BLELL ((BLE_BLELL_Type*) &BLE->BLELL) /* 0x403C1000 */
|
||||
#define BLE_BLESS ((BLE_BLESS_Type*) &BLE->BLESS) /* 0x403DF000 */
|
||||
|
||||
#endif /* _CY_DEVICE_COMMON_H_ */
|
||||
|
||||
|
||||
/* [] END OF FILE */
|
||||
|
|
@ -1,112 +0,0 @@
|
|||
/***************************************************************************//**
|
||||
* \file cy_device_headers.h
|
||||
*
|
||||
* \brief
|
||||
* Common header file to be included by the drivers.
|
||||
*
|
||||
* \note
|
||||
* Generator version: 1.3.0.1146
|
||||
* Database revision: rev#1050929
|
||||
*
|
||||
********************************************************************************
|
||||
* \copyright
|
||||
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
|
||||
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _CY_DEVICE_HEADERS_H_
|
||||
#define _CY_DEVICE_HEADERS_H_
|
||||
|
||||
#if defined (CY8C6036BZI_F04)
|
||||
#include "cy8c6036bzi_f04.h"
|
||||
#elif defined (CY8C6016BZI_F04)
|
||||
#include "cy8c6016bzi_f04.h"
|
||||
#elif defined (CY8C6116BZI_F54)
|
||||
#include "cy8c6116bzi_f54.h"
|
||||
#elif defined (CY8C6136BZI_F14)
|
||||
#include "cy8c6136bzi_f14.h"
|
||||
#elif defined (CY8C6136BZI_F34)
|
||||
#include "cy8c6136bzi_f34.h"
|
||||
#elif defined (CY8C6137BZI_F14)
|
||||
#include "cy8c6137bzi_f14.h"
|
||||
#elif defined (CY8C6137BZI_F34)
|
||||
#include "cy8c6137bzi_f34.h"
|
||||
#elif defined (CY8C6137BZI_F54)
|
||||
#include "cy8c6137bzi_f54.h"
|
||||
#elif defined (CY8C6117BZI_F34)
|
||||
#include "cy8c6117bzi_f34.h"
|
||||
#elif defined (CY8C6246BZI_D04)
|
||||
#include "cy8c6246bzi_d04.h"
|
||||
#elif defined (CY8C6247BZI_D44)
|
||||
#include "cy8c6247bzi_d44.h"
|
||||
#elif defined (CY8C6247BZI_D34)
|
||||
#include "cy8c6247bzi_d34.h"
|
||||
#elif defined (CY8C6247BZI_D54)
|
||||
#include "cy8c6247bzi_d54.h"
|
||||
#elif defined (CY8C6336BZI_BLF03)
|
||||
#include "cy8c6336bzi_blf03.h"
|
||||
#elif defined (CY8C6316BZI_BLF03)
|
||||
#include "cy8c6316bzi_blf03.h"
|
||||
#elif defined (CY8C6316BZI_BLF53)
|
||||
#include "cy8c6316bzi_blf53.h"
|
||||
#elif defined (CY8C6336BZI_BLD13)
|
||||
#include "cy8c6336bzi_bld13.h"
|
||||
#elif defined (CY8C6347BZI_BLD43)
|
||||
#include "cy8c6347bzi_bld43.h"
|
||||
#elif defined (CY8C6347BZI_BLD33)
|
||||
#include "cy8c6347bzi_bld33.h"
|
||||
#elif defined (CY8C6347BZI_BLD53)
|
||||
#include "cy8c6347bzi_bld53.h"
|
||||
#elif defined (CY8C6347FMI_BLD13)
|
||||
#include "cy8c6347fmi_bld13.h"
|
||||
#elif defined (CY8C6347FMI_BLD43)
|
||||
#include "cy8c6347fmi_bld43.h"
|
||||
#elif defined (CY8C6347FMI_BLD33)
|
||||
#include "cy8c6347fmi_bld33.h"
|
||||
#elif defined (CY8C6347FMI_BLD53)
|
||||
#include "cy8c6347fmi_bld53.h"
|
||||
#elif defined (CY8C637BZI_MD76)
|
||||
#include "cy8c637bzi_md76.h"
|
||||
#elif defined (CY8C637BZI_BLD74)
|
||||
#include "cy8c637bzi_bld74.h"
|
||||
#elif defined (CY8C637FMI_BLD73)
|
||||
#include "cy8c637fmi_bld73.h"
|
||||
#elif defined (CY8C68237BZ_BLE)
|
||||
#include "cy8c68237bz_ble.h"
|
||||
#elif defined (CY8C68237FM_BLE)
|
||||
#include "cy8c68237fm_ble.h"
|
||||
#elif defined (CY8C6137FDI_F02)
|
||||
#include "cy8c6137fdi_f02.h"
|
||||
#elif defined (CY8C6117FDI_F02)
|
||||
#include "cy8c6117fdi_f02.h"
|
||||
#elif defined (CY8C6247FDI_D02)
|
||||
#include "cy8c6247fdi_d02.h"
|
||||
#elif defined (CY8C6247FDI_D32)
|
||||
#include "cy8c6247fdi_d32.h"
|
||||
#elif defined (CY8C6336BZI_BUD13)
|
||||
#include "cy8c6336bzi_bud13.h"
|
||||
#elif defined (CY8C6347BZI_BUD43)
|
||||
#include "cy8c6347bzi_bud43.h"
|
||||
#elif defined (CY8C6347BZI_BUD33)
|
||||
#include "cy8c6347bzi_bud33.h"
|
||||
#elif defined (CY8C6347BZI_BUD53)
|
||||
#include "cy8c6347bzi_bud53.h"
|
||||
#elif defined (CY8C6337BZI_BLF13)
|
||||
#include "cy8c6337bzi_blf13.h"
|
||||
#elif defined (CY8C6136FDI_F42)
|
||||
#include "cy8c6136fdi_f42.h"
|
||||
#elif defined (CY8C6247FDI_D52)
|
||||
#include "cy8c6247fdi_d52.h"
|
||||
#elif defined (PSoC6A2M_124BGA)
|
||||
#include "psoc6a2m_124bga.h"
|
||||
#else
|
||||
#include "cy_device_common.h"
|
||||
#endif
|
||||
|
||||
#endif /* _CY_DEVICE_HEADERS_H_ */
|
||||
|
||||
|
||||
/* [] END OF FILE */
|
||||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -1,226 +0,0 @@
|
|||
/***************************************************************************//**
|
||||
* \file cyip_backup.h
|
||||
*
|
||||
* \brief
|
||||
* BACKUP IP definitions
|
||||
*
|
||||
* \note
|
||||
* Generator version: 1.3.0.1146
|
||||
* Database revision: rev#1050929
|
||||
*
|
||||
********************************************************************************
|
||||
* \copyright
|
||||
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
|
||||
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _CYIP_BACKUP_H_
|
||||
#define _CYIP_BACKUP_H_
|
||||
|
||||
#include "cyip_headers.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* BACKUP
|
||||
*******************************************************************************/
|
||||
|
||||
#define BACKUP_SECTION_SIZE 0x00010000UL
|
||||
|
||||
/**
|
||||
* \brief SRSS Backup Domain (BACKUP)
|
||||
*/
|
||||
typedef struct {
|
||||
__IOM uint32_t CTL; /*!< 0x00000000 Control */
|
||||
__IM uint32_t RESERVED;
|
||||
__IOM uint32_t RTC_RW; /*!< 0x00000008 RTC Read Write register */
|
||||
__IOM uint32_t CAL_CTL; /*!< 0x0000000C Oscillator calibration for absolute frequency */
|
||||
__IM uint32_t STATUS; /*!< 0x00000010 Status */
|
||||
__IOM uint32_t RTC_TIME; /*!< 0x00000014 Calendar Seconds, Minutes, Hours, Day of Week */
|
||||
__IOM uint32_t RTC_DATE; /*!< 0x00000018 Calendar Day of Month, Month, Year */
|
||||
__IOM uint32_t ALM1_TIME; /*!< 0x0000001C Alarm 1 Seconds, Minute, Hours, Day of Week */
|
||||
__IOM uint32_t ALM1_DATE; /*!< 0x00000020 Alarm 1 Day of Month, Month */
|
||||
__IOM uint32_t ALM2_TIME; /*!< 0x00000024 Alarm 2 Seconds, Minute, Hours, Day of Week */
|
||||
__IOM uint32_t ALM2_DATE; /*!< 0x00000028 Alarm 2 Day of Month, Month */
|
||||
__IOM uint32_t INTR; /*!< 0x0000002C Interrupt request register */
|
||||
__IOM uint32_t INTR_SET; /*!< 0x00000030 Interrupt set request register */
|
||||
__IOM uint32_t INTR_MASK; /*!< 0x00000034 Interrupt mask register */
|
||||
__IM uint32_t INTR_MASKED; /*!< 0x00000038 Interrupt masked request register */
|
||||
__IM uint32_t OSCCNT; /*!< 0x0000003C 32kHz oscillator counter */
|
||||
__IM uint32_t TICKS; /*!< 0x00000040 128Hz tick counter */
|
||||
__IOM uint32_t PMIC_CTL; /*!< 0x00000044 PMIC control register */
|
||||
__IOM uint32_t RESET; /*!< 0x00000048 Backup reset register */
|
||||
__IM uint32_t RESERVED1[1005];
|
||||
__IOM uint32_t BREG[64]; /*!< 0x00001000 Backup register region */
|
||||
__IM uint32_t RESERVED2[15232];
|
||||
__IOM uint32_t TRIM; /*!< 0x0000FF00 Trim Register */
|
||||
} BACKUP_V1_Type; /*!< Size = 65284 (0xFF04) */
|
||||
|
||||
|
||||
/* BACKUP.CTL */
|
||||
#define BACKUP_CTL_WCO_EN_Pos 3UL
|
||||
#define BACKUP_CTL_WCO_EN_Msk 0x8UL
|
||||
#define BACKUP_CTL_CLK_SEL_Pos 8UL
|
||||
#define BACKUP_CTL_CLK_SEL_Msk 0x300UL
|
||||
#define BACKUP_CTL_PRESCALER_Pos 12UL
|
||||
#define BACKUP_CTL_PRESCALER_Msk 0x3000UL
|
||||
#define BACKUP_CTL_WCO_BYPASS_Pos 16UL
|
||||
#define BACKUP_CTL_WCO_BYPASS_Msk 0x10000UL
|
||||
#define BACKUP_CTL_VDDBAK_CTL_Pos 17UL
|
||||
#define BACKUP_CTL_VDDBAK_CTL_Msk 0x60000UL
|
||||
#define BACKUP_CTL_VBACKUP_MEAS_Pos 19UL
|
||||
#define BACKUP_CTL_VBACKUP_MEAS_Msk 0x80000UL
|
||||
#define BACKUP_CTL_EN_CHARGE_KEY_Pos 24UL
|
||||
#define BACKUP_CTL_EN_CHARGE_KEY_Msk 0xFF000000UL
|
||||
/* BACKUP.RTC_RW */
|
||||
#define BACKUP_RTC_RW_READ_Pos 0UL
|
||||
#define BACKUP_RTC_RW_READ_Msk 0x1UL
|
||||
#define BACKUP_RTC_RW_WRITE_Pos 1UL
|
||||
#define BACKUP_RTC_RW_WRITE_Msk 0x2UL
|
||||
/* BACKUP.CAL_CTL */
|
||||
#define BACKUP_CAL_CTL_CALIB_VAL_Pos 0UL
|
||||
#define BACKUP_CAL_CTL_CALIB_VAL_Msk 0x3FUL
|
||||
#define BACKUP_CAL_CTL_CALIB_SIGN_Pos 6UL
|
||||
#define BACKUP_CAL_CTL_CALIB_SIGN_Msk 0x40UL
|
||||
#define BACKUP_CAL_CTL_CAL_OUT_Pos 31UL
|
||||
#define BACKUP_CAL_CTL_CAL_OUT_Msk 0x80000000UL
|
||||
/* BACKUP.STATUS */
|
||||
#define BACKUP_STATUS_RTC_BUSY_Pos 0UL
|
||||
#define BACKUP_STATUS_RTC_BUSY_Msk 0x1UL
|
||||
#define BACKUP_STATUS_WCO_OK_Pos 2UL
|
||||
#define BACKUP_STATUS_WCO_OK_Msk 0x4UL
|
||||
/* BACKUP.RTC_TIME */
|
||||
#define BACKUP_RTC_TIME_RTC_SEC_Pos 0UL
|
||||
#define BACKUP_RTC_TIME_RTC_SEC_Msk 0x7FUL
|
||||
#define BACKUP_RTC_TIME_RTC_MIN_Pos 8UL
|
||||
#define BACKUP_RTC_TIME_RTC_MIN_Msk 0x7F00UL
|
||||
#define BACKUP_RTC_TIME_RTC_HOUR_Pos 16UL
|
||||
#define BACKUP_RTC_TIME_RTC_HOUR_Msk 0x3F0000UL
|
||||
#define BACKUP_RTC_TIME_CTRL_12HR_Pos 22UL
|
||||
#define BACKUP_RTC_TIME_CTRL_12HR_Msk 0x400000UL
|
||||
#define BACKUP_RTC_TIME_RTC_DAY_Pos 24UL
|
||||
#define BACKUP_RTC_TIME_RTC_DAY_Msk 0x7000000UL
|
||||
/* BACKUP.RTC_DATE */
|
||||
#define BACKUP_RTC_DATE_RTC_DATE_Pos 0UL
|
||||
#define BACKUP_RTC_DATE_RTC_DATE_Msk 0x3FUL
|
||||
#define BACKUP_RTC_DATE_RTC_MON_Pos 8UL
|
||||
#define BACKUP_RTC_DATE_RTC_MON_Msk 0x1F00UL
|
||||
#define BACKUP_RTC_DATE_RTC_YEAR_Pos 16UL
|
||||
#define BACKUP_RTC_DATE_RTC_YEAR_Msk 0xFF0000UL
|
||||
/* BACKUP.ALM1_TIME */
|
||||
#define BACKUP_ALM1_TIME_ALM_SEC_Pos 0UL
|
||||
#define BACKUP_ALM1_TIME_ALM_SEC_Msk 0x7FUL
|
||||
#define BACKUP_ALM1_TIME_ALM_SEC_EN_Pos 7UL
|
||||
#define BACKUP_ALM1_TIME_ALM_SEC_EN_Msk 0x80UL
|
||||
#define BACKUP_ALM1_TIME_ALM_MIN_Pos 8UL
|
||||
#define BACKUP_ALM1_TIME_ALM_MIN_Msk 0x7F00UL
|
||||
#define BACKUP_ALM1_TIME_ALM_MIN_EN_Pos 15UL
|
||||
#define BACKUP_ALM1_TIME_ALM_MIN_EN_Msk 0x8000UL
|
||||
#define BACKUP_ALM1_TIME_ALM_HOUR_Pos 16UL
|
||||
#define BACKUP_ALM1_TIME_ALM_HOUR_Msk 0x3F0000UL
|
||||
#define BACKUP_ALM1_TIME_ALM_HOUR_EN_Pos 23UL
|
||||
#define BACKUP_ALM1_TIME_ALM_HOUR_EN_Msk 0x800000UL
|
||||
#define BACKUP_ALM1_TIME_ALM_DAY_Pos 24UL
|
||||
#define BACKUP_ALM1_TIME_ALM_DAY_Msk 0x7000000UL
|
||||
#define BACKUP_ALM1_TIME_ALM_DAY_EN_Pos 31UL
|
||||
#define BACKUP_ALM1_TIME_ALM_DAY_EN_Msk 0x80000000UL
|
||||
/* BACKUP.ALM1_DATE */
|
||||
#define BACKUP_ALM1_DATE_ALM_DATE_Pos 0UL
|
||||
#define BACKUP_ALM1_DATE_ALM_DATE_Msk 0x3FUL
|
||||
#define BACKUP_ALM1_DATE_ALM_DATE_EN_Pos 7UL
|
||||
#define BACKUP_ALM1_DATE_ALM_DATE_EN_Msk 0x80UL
|
||||
#define BACKUP_ALM1_DATE_ALM_MON_Pos 8UL
|
||||
#define BACKUP_ALM1_DATE_ALM_MON_Msk 0x1F00UL
|
||||
#define BACKUP_ALM1_DATE_ALM_MON_EN_Pos 15UL
|
||||
#define BACKUP_ALM1_DATE_ALM_MON_EN_Msk 0x8000UL
|
||||
#define BACKUP_ALM1_DATE_ALM_EN_Pos 31UL
|
||||
#define BACKUP_ALM1_DATE_ALM_EN_Msk 0x80000000UL
|
||||
/* BACKUP.ALM2_TIME */
|
||||
#define BACKUP_ALM2_TIME_ALM_SEC_Pos 0UL
|
||||
#define BACKUP_ALM2_TIME_ALM_SEC_Msk 0x7FUL
|
||||
#define BACKUP_ALM2_TIME_ALM_SEC_EN_Pos 7UL
|
||||
#define BACKUP_ALM2_TIME_ALM_SEC_EN_Msk 0x80UL
|
||||
#define BACKUP_ALM2_TIME_ALM_MIN_Pos 8UL
|
||||
#define BACKUP_ALM2_TIME_ALM_MIN_Msk 0x7F00UL
|
||||
#define BACKUP_ALM2_TIME_ALM_MIN_EN_Pos 15UL
|
||||
#define BACKUP_ALM2_TIME_ALM_MIN_EN_Msk 0x8000UL
|
||||
#define BACKUP_ALM2_TIME_ALM_HOUR_Pos 16UL
|
||||
#define BACKUP_ALM2_TIME_ALM_HOUR_Msk 0x3F0000UL
|
||||
#define BACKUP_ALM2_TIME_ALM_HOUR_EN_Pos 23UL
|
||||
#define BACKUP_ALM2_TIME_ALM_HOUR_EN_Msk 0x800000UL
|
||||
#define BACKUP_ALM2_TIME_ALM_DAY_Pos 24UL
|
||||
#define BACKUP_ALM2_TIME_ALM_DAY_Msk 0x7000000UL
|
||||
#define BACKUP_ALM2_TIME_ALM_DAY_EN_Pos 31UL
|
||||
#define BACKUP_ALM2_TIME_ALM_DAY_EN_Msk 0x80000000UL
|
||||
/* BACKUP.ALM2_DATE */
|
||||
#define BACKUP_ALM2_DATE_ALM_DATE_Pos 0UL
|
||||
#define BACKUP_ALM2_DATE_ALM_DATE_Msk 0x3FUL
|
||||
#define BACKUP_ALM2_DATE_ALM_DATE_EN_Pos 7UL
|
||||
#define BACKUP_ALM2_DATE_ALM_DATE_EN_Msk 0x80UL
|
||||
#define BACKUP_ALM2_DATE_ALM_MON_Pos 8UL
|
||||
#define BACKUP_ALM2_DATE_ALM_MON_Msk 0x1F00UL
|
||||
#define BACKUP_ALM2_DATE_ALM_MON_EN_Pos 15UL
|
||||
#define BACKUP_ALM2_DATE_ALM_MON_EN_Msk 0x8000UL
|
||||
#define BACKUP_ALM2_DATE_ALM_EN_Pos 31UL
|
||||
#define BACKUP_ALM2_DATE_ALM_EN_Msk 0x80000000UL
|
||||
/* BACKUP.INTR */
|
||||
#define BACKUP_INTR_ALARM1_Pos 0UL
|
||||
#define BACKUP_INTR_ALARM1_Msk 0x1UL
|
||||
#define BACKUP_INTR_ALARM2_Pos 1UL
|
||||
#define BACKUP_INTR_ALARM2_Msk 0x2UL
|
||||
#define BACKUP_INTR_CENTURY_Pos 2UL
|
||||
#define BACKUP_INTR_CENTURY_Msk 0x4UL
|
||||
/* BACKUP.INTR_SET */
|
||||
#define BACKUP_INTR_SET_ALARM1_Pos 0UL
|
||||
#define BACKUP_INTR_SET_ALARM1_Msk 0x1UL
|
||||
#define BACKUP_INTR_SET_ALARM2_Pos 1UL
|
||||
#define BACKUP_INTR_SET_ALARM2_Msk 0x2UL
|
||||
#define BACKUP_INTR_SET_CENTURY_Pos 2UL
|
||||
#define BACKUP_INTR_SET_CENTURY_Msk 0x4UL
|
||||
/* BACKUP.INTR_MASK */
|
||||
#define BACKUP_INTR_MASK_ALARM1_Pos 0UL
|
||||
#define BACKUP_INTR_MASK_ALARM1_Msk 0x1UL
|
||||
#define BACKUP_INTR_MASK_ALARM2_Pos 1UL
|
||||
#define BACKUP_INTR_MASK_ALARM2_Msk 0x2UL
|
||||
#define BACKUP_INTR_MASK_CENTURY_Pos 2UL
|
||||
#define BACKUP_INTR_MASK_CENTURY_Msk 0x4UL
|
||||
/* BACKUP.INTR_MASKED */
|
||||
#define BACKUP_INTR_MASKED_ALARM1_Pos 0UL
|
||||
#define BACKUP_INTR_MASKED_ALARM1_Msk 0x1UL
|
||||
#define BACKUP_INTR_MASKED_ALARM2_Pos 1UL
|
||||
#define BACKUP_INTR_MASKED_ALARM2_Msk 0x2UL
|
||||
#define BACKUP_INTR_MASKED_CENTURY_Pos 2UL
|
||||
#define BACKUP_INTR_MASKED_CENTURY_Msk 0x4UL
|
||||
/* BACKUP.OSCCNT */
|
||||
#define BACKUP_OSCCNT_CNT32KHZ_Pos 0UL
|
||||
#define BACKUP_OSCCNT_CNT32KHZ_Msk 0xFFUL
|
||||
/* BACKUP.TICKS */
|
||||
#define BACKUP_TICKS_CNT128HZ_Pos 0UL
|
||||
#define BACKUP_TICKS_CNT128HZ_Msk 0x3FUL
|
||||
/* BACKUP.PMIC_CTL */
|
||||
#define BACKUP_PMIC_CTL_UNLOCK_Pos 8UL
|
||||
#define BACKUP_PMIC_CTL_UNLOCK_Msk 0xFF00UL
|
||||
#define BACKUP_PMIC_CTL_POLARITY_Pos 16UL
|
||||
#define BACKUP_PMIC_CTL_POLARITY_Msk 0x10000UL
|
||||
#define BACKUP_PMIC_CTL_PMIC_EN_OUTEN_Pos 29UL
|
||||
#define BACKUP_PMIC_CTL_PMIC_EN_OUTEN_Msk 0x20000000UL
|
||||
#define BACKUP_PMIC_CTL_PMIC_ALWAYSEN_Pos 30UL
|
||||
#define BACKUP_PMIC_CTL_PMIC_ALWAYSEN_Msk 0x40000000UL
|
||||
#define BACKUP_PMIC_CTL_PMIC_EN_Pos 31UL
|
||||
#define BACKUP_PMIC_CTL_PMIC_EN_Msk 0x80000000UL
|
||||
/* BACKUP.RESET */
|
||||
#define BACKUP_RESET_RESET_Pos 31UL
|
||||
#define BACKUP_RESET_RESET_Msk 0x80000000UL
|
||||
/* BACKUP.BREG */
|
||||
#define BACKUP_BREG_BREG_Pos 0UL
|
||||
#define BACKUP_BREG_BREG_Msk 0xFFFFFFFFUL
|
||||
/* BACKUP.TRIM */
|
||||
#define BACKUP_TRIM_TRIM_Pos 0UL
|
||||
#define BACKUP_TRIM_TRIM_Msk 0x3FUL
|
||||
|
||||
|
||||
#endif /* _CYIP_BACKUP_H_ */
|
||||
|
||||
|
||||
/* [] END OF FILE */
|
||||
File diff suppressed because it is too large
Load diff
|
|
@ -1,333 +0,0 @@
|
|||
/***************************************************************************//**
|
||||
* \file cyip_cpuss.h
|
||||
*
|
||||
* \brief
|
||||
* CPUSS IP definitions
|
||||
*
|
||||
* \note
|
||||
* Generator version: 1.3.0.1146
|
||||
* Database revision: rev#1050929
|
||||
*
|
||||
********************************************************************************
|
||||
* \copyright
|
||||
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
|
||||
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _CYIP_CPUSS_H_
|
||||
#define _CYIP_CPUSS_H_
|
||||
|
||||
#include "cyip_headers.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* CPUSS
|
||||
*******************************************************************************/
|
||||
|
||||
#define CPUSS_SECTION_SIZE 0x00010000UL
|
||||
|
||||
/**
|
||||
* \brief CPU subsystem (CPUSS) (CPUSS)
|
||||
*/
|
||||
typedef struct {
|
||||
__IOM uint32_t CM0_CTL; /*!< 0x00000000 CM0+ control */
|
||||
__IM uint32_t RESERVED;
|
||||
__IM uint32_t CM0_STATUS; /*!< 0x00000008 CM0+ status */
|
||||
__IM uint32_t RESERVED1;
|
||||
__IOM uint32_t CM0_CLOCK_CTL; /*!< 0x00000010 CM0+ clock control */
|
||||
__IM uint32_t RESERVED2[3];
|
||||
__IOM uint32_t CM0_INT_CTL0; /*!< 0x00000020 CM0+ interrupt control 0 */
|
||||
__IOM uint32_t CM0_INT_CTL1; /*!< 0x00000024 CM0+ interrupt control 1 */
|
||||
__IOM uint32_t CM0_INT_CTL2; /*!< 0x00000028 CM0+ interrupt control 2 */
|
||||
__IOM uint32_t CM0_INT_CTL3; /*!< 0x0000002C CM0+ interrupt control 3 */
|
||||
__IOM uint32_t CM0_INT_CTL4; /*!< 0x00000030 CM0+ interrupt control 4 */
|
||||
__IOM uint32_t CM0_INT_CTL5; /*!< 0x00000034 CM0+ interrupt control 5 */
|
||||
__IOM uint32_t CM0_INT_CTL6; /*!< 0x00000038 CM0+ interrupt control 6 */
|
||||
__IOM uint32_t CM0_INT_CTL7; /*!< 0x0000003C CM0+ interrupt control 7 */
|
||||
__IM uint32_t RESERVED3[16];
|
||||
__IOM uint32_t CM4_PWR_CTL; /*!< 0x00000080 CM4 power control */
|
||||
__IOM uint32_t CM4_PWR_DELAY_CTL; /*!< 0x00000084 CM4 power control */
|
||||
__IM uint32_t CM4_STATUS; /*!< 0x00000088 CM4 status */
|
||||
__IM uint32_t RESERVED4;
|
||||
__IOM uint32_t CM4_CLOCK_CTL; /*!< 0x00000090 CM4 clock control */
|
||||
__IM uint32_t RESERVED5[3];
|
||||
__IOM uint32_t CM4_NMI_CTL; /*!< 0x000000A0 CM4 NMI control */
|
||||
__IM uint32_t RESERVED6[23];
|
||||
__IOM uint32_t RAM0_CTL0; /*!< 0x00000100 RAM 0 control 0 */
|
||||
__IM uint32_t RESERVED7[15];
|
||||
__IOM uint32_t RAM0_PWR_MACRO_CTL[16]; /*!< 0x00000140 RAM 0 power control */
|
||||
__IOM uint32_t RAM1_CTL0; /*!< 0x00000180 RAM 1 control 0 */
|
||||
__IM uint32_t RESERVED8[3];
|
||||
__IOM uint32_t RAM1_PWR_CTL; /*!< 0x00000190 RAM1 power control */
|
||||
__IM uint32_t RESERVED9[3];
|
||||
__IOM uint32_t RAM2_CTL0; /*!< 0x000001A0 RAM 2 control 0 */
|
||||
__IM uint32_t RESERVED10[3];
|
||||
__IOM uint32_t RAM2_PWR_CTL; /*!< 0x000001B0 RAM2 power control */
|
||||
__IM uint32_t RESERVED11[3];
|
||||
__IOM uint32_t RAM_PWR_DELAY_CTL; /*!< 0x000001C0 Power up delay used for all SRAM power domains */
|
||||
__IM uint32_t RESERVED12[3];
|
||||
__IOM uint32_t ROM_CTL; /*!< 0x000001D0 ROM control */
|
||||
__IM uint32_t RESERVED13[7];
|
||||
__IOM uint32_t UDB_PWR_CTL; /*!< 0x000001F0 UDB power control */
|
||||
__IOM uint32_t UDB_PWR_DELAY_CTL; /*!< 0x000001F4 UDB power control */
|
||||
__IM uint32_t RESERVED14[4];
|
||||
__IM uint32_t DP_STATUS; /*!< 0x00000208 Debug port status */
|
||||
__IM uint32_t RESERVED15[5];
|
||||
__IOM uint32_t BUFF_CTL; /*!< 0x00000220 Buffer control */
|
||||
__IM uint32_t RESERVED16[3];
|
||||
__IOM uint32_t DDFT_CTL; /*!< 0x00000230 DDFT control */
|
||||
__IM uint32_t RESERVED17[3];
|
||||
__IOM uint32_t SYSTICK_CTL; /*!< 0x00000240 SysTick timer control */
|
||||
__IM uint32_t RESERVED18[27];
|
||||
__IOM uint32_t CM0_VECTOR_TABLE_BASE; /*!< 0x000002B0 CM0+ vector table base */
|
||||
__IM uint32_t RESERVED19[3];
|
||||
__IOM uint32_t CM4_VECTOR_TABLE_BASE; /*!< 0x000002C0 CM4 vector table base */
|
||||
__IM uint32_t RESERVED20[23];
|
||||
__IOM uint32_t CM0_PC0_HANDLER; /*!< 0x00000320 CM0+ protection context 0 handler */
|
||||
__IM uint32_t RESERVED21[55];
|
||||
__IM uint32_t IDENTITY; /*!< 0x00000400 Identity */
|
||||
__IM uint32_t RESERVED22[63];
|
||||
__IOM uint32_t PROTECTION; /*!< 0x00000500 Protection status */
|
||||
__IM uint32_t RESERVED23[7];
|
||||
__IOM uint32_t CM0_NMI_CTL; /*!< 0x00000520 CM0+ NMI control */
|
||||
__IM uint32_t RESERVED24[31];
|
||||
__IM uint32_t MBIST_STAT; /*!< 0x000005A0 Memory BIST status */
|
||||
__IM uint32_t RESERVED25[14999];
|
||||
__IOM uint32_t TRIM_ROM_CTL; /*!< 0x0000F000 ROM trim control */
|
||||
__IOM uint32_t TRIM_RAM_CTL; /*!< 0x0000F004 RAM trim control */
|
||||
} CPUSS_V1_Type; /*!< Size = 61448 (0xF008) */
|
||||
|
||||
|
||||
/* CPUSS.CM0_CTL */
|
||||
#define CPUSS_CM0_CTL_SLV_STALL_Pos 0UL
|
||||
#define CPUSS_CM0_CTL_SLV_STALL_Msk 0x1UL
|
||||
#define CPUSS_CM0_CTL_ENABLED_Pos 1UL
|
||||
#define CPUSS_CM0_CTL_ENABLED_Msk 0x2UL
|
||||
#define CPUSS_CM0_CTL_VECTKEYSTAT_Pos 16UL
|
||||
#define CPUSS_CM0_CTL_VECTKEYSTAT_Msk 0xFFFF0000UL
|
||||
/* CPUSS.CM0_STATUS */
|
||||
#define CPUSS_CM0_STATUS_SLEEPING_Pos 0UL
|
||||
#define CPUSS_CM0_STATUS_SLEEPING_Msk 0x1UL
|
||||
#define CPUSS_CM0_STATUS_SLEEPDEEP_Pos 1UL
|
||||
#define CPUSS_CM0_STATUS_SLEEPDEEP_Msk 0x2UL
|
||||
/* CPUSS.CM0_CLOCK_CTL */
|
||||
#define CPUSS_CM0_CLOCK_CTL_SLOW_INT_DIV_Pos 8UL
|
||||
#define CPUSS_CM0_CLOCK_CTL_SLOW_INT_DIV_Msk 0xFF00UL
|
||||
#define CPUSS_CM0_CLOCK_CTL_PERI_INT_DIV_Pos 24UL
|
||||
#define CPUSS_CM0_CLOCK_CTL_PERI_INT_DIV_Msk 0xFF000000UL
|
||||
/* CPUSS.CM0_INT_CTL0 */
|
||||
#define CPUSS_CM0_INT_CTL0_MUX0_SEL_Pos 0UL
|
||||
#define CPUSS_CM0_INT_CTL0_MUX0_SEL_Msk 0xFFUL
|
||||
#define CPUSS_CM0_INT_CTL0_MUX1_SEL_Pos 8UL
|
||||
#define CPUSS_CM0_INT_CTL0_MUX1_SEL_Msk 0xFF00UL
|
||||
#define CPUSS_CM0_INT_CTL0_MUX2_SEL_Pos 16UL
|
||||
#define CPUSS_CM0_INT_CTL0_MUX2_SEL_Msk 0xFF0000UL
|
||||
#define CPUSS_CM0_INT_CTL0_MUX3_SEL_Pos 24UL
|
||||
#define CPUSS_CM0_INT_CTL0_MUX3_SEL_Msk 0xFF000000UL
|
||||
/* CPUSS.CM0_INT_CTL1 */
|
||||
#define CPUSS_CM0_INT_CTL1_MUX0_SEL_Pos 0UL
|
||||
#define CPUSS_CM0_INT_CTL1_MUX0_SEL_Msk 0xFFUL
|
||||
#define CPUSS_CM0_INT_CTL1_MUX1_SEL_Pos 8UL
|
||||
#define CPUSS_CM0_INT_CTL1_MUX1_SEL_Msk 0xFF00UL
|
||||
#define CPUSS_CM0_INT_CTL1_MUX2_SEL_Pos 16UL
|
||||
#define CPUSS_CM0_INT_CTL1_MUX2_SEL_Msk 0xFF0000UL
|
||||
#define CPUSS_CM0_INT_CTL1_MUX3_SEL_Pos 24UL
|
||||
#define CPUSS_CM0_INT_CTL1_MUX3_SEL_Msk 0xFF000000UL
|
||||
/* CPUSS.CM0_INT_CTL2 */
|
||||
#define CPUSS_CM0_INT_CTL2_MUX0_SEL_Pos 0UL
|
||||
#define CPUSS_CM0_INT_CTL2_MUX0_SEL_Msk 0xFFUL
|
||||
#define CPUSS_CM0_INT_CTL2_MUX1_SEL_Pos 8UL
|
||||
#define CPUSS_CM0_INT_CTL2_MUX1_SEL_Msk 0xFF00UL
|
||||
#define CPUSS_CM0_INT_CTL2_MUX2_SEL_Pos 16UL
|
||||
#define CPUSS_CM0_INT_CTL2_MUX2_SEL_Msk 0xFF0000UL
|
||||
#define CPUSS_CM0_INT_CTL2_MUX3_SEL_Pos 24UL
|
||||
#define CPUSS_CM0_INT_CTL2_MUX3_SEL_Msk 0xFF000000UL
|
||||
/* CPUSS.CM0_INT_CTL3 */
|
||||
#define CPUSS_CM0_INT_CTL3_MUX0_SEL_Pos 0UL
|
||||
#define CPUSS_CM0_INT_CTL3_MUX0_SEL_Msk 0xFFUL
|
||||
#define CPUSS_CM0_INT_CTL3_MUX1_SEL_Pos 8UL
|
||||
#define CPUSS_CM0_INT_CTL3_MUX1_SEL_Msk 0xFF00UL
|
||||
#define CPUSS_CM0_INT_CTL3_MUX2_SEL_Pos 16UL
|
||||
#define CPUSS_CM0_INT_CTL3_MUX2_SEL_Msk 0xFF0000UL
|
||||
#define CPUSS_CM0_INT_CTL3_MUX3_SEL_Pos 24UL
|
||||
#define CPUSS_CM0_INT_CTL3_MUX3_SEL_Msk 0xFF000000UL
|
||||
/* CPUSS.CM0_INT_CTL4 */
|
||||
#define CPUSS_CM0_INT_CTL4_MUX0_SEL_Pos 0UL
|
||||
#define CPUSS_CM0_INT_CTL4_MUX0_SEL_Msk 0xFFUL
|
||||
#define CPUSS_CM0_INT_CTL4_MUX1_SEL_Pos 8UL
|
||||
#define CPUSS_CM0_INT_CTL4_MUX1_SEL_Msk 0xFF00UL
|
||||
#define CPUSS_CM0_INT_CTL4_MUX2_SEL_Pos 16UL
|
||||
#define CPUSS_CM0_INT_CTL4_MUX2_SEL_Msk 0xFF0000UL
|
||||
#define CPUSS_CM0_INT_CTL4_MUX3_SEL_Pos 24UL
|
||||
#define CPUSS_CM0_INT_CTL4_MUX3_SEL_Msk 0xFF000000UL
|
||||
/* CPUSS.CM0_INT_CTL5 */
|
||||
#define CPUSS_CM0_INT_CTL5_MUX0_SEL_Pos 0UL
|
||||
#define CPUSS_CM0_INT_CTL5_MUX0_SEL_Msk 0xFFUL
|
||||
#define CPUSS_CM0_INT_CTL5_MUX1_SEL_Pos 8UL
|
||||
#define CPUSS_CM0_INT_CTL5_MUX1_SEL_Msk 0xFF00UL
|
||||
#define CPUSS_CM0_INT_CTL5_MUX2_SEL_Pos 16UL
|
||||
#define CPUSS_CM0_INT_CTL5_MUX2_SEL_Msk 0xFF0000UL
|
||||
#define CPUSS_CM0_INT_CTL5_MUX3_SEL_Pos 24UL
|
||||
#define CPUSS_CM0_INT_CTL5_MUX3_SEL_Msk 0xFF000000UL
|
||||
/* CPUSS.CM0_INT_CTL6 */
|
||||
#define CPUSS_CM0_INT_CTL6_MUX0_SEL_Pos 0UL
|
||||
#define CPUSS_CM0_INT_CTL6_MUX0_SEL_Msk 0xFFUL
|
||||
#define CPUSS_CM0_INT_CTL6_MUX1_SEL_Pos 8UL
|
||||
#define CPUSS_CM0_INT_CTL6_MUX1_SEL_Msk 0xFF00UL
|
||||
#define CPUSS_CM0_INT_CTL6_MUX2_SEL_Pos 16UL
|
||||
#define CPUSS_CM0_INT_CTL6_MUX2_SEL_Msk 0xFF0000UL
|
||||
#define CPUSS_CM0_INT_CTL6_MUX3_SEL_Pos 24UL
|
||||
#define CPUSS_CM0_INT_CTL6_MUX3_SEL_Msk 0xFF000000UL
|
||||
/* CPUSS.CM0_INT_CTL7 */
|
||||
#define CPUSS_CM0_INT_CTL7_MUX0_SEL_Pos 0UL
|
||||
#define CPUSS_CM0_INT_CTL7_MUX0_SEL_Msk 0xFFUL
|
||||
#define CPUSS_CM0_INT_CTL7_MUX1_SEL_Pos 8UL
|
||||
#define CPUSS_CM0_INT_CTL7_MUX1_SEL_Msk 0xFF00UL
|
||||
#define CPUSS_CM0_INT_CTL7_MUX2_SEL_Pos 16UL
|
||||
#define CPUSS_CM0_INT_CTL7_MUX2_SEL_Msk 0xFF0000UL
|
||||
#define CPUSS_CM0_INT_CTL7_MUX3_SEL_Pos 24UL
|
||||
#define CPUSS_CM0_INT_CTL7_MUX3_SEL_Msk 0xFF000000UL
|
||||
/* CPUSS.CM4_PWR_CTL */
|
||||
#define CPUSS_CM4_PWR_CTL_PWR_MODE_Pos 0UL
|
||||
#define CPUSS_CM4_PWR_CTL_PWR_MODE_Msk 0x3UL
|
||||
#define CPUSS_CM4_PWR_CTL_VECTKEYSTAT_Pos 16UL
|
||||
#define CPUSS_CM4_PWR_CTL_VECTKEYSTAT_Msk 0xFFFF0000UL
|
||||
/* CPUSS.CM4_PWR_DELAY_CTL */
|
||||
#define CPUSS_CM4_PWR_DELAY_CTL_UP_Pos 0UL
|
||||
#define CPUSS_CM4_PWR_DELAY_CTL_UP_Msk 0x3FFUL
|
||||
/* CPUSS.CM4_STATUS */
|
||||
#define CPUSS_CM4_STATUS_SLEEPING_Pos 0UL
|
||||
#define CPUSS_CM4_STATUS_SLEEPING_Msk 0x1UL
|
||||
#define CPUSS_CM4_STATUS_SLEEPDEEP_Pos 1UL
|
||||
#define CPUSS_CM4_STATUS_SLEEPDEEP_Msk 0x2UL
|
||||
#define CPUSS_CM4_STATUS_PWR_DONE_Pos 4UL
|
||||
#define CPUSS_CM4_STATUS_PWR_DONE_Msk 0x10UL
|
||||
/* CPUSS.CM4_CLOCK_CTL */
|
||||
#define CPUSS_CM4_CLOCK_CTL_FAST_INT_DIV_Pos 8UL
|
||||
#define CPUSS_CM4_CLOCK_CTL_FAST_INT_DIV_Msk 0xFF00UL
|
||||
/* CPUSS.CM4_NMI_CTL */
|
||||
#define CPUSS_CM4_NMI_CTL_MUX0_SEL_Pos 0UL
|
||||
#define CPUSS_CM4_NMI_CTL_MUX0_SEL_Msk 0xFFUL
|
||||
/* CPUSS.RAM0_CTL0 */
|
||||
#define CPUSS_RAM0_CTL0_SLOW_WS_Pos 0UL
|
||||
#define CPUSS_RAM0_CTL0_SLOW_WS_Msk 0x3UL
|
||||
#define CPUSS_RAM0_CTL0_FAST_WS_Pos 8UL
|
||||
#define CPUSS_RAM0_CTL0_FAST_WS_Msk 0x300UL
|
||||
/* CPUSS.RAM0_PWR_MACRO_CTL */
|
||||
#define CPUSS_RAM0_PWR_MACRO_CTL_PWR_MODE_Pos 0UL
|
||||
#define CPUSS_RAM0_PWR_MACRO_CTL_PWR_MODE_Msk 0x3UL
|
||||
#define CPUSS_RAM0_PWR_MACRO_CTL_VECTKEYSTAT_Pos 16UL
|
||||
#define CPUSS_RAM0_PWR_MACRO_CTL_VECTKEYSTAT_Msk 0xFFFF0000UL
|
||||
/* CPUSS.RAM1_CTL0 */
|
||||
#define CPUSS_RAM1_CTL0_SLOW_WS_Pos 0UL
|
||||
#define CPUSS_RAM1_CTL0_SLOW_WS_Msk 0x3UL
|
||||
#define CPUSS_RAM1_CTL0_FAST_WS_Pos 8UL
|
||||
#define CPUSS_RAM1_CTL0_FAST_WS_Msk 0x300UL
|
||||
/* CPUSS.RAM1_PWR_CTL */
|
||||
#define CPUSS_RAM1_PWR_CTL_PWR_MODE_Pos 0UL
|
||||
#define CPUSS_RAM1_PWR_CTL_PWR_MODE_Msk 0x3UL
|
||||
#define CPUSS_RAM1_PWR_CTL_VECTKEYSTAT_Pos 16UL
|
||||
#define CPUSS_RAM1_PWR_CTL_VECTKEYSTAT_Msk 0xFFFF0000UL
|
||||
/* CPUSS.RAM2_CTL0 */
|
||||
#define CPUSS_RAM2_CTL0_SLOW_WS_Pos 0UL
|
||||
#define CPUSS_RAM2_CTL0_SLOW_WS_Msk 0x3UL
|
||||
#define CPUSS_RAM2_CTL0_FAST_WS_Pos 8UL
|
||||
#define CPUSS_RAM2_CTL0_FAST_WS_Msk 0x300UL
|
||||
/* CPUSS.RAM2_PWR_CTL */
|
||||
#define CPUSS_RAM2_PWR_CTL_PWR_MODE_Pos 0UL
|
||||
#define CPUSS_RAM2_PWR_CTL_PWR_MODE_Msk 0x3UL
|
||||
#define CPUSS_RAM2_PWR_CTL_VECTKEYSTAT_Pos 16UL
|
||||
#define CPUSS_RAM2_PWR_CTL_VECTKEYSTAT_Msk 0xFFFF0000UL
|
||||
/* CPUSS.RAM_PWR_DELAY_CTL */
|
||||
#define CPUSS_RAM_PWR_DELAY_CTL_UP_Pos 0UL
|
||||
#define CPUSS_RAM_PWR_DELAY_CTL_UP_Msk 0x3FFUL
|
||||
/* CPUSS.ROM_CTL */
|
||||
#define CPUSS_ROM_CTL_SLOW_WS_Pos 0UL
|
||||
#define CPUSS_ROM_CTL_SLOW_WS_Msk 0x3UL
|
||||
#define CPUSS_ROM_CTL_FAST_WS_Pos 8UL
|
||||
#define CPUSS_ROM_CTL_FAST_WS_Msk 0x300UL
|
||||
/* CPUSS.UDB_PWR_CTL */
|
||||
#define CPUSS_UDB_PWR_CTL_PWR_MODE_Pos 0UL
|
||||
#define CPUSS_UDB_PWR_CTL_PWR_MODE_Msk 0x3UL
|
||||
#define CPUSS_UDB_PWR_CTL_VECTKEYSTAT_Pos 16UL
|
||||
#define CPUSS_UDB_PWR_CTL_VECTKEYSTAT_Msk 0xFFFF0000UL
|
||||
/* CPUSS.UDB_PWR_DELAY_CTL */
|
||||
#define CPUSS_UDB_PWR_DELAY_CTL_UP_Pos 0UL
|
||||
#define CPUSS_UDB_PWR_DELAY_CTL_UP_Msk 0x3FFUL
|
||||
/* CPUSS.DP_STATUS */
|
||||
#define CPUSS_DP_STATUS_SWJ_CONNECTED_Pos 0UL
|
||||
#define CPUSS_DP_STATUS_SWJ_CONNECTED_Msk 0x1UL
|
||||
#define CPUSS_DP_STATUS_SWJ_DEBUG_EN_Pos 1UL
|
||||
#define CPUSS_DP_STATUS_SWJ_DEBUG_EN_Msk 0x2UL
|
||||
#define CPUSS_DP_STATUS_SWJ_JTAG_SEL_Pos 2UL
|
||||
#define CPUSS_DP_STATUS_SWJ_JTAG_SEL_Msk 0x4UL
|
||||
/* CPUSS.BUFF_CTL */
|
||||
#define CPUSS_BUFF_CTL_WRITE_BUFF_Pos 0UL
|
||||
#define CPUSS_BUFF_CTL_WRITE_BUFF_Msk 0x1UL
|
||||
/* CPUSS.DDFT_CTL */
|
||||
#define CPUSS_DDFT_CTL_DDFT_OUT0_SEL_Pos 0UL
|
||||
#define CPUSS_DDFT_CTL_DDFT_OUT0_SEL_Msk 0x1FUL
|
||||
#define CPUSS_DDFT_CTL_DDFT_OUT1_SEL_Pos 8UL
|
||||
#define CPUSS_DDFT_CTL_DDFT_OUT1_SEL_Msk 0x1F00UL
|
||||
/* CPUSS.SYSTICK_CTL */
|
||||
#define CPUSS_SYSTICK_CTL_TENMS_Pos 0UL
|
||||
#define CPUSS_SYSTICK_CTL_TENMS_Msk 0xFFFFFFUL
|
||||
#define CPUSS_SYSTICK_CTL_CLOCK_SOURCE_Pos 24UL
|
||||
#define CPUSS_SYSTICK_CTL_CLOCK_SOURCE_Msk 0x3000000UL
|
||||
#define CPUSS_SYSTICK_CTL_SKEW_Pos 30UL
|
||||
#define CPUSS_SYSTICK_CTL_SKEW_Msk 0x40000000UL
|
||||
#define CPUSS_SYSTICK_CTL_NOREF_Pos 31UL
|
||||
#define CPUSS_SYSTICK_CTL_NOREF_Msk 0x80000000UL
|
||||
/* CPUSS.CM0_VECTOR_TABLE_BASE */
|
||||
#define CPUSS_CM0_VECTOR_TABLE_BASE_ADDR24_Pos 8UL
|
||||
#define CPUSS_CM0_VECTOR_TABLE_BASE_ADDR24_Msk 0xFFFFFF00UL
|
||||
/* CPUSS.CM4_VECTOR_TABLE_BASE */
|
||||
#define CPUSS_CM4_VECTOR_TABLE_BASE_ADDR22_Pos 10UL
|
||||
#define CPUSS_CM4_VECTOR_TABLE_BASE_ADDR22_Msk 0xFFFFFC00UL
|
||||
/* CPUSS.CM0_PC0_HANDLER */
|
||||
#define CPUSS_CM0_PC0_HANDLER_ADDR_Pos 0UL
|
||||
#define CPUSS_CM0_PC0_HANDLER_ADDR_Msk 0xFFFFFFFFUL
|
||||
/* CPUSS.IDENTITY */
|
||||
#define CPUSS_IDENTITY_P_Pos 0UL
|
||||
#define CPUSS_IDENTITY_P_Msk 0x1UL
|
||||
#define CPUSS_IDENTITY_NS_Pos 1UL
|
||||
#define CPUSS_IDENTITY_NS_Msk 0x2UL
|
||||
#define CPUSS_IDENTITY_PC_Pos 4UL
|
||||
#define CPUSS_IDENTITY_PC_Msk 0xF0UL
|
||||
#define CPUSS_IDENTITY_MS_Pos 8UL
|
||||
#define CPUSS_IDENTITY_MS_Msk 0xF00UL
|
||||
/* CPUSS.PROTECTION */
|
||||
#define CPUSS_PROTECTION_STATE_Pos 0UL
|
||||
#define CPUSS_PROTECTION_STATE_Msk 0x7UL
|
||||
/* CPUSS.CM0_NMI_CTL */
|
||||
#define CPUSS_CM0_NMI_CTL_MUX0_SEL_Pos 0UL
|
||||
#define CPUSS_CM0_NMI_CTL_MUX0_SEL_Msk 0xFFUL
|
||||
/* CPUSS.MBIST_STAT */
|
||||
#define CPUSS_MBIST_STAT_SFP_READY_Pos 0UL
|
||||
#define CPUSS_MBIST_STAT_SFP_READY_Msk 0x1UL
|
||||
#define CPUSS_MBIST_STAT_SFP_FAIL_Pos 1UL
|
||||
#define CPUSS_MBIST_STAT_SFP_FAIL_Msk 0x2UL
|
||||
/* CPUSS.TRIM_ROM_CTL */
|
||||
#define CPUSS_TRIM_ROM_CTL_RM_Pos 0UL
|
||||
#define CPUSS_TRIM_ROM_CTL_RM_Msk 0xFUL
|
||||
#define CPUSS_TRIM_ROM_CTL_RME_Pos 4UL
|
||||
#define CPUSS_TRIM_ROM_CTL_RME_Msk 0x10UL
|
||||
/* CPUSS.TRIM_RAM_CTL */
|
||||
#define CPUSS_TRIM_RAM_CTL_RM_Pos 0UL
|
||||
#define CPUSS_TRIM_RAM_CTL_RM_Msk 0xFUL
|
||||
#define CPUSS_TRIM_RAM_CTL_RME_Pos 4UL
|
||||
#define CPUSS_TRIM_RAM_CTL_RME_Msk 0x10UL
|
||||
#define CPUSS_TRIM_RAM_CTL_WPULSE_Pos 5UL
|
||||
#define CPUSS_TRIM_RAM_CTL_WPULSE_Msk 0xE0UL
|
||||
#define CPUSS_TRIM_RAM_CTL_RA_Pos 8UL
|
||||
#define CPUSS_TRIM_RAM_CTL_RA_Msk 0x300UL
|
||||
#define CPUSS_TRIM_RAM_CTL_WA_Pos 12UL
|
||||
#define CPUSS_TRIM_RAM_CTL_WA_Msk 0x7000UL
|
||||
|
||||
|
||||
#endif /* _CYIP_CPUSS_H_ */
|
||||
|
||||
|
||||
/* [] END OF FILE */
|
||||
|
|
@ -1,425 +0,0 @@
|
|||
/***************************************************************************//**
|
||||
* \file cyip_cpuss_v2.h
|
||||
*
|
||||
* \brief
|
||||
* CPUSS IP definitions
|
||||
*
|
||||
* \note
|
||||
* Generator version: 1.3.0.1146
|
||||
* Database revision: rev#1050929
|
||||
*
|
||||
********************************************************************************
|
||||
* \copyright
|
||||
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
|
||||
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _CYIP_CPUSS_V2_H_
|
||||
#define _CYIP_CPUSS_V2_H_
|
||||
|
||||
#include "cyip_headers.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* CPUSS
|
||||
*******************************************************************************/
|
||||
|
||||
#define CPUSS_V2_SECTION_SIZE 0x00010000UL
|
||||
|
||||
/**
|
||||
* \brief CPU subsystem (CPUSS) (CPUSS)
|
||||
*/
|
||||
typedef struct {
|
||||
__IM uint32_t IDENTITY; /*!< 0x00000000 Identity */
|
||||
__IM uint32_t CM4_STATUS; /*!< 0x00000004 CM4 status */
|
||||
__IOM uint32_t CM4_CLOCK_CTL; /*!< 0x00000008 CM4 clock control */
|
||||
__IOM uint32_t CM4_CTL; /*!< 0x0000000C CM4 control */
|
||||
__IM uint32_t RESERVED[60];
|
||||
__IM uint32_t CM4_INT0_STATUS; /*!< 0x00000100 CM4 interrupt 0 status */
|
||||
__IM uint32_t CM4_INT1_STATUS; /*!< 0x00000104 CM4 interrupt 1 status */
|
||||
__IM uint32_t CM4_INT2_STATUS; /*!< 0x00000108 CM4 interrupt 2 status */
|
||||
__IM uint32_t CM4_INT3_STATUS; /*!< 0x0000010C CM4 interrupt 3 status */
|
||||
__IM uint32_t CM4_INT4_STATUS; /*!< 0x00000110 CM4 interrupt 4 status */
|
||||
__IM uint32_t CM4_INT5_STATUS; /*!< 0x00000114 CM4 interrupt 5 status */
|
||||
__IM uint32_t CM4_INT6_STATUS; /*!< 0x00000118 CM4 interrupt 6 status */
|
||||
__IM uint32_t CM4_INT7_STATUS; /*!< 0x0000011C CM4 interrupt 7 status */
|
||||
__IM uint32_t RESERVED1[56];
|
||||
__IOM uint32_t CM4_VECTOR_TABLE_BASE; /*!< 0x00000200 CM4 vector table base */
|
||||
__IM uint32_t RESERVED2[15];
|
||||
__IOM uint32_t CM4_NMI_CTL[4]; /*!< 0x00000240 CM4 NMI control */
|
||||
__IM uint32_t RESERVED3[44];
|
||||
__IOM uint32_t UDB_PWR_CTL; /*!< 0x00000300 UDB power control */
|
||||
__IOM uint32_t UDB_PWR_DELAY_CTL; /*!< 0x00000304 UDB power control */
|
||||
__IM uint32_t RESERVED4[830];
|
||||
__IOM uint32_t CM0_CTL; /*!< 0x00001000 CM0+ control */
|
||||
__IM uint32_t CM0_STATUS; /*!< 0x00001004 CM0+ status */
|
||||
__IOM uint32_t CM0_CLOCK_CTL; /*!< 0x00001008 CM0+ clock control */
|
||||
__IM uint32_t RESERVED5[61];
|
||||
__IM uint32_t CM0_INT0_STATUS; /*!< 0x00001100 CM0+ interrupt 0 status */
|
||||
__IM uint32_t CM0_INT1_STATUS; /*!< 0x00001104 CM0+ interrupt 1 status */
|
||||
__IM uint32_t CM0_INT2_STATUS; /*!< 0x00001108 CM0+ interrupt 2 status */
|
||||
__IM uint32_t CM0_INT3_STATUS; /*!< 0x0000110C CM0+ interrupt 3 status */
|
||||
__IM uint32_t CM0_INT4_STATUS; /*!< 0x00001110 CM0+ interrupt 4 status */
|
||||
__IM uint32_t CM0_INT5_STATUS; /*!< 0x00001114 CM0+ interrupt 5 status */
|
||||
__IM uint32_t CM0_INT6_STATUS; /*!< 0x00001118 CM0+ interrupt 6 status */
|
||||
__IM uint32_t CM0_INT7_STATUS; /*!< 0x0000111C CM0+ interrupt 7 status */
|
||||
__IOM uint32_t CM0_VECTOR_TABLE_BASE; /*!< 0x00001120 CM0+ vector table base */
|
||||
__IM uint32_t RESERVED6[7];
|
||||
__IOM uint32_t CM0_NMI_CTL[4]; /*!< 0x00001140 CM0+ NMI control */
|
||||
__IM uint32_t RESERVED7[44];
|
||||
__IOM uint32_t CM4_PWR_CTL; /*!< 0x00001200 CM4 power control */
|
||||
__IOM uint32_t CM4_PWR_DELAY_CTL; /*!< 0x00001204 CM4 power control */
|
||||
__IM uint32_t RESERVED8[62];
|
||||
__IOM uint32_t RAM0_CTL0; /*!< 0x00001300 RAM 0 control */
|
||||
__IM uint32_t RAM0_STATUS; /*!< 0x00001304 RAM 0 status */
|
||||
__IM uint32_t RESERVED9[14];
|
||||
__IOM uint32_t RAM0_PWR_MACRO_CTL[16]; /*!< 0x00001340 RAM 0 power control */
|
||||
__IOM uint32_t RAM1_CTL0; /*!< 0x00001380 RAM 1 control */
|
||||
__IM uint32_t RAM1_STATUS; /*!< 0x00001384 RAM 1 status */
|
||||
__IOM uint32_t RAM1_PWR_CTL; /*!< 0x00001388 RAM 1 power control */
|
||||
__IM uint32_t RESERVED10[5];
|
||||
__IOM uint32_t RAM2_CTL0; /*!< 0x000013A0 RAM 2 control */
|
||||
__IM uint32_t RAM2_STATUS; /*!< 0x000013A4 RAM 2 status */
|
||||
__IOM uint32_t RAM2_PWR_CTL; /*!< 0x000013A8 RAM 2 power control */
|
||||
__IM uint32_t RESERVED11[5];
|
||||
__IOM uint32_t RAM_PWR_DELAY_CTL; /*!< 0x000013C0 Power up delay used for all SRAM power domains */
|
||||
__IOM uint32_t ROM_CTL; /*!< 0x000013C4 ROM control */
|
||||
__IOM uint32_t ECC_CTL; /*!< 0x000013C8 ECC control */
|
||||
__IM uint32_t RESERVED12[13];
|
||||
__IM uint32_t PRODUCT_ID; /*!< 0x00001400 Product identifier and version (same as CoreSight RomTables) */
|
||||
__IM uint32_t RESERVED13[3];
|
||||
__IM uint32_t DP_STATUS; /*!< 0x00001410 Debug port status */
|
||||
__IM uint32_t RESERVED14[59];
|
||||
__IOM uint32_t BUFF_CTL; /*!< 0x00001500 Buffer control */
|
||||
__IM uint32_t RESERVED15[63];
|
||||
__IOM uint32_t SYSTICK_CTL; /*!< 0x00001600 SysTick timer control */
|
||||
__IM uint32_t RESERVED16[64];
|
||||
__IM uint32_t MBIST_STAT; /*!< 0x00001704 Memory BIST status */
|
||||
__IM uint32_t RESERVED17[62];
|
||||
__IOM uint32_t CAL_SUP_SET; /*!< 0x00001800 Calibration support set and read */
|
||||
__IOM uint32_t CAL_SUP_CLR; /*!< 0x00001804 Calibration support clear and reset */
|
||||
__IM uint32_t RESERVED18[510];
|
||||
__IOM uint32_t CM0_PC_CTL; /*!< 0x00002000 CM0+ protection context control */
|
||||
__IM uint32_t RESERVED19[15];
|
||||
__IOM uint32_t CM0_PC0_HANDLER; /*!< 0x00002040 CM0+ protection context 0 handler */
|
||||
__IOM uint32_t CM0_PC1_HANDLER; /*!< 0x00002044 CM0+ protection context 1 handler */
|
||||
__IOM uint32_t CM0_PC2_HANDLER; /*!< 0x00002048 CM0+ protection context 2 handler */
|
||||
__IOM uint32_t CM0_PC3_HANDLER; /*!< 0x0000204C CM0+ protection context 3 handler */
|
||||
__IM uint32_t RESERVED20[29];
|
||||
__IOM uint32_t PROTECTION; /*!< 0x000020C4 Protection status */
|
||||
__IM uint32_t RESERVED21[14];
|
||||
__IOM uint32_t TRIM_ROM_CTL; /*!< 0x00002100 ROM trim control */
|
||||
__IOM uint32_t TRIM_RAM_CTL; /*!< 0x00002104 RAM trim control */
|
||||
__IM uint32_t RESERVED22[6078];
|
||||
__IOM uint32_t CM0_SYSTEM_INT_CTL[1023]; /*!< 0x00008000 CM0+ system interrupt control */
|
||||
__IM uint32_t RESERVED23[1025];
|
||||
__IOM uint32_t CM4_SYSTEM_INT_CTL[1023]; /*!< 0x0000A000 CM4 system interrupt control */
|
||||
} CPUSS_V2_Type; /*!< Size = 45052 (0xAFFC) */
|
||||
|
||||
|
||||
/* CPUSS.IDENTITY */
|
||||
#define CPUSS_V2_IDENTITY_P_Pos 0UL
|
||||
#define CPUSS_V2_IDENTITY_P_Msk 0x1UL
|
||||
#define CPUSS_V2_IDENTITY_NS_Pos 1UL
|
||||
#define CPUSS_V2_IDENTITY_NS_Msk 0x2UL
|
||||
#define CPUSS_V2_IDENTITY_PC_Pos 4UL
|
||||
#define CPUSS_V2_IDENTITY_PC_Msk 0xF0UL
|
||||
#define CPUSS_V2_IDENTITY_MS_Pos 8UL
|
||||
#define CPUSS_V2_IDENTITY_MS_Msk 0xF00UL
|
||||
/* CPUSS.CM4_STATUS */
|
||||
#define CPUSS_V2_CM4_STATUS_SLEEPING_Pos 0UL
|
||||
#define CPUSS_V2_CM4_STATUS_SLEEPING_Msk 0x1UL
|
||||
#define CPUSS_V2_CM4_STATUS_SLEEPDEEP_Pos 1UL
|
||||
#define CPUSS_V2_CM4_STATUS_SLEEPDEEP_Msk 0x2UL
|
||||
#define CPUSS_V2_CM4_STATUS_PWR_DONE_Pos 4UL
|
||||
#define CPUSS_V2_CM4_STATUS_PWR_DONE_Msk 0x10UL
|
||||
/* CPUSS.CM4_CLOCK_CTL */
|
||||
#define CPUSS_V2_CM4_CLOCK_CTL_FAST_INT_DIV_Pos 8UL
|
||||
#define CPUSS_V2_CM4_CLOCK_CTL_FAST_INT_DIV_Msk 0xFF00UL
|
||||
/* CPUSS.CM4_CTL */
|
||||
#define CPUSS_V2_CM4_CTL_IOC_MASK_Pos 24UL
|
||||
#define CPUSS_V2_CM4_CTL_IOC_MASK_Msk 0x1000000UL
|
||||
#define CPUSS_V2_CM4_CTL_DZC_MASK_Pos 25UL
|
||||
#define CPUSS_V2_CM4_CTL_DZC_MASK_Msk 0x2000000UL
|
||||
#define CPUSS_V2_CM4_CTL_OFC_MASK_Pos 26UL
|
||||
#define CPUSS_V2_CM4_CTL_OFC_MASK_Msk 0x4000000UL
|
||||
#define CPUSS_V2_CM4_CTL_UFC_MASK_Pos 27UL
|
||||
#define CPUSS_V2_CM4_CTL_UFC_MASK_Msk 0x8000000UL
|
||||
#define CPUSS_V2_CM4_CTL_IXC_MASK_Pos 28UL
|
||||
#define CPUSS_V2_CM4_CTL_IXC_MASK_Msk 0x10000000UL
|
||||
#define CPUSS_V2_CM4_CTL_IDC_MASK_Pos 31UL
|
||||
#define CPUSS_V2_CM4_CTL_IDC_MASK_Msk 0x80000000UL
|
||||
/* CPUSS.CM4_INT0_STATUS */
|
||||
#define CPUSS_V2_CM4_INT0_STATUS_SYSTEM_INT_IDX_Pos 0UL
|
||||
#define CPUSS_V2_CM4_INT0_STATUS_SYSTEM_INT_IDX_Msk 0x3FFUL
|
||||
#define CPUSS_V2_CM4_INT0_STATUS_SYSTEM_INT_VALID_Pos 31UL
|
||||
#define CPUSS_V2_CM4_INT0_STATUS_SYSTEM_INT_VALID_Msk 0x80000000UL
|
||||
/* CPUSS.CM4_INT1_STATUS */
|
||||
#define CPUSS_V2_CM4_INT1_STATUS_SYSTEM_INT_IDX_Pos 0UL
|
||||
#define CPUSS_V2_CM4_INT1_STATUS_SYSTEM_INT_IDX_Msk 0x3FFUL
|
||||
#define CPUSS_V2_CM4_INT1_STATUS_SYSTEM_INT_VALID_Pos 31UL
|
||||
#define CPUSS_V2_CM4_INT1_STATUS_SYSTEM_INT_VALID_Msk 0x80000000UL
|
||||
/* CPUSS.CM4_INT2_STATUS */
|
||||
#define CPUSS_V2_CM4_INT2_STATUS_SYSTEM_INT_IDX_Pos 0UL
|
||||
#define CPUSS_V2_CM4_INT2_STATUS_SYSTEM_INT_IDX_Msk 0x3FFUL
|
||||
#define CPUSS_V2_CM4_INT2_STATUS_SYSTEM_INT_VALID_Pos 31UL
|
||||
#define CPUSS_V2_CM4_INT2_STATUS_SYSTEM_INT_VALID_Msk 0x80000000UL
|
||||
/* CPUSS.CM4_INT3_STATUS */
|
||||
#define CPUSS_V2_CM4_INT3_STATUS_SYSTEM_INT_IDX_Pos 0UL
|
||||
#define CPUSS_V2_CM4_INT3_STATUS_SYSTEM_INT_IDX_Msk 0x3FFUL
|
||||
#define CPUSS_V2_CM4_INT3_STATUS_SYSTEM_INT_VALID_Pos 31UL
|
||||
#define CPUSS_V2_CM4_INT3_STATUS_SYSTEM_INT_VALID_Msk 0x80000000UL
|
||||
/* CPUSS.CM4_INT4_STATUS */
|
||||
#define CPUSS_V2_CM4_INT4_STATUS_SYSTEM_INT_IDX_Pos 0UL
|
||||
#define CPUSS_V2_CM4_INT4_STATUS_SYSTEM_INT_IDX_Msk 0x3FFUL
|
||||
#define CPUSS_V2_CM4_INT4_STATUS_SYSTEM_INT_VALID_Pos 31UL
|
||||
#define CPUSS_V2_CM4_INT4_STATUS_SYSTEM_INT_VALID_Msk 0x80000000UL
|
||||
/* CPUSS.CM4_INT5_STATUS */
|
||||
#define CPUSS_V2_CM4_INT5_STATUS_SYSTEM_INT_IDX_Pos 0UL
|
||||
#define CPUSS_V2_CM4_INT5_STATUS_SYSTEM_INT_IDX_Msk 0x3FFUL
|
||||
#define CPUSS_V2_CM4_INT5_STATUS_SYSTEM_INT_VALID_Pos 31UL
|
||||
#define CPUSS_V2_CM4_INT5_STATUS_SYSTEM_INT_VALID_Msk 0x80000000UL
|
||||
/* CPUSS.CM4_INT6_STATUS */
|
||||
#define CPUSS_V2_CM4_INT6_STATUS_SYSTEM_INT_IDX_Pos 0UL
|
||||
#define CPUSS_V2_CM4_INT6_STATUS_SYSTEM_INT_IDX_Msk 0x3FFUL
|
||||
#define CPUSS_V2_CM4_INT6_STATUS_SYSTEM_INT_VALID_Pos 31UL
|
||||
#define CPUSS_V2_CM4_INT6_STATUS_SYSTEM_INT_VALID_Msk 0x80000000UL
|
||||
/* CPUSS.CM4_INT7_STATUS */
|
||||
#define CPUSS_V2_CM4_INT7_STATUS_SYSTEM_INT_IDX_Pos 0UL
|
||||
#define CPUSS_V2_CM4_INT7_STATUS_SYSTEM_INT_IDX_Msk 0x3FFUL
|
||||
#define CPUSS_V2_CM4_INT7_STATUS_SYSTEM_INT_VALID_Pos 31UL
|
||||
#define CPUSS_V2_CM4_INT7_STATUS_SYSTEM_INT_VALID_Msk 0x80000000UL
|
||||
/* CPUSS.CM4_VECTOR_TABLE_BASE */
|
||||
#define CPUSS_V2_CM4_VECTOR_TABLE_BASE_ADDR22_Pos 10UL
|
||||
#define CPUSS_V2_CM4_VECTOR_TABLE_BASE_ADDR22_Msk 0xFFFFFC00UL
|
||||
/* CPUSS.CM4_NMI_CTL */
|
||||
#define CPUSS_V2_CM4_NMI_CTL_SYSTEM_INT_IDX_Pos 0UL
|
||||
#define CPUSS_V2_CM4_NMI_CTL_SYSTEM_INT_IDX_Msk 0x3FFUL
|
||||
/* CPUSS.UDB_PWR_CTL */
|
||||
#define CPUSS_V2_UDB_PWR_CTL_PWR_MODE_Pos 0UL
|
||||
#define CPUSS_V2_UDB_PWR_CTL_PWR_MODE_Msk 0x3UL
|
||||
#define CPUSS_V2_UDB_PWR_CTL_VECTKEYSTAT_Pos 16UL
|
||||
#define CPUSS_V2_UDB_PWR_CTL_VECTKEYSTAT_Msk 0xFFFF0000UL
|
||||
/* CPUSS.UDB_PWR_DELAY_CTL */
|
||||
#define CPUSS_V2_UDB_PWR_DELAY_CTL_UP_Pos 0UL
|
||||
#define CPUSS_V2_UDB_PWR_DELAY_CTL_UP_Msk 0x3FFUL
|
||||
/* CPUSS.CM0_CTL */
|
||||
#define CPUSS_V2_CM0_CTL_SLV_STALL_Pos 0UL
|
||||
#define CPUSS_V2_CM0_CTL_SLV_STALL_Msk 0x1UL
|
||||
#define CPUSS_V2_CM0_CTL_ENABLED_Pos 1UL
|
||||
#define CPUSS_V2_CM0_CTL_ENABLED_Msk 0x2UL
|
||||
#define CPUSS_V2_CM0_CTL_VECTKEYSTAT_Pos 16UL
|
||||
#define CPUSS_V2_CM0_CTL_VECTKEYSTAT_Msk 0xFFFF0000UL
|
||||
/* CPUSS.CM0_STATUS */
|
||||
#define CPUSS_V2_CM0_STATUS_SLEEPING_Pos 0UL
|
||||
#define CPUSS_V2_CM0_STATUS_SLEEPING_Msk 0x1UL
|
||||
#define CPUSS_V2_CM0_STATUS_SLEEPDEEP_Pos 1UL
|
||||
#define CPUSS_V2_CM0_STATUS_SLEEPDEEP_Msk 0x2UL
|
||||
/* CPUSS.CM0_CLOCK_CTL */
|
||||
#define CPUSS_V2_CM0_CLOCK_CTL_SLOW_INT_DIV_Pos 8UL
|
||||
#define CPUSS_V2_CM0_CLOCK_CTL_SLOW_INT_DIV_Msk 0xFF00UL
|
||||
#define CPUSS_V2_CM0_CLOCK_CTL_PERI_INT_DIV_Pos 24UL
|
||||
#define CPUSS_V2_CM0_CLOCK_CTL_PERI_INT_DIV_Msk 0xFF000000UL
|
||||
/* CPUSS.CM0_INT0_STATUS */
|
||||
#define CPUSS_V2_CM0_INT0_STATUS_SYSTEM_INT_IDX_Pos 0UL
|
||||
#define CPUSS_V2_CM0_INT0_STATUS_SYSTEM_INT_IDX_Msk 0x3FFUL
|
||||
#define CPUSS_V2_CM0_INT0_STATUS_SYSTEM_INT_VALID_Pos 31UL
|
||||
#define CPUSS_V2_CM0_INT0_STATUS_SYSTEM_INT_VALID_Msk 0x80000000UL
|
||||
/* CPUSS.CM0_INT1_STATUS */
|
||||
#define CPUSS_V2_CM0_INT1_STATUS_SYSTEM_INT_IDX_Pos 0UL
|
||||
#define CPUSS_V2_CM0_INT1_STATUS_SYSTEM_INT_IDX_Msk 0x3FFUL
|
||||
#define CPUSS_V2_CM0_INT1_STATUS_SYSTEM_INT_VALID_Pos 31UL
|
||||
#define CPUSS_V2_CM0_INT1_STATUS_SYSTEM_INT_VALID_Msk 0x80000000UL
|
||||
/* CPUSS.CM0_INT2_STATUS */
|
||||
#define CPUSS_V2_CM0_INT2_STATUS_SYSTEM_INT_IDX_Pos 0UL
|
||||
#define CPUSS_V2_CM0_INT2_STATUS_SYSTEM_INT_IDX_Msk 0x3FFUL
|
||||
#define CPUSS_V2_CM0_INT2_STATUS_SYSTEM_INT_VALID_Pos 31UL
|
||||
#define CPUSS_V2_CM0_INT2_STATUS_SYSTEM_INT_VALID_Msk 0x80000000UL
|
||||
/* CPUSS.CM0_INT3_STATUS */
|
||||
#define CPUSS_V2_CM0_INT3_STATUS_SYSTEM_INT_IDX_Pos 0UL
|
||||
#define CPUSS_V2_CM0_INT3_STATUS_SYSTEM_INT_IDX_Msk 0x3FFUL
|
||||
#define CPUSS_V2_CM0_INT3_STATUS_SYSTEM_INT_VALID_Pos 31UL
|
||||
#define CPUSS_V2_CM0_INT3_STATUS_SYSTEM_INT_VALID_Msk 0x80000000UL
|
||||
/* CPUSS.CM0_INT4_STATUS */
|
||||
#define CPUSS_V2_CM0_INT4_STATUS_SYSTEM_INT_IDX_Pos 0UL
|
||||
#define CPUSS_V2_CM0_INT4_STATUS_SYSTEM_INT_IDX_Msk 0x3FFUL
|
||||
#define CPUSS_V2_CM0_INT4_STATUS_SYSTEM_INT_VALID_Pos 31UL
|
||||
#define CPUSS_V2_CM0_INT4_STATUS_SYSTEM_INT_VALID_Msk 0x80000000UL
|
||||
/* CPUSS.CM0_INT5_STATUS */
|
||||
#define CPUSS_V2_CM0_INT5_STATUS_SYSTEM_INT_IDX_Pos 0UL
|
||||
#define CPUSS_V2_CM0_INT5_STATUS_SYSTEM_INT_IDX_Msk 0x3FFUL
|
||||
#define CPUSS_V2_CM0_INT5_STATUS_SYSTEM_INT_VALID_Pos 31UL
|
||||
#define CPUSS_V2_CM0_INT5_STATUS_SYSTEM_INT_VALID_Msk 0x80000000UL
|
||||
/* CPUSS.CM0_INT6_STATUS */
|
||||
#define CPUSS_V2_CM0_INT6_STATUS_SYSTEM_INT_IDX_Pos 0UL
|
||||
#define CPUSS_V2_CM0_INT6_STATUS_SYSTEM_INT_IDX_Msk 0x3FFUL
|
||||
#define CPUSS_V2_CM0_INT6_STATUS_SYSTEM_INT_VALID_Pos 31UL
|
||||
#define CPUSS_V2_CM0_INT6_STATUS_SYSTEM_INT_VALID_Msk 0x80000000UL
|
||||
/* CPUSS.CM0_INT7_STATUS */
|
||||
#define CPUSS_V2_CM0_INT7_STATUS_SYSTEM_INT_IDX_Pos 0UL
|
||||
#define CPUSS_V2_CM0_INT7_STATUS_SYSTEM_INT_IDX_Msk 0x3FFUL
|
||||
#define CPUSS_V2_CM0_INT7_STATUS_SYSTEM_INT_VALID_Pos 31UL
|
||||
#define CPUSS_V2_CM0_INT7_STATUS_SYSTEM_INT_VALID_Msk 0x80000000UL
|
||||
/* CPUSS.CM0_VECTOR_TABLE_BASE */
|
||||
#define CPUSS_V2_CM0_VECTOR_TABLE_BASE_ADDR24_Pos 8UL
|
||||
#define CPUSS_V2_CM0_VECTOR_TABLE_BASE_ADDR24_Msk 0xFFFFFF00UL
|
||||
/* CPUSS.CM0_NMI_CTL */
|
||||
#define CPUSS_V2_CM0_NMI_CTL_SYSTEM_INT_IDX_Pos 0UL
|
||||
#define CPUSS_V2_CM0_NMI_CTL_SYSTEM_INT_IDX_Msk 0x3FFUL
|
||||
/* CPUSS.CM4_PWR_CTL */
|
||||
#define CPUSS_V2_CM4_PWR_CTL_PWR_MODE_Pos 0UL
|
||||
#define CPUSS_V2_CM4_PWR_CTL_PWR_MODE_Msk 0x3UL
|
||||
#define CPUSS_V2_CM4_PWR_CTL_VECTKEYSTAT_Pos 16UL
|
||||
#define CPUSS_V2_CM4_PWR_CTL_VECTKEYSTAT_Msk 0xFFFF0000UL
|
||||
/* CPUSS.CM4_PWR_DELAY_CTL */
|
||||
#define CPUSS_V2_CM4_PWR_DELAY_CTL_UP_Pos 0UL
|
||||
#define CPUSS_V2_CM4_PWR_DELAY_CTL_UP_Msk 0x3FFUL
|
||||
/* CPUSS.RAM0_CTL0 */
|
||||
#define CPUSS_V2_RAM0_CTL0_SLOW_WS_Pos 0UL
|
||||
#define CPUSS_V2_RAM0_CTL0_SLOW_WS_Msk 0x3UL
|
||||
#define CPUSS_V2_RAM0_CTL0_FAST_WS_Pos 8UL
|
||||
#define CPUSS_V2_RAM0_CTL0_FAST_WS_Msk 0x300UL
|
||||
#define CPUSS_V2_RAM0_CTL0_ECC_EN_Pos 16UL
|
||||
#define CPUSS_V2_RAM0_CTL0_ECC_EN_Msk 0x10000UL
|
||||
#define CPUSS_V2_RAM0_CTL0_ECC_AUTO_CORRECT_Pos 17UL
|
||||
#define CPUSS_V2_RAM0_CTL0_ECC_AUTO_CORRECT_Msk 0x20000UL
|
||||
#define CPUSS_V2_RAM0_CTL0_ECC_INJ_EN_Pos 18UL
|
||||
#define CPUSS_V2_RAM0_CTL0_ECC_INJ_EN_Msk 0x40000UL
|
||||
/* CPUSS.RAM0_STATUS */
|
||||
#define CPUSS_V2_RAM0_STATUS_WB_EMPTY_Pos 0UL
|
||||
#define CPUSS_V2_RAM0_STATUS_WB_EMPTY_Msk 0x1UL
|
||||
/* CPUSS.RAM0_PWR_MACRO_CTL */
|
||||
#define CPUSS_V2_RAM0_PWR_MACRO_CTL_PWR_MODE_Pos 0UL
|
||||
#define CPUSS_V2_RAM0_PWR_MACRO_CTL_PWR_MODE_Msk 0x3UL
|
||||
#define CPUSS_V2_RAM0_PWR_MACRO_CTL_VECTKEYSTAT_Pos 16UL
|
||||
#define CPUSS_V2_RAM0_PWR_MACRO_CTL_VECTKEYSTAT_Msk 0xFFFF0000UL
|
||||
/* CPUSS.RAM1_CTL0 */
|
||||
#define CPUSS_V2_RAM1_CTL0_SLOW_WS_Pos 0UL
|
||||
#define CPUSS_V2_RAM1_CTL0_SLOW_WS_Msk 0x3UL
|
||||
#define CPUSS_V2_RAM1_CTL0_FAST_WS_Pos 8UL
|
||||
#define CPUSS_V2_RAM1_CTL0_FAST_WS_Msk 0x300UL
|
||||
#define CPUSS_V2_RAM1_CTL0_ECC_EN_Pos 16UL
|
||||
#define CPUSS_V2_RAM1_CTL0_ECC_EN_Msk 0x10000UL
|
||||
#define CPUSS_V2_RAM1_CTL0_ECC_AUTO_CORRECT_Pos 17UL
|
||||
#define CPUSS_V2_RAM1_CTL0_ECC_AUTO_CORRECT_Msk 0x20000UL
|
||||
#define CPUSS_V2_RAM1_CTL0_ECC_INJ_EN_Pos 18UL
|
||||
#define CPUSS_V2_RAM1_CTL0_ECC_INJ_EN_Msk 0x40000UL
|
||||
/* CPUSS.RAM1_STATUS */
|
||||
#define CPUSS_V2_RAM1_STATUS_WB_EMPTY_Pos 0UL
|
||||
#define CPUSS_V2_RAM1_STATUS_WB_EMPTY_Msk 0x1UL
|
||||
/* CPUSS.RAM1_PWR_CTL */
|
||||
#define CPUSS_V2_RAM1_PWR_CTL_PWR_MODE_Pos 0UL
|
||||
#define CPUSS_V2_RAM1_PWR_CTL_PWR_MODE_Msk 0x3UL
|
||||
#define CPUSS_V2_RAM1_PWR_CTL_VECTKEYSTAT_Pos 16UL
|
||||
#define CPUSS_V2_RAM1_PWR_CTL_VECTKEYSTAT_Msk 0xFFFF0000UL
|
||||
/* CPUSS.RAM2_CTL0 */
|
||||
#define CPUSS_V2_RAM2_CTL0_SLOW_WS_Pos 0UL
|
||||
#define CPUSS_V2_RAM2_CTL0_SLOW_WS_Msk 0x3UL
|
||||
#define CPUSS_V2_RAM2_CTL0_FAST_WS_Pos 8UL
|
||||
#define CPUSS_V2_RAM2_CTL0_FAST_WS_Msk 0x300UL
|
||||
#define CPUSS_V2_RAM2_CTL0_ECC_EN_Pos 16UL
|
||||
#define CPUSS_V2_RAM2_CTL0_ECC_EN_Msk 0x10000UL
|
||||
#define CPUSS_V2_RAM2_CTL0_ECC_AUTO_CORRECT_Pos 17UL
|
||||
#define CPUSS_V2_RAM2_CTL0_ECC_AUTO_CORRECT_Msk 0x20000UL
|
||||
#define CPUSS_V2_RAM2_CTL0_ECC_INJ_EN_Pos 18UL
|
||||
#define CPUSS_V2_RAM2_CTL0_ECC_INJ_EN_Msk 0x40000UL
|
||||
/* CPUSS.RAM2_STATUS */
|
||||
#define CPUSS_V2_RAM2_STATUS_WB_EMPTY_Pos 0UL
|
||||
#define CPUSS_V2_RAM2_STATUS_WB_EMPTY_Msk 0x1UL
|
||||
/* CPUSS.RAM2_PWR_CTL */
|
||||
#define CPUSS_V2_RAM2_PWR_CTL_PWR_MODE_Pos 0UL
|
||||
#define CPUSS_V2_RAM2_PWR_CTL_PWR_MODE_Msk 0x3UL
|
||||
#define CPUSS_V2_RAM2_PWR_CTL_VECTKEYSTAT_Pos 16UL
|
||||
#define CPUSS_V2_RAM2_PWR_CTL_VECTKEYSTAT_Msk 0xFFFF0000UL
|
||||
/* CPUSS.RAM_PWR_DELAY_CTL */
|
||||
#define CPUSS_V2_RAM_PWR_DELAY_CTL_UP_Pos 0UL
|
||||
#define CPUSS_V2_RAM_PWR_DELAY_CTL_UP_Msk 0x3FFUL
|
||||
/* CPUSS.ROM_CTL */
|
||||
#define CPUSS_V2_ROM_CTL_SLOW_WS_Pos 0UL
|
||||
#define CPUSS_V2_ROM_CTL_SLOW_WS_Msk 0x3UL
|
||||
#define CPUSS_V2_ROM_CTL_FAST_WS_Pos 8UL
|
||||
#define CPUSS_V2_ROM_CTL_FAST_WS_Msk 0x300UL
|
||||
/* CPUSS.ECC_CTL */
|
||||
#define CPUSS_V2_ECC_CTL_WORD_ADDR_Pos 0UL
|
||||
#define CPUSS_V2_ECC_CTL_WORD_ADDR_Msk 0x1FFFFFFUL
|
||||
#define CPUSS_V2_ECC_CTL_PARITY_Pos 25UL
|
||||
#define CPUSS_V2_ECC_CTL_PARITY_Msk 0xFE000000UL
|
||||
/* CPUSS.PRODUCT_ID */
|
||||
#define CPUSS_V2_PRODUCT_ID_FAMILY_ID_Pos 0UL
|
||||
#define CPUSS_V2_PRODUCT_ID_FAMILY_ID_Msk 0xFFFUL
|
||||
#define CPUSS_V2_PRODUCT_ID_MAJOR_REV_Pos 16UL
|
||||
#define CPUSS_V2_PRODUCT_ID_MAJOR_REV_Msk 0xF0000UL
|
||||
#define CPUSS_V2_PRODUCT_ID_MINOR_REV_Pos 20UL
|
||||
#define CPUSS_V2_PRODUCT_ID_MINOR_REV_Msk 0xF00000UL
|
||||
/* CPUSS.DP_STATUS */
|
||||
#define CPUSS_V2_DP_STATUS_SWJ_CONNECTED_Pos 0UL
|
||||
#define CPUSS_V2_DP_STATUS_SWJ_CONNECTED_Msk 0x1UL
|
||||
#define CPUSS_V2_DP_STATUS_SWJ_DEBUG_EN_Pos 1UL
|
||||
#define CPUSS_V2_DP_STATUS_SWJ_DEBUG_EN_Msk 0x2UL
|
||||
#define CPUSS_V2_DP_STATUS_SWJ_JTAG_SEL_Pos 2UL
|
||||
#define CPUSS_V2_DP_STATUS_SWJ_JTAG_SEL_Msk 0x4UL
|
||||
/* CPUSS.BUFF_CTL */
|
||||
#define CPUSS_V2_BUFF_CTL_WRITE_BUFF_Pos 0UL
|
||||
#define CPUSS_V2_BUFF_CTL_WRITE_BUFF_Msk 0x1UL
|
||||
/* CPUSS.SYSTICK_CTL */
|
||||
#define CPUSS_V2_SYSTICK_CTL_TENMS_Pos 0UL
|
||||
#define CPUSS_V2_SYSTICK_CTL_TENMS_Msk 0xFFFFFFUL
|
||||
#define CPUSS_V2_SYSTICK_CTL_CLOCK_SOURCE_Pos 24UL
|
||||
#define CPUSS_V2_SYSTICK_CTL_CLOCK_SOURCE_Msk 0x3000000UL
|
||||
#define CPUSS_V2_SYSTICK_CTL_SKEW_Pos 30UL
|
||||
#define CPUSS_V2_SYSTICK_CTL_SKEW_Msk 0x40000000UL
|
||||
#define CPUSS_V2_SYSTICK_CTL_NOREF_Pos 31UL
|
||||
#define CPUSS_V2_SYSTICK_CTL_NOREF_Msk 0x80000000UL
|
||||
/* CPUSS.MBIST_STAT */
|
||||
#define CPUSS_V2_MBIST_STAT_SFP_READY_Pos 0UL
|
||||
#define CPUSS_V2_MBIST_STAT_SFP_READY_Msk 0x1UL
|
||||
#define CPUSS_V2_MBIST_STAT_SFP_FAIL_Pos 1UL
|
||||
#define CPUSS_V2_MBIST_STAT_SFP_FAIL_Msk 0x2UL
|
||||
/* CPUSS.CAL_SUP_SET */
|
||||
#define CPUSS_V2_CAL_SUP_SET_DATA_Pos 0UL
|
||||
#define CPUSS_V2_CAL_SUP_SET_DATA_Msk 0xFFFFFFFFUL
|
||||
/* CPUSS.CAL_SUP_CLR */
|
||||
#define CPUSS_V2_CAL_SUP_CLR_DATA_Pos 0UL
|
||||
#define CPUSS_V2_CAL_SUP_CLR_DATA_Msk 0xFFFFFFFFUL
|
||||
/* CPUSS.CM0_PC_CTL */
|
||||
#define CPUSS_V2_CM0_PC_CTL_VALID_Pos 0UL
|
||||
#define CPUSS_V2_CM0_PC_CTL_VALID_Msk 0xFUL
|
||||
/* CPUSS.CM0_PC0_HANDLER */
|
||||
#define CPUSS_V2_CM0_PC0_HANDLER_ADDR_Pos 0UL
|
||||
#define CPUSS_V2_CM0_PC0_HANDLER_ADDR_Msk 0xFFFFFFFFUL
|
||||
/* CPUSS.CM0_PC1_HANDLER */
|
||||
#define CPUSS_V2_CM0_PC1_HANDLER_ADDR_Pos 0UL
|
||||
#define CPUSS_V2_CM0_PC1_HANDLER_ADDR_Msk 0xFFFFFFFFUL
|
||||
/* CPUSS.CM0_PC2_HANDLER */
|
||||
#define CPUSS_V2_CM0_PC2_HANDLER_ADDR_Pos 0UL
|
||||
#define CPUSS_V2_CM0_PC2_HANDLER_ADDR_Msk 0xFFFFFFFFUL
|
||||
/* CPUSS.CM0_PC3_HANDLER */
|
||||
#define CPUSS_V2_CM0_PC3_HANDLER_ADDR_Pos 0UL
|
||||
#define CPUSS_V2_CM0_PC3_HANDLER_ADDR_Msk 0xFFFFFFFFUL
|
||||
/* CPUSS.PROTECTION */
|
||||
#define CPUSS_V2_PROTECTION_STATE_Pos 0UL
|
||||
#define CPUSS_V2_PROTECTION_STATE_Msk 0x7UL
|
||||
/* CPUSS.TRIM_ROM_CTL */
|
||||
#define CPUSS_V2_TRIM_ROM_CTL_TRIM_Pos 0UL
|
||||
#define CPUSS_V2_TRIM_ROM_CTL_TRIM_Msk 0xFFFFFFFFUL
|
||||
/* CPUSS.TRIM_RAM_CTL */
|
||||
#define CPUSS_V2_TRIM_RAM_CTL_TRIM_Pos 0UL
|
||||
#define CPUSS_V2_TRIM_RAM_CTL_TRIM_Msk 0xFFFFFFFFUL
|
||||
/* CPUSS.CM0_SYSTEM_INT_CTL */
|
||||
#define CPUSS_V2_CM0_SYSTEM_INT_CTL_CPU_INT_IDX_Pos 0UL
|
||||
#define CPUSS_V2_CM0_SYSTEM_INT_CTL_CPU_INT_IDX_Msk 0x7UL
|
||||
#define CPUSS_V2_CM0_SYSTEM_INT_CTL_CPU_INT_VALID_Pos 31UL
|
||||
#define CPUSS_V2_CM0_SYSTEM_INT_CTL_CPU_INT_VALID_Msk 0x80000000UL
|
||||
/* CPUSS.CM4_SYSTEM_INT_CTL */
|
||||
#define CPUSS_V2_CM4_SYSTEM_INT_CTL_CPU_INT_IDX_Pos 0UL
|
||||
#define CPUSS_V2_CM4_SYSTEM_INT_CTL_CPU_INT_IDX_Msk 0x7UL
|
||||
#define CPUSS_V2_CM4_SYSTEM_INT_CTL_CPU_INT_VALID_Pos 31UL
|
||||
#define CPUSS_V2_CM4_SYSTEM_INT_CTL_CPU_INT_VALID_Msk 0x80000000UL
|
||||
|
||||
|
||||
#endif /* _CYIP_CPUSS_V2_H_ */
|
||||
|
||||
|
||||
/* [] END OF FILE */
|
||||
|
|
@ -1,376 +0,0 @@
|
|||
/***************************************************************************//**
|
||||
* \file cyip_crypto.h
|
||||
*
|
||||
* \brief
|
||||
* CRYPTO IP definitions
|
||||
*
|
||||
* \note
|
||||
* Generator version: 1.3.0.1146
|
||||
* Database revision: rev#1050929
|
||||
*
|
||||
********************************************************************************
|
||||
* \copyright
|
||||
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
|
||||
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _CYIP_CRYPTO_H_
|
||||
#define _CYIP_CRYPTO_H_
|
||||
|
||||
#include "cyip_headers.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* CRYPTO
|
||||
*******************************************************************************/
|
||||
|
||||
#define CRYPTO_SECTION_SIZE 0x00010000UL
|
||||
|
||||
/**
|
||||
* \brief Cryptography component (CRYPTO)
|
||||
*/
|
||||
typedef struct {
|
||||
__IOM uint32_t CTL; /*!< 0x00000000 Control */
|
||||
__IM uint32_t STATUS; /*!< 0x00000004 Status */
|
||||
__IOM uint32_t RAM_PWRUP_DELAY; /*!< 0x00000008 Power up delay used for SRAM power domain */
|
||||
__IM uint32_t RESERVED[5];
|
||||
__IM uint32_t ERROR_STATUS0; /*!< 0x00000020 Error status 0 */
|
||||
__IOM uint32_t ERROR_STATUS1; /*!< 0x00000024 Error status 1 */
|
||||
__IM uint32_t RESERVED1[6];
|
||||
__IOM uint32_t INSTR_FF_CTL; /*!< 0x00000040 Instruction FIFO control */
|
||||
__IM uint32_t INSTR_FF_STATUS; /*!< 0x00000044 Instruction FIFO status */
|
||||
__OM uint32_t INSTR_FF_WR; /*!< 0x00000048 Instruction FIFO write */
|
||||
__IM uint32_t RESERVED2[13];
|
||||
__IM uint32_t RF_DATA[16]; /*!< 0x00000080 Register-file */
|
||||
__IM uint32_t RESERVED3[16];
|
||||
__IOM uint32_t AES_CTL; /*!< 0x00000100 AES control */
|
||||
__IM uint32_t RESERVED4[31];
|
||||
__IM uint32_t STR_RESULT; /*!< 0x00000180 String result */
|
||||
__IM uint32_t RESERVED5[31];
|
||||
__IOM uint32_t PR_LFSR_CTL0; /*!< 0x00000200 Pseudo random LFSR control 0 */
|
||||
__IOM uint32_t PR_LFSR_CTL1; /*!< 0x00000204 Pseudo random LFSR control 1 */
|
||||
__IOM uint32_t PR_LFSR_CTL2; /*!< 0x00000208 Pseudo random LFSR control 2 */
|
||||
__IM uint32_t RESERVED6;
|
||||
__IOM uint32_t PR_RESULT; /*!< 0x00000210 Pseudo random result */
|
||||
__IM uint32_t RESERVED7[27];
|
||||
__IOM uint32_t TR_CTL0; /*!< 0x00000280 True random control 0 */
|
||||
__IOM uint32_t TR_CTL1; /*!< 0x00000284 True random control 1 */
|
||||
__IOM uint32_t TR_RESULT; /*!< 0x00000288 True random result */
|
||||
__IM uint32_t RESERVED8[5];
|
||||
__IOM uint32_t TR_GARO_CTL; /*!< 0x000002A0 True random GARO control */
|
||||
__IOM uint32_t TR_FIRO_CTL; /*!< 0x000002A4 True random FIRO control */
|
||||
__IM uint32_t RESERVED9[6];
|
||||
__IOM uint32_t TR_MON_CTL; /*!< 0x000002C0 True random monitor control */
|
||||
__IM uint32_t RESERVED10;
|
||||
__IOM uint32_t TR_MON_CMD; /*!< 0x000002C8 True random monitor command */
|
||||
__IM uint32_t RESERVED11;
|
||||
__IOM uint32_t TR_MON_RC_CTL; /*!< 0x000002D0 True random monitor RC control */
|
||||
__IM uint32_t RESERVED12;
|
||||
__IM uint32_t TR_MON_RC_STATUS0; /*!< 0x000002D8 True random monitor RC status 0 */
|
||||
__IM uint32_t TR_MON_RC_STATUS1; /*!< 0x000002DC True random monitor RC status 1 */
|
||||
__IOM uint32_t TR_MON_AP_CTL; /*!< 0x000002E0 True random monitor AP control */
|
||||
__IM uint32_t RESERVED13;
|
||||
__IM uint32_t TR_MON_AP_STATUS0; /*!< 0x000002E8 True random monitor AP status 0 */
|
||||
__IM uint32_t TR_MON_AP_STATUS1; /*!< 0x000002EC True random monitor AP status 1 */
|
||||
__IM uint32_t RESERVED14[4];
|
||||
__IOM uint32_t SHA_CTL; /*!< 0x00000300 SHA control */
|
||||
__IM uint32_t RESERVED15[63];
|
||||
__IOM uint32_t CRC_CTL; /*!< 0x00000400 CRC control */
|
||||
__IM uint32_t RESERVED16[3];
|
||||
__IOM uint32_t CRC_DATA_CTL; /*!< 0x00000410 CRC data control */
|
||||
__IM uint32_t RESERVED17[3];
|
||||
__IOM uint32_t CRC_POL_CTL; /*!< 0x00000420 CRC polynomial control */
|
||||
__IM uint32_t RESERVED18[3];
|
||||
__IOM uint32_t CRC_LFSR_CTL; /*!< 0x00000430 CRC LFSR control */
|
||||
__IM uint32_t RESERVED19[3];
|
||||
__IOM uint32_t CRC_REM_CTL; /*!< 0x00000440 CRC remainder control */
|
||||
__IM uint32_t RESERVED20;
|
||||
__IM uint32_t CRC_REM_RESULT; /*!< 0x00000448 CRC remainder result */
|
||||
__IM uint32_t RESERVED21[13];
|
||||
__IOM uint32_t VU_CTL0; /*!< 0x00000480 Vector unit control 0 */
|
||||
__IOM uint32_t VU_CTL1; /*!< 0x00000484 Vector unit control 1 */
|
||||
__IM uint32_t RESERVED22[2];
|
||||
__IM uint32_t VU_STATUS; /*!< 0x00000490 Vector unit status */
|
||||
__IM uint32_t RESERVED23[203];
|
||||
__IOM uint32_t INTR; /*!< 0x000007C0 Interrupt register */
|
||||
__IOM uint32_t INTR_SET; /*!< 0x000007C4 Interrupt set register */
|
||||
__IOM uint32_t INTR_MASK; /*!< 0x000007C8 Interrupt mask register */
|
||||
__IM uint32_t INTR_MASKED; /*!< 0x000007CC Interrupt masked register */
|
||||
__IM uint32_t RESERVED24[3596];
|
||||
__IOM uint32_t MEM_BUFF[4096]; /*!< 0x00004000 Memory buffer */
|
||||
} CRYPTO_V1_Type; /*!< Size = 32768 (0x8000) */
|
||||
|
||||
|
||||
/* CRYPTO.CTL */
|
||||
#define CRYPTO_CTL_PWR_MODE_Pos 0UL
|
||||
#define CRYPTO_CTL_PWR_MODE_Msk 0x3UL
|
||||
#define CRYPTO_CTL_ENABLED_Pos 31UL
|
||||
#define CRYPTO_CTL_ENABLED_Msk 0x80000000UL
|
||||
/* CRYPTO.STATUS */
|
||||
#define CRYPTO_STATUS_AES_BUSY_Pos 0UL
|
||||
#define CRYPTO_STATUS_AES_BUSY_Msk 0x1UL
|
||||
#define CRYPTO_STATUS_DES_BUSY_Pos 1UL
|
||||
#define CRYPTO_STATUS_DES_BUSY_Msk 0x2UL
|
||||
#define CRYPTO_STATUS_SHA_BUSY_Pos 2UL
|
||||
#define CRYPTO_STATUS_SHA_BUSY_Msk 0x4UL
|
||||
#define CRYPTO_STATUS_CRC_BUSY_Pos 3UL
|
||||
#define CRYPTO_STATUS_CRC_BUSY_Msk 0x8UL
|
||||
#define CRYPTO_STATUS_STR_BUSY_Pos 4UL
|
||||
#define CRYPTO_STATUS_STR_BUSY_Msk 0x10UL
|
||||
#define CRYPTO_STATUS_PR_BUSY_Pos 5UL
|
||||
#define CRYPTO_STATUS_PR_BUSY_Msk 0x20UL
|
||||
#define CRYPTO_STATUS_TR_BUSY_Pos 6UL
|
||||
#define CRYPTO_STATUS_TR_BUSY_Msk 0x40UL
|
||||
#define CRYPTO_STATUS_VU_BUSY_Pos 7UL
|
||||
#define CRYPTO_STATUS_VU_BUSY_Msk 0x80UL
|
||||
#define CRYPTO_STATUS_CMD_FF_BUSY_Pos 31UL
|
||||
#define CRYPTO_STATUS_CMD_FF_BUSY_Msk 0x80000000UL
|
||||
/* CRYPTO.RAM_PWRUP_DELAY */
|
||||
#define CRYPTO_RAM_PWRUP_DELAY_PWRUP_DELAY_Pos 0UL
|
||||
#define CRYPTO_RAM_PWRUP_DELAY_PWRUP_DELAY_Msk 0x3FFUL
|
||||
/* CRYPTO.ERROR_STATUS0 */
|
||||
#define CRYPTO_ERROR_STATUS0_DATA32_Pos 0UL
|
||||
#define CRYPTO_ERROR_STATUS0_DATA32_Msk 0xFFFFFFFFUL
|
||||
/* CRYPTO.ERROR_STATUS1 */
|
||||
#define CRYPTO_ERROR_STATUS1_DATA23_Pos 0UL
|
||||
#define CRYPTO_ERROR_STATUS1_DATA23_Msk 0xFFFFFFUL
|
||||
#define CRYPTO_ERROR_STATUS1_IDX_Pos 24UL
|
||||
#define CRYPTO_ERROR_STATUS1_IDX_Msk 0x7000000UL
|
||||
#define CRYPTO_ERROR_STATUS1_VALID_Pos 31UL
|
||||
#define CRYPTO_ERROR_STATUS1_VALID_Msk 0x80000000UL
|
||||
/* CRYPTO.INSTR_FF_CTL */
|
||||
#define CRYPTO_INSTR_FF_CTL_EVENT_LEVEL_Pos 0UL
|
||||
#define CRYPTO_INSTR_FF_CTL_EVENT_LEVEL_Msk 0x7UL
|
||||
#define CRYPTO_INSTR_FF_CTL_CLEAR_Pos 16UL
|
||||
#define CRYPTO_INSTR_FF_CTL_CLEAR_Msk 0x10000UL
|
||||
#define CRYPTO_INSTR_FF_CTL_BLOCK_Pos 17UL
|
||||
#define CRYPTO_INSTR_FF_CTL_BLOCK_Msk 0x20000UL
|
||||
/* CRYPTO.INSTR_FF_STATUS */
|
||||
#define CRYPTO_INSTR_FF_STATUS_USED_Pos 0UL
|
||||
#define CRYPTO_INSTR_FF_STATUS_USED_Msk 0xFUL
|
||||
#define CRYPTO_INSTR_FF_STATUS_EVENT_Pos 16UL
|
||||
#define CRYPTO_INSTR_FF_STATUS_EVENT_Msk 0x10000UL
|
||||
#define CRYPTO_INSTR_FF_STATUS_BUSY_Pos 31UL
|
||||
#define CRYPTO_INSTR_FF_STATUS_BUSY_Msk 0x80000000UL
|
||||
/* CRYPTO.INSTR_FF_WR */
|
||||
#define CRYPTO_INSTR_FF_WR_DATA32_Pos 0UL
|
||||
#define CRYPTO_INSTR_FF_WR_DATA32_Msk 0xFFFFFFFFUL
|
||||
/* CRYPTO.RF_DATA */
|
||||
#define CRYPTO_RF_DATA_DATA32_Pos 0UL
|
||||
#define CRYPTO_RF_DATA_DATA32_Msk 0xFFFFFFFFUL
|
||||
/* CRYPTO.AES_CTL */
|
||||
#define CRYPTO_AES_CTL_KEY_SIZE_Pos 0UL
|
||||
#define CRYPTO_AES_CTL_KEY_SIZE_Msk 0x3UL
|
||||
/* CRYPTO.STR_RESULT */
|
||||
#define CRYPTO_STR_RESULT_MEMCMP_Pos 0UL
|
||||
#define CRYPTO_STR_RESULT_MEMCMP_Msk 0x1UL
|
||||
/* CRYPTO.PR_LFSR_CTL0 */
|
||||
#define CRYPTO_PR_LFSR_CTL0_LFSR32_Pos 0UL
|
||||
#define CRYPTO_PR_LFSR_CTL0_LFSR32_Msk 0xFFFFFFFFUL
|
||||
/* CRYPTO.PR_LFSR_CTL1 */
|
||||
#define CRYPTO_PR_LFSR_CTL1_LFSR31_Pos 0UL
|
||||
#define CRYPTO_PR_LFSR_CTL1_LFSR31_Msk 0x7FFFFFFFUL
|
||||
/* CRYPTO.PR_LFSR_CTL2 */
|
||||
#define CRYPTO_PR_LFSR_CTL2_LFSR29_Pos 0UL
|
||||
#define CRYPTO_PR_LFSR_CTL2_LFSR29_Msk 0x1FFFFFFFUL
|
||||
/* CRYPTO.PR_RESULT */
|
||||
#define CRYPTO_PR_RESULT_DATA32_Pos 0UL
|
||||
#define CRYPTO_PR_RESULT_DATA32_Msk 0xFFFFFFFFUL
|
||||
/* CRYPTO.TR_CTL0 */
|
||||
#define CRYPTO_TR_CTL0_SAMPLE_CLOCK_DIV_Pos 0UL
|
||||
#define CRYPTO_TR_CTL0_SAMPLE_CLOCK_DIV_Msk 0xFFUL
|
||||
#define CRYPTO_TR_CTL0_RED_CLOCK_DIV_Pos 8UL
|
||||
#define CRYPTO_TR_CTL0_RED_CLOCK_DIV_Msk 0xFF00UL
|
||||
#define CRYPTO_TR_CTL0_INIT_DELAY_Pos 16UL
|
||||
#define CRYPTO_TR_CTL0_INIT_DELAY_Msk 0xFF0000UL
|
||||
#define CRYPTO_TR_CTL0_VON_NEUMANN_CORR_Pos 24UL
|
||||
#define CRYPTO_TR_CTL0_VON_NEUMANN_CORR_Msk 0x1000000UL
|
||||
#define CRYPTO_TR_CTL0_STOP_ON_AP_DETECT_Pos 28UL
|
||||
#define CRYPTO_TR_CTL0_STOP_ON_AP_DETECT_Msk 0x10000000UL
|
||||
#define CRYPTO_TR_CTL0_STOP_ON_RC_DETECT_Pos 29UL
|
||||
#define CRYPTO_TR_CTL0_STOP_ON_RC_DETECT_Msk 0x20000000UL
|
||||
/* CRYPTO.TR_CTL1 */
|
||||
#define CRYPTO_TR_CTL1_RO11_EN_Pos 0UL
|
||||
#define CRYPTO_TR_CTL1_RO11_EN_Msk 0x1UL
|
||||
#define CRYPTO_TR_CTL1_RO15_EN_Pos 1UL
|
||||
#define CRYPTO_TR_CTL1_RO15_EN_Msk 0x2UL
|
||||
#define CRYPTO_TR_CTL1_GARO15_EN_Pos 2UL
|
||||
#define CRYPTO_TR_CTL1_GARO15_EN_Msk 0x4UL
|
||||
#define CRYPTO_TR_CTL1_GARO31_EN_Pos 3UL
|
||||
#define CRYPTO_TR_CTL1_GARO31_EN_Msk 0x8UL
|
||||
#define CRYPTO_TR_CTL1_FIRO15_EN_Pos 4UL
|
||||
#define CRYPTO_TR_CTL1_FIRO15_EN_Msk 0x10UL
|
||||
#define CRYPTO_TR_CTL1_FIRO31_EN_Pos 5UL
|
||||
#define CRYPTO_TR_CTL1_FIRO31_EN_Msk 0x20UL
|
||||
/* CRYPTO.TR_RESULT */
|
||||
#define CRYPTO_TR_RESULT_DATA32_Pos 0UL
|
||||
#define CRYPTO_TR_RESULT_DATA32_Msk 0xFFFFFFFFUL
|
||||
/* CRYPTO.TR_GARO_CTL */
|
||||
#define CRYPTO_TR_GARO_CTL_POLYNOMIAL31_Pos 0UL
|
||||
#define CRYPTO_TR_GARO_CTL_POLYNOMIAL31_Msk 0x7FFFFFFFUL
|
||||
/* CRYPTO.TR_FIRO_CTL */
|
||||
#define CRYPTO_TR_FIRO_CTL_POLYNOMIAL31_Pos 0UL
|
||||
#define CRYPTO_TR_FIRO_CTL_POLYNOMIAL31_Msk 0x7FFFFFFFUL
|
||||
/* CRYPTO.TR_MON_CTL */
|
||||
#define CRYPTO_TR_MON_CTL_BITSTREAM_SEL_Pos 0UL
|
||||
#define CRYPTO_TR_MON_CTL_BITSTREAM_SEL_Msk 0x3UL
|
||||
/* CRYPTO.TR_MON_CMD */
|
||||
#define CRYPTO_TR_MON_CMD_START_AP_Pos 0UL
|
||||
#define CRYPTO_TR_MON_CMD_START_AP_Msk 0x1UL
|
||||
#define CRYPTO_TR_MON_CMD_START_RC_Pos 1UL
|
||||
#define CRYPTO_TR_MON_CMD_START_RC_Msk 0x2UL
|
||||
/* CRYPTO.TR_MON_RC_CTL */
|
||||
#define CRYPTO_TR_MON_RC_CTL_CUTOFF_COUNT8_Pos 0UL
|
||||
#define CRYPTO_TR_MON_RC_CTL_CUTOFF_COUNT8_Msk 0xFFUL
|
||||
/* CRYPTO.TR_MON_RC_STATUS0 */
|
||||
#define CRYPTO_TR_MON_RC_STATUS0_BIT_Pos 0UL
|
||||
#define CRYPTO_TR_MON_RC_STATUS0_BIT_Msk 0x1UL
|
||||
/* CRYPTO.TR_MON_RC_STATUS1 */
|
||||
#define CRYPTO_TR_MON_RC_STATUS1_REP_COUNT_Pos 0UL
|
||||
#define CRYPTO_TR_MON_RC_STATUS1_REP_COUNT_Msk 0xFFUL
|
||||
/* CRYPTO.TR_MON_AP_CTL */
|
||||
#define CRYPTO_TR_MON_AP_CTL_CUTOFF_COUNT16_Pos 0UL
|
||||
#define CRYPTO_TR_MON_AP_CTL_CUTOFF_COUNT16_Msk 0xFFFFUL
|
||||
#define CRYPTO_TR_MON_AP_CTL_WINDOW_SIZE_Pos 16UL
|
||||
#define CRYPTO_TR_MON_AP_CTL_WINDOW_SIZE_Msk 0xFFFF0000UL
|
||||
/* CRYPTO.TR_MON_AP_STATUS0 */
|
||||
#define CRYPTO_TR_MON_AP_STATUS0_BIT_Pos 0UL
|
||||
#define CRYPTO_TR_MON_AP_STATUS0_BIT_Msk 0x1UL
|
||||
/* CRYPTO.TR_MON_AP_STATUS1 */
|
||||
#define CRYPTO_TR_MON_AP_STATUS1_OCC_COUNT_Pos 0UL
|
||||
#define CRYPTO_TR_MON_AP_STATUS1_OCC_COUNT_Msk 0xFFFFUL
|
||||
#define CRYPTO_TR_MON_AP_STATUS1_WINDOW_INDEX_Pos 16UL
|
||||
#define CRYPTO_TR_MON_AP_STATUS1_WINDOW_INDEX_Msk 0xFFFF0000UL
|
||||
/* CRYPTO.SHA_CTL */
|
||||
#define CRYPTO_SHA_CTL_MODE_Pos 0UL
|
||||
#define CRYPTO_SHA_CTL_MODE_Msk 0x7UL
|
||||
/* CRYPTO.CRC_CTL */
|
||||
#define CRYPTO_CRC_CTL_DATA_REVERSE_Pos 0UL
|
||||
#define CRYPTO_CRC_CTL_DATA_REVERSE_Msk 0x1UL
|
||||
#define CRYPTO_CRC_CTL_REM_REVERSE_Pos 8UL
|
||||
#define CRYPTO_CRC_CTL_REM_REVERSE_Msk 0x100UL
|
||||
/* CRYPTO.CRC_DATA_CTL */
|
||||
#define CRYPTO_CRC_DATA_CTL_DATA_XOR_Pos 0UL
|
||||
#define CRYPTO_CRC_DATA_CTL_DATA_XOR_Msk 0xFFUL
|
||||
/* CRYPTO.CRC_POL_CTL */
|
||||
#define CRYPTO_CRC_POL_CTL_POLYNOMIAL_Pos 0UL
|
||||
#define CRYPTO_CRC_POL_CTL_POLYNOMIAL_Msk 0xFFFFFFFFUL
|
||||
/* CRYPTO.CRC_LFSR_CTL */
|
||||
#define CRYPTO_CRC_LFSR_CTL_LFSR32_Pos 0UL
|
||||
#define CRYPTO_CRC_LFSR_CTL_LFSR32_Msk 0xFFFFFFFFUL
|
||||
/* CRYPTO.CRC_REM_CTL */
|
||||
#define CRYPTO_CRC_REM_CTL_REM_XOR_Pos 0UL
|
||||
#define CRYPTO_CRC_REM_CTL_REM_XOR_Msk 0xFFFFFFFFUL
|
||||
/* CRYPTO.CRC_REM_RESULT */
|
||||
#define CRYPTO_CRC_REM_RESULT_REM_Pos 0UL
|
||||
#define CRYPTO_CRC_REM_RESULT_REM_Msk 0xFFFFFFFFUL
|
||||
/* CRYPTO.VU_CTL0 */
|
||||
#define CRYPTO_VU_CTL0_ALWAYS_EXECUTE_Pos 0UL
|
||||
#define CRYPTO_VU_CTL0_ALWAYS_EXECUTE_Msk 0x1UL
|
||||
/* CRYPTO.VU_CTL1 */
|
||||
#define CRYPTO_VU_CTL1_ADDR_Pos 14UL
|
||||
#define CRYPTO_VU_CTL1_ADDR_Msk 0xFFFFC000UL
|
||||
/* CRYPTO.VU_STATUS */
|
||||
#define CRYPTO_VU_STATUS_CARRY_Pos 0UL
|
||||
#define CRYPTO_VU_STATUS_CARRY_Msk 0x1UL
|
||||
#define CRYPTO_VU_STATUS_EVEN_Pos 1UL
|
||||
#define CRYPTO_VU_STATUS_EVEN_Msk 0x2UL
|
||||
#define CRYPTO_VU_STATUS_ZERO_Pos 2UL
|
||||
#define CRYPTO_VU_STATUS_ZERO_Msk 0x4UL
|
||||
#define CRYPTO_VU_STATUS_ONE_Pos 3UL
|
||||
#define CRYPTO_VU_STATUS_ONE_Msk 0x8UL
|
||||
/* CRYPTO.INTR */
|
||||
#define CRYPTO_INTR_INSTR_FF_LEVEL_Pos 0UL
|
||||
#define CRYPTO_INTR_INSTR_FF_LEVEL_Msk 0x1UL
|
||||
#define CRYPTO_INTR_INSTR_FF_OVERFLOW_Pos 1UL
|
||||
#define CRYPTO_INTR_INSTR_FF_OVERFLOW_Msk 0x2UL
|
||||
#define CRYPTO_INTR_TR_INITIALIZED_Pos 2UL
|
||||
#define CRYPTO_INTR_TR_INITIALIZED_Msk 0x4UL
|
||||
#define CRYPTO_INTR_TR_DATA_AVAILABLE_Pos 3UL
|
||||
#define CRYPTO_INTR_TR_DATA_AVAILABLE_Msk 0x8UL
|
||||
#define CRYPTO_INTR_PR_DATA_AVAILABLE_Pos 4UL
|
||||
#define CRYPTO_INTR_PR_DATA_AVAILABLE_Msk 0x10UL
|
||||
#define CRYPTO_INTR_INSTR_OPC_ERROR_Pos 16UL
|
||||
#define CRYPTO_INTR_INSTR_OPC_ERROR_Msk 0x10000UL
|
||||
#define CRYPTO_INTR_INSTR_CC_ERROR_Pos 17UL
|
||||
#define CRYPTO_INTR_INSTR_CC_ERROR_Msk 0x20000UL
|
||||
#define CRYPTO_INTR_BUS_ERROR_Pos 18UL
|
||||
#define CRYPTO_INTR_BUS_ERROR_Msk 0x40000UL
|
||||
#define CRYPTO_INTR_TR_AP_DETECT_ERROR_Pos 19UL
|
||||
#define CRYPTO_INTR_TR_AP_DETECT_ERROR_Msk 0x80000UL
|
||||
#define CRYPTO_INTR_TR_RC_DETECT_ERROR_Pos 20UL
|
||||
#define CRYPTO_INTR_TR_RC_DETECT_ERROR_Msk 0x100000UL
|
||||
/* CRYPTO.INTR_SET */
|
||||
#define CRYPTO_INTR_SET_INSTR_FF_LEVEL_Pos 0UL
|
||||
#define CRYPTO_INTR_SET_INSTR_FF_LEVEL_Msk 0x1UL
|
||||
#define CRYPTO_INTR_SET_INSTR_FF_OVERFLOW_Pos 1UL
|
||||
#define CRYPTO_INTR_SET_INSTR_FF_OVERFLOW_Msk 0x2UL
|
||||
#define CRYPTO_INTR_SET_TR_INITIALIZED_Pos 2UL
|
||||
#define CRYPTO_INTR_SET_TR_INITIALIZED_Msk 0x4UL
|
||||
#define CRYPTO_INTR_SET_TR_DATA_AVAILABLE_Pos 3UL
|
||||
#define CRYPTO_INTR_SET_TR_DATA_AVAILABLE_Msk 0x8UL
|
||||
#define CRYPTO_INTR_SET_PR_DATA_AVAILABLE_Pos 4UL
|
||||
#define CRYPTO_INTR_SET_PR_DATA_AVAILABLE_Msk 0x10UL
|
||||
#define CRYPTO_INTR_SET_INSTR_OPC_ERROR_Pos 16UL
|
||||
#define CRYPTO_INTR_SET_INSTR_OPC_ERROR_Msk 0x10000UL
|
||||
#define CRYPTO_INTR_SET_INSTR_CC_ERROR_Pos 17UL
|
||||
#define CRYPTO_INTR_SET_INSTR_CC_ERROR_Msk 0x20000UL
|
||||
#define CRYPTO_INTR_SET_BUS_ERROR_Pos 18UL
|
||||
#define CRYPTO_INTR_SET_BUS_ERROR_Msk 0x40000UL
|
||||
#define CRYPTO_INTR_SET_TR_AP_DETECT_ERROR_Pos 19UL
|
||||
#define CRYPTO_INTR_SET_TR_AP_DETECT_ERROR_Msk 0x80000UL
|
||||
#define CRYPTO_INTR_SET_TR_RC_DETECT_ERROR_Pos 20UL
|
||||
#define CRYPTO_INTR_SET_TR_RC_DETECT_ERROR_Msk 0x100000UL
|
||||
/* CRYPTO.INTR_MASK */
|
||||
#define CRYPTO_INTR_MASK_INSTR_FF_LEVEL_Pos 0UL
|
||||
#define CRYPTO_INTR_MASK_INSTR_FF_LEVEL_Msk 0x1UL
|
||||
#define CRYPTO_INTR_MASK_INSTR_FF_OVERFLOW_Pos 1UL
|
||||
#define CRYPTO_INTR_MASK_INSTR_FF_OVERFLOW_Msk 0x2UL
|
||||
#define CRYPTO_INTR_MASK_TR_INITIALIZED_Pos 2UL
|
||||
#define CRYPTO_INTR_MASK_TR_INITIALIZED_Msk 0x4UL
|
||||
#define CRYPTO_INTR_MASK_TR_DATA_AVAILABLE_Pos 3UL
|
||||
#define CRYPTO_INTR_MASK_TR_DATA_AVAILABLE_Msk 0x8UL
|
||||
#define CRYPTO_INTR_MASK_PR_DATA_AVAILABLE_Pos 4UL
|
||||
#define CRYPTO_INTR_MASK_PR_DATA_AVAILABLE_Msk 0x10UL
|
||||
#define CRYPTO_INTR_MASK_INSTR_OPC_ERROR_Pos 16UL
|
||||
#define CRYPTO_INTR_MASK_INSTR_OPC_ERROR_Msk 0x10000UL
|
||||
#define CRYPTO_INTR_MASK_INSTR_CC_ERROR_Pos 17UL
|
||||
#define CRYPTO_INTR_MASK_INSTR_CC_ERROR_Msk 0x20000UL
|
||||
#define CRYPTO_INTR_MASK_BUS_ERROR_Pos 18UL
|
||||
#define CRYPTO_INTR_MASK_BUS_ERROR_Msk 0x40000UL
|
||||
#define CRYPTO_INTR_MASK_TR_AP_DETECT_ERROR_Pos 19UL
|
||||
#define CRYPTO_INTR_MASK_TR_AP_DETECT_ERROR_Msk 0x80000UL
|
||||
#define CRYPTO_INTR_MASK_TR_RC_DETECT_ERROR_Pos 20UL
|
||||
#define CRYPTO_INTR_MASK_TR_RC_DETECT_ERROR_Msk 0x100000UL
|
||||
/* CRYPTO.INTR_MASKED */
|
||||
#define CRYPTO_INTR_MASKED_INSTR_FF_LEVEL_Pos 0UL
|
||||
#define CRYPTO_INTR_MASKED_INSTR_FF_LEVEL_Msk 0x1UL
|
||||
#define CRYPTO_INTR_MASKED_INSTR_FF_OVERFLOW_Pos 1UL
|
||||
#define CRYPTO_INTR_MASKED_INSTR_FF_OVERFLOW_Msk 0x2UL
|
||||
#define CRYPTO_INTR_MASKED_TR_INITIALIZED_Pos 2UL
|
||||
#define CRYPTO_INTR_MASKED_TR_INITIALIZED_Msk 0x4UL
|
||||
#define CRYPTO_INTR_MASKED_TR_DATA_AVAILABLE_Pos 3UL
|
||||
#define CRYPTO_INTR_MASKED_TR_DATA_AVAILABLE_Msk 0x8UL
|
||||
#define CRYPTO_INTR_MASKED_PR_DATA_AVAILABLE_Pos 4UL
|
||||
#define CRYPTO_INTR_MASKED_PR_DATA_AVAILABLE_Msk 0x10UL
|
||||
#define CRYPTO_INTR_MASKED_INSTR_OPC_ERROR_Pos 16UL
|
||||
#define CRYPTO_INTR_MASKED_INSTR_OPC_ERROR_Msk 0x10000UL
|
||||
#define CRYPTO_INTR_MASKED_INSTR_CC_ERROR_Pos 17UL
|
||||
#define CRYPTO_INTR_MASKED_INSTR_CC_ERROR_Msk 0x20000UL
|
||||
#define CRYPTO_INTR_MASKED_BUS_ERROR_Pos 18UL
|
||||
#define CRYPTO_INTR_MASKED_BUS_ERROR_Msk 0x40000UL
|
||||
#define CRYPTO_INTR_MASKED_TR_AP_DETECT_ERROR_Pos 19UL
|
||||
#define CRYPTO_INTR_MASKED_TR_AP_DETECT_ERROR_Msk 0x80000UL
|
||||
#define CRYPTO_INTR_MASKED_TR_RC_DETECT_ERROR_Pos 20UL
|
||||
#define CRYPTO_INTR_MASKED_TR_RC_DETECT_ERROR_Msk 0x100000UL
|
||||
/* CRYPTO.MEM_BUFF */
|
||||
#define CRYPTO_MEM_BUFF_DATA32_Pos 0UL
|
||||
#define CRYPTO_MEM_BUFF_DATA32_Msk 0xFFFFFFFFUL
|
||||
|
||||
|
||||
#endif /* _CYIP_CRYPTO_H_ */
|
||||
|
||||
|
||||
/* [] END OF FILE */
|
||||
|
|
@ -1,455 +0,0 @@
|
|||
/***************************************************************************//**
|
||||
* \file cyip_crypto_v2.h
|
||||
*
|
||||
* \brief
|
||||
* CRYPTO IP definitions
|
||||
*
|
||||
* \note
|
||||
* Generator version: 1.3.0.1146
|
||||
* Database revision: rev#1050929
|
||||
*
|
||||
********************************************************************************
|
||||
* \copyright
|
||||
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
|
||||
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _CYIP_CRYPTO_V2_H_
|
||||
#define _CYIP_CRYPTO_V2_H_
|
||||
|
||||
#include "cyip_headers.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* CRYPTO
|
||||
*******************************************************************************/
|
||||
|
||||
#define CRYPTO_V2_SECTION_SIZE 0x00010000UL
|
||||
|
||||
/**
|
||||
* \brief Cryptography component (CRYPTO)
|
||||
*/
|
||||
typedef struct {
|
||||
__IOM uint32_t CTL; /*!< 0x00000000 Control */
|
||||
__IM uint32_t RESERVED;
|
||||
__IOM uint32_t RAM_PWR_CTL; /*!< 0x00000008 SRAM power control */
|
||||
__IOM uint32_t RAM_PWR_DELAY_CTL; /*!< 0x0000000C SRAM power delay control */
|
||||
__IOM uint32_t ECC_CTL; /*!< 0x00000010 ECC control */
|
||||
__IM uint32_t RESERVED1[3];
|
||||
__IM uint32_t ERROR_STATUS0; /*!< 0x00000020 Error status 0 */
|
||||
__IOM uint32_t ERROR_STATUS1; /*!< 0x00000024 Error status 1 */
|
||||
__IM uint32_t RESERVED2[54];
|
||||
__IOM uint32_t INTR; /*!< 0x00000100 Interrupt register */
|
||||
__IOM uint32_t INTR_SET; /*!< 0x00000104 Interrupt set register */
|
||||
__IOM uint32_t INTR_MASK; /*!< 0x00000108 Interrupt mask register */
|
||||
__IM uint32_t INTR_MASKED; /*!< 0x0000010C Interrupt masked register */
|
||||
__IM uint32_t RESERVED3[60];
|
||||
__IOM uint32_t PR_LFSR_CTL0; /*!< 0x00000200 Pseudo random LFSR control 0 */
|
||||
__IOM uint32_t PR_LFSR_CTL1; /*!< 0x00000204 Pseudo random LFSR control 1 */
|
||||
__IOM uint32_t PR_LFSR_CTL2; /*!< 0x00000208 Pseudo random LFSR control 2 */
|
||||
__IOM uint32_t PR_MAX_CTL; /*!< 0x0000020C Pseudo random maximum control */
|
||||
__IOM uint32_t PR_CMD; /*!< 0x00000210 Pseudo random command */
|
||||
__IM uint32_t RESERVED4;
|
||||
__IOM uint32_t PR_RESULT; /*!< 0x00000218 Pseudo random result */
|
||||
__IM uint32_t RESERVED5[25];
|
||||
__IOM uint32_t TR_CTL0; /*!< 0x00000280 True random control 0 */
|
||||
__IOM uint32_t TR_CTL1; /*!< 0x00000284 True random control 1 */
|
||||
__IOM uint32_t TR_CTL2; /*!< 0x00000288 True random control 2 */
|
||||
__IM uint32_t TR_STATUS; /*!< 0x0000028C True random status */
|
||||
__IOM uint32_t TR_CMD; /*!< 0x00000290 True random command */
|
||||
__IM uint32_t RESERVED6;
|
||||
__IOM uint32_t TR_RESULT; /*!< 0x00000298 True random result */
|
||||
__IM uint32_t RESERVED7;
|
||||
__IOM uint32_t TR_GARO_CTL; /*!< 0x000002A0 True random GARO control */
|
||||
__IOM uint32_t TR_FIRO_CTL; /*!< 0x000002A4 True random FIRO control */
|
||||
__IM uint32_t RESERVED8[6];
|
||||
__IOM uint32_t TR_MON_CTL; /*!< 0x000002C0 True random monitor control */
|
||||
__IM uint32_t RESERVED9;
|
||||
__IOM uint32_t TR_MON_CMD; /*!< 0x000002C8 True random monitor command */
|
||||
__IM uint32_t RESERVED10;
|
||||
__IOM uint32_t TR_MON_RC_CTL; /*!< 0x000002D0 True random monitor RC control */
|
||||
__IM uint32_t RESERVED11;
|
||||
__IM uint32_t TR_MON_RC_STATUS0; /*!< 0x000002D8 True random monitor RC status 0 */
|
||||
__IM uint32_t TR_MON_RC_STATUS1; /*!< 0x000002DC True random monitor RC status 1 */
|
||||
__IOM uint32_t TR_MON_AP_CTL; /*!< 0x000002E0 True random monitor AP control */
|
||||
__IM uint32_t RESERVED12;
|
||||
__IM uint32_t TR_MON_AP_STATUS0; /*!< 0x000002E8 True random monitor AP status 0 */
|
||||
__IM uint32_t TR_MON_AP_STATUS1; /*!< 0x000002EC True random monitor AP status 1 */
|
||||
__IM uint32_t RESERVED13[837];
|
||||
__IM uint32_t STATUS; /*!< 0x00001004 Status */
|
||||
__IM uint32_t RESERVED14[14];
|
||||
__IOM uint32_t INSTR_FF_CTL; /*!< 0x00001040 Instruction FIFO control */
|
||||
__IM uint32_t INSTR_FF_STATUS; /*!< 0x00001044 Instruction FIFO status */
|
||||
__OM uint32_t INSTR_FF_WR; /*!< 0x00001048 Instruction FIFO write */
|
||||
__IM uint32_t RESERVED15[29];
|
||||
__IM uint32_t LOAD0_FF_STATUS; /*!< 0x000010C0 Load 0 FIFO status */
|
||||
__IM uint32_t RESERVED16[3];
|
||||
__IM uint32_t LOAD1_FF_STATUS; /*!< 0x000010D0 Load 1 FIFO status */
|
||||
__IM uint32_t RESERVED17[7];
|
||||
__IM uint32_t STORE_FF_STATUS; /*!< 0x000010F0 Store FIFO status */
|
||||
__IM uint32_t RESERVED18[3];
|
||||
__IOM uint32_t AES_CTL; /*!< 0x00001100 AES control */
|
||||
__IM uint32_t RESERVED19[31];
|
||||
__IOM uint32_t RESULT; /*!< 0x00001180 Result */
|
||||
__IM uint32_t RESERVED20[159];
|
||||
__IOM uint32_t CRC_CTL; /*!< 0x00001400 CRC control */
|
||||
__IM uint32_t RESERVED21[3];
|
||||
__IOM uint32_t CRC_DATA_CTL; /*!< 0x00001410 CRC data control */
|
||||
__IM uint32_t RESERVED22[3];
|
||||
__IOM uint32_t CRC_POL_CTL; /*!< 0x00001420 CRC polynomial control */
|
||||
__IM uint32_t RESERVED23[7];
|
||||
__IOM uint32_t CRC_REM_CTL; /*!< 0x00001440 CRC remainder control */
|
||||
__IM uint32_t RESERVED24;
|
||||
__IM uint32_t CRC_REM_RESULT; /*!< 0x00001448 CRC remainder result */
|
||||
__IM uint32_t RESERVED25[13];
|
||||
__IOM uint32_t VU_CTL0; /*!< 0x00001480 Vector unit control 0 */
|
||||
__IOM uint32_t VU_CTL1; /*!< 0x00001484 Vector unit control 1 */
|
||||
__IOM uint32_t VU_CTL2; /*!< 0x00001488 Vector unit control 2 */
|
||||
__IM uint32_t RESERVED26;
|
||||
__IM uint32_t VU_STATUS; /*!< 0x00001490 Vector unit status */
|
||||
__IM uint32_t RESERVED27[11];
|
||||
__IM uint32_t VU_RF_DATA[16]; /*!< 0x000014C0 Vector unit register-file */
|
||||
__IM uint32_t RESERVED28[704];
|
||||
__IOM uint32_t DEV_KEY_ADDR0_CTL; /*!< 0x00002000 Device key address 0 control */
|
||||
__IOM uint32_t DEV_KEY_ADDR0; /*!< 0x00002004 Device key address 0 */
|
||||
__IM uint32_t RESERVED29[6];
|
||||
__IOM uint32_t DEV_KEY_ADDR1_CTL; /*!< 0x00002020 Device key address 1 control */
|
||||
__IOM uint32_t DEV_KEY_ADDR1; /*!< 0x00002024 Device key address 1 control */
|
||||
__IM uint32_t RESERVED30[22];
|
||||
__IM uint32_t DEV_KEY_STATUS; /*!< 0x00002080 Device key status */
|
||||
__IM uint32_t RESERVED31[31];
|
||||
__IOM uint32_t DEV_KEY_CTL0; /*!< 0x00002100 Device key control 0 */
|
||||
__IM uint32_t RESERVED32[7];
|
||||
__IOM uint32_t DEV_KEY_CTL1; /*!< 0x00002120 Device key control 1 */
|
||||
__IM uint32_t RESERVED33[6071];
|
||||
__IOM uint32_t MEM_BUFF[8192]; /*!< 0x00008000 Memory buffer */
|
||||
} CRYPTO_V2_Type; /*!< Size = 65536 (0x10000) */
|
||||
|
||||
|
||||
/* CRYPTO.CTL */
|
||||
#define CRYPTO_V2_CTL_P_Pos 0UL
|
||||
#define CRYPTO_V2_CTL_P_Msk 0x1UL
|
||||
#define CRYPTO_V2_CTL_NS_Pos 1UL
|
||||
#define CRYPTO_V2_CTL_NS_Msk 0x2UL
|
||||
#define CRYPTO_V2_CTL_PC_Pos 4UL
|
||||
#define CRYPTO_V2_CTL_PC_Msk 0xF0UL
|
||||
#define CRYPTO_V2_CTL_ECC_EN_Pos 16UL
|
||||
#define CRYPTO_V2_CTL_ECC_EN_Msk 0x10000UL
|
||||
#define CRYPTO_V2_CTL_ECC_INJ_EN_Pos 17UL
|
||||
#define CRYPTO_V2_CTL_ECC_INJ_EN_Msk 0x20000UL
|
||||
#define CRYPTO_V2_CTL_ENABLED_Pos 31UL
|
||||
#define CRYPTO_V2_CTL_ENABLED_Msk 0x80000000UL
|
||||
/* CRYPTO.RAM_PWR_CTL */
|
||||
#define CRYPTO_V2_RAM_PWR_CTL_PWR_MODE_Pos 0UL
|
||||
#define CRYPTO_V2_RAM_PWR_CTL_PWR_MODE_Msk 0x3UL
|
||||
/* CRYPTO.RAM_PWR_DELAY_CTL */
|
||||
#define CRYPTO_V2_RAM_PWR_DELAY_CTL_UP_Pos 0UL
|
||||
#define CRYPTO_V2_RAM_PWR_DELAY_CTL_UP_Msk 0x3FFUL
|
||||
/* CRYPTO.ECC_CTL */
|
||||
#define CRYPTO_V2_ECC_CTL_WORD_ADDR_Pos 0UL
|
||||
#define CRYPTO_V2_ECC_CTL_WORD_ADDR_Msk 0x1FFFUL
|
||||
#define CRYPTO_V2_ECC_CTL_PARITY_Pos 25UL
|
||||
#define CRYPTO_V2_ECC_CTL_PARITY_Msk 0xFE000000UL
|
||||
/* CRYPTO.ERROR_STATUS0 */
|
||||
#define CRYPTO_V2_ERROR_STATUS0_DATA32_Pos 0UL
|
||||
#define CRYPTO_V2_ERROR_STATUS0_DATA32_Msk 0xFFFFFFFFUL
|
||||
/* CRYPTO.ERROR_STATUS1 */
|
||||
#define CRYPTO_V2_ERROR_STATUS1_DATA24_Pos 0UL
|
||||
#define CRYPTO_V2_ERROR_STATUS1_DATA24_Msk 0xFFFFFFUL
|
||||
#define CRYPTO_V2_ERROR_STATUS1_IDX_Pos 24UL
|
||||
#define CRYPTO_V2_ERROR_STATUS1_IDX_Msk 0x7000000UL
|
||||
#define CRYPTO_V2_ERROR_STATUS1_VALID_Pos 31UL
|
||||
#define CRYPTO_V2_ERROR_STATUS1_VALID_Msk 0x80000000UL
|
||||
/* CRYPTO.INTR */
|
||||
#define CRYPTO_V2_INTR_INSTR_FF_LEVEL_Pos 0UL
|
||||
#define CRYPTO_V2_INTR_INSTR_FF_LEVEL_Msk 0x1UL
|
||||
#define CRYPTO_V2_INTR_INSTR_FF_OVERFLOW_Pos 1UL
|
||||
#define CRYPTO_V2_INTR_INSTR_FF_OVERFLOW_Msk 0x2UL
|
||||
#define CRYPTO_V2_INTR_TR_INITIALIZED_Pos 2UL
|
||||
#define CRYPTO_V2_INTR_TR_INITIALIZED_Msk 0x4UL
|
||||
#define CRYPTO_V2_INTR_TR_DATA_AVAILABLE_Pos 3UL
|
||||
#define CRYPTO_V2_INTR_TR_DATA_AVAILABLE_Msk 0x8UL
|
||||
#define CRYPTO_V2_INTR_PR_DATA_AVAILABLE_Pos 4UL
|
||||
#define CRYPTO_V2_INTR_PR_DATA_AVAILABLE_Msk 0x10UL
|
||||
#define CRYPTO_V2_INTR_INSTR_OPC_ERROR_Pos 16UL
|
||||
#define CRYPTO_V2_INTR_INSTR_OPC_ERROR_Msk 0x10000UL
|
||||
#define CRYPTO_V2_INTR_INSTR_CC_ERROR_Pos 17UL
|
||||
#define CRYPTO_V2_INTR_INSTR_CC_ERROR_Msk 0x20000UL
|
||||
#define CRYPTO_V2_INTR_BUS_ERROR_Pos 18UL
|
||||
#define CRYPTO_V2_INTR_BUS_ERROR_Msk 0x40000UL
|
||||
#define CRYPTO_V2_INTR_TR_AP_DETECT_ERROR_Pos 19UL
|
||||
#define CRYPTO_V2_INTR_TR_AP_DETECT_ERROR_Msk 0x80000UL
|
||||
#define CRYPTO_V2_INTR_TR_RC_DETECT_ERROR_Pos 20UL
|
||||
#define CRYPTO_V2_INTR_TR_RC_DETECT_ERROR_Msk 0x100000UL
|
||||
#define CRYPTO_V2_INTR_INSTR_DEV_KEY_ERROR_Pos 21UL
|
||||
#define CRYPTO_V2_INTR_INSTR_DEV_KEY_ERROR_Msk 0x200000UL
|
||||
/* CRYPTO.INTR_SET */
|
||||
#define CRYPTO_V2_INTR_SET_INSTR_FF_LEVEL_Pos 0UL
|
||||
#define CRYPTO_V2_INTR_SET_INSTR_FF_LEVEL_Msk 0x1UL
|
||||
#define CRYPTO_V2_INTR_SET_INSTR_FF_OVERFLOW_Pos 1UL
|
||||
#define CRYPTO_V2_INTR_SET_INSTR_FF_OVERFLOW_Msk 0x2UL
|
||||
#define CRYPTO_V2_INTR_SET_TR_INITIALIZED_Pos 2UL
|
||||
#define CRYPTO_V2_INTR_SET_TR_INITIALIZED_Msk 0x4UL
|
||||
#define CRYPTO_V2_INTR_SET_TR_DATA_AVAILABLE_Pos 3UL
|
||||
#define CRYPTO_V2_INTR_SET_TR_DATA_AVAILABLE_Msk 0x8UL
|
||||
#define CRYPTO_V2_INTR_SET_PR_DATA_AVAILABLE_Pos 4UL
|
||||
#define CRYPTO_V2_INTR_SET_PR_DATA_AVAILABLE_Msk 0x10UL
|
||||
#define CRYPTO_V2_INTR_SET_INSTR_OPC_ERROR_Pos 16UL
|
||||
#define CRYPTO_V2_INTR_SET_INSTR_OPC_ERROR_Msk 0x10000UL
|
||||
#define CRYPTO_V2_INTR_SET_INSTR_CC_ERROR_Pos 17UL
|
||||
#define CRYPTO_V2_INTR_SET_INSTR_CC_ERROR_Msk 0x20000UL
|
||||
#define CRYPTO_V2_INTR_SET_BUS_ERROR_Pos 18UL
|
||||
#define CRYPTO_V2_INTR_SET_BUS_ERROR_Msk 0x40000UL
|
||||
#define CRYPTO_V2_INTR_SET_TR_AP_DETECT_ERROR_Pos 19UL
|
||||
#define CRYPTO_V2_INTR_SET_TR_AP_DETECT_ERROR_Msk 0x80000UL
|
||||
#define CRYPTO_V2_INTR_SET_TR_RC_DETECT_ERROR_Pos 20UL
|
||||
#define CRYPTO_V2_INTR_SET_TR_RC_DETECT_ERROR_Msk 0x100000UL
|
||||
#define CRYPTO_V2_INTR_SET_INSTR_DEV_KEY_ERROR_Pos 21UL
|
||||
#define CRYPTO_V2_INTR_SET_INSTR_DEV_KEY_ERROR_Msk 0x200000UL
|
||||
/* CRYPTO.INTR_MASK */
|
||||
#define CRYPTO_V2_INTR_MASK_INSTR_FF_LEVEL_Pos 0UL
|
||||
#define CRYPTO_V2_INTR_MASK_INSTR_FF_LEVEL_Msk 0x1UL
|
||||
#define CRYPTO_V2_INTR_MASK_INSTR_FF_OVERFLOW_Pos 1UL
|
||||
#define CRYPTO_V2_INTR_MASK_INSTR_FF_OVERFLOW_Msk 0x2UL
|
||||
#define CRYPTO_V2_INTR_MASK_TR_INITIALIZED_Pos 2UL
|
||||
#define CRYPTO_V2_INTR_MASK_TR_INITIALIZED_Msk 0x4UL
|
||||
#define CRYPTO_V2_INTR_MASK_TR_DATA_AVAILABLE_Pos 3UL
|
||||
#define CRYPTO_V2_INTR_MASK_TR_DATA_AVAILABLE_Msk 0x8UL
|
||||
#define CRYPTO_V2_INTR_MASK_PR_DATA_AVAILABLE_Pos 4UL
|
||||
#define CRYPTO_V2_INTR_MASK_PR_DATA_AVAILABLE_Msk 0x10UL
|
||||
#define CRYPTO_V2_INTR_MASK_INSTR_OPC_ERROR_Pos 16UL
|
||||
#define CRYPTO_V2_INTR_MASK_INSTR_OPC_ERROR_Msk 0x10000UL
|
||||
#define CRYPTO_V2_INTR_MASK_INSTR_CC_ERROR_Pos 17UL
|
||||
#define CRYPTO_V2_INTR_MASK_INSTR_CC_ERROR_Msk 0x20000UL
|
||||
#define CRYPTO_V2_INTR_MASK_BUS_ERROR_Pos 18UL
|
||||
#define CRYPTO_V2_INTR_MASK_BUS_ERROR_Msk 0x40000UL
|
||||
#define CRYPTO_V2_INTR_MASK_TR_AP_DETECT_ERROR_Pos 19UL
|
||||
#define CRYPTO_V2_INTR_MASK_TR_AP_DETECT_ERROR_Msk 0x80000UL
|
||||
#define CRYPTO_V2_INTR_MASK_TR_RC_DETECT_ERROR_Pos 20UL
|
||||
#define CRYPTO_V2_INTR_MASK_TR_RC_DETECT_ERROR_Msk 0x100000UL
|
||||
#define CRYPTO_V2_INTR_MASK_INSTR_DEV_KEY_ERROR_Pos 21UL
|
||||
#define CRYPTO_V2_INTR_MASK_INSTR_DEV_KEY_ERROR_Msk 0x200000UL
|
||||
/* CRYPTO.INTR_MASKED */
|
||||
#define CRYPTO_V2_INTR_MASKED_INSTR_FF_LEVEL_Pos 0UL
|
||||
#define CRYPTO_V2_INTR_MASKED_INSTR_FF_LEVEL_Msk 0x1UL
|
||||
#define CRYPTO_V2_INTR_MASKED_INSTR_FF_OVERFLOW_Pos 1UL
|
||||
#define CRYPTO_V2_INTR_MASKED_INSTR_FF_OVERFLOW_Msk 0x2UL
|
||||
#define CRYPTO_V2_INTR_MASKED_TR_INITIALIZED_Pos 2UL
|
||||
#define CRYPTO_V2_INTR_MASKED_TR_INITIALIZED_Msk 0x4UL
|
||||
#define CRYPTO_V2_INTR_MASKED_TR_DATA_AVAILABLE_Pos 3UL
|
||||
#define CRYPTO_V2_INTR_MASKED_TR_DATA_AVAILABLE_Msk 0x8UL
|
||||
#define CRYPTO_V2_INTR_MASKED_PR_DATA_AVAILABLE_Pos 4UL
|
||||
#define CRYPTO_V2_INTR_MASKED_PR_DATA_AVAILABLE_Msk 0x10UL
|
||||
#define CRYPTO_V2_INTR_MASKED_INSTR_OPC_ERROR_Pos 16UL
|
||||
#define CRYPTO_V2_INTR_MASKED_INSTR_OPC_ERROR_Msk 0x10000UL
|
||||
#define CRYPTO_V2_INTR_MASKED_INSTR_CC_ERROR_Pos 17UL
|
||||
#define CRYPTO_V2_INTR_MASKED_INSTR_CC_ERROR_Msk 0x20000UL
|
||||
#define CRYPTO_V2_INTR_MASKED_BUS_ERROR_Pos 18UL
|
||||
#define CRYPTO_V2_INTR_MASKED_BUS_ERROR_Msk 0x40000UL
|
||||
#define CRYPTO_V2_INTR_MASKED_TR_AP_DETECT_ERROR_Pos 19UL
|
||||
#define CRYPTO_V2_INTR_MASKED_TR_AP_DETECT_ERROR_Msk 0x80000UL
|
||||
#define CRYPTO_V2_INTR_MASKED_TR_RC_DETECT_ERROR_Pos 20UL
|
||||
#define CRYPTO_V2_INTR_MASKED_TR_RC_DETECT_ERROR_Msk 0x100000UL
|
||||
#define CRYPTO_V2_INTR_MASKED_INSTR_DEV_KEY_ERROR_Pos 21UL
|
||||
#define CRYPTO_V2_INTR_MASKED_INSTR_DEV_KEY_ERROR_Msk 0x200000UL
|
||||
/* CRYPTO.PR_LFSR_CTL0 */
|
||||
#define CRYPTO_V2_PR_LFSR_CTL0_LFSR32_Pos 0UL
|
||||
#define CRYPTO_V2_PR_LFSR_CTL0_LFSR32_Msk 0xFFFFFFFFUL
|
||||
/* CRYPTO.PR_LFSR_CTL1 */
|
||||
#define CRYPTO_V2_PR_LFSR_CTL1_LFSR31_Pos 0UL
|
||||
#define CRYPTO_V2_PR_LFSR_CTL1_LFSR31_Msk 0x7FFFFFFFUL
|
||||
/* CRYPTO.PR_LFSR_CTL2 */
|
||||
#define CRYPTO_V2_PR_LFSR_CTL2_LFSR29_Pos 0UL
|
||||
#define CRYPTO_V2_PR_LFSR_CTL2_LFSR29_Msk 0x1FFFFFFFUL
|
||||
/* CRYPTO.PR_MAX_CTL */
|
||||
#define CRYPTO_V2_PR_MAX_CTL_DATA32_Pos 0UL
|
||||
#define CRYPTO_V2_PR_MAX_CTL_DATA32_Msk 0xFFFFFFFFUL
|
||||
/* CRYPTO.PR_CMD */
|
||||
#define CRYPTO_V2_PR_CMD_START_Pos 0UL
|
||||
#define CRYPTO_V2_PR_CMD_START_Msk 0x1UL
|
||||
/* CRYPTO.PR_RESULT */
|
||||
#define CRYPTO_V2_PR_RESULT_DATA32_Pos 0UL
|
||||
#define CRYPTO_V2_PR_RESULT_DATA32_Msk 0xFFFFFFFFUL
|
||||
/* CRYPTO.TR_CTL0 */
|
||||
#define CRYPTO_V2_TR_CTL0_SAMPLE_CLOCK_DIV_Pos 0UL
|
||||
#define CRYPTO_V2_TR_CTL0_SAMPLE_CLOCK_DIV_Msk 0xFFUL
|
||||
#define CRYPTO_V2_TR_CTL0_RED_CLOCK_DIV_Pos 8UL
|
||||
#define CRYPTO_V2_TR_CTL0_RED_CLOCK_DIV_Msk 0xFF00UL
|
||||
#define CRYPTO_V2_TR_CTL0_INIT_DELAY_Pos 16UL
|
||||
#define CRYPTO_V2_TR_CTL0_INIT_DELAY_Msk 0xFF0000UL
|
||||
#define CRYPTO_V2_TR_CTL0_VON_NEUMANN_CORR_Pos 24UL
|
||||
#define CRYPTO_V2_TR_CTL0_VON_NEUMANN_CORR_Msk 0x1000000UL
|
||||
#define CRYPTO_V2_TR_CTL0_STOP_ON_AP_DETECT_Pos 28UL
|
||||
#define CRYPTO_V2_TR_CTL0_STOP_ON_AP_DETECT_Msk 0x10000000UL
|
||||
#define CRYPTO_V2_TR_CTL0_STOP_ON_RC_DETECT_Pos 29UL
|
||||
#define CRYPTO_V2_TR_CTL0_STOP_ON_RC_DETECT_Msk 0x20000000UL
|
||||
/* CRYPTO.TR_CTL1 */
|
||||
#define CRYPTO_V2_TR_CTL1_RO11_EN_Pos 0UL
|
||||
#define CRYPTO_V2_TR_CTL1_RO11_EN_Msk 0x1UL
|
||||
#define CRYPTO_V2_TR_CTL1_RO15_EN_Pos 1UL
|
||||
#define CRYPTO_V2_TR_CTL1_RO15_EN_Msk 0x2UL
|
||||
#define CRYPTO_V2_TR_CTL1_GARO15_EN_Pos 2UL
|
||||
#define CRYPTO_V2_TR_CTL1_GARO15_EN_Msk 0x4UL
|
||||
#define CRYPTO_V2_TR_CTL1_GARO31_EN_Pos 3UL
|
||||
#define CRYPTO_V2_TR_CTL1_GARO31_EN_Msk 0x8UL
|
||||
#define CRYPTO_V2_TR_CTL1_FIRO15_EN_Pos 4UL
|
||||
#define CRYPTO_V2_TR_CTL1_FIRO15_EN_Msk 0x10UL
|
||||
#define CRYPTO_V2_TR_CTL1_FIRO31_EN_Pos 5UL
|
||||
#define CRYPTO_V2_TR_CTL1_FIRO31_EN_Msk 0x20UL
|
||||
/* CRYPTO.TR_CTL2 */
|
||||
#define CRYPTO_V2_TR_CTL2_SIZE_Pos 0UL
|
||||
#define CRYPTO_V2_TR_CTL2_SIZE_Msk 0x3FUL
|
||||
/* CRYPTO.TR_STATUS */
|
||||
#define CRYPTO_V2_TR_STATUS_INITIALIZED_Pos 0UL
|
||||
#define CRYPTO_V2_TR_STATUS_INITIALIZED_Msk 0x1UL
|
||||
/* CRYPTO.TR_CMD */
|
||||
#define CRYPTO_V2_TR_CMD_START_Pos 0UL
|
||||
#define CRYPTO_V2_TR_CMD_START_Msk 0x1UL
|
||||
/* CRYPTO.TR_RESULT */
|
||||
#define CRYPTO_V2_TR_RESULT_DATA32_Pos 0UL
|
||||
#define CRYPTO_V2_TR_RESULT_DATA32_Msk 0xFFFFFFFFUL
|
||||
/* CRYPTO.TR_GARO_CTL */
|
||||
#define CRYPTO_V2_TR_GARO_CTL_POLYNOMIAL31_Pos 0UL
|
||||
#define CRYPTO_V2_TR_GARO_CTL_POLYNOMIAL31_Msk 0x7FFFFFFFUL
|
||||
/* CRYPTO.TR_FIRO_CTL */
|
||||
#define CRYPTO_V2_TR_FIRO_CTL_POLYNOMIAL31_Pos 0UL
|
||||
#define CRYPTO_V2_TR_FIRO_CTL_POLYNOMIAL31_Msk 0x7FFFFFFFUL
|
||||
/* CRYPTO.TR_MON_CTL */
|
||||
#define CRYPTO_V2_TR_MON_CTL_BITSTREAM_SEL_Pos 0UL
|
||||
#define CRYPTO_V2_TR_MON_CTL_BITSTREAM_SEL_Msk 0x3UL
|
||||
/* CRYPTO.TR_MON_CMD */
|
||||
#define CRYPTO_V2_TR_MON_CMD_START_AP_Pos 0UL
|
||||
#define CRYPTO_V2_TR_MON_CMD_START_AP_Msk 0x1UL
|
||||
#define CRYPTO_V2_TR_MON_CMD_START_RC_Pos 1UL
|
||||
#define CRYPTO_V2_TR_MON_CMD_START_RC_Msk 0x2UL
|
||||
/* CRYPTO.TR_MON_RC_CTL */
|
||||
#define CRYPTO_V2_TR_MON_RC_CTL_CUTOFF_COUNT8_Pos 0UL
|
||||
#define CRYPTO_V2_TR_MON_RC_CTL_CUTOFF_COUNT8_Msk 0xFFUL
|
||||
/* CRYPTO.TR_MON_RC_STATUS0 */
|
||||
#define CRYPTO_V2_TR_MON_RC_STATUS0_BIT_Pos 0UL
|
||||
#define CRYPTO_V2_TR_MON_RC_STATUS0_BIT_Msk 0x1UL
|
||||
/* CRYPTO.TR_MON_RC_STATUS1 */
|
||||
#define CRYPTO_V2_TR_MON_RC_STATUS1_REP_COUNT_Pos 0UL
|
||||
#define CRYPTO_V2_TR_MON_RC_STATUS1_REP_COUNT_Msk 0xFFUL
|
||||
/* CRYPTO.TR_MON_AP_CTL */
|
||||
#define CRYPTO_V2_TR_MON_AP_CTL_CUTOFF_COUNT16_Pos 0UL
|
||||
#define CRYPTO_V2_TR_MON_AP_CTL_CUTOFF_COUNT16_Msk 0xFFFFUL
|
||||
#define CRYPTO_V2_TR_MON_AP_CTL_WINDOW_SIZE_Pos 16UL
|
||||
#define CRYPTO_V2_TR_MON_AP_CTL_WINDOW_SIZE_Msk 0xFFFF0000UL
|
||||
/* CRYPTO.TR_MON_AP_STATUS0 */
|
||||
#define CRYPTO_V2_TR_MON_AP_STATUS0_BIT_Pos 0UL
|
||||
#define CRYPTO_V2_TR_MON_AP_STATUS0_BIT_Msk 0x1UL
|
||||
/* CRYPTO.TR_MON_AP_STATUS1 */
|
||||
#define CRYPTO_V2_TR_MON_AP_STATUS1_OCC_COUNT_Pos 0UL
|
||||
#define CRYPTO_V2_TR_MON_AP_STATUS1_OCC_COUNT_Msk 0xFFFFUL
|
||||
#define CRYPTO_V2_TR_MON_AP_STATUS1_WINDOW_INDEX_Pos 16UL
|
||||
#define CRYPTO_V2_TR_MON_AP_STATUS1_WINDOW_INDEX_Msk 0xFFFF0000UL
|
||||
/* CRYPTO.STATUS */
|
||||
#define CRYPTO_V2_STATUS_BUSY_Pos 31UL
|
||||
#define CRYPTO_V2_STATUS_BUSY_Msk 0x80000000UL
|
||||
/* CRYPTO.INSTR_FF_CTL */
|
||||
#define CRYPTO_V2_INSTR_FF_CTL_EVENT_LEVEL_Pos 0UL
|
||||
#define CRYPTO_V2_INSTR_FF_CTL_EVENT_LEVEL_Msk 0x7UL
|
||||
#define CRYPTO_V2_INSTR_FF_CTL_CLEAR_Pos 16UL
|
||||
#define CRYPTO_V2_INSTR_FF_CTL_CLEAR_Msk 0x10000UL
|
||||
#define CRYPTO_V2_INSTR_FF_CTL_BLOCK_Pos 17UL
|
||||
#define CRYPTO_V2_INSTR_FF_CTL_BLOCK_Msk 0x20000UL
|
||||
/* CRYPTO.INSTR_FF_STATUS */
|
||||
#define CRYPTO_V2_INSTR_FF_STATUS_USED_Pos 0UL
|
||||
#define CRYPTO_V2_INSTR_FF_STATUS_USED_Msk 0xFUL
|
||||
#define CRYPTO_V2_INSTR_FF_STATUS_EVENT_Pos 16UL
|
||||
#define CRYPTO_V2_INSTR_FF_STATUS_EVENT_Msk 0x10000UL
|
||||
/* CRYPTO.INSTR_FF_WR */
|
||||
#define CRYPTO_V2_INSTR_FF_WR_DATA32_Pos 0UL
|
||||
#define CRYPTO_V2_INSTR_FF_WR_DATA32_Msk 0xFFFFFFFFUL
|
||||
/* CRYPTO.LOAD0_FF_STATUS */
|
||||
#define CRYPTO_V2_LOAD0_FF_STATUS_USED5_Pos 0UL
|
||||
#define CRYPTO_V2_LOAD0_FF_STATUS_USED5_Msk 0x1FUL
|
||||
#define CRYPTO_V2_LOAD0_FF_STATUS_BUSY_Pos 31UL
|
||||
#define CRYPTO_V2_LOAD0_FF_STATUS_BUSY_Msk 0x80000000UL
|
||||
/* CRYPTO.LOAD1_FF_STATUS */
|
||||
#define CRYPTO_V2_LOAD1_FF_STATUS_USED5_Pos 0UL
|
||||
#define CRYPTO_V2_LOAD1_FF_STATUS_USED5_Msk 0x1FUL
|
||||
#define CRYPTO_V2_LOAD1_FF_STATUS_BUSY_Pos 31UL
|
||||
#define CRYPTO_V2_LOAD1_FF_STATUS_BUSY_Msk 0x80000000UL
|
||||
/* CRYPTO.STORE_FF_STATUS */
|
||||
#define CRYPTO_V2_STORE_FF_STATUS_USED5_Pos 0UL
|
||||
#define CRYPTO_V2_STORE_FF_STATUS_USED5_Msk 0x1FUL
|
||||
#define CRYPTO_V2_STORE_FF_STATUS_BUSY_Pos 31UL
|
||||
#define CRYPTO_V2_STORE_FF_STATUS_BUSY_Msk 0x80000000UL
|
||||
/* CRYPTO.AES_CTL */
|
||||
#define CRYPTO_V2_AES_CTL_KEY_SIZE_Pos 0UL
|
||||
#define CRYPTO_V2_AES_CTL_KEY_SIZE_Msk 0x3UL
|
||||
/* CRYPTO.RESULT */
|
||||
#define CRYPTO_V2_RESULT_DATA_Pos 0UL
|
||||
#define CRYPTO_V2_RESULT_DATA_Msk 0xFFFFFFFFUL
|
||||
/* CRYPTO.CRC_CTL */
|
||||
#define CRYPTO_V2_CRC_CTL_DATA_REVERSE_Pos 0UL
|
||||
#define CRYPTO_V2_CRC_CTL_DATA_REVERSE_Msk 0x1UL
|
||||
#define CRYPTO_V2_CRC_CTL_REM_REVERSE_Pos 8UL
|
||||
#define CRYPTO_V2_CRC_CTL_REM_REVERSE_Msk 0x100UL
|
||||
/* CRYPTO.CRC_DATA_CTL */
|
||||
#define CRYPTO_V2_CRC_DATA_CTL_DATA_XOR_Pos 0UL
|
||||
#define CRYPTO_V2_CRC_DATA_CTL_DATA_XOR_Msk 0xFFUL
|
||||
/* CRYPTO.CRC_POL_CTL */
|
||||
#define CRYPTO_V2_CRC_POL_CTL_POLYNOMIAL_Pos 0UL
|
||||
#define CRYPTO_V2_CRC_POL_CTL_POLYNOMIAL_Msk 0xFFFFFFFFUL
|
||||
/* CRYPTO.CRC_REM_CTL */
|
||||
#define CRYPTO_V2_CRC_REM_CTL_REM_XOR_Pos 0UL
|
||||
#define CRYPTO_V2_CRC_REM_CTL_REM_XOR_Msk 0xFFFFFFFFUL
|
||||
/* CRYPTO.CRC_REM_RESULT */
|
||||
#define CRYPTO_V2_CRC_REM_RESULT_REM_Pos 0UL
|
||||
#define CRYPTO_V2_CRC_REM_RESULT_REM_Msk 0xFFFFFFFFUL
|
||||
/* CRYPTO.VU_CTL0 */
|
||||
#define CRYPTO_V2_VU_CTL0_ALWAYS_EXECUTE_Pos 0UL
|
||||
#define CRYPTO_V2_VU_CTL0_ALWAYS_EXECUTE_Msk 0x1UL
|
||||
/* CRYPTO.VU_CTL1 */
|
||||
#define CRYPTO_V2_VU_CTL1_ADDR24_Pos 8UL
|
||||
#define CRYPTO_V2_VU_CTL1_ADDR24_Msk 0xFFFFFF00UL
|
||||
/* CRYPTO.VU_CTL2 */
|
||||
#define CRYPTO_V2_VU_CTL2_MASK_Pos 8UL
|
||||
#define CRYPTO_V2_VU_CTL2_MASK_Msk 0x7F00UL
|
||||
/* CRYPTO.VU_STATUS */
|
||||
#define CRYPTO_V2_VU_STATUS_CARRY_Pos 0UL
|
||||
#define CRYPTO_V2_VU_STATUS_CARRY_Msk 0x1UL
|
||||
#define CRYPTO_V2_VU_STATUS_EVEN_Pos 1UL
|
||||
#define CRYPTO_V2_VU_STATUS_EVEN_Msk 0x2UL
|
||||
#define CRYPTO_V2_VU_STATUS_ZERO_Pos 2UL
|
||||
#define CRYPTO_V2_VU_STATUS_ZERO_Msk 0x4UL
|
||||
#define CRYPTO_V2_VU_STATUS_ONE_Pos 3UL
|
||||
#define CRYPTO_V2_VU_STATUS_ONE_Msk 0x8UL
|
||||
/* CRYPTO.VU_RF_DATA */
|
||||
#define CRYPTO_V2_VU_RF_DATA_DATA32_Pos 0UL
|
||||
#define CRYPTO_V2_VU_RF_DATA_DATA32_Msk 0xFFFFFFFFUL
|
||||
/* CRYPTO.DEV_KEY_ADDR0_CTL */
|
||||
#define CRYPTO_V2_DEV_KEY_ADDR0_CTL_VALID_Pos 31UL
|
||||
#define CRYPTO_V2_DEV_KEY_ADDR0_CTL_VALID_Msk 0x80000000UL
|
||||
/* CRYPTO.DEV_KEY_ADDR0 */
|
||||
#define CRYPTO_V2_DEV_KEY_ADDR0_ADDR32_Pos 0UL
|
||||
#define CRYPTO_V2_DEV_KEY_ADDR0_ADDR32_Msk 0xFFFFFFFFUL
|
||||
/* CRYPTO.DEV_KEY_ADDR1_CTL */
|
||||
#define CRYPTO_V2_DEV_KEY_ADDR1_CTL_VALID_Pos 31UL
|
||||
#define CRYPTO_V2_DEV_KEY_ADDR1_CTL_VALID_Msk 0x80000000UL
|
||||
/* CRYPTO.DEV_KEY_ADDR1 */
|
||||
#define CRYPTO_V2_DEV_KEY_ADDR1_ADDR32_Pos 0UL
|
||||
#define CRYPTO_V2_DEV_KEY_ADDR1_ADDR32_Msk 0xFFFFFFFFUL
|
||||
/* CRYPTO.DEV_KEY_STATUS */
|
||||
#define CRYPTO_V2_DEV_KEY_STATUS_LOADED_Pos 0UL
|
||||
#define CRYPTO_V2_DEV_KEY_STATUS_LOADED_Msk 0x1UL
|
||||
/* CRYPTO.DEV_KEY_CTL0 */
|
||||
#define CRYPTO_V2_DEV_KEY_CTL0_ALLOWED_Pos 0UL
|
||||
#define CRYPTO_V2_DEV_KEY_CTL0_ALLOWED_Msk 0x1UL
|
||||
/* CRYPTO.DEV_KEY_CTL1 */
|
||||
#define CRYPTO_V2_DEV_KEY_CTL1_ALLOWED_Pos 0UL
|
||||
#define CRYPTO_V2_DEV_KEY_CTL1_ALLOWED_Msk 0x1UL
|
||||
/* CRYPTO.MEM_BUFF */
|
||||
#define CRYPTO_V2_MEM_BUFF_DATA32_Pos 0UL
|
||||
#define CRYPTO_V2_MEM_BUFF_DATA32_Msk 0xFFFFFFFFUL
|
||||
|
||||
|
||||
#endif /* _CYIP_CRYPTO_V2_H_ */
|
||||
|
||||
|
||||
/* [] END OF FILE */
|
||||
|
|
@ -1,478 +0,0 @@
|
|||
/***************************************************************************//**
|
||||
* \file cyip_csd.h
|
||||
*
|
||||
* \brief
|
||||
* CSD IP definitions
|
||||
*
|
||||
* \note
|
||||
* Generator version: 1.3.0.1146
|
||||
* Database revision: rev#1050929
|
||||
*
|
||||
********************************************************************************
|
||||
* \copyright
|
||||
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
|
||||
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _CYIP_CSD_H_
|
||||
#define _CYIP_CSD_H_
|
||||
|
||||
#include "cyip_headers.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* CSD
|
||||
*******************************************************************************/
|
||||
|
||||
#define CSD_SECTION_SIZE 0x00001000UL
|
||||
|
||||
/**
|
||||
* \brief Capsense Controller (CSD)
|
||||
*/
|
||||
typedef struct {
|
||||
__IOM uint32_t CONFIG; /*!< 0x00000000 Configuration and Control */
|
||||
__IOM uint32_t SPARE; /*!< 0x00000004 Spare MMIO */
|
||||
__IM uint32_t RESERVED[30];
|
||||
__IM uint32_t STATUS; /*!< 0x00000080 Status Register */
|
||||
__IM uint32_t STAT_SEQ; /*!< 0x00000084 Current Sequencer status */
|
||||
__IM uint32_t STAT_CNTS; /*!< 0x00000088 Current status counts */
|
||||
__IM uint32_t STAT_HCNT; /*!< 0x0000008C Current count of the HSCMP counter */
|
||||
__IM uint32_t RESERVED1[16];
|
||||
__IM uint32_t RESULT_VAL1; /*!< 0x000000D0 Result CSD/CSX accumulation counter value 1 */
|
||||
__IM uint32_t RESULT_VAL2; /*!< 0x000000D4 Result CSX accumulation counter value 2 */
|
||||
__IM uint32_t RESERVED2[2];
|
||||
__IM uint32_t ADC_RES; /*!< 0x000000E0 ADC measurement */
|
||||
__IM uint32_t RESERVED3[3];
|
||||
__IOM uint32_t INTR; /*!< 0x000000F0 CSD Interrupt Request Register */
|
||||
__IOM uint32_t INTR_SET; /*!< 0x000000F4 CSD Interrupt set register */
|
||||
__IOM uint32_t INTR_MASK; /*!< 0x000000F8 CSD Interrupt mask register */
|
||||
__IM uint32_t INTR_MASKED; /*!< 0x000000FC CSD Interrupt masked register */
|
||||
__IM uint32_t RESERVED4[32];
|
||||
__IOM uint32_t HSCMP; /*!< 0x00000180 High Speed Comparator configuration */
|
||||
__IOM uint32_t AMBUF; /*!< 0x00000184 Reference Generator configuration */
|
||||
__IOM uint32_t REFGEN; /*!< 0x00000188 Reference Generator configuration */
|
||||
__IOM uint32_t CSDCMP; /*!< 0x0000018C CSD Comparator configuration */
|
||||
__IM uint32_t RESERVED5[24];
|
||||
__IOM uint32_t SW_RES; /*!< 0x000001F0 Switch Resistance configuration */
|
||||
__IM uint32_t RESERVED6[3];
|
||||
__IOM uint32_t SENSE_PERIOD; /*!< 0x00000200 Sense clock period */
|
||||
__IOM uint32_t SENSE_DUTY; /*!< 0x00000204 Sense clock duty cycle */
|
||||
__IM uint32_t RESERVED7[30];
|
||||
__IOM uint32_t SW_HS_P_SEL; /*!< 0x00000280 HSCMP Pos input switch Waveform selection */
|
||||
__IOM uint32_t SW_HS_N_SEL; /*!< 0x00000284 HSCMP Neg input switch Waveform selection */
|
||||
__IOM uint32_t SW_SHIELD_SEL; /*!< 0x00000288 Shielding switches Waveform selection */
|
||||
__IM uint32_t RESERVED8;
|
||||
__IOM uint32_t SW_AMUXBUF_SEL; /*!< 0x00000290 Amuxbuffer switches Waveform selection */
|
||||
__IOM uint32_t SW_BYP_SEL; /*!< 0x00000294 AMUXBUS bypass switches Waveform selection */
|
||||
__IM uint32_t RESERVED9[2];
|
||||
__IOM uint32_t SW_CMP_P_SEL; /*!< 0x000002A0 CSDCMP Pos Switch Waveform selection */
|
||||
__IOM uint32_t SW_CMP_N_SEL; /*!< 0x000002A4 CSDCMP Neg Switch Waveform selection */
|
||||
__IOM uint32_t SW_REFGEN_SEL; /*!< 0x000002A8 Reference Generator Switch Waveform selection */
|
||||
__IM uint32_t RESERVED10;
|
||||
__IOM uint32_t SW_FW_MOD_SEL; /*!< 0x000002B0 Full Wave Cmod Switch Waveform selection */
|
||||
__IOM uint32_t SW_FW_TANK_SEL; /*!< 0x000002B4 Full Wave Csh_tank Switch Waveform selection */
|
||||
__IM uint32_t RESERVED11[2];
|
||||
__IOM uint32_t SW_DSI_SEL; /*!< 0x000002C0 DSI output switch control Waveform selection */
|
||||
__IM uint32_t RESERVED12[3];
|
||||
__IOM uint32_t IO_SEL; /*!< 0x000002D0 IO output control Waveform selection */
|
||||
__IM uint32_t RESERVED13[11];
|
||||
__IOM uint32_t SEQ_TIME; /*!< 0x00000300 Sequencer Timing */
|
||||
__IM uint32_t RESERVED14[3];
|
||||
__IOM uint32_t SEQ_INIT_CNT; /*!< 0x00000310 Sequencer Initial conversion and sample counts */
|
||||
__IOM uint32_t SEQ_NORM_CNT; /*!< 0x00000314 Sequencer Normal conversion and sample counts */
|
||||
__IM uint32_t RESERVED15[2];
|
||||
__IOM uint32_t ADC_CTL; /*!< 0x00000320 ADC Control */
|
||||
__IM uint32_t RESERVED16[7];
|
||||
__IOM uint32_t SEQ_START; /*!< 0x00000340 Sequencer start */
|
||||
__IM uint32_t RESERVED17[47];
|
||||
__IOM uint32_t IDACA; /*!< 0x00000400 IDACA Configuration */
|
||||
__IM uint32_t RESERVED18[63];
|
||||
__IOM uint32_t IDACB; /*!< 0x00000500 IDACB Configuration */
|
||||
} CSD_V1_Type; /*!< Size = 1284 (0x504) */
|
||||
|
||||
|
||||
/* CSD.CONFIG */
|
||||
#define CSD_CONFIG_IREF_SEL_Pos 0UL
|
||||
#define CSD_CONFIG_IREF_SEL_Msk 0x1UL
|
||||
#define CSD_CONFIG_FILTER_DELAY_Pos 4UL
|
||||
#define CSD_CONFIG_FILTER_DELAY_Msk 0x1F0UL
|
||||
#define CSD_CONFIG_SHIELD_DELAY_Pos 10UL
|
||||
#define CSD_CONFIG_SHIELD_DELAY_Msk 0xC00UL
|
||||
#define CSD_CONFIG_SENSE_EN_Pos 12UL
|
||||
#define CSD_CONFIG_SENSE_EN_Msk 0x1000UL
|
||||
#define CSD_CONFIG_FULL_WAVE_Pos 17UL
|
||||
#define CSD_CONFIG_FULL_WAVE_Msk 0x20000UL
|
||||
#define CSD_CONFIG_MUTUAL_CAP_Pos 18UL
|
||||
#define CSD_CONFIG_MUTUAL_CAP_Msk 0x40000UL
|
||||
#define CSD_CONFIG_CSX_DUAL_CNT_Pos 19UL
|
||||
#define CSD_CONFIG_CSX_DUAL_CNT_Msk 0x80000UL
|
||||
#define CSD_CONFIG_DSI_COUNT_SEL_Pos 24UL
|
||||
#define CSD_CONFIG_DSI_COUNT_SEL_Msk 0x1000000UL
|
||||
#define CSD_CONFIG_DSI_SAMPLE_EN_Pos 25UL
|
||||
#define CSD_CONFIG_DSI_SAMPLE_EN_Msk 0x2000000UL
|
||||
#define CSD_CONFIG_SAMPLE_SYNC_Pos 26UL
|
||||
#define CSD_CONFIG_SAMPLE_SYNC_Msk 0x4000000UL
|
||||
#define CSD_CONFIG_DSI_SENSE_EN_Pos 27UL
|
||||
#define CSD_CONFIG_DSI_SENSE_EN_Msk 0x8000000UL
|
||||
#define CSD_CONFIG_LP_MODE_Pos 30UL
|
||||
#define CSD_CONFIG_LP_MODE_Msk 0x40000000UL
|
||||
#define CSD_CONFIG_ENABLE_Pos 31UL
|
||||
#define CSD_CONFIG_ENABLE_Msk 0x80000000UL
|
||||
/* CSD.SPARE */
|
||||
#define CSD_SPARE_SPARE_Pos 0UL
|
||||
#define CSD_SPARE_SPARE_Msk 0xFUL
|
||||
/* CSD.STATUS */
|
||||
#define CSD_STATUS_CSD_SENSE_Pos 1UL
|
||||
#define CSD_STATUS_CSD_SENSE_Msk 0x2UL
|
||||
#define CSD_STATUS_HSCMP_OUT_Pos 2UL
|
||||
#define CSD_STATUS_HSCMP_OUT_Msk 0x4UL
|
||||
#define CSD_STATUS_CSDCMP_OUT_Pos 3UL
|
||||
#define CSD_STATUS_CSDCMP_OUT_Msk 0x8UL
|
||||
/* CSD.STAT_SEQ */
|
||||
#define CSD_STAT_SEQ_SEQ_STATE_Pos 0UL
|
||||
#define CSD_STAT_SEQ_SEQ_STATE_Msk 0x7UL
|
||||
#define CSD_STAT_SEQ_ADC_STATE_Pos 16UL
|
||||
#define CSD_STAT_SEQ_ADC_STATE_Msk 0x70000UL
|
||||
/* CSD.STAT_CNTS */
|
||||
#define CSD_STAT_CNTS_NUM_CONV_Pos 0UL
|
||||
#define CSD_STAT_CNTS_NUM_CONV_Msk 0xFFFFUL
|
||||
/* CSD.STAT_HCNT */
|
||||
#define CSD_STAT_HCNT_CNT_Pos 0UL
|
||||
#define CSD_STAT_HCNT_CNT_Msk 0xFFFFUL
|
||||
/* CSD.RESULT_VAL1 */
|
||||
#define CSD_RESULT_VAL1_VALUE_Pos 0UL
|
||||
#define CSD_RESULT_VAL1_VALUE_Msk 0xFFFFUL
|
||||
#define CSD_RESULT_VAL1_BAD_CONVS_Pos 16UL
|
||||
#define CSD_RESULT_VAL1_BAD_CONVS_Msk 0xFF0000UL
|
||||
/* CSD.RESULT_VAL2 */
|
||||
#define CSD_RESULT_VAL2_VALUE_Pos 0UL
|
||||
#define CSD_RESULT_VAL2_VALUE_Msk 0xFFFFUL
|
||||
/* CSD.ADC_RES */
|
||||
#define CSD_ADC_RES_VIN_CNT_Pos 0UL
|
||||
#define CSD_ADC_RES_VIN_CNT_Msk 0xFFFFUL
|
||||
#define CSD_ADC_RES_HSCMP_POL_Pos 16UL
|
||||
#define CSD_ADC_RES_HSCMP_POL_Msk 0x10000UL
|
||||
#define CSD_ADC_RES_ADC_OVERFLOW_Pos 30UL
|
||||
#define CSD_ADC_RES_ADC_OVERFLOW_Msk 0x40000000UL
|
||||
#define CSD_ADC_RES_ADC_ABORT_Pos 31UL
|
||||
#define CSD_ADC_RES_ADC_ABORT_Msk 0x80000000UL
|
||||
/* CSD.INTR */
|
||||
#define CSD_INTR_SAMPLE_Pos 1UL
|
||||
#define CSD_INTR_SAMPLE_Msk 0x2UL
|
||||
#define CSD_INTR_INIT_Pos 2UL
|
||||
#define CSD_INTR_INIT_Msk 0x4UL
|
||||
#define CSD_INTR_ADC_RES_Pos 8UL
|
||||
#define CSD_INTR_ADC_RES_Msk 0x100UL
|
||||
/* CSD.INTR_SET */
|
||||
#define CSD_INTR_SET_SAMPLE_Pos 1UL
|
||||
#define CSD_INTR_SET_SAMPLE_Msk 0x2UL
|
||||
#define CSD_INTR_SET_INIT_Pos 2UL
|
||||
#define CSD_INTR_SET_INIT_Msk 0x4UL
|
||||
#define CSD_INTR_SET_ADC_RES_Pos 8UL
|
||||
#define CSD_INTR_SET_ADC_RES_Msk 0x100UL
|
||||
/* CSD.INTR_MASK */
|
||||
#define CSD_INTR_MASK_SAMPLE_Pos 1UL
|
||||
#define CSD_INTR_MASK_SAMPLE_Msk 0x2UL
|
||||
#define CSD_INTR_MASK_INIT_Pos 2UL
|
||||
#define CSD_INTR_MASK_INIT_Msk 0x4UL
|
||||
#define CSD_INTR_MASK_ADC_RES_Pos 8UL
|
||||
#define CSD_INTR_MASK_ADC_RES_Msk 0x100UL
|
||||
/* CSD.INTR_MASKED */
|
||||
#define CSD_INTR_MASKED_SAMPLE_Pos 1UL
|
||||
#define CSD_INTR_MASKED_SAMPLE_Msk 0x2UL
|
||||
#define CSD_INTR_MASKED_INIT_Pos 2UL
|
||||
#define CSD_INTR_MASKED_INIT_Msk 0x4UL
|
||||
#define CSD_INTR_MASKED_ADC_RES_Pos 8UL
|
||||
#define CSD_INTR_MASKED_ADC_RES_Msk 0x100UL
|
||||
/* CSD.HSCMP */
|
||||
#define CSD_HSCMP_HSCMP_EN_Pos 0UL
|
||||
#define CSD_HSCMP_HSCMP_EN_Msk 0x1UL
|
||||
#define CSD_HSCMP_HSCMP_INVERT_Pos 4UL
|
||||
#define CSD_HSCMP_HSCMP_INVERT_Msk 0x10UL
|
||||
#define CSD_HSCMP_AZ_EN_Pos 31UL
|
||||
#define CSD_HSCMP_AZ_EN_Msk 0x80000000UL
|
||||
/* CSD.AMBUF */
|
||||
#define CSD_AMBUF_PWR_MODE_Pos 0UL
|
||||
#define CSD_AMBUF_PWR_MODE_Msk 0x3UL
|
||||
/* CSD.REFGEN */
|
||||
#define CSD_REFGEN_REFGEN_EN_Pos 0UL
|
||||
#define CSD_REFGEN_REFGEN_EN_Msk 0x1UL
|
||||
#define CSD_REFGEN_BYPASS_Pos 4UL
|
||||
#define CSD_REFGEN_BYPASS_Msk 0x10UL
|
||||
#define CSD_REFGEN_VDDA_EN_Pos 5UL
|
||||
#define CSD_REFGEN_VDDA_EN_Msk 0x20UL
|
||||
#define CSD_REFGEN_RES_EN_Pos 6UL
|
||||
#define CSD_REFGEN_RES_EN_Msk 0x40UL
|
||||
#define CSD_REFGEN_GAIN_Pos 8UL
|
||||
#define CSD_REFGEN_GAIN_Msk 0x1F00UL
|
||||
#define CSD_REFGEN_VREFLO_SEL_Pos 16UL
|
||||
#define CSD_REFGEN_VREFLO_SEL_Msk 0x1F0000UL
|
||||
#define CSD_REFGEN_VREFLO_INT_Pos 23UL
|
||||
#define CSD_REFGEN_VREFLO_INT_Msk 0x800000UL
|
||||
/* CSD.CSDCMP */
|
||||
#define CSD_CSDCMP_CSDCMP_EN_Pos 0UL
|
||||
#define CSD_CSDCMP_CSDCMP_EN_Msk 0x1UL
|
||||
#define CSD_CSDCMP_POLARITY_SEL_Pos 4UL
|
||||
#define CSD_CSDCMP_POLARITY_SEL_Msk 0x30UL
|
||||
#define CSD_CSDCMP_CMP_PHASE_Pos 8UL
|
||||
#define CSD_CSDCMP_CMP_PHASE_Msk 0x300UL
|
||||
#define CSD_CSDCMP_CMP_MODE_Pos 28UL
|
||||
#define CSD_CSDCMP_CMP_MODE_Msk 0x10000000UL
|
||||
#define CSD_CSDCMP_FEEDBACK_MODE_Pos 29UL
|
||||
#define CSD_CSDCMP_FEEDBACK_MODE_Msk 0x20000000UL
|
||||
#define CSD_CSDCMP_AZ_EN_Pos 31UL
|
||||
#define CSD_CSDCMP_AZ_EN_Msk 0x80000000UL
|
||||
/* CSD.SW_RES */
|
||||
#define CSD_SW_RES_RES_HCAV_Pos 0UL
|
||||
#define CSD_SW_RES_RES_HCAV_Msk 0x3UL
|
||||
#define CSD_SW_RES_RES_HCAG_Pos 2UL
|
||||
#define CSD_SW_RES_RES_HCAG_Msk 0xCUL
|
||||
#define CSD_SW_RES_RES_HCBV_Pos 4UL
|
||||
#define CSD_SW_RES_RES_HCBV_Msk 0x30UL
|
||||
#define CSD_SW_RES_RES_HCBG_Pos 6UL
|
||||
#define CSD_SW_RES_RES_HCBG_Msk 0xC0UL
|
||||
#define CSD_SW_RES_RES_F1PM_Pos 16UL
|
||||
#define CSD_SW_RES_RES_F1PM_Msk 0x30000UL
|
||||
#define CSD_SW_RES_RES_F2PT_Pos 18UL
|
||||
#define CSD_SW_RES_RES_F2PT_Msk 0xC0000UL
|
||||
/* CSD.SENSE_PERIOD */
|
||||
#define CSD_SENSE_PERIOD_SENSE_DIV_Pos 0UL
|
||||
#define CSD_SENSE_PERIOD_SENSE_DIV_Msk 0xFFFUL
|
||||
#define CSD_SENSE_PERIOD_LFSR_SIZE_Pos 16UL
|
||||
#define CSD_SENSE_PERIOD_LFSR_SIZE_Msk 0x70000UL
|
||||
#define CSD_SENSE_PERIOD_LFSR_SCALE_Pos 20UL
|
||||
#define CSD_SENSE_PERIOD_LFSR_SCALE_Msk 0xF00000UL
|
||||
#define CSD_SENSE_PERIOD_LFSR_CLEAR_Pos 24UL
|
||||
#define CSD_SENSE_PERIOD_LFSR_CLEAR_Msk 0x1000000UL
|
||||
#define CSD_SENSE_PERIOD_SEL_LFSR_MSB_Pos 25UL
|
||||
#define CSD_SENSE_PERIOD_SEL_LFSR_MSB_Msk 0x2000000UL
|
||||
#define CSD_SENSE_PERIOD_LFSR_BITS_Pos 26UL
|
||||
#define CSD_SENSE_PERIOD_LFSR_BITS_Msk 0xC000000UL
|
||||
/* CSD.SENSE_DUTY */
|
||||
#define CSD_SENSE_DUTY_SENSE_WIDTH_Pos 0UL
|
||||
#define CSD_SENSE_DUTY_SENSE_WIDTH_Msk 0xFFFUL
|
||||
#define CSD_SENSE_DUTY_SENSE_POL_Pos 16UL
|
||||
#define CSD_SENSE_DUTY_SENSE_POL_Msk 0x10000UL
|
||||
#define CSD_SENSE_DUTY_OVERLAP_PHI1_Pos 18UL
|
||||
#define CSD_SENSE_DUTY_OVERLAP_PHI1_Msk 0x40000UL
|
||||
#define CSD_SENSE_DUTY_OVERLAP_PHI2_Pos 19UL
|
||||
#define CSD_SENSE_DUTY_OVERLAP_PHI2_Msk 0x80000UL
|
||||
/* CSD.SW_HS_P_SEL */
|
||||
#define CSD_SW_HS_P_SEL_SW_HMPM_Pos 0UL
|
||||
#define CSD_SW_HS_P_SEL_SW_HMPM_Msk 0x1UL
|
||||
#define CSD_SW_HS_P_SEL_SW_HMPT_Pos 4UL
|
||||
#define CSD_SW_HS_P_SEL_SW_HMPT_Msk 0x10UL
|
||||
#define CSD_SW_HS_P_SEL_SW_HMPS_Pos 8UL
|
||||
#define CSD_SW_HS_P_SEL_SW_HMPS_Msk 0x100UL
|
||||
#define CSD_SW_HS_P_SEL_SW_HMMA_Pos 12UL
|
||||
#define CSD_SW_HS_P_SEL_SW_HMMA_Msk 0x1000UL
|
||||
#define CSD_SW_HS_P_SEL_SW_HMMB_Pos 16UL
|
||||
#define CSD_SW_HS_P_SEL_SW_HMMB_Msk 0x10000UL
|
||||
#define CSD_SW_HS_P_SEL_SW_HMCA_Pos 20UL
|
||||
#define CSD_SW_HS_P_SEL_SW_HMCA_Msk 0x100000UL
|
||||
#define CSD_SW_HS_P_SEL_SW_HMCB_Pos 24UL
|
||||
#define CSD_SW_HS_P_SEL_SW_HMCB_Msk 0x1000000UL
|
||||
#define CSD_SW_HS_P_SEL_SW_HMRH_Pos 28UL
|
||||
#define CSD_SW_HS_P_SEL_SW_HMRH_Msk 0x10000000UL
|
||||
/* CSD.SW_HS_N_SEL */
|
||||
#define CSD_SW_HS_N_SEL_SW_HCCC_Pos 16UL
|
||||
#define CSD_SW_HS_N_SEL_SW_HCCC_Msk 0x10000UL
|
||||
#define CSD_SW_HS_N_SEL_SW_HCCD_Pos 20UL
|
||||
#define CSD_SW_HS_N_SEL_SW_HCCD_Msk 0x100000UL
|
||||
#define CSD_SW_HS_N_SEL_SW_HCRH_Pos 24UL
|
||||
#define CSD_SW_HS_N_SEL_SW_HCRH_Msk 0x7000000UL
|
||||
#define CSD_SW_HS_N_SEL_SW_HCRL_Pos 28UL
|
||||
#define CSD_SW_HS_N_SEL_SW_HCRL_Msk 0x70000000UL
|
||||
/* CSD.SW_SHIELD_SEL */
|
||||
#define CSD_SW_SHIELD_SEL_SW_HCAV_Pos 0UL
|
||||
#define CSD_SW_SHIELD_SEL_SW_HCAV_Msk 0x7UL
|
||||
#define CSD_SW_SHIELD_SEL_SW_HCAG_Pos 4UL
|
||||
#define CSD_SW_SHIELD_SEL_SW_HCAG_Msk 0x70UL
|
||||
#define CSD_SW_SHIELD_SEL_SW_HCBV_Pos 8UL
|
||||
#define CSD_SW_SHIELD_SEL_SW_HCBV_Msk 0x700UL
|
||||
#define CSD_SW_SHIELD_SEL_SW_HCBG_Pos 12UL
|
||||
#define CSD_SW_SHIELD_SEL_SW_HCBG_Msk 0x7000UL
|
||||
#define CSD_SW_SHIELD_SEL_SW_HCCV_Pos 16UL
|
||||
#define CSD_SW_SHIELD_SEL_SW_HCCV_Msk 0x10000UL
|
||||
#define CSD_SW_SHIELD_SEL_SW_HCCG_Pos 20UL
|
||||
#define CSD_SW_SHIELD_SEL_SW_HCCG_Msk 0x100000UL
|
||||
/* CSD.SW_AMUXBUF_SEL */
|
||||
#define CSD_SW_AMUXBUF_SEL_SW_IRBY_Pos 4UL
|
||||
#define CSD_SW_AMUXBUF_SEL_SW_IRBY_Msk 0x10UL
|
||||
#define CSD_SW_AMUXBUF_SEL_SW_IRLB_Pos 8UL
|
||||
#define CSD_SW_AMUXBUF_SEL_SW_IRLB_Msk 0x100UL
|
||||
#define CSD_SW_AMUXBUF_SEL_SW_ICA_Pos 12UL
|
||||
#define CSD_SW_AMUXBUF_SEL_SW_ICA_Msk 0x1000UL
|
||||
#define CSD_SW_AMUXBUF_SEL_SW_ICB_Pos 16UL
|
||||
#define CSD_SW_AMUXBUF_SEL_SW_ICB_Msk 0x70000UL
|
||||
#define CSD_SW_AMUXBUF_SEL_SW_IRLI_Pos 20UL
|
||||
#define CSD_SW_AMUXBUF_SEL_SW_IRLI_Msk 0x100000UL
|
||||
#define CSD_SW_AMUXBUF_SEL_SW_IRH_Pos 24UL
|
||||
#define CSD_SW_AMUXBUF_SEL_SW_IRH_Msk 0x1000000UL
|
||||
#define CSD_SW_AMUXBUF_SEL_SW_IRL_Pos 28UL
|
||||
#define CSD_SW_AMUXBUF_SEL_SW_IRL_Msk 0x10000000UL
|
||||
/* CSD.SW_BYP_SEL */
|
||||
#define CSD_SW_BYP_SEL_SW_BYA_Pos 12UL
|
||||
#define CSD_SW_BYP_SEL_SW_BYA_Msk 0x1000UL
|
||||
#define CSD_SW_BYP_SEL_SW_BYB_Pos 16UL
|
||||
#define CSD_SW_BYP_SEL_SW_BYB_Msk 0x10000UL
|
||||
#define CSD_SW_BYP_SEL_SW_CBCC_Pos 20UL
|
||||
#define CSD_SW_BYP_SEL_SW_CBCC_Msk 0x100000UL
|
||||
/* CSD.SW_CMP_P_SEL */
|
||||
#define CSD_SW_CMP_P_SEL_SW_SFPM_Pos 0UL
|
||||
#define CSD_SW_CMP_P_SEL_SW_SFPM_Msk 0x7UL
|
||||
#define CSD_SW_CMP_P_SEL_SW_SFPT_Pos 4UL
|
||||
#define CSD_SW_CMP_P_SEL_SW_SFPT_Msk 0x70UL
|
||||
#define CSD_SW_CMP_P_SEL_SW_SFPS_Pos 8UL
|
||||
#define CSD_SW_CMP_P_SEL_SW_SFPS_Msk 0x700UL
|
||||
#define CSD_SW_CMP_P_SEL_SW_SFMA_Pos 12UL
|
||||
#define CSD_SW_CMP_P_SEL_SW_SFMA_Msk 0x1000UL
|
||||
#define CSD_SW_CMP_P_SEL_SW_SFMB_Pos 16UL
|
||||
#define CSD_SW_CMP_P_SEL_SW_SFMB_Msk 0x10000UL
|
||||
#define CSD_SW_CMP_P_SEL_SW_SFCA_Pos 20UL
|
||||
#define CSD_SW_CMP_P_SEL_SW_SFCA_Msk 0x100000UL
|
||||
#define CSD_SW_CMP_P_SEL_SW_SFCB_Pos 24UL
|
||||
#define CSD_SW_CMP_P_SEL_SW_SFCB_Msk 0x1000000UL
|
||||
/* CSD.SW_CMP_N_SEL */
|
||||
#define CSD_SW_CMP_N_SEL_SW_SCRH_Pos 24UL
|
||||
#define CSD_SW_CMP_N_SEL_SW_SCRH_Msk 0x7000000UL
|
||||
#define CSD_SW_CMP_N_SEL_SW_SCRL_Pos 28UL
|
||||
#define CSD_SW_CMP_N_SEL_SW_SCRL_Msk 0x70000000UL
|
||||
/* CSD.SW_REFGEN_SEL */
|
||||
#define CSD_SW_REFGEN_SEL_SW_IAIB_Pos 0UL
|
||||
#define CSD_SW_REFGEN_SEL_SW_IAIB_Msk 0x1UL
|
||||
#define CSD_SW_REFGEN_SEL_SW_IBCB_Pos 4UL
|
||||
#define CSD_SW_REFGEN_SEL_SW_IBCB_Msk 0x10UL
|
||||
#define CSD_SW_REFGEN_SEL_SW_SGMB_Pos 16UL
|
||||
#define CSD_SW_REFGEN_SEL_SW_SGMB_Msk 0x10000UL
|
||||
#define CSD_SW_REFGEN_SEL_SW_SGRP_Pos 20UL
|
||||
#define CSD_SW_REFGEN_SEL_SW_SGRP_Msk 0x100000UL
|
||||
#define CSD_SW_REFGEN_SEL_SW_SGRE_Pos 24UL
|
||||
#define CSD_SW_REFGEN_SEL_SW_SGRE_Msk 0x1000000UL
|
||||
#define CSD_SW_REFGEN_SEL_SW_SGR_Pos 28UL
|
||||
#define CSD_SW_REFGEN_SEL_SW_SGR_Msk 0x10000000UL
|
||||
/* CSD.SW_FW_MOD_SEL */
|
||||
#define CSD_SW_FW_MOD_SEL_SW_F1PM_Pos 0UL
|
||||
#define CSD_SW_FW_MOD_SEL_SW_F1PM_Msk 0x1UL
|
||||
#define CSD_SW_FW_MOD_SEL_SW_F1MA_Pos 8UL
|
||||
#define CSD_SW_FW_MOD_SEL_SW_F1MA_Msk 0x700UL
|
||||
#define CSD_SW_FW_MOD_SEL_SW_F1CA_Pos 16UL
|
||||
#define CSD_SW_FW_MOD_SEL_SW_F1CA_Msk 0x70000UL
|
||||
#define CSD_SW_FW_MOD_SEL_SW_C1CC_Pos 20UL
|
||||
#define CSD_SW_FW_MOD_SEL_SW_C1CC_Msk 0x100000UL
|
||||
#define CSD_SW_FW_MOD_SEL_SW_C1CD_Pos 24UL
|
||||
#define CSD_SW_FW_MOD_SEL_SW_C1CD_Msk 0x1000000UL
|
||||
#define CSD_SW_FW_MOD_SEL_SW_C1F1_Pos 28UL
|
||||
#define CSD_SW_FW_MOD_SEL_SW_C1F1_Msk 0x10000000UL
|
||||
/* CSD.SW_FW_TANK_SEL */
|
||||
#define CSD_SW_FW_TANK_SEL_SW_F2PT_Pos 4UL
|
||||
#define CSD_SW_FW_TANK_SEL_SW_F2PT_Msk 0x10UL
|
||||
#define CSD_SW_FW_TANK_SEL_SW_F2MA_Pos 8UL
|
||||
#define CSD_SW_FW_TANK_SEL_SW_F2MA_Msk 0x700UL
|
||||
#define CSD_SW_FW_TANK_SEL_SW_F2CA_Pos 12UL
|
||||
#define CSD_SW_FW_TANK_SEL_SW_F2CA_Msk 0x7000UL
|
||||
#define CSD_SW_FW_TANK_SEL_SW_F2CB_Pos 16UL
|
||||
#define CSD_SW_FW_TANK_SEL_SW_F2CB_Msk 0x70000UL
|
||||
#define CSD_SW_FW_TANK_SEL_SW_C2CC_Pos 20UL
|
||||
#define CSD_SW_FW_TANK_SEL_SW_C2CC_Msk 0x100000UL
|
||||
#define CSD_SW_FW_TANK_SEL_SW_C2CD_Pos 24UL
|
||||
#define CSD_SW_FW_TANK_SEL_SW_C2CD_Msk 0x1000000UL
|
||||
#define CSD_SW_FW_TANK_SEL_SW_C2F2_Pos 28UL
|
||||
#define CSD_SW_FW_TANK_SEL_SW_C2F2_Msk 0x10000000UL
|
||||
/* CSD.SW_DSI_SEL */
|
||||
#define CSD_SW_DSI_SEL_DSI_CSH_TANK_Pos 0UL
|
||||
#define CSD_SW_DSI_SEL_DSI_CSH_TANK_Msk 0xFUL
|
||||
#define CSD_SW_DSI_SEL_DSI_CMOD_Pos 4UL
|
||||
#define CSD_SW_DSI_SEL_DSI_CMOD_Msk 0xF0UL
|
||||
/* CSD.IO_SEL */
|
||||
#define CSD_IO_SEL_CSD_TX_OUT_Pos 0UL
|
||||
#define CSD_IO_SEL_CSD_TX_OUT_Msk 0xFUL
|
||||
#define CSD_IO_SEL_CSD_TX_OUT_EN_Pos 4UL
|
||||
#define CSD_IO_SEL_CSD_TX_OUT_EN_Msk 0xF0UL
|
||||
#define CSD_IO_SEL_CSD_TX_AMUXB_EN_Pos 12UL
|
||||
#define CSD_IO_SEL_CSD_TX_AMUXB_EN_Msk 0xF000UL
|
||||
#define CSD_IO_SEL_CSD_TX_N_OUT_Pos 16UL
|
||||
#define CSD_IO_SEL_CSD_TX_N_OUT_Msk 0xF0000UL
|
||||
#define CSD_IO_SEL_CSD_TX_N_OUT_EN_Pos 20UL
|
||||
#define CSD_IO_SEL_CSD_TX_N_OUT_EN_Msk 0xF00000UL
|
||||
#define CSD_IO_SEL_CSD_TX_N_AMUXA_EN_Pos 24UL
|
||||
#define CSD_IO_SEL_CSD_TX_N_AMUXA_EN_Msk 0xF000000UL
|
||||
/* CSD.SEQ_TIME */
|
||||
#define CSD_SEQ_TIME_AZ_TIME_Pos 0UL
|
||||
#define CSD_SEQ_TIME_AZ_TIME_Msk 0xFFUL
|
||||
/* CSD.SEQ_INIT_CNT */
|
||||
#define CSD_SEQ_INIT_CNT_CONV_CNT_Pos 0UL
|
||||
#define CSD_SEQ_INIT_CNT_CONV_CNT_Msk 0xFFFFUL
|
||||
/* CSD.SEQ_NORM_CNT */
|
||||
#define CSD_SEQ_NORM_CNT_CONV_CNT_Pos 0UL
|
||||
#define CSD_SEQ_NORM_CNT_CONV_CNT_Msk 0xFFFFUL
|
||||
/* CSD.ADC_CTL */
|
||||
#define CSD_ADC_CTL_ADC_TIME_Pos 0UL
|
||||
#define CSD_ADC_CTL_ADC_TIME_Msk 0xFFUL
|
||||
#define CSD_ADC_CTL_ADC_MODE_Pos 16UL
|
||||
#define CSD_ADC_CTL_ADC_MODE_Msk 0x30000UL
|
||||
/* CSD.SEQ_START */
|
||||
#define CSD_SEQ_START_START_Pos 0UL
|
||||
#define CSD_SEQ_START_START_Msk 0x1UL
|
||||
#define CSD_SEQ_START_SEQ_MODE_Pos 1UL
|
||||
#define CSD_SEQ_START_SEQ_MODE_Msk 0x2UL
|
||||
#define CSD_SEQ_START_ABORT_Pos 3UL
|
||||
#define CSD_SEQ_START_ABORT_Msk 0x8UL
|
||||
#define CSD_SEQ_START_DSI_START_EN_Pos 4UL
|
||||
#define CSD_SEQ_START_DSI_START_EN_Msk 0x10UL
|
||||
#define CSD_SEQ_START_AZ0_SKIP_Pos 8UL
|
||||
#define CSD_SEQ_START_AZ0_SKIP_Msk 0x100UL
|
||||
#define CSD_SEQ_START_AZ1_SKIP_Pos 9UL
|
||||
#define CSD_SEQ_START_AZ1_SKIP_Msk 0x200UL
|
||||
/* CSD.IDACA */
|
||||
#define CSD_IDACA_VAL_Pos 0UL
|
||||
#define CSD_IDACA_VAL_Msk 0x7FUL
|
||||
#define CSD_IDACA_POL_DYN_Pos 7UL
|
||||
#define CSD_IDACA_POL_DYN_Msk 0x80UL
|
||||
#define CSD_IDACA_POLARITY_Pos 8UL
|
||||
#define CSD_IDACA_POLARITY_Msk 0x300UL
|
||||
#define CSD_IDACA_BAL_MODE_Pos 10UL
|
||||
#define CSD_IDACA_BAL_MODE_Msk 0xC00UL
|
||||
#define CSD_IDACA_LEG1_MODE_Pos 16UL
|
||||
#define CSD_IDACA_LEG1_MODE_Msk 0x30000UL
|
||||
#define CSD_IDACA_LEG2_MODE_Pos 18UL
|
||||
#define CSD_IDACA_LEG2_MODE_Msk 0xC0000UL
|
||||
#define CSD_IDACA_DSI_CTRL_EN_Pos 21UL
|
||||
#define CSD_IDACA_DSI_CTRL_EN_Msk 0x200000UL
|
||||
#define CSD_IDACA_RANGE_Pos 22UL
|
||||
#define CSD_IDACA_RANGE_Msk 0xC00000UL
|
||||
#define CSD_IDACA_LEG1_EN_Pos 24UL
|
||||
#define CSD_IDACA_LEG1_EN_Msk 0x1000000UL
|
||||
#define CSD_IDACA_LEG2_EN_Pos 25UL
|
||||
#define CSD_IDACA_LEG2_EN_Msk 0x2000000UL
|
||||
/* CSD.IDACB */
|
||||
#define CSD_IDACB_VAL_Pos 0UL
|
||||
#define CSD_IDACB_VAL_Msk 0x7FUL
|
||||
#define CSD_IDACB_POL_DYN_Pos 7UL
|
||||
#define CSD_IDACB_POL_DYN_Msk 0x80UL
|
||||
#define CSD_IDACB_POLARITY_Pos 8UL
|
||||
#define CSD_IDACB_POLARITY_Msk 0x300UL
|
||||
#define CSD_IDACB_BAL_MODE_Pos 10UL
|
||||
#define CSD_IDACB_BAL_MODE_Msk 0xC00UL
|
||||
#define CSD_IDACB_LEG1_MODE_Pos 16UL
|
||||
#define CSD_IDACB_LEG1_MODE_Msk 0x30000UL
|
||||
#define CSD_IDACB_LEG2_MODE_Pos 18UL
|
||||
#define CSD_IDACB_LEG2_MODE_Msk 0xC0000UL
|
||||
#define CSD_IDACB_DSI_CTRL_EN_Pos 21UL
|
||||
#define CSD_IDACB_DSI_CTRL_EN_Msk 0x200000UL
|
||||
#define CSD_IDACB_RANGE_Pos 22UL
|
||||
#define CSD_IDACB_RANGE_Msk 0xC00000UL
|
||||
#define CSD_IDACB_LEG1_EN_Pos 24UL
|
||||
#define CSD_IDACB_LEG1_EN_Msk 0x1000000UL
|
||||
#define CSD_IDACB_LEG2_EN_Pos 25UL
|
||||
#define CSD_IDACB_LEG2_EN_Msk 0x2000000UL
|
||||
#define CSD_IDACB_LEG3_EN_Pos 26UL
|
||||
#define CSD_IDACB_LEG3_EN_Msk 0x4000000UL
|
||||
|
||||
|
||||
#endif /* _CYIP_CSD_H_ */
|
||||
|
||||
|
||||
/* [] END OF FILE */
|
||||
|
|
@ -1,288 +0,0 @@
|
|||
/***************************************************************************//**
|
||||
* \file cyip_ctbm.h
|
||||
*
|
||||
* \brief
|
||||
* CTBM IP definitions
|
||||
*
|
||||
* \note
|
||||
* Generator version: 1.3.0.1146
|
||||
* Database revision: rev#1050929
|
||||
*
|
||||
********************************************************************************
|
||||
* \copyright
|
||||
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
|
||||
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _CYIP_CTBM_H_
|
||||
#define _CYIP_CTBM_H_
|
||||
|
||||
#include "cyip_headers.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* CTBM
|
||||
*******************************************************************************/
|
||||
|
||||
#define CTBM_SECTION_SIZE 0x00010000UL
|
||||
|
||||
/**
|
||||
* \brief Continuous Time Block Mini (CTBM)
|
||||
*/
|
||||
typedef struct {
|
||||
__IOM uint32_t CTB_CTRL; /*!< 0x00000000 global CTB and power control */
|
||||
__IOM uint32_t OA_RES0_CTRL; /*!< 0x00000004 Opamp0 and resistor0 control */
|
||||
__IOM uint32_t OA_RES1_CTRL; /*!< 0x00000008 Opamp1 and resistor1 control */
|
||||
__IM uint32_t COMP_STAT; /*!< 0x0000000C Comparator status */
|
||||
__IM uint32_t RESERVED[4];
|
||||
__IOM uint32_t INTR; /*!< 0x00000020 Interrupt request register */
|
||||
__IOM uint32_t INTR_SET; /*!< 0x00000024 Interrupt request set register */
|
||||
__IOM uint32_t INTR_MASK; /*!< 0x00000028 Interrupt request mask */
|
||||
__IM uint32_t INTR_MASKED; /*!< 0x0000002C Interrupt request masked */
|
||||
__IM uint32_t RESERVED1[20];
|
||||
__IOM uint32_t OA0_SW; /*!< 0x00000080 Opamp0 switch control */
|
||||
__IOM uint32_t OA0_SW_CLEAR; /*!< 0x00000084 Opamp0 switch control clear */
|
||||
__IOM uint32_t OA1_SW; /*!< 0x00000088 Opamp1 switch control */
|
||||
__IOM uint32_t OA1_SW_CLEAR; /*!< 0x0000008C Opamp1 switch control clear */
|
||||
__IM uint32_t RESERVED2[4];
|
||||
__IOM uint32_t CTD_SW; /*!< 0x000000A0 CTDAC connection switch control */
|
||||
__IOM uint32_t CTD_SW_CLEAR; /*!< 0x000000A4 CTDAC connection switch control clear */
|
||||
__IM uint32_t RESERVED3[6];
|
||||
__IOM uint32_t CTB_SW_DS_CTRL; /*!< 0x000000C0 CTB bus switch control */
|
||||
__IOM uint32_t CTB_SW_SQ_CTRL; /*!< 0x000000C4 CTB bus switch Sar Sequencer control */
|
||||
__IM uint32_t CTB_SW_STATUS; /*!< 0x000000C8 CTB bus switch control status */
|
||||
__IM uint32_t RESERVED4[909];
|
||||
__IOM uint32_t OA0_OFFSET_TRIM; /*!< 0x00000F00 Opamp0 trim control */
|
||||
__IOM uint32_t OA0_SLOPE_OFFSET_TRIM; /*!< 0x00000F04 Opamp0 trim control */
|
||||
__IOM uint32_t OA0_COMP_TRIM; /*!< 0x00000F08 Opamp0 trim control */
|
||||
__IOM uint32_t OA1_OFFSET_TRIM; /*!< 0x00000F0C Opamp1 trim control */
|
||||
__IOM uint32_t OA1_SLOPE_OFFSET_TRIM; /*!< 0x00000F10 Opamp1 trim control */
|
||||
__IOM uint32_t OA1_COMP_TRIM; /*!< 0x00000F14 Opamp1 trim control */
|
||||
} CTBM_V1_Type; /*!< Size = 3864 (0xF18) */
|
||||
|
||||
|
||||
/* CTBM.CTB_CTRL */
|
||||
#define CTBM_CTB_CTRL_DEEPSLEEP_ON_Pos 30UL
|
||||
#define CTBM_CTB_CTRL_DEEPSLEEP_ON_Msk 0x40000000UL
|
||||
#define CTBM_CTB_CTRL_ENABLED_Pos 31UL
|
||||
#define CTBM_CTB_CTRL_ENABLED_Msk 0x80000000UL
|
||||
/* CTBM.OA_RES0_CTRL */
|
||||
#define CTBM_OA_RES0_CTRL_OA0_PWR_MODE_Pos 0UL
|
||||
#define CTBM_OA_RES0_CTRL_OA0_PWR_MODE_Msk 0x7UL
|
||||
#define CTBM_OA_RES0_CTRL_OA0_DRIVE_STR_SEL_Pos 3UL
|
||||
#define CTBM_OA_RES0_CTRL_OA0_DRIVE_STR_SEL_Msk 0x8UL
|
||||
#define CTBM_OA_RES0_CTRL_OA0_COMP_EN_Pos 4UL
|
||||
#define CTBM_OA_RES0_CTRL_OA0_COMP_EN_Msk 0x10UL
|
||||
#define CTBM_OA_RES0_CTRL_OA0_HYST_EN_Pos 5UL
|
||||
#define CTBM_OA_RES0_CTRL_OA0_HYST_EN_Msk 0x20UL
|
||||
#define CTBM_OA_RES0_CTRL_OA0_BYPASS_DSI_SYNC_Pos 6UL
|
||||
#define CTBM_OA_RES0_CTRL_OA0_BYPASS_DSI_SYNC_Msk 0x40UL
|
||||
#define CTBM_OA_RES0_CTRL_OA0_DSI_LEVEL_Pos 7UL
|
||||
#define CTBM_OA_RES0_CTRL_OA0_DSI_LEVEL_Msk 0x80UL
|
||||
#define CTBM_OA_RES0_CTRL_OA0_COMPINT_Pos 8UL
|
||||
#define CTBM_OA_RES0_CTRL_OA0_COMPINT_Msk 0x300UL
|
||||
#define CTBM_OA_RES0_CTRL_OA0_PUMP_EN_Pos 11UL
|
||||
#define CTBM_OA_RES0_CTRL_OA0_PUMP_EN_Msk 0x800UL
|
||||
#define CTBM_OA_RES0_CTRL_OA0_BOOST_EN_Pos 12UL
|
||||
#define CTBM_OA_RES0_CTRL_OA0_BOOST_EN_Msk 0x1000UL
|
||||
/* CTBM.OA_RES1_CTRL */
|
||||
#define CTBM_OA_RES1_CTRL_OA1_PWR_MODE_Pos 0UL
|
||||
#define CTBM_OA_RES1_CTRL_OA1_PWR_MODE_Msk 0x7UL
|
||||
#define CTBM_OA_RES1_CTRL_OA1_DRIVE_STR_SEL_Pos 3UL
|
||||
#define CTBM_OA_RES1_CTRL_OA1_DRIVE_STR_SEL_Msk 0x8UL
|
||||
#define CTBM_OA_RES1_CTRL_OA1_COMP_EN_Pos 4UL
|
||||
#define CTBM_OA_RES1_CTRL_OA1_COMP_EN_Msk 0x10UL
|
||||
#define CTBM_OA_RES1_CTRL_OA1_HYST_EN_Pos 5UL
|
||||
#define CTBM_OA_RES1_CTRL_OA1_HYST_EN_Msk 0x20UL
|
||||
#define CTBM_OA_RES1_CTRL_OA1_BYPASS_DSI_SYNC_Pos 6UL
|
||||
#define CTBM_OA_RES1_CTRL_OA1_BYPASS_DSI_SYNC_Msk 0x40UL
|
||||
#define CTBM_OA_RES1_CTRL_OA1_DSI_LEVEL_Pos 7UL
|
||||
#define CTBM_OA_RES1_CTRL_OA1_DSI_LEVEL_Msk 0x80UL
|
||||
#define CTBM_OA_RES1_CTRL_OA1_COMPINT_Pos 8UL
|
||||
#define CTBM_OA_RES1_CTRL_OA1_COMPINT_Msk 0x300UL
|
||||
#define CTBM_OA_RES1_CTRL_OA1_PUMP_EN_Pos 11UL
|
||||
#define CTBM_OA_RES1_CTRL_OA1_PUMP_EN_Msk 0x800UL
|
||||
#define CTBM_OA_RES1_CTRL_OA1_BOOST_EN_Pos 12UL
|
||||
#define CTBM_OA_RES1_CTRL_OA1_BOOST_EN_Msk 0x1000UL
|
||||
/* CTBM.COMP_STAT */
|
||||
#define CTBM_COMP_STAT_OA0_COMP_Pos 0UL
|
||||
#define CTBM_COMP_STAT_OA0_COMP_Msk 0x1UL
|
||||
#define CTBM_COMP_STAT_OA1_COMP_Pos 16UL
|
||||
#define CTBM_COMP_STAT_OA1_COMP_Msk 0x10000UL
|
||||
/* CTBM.INTR */
|
||||
#define CTBM_INTR_COMP0_Pos 0UL
|
||||
#define CTBM_INTR_COMP0_Msk 0x1UL
|
||||
#define CTBM_INTR_COMP1_Pos 1UL
|
||||
#define CTBM_INTR_COMP1_Msk 0x2UL
|
||||
/* CTBM.INTR_SET */
|
||||
#define CTBM_INTR_SET_COMP0_SET_Pos 0UL
|
||||
#define CTBM_INTR_SET_COMP0_SET_Msk 0x1UL
|
||||
#define CTBM_INTR_SET_COMP1_SET_Pos 1UL
|
||||
#define CTBM_INTR_SET_COMP1_SET_Msk 0x2UL
|
||||
/* CTBM.INTR_MASK */
|
||||
#define CTBM_INTR_MASK_COMP0_MASK_Pos 0UL
|
||||
#define CTBM_INTR_MASK_COMP0_MASK_Msk 0x1UL
|
||||
#define CTBM_INTR_MASK_COMP1_MASK_Pos 1UL
|
||||
#define CTBM_INTR_MASK_COMP1_MASK_Msk 0x2UL
|
||||
/* CTBM.INTR_MASKED */
|
||||
#define CTBM_INTR_MASKED_COMP0_MASKED_Pos 0UL
|
||||
#define CTBM_INTR_MASKED_COMP0_MASKED_Msk 0x1UL
|
||||
#define CTBM_INTR_MASKED_COMP1_MASKED_Pos 1UL
|
||||
#define CTBM_INTR_MASKED_COMP1_MASKED_Msk 0x2UL
|
||||
/* CTBM.OA0_SW */
|
||||
#define CTBM_OA0_SW_OA0P_A00_Pos 0UL
|
||||
#define CTBM_OA0_SW_OA0P_A00_Msk 0x1UL
|
||||
#define CTBM_OA0_SW_OA0P_A20_Pos 2UL
|
||||
#define CTBM_OA0_SW_OA0P_A20_Msk 0x4UL
|
||||
#define CTBM_OA0_SW_OA0P_A30_Pos 3UL
|
||||
#define CTBM_OA0_SW_OA0P_A30_Msk 0x8UL
|
||||
#define CTBM_OA0_SW_OA0M_A11_Pos 8UL
|
||||
#define CTBM_OA0_SW_OA0M_A11_Msk 0x100UL
|
||||
#define CTBM_OA0_SW_OA0M_A81_Pos 14UL
|
||||
#define CTBM_OA0_SW_OA0M_A81_Msk 0x4000UL
|
||||
#define CTBM_OA0_SW_OA0O_D51_Pos 18UL
|
||||
#define CTBM_OA0_SW_OA0O_D51_Msk 0x40000UL
|
||||
#define CTBM_OA0_SW_OA0O_D81_Pos 21UL
|
||||
#define CTBM_OA0_SW_OA0O_D81_Msk 0x200000UL
|
||||
/* CTBM.OA0_SW_CLEAR */
|
||||
#define CTBM_OA0_SW_CLEAR_OA0P_A00_Pos 0UL
|
||||
#define CTBM_OA0_SW_CLEAR_OA0P_A00_Msk 0x1UL
|
||||
#define CTBM_OA0_SW_CLEAR_OA0P_A20_Pos 2UL
|
||||
#define CTBM_OA0_SW_CLEAR_OA0P_A20_Msk 0x4UL
|
||||
#define CTBM_OA0_SW_CLEAR_OA0P_A30_Pos 3UL
|
||||
#define CTBM_OA0_SW_CLEAR_OA0P_A30_Msk 0x8UL
|
||||
#define CTBM_OA0_SW_CLEAR_OA0M_A11_Pos 8UL
|
||||
#define CTBM_OA0_SW_CLEAR_OA0M_A11_Msk 0x100UL
|
||||
#define CTBM_OA0_SW_CLEAR_OA0M_A81_Pos 14UL
|
||||
#define CTBM_OA0_SW_CLEAR_OA0M_A81_Msk 0x4000UL
|
||||
#define CTBM_OA0_SW_CLEAR_OA0O_D51_Pos 18UL
|
||||
#define CTBM_OA0_SW_CLEAR_OA0O_D51_Msk 0x40000UL
|
||||
#define CTBM_OA0_SW_CLEAR_OA0O_D81_Pos 21UL
|
||||
#define CTBM_OA0_SW_CLEAR_OA0O_D81_Msk 0x200000UL
|
||||
/* CTBM.OA1_SW */
|
||||
#define CTBM_OA1_SW_OA1P_A03_Pos 0UL
|
||||
#define CTBM_OA1_SW_OA1P_A03_Msk 0x1UL
|
||||
#define CTBM_OA1_SW_OA1P_A13_Pos 1UL
|
||||
#define CTBM_OA1_SW_OA1P_A13_Msk 0x2UL
|
||||
#define CTBM_OA1_SW_OA1P_A43_Pos 4UL
|
||||
#define CTBM_OA1_SW_OA1P_A43_Msk 0x10UL
|
||||
#define CTBM_OA1_SW_OA1P_A73_Pos 7UL
|
||||
#define CTBM_OA1_SW_OA1P_A73_Msk 0x80UL
|
||||
#define CTBM_OA1_SW_OA1M_A22_Pos 8UL
|
||||
#define CTBM_OA1_SW_OA1M_A22_Msk 0x100UL
|
||||
#define CTBM_OA1_SW_OA1M_A82_Pos 14UL
|
||||
#define CTBM_OA1_SW_OA1M_A82_Msk 0x4000UL
|
||||
#define CTBM_OA1_SW_OA1O_D52_Pos 18UL
|
||||
#define CTBM_OA1_SW_OA1O_D52_Msk 0x40000UL
|
||||
#define CTBM_OA1_SW_OA1O_D62_Pos 19UL
|
||||
#define CTBM_OA1_SW_OA1O_D62_Msk 0x80000UL
|
||||
#define CTBM_OA1_SW_OA1O_D82_Pos 21UL
|
||||
#define CTBM_OA1_SW_OA1O_D82_Msk 0x200000UL
|
||||
/* CTBM.OA1_SW_CLEAR */
|
||||
#define CTBM_OA1_SW_CLEAR_OA1P_A03_Pos 0UL
|
||||
#define CTBM_OA1_SW_CLEAR_OA1P_A03_Msk 0x1UL
|
||||
#define CTBM_OA1_SW_CLEAR_OA1P_A13_Pos 1UL
|
||||
#define CTBM_OA1_SW_CLEAR_OA1P_A13_Msk 0x2UL
|
||||
#define CTBM_OA1_SW_CLEAR_OA1P_A43_Pos 4UL
|
||||
#define CTBM_OA1_SW_CLEAR_OA1P_A43_Msk 0x10UL
|
||||
#define CTBM_OA1_SW_CLEAR_OA1P_A73_Pos 7UL
|
||||
#define CTBM_OA1_SW_CLEAR_OA1P_A73_Msk 0x80UL
|
||||
#define CTBM_OA1_SW_CLEAR_OA1M_A22_Pos 8UL
|
||||
#define CTBM_OA1_SW_CLEAR_OA1M_A22_Msk 0x100UL
|
||||
#define CTBM_OA1_SW_CLEAR_OA1M_A82_Pos 14UL
|
||||
#define CTBM_OA1_SW_CLEAR_OA1M_A82_Msk 0x4000UL
|
||||
#define CTBM_OA1_SW_CLEAR_OA1O_D52_Pos 18UL
|
||||
#define CTBM_OA1_SW_CLEAR_OA1O_D52_Msk 0x40000UL
|
||||
#define CTBM_OA1_SW_CLEAR_OA1O_D62_Pos 19UL
|
||||
#define CTBM_OA1_SW_CLEAR_OA1O_D62_Msk 0x80000UL
|
||||
#define CTBM_OA1_SW_CLEAR_OA1O_D82_Pos 21UL
|
||||
#define CTBM_OA1_SW_CLEAR_OA1O_D82_Msk 0x200000UL
|
||||
/* CTBM.CTD_SW */
|
||||
#define CTBM_CTD_SW_CTDD_CRD_Pos 1UL
|
||||
#define CTBM_CTD_SW_CTDD_CRD_Msk 0x2UL
|
||||
#define CTBM_CTD_SW_CTDS_CRS_Pos 4UL
|
||||
#define CTBM_CTD_SW_CTDS_CRS_Msk 0x10UL
|
||||
#define CTBM_CTD_SW_CTDS_COR_Pos 5UL
|
||||
#define CTBM_CTD_SW_CTDS_COR_Msk 0x20UL
|
||||
#define CTBM_CTD_SW_CTDO_C6H_Pos 8UL
|
||||
#define CTBM_CTD_SW_CTDO_C6H_Msk 0x100UL
|
||||
#define CTBM_CTD_SW_CTDO_COS_Pos 9UL
|
||||
#define CTBM_CTD_SW_CTDO_COS_Msk 0x200UL
|
||||
#define CTBM_CTD_SW_CTDH_COB_Pos 10UL
|
||||
#define CTBM_CTD_SW_CTDH_COB_Msk 0x400UL
|
||||
#define CTBM_CTD_SW_CTDH_CHD_Pos 12UL
|
||||
#define CTBM_CTD_SW_CTDH_CHD_Msk 0x1000UL
|
||||
#define CTBM_CTD_SW_CTDH_CA0_Pos 13UL
|
||||
#define CTBM_CTD_SW_CTDH_CA0_Msk 0x2000UL
|
||||
#define CTBM_CTD_SW_CTDH_CIS_Pos 14UL
|
||||
#define CTBM_CTD_SW_CTDH_CIS_Msk 0x4000UL
|
||||
#define CTBM_CTD_SW_CTDH_ILR_Pos 15UL
|
||||
#define CTBM_CTD_SW_CTDH_ILR_Msk 0x8000UL
|
||||
/* CTBM.CTD_SW_CLEAR */
|
||||
#define CTBM_CTD_SW_CLEAR_CTDD_CRD_Pos 1UL
|
||||
#define CTBM_CTD_SW_CLEAR_CTDD_CRD_Msk 0x2UL
|
||||
#define CTBM_CTD_SW_CLEAR_CTDS_CRS_Pos 4UL
|
||||
#define CTBM_CTD_SW_CLEAR_CTDS_CRS_Msk 0x10UL
|
||||
#define CTBM_CTD_SW_CLEAR_CTDS_COR_Pos 5UL
|
||||
#define CTBM_CTD_SW_CLEAR_CTDS_COR_Msk 0x20UL
|
||||
#define CTBM_CTD_SW_CLEAR_CTDO_C6H_Pos 8UL
|
||||
#define CTBM_CTD_SW_CLEAR_CTDO_C6H_Msk 0x100UL
|
||||
#define CTBM_CTD_SW_CLEAR_CTDO_COS_Pos 9UL
|
||||
#define CTBM_CTD_SW_CLEAR_CTDO_COS_Msk 0x200UL
|
||||
#define CTBM_CTD_SW_CLEAR_CTDH_COB_Pos 10UL
|
||||
#define CTBM_CTD_SW_CLEAR_CTDH_COB_Msk 0x400UL
|
||||
#define CTBM_CTD_SW_CLEAR_CTDH_CHD_Pos 12UL
|
||||
#define CTBM_CTD_SW_CLEAR_CTDH_CHD_Msk 0x1000UL
|
||||
#define CTBM_CTD_SW_CLEAR_CTDH_CA0_Pos 13UL
|
||||
#define CTBM_CTD_SW_CLEAR_CTDH_CA0_Msk 0x2000UL
|
||||
#define CTBM_CTD_SW_CLEAR_CTDH_CIS_Pos 14UL
|
||||
#define CTBM_CTD_SW_CLEAR_CTDH_CIS_Msk 0x4000UL
|
||||
#define CTBM_CTD_SW_CLEAR_CTDH_ILR_Pos 15UL
|
||||
#define CTBM_CTD_SW_CLEAR_CTDH_ILR_Msk 0x8000UL
|
||||
/* CTBM.CTB_SW_DS_CTRL */
|
||||
#define CTBM_CTB_SW_DS_CTRL_P2_DS_CTRL23_Pos 10UL
|
||||
#define CTBM_CTB_SW_DS_CTRL_P2_DS_CTRL23_Msk 0x400UL
|
||||
#define CTBM_CTB_SW_DS_CTRL_P3_DS_CTRL23_Pos 11UL
|
||||
#define CTBM_CTB_SW_DS_CTRL_P3_DS_CTRL23_Msk 0x800UL
|
||||
#define CTBM_CTB_SW_DS_CTRL_CTD_COS_DS_CTRL_Pos 31UL
|
||||
#define CTBM_CTB_SW_DS_CTRL_CTD_COS_DS_CTRL_Msk 0x80000000UL
|
||||
/* CTBM.CTB_SW_SQ_CTRL */
|
||||
#define CTBM_CTB_SW_SQ_CTRL_P2_SQ_CTRL23_Pos 10UL
|
||||
#define CTBM_CTB_SW_SQ_CTRL_P2_SQ_CTRL23_Msk 0x400UL
|
||||
#define CTBM_CTB_SW_SQ_CTRL_P3_SQ_CTRL23_Pos 11UL
|
||||
#define CTBM_CTB_SW_SQ_CTRL_P3_SQ_CTRL23_Msk 0x800UL
|
||||
/* CTBM.CTB_SW_STATUS */
|
||||
#define CTBM_CTB_SW_STATUS_OA0O_D51_STAT_Pos 28UL
|
||||
#define CTBM_CTB_SW_STATUS_OA0O_D51_STAT_Msk 0x10000000UL
|
||||
#define CTBM_CTB_SW_STATUS_OA1O_D52_STAT_Pos 29UL
|
||||
#define CTBM_CTB_SW_STATUS_OA1O_D52_STAT_Msk 0x20000000UL
|
||||
#define CTBM_CTB_SW_STATUS_OA1O_D62_STAT_Pos 30UL
|
||||
#define CTBM_CTB_SW_STATUS_OA1O_D62_STAT_Msk 0x40000000UL
|
||||
#define CTBM_CTB_SW_STATUS_CTD_COS_STAT_Pos 31UL
|
||||
#define CTBM_CTB_SW_STATUS_CTD_COS_STAT_Msk 0x80000000UL
|
||||
/* CTBM.OA0_OFFSET_TRIM */
|
||||
#define CTBM_OA0_OFFSET_TRIM_OA0_OFFSET_TRIM_Pos 0UL
|
||||
#define CTBM_OA0_OFFSET_TRIM_OA0_OFFSET_TRIM_Msk 0x3FUL
|
||||
/* CTBM.OA0_SLOPE_OFFSET_TRIM */
|
||||
#define CTBM_OA0_SLOPE_OFFSET_TRIM_OA0_SLOPE_OFFSET_TRIM_Pos 0UL
|
||||
#define CTBM_OA0_SLOPE_OFFSET_TRIM_OA0_SLOPE_OFFSET_TRIM_Msk 0x3FUL
|
||||
/* CTBM.OA0_COMP_TRIM */
|
||||
#define CTBM_OA0_COMP_TRIM_OA0_COMP_TRIM_Pos 0UL
|
||||
#define CTBM_OA0_COMP_TRIM_OA0_COMP_TRIM_Msk 0x3UL
|
||||
/* CTBM.OA1_OFFSET_TRIM */
|
||||
#define CTBM_OA1_OFFSET_TRIM_OA1_OFFSET_TRIM_Pos 0UL
|
||||
#define CTBM_OA1_OFFSET_TRIM_OA1_OFFSET_TRIM_Msk 0x3FUL
|
||||
/* CTBM.OA1_SLOPE_OFFSET_TRIM */
|
||||
#define CTBM_OA1_SLOPE_OFFSET_TRIM_OA1_SLOPE_OFFSET_TRIM_Pos 0UL
|
||||
#define CTBM_OA1_SLOPE_OFFSET_TRIM_OA1_SLOPE_OFFSET_TRIM_Msk 0x3FUL
|
||||
/* CTBM.OA1_COMP_TRIM */
|
||||
#define CTBM_OA1_COMP_TRIM_OA1_COMP_TRIM_Pos 0UL
|
||||
#define CTBM_OA1_COMP_TRIM_OA1_COMP_TRIM_Msk 0x3UL
|
||||
|
||||
|
||||
#endif /* _CYIP_CTBM_H_ */
|
||||
|
||||
|
||||
/* [] END OF FILE */
|
||||
|
|
@ -1,106 +0,0 @@
|
|||
/***************************************************************************//**
|
||||
* \file cyip_ctdac.h
|
||||
*
|
||||
* \brief
|
||||
* CTDAC IP definitions
|
||||
*
|
||||
* \note
|
||||
* Generator version: 1.3.0.1146
|
||||
* Database revision: rev#1050929
|
||||
*
|
||||
********************************************************************************
|
||||
* \copyright
|
||||
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
|
||||
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _CYIP_CTDAC_H_
|
||||
#define _CYIP_CTDAC_H_
|
||||
|
||||
#include "cyip_headers.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* CTDAC
|
||||
*******************************************************************************/
|
||||
|
||||
#define CTDAC_SECTION_SIZE 0x00010000UL
|
||||
|
||||
/**
|
||||
* \brief Continuous Time DAC (CTDAC)
|
||||
*/
|
||||
typedef struct {
|
||||
__IOM uint32_t CTDAC_CTRL; /*!< 0x00000000 Global CTDAC control */
|
||||
__IM uint32_t RESERVED[7];
|
||||
__IOM uint32_t INTR; /*!< 0x00000020 Interrupt request register */
|
||||
__IOM uint32_t INTR_SET; /*!< 0x00000024 Interrupt request set register */
|
||||
__IOM uint32_t INTR_MASK; /*!< 0x00000028 Interrupt request mask */
|
||||
__IM uint32_t INTR_MASKED; /*!< 0x0000002C Interrupt request masked */
|
||||
__IM uint32_t RESERVED1[32];
|
||||
__IOM uint32_t CTDAC_SW; /*!< 0x000000B0 CTDAC switch control */
|
||||
__IOM uint32_t CTDAC_SW_CLEAR; /*!< 0x000000B4 CTDAC switch control clear */
|
||||
__IM uint32_t RESERVED2[18];
|
||||
__IOM uint32_t CTDAC_VAL; /*!< 0x00000100 DAC Value */
|
||||
__IOM uint32_t CTDAC_VAL_NXT; /*!< 0x00000104 Next DAC value (double buffering) */
|
||||
} CTDAC_V1_Type; /*!< Size = 264 (0x108) */
|
||||
|
||||
|
||||
/* CTDAC.CTDAC_CTRL */
|
||||
#define CTDAC_CTDAC_CTRL_DEGLITCH_CNT_Pos 0UL
|
||||
#define CTDAC_CTDAC_CTRL_DEGLITCH_CNT_Msk 0x3FUL
|
||||
#define CTDAC_CTDAC_CTRL_DEGLITCH_CO6_Pos 8UL
|
||||
#define CTDAC_CTDAC_CTRL_DEGLITCH_CO6_Msk 0x100UL
|
||||
#define CTDAC_CTDAC_CTRL_DEGLITCH_COS_Pos 9UL
|
||||
#define CTDAC_CTDAC_CTRL_DEGLITCH_COS_Msk 0x200UL
|
||||
#define CTDAC_CTDAC_CTRL_OUT_EN_Pos 22UL
|
||||
#define CTDAC_CTDAC_CTRL_OUT_EN_Msk 0x400000UL
|
||||
#define CTDAC_CTDAC_CTRL_CTDAC_RANGE_Pos 23UL
|
||||
#define CTDAC_CTDAC_CTRL_CTDAC_RANGE_Msk 0x800000UL
|
||||
#define CTDAC_CTDAC_CTRL_CTDAC_MODE_Pos 24UL
|
||||
#define CTDAC_CTDAC_CTRL_CTDAC_MODE_Msk 0x3000000UL
|
||||
#define CTDAC_CTDAC_CTRL_DISABLED_MODE_Pos 27UL
|
||||
#define CTDAC_CTDAC_CTRL_DISABLED_MODE_Msk 0x8000000UL
|
||||
#define CTDAC_CTDAC_CTRL_DSI_STROBE_EN_Pos 28UL
|
||||
#define CTDAC_CTDAC_CTRL_DSI_STROBE_EN_Msk 0x10000000UL
|
||||
#define CTDAC_CTDAC_CTRL_DSI_STROBE_LEVEL_Pos 29UL
|
||||
#define CTDAC_CTDAC_CTRL_DSI_STROBE_LEVEL_Msk 0x20000000UL
|
||||
#define CTDAC_CTDAC_CTRL_DEEPSLEEP_ON_Pos 30UL
|
||||
#define CTDAC_CTDAC_CTRL_DEEPSLEEP_ON_Msk 0x40000000UL
|
||||
#define CTDAC_CTDAC_CTRL_ENABLED_Pos 31UL
|
||||
#define CTDAC_CTDAC_CTRL_ENABLED_Msk 0x80000000UL
|
||||
/* CTDAC.INTR */
|
||||
#define CTDAC_INTR_VDAC_EMPTY_Pos 0UL
|
||||
#define CTDAC_INTR_VDAC_EMPTY_Msk 0x1UL
|
||||
/* CTDAC.INTR_SET */
|
||||
#define CTDAC_INTR_SET_VDAC_EMPTY_SET_Pos 0UL
|
||||
#define CTDAC_INTR_SET_VDAC_EMPTY_SET_Msk 0x1UL
|
||||
/* CTDAC.INTR_MASK */
|
||||
#define CTDAC_INTR_MASK_VDAC_EMPTY_MASK_Pos 0UL
|
||||
#define CTDAC_INTR_MASK_VDAC_EMPTY_MASK_Msk 0x1UL
|
||||
/* CTDAC.INTR_MASKED */
|
||||
#define CTDAC_INTR_MASKED_VDAC_EMPTY_MASKED_Pos 0UL
|
||||
#define CTDAC_INTR_MASKED_VDAC_EMPTY_MASKED_Msk 0x1UL
|
||||
/* CTDAC.CTDAC_SW */
|
||||
#define CTDAC_CTDAC_SW_CTDD_CVD_Pos 0UL
|
||||
#define CTDAC_CTDAC_SW_CTDD_CVD_Msk 0x1UL
|
||||
#define CTDAC_CTDAC_SW_CTDO_CO6_Pos 8UL
|
||||
#define CTDAC_CTDAC_SW_CTDO_CO6_Msk 0x100UL
|
||||
/* CTDAC.CTDAC_SW_CLEAR */
|
||||
#define CTDAC_CTDAC_SW_CLEAR_CTDD_CVD_Pos 0UL
|
||||
#define CTDAC_CTDAC_SW_CLEAR_CTDD_CVD_Msk 0x1UL
|
||||
#define CTDAC_CTDAC_SW_CLEAR_CTDO_CO6_Pos 8UL
|
||||
#define CTDAC_CTDAC_SW_CLEAR_CTDO_CO6_Msk 0x100UL
|
||||
/* CTDAC.CTDAC_VAL */
|
||||
#define CTDAC_CTDAC_VAL_VALUE_Pos 0UL
|
||||
#define CTDAC_CTDAC_VAL_VALUE_Msk 0xFFFUL
|
||||
/* CTDAC.CTDAC_VAL_NXT */
|
||||
#define CTDAC_CTDAC_VAL_NXT_VALUE_Pos 0UL
|
||||
#define CTDAC_CTDAC_VAL_NXT_VALUE_Msk 0xFFFUL
|
||||
|
||||
|
||||
#endif /* _CYIP_CTDAC_H_ */
|
||||
|
||||
|
||||
/* [] END OF FILE */
|
||||
|
|
@ -1,230 +0,0 @@
|
|||
/***************************************************************************//**
|
||||
* \file cyip_dmac_v2.h
|
||||
*
|
||||
* \brief
|
||||
* DMAC IP definitions
|
||||
*
|
||||
* \note
|
||||
* Generator version: 1.3.0.1146
|
||||
* Database revision: rev#1050929
|
||||
*
|
||||
********************************************************************************
|
||||
* \copyright
|
||||
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
|
||||
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _CYIP_DMAC_V2_H_
|
||||
#define _CYIP_DMAC_V2_H_
|
||||
|
||||
#include "cyip_headers.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* DMAC
|
||||
*******************************************************************************/
|
||||
|
||||
#define DMAC_CH_V2_SECTION_SIZE 0x00000100UL
|
||||
#define DMAC_V2_SECTION_SIZE 0x00010000UL
|
||||
|
||||
/**
|
||||
* \brief DMA controller channel (DMAC_CH)
|
||||
*/
|
||||
typedef struct {
|
||||
__IOM uint32_t CTL; /*!< 0x00000000 Channel control */
|
||||
__IM uint32_t RESERVED[3];
|
||||
__IM uint32_t IDX; /*!< 0x00000010 Channel current indices */
|
||||
__IM uint32_t SRC; /*!< 0x00000014 Channel current source address */
|
||||
__IM uint32_t DST; /*!< 0x00000018 Channel current destination address */
|
||||
__IM uint32_t RESERVED1;
|
||||
__IOM uint32_t CURR; /*!< 0x00000020 Channel current descriptor pointer */
|
||||
__IM uint32_t RESERVED2[7];
|
||||
__IM uint32_t DESCR_STATUS; /*!< 0x00000040 Channel descriptor status */
|
||||
__IM uint32_t RESERVED3[7];
|
||||
__IM uint32_t DESCR_CTL; /*!< 0x00000060 Channel descriptor control */
|
||||
__IM uint32_t DESCR_SRC; /*!< 0x00000064 Channel descriptor source */
|
||||
__IM uint32_t DESCR_DST; /*!< 0x00000068 Channel descriptor destination */
|
||||
__IM uint32_t DESCR_X_SIZE; /*!< 0x0000006C Channel descriptor X size */
|
||||
__IM uint32_t DESCR_X_INCR; /*!< 0x00000070 Channel descriptor X increment */
|
||||
__IM uint32_t DESCR_Y_SIZE; /*!< 0x00000074 Channel descriptor Y size */
|
||||
__IM uint32_t DESCR_Y_INCR; /*!< 0x00000078 Channel descriptor Y increment */
|
||||
__IM uint32_t DESCR_NEXT; /*!< 0x0000007C Channel descriptor next pointer */
|
||||
__IOM uint32_t INTR; /*!< 0x00000080 Interrupt */
|
||||
__IOM uint32_t INTR_SET; /*!< 0x00000084 Interrupt set */
|
||||
__IOM uint32_t INTR_MASK; /*!< 0x00000088 Interrupt mask */
|
||||
__IM uint32_t INTR_MASKED; /*!< 0x0000008C Interrupt masked */
|
||||
__IM uint32_t RESERVED4[28];
|
||||
} DMAC_CH_V2_Type; /*!< Size = 256 (0x100) */
|
||||
|
||||
/**
|
||||
* \brief DMAC (DMAC)
|
||||
*/
|
||||
typedef struct {
|
||||
__IOM uint32_t CTL; /*!< 0x00000000 Control */
|
||||
__IM uint32_t RESERVED;
|
||||
__IM uint32_t ACTIVE; /*!< 0x00000008 Active channels */
|
||||
__IM uint32_t RESERVED1[1021];
|
||||
DMAC_CH_V2_Type CH[8]; /*!< 0x00001000 DMA controller channel */
|
||||
} DMAC_V2_Type; /*!< Size = 6144 (0x1800) */
|
||||
|
||||
|
||||
/* DMAC_CH.CTL */
|
||||
#define DMAC_CH_V2_CTL_P_Pos 0UL
|
||||
#define DMAC_CH_V2_CTL_P_Msk 0x1UL
|
||||
#define DMAC_CH_V2_CTL_NS_Pos 1UL
|
||||
#define DMAC_CH_V2_CTL_NS_Msk 0x2UL
|
||||
#define DMAC_CH_V2_CTL_B_Pos 2UL
|
||||
#define DMAC_CH_V2_CTL_B_Msk 0x4UL
|
||||
#define DMAC_CH_V2_CTL_PC_Pos 4UL
|
||||
#define DMAC_CH_V2_CTL_PC_Msk 0xF0UL
|
||||
#define DMAC_CH_V2_CTL_PRIO_Pos 8UL
|
||||
#define DMAC_CH_V2_CTL_PRIO_Msk 0x300UL
|
||||
#define DMAC_CH_V2_CTL_ENABLED_Pos 31UL
|
||||
#define DMAC_CH_V2_CTL_ENABLED_Msk 0x80000000UL
|
||||
/* DMAC_CH.IDX */
|
||||
#define DMAC_CH_V2_IDX_X_Pos 0UL
|
||||
#define DMAC_CH_V2_IDX_X_Msk 0xFFFFUL
|
||||
#define DMAC_CH_V2_IDX_Y_Pos 16UL
|
||||
#define DMAC_CH_V2_IDX_Y_Msk 0xFFFF0000UL
|
||||
/* DMAC_CH.SRC */
|
||||
#define DMAC_CH_V2_SRC_ADDR_Pos 0UL
|
||||
#define DMAC_CH_V2_SRC_ADDR_Msk 0xFFFFFFFFUL
|
||||
/* DMAC_CH.DST */
|
||||
#define DMAC_CH_V2_DST_ADDR_Pos 0UL
|
||||
#define DMAC_CH_V2_DST_ADDR_Msk 0xFFFFFFFFUL
|
||||
/* DMAC_CH.CURR */
|
||||
#define DMAC_CH_V2_CURR_PTR_Pos 2UL
|
||||
#define DMAC_CH_V2_CURR_PTR_Msk 0xFFFFFFFCUL
|
||||
/* DMAC_CH.DESCR_STATUS */
|
||||
#define DMAC_CH_V2_DESCR_STATUS_VALID_Pos 31UL
|
||||
#define DMAC_CH_V2_DESCR_STATUS_VALID_Msk 0x80000000UL
|
||||
/* DMAC_CH.DESCR_CTL */
|
||||
#define DMAC_CH_V2_DESCR_CTL_WAIT_FOR_DEACT_Pos 0UL
|
||||
#define DMAC_CH_V2_DESCR_CTL_WAIT_FOR_DEACT_Msk 0x3UL
|
||||
#define DMAC_CH_V2_DESCR_CTL_INTR_TYPE_Pos 2UL
|
||||
#define DMAC_CH_V2_DESCR_CTL_INTR_TYPE_Msk 0xCUL
|
||||
#define DMAC_CH_V2_DESCR_CTL_TR_OUT_TYPE_Pos 4UL
|
||||
#define DMAC_CH_V2_DESCR_CTL_TR_OUT_TYPE_Msk 0x30UL
|
||||
#define DMAC_CH_V2_DESCR_CTL_TR_IN_TYPE_Pos 6UL
|
||||
#define DMAC_CH_V2_DESCR_CTL_TR_IN_TYPE_Msk 0xC0UL
|
||||
#define DMAC_CH_V2_DESCR_CTL_DATA_PREFETCH_Pos 8UL
|
||||
#define DMAC_CH_V2_DESCR_CTL_DATA_PREFETCH_Msk 0x100UL
|
||||
#define DMAC_CH_V2_DESCR_CTL_DATA_SIZE_Pos 16UL
|
||||
#define DMAC_CH_V2_DESCR_CTL_DATA_SIZE_Msk 0x30000UL
|
||||
#define DMAC_CH_V2_DESCR_CTL_CH_DISABLE_Pos 24UL
|
||||
#define DMAC_CH_V2_DESCR_CTL_CH_DISABLE_Msk 0x1000000UL
|
||||
#define DMAC_CH_V2_DESCR_CTL_SRC_TRANSFER_SIZE_Pos 26UL
|
||||
#define DMAC_CH_V2_DESCR_CTL_SRC_TRANSFER_SIZE_Msk 0x4000000UL
|
||||
#define DMAC_CH_V2_DESCR_CTL_DST_TRANSFER_SIZE_Pos 27UL
|
||||
#define DMAC_CH_V2_DESCR_CTL_DST_TRANSFER_SIZE_Msk 0x8000000UL
|
||||
#define DMAC_CH_V2_DESCR_CTL_DESCR_TYPE_Pos 28UL
|
||||
#define DMAC_CH_V2_DESCR_CTL_DESCR_TYPE_Msk 0x70000000UL
|
||||
/* DMAC_CH.DESCR_SRC */
|
||||
#define DMAC_CH_V2_DESCR_SRC_ADDR_Pos 0UL
|
||||
#define DMAC_CH_V2_DESCR_SRC_ADDR_Msk 0xFFFFFFFFUL
|
||||
/* DMAC_CH.DESCR_DST */
|
||||
#define DMAC_CH_V2_DESCR_DST_ADDR_Pos 0UL
|
||||
#define DMAC_CH_V2_DESCR_DST_ADDR_Msk 0xFFFFFFFFUL
|
||||
/* DMAC_CH.DESCR_X_SIZE */
|
||||
#define DMAC_CH_V2_DESCR_X_SIZE_X_COUNT_Pos 0UL
|
||||
#define DMAC_CH_V2_DESCR_X_SIZE_X_COUNT_Msk 0xFFFFUL
|
||||
/* DMAC_CH.DESCR_X_INCR */
|
||||
#define DMAC_CH_V2_DESCR_X_INCR_SRC_X_Pos 0UL
|
||||
#define DMAC_CH_V2_DESCR_X_INCR_SRC_X_Msk 0xFFFFUL
|
||||
#define DMAC_CH_V2_DESCR_X_INCR_DST_X_Pos 16UL
|
||||
#define DMAC_CH_V2_DESCR_X_INCR_DST_X_Msk 0xFFFF0000UL
|
||||
/* DMAC_CH.DESCR_Y_SIZE */
|
||||
#define DMAC_CH_V2_DESCR_Y_SIZE_Y_COUNT_Pos 0UL
|
||||
#define DMAC_CH_V2_DESCR_Y_SIZE_Y_COUNT_Msk 0xFFFFUL
|
||||
/* DMAC_CH.DESCR_Y_INCR */
|
||||
#define DMAC_CH_V2_DESCR_Y_INCR_SRC_Y_Pos 0UL
|
||||
#define DMAC_CH_V2_DESCR_Y_INCR_SRC_Y_Msk 0xFFFFUL
|
||||
#define DMAC_CH_V2_DESCR_Y_INCR_DST_Y_Pos 16UL
|
||||
#define DMAC_CH_V2_DESCR_Y_INCR_DST_Y_Msk 0xFFFF0000UL
|
||||
/* DMAC_CH.DESCR_NEXT */
|
||||
#define DMAC_CH_V2_DESCR_NEXT_PTR_Pos 2UL
|
||||
#define DMAC_CH_V2_DESCR_NEXT_PTR_Msk 0xFFFFFFFCUL
|
||||
/* DMAC_CH.INTR */
|
||||
#define DMAC_CH_V2_INTR_COMPLETION_Pos 0UL
|
||||
#define DMAC_CH_V2_INTR_COMPLETION_Msk 0x1UL
|
||||
#define DMAC_CH_V2_INTR_SRC_BUS_ERROR_Pos 1UL
|
||||
#define DMAC_CH_V2_INTR_SRC_BUS_ERROR_Msk 0x2UL
|
||||
#define DMAC_CH_V2_INTR_DST_BUS_ERROR_Pos 2UL
|
||||
#define DMAC_CH_V2_INTR_DST_BUS_ERROR_Msk 0x4UL
|
||||
#define DMAC_CH_V2_INTR_SRC_MISAL_Pos 3UL
|
||||
#define DMAC_CH_V2_INTR_SRC_MISAL_Msk 0x8UL
|
||||
#define DMAC_CH_V2_INTR_DST_MISAL_Pos 4UL
|
||||
#define DMAC_CH_V2_INTR_DST_MISAL_Msk 0x10UL
|
||||
#define DMAC_CH_V2_INTR_CURR_PTR_NULL_Pos 5UL
|
||||
#define DMAC_CH_V2_INTR_CURR_PTR_NULL_Msk 0x20UL
|
||||
#define DMAC_CH_V2_INTR_ACTIVE_CH_DISABLED_Pos 6UL
|
||||
#define DMAC_CH_V2_INTR_ACTIVE_CH_DISABLED_Msk 0x40UL
|
||||
#define DMAC_CH_V2_INTR_DESCR_BUS_ERROR_Pos 7UL
|
||||
#define DMAC_CH_V2_INTR_DESCR_BUS_ERROR_Msk 0x80UL
|
||||
/* DMAC_CH.INTR_SET */
|
||||
#define DMAC_CH_V2_INTR_SET_COMPLETION_Pos 0UL
|
||||
#define DMAC_CH_V2_INTR_SET_COMPLETION_Msk 0x1UL
|
||||
#define DMAC_CH_V2_INTR_SET_SRC_BUS_ERROR_Pos 1UL
|
||||
#define DMAC_CH_V2_INTR_SET_SRC_BUS_ERROR_Msk 0x2UL
|
||||
#define DMAC_CH_V2_INTR_SET_DST_BUS_ERROR_Pos 2UL
|
||||
#define DMAC_CH_V2_INTR_SET_DST_BUS_ERROR_Msk 0x4UL
|
||||
#define DMAC_CH_V2_INTR_SET_SRC_MISAL_Pos 3UL
|
||||
#define DMAC_CH_V2_INTR_SET_SRC_MISAL_Msk 0x8UL
|
||||
#define DMAC_CH_V2_INTR_SET_DST_MISAL_Pos 4UL
|
||||
#define DMAC_CH_V2_INTR_SET_DST_MISAL_Msk 0x10UL
|
||||
#define DMAC_CH_V2_INTR_SET_CURR_PTR_NULL_Pos 5UL
|
||||
#define DMAC_CH_V2_INTR_SET_CURR_PTR_NULL_Msk 0x20UL
|
||||
#define DMAC_CH_V2_INTR_SET_ACTIVE_CH_DISABLED_Pos 6UL
|
||||
#define DMAC_CH_V2_INTR_SET_ACTIVE_CH_DISABLED_Msk 0x40UL
|
||||
#define DMAC_CH_V2_INTR_SET_DESCR_BUS_ERROR_Pos 7UL
|
||||
#define DMAC_CH_V2_INTR_SET_DESCR_BUS_ERROR_Msk 0x80UL
|
||||
/* DMAC_CH.INTR_MASK */
|
||||
#define DMAC_CH_V2_INTR_MASK_COMPLETION_Pos 0UL
|
||||
#define DMAC_CH_V2_INTR_MASK_COMPLETION_Msk 0x1UL
|
||||
#define DMAC_CH_V2_INTR_MASK_SRC_BUS_ERROR_Pos 1UL
|
||||
#define DMAC_CH_V2_INTR_MASK_SRC_BUS_ERROR_Msk 0x2UL
|
||||
#define DMAC_CH_V2_INTR_MASK_DST_BUS_ERROR_Pos 2UL
|
||||
#define DMAC_CH_V2_INTR_MASK_DST_BUS_ERROR_Msk 0x4UL
|
||||
#define DMAC_CH_V2_INTR_MASK_SRC_MISAL_Pos 3UL
|
||||
#define DMAC_CH_V2_INTR_MASK_SRC_MISAL_Msk 0x8UL
|
||||
#define DMAC_CH_V2_INTR_MASK_DST_MISAL_Pos 4UL
|
||||
#define DMAC_CH_V2_INTR_MASK_DST_MISAL_Msk 0x10UL
|
||||
#define DMAC_CH_V2_INTR_MASK_CURR_PTR_NULL_Pos 5UL
|
||||
#define DMAC_CH_V2_INTR_MASK_CURR_PTR_NULL_Msk 0x20UL
|
||||
#define DMAC_CH_V2_INTR_MASK_ACTIVE_CH_DISABLED_Pos 6UL
|
||||
#define DMAC_CH_V2_INTR_MASK_ACTIVE_CH_DISABLED_Msk 0x40UL
|
||||
#define DMAC_CH_V2_INTR_MASK_DESCR_BUS_ERROR_Pos 7UL
|
||||
#define DMAC_CH_V2_INTR_MASK_DESCR_BUS_ERROR_Msk 0x80UL
|
||||
/* DMAC_CH.INTR_MASKED */
|
||||
#define DMAC_CH_V2_INTR_MASKED_COMPLETION_Pos 0UL
|
||||
#define DMAC_CH_V2_INTR_MASKED_COMPLETION_Msk 0x1UL
|
||||
#define DMAC_CH_V2_INTR_MASKED_SRC_BUS_ERROR_Pos 1UL
|
||||
#define DMAC_CH_V2_INTR_MASKED_SRC_BUS_ERROR_Msk 0x2UL
|
||||
#define DMAC_CH_V2_INTR_MASKED_DST_BUS_ERROR_Pos 2UL
|
||||
#define DMAC_CH_V2_INTR_MASKED_DST_BUS_ERROR_Msk 0x4UL
|
||||
#define DMAC_CH_V2_INTR_MASKED_SRC_MISAL_Pos 3UL
|
||||
#define DMAC_CH_V2_INTR_MASKED_SRC_MISAL_Msk 0x8UL
|
||||
#define DMAC_CH_V2_INTR_MASKED_DST_MISAL_Pos 4UL
|
||||
#define DMAC_CH_V2_INTR_MASKED_DST_MISAL_Msk 0x10UL
|
||||
#define DMAC_CH_V2_INTR_MASKED_CURR_PTR_NULL_Pos 5UL
|
||||
#define DMAC_CH_V2_INTR_MASKED_CURR_PTR_NULL_Msk 0x20UL
|
||||
#define DMAC_CH_V2_INTR_MASKED_ACTIVE_CH_DISABLED_Pos 6UL
|
||||
#define DMAC_CH_V2_INTR_MASKED_ACTIVE_CH_DISABLED_Msk 0x40UL
|
||||
#define DMAC_CH_V2_INTR_MASKED_DESCR_BUS_ERROR_Pos 7UL
|
||||
#define DMAC_CH_V2_INTR_MASKED_DESCR_BUS_ERROR_Msk 0x80UL
|
||||
|
||||
|
||||
/* DMAC.CTL */
|
||||
#define DMAC_V2_CTL_ENABLED_Pos 31UL
|
||||
#define DMAC_V2_CTL_ENABLED_Msk 0x80000000UL
|
||||
/* DMAC.ACTIVE */
|
||||
#define DMAC_V2_ACTIVE_ACTIVE_Pos 0UL
|
||||
#define DMAC_V2_ACTIVE_ACTIVE_Msk 0xFFUL
|
||||
|
||||
|
||||
#endif /* _CYIP_DMAC_V2_H_ */
|
||||
|
||||
|
||||
/* [] END OF FILE */
|
||||
|
|
@ -1,172 +0,0 @@
|
|||
/***************************************************************************//**
|
||||
* \file cyip_dw.h
|
||||
*
|
||||
* \brief
|
||||
* DW IP definitions
|
||||
*
|
||||
* \note
|
||||
* Generator version: 1.3.0.1146
|
||||
* Database revision: rev#1050929
|
||||
*
|
||||
********************************************************************************
|
||||
* \copyright
|
||||
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
|
||||
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _CYIP_DW_H_
|
||||
#define _CYIP_DW_H_
|
||||
|
||||
#include "cyip_headers.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* DW
|
||||
*******************************************************************************/
|
||||
|
||||
#define DW_CH_STRUCT_SECTION_SIZE 0x00000020UL
|
||||
#define DW_SECTION_SIZE 0x00001000UL
|
||||
|
||||
/**
|
||||
* \brief DW channel structure (DW_CH_STRUCT)
|
||||
*/
|
||||
typedef struct {
|
||||
__IOM uint32_t CH_CTL; /*!< 0x00000000 Channel control */
|
||||
__IM uint32_t CH_STATUS; /*!< 0x00000004 Channel status */
|
||||
__IOM uint32_t CH_IDX; /*!< 0x00000008 Channel current indices */
|
||||
__IOM uint32_t CH_CURR_PTR; /*!< 0x0000000C Channel current descriptor pointer */
|
||||
__IOM uint32_t INTR; /*!< 0x00000010 Interrupt */
|
||||
__IOM uint32_t INTR_SET; /*!< 0x00000014 Interrupt set */
|
||||
__IOM uint32_t INTR_MASK; /*!< 0x00000018 Interrupt mask */
|
||||
__IM uint32_t INTR_MASKED; /*!< 0x0000001C Interrupt masked */
|
||||
} DW_CH_STRUCT_V1_Type; /*!< Size = 32 (0x20) */
|
||||
|
||||
/**
|
||||
* \brief Datawire Controller (DW)
|
||||
*/
|
||||
typedef struct {
|
||||
__IOM uint32_t CTL; /*!< 0x00000000 Control */
|
||||
__IM uint32_t STATUS; /*!< 0x00000004 Status */
|
||||
__IM uint32_t PENDING; /*!< 0x00000008 Pending channels */
|
||||
__IM uint32_t RESERVED;
|
||||
__IM uint32_t STATUS_INTR; /*!< 0x00000010 System interrupt control */
|
||||
__IM uint32_t STATUS_INTR_MASKED; /*!< 0x00000014 Status of interrupts masked */
|
||||
__IM uint32_t RESERVED1[2];
|
||||
__IM uint32_t ACT_DESCR_CTL; /*!< 0x00000020 Active descriptor control */
|
||||
__IM uint32_t ACT_DESCR_SRC; /*!< 0x00000024 Active descriptor source */
|
||||
__IM uint32_t ACT_DESCR_DST; /*!< 0x00000028 Active descriptor destination */
|
||||
__IM uint32_t RESERVED2;
|
||||
__IM uint32_t ACT_DESCR_X_CTL; /*!< 0x00000030 Active descriptor X loop control */
|
||||
__IM uint32_t ACT_DESCR_Y_CTL; /*!< 0x00000034 Active descriptor Y loop control */
|
||||
__IM uint32_t ACT_DESCR_NEXT_PTR; /*!< 0x00000038 Active descriptor next pointer */
|
||||
__IM uint32_t RESERVED3;
|
||||
__IM uint32_t ACT_SRC; /*!< 0x00000040 Active source */
|
||||
__IM uint32_t ACT_DST; /*!< 0x00000044 Active destination */
|
||||
__IM uint32_t RESERVED4[494];
|
||||
DW_CH_STRUCT_V1_Type CH_STRUCT[32]; /*!< 0x00000800 DW channel structure */
|
||||
} DW_V1_Type; /*!< Size = 3072 (0xC00) */
|
||||
|
||||
|
||||
/* DW_CH_STRUCT.CH_CTL */
|
||||
#define DW_CH_STRUCT_CH_CTL_P_Pos 0UL
|
||||
#define DW_CH_STRUCT_CH_CTL_P_Msk 0x1UL
|
||||
#define DW_CH_STRUCT_CH_CTL_NS_Pos 1UL
|
||||
#define DW_CH_STRUCT_CH_CTL_NS_Msk 0x2UL
|
||||
#define DW_CH_STRUCT_CH_CTL_B_Pos 2UL
|
||||
#define DW_CH_STRUCT_CH_CTL_B_Msk 0x4UL
|
||||
#define DW_CH_STRUCT_CH_CTL_PC_Pos 4UL
|
||||
#define DW_CH_STRUCT_CH_CTL_PC_Msk 0xF0UL
|
||||
#define DW_CH_STRUCT_CH_CTL_PRIO_Pos 16UL
|
||||
#define DW_CH_STRUCT_CH_CTL_PRIO_Msk 0x30000UL
|
||||
#define DW_CH_STRUCT_CH_CTL_PREEMPTABLE_Pos 18UL
|
||||
#define DW_CH_STRUCT_CH_CTL_PREEMPTABLE_Msk 0x40000UL
|
||||
#define DW_CH_STRUCT_CH_CTL_ENABLED_Pos 31UL
|
||||
#define DW_CH_STRUCT_CH_CTL_ENABLED_Msk 0x80000000UL
|
||||
/* DW_CH_STRUCT.CH_STATUS */
|
||||
#define DW_CH_STRUCT_CH_STATUS_INTR_CAUSE_Pos 0UL
|
||||
#define DW_CH_STRUCT_CH_STATUS_INTR_CAUSE_Msk 0xFUL
|
||||
/* DW_CH_STRUCT.CH_IDX */
|
||||
#define DW_CH_STRUCT_CH_IDX_X_IDX_Pos 0UL
|
||||
#define DW_CH_STRUCT_CH_IDX_X_IDX_Msk 0xFFUL
|
||||
#define DW_CH_STRUCT_CH_IDX_Y_IDX_Pos 8UL
|
||||
#define DW_CH_STRUCT_CH_IDX_Y_IDX_Msk 0xFF00UL
|
||||
/* DW_CH_STRUCT.CH_CURR_PTR */
|
||||
#define DW_CH_STRUCT_CH_CURR_PTR_ADDR_Pos 2UL
|
||||
#define DW_CH_STRUCT_CH_CURR_PTR_ADDR_Msk 0xFFFFFFFCUL
|
||||
/* DW_CH_STRUCT.INTR */
|
||||
#define DW_CH_STRUCT_INTR_CH_Pos 0UL
|
||||
#define DW_CH_STRUCT_INTR_CH_Msk 0x1UL
|
||||
/* DW_CH_STRUCT.INTR_SET */
|
||||
#define DW_CH_STRUCT_INTR_SET_CH_Pos 0UL
|
||||
#define DW_CH_STRUCT_INTR_SET_CH_Msk 0x1UL
|
||||
/* DW_CH_STRUCT.INTR_MASK */
|
||||
#define DW_CH_STRUCT_INTR_MASK_CH_Pos 0UL
|
||||
#define DW_CH_STRUCT_INTR_MASK_CH_Msk 0x1UL
|
||||
/* DW_CH_STRUCT.INTR_MASKED */
|
||||
#define DW_CH_STRUCT_INTR_MASKED_CH_Pos 0UL
|
||||
#define DW_CH_STRUCT_INTR_MASKED_CH_Msk 0x1UL
|
||||
|
||||
|
||||
/* DW.CTL */
|
||||
#define DW_CTL_ENABLED_Pos 31UL
|
||||
#define DW_CTL_ENABLED_Msk 0x80000000UL
|
||||
/* DW.STATUS */
|
||||
#define DW_STATUS_P_Pos 0UL
|
||||
#define DW_STATUS_P_Msk 0x1UL
|
||||
#define DW_STATUS_NS_Pos 1UL
|
||||
#define DW_STATUS_NS_Msk 0x2UL
|
||||
#define DW_STATUS_B_Pos 2UL
|
||||
#define DW_STATUS_B_Msk 0x4UL
|
||||
#define DW_STATUS_PC_Pos 4UL
|
||||
#define DW_STATUS_PC_Msk 0xF0UL
|
||||
#define DW_STATUS_CH_IDX_Pos 8UL
|
||||
#define DW_STATUS_CH_IDX_Msk 0x1F00UL
|
||||
#define DW_STATUS_PRIO_Pos 16UL
|
||||
#define DW_STATUS_PRIO_Msk 0x30000UL
|
||||
#define DW_STATUS_PREEMPTABLE_Pos 18UL
|
||||
#define DW_STATUS_PREEMPTABLE_Msk 0x40000UL
|
||||
#define DW_STATUS_STATE_Pos 20UL
|
||||
#define DW_STATUS_STATE_Msk 0x700000UL
|
||||
#define DW_STATUS_ACTIVE_Pos 31UL
|
||||
#define DW_STATUS_ACTIVE_Msk 0x80000000UL
|
||||
/* DW.PENDING */
|
||||
#define DW_PENDING_CH_PENDING_Pos 0UL
|
||||
#define DW_PENDING_CH_PENDING_Msk 0xFFFFFFFFUL
|
||||
/* DW.STATUS_INTR */
|
||||
#define DW_STATUS_INTR_CH_Pos 0UL
|
||||
#define DW_STATUS_INTR_CH_Msk 0xFFFFFFFFUL
|
||||
/* DW.STATUS_INTR_MASKED */
|
||||
#define DW_STATUS_INTR_MASKED_CH_Pos 0UL
|
||||
#define DW_STATUS_INTR_MASKED_CH_Msk 0xFFFFFFFFUL
|
||||
/* DW.ACT_DESCR_CTL */
|
||||
#define DW_ACT_DESCR_CTL_DATA_Pos 0UL
|
||||
#define DW_ACT_DESCR_CTL_DATA_Msk 0xFFFFFFFFUL
|
||||
/* DW.ACT_DESCR_SRC */
|
||||
#define DW_ACT_DESCR_SRC_DATA_Pos 0UL
|
||||
#define DW_ACT_DESCR_SRC_DATA_Msk 0xFFFFFFFFUL
|
||||
/* DW.ACT_DESCR_DST */
|
||||
#define DW_ACT_DESCR_DST_DATA_Pos 0UL
|
||||
#define DW_ACT_DESCR_DST_DATA_Msk 0xFFFFFFFFUL
|
||||
/* DW.ACT_DESCR_X_CTL */
|
||||
#define DW_ACT_DESCR_X_CTL_DATA_Pos 0UL
|
||||
#define DW_ACT_DESCR_X_CTL_DATA_Msk 0xFFFFFFFFUL
|
||||
/* DW.ACT_DESCR_Y_CTL */
|
||||
#define DW_ACT_DESCR_Y_CTL_DATA_Pos 0UL
|
||||
#define DW_ACT_DESCR_Y_CTL_DATA_Msk 0xFFFFFFFFUL
|
||||
/* DW.ACT_DESCR_NEXT_PTR */
|
||||
#define DW_ACT_DESCR_NEXT_PTR_ADDR_Pos 2UL
|
||||
#define DW_ACT_DESCR_NEXT_PTR_ADDR_Msk 0xFFFFFFFCUL
|
||||
/* DW.ACT_SRC */
|
||||
#define DW_ACT_SRC_SRC_ADDR_Pos 0UL
|
||||
#define DW_ACT_SRC_SRC_ADDR_Msk 0xFFFFFFFFUL
|
||||
/* DW.ACT_DST */
|
||||
#define DW_ACT_DST_DST_ADDR_Pos 0UL
|
||||
#define DW_ACT_DST_DST_ADDR_Msk 0xFFFFFFFFUL
|
||||
|
||||
|
||||
#endif /* _CYIP_DW_H_ */
|
||||
|
||||
|
||||
/* [] END OF FILE */
|
||||
|
|
@ -1,213 +0,0 @@
|
|||
/***************************************************************************//**
|
||||
* \file cyip_dw_v2.h
|
||||
*
|
||||
* \brief
|
||||
* DW IP definitions
|
||||
*
|
||||
* \note
|
||||
* Generator version: 1.3.0.1146
|
||||
* Database revision: rev#1050929
|
||||
*
|
||||
********************************************************************************
|
||||
* \copyright
|
||||
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
|
||||
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _CYIP_DW_V2_H_
|
||||
#define _CYIP_DW_V2_H_
|
||||
|
||||
#include "cyip_headers.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* DW
|
||||
*******************************************************************************/
|
||||
|
||||
#define DW_CH_STRUCT_V2_SECTION_SIZE 0x00000040UL
|
||||
#define DW_V2_SECTION_SIZE 0x00010000UL
|
||||
|
||||
/**
|
||||
* \brief DW channel structure (DW_CH_STRUCT)
|
||||
*/
|
||||
typedef struct {
|
||||
__IOM uint32_t CH_CTL; /*!< 0x00000000 Channel control */
|
||||
__IM uint32_t CH_STATUS; /*!< 0x00000004 Channel status */
|
||||
__IOM uint32_t CH_IDX; /*!< 0x00000008 Channel current indices */
|
||||
__IOM uint32_t CH_CURR_PTR; /*!< 0x0000000C Channel current descriptor pointer */
|
||||
__IOM uint32_t INTR; /*!< 0x00000010 Interrupt */
|
||||
__IOM uint32_t INTR_SET; /*!< 0x00000014 Interrupt set */
|
||||
__IOM uint32_t INTR_MASK; /*!< 0x00000018 Interrupt mask */
|
||||
__IM uint32_t INTR_MASKED; /*!< 0x0000001C Interrupt masked */
|
||||
__IOM uint32_t SRAM_DATA0; /*!< 0x00000020 SRAM data 0 */
|
||||
__IOM uint32_t SRAM_DATA1; /*!< 0x00000024 SRAM data 1 */
|
||||
__IM uint32_t RESERVED[6];
|
||||
} DW_CH_STRUCT_V2_Type; /*!< Size = 64 (0x40) */
|
||||
|
||||
/**
|
||||
* \brief Datawire Controller (DW)
|
||||
*/
|
||||
typedef struct {
|
||||
__IOM uint32_t CTL; /*!< 0x00000000 Control */
|
||||
__IM uint32_t STATUS; /*!< 0x00000004 Status */
|
||||
__IM uint32_t RESERVED[6];
|
||||
__IM uint32_t ACT_DESCR_CTL; /*!< 0x00000020 Active descriptor control */
|
||||
__IM uint32_t ACT_DESCR_SRC; /*!< 0x00000024 Active descriptor source */
|
||||
__IM uint32_t ACT_DESCR_DST; /*!< 0x00000028 Active descriptor destination */
|
||||
__IM uint32_t RESERVED1;
|
||||
__IM uint32_t ACT_DESCR_X_CTL; /*!< 0x00000030 Active descriptor X loop control */
|
||||
__IM uint32_t ACT_DESCR_Y_CTL; /*!< 0x00000034 Active descriptor Y loop control */
|
||||
__IM uint32_t ACT_DESCR_NEXT_PTR; /*!< 0x00000038 Active descriptor next pointer */
|
||||
__IM uint32_t RESERVED2;
|
||||
__IM uint32_t ACT_SRC; /*!< 0x00000040 Active source */
|
||||
__IM uint32_t ACT_DST; /*!< 0x00000044 Active destination */
|
||||
__IM uint32_t RESERVED3[14];
|
||||
__IOM uint32_t ECC_CTL; /*!< 0x00000080 ECC control */
|
||||
__IM uint32_t RESERVED4[31];
|
||||
__IOM uint32_t CRC_CTL; /*!< 0x00000100 CRC control */
|
||||
__IM uint32_t RESERVED5[3];
|
||||
__IOM uint32_t CRC_DATA_CTL; /*!< 0x00000110 CRC data control */
|
||||
__IM uint32_t RESERVED6[3];
|
||||
__IOM uint32_t CRC_POL_CTL; /*!< 0x00000120 CRC polynomial control */
|
||||
__IM uint32_t RESERVED7[3];
|
||||
__IOM uint32_t CRC_LFSR_CTL; /*!< 0x00000130 CRC LFSR control */
|
||||
__IM uint32_t RESERVED8[3];
|
||||
__IOM uint32_t CRC_REM_CTL; /*!< 0x00000140 CRC remainder control */
|
||||
__IM uint32_t RESERVED9;
|
||||
__IM uint32_t CRC_REM_RESULT; /*!< 0x00000148 CRC remainder result */
|
||||
__IM uint32_t RESERVED10[8109];
|
||||
DW_CH_STRUCT_V2_Type CH_STRUCT[512]; /*!< 0x00008000 DW channel structure */
|
||||
} DW_V2_Type; /*!< Size = 65536 (0x10000) */
|
||||
|
||||
|
||||
/* DW_CH_STRUCT.CH_CTL */
|
||||
#define DW_CH_STRUCT_V2_CH_CTL_P_Pos 0UL
|
||||
#define DW_CH_STRUCT_V2_CH_CTL_P_Msk 0x1UL
|
||||
#define DW_CH_STRUCT_V2_CH_CTL_NS_Pos 1UL
|
||||
#define DW_CH_STRUCT_V2_CH_CTL_NS_Msk 0x2UL
|
||||
#define DW_CH_STRUCT_V2_CH_CTL_B_Pos 2UL
|
||||
#define DW_CH_STRUCT_V2_CH_CTL_B_Msk 0x4UL
|
||||
#define DW_CH_STRUCT_V2_CH_CTL_PC_Pos 4UL
|
||||
#define DW_CH_STRUCT_V2_CH_CTL_PC_Msk 0xF0UL
|
||||
#define DW_CH_STRUCT_V2_CH_CTL_PRIO_Pos 8UL
|
||||
#define DW_CH_STRUCT_V2_CH_CTL_PRIO_Msk 0x300UL
|
||||
#define DW_CH_STRUCT_V2_CH_CTL_PREEMPTABLE_Pos 11UL
|
||||
#define DW_CH_STRUCT_V2_CH_CTL_PREEMPTABLE_Msk 0x800UL
|
||||
#define DW_CH_STRUCT_V2_CH_CTL_ENABLED_Pos 31UL
|
||||
#define DW_CH_STRUCT_V2_CH_CTL_ENABLED_Msk 0x80000000UL
|
||||
/* DW_CH_STRUCT.CH_STATUS */
|
||||
#define DW_CH_STRUCT_V2_CH_STATUS_INTR_CAUSE_Pos 0UL
|
||||
#define DW_CH_STRUCT_V2_CH_STATUS_INTR_CAUSE_Msk 0xFUL
|
||||
#define DW_CH_STRUCT_V2_CH_STATUS_PENDING_Pos 31UL
|
||||
#define DW_CH_STRUCT_V2_CH_STATUS_PENDING_Msk 0x80000000UL
|
||||
/* DW_CH_STRUCT.CH_IDX */
|
||||
#define DW_CH_STRUCT_V2_CH_IDX_X_IDX_Pos 0UL
|
||||
#define DW_CH_STRUCT_V2_CH_IDX_X_IDX_Msk 0xFFUL
|
||||
#define DW_CH_STRUCT_V2_CH_IDX_Y_IDX_Pos 8UL
|
||||
#define DW_CH_STRUCT_V2_CH_IDX_Y_IDX_Msk 0xFF00UL
|
||||
/* DW_CH_STRUCT.CH_CURR_PTR */
|
||||
#define DW_CH_STRUCT_V2_CH_CURR_PTR_ADDR_Pos 2UL
|
||||
#define DW_CH_STRUCT_V2_CH_CURR_PTR_ADDR_Msk 0xFFFFFFFCUL
|
||||
/* DW_CH_STRUCT.INTR */
|
||||
#define DW_CH_STRUCT_V2_INTR_CH_Pos 0UL
|
||||
#define DW_CH_STRUCT_V2_INTR_CH_Msk 0x1UL
|
||||
/* DW_CH_STRUCT.INTR_SET */
|
||||
#define DW_CH_STRUCT_V2_INTR_SET_CH_Pos 0UL
|
||||
#define DW_CH_STRUCT_V2_INTR_SET_CH_Msk 0x1UL
|
||||
/* DW_CH_STRUCT.INTR_MASK */
|
||||
#define DW_CH_STRUCT_V2_INTR_MASK_CH_Pos 0UL
|
||||
#define DW_CH_STRUCT_V2_INTR_MASK_CH_Msk 0x1UL
|
||||
/* DW_CH_STRUCT.INTR_MASKED */
|
||||
#define DW_CH_STRUCT_V2_INTR_MASKED_CH_Pos 0UL
|
||||
#define DW_CH_STRUCT_V2_INTR_MASKED_CH_Msk 0x1UL
|
||||
/* DW_CH_STRUCT.SRAM_DATA0 */
|
||||
#define DW_CH_STRUCT_V2_SRAM_DATA0_DATA_Pos 0UL
|
||||
#define DW_CH_STRUCT_V2_SRAM_DATA0_DATA_Msk 0xFFFFFFFFUL
|
||||
/* DW_CH_STRUCT.SRAM_DATA1 */
|
||||
#define DW_CH_STRUCT_V2_SRAM_DATA1_DATA_Pos 0UL
|
||||
#define DW_CH_STRUCT_V2_SRAM_DATA1_DATA_Msk 0xFFFFFFFFUL
|
||||
|
||||
|
||||
/* DW.CTL */
|
||||
#define DW_V2_CTL_ECC_EN_Pos 0UL
|
||||
#define DW_V2_CTL_ECC_EN_Msk 0x1UL
|
||||
#define DW_V2_CTL_ECC_INJ_EN_Pos 1UL
|
||||
#define DW_V2_CTL_ECC_INJ_EN_Msk 0x2UL
|
||||
#define DW_V2_CTL_ENABLED_Pos 31UL
|
||||
#define DW_V2_CTL_ENABLED_Msk 0x80000000UL
|
||||
/* DW.STATUS */
|
||||
#define DW_V2_STATUS_P_Pos 0UL
|
||||
#define DW_V2_STATUS_P_Msk 0x1UL
|
||||
#define DW_V2_STATUS_NS_Pos 1UL
|
||||
#define DW_V2_STATUS_NS_Msk 0x2UL
|
||||
#define DW_V2_STATUS_B_Pos 2UL
|
||||
#define DW_V2_STATUS_B_Msk 0x4UL
|
||||
#define DW_V2_STATUS_PC_Pos 4UL
|
||||
#define DW_V2_STATUS_PC_Msk 0xF0UL
|
||||
#define DW_V2_STATUS_PRIO_Pos 8UL
|
||||
#define DW_V2_STATUS_PRIO_Msk 0x300UL
|
||||
#define DW_V2_STATUS_PREEMPTABLE_Pos 11UL
|
||||
#define DW_V2_STATUS_PREEMPTABLE_Msk 0x800UL
|
||||
#define DW_V2_STATUS_CH_IDX_Pos 16UL
|
||||
#define DW_V2_STATUS_CH_IDX_Msk 0x1FF0000UL
|
||||
#define DW_V2_STATUS_STATE_Pos 28UL
|
||||
#define DW_V2_STATUS_STATE_Msk 0x70000000UL
|
||||
#define DW_V2_STATUS_ACTIVE_Pos 31UL
|
||||
#define DW_V2_STATUS_ACTIVE_Msk 0x80000000UL
|
||||
/* DW.ACT_DESCR_CTL */
|
||||
#define DW_V2_ACT_DESCR_CTL_DATA_Pos 0UL
|
||||
#define DW_V2_ACT_DESCR_CTL_DATA_Msk 0xFFFFFFFFUL
|
||||
/* DW.ACT_DESCR_SRC */
|
||||
#define DW_V2_ACT_DESCR_SRC_DATA_Pos 0UL
|
||||
#define DW_V2_ACT_DESCR_SRC_DATA_Msk 0xFFFFFFFFUL
|
||||
/* DW.ACT_DESCR_DST */
|
||||
#define DW_V2_ACT_DESCR_DST_DATA_Pos 0UL
|
||||
#define DW_V2_ACT_DESCR_DST_DATA_Msk 0xFFFFFFFFUL
|
||||
/* DW.ACT_DESCR_X_CTL */
|
||||
#define DW_V2_ACT_DESCR_X_CTL_DATA_Pos 0UL
|
||||
#define DW_V2_ACT_DESCR_X_CTL_DATA_Msk 0xFFFFFFFFUL
|
||||
/* DW.ACT_DESCR_Y_CTL */
|
||||
#define DW_V2_ACT_DESCR_Y_CTL_DATA_Pos 0UL
|
||||
#define DW_V2_ACT_DESCR_Y_CTL_DATA_Msk 0xFFFFFFFFUL
|
||||
/* DW.ACT_DESCR_NEXT_PTR */
|
||||
#define DW_V2_ACT_DESCR_NEXT_PTR_ADDR_Pos 2UL
|
||||
#define DW_V2_ACT_DESCR_NEXT_PTR_ADDR_Msk 0xFFFFFFFCUL
|
||||
/* DW.ACT_SRC */
|
||||
#define DW_V2_ACT_SRC_SRC_ADDR_Pos 0UL
|
||||
#define DW_V2_ACT_SRC_SRC_ADDR_Msk 0xFFFFFFFFUL
|
||||
/* DW.ACT_DST */
|
||||
#define DW_V2_ACT_DST_DST_ADDR_Pos 0UL
|
||||
#define DW_V2_ACT_DST_DST_ADDR_Msk 0xFFFFFFFFUL
|
||||
/* DW.ECC_CTL */
|
||||
#define DW_V2_ECC_CTL_WORD_ADDR_Pos 0UL
|
||||
#define DW_V2_ECC_CTL_WORD_ADDR_Msk 0x3FFUL
|
||||
#define DW_V2_ECC_CTL_PARITY_Pos 25UL
|
||||
#define DW_V2_ECC_CTL_PARITY_Msk 0xFE000000UL
|
||||
/* DW.CRC_CTL */
|
||||
#define DW_V2_CRC_CTL_DATA_REVERSE_Pos 0UL
|
||||
#define DW_V2_CRC_CTL_DATA_REVERSE_Msk 0x1UL
|
||||
#define DW_V2_CRC_CTL_REM_REVERSE_Pos 8UL
|
||||
#define DW_V2_CRC_CTL_REM_REVERSE_Msk 0x100UL
|
||||
/* DW.CRC_DATA_CTL */
|
||||
#define DW_V2_CRC_DATA_CTL_DATA_XOR_Pos 0UL
|
||||
#define DW_V2_CRC_DATA_CTL_DATA_XOR_Msk 0xFFUL
|
||||
/* DW.CRC_POL_CTL */
|
||||
#define DW_V2_CRC_POL_CTL_POLYNOMIAL_Pos 0UL
|
||||
#define DW_V2_CRC_POL_CTL_POLYNOMIAL_Msk 0xFFFFFFFFUL
|
||||
/* DW.CRC_LFSR_CTL */
|
||||
#define DW_V2_CRC_LFSR_CTL_LFSR32_Pos 0UL
|
||||
#define DW_V2_CRC_LFSR_CTL_LFSR32_Msk 0xFFFFFFFFUL
|
||||
/* DW.CRC_REM_CTL */
|
||||
#define DW_V2_CRC_REM_CTL_REM_XOR_Pos 0UL
|
||||
#define DW_V2_CRC_REM_CTL_REM_XOR_Msk 0xFFFFFFFFUL
|
||||
/* DW.CRC_REM_RESULT */
|
||||
#define DW_V2_CRC_REM_RESULT_REM_Pos 0UL
|
||||
#define DW_V2_CRC_REM_RESULT_REM_Msk 0xFFFFFFFFUL
|
||||
|
||||
|
||||
#endif /* _CYIP_DW_V2_H_ */
|
||||
|
||||
|
||||
/* [] END OF FILE */
|
||||
|
|
@ -1,319 +0,0 @@
|
|||
/***************************************************************************//**
|
||||
* \file cyip_efuse.h
|
||||
*
|
||||
* \brief
|
||||
* EFUSE IP definitions
|
||||
*
|
||||
* \note
|
||||
* Generator version: 1.3.0.1146
|
||||
* Database revision: rev#1050929
|
||||
*
|
||||
********************************************************************************
|
||||
* \copyright
|
||||
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
|
||||
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _CYIP_EFUSE_H_
|
||||
#define _CYIP_EFUSE_H_
|
||||
|
||||
#include "cyip_headers.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* EFUSE
|
||||
*******************************************************************************/
|
||||
|
||||
#define EFUSE_SECTION_SIZE 0x00000080UL
|
||||
|
||||
/**
|
||||
* \brief EFUSE MXS40 registers (EFUSE)
|
||||
*/
|
||||
typedef struct {
|
||||
__IOM uint32_t CTL; /*!< 0x00000000 Control */
|
||||
__IM uint32_t RESERVED[3];
|
||||
__IOM uint32_t CMD; /*!< 0x00000010 Command */
|
||||
__IM uint32_t RESERVED1[3];
|
||||
__IOM uint32_t SEQ_DEFAULT; /*!< 0x00000020 Sequencer Default value */
|
||||
__IM uint32_t RESERVED2[7];
|
||||
__IOM uint32_t SEQ_READ_CTL_0; /*!< 0x00000040 Sequencer read control 0 */
|
||||
__IOM uint32_t SEQ_READ_CTL_1; /*!< 0x00000044 Sequencer read control 1 */
|
||||
__IOM uint32_t SEQ_READ_CTL_2; /*!< 0x00000048 Sequencer read control 2 */
|
||||
__IOM uint32_t SEQ_READ_CTL_3; /*!< 0x0000004C Sequencer read control 3 */
|
||||
__IOM uint32_t SEQ_READ_CTL_4; /*!< 0x00000050 Sequencer read control 4 */
|
||||
__IOM uint32_t SEQ_READ_CTL_5; /*!< 0x00000054 Sequencer read control 5 */
|
||||
__IM uint32_t RESERVED3[2];
|
||||
__IOM uint32_t SEQ_PROGRAM_CTL_0; /*!< 0x00000060 Sequencer program control 0 */
|
||||
__IOM uint32_t SEQ_PROGRAM_CTL_1; /*!< 0x00000064 Sequencer program control 1 */
|
||||
__IOM uint32_t SEQ_PROGRAM_CTL_2; /*!< 0x00000068 Sequencer program control 2 */
|
||||
__IOM uint32_t SEQ_PROGRAM_CTL_3; /*!< 0x0000006C Sequencer program control 3 */
|
||||
__IOM uint32_t SEQ_PROGRAM_CTL_4; /*!< 0x00000070 Sequencer program control 4 */
|
||||
__IOM uint32_t SEQ_PROGRAM_CTL_5; /*!< 0x00000074 Sequencer program control 5 */
|
||||
} EFUSE_V1_Type; /*!< Size = 120 (0x78) */
|
||||
|
||||
|
||||
/* EFUSE.CTL */
|
||||
#define EFUSE_CTL_ENABLED_Pos 31UL
|
||||
#define EFUSE_CTL_ENABLED_Msk 0x80000000UL
|
||||
/* EFUSE.CMD */
|
||||
#define EFUSE_CMD_BIT_DATA_Pos 0UL
|
||||
#define EFUSE_CMD_BIT_DATA_Msk 0x1UL
|
||||
#define EFUSE_CMD_BIT_ADDR_Pos 4UL
|
||||
#define EFUSE_CMD_BIT_ADDR_Msk 0x70UL
|
||||
#define EFUSE_CMD_BYTE_ADDR_Pos 8UL
|
||||
#define EFUSE_CMD_BYTE_ADDR_Msk 0x1F00UL
|
||||
#define EFUSE_CMD_MACRO_ADDR_Pos 16UL
|
||||
#define EFUSE_CMD_MACRO_ADDR_Msk 0xF0000UL
|
||||
#define EFUSE_CMD_START_Pos 31UL
|
||||
#define EFUSE_CMD_START_Msk 0x80000000UL
|
||||
/* EFUSE.SEQ_DEFAULT */
|
||||
#define EFUSE_SEQ_DEFAULT_STROBE_A_Pos 16UL
|
||||
#define EFUSE_SEQ_DEFAULT_STROBE_A_Msk 0x10000UL
|
||||
#define EFUSE_SEQ_DEFAULT_STROBE_B_Pos 17UL
|
||||
#define EFUSE_SEQ_DEFAULT_STROBE_B_Msk 0x20000UL
|
||||
#define EFUSE_SEQ_DEFAULT_STROBE_C_Pos 18UL
|
||||
#define EFUSE_SEQ_DEFAULT_STROBE_C_Msk 0x40000UL
|
||||
#define EFUSE_SEQ_DEFAULT_STROBE_D_Pos 19UL
|
||||
#define EFUSE_SEQ_DEFAULT_STROBE_D_Msk 0x80000UL
|
||||
#define EFUSE_SEQ_DEFAULT_STROBE_E_Pos 20UL
|
||||
#define EFUSE_SEQ_DEFAULT_STROBE_E_Msk 0x100000UL
|
||||
#define EFUSE_SEQ_DEFAULT_STROBE_F_Pos 21UL
|
||||
#define EFUSE_SEQ_DEFAULT_STROBE_F_Msk 0x200000UL
|
||||
#define EFUSE_SEQ_DEFAULT_STROBE_G_Pos 22UL
|
||||
#define EFUSE_SEQ_DEFAULT_STROBE_G_Msk 0x400000UL
|
||||
/* EFUSE.SEQ_READ_CTL_0 */
|
||||
#define EFUSE_SEQ_READ_CTL_0_CYCLES_Pos 0UL
|
||||
#define EFUSE_SEQ_READ_CTL_0_CYCLES_Msk 0x3FFUL
|
||||
#define EFUSE_SEQ_READ_CTL_0_STROBE_A_Pos 16UL
|
||||
#define EFUSE_SEQ_READ_CTL_0_STROBE_A_Msk 0x10000UL
|
||||
#define EFUSE_SEQ_READ_CTL_0_STROBE_B_Pos 17UL
|
||||
#define EFUSE_SEQ_READ_CTL_0_STROBE_B_Msk 0x20000UL
|
||||
#define EFUSE_SEQ_READ_CTL_0_STROBE_C_Pos 18UL
|
||||
#define EFUSE_SEQ_READ_CTL_0_STROBE_C_Msk 0x40000UL
|
||||
#define EFUSE_SEQ_READ_CTL_0_STROBE_D_Pos 19UL
|
||||
#define EFUSE_SEQ_READ_CTL_0_STROBE_D_Msk 0x80000UL
|
||||
#define EFUSE_SEQ_READ_CTL_0_STROBE_E_Pos 20UL
|
||||
#define EFUSE_SEQ_READ_CTL_0_STROBE_E_Msk 0x100000UL
|
||||
#define EFUSE_SEQ_READ_CTL_0_STROBE_F_Pos 21UL
|
||||
#define EFUSE_SEQ_READ_CTL_0_STROBE_F_Msk 0x200000UL
|
||||
#define EFUSE_SEQ_READ_CTL_0_STROBE_G_Pos 22UL
|
||||
#define EFUSE_SEQ_READ_CTL_0_STROBE_G_Msk 0x400000UL
|
||||
#define EFUSE_SEQ_READ_CTL_0_DONE_Pos 31UL
|
||||
#define EFUSE_SEQ_READ_CTL_0_DONE_Msk 0x80000000UL
|
||||
/* EFUSE.SEQ_READ_CTL_1 */
|
||||
#define EFUSE_SEQ_READ_CTL_1_CYCLES_Pos 0UL
|
||||
#define EFUSE_SEQ_READ_CTL_1_CYCLES_Msk 0x3FFUL
|
||||
#define EFUSE_SEQ_READ_CTL_1_STROBE_A_Pos 16UL
|
||||
#define EFUSE_SEQ_READ_CTL_1_STROBE_A_Msk 0x10000UL
|
||||
#define EFUSE_SEQ_READ_CTL_1_STROBE_B_Pos 17UL
|
||||
#define EFUSE_SEQ_READ_CTL_1_STROBE_B_Msk 0x20000UL
|
||||
#define EFUSE_SEQ_READ_CTL_1_STROBE_C_Pos 18UL
|
||||
#define EFUSE_SEQ_READ_CTL_1_STROBE_C_Msk 0x40000UL
|
||||
#define EFUSE_SEQ_READ_CTL_1_STROBE_D_Pos 19UL
|
||||
#define EFUSE_SEQ_READ_CTL_1_STROBE_D_Msk 0x80000UL
|
||||
#define EFUSE_SEQ_READ_CTL_1_STROBE_E_Pos 20UL
|
||||
#define EFUSE_SEQ_READ_CTL_1_STROBE_E_Msk 0x100000UL
|
||||
#define EFUSE_SEQ_READ_CTL_1_STROBE_F_Pos 21UL
|
||||
#define EFUSE_SEQ_READ_CTL_1_STROBE_F_Msk 0x200000UL
|
||||
#define EFUSE_SEQ_READ_CTL_1_STROBE_G_Pos 22UL
|
||||
#define EFUSE_SEQ_READ_CTL_1_STROBE_G_Msk 0x400000UL
|
||||
#define EFUSE_SEQ_READ_CTL_1_DONE_Pos 31UL
|
||||
#define EFUSE_SEQ_READ_CTL_1_DONE_Msk 0x80000000UL
|
||||
/* EFUSE.SEQ_READ_CTL_2 */
|
||||
#define EFUSE_SEQ_READ_CTL_2_CYCLES_Pos 0UL
|
||||
#define EFUSE_SEQ_READ_CTL_2_CYCLES_Msk 0x3FFUL
|
||||
#define EFUSE_SEQ_READ_CTL_2_STROBE_A_Pos 16UL
|
||||
#define EFUSE_SEQ_READ_CTL_2_STROBE_A_Msk 0x10000UL
|
||||
#define EFUSE_SEQ_READ_CTL_2_STROBE_B_Pos 17UL
|
||||
#define EFUSE_SEQ_READ_CTL_2_STROBE_B_Msk 0x20000UL
|
||||
#define EFUSE_SEQ_READ_CTL_2_STROBE_C_Pos 18UL
|
||||
#define EFUSE_SEQ_READ_CTL_2_STROBE_C_Msk 0x40000UL
|
||||
#define EFUSE_SEQ_READ_CTL_2_STROBE_D_Pos 19UL
|
||||
#define EFUSE_SEQ_READ_CTL_2_STROBE_D_Msk 0x80000UL
|
||||
#define EFUSE_SEQ_READ_CTL_2_STROBE_E_Pos 20UL
|
||||
#define EFUSE_SEQ_READ_CTL_2_STROBE_E_Msk 0x100000UL
|
||||
#define EFUSE_SEQ_READ_CTL_2_STROBE_F_Pos 21UL
|
||||
#define EFUSE_SEQ_READ_CTL_2_STROBE_F_Msk 0x200000UL
|
||||
#define EFUSE_SEQ_READ_CTL_2_STROBE_G_Pos 22UL
|
||||
#define EFUSE_SEQ_READ_CTL_2_STROBE_G_Msk 0x400000UL
|
||||
#define EFUSE_SEQ_READ_CTL_2_DONE_Pos 31UL
|
||||
#define EFUSE_SEQ_READ_CTL_2_DONE_Msk 0x80000000UL
|
||||
/* EFUSE.SEQ_READ_CTL_3 */
|
||||
#define EFUSE_SEQ_READ_CTL_3_CYCLES_Pos 0UL
|
||||
#define EFUSE_SEQ_READ_CTL_3_CYCLES_Msk 0x3FFUL
|
||||
#define EFUSE_SEQ_READ_CTL_3_STROBE_A_Pos 16UL
|
||||
#define EFUSE_SEQ_READ_CTL_3_STROBE_A_Msk 0x10000UL
|
||||
#define EFUSE_SEQ_READ_CTL_3_STROBE_B_Pos 17UL
|
||||
#define EFUSE_SEQ_READ_CTL_3_STROBE_B_Msk 0x20000UL
|
||||
#define EFUSE_SEQ_READ_CTL_3_STROBE_C_Pos 18UL
|
||||
#define EFUSE_SEQ_READ_CTL_3_STROBE_C_Msk 0x40000UL
|
||||
#define EFUSE_SEQ_READ_CTL_3_STROBE_D_Pos 19UL
|
||||
#define EFUSE_SEQ_READ_CTL_3_STROBE_D_Msk 0x80000UL
|
||||
#define EFUSE_SEQ_READ_CTL_3_STROBE_E_Pos 20UL
|
||||
#define EFUSE_SEQ_READ_CTL_3_STROBE_E_Msk 0x100000UL
|
||||
#define EFUSE_SEQ_READ_CTL_3_STROBE_F_Pos 21UL
|
||||
#define EFUSE_SEQ_READ_CTL_3_STROBE_F_Msk 0x200000UL
|
||||
#define EFUSE_SEQ_READ_CTL_3_STROBE_G_Pos 22UL
|
||||
#define EFUSE_SEQ_READ_CTL_3_STROBE_G_Msk 0x400000UL
|
||||
#define EFUSE_SEQ_READ_CTL_3_DONE_Pos 31UL
|
||||
#define EFUSE_SEQ_READ_CTL_3_DONE_Msk 0x80000000UL
|
||||
/* EFUSE.SEQ_READ_CTL_4 */
|
||||
#define EFUSE_SEQ_READ_CTL_4_CYCLES_Pos 0UL
|
||||
#define EFUSE_SEQ_READ_CTL_4_CYCLES_Msk 0x3FFUL
|
||||
#define EFUSE_SEQ_READ_CTL_4_STROBE_A_Pos 16UL
|
||||
#define EFUSE_SEQ_READ_CTL_4_STROBE_A_Msk 0x10000UL
|
||||
#define EFUSE_SEQ_READ_CTL_4_STROBE_B_Pos 17UL
|
||||
#define EFUSE_SEQ_READ_CTL_4_STROBE_B_Msk 0x20000UL
|
||||
#define EFUSE_SEQ_READ_CTL_4_STROBE_C_Pos 18UL
|
||||
#define EFUSE_SEQ_READ_CTL_4_STROBE_C_Msk 0x40000UL
|
||||
#define EFUSE_SEQ_READ_CTL_4_STROBE_D_Pos 19UL
|
||||
#define EFUSE_SEQ_READ_CTL_4_STROBE_D_Msk 0x80000UL
|
||||
#define EFUSE_SEQ_READ_CTL_4_STROBE_E_Pos 20UL
|
||||
#define EFUSE_SEQ_READ_CTL_4_STROBE_E_Msk 0x100000UL
|
||||
#define EFUSE_SEQ_READ_CTL_4_STROBE_F_Pos 21UL
|
||||
#define EFUSE_SEQ_READ_CTL_4_STROBE_F_Msk 0x200000UL
|
||||
#define EFUSE_SEQ_READ_CTL_4_STROBE_G_Pos 22UL
|
||||
#define EFUSE_SEQ_READ_CTL_4_STROBE_G_Msk 0x400000UL
|
||||
#define EFUSE_SEQ_READ_CTL_4_DONE_Pos 31UL
|
||||
#define EFUSE_SEQ_READ_CTL_4_DONE_Msk 0x80000000UL
|
||||
/* EFUSE.SEQ_READ_CTL_5 */
|
||||
#define EFUSE_SEQ_READ_CTL_5_CYCLES_Pos 0UL
|
||||
#define EFUSE_SEQ_READ_CTL_5_CYCLES_Msk 0x3FFUL
|
||||
#define EFUSE_SEQ_READ_CTL_5_STROBE_A_Pos 16UL
|
||||
#define EFUSE_SEQ_READ_CTL_5_STROBE_A_Msk 0x10000UL
|
||||
#define EFUSE_SEQ_READ_CTL_5_STROBE_B_Pos 17UL
|
||||
#define EFUSE_SEQ_READ_CTL_5_STROBE_B_Msk 0x20000UL
|
||||
#define EFUSE_SEQ_READ_CTL_5_STROBE_C_Pos 18UL
|
||||
#define EFUSE_SEQ_READ_CTL_5_STROBE_C_Msk 0x40000UL
|
||||
#define EFUSE_SEQ_READ_CTL_5_STROBE_D_Pos 19UL
|
||||
#define EFUSE_SEQ_READ_CTL_5_STROBE_D_Msk 0x80000UL
|
||||
#define EFUSE_SEQ_READ_CTL_5_STROBE_E_Pos 20UL
|
||||
#define EFUSE_SEQ_READ_CTL_5_STROBE_E_Msk 0x100000UL
|
||||
#define EFUSE_SEQ_READ_CTL_5_STROBE_F_Pos 21UL
|
||||
#define EFUSE_SEQ_READ_CTL_5_STROBE_F_Msk 0x200000UL
|
||||
#define EFUSE_SEQ_READ_CTL_5_STROBE_G_Pos 22UL
|
||||
#define EFUSE_SEQ_READ_CTL_5_STROBE_G_Msk 0x400000UL
|
||||
#define EFUSE_SEQ_READ_CTL_5_DONE_Pos 31UL
|
||||
#define EFUSE_SEQ_READ_CTL_5_DONE_Msk 0x80000000UL
|
||||
/* EFUSE.SEQ_PROGRAM_CTL_0 */
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_0_CYCLES_Pos 0UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_0_CYCLES_Msk 0x3FFUL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_0_STROBE_A_Pos 16UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_0_STROBE_A_Msk 0x10000UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_0_STROBE_B_Pos 17UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_0_STROBE_B_Msk 0x20000UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_0_STROBE_C_Pos 18UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_0_STROBE_C_Msk 0x40000UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_0_STROBE_D_Pos 19UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_0_STROBE_D_Msk 0x80000UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_0_STROBE_E_Pos 20UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_0_STROBE_E_Msk 0x100000UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_0_STROBE_F_Pos 21UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_0_STROBE_F_Msk 0x200000UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_0_STROBE_G_Pos 22UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_0_STROBE_G_Msk 0x400000UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_0_DONE_Pos 31UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_0_DONE_Msk 0x80000000UL
|
||||
/* EFUSE.SEQ_PROGRAM_CTL_1 */
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_1_CYCLES_Pos 0UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_1_CYCLES_Msk 0x3FFUL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_1_STROBE_A_Pos 16UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_1_STROBE_A_Msk 0x10000UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_1_STROBE_B_Pos 17UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_1_STROBE_B_Msk 0x20000UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_1_STROBE_C_Pos 18UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_1_STROBE_C_Msk 0x40000UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_1_STROBE_D_Pos 19UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_1_STROBE_D_Msk 0x80000UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_1_STROBE_E_Pos 20UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_1_STROBE_E_Msk 0x100000UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_1_STROBE_F_Pos 21UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_1_STROBE_F_Msk 0x200000UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_1_STROBE_G_Pos 22UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_1_STROBE_G_Msk 0x400000UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_1_DONE_Pos 31UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_1_DONE_Msk 0x80000000UL
|
||||
/* EFUSE.SEQ_PROGRAM_CTL_2 */
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_2_CYCLES_Pos 0UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_2_CYCLES_Msk 0x3FFUL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_2_STROBE_A_Pos 16UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_2_STROBE_A_Msk 0x10000UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_2_STROBE_B_Pos 17UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_2_STROBE_B_Msk 0x20000UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_2_STROBE_C_Pos 18UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_2_STROBE_C_Msk 0x40000UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_2_STROBE_D_Pos 19UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_2_STROBE_D_Msk 0x80000UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_2_STROBE_E_Pos 20UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_2_STROBE_E_Msk 0x100000UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_2_STROBE_F_Pos 21UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_2_STROBE_F_Msk 0x200000UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_2_STROBE_G_Pos 22UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_2_STROBE_G_Msk 0x400000UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_2_DONE_Pos 31UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_2_DONE_Msk 0x80000000UL
|
||||
/* EFUSE.SEQ_PROGRAM_CTL_3 */
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_3_CYCLES_Pos 0UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_3_CYCLES_Msk 0x3FFUL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_3_STROBE_A_Pos 16UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_3_STROBE_A_Msk 0x10000UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_3_STROBE_B_Pos 17UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_3_STROBE_B_Msk 0x20000UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_3_STROBE_C_Pos 18UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_3_STROBE_C_Msk 0x40000UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_3_STROBE_D_Pos 19UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_3_STROBE_D_Msk 0x80000UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_3_STROBE_E_Pos 20UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_3_STROBE_E_Msk 0x100000UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_3_STROBE_F_Pos 21UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_3_STROBE_F_Msk 0x200000UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_3_STROBE_G_Pos 22UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_3_STROBE_G_Msk 0x400000UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_3_DONE_Pos 31UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_3_DONE_Msk 0x80000000UL
|
||||
/* EFUSE.SEQ_PROGRAM_CTL_4 */
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_4_CYCLES_Pos 0UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_4_CYCLES_Msk 0x3FFUL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_4_STROBE_A_Pos 16UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_4_STROBE_A_Msk 0x10000UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_4_STROBE_B_Pos 17UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_4_STROBE_B_Msk 0x20000UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_4_STROBE_C_Pos 18UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_4_STROBE_C_Msk 0x40000UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_4_STROBE_D_Pos 19UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_4_STROBE_D_Msk 0x80000UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_4_STROBE_E_Pos 20UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_4_STROBE_E_Msk 0x100000UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_4_STROBE_F_Pos 21UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_4_STROBE_F_Msk 0x200000UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_4_STROBE_G_Pos 22UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_4_STROBE_G_Msk 0x400000UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_4_DONE_Pos 31UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_4_DONE_Msk 0x80000000UL
|
||||
/* EFUSE.SEQ_PROGRAM_CTL_5 */
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_5_CYCLES_Pos 0UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_5_CYCLES_Msk 0x3FFUL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_5_STROBE_A_Pos 16UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_5_STROBE_A_Msk 0x10000UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_5_STROBE_B_Pos 17UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_5_STROBE_B_Msk 0x20000UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_5_STROBE_C_Pos 18UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_5_STROBE_C_Msk 0x40000UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_5_STROBE_D_Pos 19UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_5_STROBE_D_Msk 0x80000UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_5_STROBE_E_Pos 20UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_5_STROBE_E_Msk 0x100000UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_5_STROBE_F_Pos 21UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_5_STROBE_F_Msk 0x200000UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_5_STROBE_G_Pos 22UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_5_STROBE_G_Msk 0x400000UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_5_DONE_Pos 31UL
|
||||
#define EFUSE_SEQ_PROGRAM_CTL_5_DONE_Msk 0x80000000UL
|
||||
|
||||
|
||||
#endif /* _CYIP_EFUSE_H_ */
|
||||
|
||||
|
||||
/* [] END OF FILE */
|
||||
|
|
@ -1,116 +0,0 @@
|
|||
/***************************************************************************//**
|
||||
* \file cyip_efuse_data.h
|
||||
*
|
||||
* \brief
|
||||
* EFUSE_DATA IP definitions
|
||||
*
|
||||
* \note
|
||||
* Generator version: 1.3.0.1146
|
||||
* Database revision: rev#1050929
|
||||
*
|
||||
********************************************************************************
|
||||
* \copyright
|
||||
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
|
||||
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _CYIP_EFUSE_DATA_H_
|
||||
#define _CYIP_EFUSE_DATA_H_
|
||||
|
||||
#include "cyip_headers.h"
|
||||
|
||||
/**
|
||||
* \brief DEAD access restrictions (DEAD_ACCESS_RESTRICT0)
|
||||
*/
|
||||
typedef struct {
|
||||
uint8_t AP_CTL_CM0_DISABLE[2];
|
||||
uint8_t AP_CTL_CM4_DISABLE[2];
|
||||
uint8_t AP_CTL_SYS_DISABLE[2];
|
||||
uint8_t SYS_AP_MPU_ENABLE;
|
||||
uint8_t DIRECT_EXECUTE_DISABLE;
|
||||
} cy_stc_dead_access_restrict0_t;
|
||||
|
||||
/**
|
||||
* \brief DEAD access restrictions (DEAD_ACCESS_RESTRICT1)
|
||||
*/
|
||||
typedef struct {
|
||||
uint8_t FLASH_ALLOWED[3];
|
||||
uint8_t SRAM_ALLOWED[3];
|
||||
uint8_t SFLASH_ALLOWED[2];
|
||||
} cy_stc_dead_access_restrict1_t;
|
||||
|
||||
/**
|
||||
* \brief SECURE access restrictions (SECURE_ACCESS_RESTRICT0)
|
||||
*/
|
||||
typedef struct {
|
||||
uint8_t AP_CTL_CM0_DISABLE[2];
|
||||
uint8_t AP_CTL_CM4_DISABLE[2];
|
||||
uint8_t AP_CTL_SYS_DISABLE[2];
|
||||
uint8_t SYS_AP_MPU_ENABLE;
|
||||
uint8_t DIRECT_EXECUTE_DISABLE;
|
||||
} cy_stc_secure_access_restrict0_t;
|
||||
|
||||
/**
|
||||
* \brief SECURE access restrictions (SECURE_ACCESS_RESTRICT1)
|
||||
*/
|
||||
typedef struct {
|
||||
uint8_t FLASH_ALLOWED[3];
|
||||
uint8_t SRAM_ALLOWED[3];
|
||||
uint8_t SFLASH_ALLOWED[2];
|
||||
} cy_stc_secure_access_restrict1_t;
|
||||
|
||||
/**
|
||||
* \brief NORMAL, SECURE_WITH_DEBUG, SECURE, and NORMAL_NO_SECURE fuse bits (LIFECYCLE_STAGE)
|
||||
*/
|
||||
typedef struct {
|
||||
uint8_t NORMAL;
|
||||
uint8_t SECURE_WITH_DEBUG;
|
||||
uint8_t SECURE;
|
||||
uint8_t RMA;
|
||||
uint8_t NORMAL_NO_SECURE;
|
||||
uint8_t RESERVED;
|
||||
uint8_t DEAD_WORK_FLASH_ALLOWED[2];
|
||||
} cy_stc_lifecycle_stage_t;
|
||||
|
||||
/**
|
||||
* \brief MMIO_SMIF_ACCESS_RESTRICT (MMIO_SMIF_ACCESS_RESTRICT)
|
||||
*/
|
||||
typedef struct {
|
||||
uint8_t DEAD_MMIO_ALLOWED[2];
|
||||
uint8_t DEAD_SMIF_XIP_ALLOWED;
|
||||
uint8_t SECURE_MMIO_ALLOWED[2];
|
||||
uint8_t SECURE_SMIF_XIP_ALLOWED;
|
||||
uint8_t SECURE_WORK_FLASH_ALLOWED[2];
|
||||
} cy_stc_mmio_smif_access_restrict_t;
|
||||
|
||||
/**
|
||||
* \brief Customer data (CUSTOMER_DATA)
|
||||
*/
|
||||
typedef struct {
|
||||
uint8_t CUSTOMER_USE[8];
|
||||
} cy_stc_customer_data_t;
|
||||
|
||||
|
||||
/**
|
||||
* \brief eFUSE memory (EFUSE_DATA)
|
||||
*/
|
||||
typedef struct {
|
||||
uint8_t RESERVED[312];
|
||||
cy_stc_dead_access_restrict0_t DEAD_ACCESS_RESTRICT0;
|
||||
cy_stc_dead_access_restrict1_t DEAD_ACCESS_RESTRICT1;
|
||||
cy_stc_secure_access_restrict0_t SECURE_ACCESS_RESTRICT0;
|
||||
cy_stc_secure_access_restrict1_t SECURE_ACCESS_RESTRICT1;
|
||||
cy_stc_lifecycle_stage_t LIFECYCLE_STAGE;
|
||||
uint8_t RESERVED1[152];
|
||||
cy_stc_mmio_smif_access_restrict_t MMIO_SMIF_ACCESS_RESTRICT;
|
||||
cy_stc_customer_data_t CUSTOMER_DATA[64];
|
||||
} cy_stc_efuse_data_t;
|
||||
|
||||
|
||||
#endif /* _CYIP_EFUSE_DATA_H_ */
|
||||
|
||||
|
||||
/* [] END OF FILE */
|
||||
|
|
@ -1,114 +0,0 @@
|
|||
/***************************************************************************//**
|
||||
* \file cyip_fault.h
|
||||
*
|
||||
* \brief
|
||||
* FAULT IP definitions
|
||||
*
|
||||
* \note
|
||||
* Generator version: 1.3.0.1146
|
||||
* Database revision: rev#1050929
|
||||
*
|
||||
********************************************************************************
|
||||
* \copyright
|
||||
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
|
||||
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _CYIP_FAULT_H_
|
||||
#define _CYIP_FAULT_H_
|
||||
|
||||
#include "cyip_headers.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* FAULT
|
||||
*******************************************************************************/
|
||||
|
||||
#define FAULT_STRUCT_SECTION_SIZE 0x00000100UL
|
||||
#define FAULT_SECTION_SIZE 0x00010000UL
|
||||
|
||||
/**
|
||||
* \brief Fault structure (FAULT_STRUCT)
|
||||
*/
|
||||
typedef struct {
|
||||
__IOM uint32_t CTL; /*!< 0x00000000 Fault control */
|
||||
__IM uint32_t RESERVED[2];
|
||||
__IOM uint32_t STATUS; /*!< 0x0000000C Fault status */
|
||||
__IM uint32_t DATA[4]; /*!< 0x00000010 Fault data */
|
||||
__IM uint32_t RESERVED1[8];
|
||||
__IM uint32_t PENDING0; /*!< 0x00000040 Fault pending 0 */
|
||||
__IM uint32_t PENDING1; /*!< 0x00000044 Fault pending 1 */
|
||||
__IM uint32_t PENDING2; /*!< 0x00000048 Fault pending 2 */
|
||||
__IM uint32_t RESERVED2;
|
||||
__IOM uint32_t MASK0; /*!< 0x00000050 Fault mask 0 */
|
||||
__IOM uint32_t MASK1; /*!< 0x00000054 Fault mask 1 */
|
||||
__IOM uint32_t MASK2; /*!< 0x00000058 Fault mask 2 */
|
||||
__IM uint32_t RESERVED3[25];
|
||||
__IOM uint32_t INTR; /*!< 0x000000C0 Interrupt */
|
||||
__IOM uint32_t INTR_SET; /*!< 0x000000C4 Interrupt set */
|
||||
__IOM uint32_t INTR_MASK; /*!< 0x000000C8 Interrupt mask */
|
||||
__IM uint32_t INTR_MASKED; /*!< 0x000000CC Interrupt masked */
|
||||
__IM uint32_t RESERVED4[12];
|
||||
} FAULT_STRUCT_V1_Type; /*!< Size = 256 (0x100) */
|
||||
|
||||
/**
|
||||
* \brief Fault structures (FAULT)
|
||||
*/
|
||||
typedef struct {
|
||||
FAULT_STRUCT_V1_Type STRUCT[4]; /*!< 0x00000000 Fault structure */
|
||||
} FAULT_V1_Type; /*!< Size = 1024 (0x400) */
|
||||
|
||||
|
||||
/* FAULT_STRUCT.CTL */
|
||||
#define FAULT_STRUCT_CTL_TR_EN_Pos 0UL
|
||||
#define FAULT_STRUCT_CTL_TR_EN_Msk 0x1UL
|
||||
#define FAULT_STRUCT_CTL_OUT_EN_Pos 1UL
|
||||
#define FAULT_STRUCT_CTL_OUT_EN_Msk 0x2UL
|
||||
#define FAULT_STRUCT_CTL_RESET_REQ_EN_Pos 2UL
|
||||
#define FAULT_STRUCT_CTL_RESET_REQ_EN_Msk 0x4UL
|
||||
/* FAULT_STRUCT.STATUS */
|
||||
#define FAULT_STRUCT_STATUS_IDX_Pos 0UL
|
||||
#define FAULT_STRUCT_STATUS_IDX_Msk 0x7FUL
|
||||
#define FAULT_STRUCT_STATUS_VALID_Pos 31UL
|
||||
#define FAULT_STRUCT_STATUS_VALID_Msk 0x80000000UL
|
||||
/* FAULT_STRUCT.DATA */
|
||||
#define FAULT_STRUCT_DATA_DATA_Pos 0UL
|
||||
#define FAULT_STRUCT_DATA_DATA_Msk 0xFFFFFFFFUL
|
||||
/* FAULT_STRUCT.PENDING0 */
|
||||
#define FAULT_STRUCT_PENDING0_SOURCE_Pos 0UL
|
||||
#define FAULT_STRUCT_PENDING0_SOURCE_Msk 0xFFFFFFFFUL
|
||||
/* FAULT_STRUCT.PENDING1 */
|
||||
#define FAULT_STRUCT_PENDING1_SOURCE_Pos 0UL
|
||||
#define FAULT_STRUCT_PENDING1_SOURCE_Msk 0xFFFFFFFFUL
|
||||
/* FAULT_STRUCT.PENDING2 */
|
||||
#define FAULT_STRUCT_PENDING2_SOURCE_Pos 0UL
|
||||
#define FAULT_STRUCT_PENDING2_SOURCE_Msk 0xFFFFFFFFUL
|
||||
/* FAULT_STRUCT.MASK0 */
|
||||
#define FAULT_STRUCT_MASK0_SOURCE_Pos 0UL
|
||||
#define FAULT_STRUCT_MASK0_SOURCE_Msk 0xFFFFFFFFUL
|
||||
/* FAULT_STRUCT.MASK1 */
|
||||
#define FAULT_STRUCT_MASK1_SOURCE_Pos 0UL
|
||||
#define FAULT_STRUCT_MASK1_SOURCE_Msk 0xFFFFFFFFUL
|
||||
/* FAULT_STRUCT.MASK2 */
|
||||
#define FAULT_STRUCT_MASK2_SOURCE_Pos 0UL
|
||||
#define FAULT_STRUCT_MASK2_SOURCE_Msk 0xFFFFFFFFUL
|
||||
/* FAULT_STRUCT.INTR */
|
||||
#define FAULT_STRUCT_INTR_FAULT_Pos 0UL
|
||||
#define FAULT_STRUCT_INTR_FAULT_Msk 0x1UL
|
||||
/* FAULT_STRUCT.INTR_SET */
|
||||
#define FAULT_STRUCT_INTR_SET_FAULT_Pos 0UL
|
||||
#define FAULT_STRUCT_INTR_SET_FAULT_Msk 0x1UL
|
||||
/* FAULT_STRUCT.INTR_MASK */
|
||||
#define FAULT_STRUCT_INTR_MASK_FAULT_Pos 0UL
|
||||
#define FAULT_STRUCT_INTR_MASK_FAULT_Msk 0x1UL
|
||||
/* FAULT_STRUCT.INTR_MASKED */
|
||||
#define FAULT_STRUCT_INTR_MASKED_FAULT_Pos 0UL
|
||||
#define FAULT_STRUCT_INTR_MASKED_FAULT_Msk 0x1UL
|
||||
|
||||
|
||||
#endif /* _CYIP_FAULT_H_ */
|
||||
|
||||
|
||||
/* [] END OF FILE */
|
||||
|
|
@ -1,114 +0,0 @@
|
|||
/***************************************************************************//**
|
||||
* \file cyip_fault_v2.h
|
||||
*
|
||||
* \brief
|
||||
* FAULT IP definitions
|
||||
*
|
||||
* \note
|
||||
* Generator version: 1.3.0.1146
|
||||
* Database revision: rev#1050929
|
||||
*
|
||||
********************************************************************************
|
||||
* \copyright
|
||||
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
|
||||
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _CYIP_FAULT_V2_H_
|
||||
#define _CYIP_FAULT_V2_H_
|
||||
|
||||
#include "cyip_headers.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* FAULT
|
||||
*******************************************************************************/
|
||||
|
||||
#define FAULT_STRUCT_V2_SECTION_SIZE 0x00000100UL
|
||||
#define FAULT_V2_SECTION_SIZE 0x00010000UL
|
||||
|
||||
/**
|
||||
* \brief Fault structure (FAULT_STRUCT)
|
||||
*/
|
||||
typedef struct {
|
||||
__IOM uint32_t CTL; /*!< 0x00000000 Fault control */
|
||||
__IM uint32_t RESERVED[2];
|
||||
__IOM uint32_t STATUS; /*!< 0x0000000C Fault status */
|
||||
__IOM uint32_t DATA[4]; /*!< 0x00000010 Fault data */
|
||||
__IM uint32_t RESERVED1[8];
|
||||
__IM uint32_t PENDING0; /*!< 0x00000040 Fault pending 0 */
|
||||
__IM uint32_t PENDING1; /*!< 0x00000044 Fault pending 1 */
|
||||
__IM uint32_t PENDING2; /*!< 0x00000048 Fault pending 2 */
|
||||
__IM uint32_t RESERVED2;
|
||||
__IOM uint32_t MASK0; /*!< 0x00000050 Fault mask 0 */
|
||||
__IOM uint32_t MASK1; /*!< 0x00000054 Fault mask 1 */
|
||||
__IOM uint32_t MASK2; /*!< 0x00000058 Fault mask 2 */
|
||||
__IM uint32_t RESERVED3[25];
|
||||
__IOM uint32_t INTR; /*!< 0x000000C0 Interrupt */
|
||||
__IOM uint32_t INTR_SET; /*!< 0x000000C4 Interrupt set */
|
||||
__IOM uint32_t INTR_MASK; /*!< 0x000000C8 Interrupt mask */
|
||||
__IM uint32_t INTR_MASKED; /*!< 0x000000CC Interrupt masked */
|
||||
__IM uint32_t RESERVED4[12];
|
||||
} FAULT_STRUCT_V2_Type; /*!< Size = 256 (0x100) */
|
||||
|
||||
/**
|
||||
* \brief Fault structures (FAULT)
|
||||
*/
|
||||
typedef struct {
|
||||
FAULT_STRUCT_V2_Type STRUCT[4]; /*!< 0x00000000 Fault structure */
|
||||
} FAULT_V2_Type; /*!< Size = 1024 (0x400) */
|
||||
|
||||
|
||||
/* FAULT_STRUCT.CTL */
|
||||
#define FAULT_STRUCT_V2_CTL_TR_EN_Pos 0UL
|
||||
#define FAULT_STRUCT_V2_CTL_TR_EN_Msk 0x1UL
|
||||
#define FAULT_STRUCT_V2_CTL_OUT_EN_Pos 1UL
|
||||
#define FAULT_STRUCT_V2_CTL_OUT_EN_Msk 0x2UL
|
||||
#define FAULT_STRUCT_V2_CTL_RESET_REQ_EN_Pos 2UL
|
||||
#define FAULT_STRUCT_V2_CTL_RESET_REQ_EN_Msk 0x4UL
|
||||
/* FAULT_STRUCT.STATUS */
|
||||
#define FAULT_STRUCT_V2_STATUS_IDX_Pos 0UL
|
||||
#define FAULT_STRUCT_V2_STATUS_IDX_Msk 0x7FUL
|
||||
#define FAULT_STRUCT_V2_STATUS_VALID_Pos 31UL
|
||||
#define FAULT_STRUCT_V2_STATUS_VALID_Msk 0x80000000UL
|
||||
/* FAULT_STRUCT.DATA */
|
||||
#define FAULT_STRUCT_V2_DATA_DATA_Pos 0UL
|
||||
#define FAULT_STRUCT_V2_DATA_DATA_Msk 0xFFFFFFFFUL
|
||||
/* FAULT_STRUCT.PENDING0 */
|
||||
#define FAULT_STRUCT_V2_PENDING0_SOURCE_Pos 0UL
|
||||
#define FAULT_STRUCT_V2_PENDING0_SOURCE_Msk 0xFFFFFFFFUL
|
||||
/* FAULT_STRUCT.PENDING1 */
|
||||
#define FAULT_STRUCT_V2_PENDING1_SOURCE_Pos 0UL
|
||||
#define FAULT_STRUCT_V2_PENDING1_SOURCE_Msk 0xFFFFFFFFUL
|
||||
/* FAULT_STRUCT.PENDING2 */
|
||||
#define FAULT_STRUCT_V2_PENDING2_SOURCE_Pos 0UL
|
||||
#define FAULT_STRUCT_V2_PENDING2_SOURCE_Msk 0xFFFFFFFFUL
|
||||
/* FAULT_STRUCT.MASK0 */
|
||||
#define FAULT_STRUCT_V2_MASK0_SOURCE_Pos 0UL
|
||||
#define FAULT_STRUCT_V2_MASK0_SOURCE_Msk 0xFFFFFFFFUL
|
||||
/* FAULT_STRUCT.MASK1 */
|
||||
#define FAULT_STRUCT_V2_MASK1_SOURCE_Pos 0UL
|
||||
#define FAULT_STRUCT_V2_MASK1_SOURCE_Msk 0xFFFFFFFFUL
|
||||
/* FAULT_STRUCT.MASK2 */
|
||||
#define FAULT_STRUCT_V2_MASK2_SOURCE_Pos 0UL
|
||||
#define FAULT_STRUCT_V2_MASK2_SOURCE_Msk 0xFFFFFFFFUL
|
||||
/* FAULT_STRUCT.INTR */
|
||||
#define FAULT_STRUCT_V2_INTR_FAULT_Pos 0UL
|
||||
#define FAULT_STRUCT_V2_INTR_FAULT_Msk 0x1UL
|
||||
/* FAULT_STRUCT.INTR_SET */
|
||||
#define FAULT_STRUCT_V2_INTR_SET_FAULT_Pos 0UL
|
||||
#define FAULT_STRUCT_V2_INTR_SET_FAULT_Msk 0x1UL
|
||||
/* FAULT_STRUCT.INTR_MASK */
|
||||
#define FAULT_STRUCT_V2_INTR_MASK_FAULT_Pos 0UL
|
||||
#define FAULT_STRUCT_V2_INTR_MASK_FAULT_Msk 0x1UL
|
||||
/* FAULT_STRUCT.INTR_MASKED */
|
||||
#define FAULT_STRUCT_V2_INTR_MASKED_FAULT_Pos 0UL
|
||||
#define FAULT_STRUCT_V2_INTR_MASKED_FAULT_Msk 0x1UL
|
||||
|
||||
|
||||
#endif /* _CYIP_FAULT_V2_H_ */
|
||||
|
||||
|
||||
/* [] END OF FILE */
|
||||
|
|
@ -1,595 +0,0 @@
|
|||
/***************************************************************************//**
|
||||
* \file cyip_flashc.h
|
||||
*
|
||||
* \brief
|
||||
* FLASHC IP definitions
|
||||
*
|
||||
* \note
|
||||
* Generator version: 1.3.0.1146
|
||||
* Database revision: rev#1050929
|
||||
*
|
||||
********************************************************************************
|
||||
* \copyright
|
||||
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
|
||||
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _CYIP_FLASHC_H_
|
||||
#define _CYIP_FLASHC_H_
|
||||
|
||||
#include "cyip_headers.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* FLASHC
|
||||
*******************************************************************************/
|
||||
|
||||
#define FLASHC_FM_CTL_SECTION_SIZE 0x00001000UL
|
||||
#define FLASHC_SECTION_SIZE 0x00010000UL
|
||||
|
||||
/**
|
||||
* \brief Flash Macro Registers (FLASHC_FM_CTL)
|
||||
*/
|
||||
typedef struct {
|
||||
__IOM uint32_t FM_CTL; /*!< 0x00000000 Flash macro control */
|
||||
__IM uint32_t STATUS; /*!< 0x00000004 Status */
|
||||
__IOM uint32_t FM_ADDR; /*!< 0x00000008 Flash macro address */
|
||||
__IM uint32_t GEOMETRY; /*!< 0x0000000C Regular flash geometry */
|
||||
__IM uint32_t GEOMETRY_SUPERVISORY; /*!< 0x00000010 Supervisory flash geometry */
|
||||
__IOM uint32_t TIMER_CTL; /*!< 0x00000014 Timer control */
|
||||
__IOM uint32_t ANA_CTL0; /*!< 0x00000018 Analog control 0 */
|
||||
__IOM uint32_t ANA_CTL1; /*!< 0x0000001C Analog control 1 */
|
||||
__IM uint32_t GEOMETRY_GEN; /*!< 0x00000020 N/A, DNU */
|
||||
__IOM uint32_t TEST_CTL; /*!< 0x00000024 Test mode control */
|
||||
__IOM uint32_t WAIT_CTL; /*!< 0x00000028 Wiat State control */
|
||||
__IM uint32_t MONITOR_STATUS; /*!< 0x0000002C Monitor Status */
|
||||
__IOM uint32_t SCRATCH_CTL; /*!< 0x00000030 Scratch Control */
|
||||
__IOM uint32_t HV_CTL; /*!< 0x00000034 High voltage control */
|
||||
__OM uint32_t ACLK_CTL; /*!< 0x00000038 Aclk control */
|
||||
__IOM uint32_t INTR; /*!< 0x0000003C Interrupt */
|
||||
__IOM uint32_t INTR_SET; /*!< 0x00000040 Interrupt set */
|
||||
__IOM uint32_t INTR_MASK; /*!< 0x00000044 Interrupt mask */
|
||||
__IM uint32_t INTR_MASKED; /*!< 0x00000048 Interrupt masked */
|
||||
__OM uint32_t FM_HV_DATA_ALL; /*!< 0x0000004C Flash macro high Voltage page latches data (for all page
|
||||
latches) */
|
||||
__IOM uint32_t CAL_CTL0; /*!< 0x00000050 Cal control BG LO trim bits */
|
||||
__IOM uint32_t CAL_CTL1; /*!< 0x00000054 Cal control BG HI trim bits */
|
||||
__IOM uint32_t CAL_CTL2; /*!< 0x00000058 Cal control BG LO&HI ipref trim, ref sel, fm_active, turbo_ext */
|
||||
__IOM uint32_t CAL_CTL3; /*!< 0x0000005C Cal control osc trim bits, idac, sdac, itim, bdac. */
|
||||
__OM uint32_t BOOKMARK; /*!< 0x00000060 Bookmark register - keeps the current FW HV seq */
|
||||
__IM uint32_t RESERVED[7];
|
||||
__IOM uint32_t RED_CTL01; /*!< 0x00000080 Redundancy Control normal sectors 0,1 */
|
||||
__IOM uint32_t RED_CTL23; /*!< 0x00000084 Redundancy Controll normal sectors 2,3 */
|
||||
__IOM uint32_t RED_CTL45; /*!< 0x00000088 Redundancy Controll normal sectors 4,5 */
|
||||
__IOM uint32_t RED_CTL67; /*!< 0x0000008C Redundancy Controll normal sectors 6,7 */
|
||||
__IOM uint32_t RED_CTL_SM01; /*!< 0x00000090 Redundancy Controll special sectors 0,1 */
|
||||
__IM uint32_t RESERVED1[27];
|
||||
__IM uint32_t TM_CMPR[32]; /*!< 0x00000100 Do Not Use */
|
||||
__IM uint32_t RESERVED2[416];
|
||||
__IOM uint32_t FM_HV_DATA[256]; /*!< 0x00000800 Flash macro high Voltage page latches data */
|
||||
__IM uint32_t FM_MEM_DATA[256]; /*!< 0x00000C00 Flash macro memory sense amplifier and column decoder data */
|
||||
} FLASHC_FM_CTL_V1_Type; /*!< Size = 4096 (0x1000) */
|
||||
|
||||
/**
|
||||
* \brief Flash controller (FLASHC)
|
||||
*/
|
||||
typedef struct {
|
||||
__IOM uint32_t FLASH_CTL; /*!< 0x00000000 Control */
|
||||
__IOM uint32_t FLASH_PWR_CTL; /*!< 0x00000004 Flash power control */
|
||||
__IOM uint32_t FLASH_CMD; /*!< 0x00000008 Command */
|
||||
__IM uint32_t RESERVED[61];
|
||||
__IOM uint32_t BIST_CTL; /*!< 0x00000100 BIST control */
|
||||
__IOM uint32_t BIST_CMD; /*!< 0x00000104 BIST command */
|
||||
__IOM uint32_t BIST_ADDR_START; /*!< 0x00000108 BIST address start register */
|
||||
__IOM uint32_t BIST_DATA[8]; /*!< 0x0000010C BIST data register(s) */
|
||||
__IM uint32_t BIST_DATA_ACT[8]; /*!< 0x0000012C BIST data actual register(s) */
|
||||
__IM uint32_t BIST_DATA_EXP[8]; /*!< 0x0000014C BIST data expected register(s) */
|
||||
__IM uint32_t BIST_ADDR; /*!< 0x0000016C BIST address register */
|
||||
__IOM uint32_t BIST_STATUS; /*!< 0x00000170 BIST status register */
|
||||
__IM uint32_t RESERVED1[163];
|
||||
__IOM uint32_t CM0_CA_CTL0; /*!< 0x00000400 CM0+ cache control */
|
||||
__IOM uint32_t CM0_CA_CTL1; /*!< 0x00000404 CM0+ cache control */
|
||||
__IOM uint32_t CM0_CA_CTL2; /*!< 0x00000408 CM0+ cache control */
|
||||
__IOM uint32_t CM0_CA_CMD; /*!< 0x0000040C CM0+ cache command */
|
||||
__IM uint32_t RESERVED2[12];
|
||||
__IM uint32_t CM0_CA_STATUS0; /*!< 0x00000440 CM0+ cache status 0 */
|
||||
__IM uint32_t CM0_CA_STATUS1; /*!< 0x00000444 CM0+ cache status 1 */
|
||||
__IM uint32_t CM0_CA_STATUS2; /*!< 0x00000448 CM0+ cache status 2 */
|
||||
__IM uint32_t RESERVED3[13];
|
||||
__IOM uint32_t CM4_CA_CTL0; /*!< 0x00000480 CM4 cache control */
|
||||
__IOM uint32_t CM4_CA_CTL1; /*!< 0x00000484 CM4 cache control */
|
||||
__IOM uint32_t CM4_CA_CTL2; /*!< 0x00000488 CM4 cache control */
|
||||
__IOM uint32_t CM4_CA_CMD; /*!< 0x0000048C CM4 cache command */
|
||||
__IM uint32_t RESERVED4[12];
|
||||
__IM uint32_t CM4_CA_STATUS0; /*!< 0x000004C0 CM4 cache status 0 */
|
||||
__IM uint32_t CM4_CA_STATUS1; /*!< 0x000004C4 CM4 cache status 1 */
|
||||
__IM uint32_t CM4_CA_STATUS2; /*!< 0x000004C8 CM4 cache status 2 */
|
||||
__IM uint32_t RESERVED5[13];
|
||||
__IOM uint32_t CRYPTO_BUFF_CTL; /*!< 0x00000500 Cryptography buffer control */
|
||||
__IM uint32_t RESERVED6;
|
||||
__IOM uint32_t CRYPTO_BUFF_CMD; /*!< 0x00000508 Cryptography buffer command */
|
||||
__IM uint32_t RESERVED7[29];
|
||||
__IOM uint32_t DW0_BUFF_CTL; /*!< 0x00000580 Datawire 0 buffer control */
|
||||
__IM uint32_t RESERVED8;
|
||||
__IOM uint32_t DW0_BUFF_CMD; /*!< 0x00000588 Datawire 0 buffer command */
|
||||
__IM uint32_t RESERVED9[29];
|
||||
__IOM uint32_t DW1_BUFF_CTL; /*!< 0x00000600 Datawire 1 buffer control */
|
||||
__IM uint32_t RESERVED10;
|
||||
__IOM uint32_t DW1_BUFF_CMD; /*!< 0x00000608 Datawire 1 buffer command */
|
||||
__IM uint32_t RESERVED11[29];
|
||||
__IOM uint32_t DAP_BUFF_CTL; /*!< 0x00000680 Debug access port buffer control */
|
||||
__IM uint32_t RESERVED12;
|
||||
__IOM uint32_t DAP_BUFF_CMD; /*!< 0x00000688 Debug access port buffer command */
|
||||
__IM uint32_t RESERVED13[29];
|
||||
__IOM uint32_t EXT_MS0_BUFF_CTL; /*!< 0x00000700 External master 0 buffer control */
|
||||
__IM uint32_t RESERVED14;
|
||||
__IOM uint32_t EXT_MS0_BUFF_CMD; /*!< 0x00000708 External master 0 buffer command */
|
||||
__IM uint32_t RESERVED15[29];
|
||||
__IOM uint32_t EXT_MS1_BUFF_CTL; /*!< 0x00000780 External master 1 buffer control */
|
||||
__IM uint32_t RESERVED16;
|
||||
__IOM uint32_t EXT_MS1_BUFF_CMD; /*!< 0x00000788 External master 1 buffer command */
|
||||
__IM uint32_t RESERVED17[14877];
|
||||
FLASHC_FM_CTL_V1_Type FM_CTL; /*!< 0x0000F000 Flash Macro Registers */
|
||||
} FLASHC_V1_Type; /*!< Size = 65536 (0x10000) */
|
||||
|
||||
|
||||
/* FLASHC_FM_CTL.FM_CTL */
|
||||
#define FLASHC_FM_CTL_FM_CTL_FM_MODE_Pos 0UL
|
||||
#define FLASHC_FM_CTL_FM_CTL_FM_MODE_Msk 0xFUL
|
||||
#define FLASHC_FM_CTL_FM_CTL_FM_SEQ_Pos 8UL
|
||||
#define FLASHC_FM_CTL_FM_CTL_FM_SEQ_Msk 0x300UL
|
||||
#define FLASHC_FM_CTL_FM_CTL_DAA_MUX_SEL_Pos 16UL
|
||||
#define FLASHC_FM_CTL_FM_CTL_DAA_MUX_SEL_Msk 0x7F0000UL
|
||||
#define FLASHC_FM_CTL_FM_CTL_IF_SEL_Pos 24UL
|
||||
#define FLASHC_FM_CTL_FM_CTL_IF_SEL_Msk 0x1000000UL
|
||||
#define FLASHC_FM_CTL_FM_CTL_WR_EN_Pos 25UL
|
||||
#define FLASHC_FM_CTL_FM_CTL_WR_EN_Msk 0x2000000UL
|
||||
/* FLASHC_FM_CTL.STATUS */
|
||||
#define FLASHC_FM_CTL_STATUS_HV_TIMER_RUNNING_Pos 0UL
|
||||
#define FLASHC_FM_CTL_STATUS_HV_TIMER_RUNNING_Msk 0x1UL
|
||||
#define FLASHC_FM_CTL_STATUS_HV_REGS_ISOLATED_Pos 1UL
|
||||
#define FLASHC_FM_CTL_STATUS_HV_REGS_ISOLATED_Msk 0x2UL
|
||||
#define FLASHC_FM_CTL_STATUS_ILLEGAL_HVOP_Pos 2UL
|
||||
#define FLASHC_FM_CTL_STATUS_ILLEGAL_HVOP_Msk 0x4UL
|
||||
#define FLASHC_FM_CTL_STATUS_TURBO_N_Pos 3UL
|
||||
#define FLASHC_FM_CTL_STATUS_TURBO_N_Msk 0x8UL
|
||||
#define FLASHC_FM_CTL_STATUS_WR_EN_MON_Pos 4UL
|
||||
#define FLASHC_FM_CTL_STATUS_WR_EN_MON_Msk 0x10UL
|
||||
#define FLASHC_FM_CTL_STATUS_IF_SEL_MON_Pos 5UL
|
||||
#define FLASHC_FM_CTL_STATUS_IF_SEL_MON_Msk 0x20UL
|
||||
/* FLASHC_FM_CTL.FM_ADDR */
|
||||
#define FLASHC_FM_CTL_FM_ADDR_RA_Pos 0UL
|
||||
#define FLASHC_FM_CTL_FM_ADDR_RA_Msk 0xFFFFUL
|
||||
#define FLASHC_FM_CTL_FM_ADDR_BA_Pos 16UL
|
||||
#define FLASHC_FM_CTL_FM_ADDR_BA_Msk 0xFF0000UL
|
||||
#define FLASHC_FM_CTL_FM_ADDR_AXA_Pos 24UL
|
||||
#define FLASHC_FM_CTL_FM_ADDR_AXA_Msk 0x1000000UL
|
||||
/* FLASHC_FM_CTL.GEOMETRY */
|
||||
#define FLASHC_FM_CTL_GEOMETRY_WORD_SIZE_LOG2_Pos 0UL
|
||||
#define FLASHC_FM_CTL_GEOMETRY_WORD_SIZE_LOG2_Msk 0xFUL
|
||||
#define FLASHC_FM_CTL_GEOMETRY_PAGE_SIZE_LOG2_Pos 4UL
|
||||
#define FLASHC_FM_CTL_GEOMETRY_PAGE_SIZE_LOG2_Msk 0xF0UL
|
||||
#define FLASHC_FM_CTL_GEOMETRY_ROW_COUNT_Pos 8UL
|
||||
#define FLASHC_FM_CTL_GEOMETRY_ROW_COUNT_Msk 0xFFFF00UL
|
||||
#define FLASHC_FM_CTL_GEOMETRY_BANK_COUNT_Pos 24UL
|
||||
#define FLASHC_FM_CTL_GEOMETRY_BANK_COUNT_Msk 0xFF000000UL
|
||||
/* FLASHC_FM_CTL.GEOMETRY_SUPERVISORY */
|
||||
#define FLASHC_FM_CTL_GEOMETRY_SUPERVISORY_WORD_SIZE_LOG2_Pos 0UL
|
||||
#define FLASHC_FM_CTL_GEOMETRY_SUPERVISORY_WORD_SIZE_LOG2_Msk 0xFUL
|
||||
#define FLASHC_FM_CTL_GEOMETRY_SUPERVISORY_PAGE_SIZE_LOG2_Pos 4UL
|
||||
#define FLASHC_FM_CTL_GEOMETRY_SUPERVISORY_PAGE_SIZE_LOG2_Msk 0xF0UL
|
||||
#define FLASHC_FM_CTL_GEOMETRY_SUPERVISORY_ROW_COUNT_Pos 8UL
|
||||
#define FLASHC_FM_CTL_GEOMETRY_SUPERVISORY_ROW_COUNT_Msk 0xFFFF00UL
|
||||
#define FLASHC_FM_CTL_GEOMETRY_SUPERVISORY_BANK_COUNT_Pos 24UL
|
||||
#define FLASHC_FM_CTL_GEOMETRY_SUPERVISORY_BANK_COUNT_Msk 0xFF000000UL
|
||||
/* FLASHC_FM_CTL.TIMER_CTL */
|
||||
#define FLASHC_FM_CTL_TIMER_CTL_PERIOD_Pos 0UL
|
||||
#define FLASHC_FM_CTL_TIMER_CTL_PERIOD_Msk 0xFFFFUL
|
||||
#define FLASHC_FM_CTL_TIMER_CTL_SCALE_Pos 16UL
|
||||
#define FLASHC_FM_CTL_TIMER_CTL_SCALE_Msk 0x10000UL
|
||||
#define FLASHC_FM_CTL_TIMER_CTL_PUMP_CLOCK_SEL_Pos 24UL
|
||||
#define FLASHC_FM_CTL_TIMER_CTL_PUMP_CLOCK_SEL_Msk 0x1000000UL
|
||||
#define FLASHC_FM_CTL_TIMER_CTL_PRE_PROG_Pos 25UL
|
||||
#define FLASHC_FM_CTL_TIMER_CTL_PRE_PROG_Msk 0x2000000UL
|
||||
#define FLASHC_FM_CTL_TIMER_CTL_PRE_PROG_CSL_Pos 26UL
|
||||
#define FLASHC_FM_CTL_TIMER_CTL_PRE_PROG_CSL_Msk 0x4000000UL
|
||||
#define FLASHC_FM_CTL_TIMER_CTL_PUMP_EN_Pos 29UL
|
||||
#define FLASHC_FM_CTL_TIMER_CTL_PUMP_EN_Msk 0x20000000UL
|
||||
#define FLASHC_FM_CTL_TIMER_CTL_ACLK_EN_Pos 30UL
|
||||
#define FLASHC_FM_CTL_TIMER_CTL_ACLK_EN_Msk 0x40000000UL
|
||||
#define FLASHC_FM_CTL_TIMER_CTL_TIMER_EN_Pos 31UL
|
||||
#define FLASHC_FM_CTL_TIMER_CTL_TIMER_EN_Msk 0x80000000UL
|
||||
/* FLASHC_FM_CTL.ANA_CTL0 */
|
||||
#define FLASHC_FM_CTL_ANA_CTL0_CSLDAC_Pos 8UL
|
||||
#define FLASHC_FM_CTL_ANA_CTL0_CSLDAC_Msk 0x700UL
|
||||
#define FLASHC_FM_CTL_ANA_CTL0_VCC_SEL_Pos 24UL
|
||||
#define FLASHC_FM_CTL_ANA_CTL0_VCC_SEL_Msk 0x1000000UL
|
||||
#define FLASHC_FM_CTL_ANA_CTL0_FLIP_AMUXBUS_AB_Pos 27UL
|
||||
#define FLASHC_FM_CTL_ANA_CTL0_FLIP_AMUXBUS_AB_Msk 0x8000000UL
|
||||
/* FLASHC_FM_CTL.ANA_CTL1 */
|
||||
#define FLASHC_FM_CTL_ANA_CTL1_MDAC_Pos 0UL
|
||||
#define FLASHC_FM_CTL_ANA_CTL1_MDAC_Msk 0xFFUL
|
||||
#define FLASHC_FM_CTL_ANA_CTL1_PDAC_Pos 16UL
|
||||
#define FLASHC_FM_CTL_ANA_CTL1_PDAC_Msk 0xF0000UL
|
||||
#define FLASHC_FM_CTL_ANA_CTL1_NDAC_Pos 24UL
|
||||
#define FLASHC_FM_CTL_ANA_CTL1_NDAC_Msk 0xF000000UL
|
||||
#define FLASHC_FM_CTL_ANA_CTL1_VPROT_OVERRIDE_Pos 28UL
|
||||
#define FLASHC_FM_CTL_ANA_CTL1_VPROT_OVERRIDE_Msk 0x10000000UL
|
||||
#define FLASHC_FM_CTL_ANA_CTL1_R_GRANT_CTL_Pos 29UL
|
||||
#define FLASHC_FM_CTL_ANA_CTL1_R_GRANT_CTL_Msk 0x20000000UL
|
||||
#define FLASHC_FM_CTL_ANA_CTL1_RST_SFT_HVPL_Pos 30UL
|
||||
#define FLASHC_FM_CTL_ANA_CTL1_RST_SFT_HVPL_Msk 0x40000000UL
|
||||
/* FLASHC_FM_CTL.GEOMETRY_GEN */
|
||||
#define FLASHC_FM_CTL_GEOMETRY_GEN_DNU_0X20_1_Pos 1UL
|
||||
#define FLASHC_FM_CTL_GEOMETRY_GEN_DNU_0X20_1_Msk 0x2UL
|
||||
#define FLASHC_FM_CTL_GEOMETRY_GEN_DNU_0X20_2_Pos 2UL
|
||||
#define FLASHC_FM_CTL_GEOMETRY_GEN_DNU_0X20_2_Msk 0x4UL
|
||||
#define FLASHC_FM_CTL_GEOMETRY_GEN_DNU_0X20_3_Pos 3UL
|
||||
#define FLASHC_FM_CTL_GEOMETRY_GEN_DNU_0X20_3_Msk 0x8UL
|
||||
/* FLASHC_FM_CTL.TEST_CTL */
|
||||
#define FLASHC_FM_CTL_TEST_CTL_TEST_MODE_Pos 0UL
|
||||
#define FLASHC_FM_CTL_TEST_CTL_TEST_MODE_Msk 0x1FUL
|
||||
#define FLASHC_FM_CTL_TEST_CTL_PN_CTL_Pos 8UL
|
||||
#define FLASHC_FM_CTL_TEST_CTL_PN_CTL_Msk 0x100UL
|
||||
#define FLASHC_FM_CTL_TEST_CTL_TM_PE_Pos 9UL
|
||||
#define FLASHC_FM_CTL_TEST_CTL_TM_PE_Msk 0x200UL
|
||||
#define FLASHC_FM_CTL_TEST_CTL_TM_DISPOS_Pos 10UL
|
||||
#define FLASHC_FM_CTL_TEST_CTL_TM_DISPOS_Msk 0x400UL
|
||||
#define FLASHC_FM_CTL_TEST_CTL_TM_DISNEG_Pos 11UL
|
||||
#define FLASHC_FM_CTL_TEST_CTL_TM_DISNEG_Msk 0x800UL
|
||||
#define FLASHC_FM_CTL_TEST_CTL_EN_CLK_MON_Pos 16UL
|
||||
#define FLASHC_FM_CTL_TEST_CTL_EN_CLK_MON_Msk 0x10000UL
|
||||
#define FLASHC_FM_CTL_TEST_CTL_CSL_DEBUG_Pos 17UL
|
||||
#define FLASHC_FM_CTL_TEST_CTL_CSL_DEBUG_Msk 0x20000UL
|
||||
#define FLASHC_FM_CTL_TEST_CTL_ENABLE_OSC_Pos 18UL
|
||||
#define FLASHC_FM_CTL_TEST_CTL_ENABLE_OSC_Msk 0x40000UL
|
||||
#define FLASHC_FM_CTL_TEST_CTL_UNSCRAMBLE_WA_Pos 31UL
|
||||
#define FLASHC_FM_CTL_TEST_CTL_UNSCRAMBLE_WA_Msk 0x80000000UL
|
||||
/* FLASHC_FM_CTL.WAIT_CTL */
|
||||
#define FLASHC_FM_CTL_WAIT_CTL_WAIT_FM_MEM_RD_Pos 0UL
|
||||
#define FLASHC_FM_CTL_WAIT_CTL_WAIT_FM_MEM_RD_Msk 0xFUL
|
||||
#define FLASHC_FM_CTL_WAIT_CTL_WAIT_FM_HV_RD_Pos 8UL
|
||||
#define FLASHC_FM_CTL_WAIT_CTL_WAIT_FM_HV_RD_Msk 0xF00UL
|
||||
#define FLASHC_FM_CTL_WAIT_CTL_WAIT_FM_HV_WR_Pos 16UL
|
||||
#define FLASHC_FM_CTL_WAIT_CTL_WAIT_FM_HV_WR_Msk 0x70000UL
|
||||
/* FLASHC_FM_CTL.MONITOR_STATUS */
|
||||
#define FLASHC_FM_CTL_MONITOR_STATUS_POS_PUMP_VLO_Pos 1UL
|
||||
#define FLASHC_FM_CTL_MONITOR_STATUS_POS_PUMP_VLO_Msk 0x2UL
|
||||
#define FLASHC_FM_CTL_MONITOR_STATUS_NEG_PUMP_VHI_Pos 2UL
|
||||
#define FLASHC_FM_CTL_MONITOR_STATUS_NEG_PUMP_VHI_Msk 0x4UL
|
||||
/* FLASHC_FM_CTL.SCRATCH_CTL */
|
||||
#define FLASHC_FM_CTL_SCRATCH_CTL_DUMMY32_Pos 0UL
|
||||
#define FLASHC_FM_CTL_SCRATCH_CTL_DUMMY32_Msk 0xFFFFFFFFUL
|
||||
/* FLASHC_FM_CTL.HV_CTL */
|
||||
#define FLASHC_FM_CTL_HV_CTL_TIMER_CLOCK_FREQ_Pos 0UL
|
||||
#define FLASHC_FM_CTL_HV_CTL_TIMER_CLOCK_FREQ_Msk 0xFFUL
|
||||
/* FLASHC_FM_CTL.ACLK_CTL */
|
||||
#define FLASHC_FM_CTL_ACLK_CTL_ACLK_GEN_Pos 0UL
|
||||
#define FLASHC_FM_CTL_ACLK_CTL_ACLK_GEN_Msk 0x1UL
|
||||
/* FLASHC_FM_CTL.INTR */
|
||||
#define FLASHC_FM_CTL_INTR_TIMER_EXPIRED_Pos 0UL
|
||||
#define FLASHC_FM_CTL_INTR_TIMER_EXPIRED_Msk 0x1UL
|
||||
/* FLASHC_FM_CTL.INTR_SET */
|
||||
#define FLASHC_FM_CTL_INTR_SET_TIMER_EXPIRED_Pos 0UL
|
||||
#define FLASHC_FM_CTL_INTR_SET_TIMER_EXPIRED_Msk 0x1UL
|
||||
/* FLASHC_FM_CTL.INTR_MASK */
|
||||
#define FLASHC_FM_CTL_INTR_MASK_TIMER_EXPIRED_Pos 0UL
|
||||
#define FLASHC_FM_CTL_INTR_MASK_TIMER_EXPIRED_Msk 0x1UL
|
||||
/* FLASHC_FM_CTL.INTR_MASKED */
|
||||
#define FLASHC_FM_CTL_INTR_MASKED_TIMER_EXPIRED_Pos 0UL
|
||||
#define FLASHC_FM_CTL_INTR_MASKED_TIMER_EXPIRED_Msk 0x1UL
|
||||
/* FLASHC_FM_CTL.FM_HV_DATA_ALL */
|
||||
#define FLASHC_FM_CTL_FM_HV_DATA_ALL_DATA32_Pos 0UL
|
||||
#define FLASHC_FM_CTL_FM_HV_DATA_ALL_DATA32_Msk 0xFFFFFFFFUL
|
||||
/* FLASHC_FM_CTL.CAL_CTL0 */
|
||||
#define FLASHC_FM_CTL_CAL_CTL0_VCT_TRIM_LO_HV_Pos 0UL
|
||||
#define FLASHC_FM_CTL_CAL_CTL0_VCT_TRIM_LO_HV_Msk 0x1FUL
|
||||
#define FLASHC_FM_CTL_CAL_CTL0_CDAC_LO_HV_Pos 5UL
|
||||
#define FLASHC_FM_CTL_CAL_CTL0_CDAC_LO_HV_Msk 0xE0UL
|
||||
#define FLASHC_FM_CTL_CAL_CTL0_VBG_TRIM_LO_HV_Pos 8UL
|
||||
#define FLASHC_FM_CTL_CAL_CTL0_VBG_TRIM_LO_HV_Msk 0x1F00UL
|
||||
#define FLASHC_FM_CTL_CAL_CTL0_VBG_TC_TRIM_LO_HV_Pos 13UL
|
||||
#define FLASHC_FM_CTL_CAL_CTL0_VBG_TC_TRIM_LO_HV_Msk 0xE000UL
|
||||
#define FLASHC_FM_CTL_CAL_CTL0_IPREF_TRIM_LO_HV_Pos 16UL
|
||||
#define FLASHC_FM_CTL_CAL_CTL0_IPREF_TRIM_LO_HV_Msk 0xF0000UL
|
||||
/* FLASHC_FM_CTL.CAL_CTL1 */
|
||||
#define FLASHC_FM_CTL_CAL_CTL1_VCT_TRIM_HI_HV_Pos 0UL
|
||||
#define FLASHC_FM_CTL_CAL_CTL1_VCT_TRIM_HI_HV_Msk 0x1FUL
|
||||
#define FLASHC_FM_CTL_CAL_CTL1_CDAC_HI_HV_Pos 5UL
|
||||
#define FLASHC_FM_CTL_CAL_CTL1_CDAC_HI_HV_Msk 0xE0UL
|
||||
#define FLASHC_FM_CTL_CAL_CTL1_VBG_TRIM_HI_HV_Pos 8UL
|
||||
#define FLASHC_FM_CTL_CAL_CTL1_VBG_TRIM_HI_HV_Msk 0x1F00UL
|
||||
#define FLASHC_FM_CTL_CAL_CTL1_VBG_TC_TRIM_HI_HV_Pos 13UL
|
||||
#define FLASHC_FM_CTL_CAL_CTL1_VBG_TC_TRIM_HI_HV_Msk 0xE000UL
|
||||
#define FLASHC_FM_CTL_CAL_CTL1_IPREF_TRIM_HI_HV_Pos 16UL
|
||||
#define FLASHC_FM_CTL_CAL_CTL1_IPREF_TRIM_HI_HV_Msk 0xF0000UL
|
||||
/* FLASHC_FM_CTL.CAL_CTL2 */
|
||||
#define FLASHC_FM_CTL_CAL_CTL2_ICREF_TRIM_LO_HV_Pos 0UL
|
||||
#define FLASHC_FM_CTL_CAL_CTL2_ICREF_TRIM_LO_HV_Msk 0x1FUL
|
||||
#define FLASHC_FM_CTL_CAL_CTL2_ICREF_TC_TRIM_LO_HV_Pos 5UL
|
||||
#define FLASHC_FM_CTL_CAL_CTL2_ICREF_TC_TRIM_LO_HV_Msk 0xE0UL
|
||||
#define FLASHC_FM_CTL_CAL_CTL2_ICREF_TRIM_HI_HV_Pos 8UL
|
||||
#define FLASHC_FM_CTL_CAL_CTL2_ICREF_TRIM_HI_HV_Msk 0x1F00UL
|
||||
#define FLASHC_FM_CTL_CAL_CTL2_ICREF_TC_TRIM_HI_HV_Pos 13UL
|
||||
#define FLASHC_FM_CTL_CAL_CTL2_ICREF_TC_TRIM_HI_HV_Msk 0xE000UL
|
||||
#define FLASHC_FM_CTL_CAL_CTL2_VREF_SEL_HV_Pos 16UL
|
||||
#define FLASHC_FM_CTL_CAL_CTL2_VREF_SEL_HV_Msk 0x10000UL
|
||||
#define FLASHC_FM_CTL_CAL_CTL2_IREF_SEL_HV_Pos 17UL
|
||||
#define FLASHC_FM_CTL_CAL_CTL2_IREF_SEL_HV_Msk 0x20000UL
|
||||
#define FLASHC_FM_CTL_CAL_CTL2_FM_ACTIVE_HV_Pos 18UL
|
||||
#define FLASHC_FM_CTL_CAL_CTL2_FM_ACTIVE_HV_Msk 0x40000UL
|
||||
#define FLASHC_FM_CTL_CAL_CTL2_TURBO_EXT_HV_Pos 19UL
|
||||
#define FLASHC_FM_CTL_CAL_CTL2_TURBO_EXT_HV_Msk 0x80000UL
|
||||
/* FLASHC_FM_CTL.CAL_CTL3 */
|
||||
#define FLASHC_FM_CTL_CAL_CTL3_OSC_TRIM_HV_Pos 0UL
|
||||
#define FLASHC_FM_CTL_CAL_CTL3_OSC_TRIM_HV_Msk 0xFUL
|
||||
#define FLASHC_FM_CTL_CAL_CTL3_OSC_RANGE_TRIM_HV_Pos 4UL
|
||||
#define FLASHC_FM_CTL_CAL_CTL3_OSC_RANGE_TRIM_HV_Msk 0x10UL
|
||||
#define FLASHC_FM_CTL_CAL_CTL3_IDAC_HV_Pos 5UL
|
||||
#define FLASHC_FM_CTL_CAL_CTL3_IDAC_HV_Msk 0x1E0UL
|
||||
#define FLASHC_FM_CTL_CAL_CTL3_SDAC_HV_Pos 9UL
|
||||
#define FLASHC_FM_CTL_CAL_CTL3_SDAC_HV_Msk 0x600UL
|
||||
#define FLASHC_FM_CTL_CAL_CTL3_ITIM_HV_Pos 11UL
|
||||
#define FLASHC_FM_CTL_CAL_CTL3_ITIM_HV_Msk 0x7800UL
|
||||
#define FLASHC_FM_CTL_CAL_CTL3_VDDHI_HV_Pos 15UL
|
||||
#define FLASHC_FM_CTL_CAL_CTL3_VDDHI_HV_Msk 0x8000UL
|
||||
#define FLASHC_FM_CTL_CAL_CTL3_TURBO_PULSEW_HV_Pos 16UL
|
||||
#define FLASHC_FM_CTL_CAL_CTL3_TURBO_PULSEW_HV_Msk 0x30000UL
|
||||
#define FLASHC_FM_CTL_CAL_CTL3_BGLO_EN_HV_Pos 18UL
|
||||
#define FLASHC_FM_CTL_CAL_CTL3_BGLO_EN_HV_Msk 0x40000UL
|
||||
#define FLASHC_FM_CTL_CAL_CTL3_BGHI_EN_HV_Pos 19UL
|
||||
#define FLASHC_FM_CTL_CAL_CTL3_BGHI_EN_HV_Msk 0x80000UL
|
||||
/* FLASHC_FM_CTL.BOOKMARK */
|
||||
#define FLASHC_FM_CTL_BOOKMARK_BOOKMARK_Pos 0UL
|
||||
#define FLASHC_FM_CTL_BOOKMARK_BOOKMARK_Msk 0xFFFFFFFFUL
|
||||
/* FLASHC_FM_CTL.RED_CTL01 */
|
||||
#define FLASHC_FM_CTL_RED_CTL01_RED_ADDR_0_Pos 0UL
|
||||
#define FLASHC_FM_CTL_RED_CTL01_RED_ADDR_0_Msk 0xFFUL
|
||||
#define FLASHC_FM_CTL_RED_CTL01_RED_EN_0_Pos 8UL
|
||||
#define FLASHC_FM_CTL_RED_CTL01_RED_EN_0_Msk 0x100UL
|
||||
#define FLASHC_FM_CTL_RED_CTL01_RED_ADDR_1_Pos 16UL
|
||||
#define FLASHC_FM_CTL_RED_CTL01_RED_ADDR_1_Msk 0xFF0000UL
|
||||
#define FLASHC_FM_CTL_RED_CTL01_RED_EN_1_Pos 24UL
|
||||
#define FLASHC_FM_CTL_RED_CTL01_RED_EN_1_Msk 0x1000000UL
|
||||
/* FLASHC_FM_CTL.RED_CTL23 */
|
||||
#define FLASHC_FM_CTL_RED_CTL23_RED_ADDR_2_Pos 0UL
|
||||
#define FLASHC_FM_CTL_RED_CTL23_RED_ADDR_2_Msk 0xFFUL
|
||||
#define FLASHC_FM_CTL_RED_CTL23_RED_EN_2_Pos 8UL
|
||||
#define FLASHC_FM_CTL_RED_CTL23_RED_EN_2_Msk 0x100UL
|
||||
#define FLASHC_FM_CTL_RED_CTL23_RED_ADDR_3_Pos 16UL
|
||||
#define FLASHC_FM_CTL_RED_CTL23_RED_ADDR_3_Msk 0xFF0000UL
|
||||
#define FLASHC_FM_CTL_RED_CTL23_RED_EN_3_Pos 24UL
|
||||
#define FLASHC_FM_CTL_RED_CTL23_RED_EN_3_Msk 0x1000000UL
|
||||
/* FLASHC_FM_CTL.RED_CTL45 */
|
||||
#define FLASHC_FM_CTL_RED_CTL45_DNU_45_1_Pos 0UL
|
||||
#define FLASHC_FM_CTL_RED_CTL45_DNU_45_1_Msk 0x1UL
|
||||
#define FLASHC_FM_CTL_RED_CTL45_REG_ACT_HV_Pos 1UL
|
||||
#define FLASHC_FM_CTL_RED_CTL45_REG_ACT_HV_Msk 0x2UL
|
||||
#define FLASHC_FM_CTL_RED_CTL45_DNU_45_3_Pos 2UL
|
||||
#define FLASHC_FM_CTL_RED_CTL45_DNU_45_3_Msk 0x4UL
|
||||
#define FLASHC_FM_CTL_RED_CTL45_FDIV_TRIM_HV_0_Pos 3UL
|
||||
#define FLASHC_FM_CTL_RED_CTL45_FDIV_TRIM_HV_0_Msk 0x8UL
|
||||
#define FLASHC_FM_CTL_RED_CTL45_DNU_45_5_Pos 4UL
|
||||
#define FLASHC_FM_CTL_RED_CTL45_DNU_45_5_Msk 0x10UL
|
||||
#define FLASHC_FM_CTL_RED_CTL45_FDIV_TRIM_HV_1_Pos 5UL
|
||||
#define FLASHC_FM_CTL_RED_CTL45_FDIV_TRIM_HV_1_Msk 0x20UL
|
||||
#define FLASHC_FM_CTL_RED_CTL45_DNU_45_6_Pos 6UL
|
||||
#define FLASHC_FM_CTL_RED_CTL45_DNU_45_6_Msk 0x40UL
|
||||
#define FLASHC_FM_CTL_RED_CTL45_VLIM_TRIM_HV_0_Pos 7UL
|
||||
#define FLASHC_FM_CTL_RED_CTL45_VLIM_TRIM_HV_0_Msk 0x80UL
|
||||
#define FLASHC_FM_CTL_RED_CTL45_DNU_45_8_Pos 8UL
|
||||
#define FLASHC_FM_CTL_RED_CTL45_DNU_45_8_Msk 0x100UL
|
||||
#define FLASHC_FM_CTL_RED_CTL45_DNU_45_23_16_Pos 16UL
|
||||
#define FLASHC_FM_CTL_RED_CTL45_DNU_45_23_16_Msk 0xFF0000UL
|
||||
/* FLASHC_FM_CTL.RED_CTL67 */
|
||||
#define FLASHC_FM_CTL_RED_CTL67_VLIM_TRIM_HV_1_Pos 0UL
|
||||
#define FLASHC_FM_CTL_RED_CTL67_VLIM_TRIM_HV_1_Msk 0x1UL
|
||||
#define FLASHC_FM_CTL_RED_CTL67_DNU_67_1_Pos 1UL
|
||||
#define FLASHC_FM_CTL_RED_CTL67_DNU_67_1_Msk 0x2UL
|
||||
#define FLASHC_FM_CTL_RED_CTL67_VPROT_ACT_HV_Pos 2UL
|
||||
#define FLASHC_FM_CTL_RED_CTL67_VPROT_ACT_HV_Msk 0x4UL
|
||||
#define FLASHC_FM_CTL_RED_CTL67_DNU_67_3_Pos 3UL
|
||||
#define FLASHC_FM_CTL_RED_CTL67_DNU_67_3_Msk 0x8UL
|
||||
#define FLASHC_FM_CTL_RED_CTL67_IPREF_TC_HV_Pos 4UL
|
||||
#define FLASHC_FM_CTL_RED_CTL67_IPREF_TC_HV_Msk 0x10UL
|
||||
#define FLASHC_FM_CTL_RED_CTL67_DNU_67_5_Pos 5UL
|
||||
#define FLASHC_FM_CTL_RED_CTL67_DNU_67_5_Msk 0x20UL
|
||||
#define FLASHC_FM_CTL_RED_CTL67_IPREF_TRIMA_HI_HV_Pos 6UL
|
||||
#define FLASHC_FM_CTL_RED_CTL67_IPREF_TRIMA_HI_HV_Msk 0x40UL
|
||||
#define FLASHC_FM_CTL_RED_CTL67_DNU_67_7_Pos 7UL
|
||||
#define FLASHC_FM_CTL_RED_CTL67_DNU_67_7_Msk 0x80UL
|
||||
#define FLASHC_FM_CTL_RED_CTL67_IPREF_TRIMA_LO_HV_Pos 8UL
|
||||
#define FLASHC_FM_CTL_RED_CTL67_IPREF_TRIMA_LO_HV_Msk 0x100UL
|
||||
#define FLASHC_FM_CTL_RED_CTL67_DNU_67_23_16_Pos 16UL
|
||||
#define FLASHC_FM_CTL_RED_CTL67_DNU_67_23_16_Msk 0xFF0000UL
|
||||
/* FLASHC_FM_CTL.RED_CTL_SM01 */
|
||||
#define FLASHC_FM_CTL_RED_CTL_SM01_RED_ADDR_SM0_Pos 0UL
|
||||
#define FLASHC_FM_CTL_RED_CTL_SM01_RED_ADDR_SM0_Msk 0xFFUL
|
||||
#define FLASHC_FM_CTL_RED_CTL_SM01_RED_EN_SM0_Pos 8UL
|
||||
#define FLASHC_FM_CTL_RED_CTL_SM01_RED_EN_SM0_Msk 0x100UL
|
||||
#define FLASHC_FM_CTL_RED_CTL_SM01_RED_ADDR_SM1_Pos 16UL
|
||||
#define FLASHC_FM_CTL_RED_CTL_SM01_RED_ADDR_SM1_Msk 0xFF0000UL
|
||||
#define FLASHC_FM_CTL_RED_CTL_SM01_RED_EN_SM1_Pos 24UL
|
||||
#define FLASHC_FM_CTL_RED_CTL_SM01_RED_EN_SM1_Msk 0x1000000UL
|
||||
#define FLASHC_FM_CTL_RED_CTL_SM01_TRKD_Pos 30UL
|
||||
#define FLASHC_FM_CTL_RED_CTL_SM01_TRKD_Msk 0x40000000UL
|
||||
#define FLASHC_FM_CTL_RED_CTL_SM01_R_GRANT_EN_Pos 31UL
|
||||
#define FLASHC_FM_CTL_RED_CTL_SM01_R_GRANT_EN_Msk 0x80000000UL
|
||||
/* FLASHC_FM_CTL.TM_CMPR */
|
||||
#define FLASHC_FM_CTL_TM_CMPR_DATA_COMP_RESULT_Pos 0UL
|
||||
#define FLASHC_FM_CTL_TM_CMPR_DATA_COMP_RESULT_Msk 0x1UL
|
||||
/* FLASHC_FM_CTL.FM_HV_DATA */
|
||||
#define FLASHC_FM_CTL_FM_HV_DATA_DATA32_Pos 0UL
|
||||
#define FLASHC_FM_CTL_FM_HV_DATA_DATA32_Msk 0xFFFFFFFFUL
|
||||
/* FLASHC_FM_CTL.FM_MEM_DATA */
|
||||
#define FLASHC_FM_CTL_FM_MEM_DATA_DATA32_Pos 0UL
|
||||
#define FLASHC_FM_CTL_FM_MEM_DATA_DATA32_Msk 0xFFFFFFFFUL
|
||||
|
||||
|
||||
/* FLASHC.FLASH_CTL */
|
||||
#define FLASHC_FLASH_CTL_MAIN_WS_Pos 0UL
|
||||
#define FLASHC_FLASH_CTL_MAIN_WS_Msk 0xFUL
|
||||
#define FLASHC_FLASH_CTL_REMAP_Pos 8UL
|
||||
#define FLASHC_FLASH_CTL_REMAP_Msk 0x100UL
|
||||
/* FLASHC.FLASH_PWR_CTL */
|
||||
#define FLASHC_FLASH_PWR_CTL_ENABLE_Pos 0UL
|
||||
#define FLASHC_FLASH_PWR_CTL_ENABLE_Msk 0x1UL
|
||||
#define FLASHC_FLASH_PWR_CTL_ENABLE_HV_Pos 1UL
|
||||
#define FLASHC_FLASH_PWR_CTL_ENABLE_HV_Msk 0x2UL
|
||||
/* FLASHC.FLASH_CMD */
|
||||
#define FLASHC_FLASH_CMD_INV_Pos 0UL
|
||||
#define FLASHC_FLASH_CMD_INV_Msk 0x1UL
|
||||
/* FLASHC.BIST_CTL */
|
||||
#define FLASHC_BIST_CTL_OPCODE_Pos 0UL
|
||||
#define FLASHC_BIST_CTL_OPCODE_Msk 0x3UL
|
||||
#define FLASHC_BIST_CTL_UP_Pos 2UL
|
||||
#define FLASHC_BIST_CTL_UP_Msk 0x4UL
|
||||
#define FLASHC_BIST_CTL_ROW_FIRST_Pos 3UL
|
||||
#define FLASHC_BIST_CTL_ROW_FIRST_Msk 0x8UL
|
||||
#define FLASHC_BIST_CTL_ADDR_START_ENABLED_Pos 4UL
|
||||
#define FLASHC_BIST_CTL_ADDR_START_ENABLED_Msk 0x10UL
|
||||
#define FLASHC_BIST_CTL_ADDR_COMPLIMENT_ENABLED_Pos 5UL
|
||||
#define FLASHC_BIST_CTL_ADDR_COMPLIMENT_ENABLED_Msk 0x20UL
|
||||
#define FLASHC_BIST_CTL_INCR_DECR_BOTH_Pos 6UL
|
||||
#define FLASHC_BIST_CTL_INCR_DECR_BOTH_Msk 0x40UL
|
||||
#define FLASHC_BIST_CTL_STOP_ON_ERROR_Pos 7UL
|
||||
#define FLASHC_BIST_CTL_STOP_ON_ERROR_Msk 0x80UL
|
||||
/* FLASHC.BIST_CMD */
|
||||
#define FLASHC_BIST_CMD_START_Pos 0UL
|
||||
#define FLASHC_BIST_CMD_START_Msk 0x1UL
|
||||
/* FLASHC.BIST_ADDR_START */
|
||||
#define FLASHC_BIST_ADDR_START_COL_ADDR_START_Pos 0UL
|
||||
#define FLASHC_BIST_ADDR_START_COL_ADDR_START_Msk 0xFFFFUL
|
||||
#define FLASHC_BIST_ADDR_START_ROW_ADDR_START_Pos 16UL
|
||||
#define FLASHC_BIST_ADDR_START_ROW_ADDR_START_Msk 0xFFFF0000UL
|
||||
/* FLASHC.BIST_DATA */
|
||||
#define FLASHC_BIST_DATA_DATA_Pos 0UL
|
||||
#define FLASHC_BIST_DATA_DATA_Msk 0xFFFFFFFFUL
|
||||
/* FLASHC.BIST_DATA_ACT */
|
||||
#define FLASHC_BIST_DATA_ACT_DATA_Pos 0UL
|
||||
#define FLASHC_BIST_DATA_ACT_DATA_Msk 0xFFFFFFFFUL
|
||||
/* FLASHC.BIST_DATA_EXP */
|
||||
#define FLASHC_BIST_DATA_EXP_DATA_Pos 0UL
|
||||
#define FLASHC_BIST_DATA_EXP_DATA_Msk 0xFFFFFFFFUL
|
||||
/* FLASHC.BIST_ADDR */
|
||||
#define FLASHC_BIST_ADDR_COL_ADDR_Pos 0UL
|
||||
#define FLASHC_BIST_ADDR_COL_ADDR_Msk 0xFFFFUL
|
||||
#define FLASHC_BIST_ADDR_ROW_ADDR_Pos 16UL
|
||||
#define FLASHC_BIST_ADDR_ROW_ADDR_Msk 0xFFFF0000UL
|
||||
/* FLASHC.BIST_STATUS */
|
||||
#define FLASHC_BIST_STATUS_FAIL_Pos 0UL
|
||||
#define FLASHC_BIST_STATUS_FAIL_Msk 0x1UL
|
||||
/* FLASHC.CM0_CA_CTL0 */
|
||||
#define FLASHC_CM0_CA_CTL0_WAY_Pos 16UL
|
||||
#define FLASHC_CM0_CA_CTL0_WAY_Msk 0x30000UL
|
||||
#define FLASHC_CM0_CA_CTL0_SET_ADDR_Pos 24UL
|
||||
#define FLASHC_CM0_CA_CTL0_SET_ADDR_Msk 0x7000000UL
|
||||
#define FLASHC_CM0_CA_CTL0_PREF_EN_Pos 30UL
|
||||
#define FLASHC_CM0_CA_CTL0_PREF_EN_Msk 0x40000000UL
|
||||
#define FLASHC_CM0_CA_CTL0_ENABLED_Pos 31UL
|
||||
#define FLASHC_CM0_CA_CTL0_ENABLED_Msk 0x80000000UL
|
||||
/* FLASHC.CM0_CA_CTL1 */
|
||||
#define FLASHC_CM0_CA_CTL1_PWR_MODE_Pos 0UL
|
||||
#define FLASHC_CM0_CA_CTL1_PWR_MODE_Msk 0x3UL
|
||||
#define FLASHC_CM0_CA_CTL1_VECTKEYSTAT_Pos 16UL
|
||||
#define FLASHC_CM0_CA_CTL1_VECTKEYSTAT_Msk 0xFFFF0000UL
|
||||
/* FLASHC.CM0_CA_CTL2 */
|
||||
#define FLASHC_CM0_CA_CTL2_PWRUP_DELAY_Pos 0UL
|
||||
#define FLASHC_CM0_CA_CTL2_PWRUP_DELAY_Msk 0x3FFUL
|
||||
/* FLASHC.CM0_CA_CMD */
|
||||
#define FLASHC_CM0_CA_CMD_INV_Pos 0UL
|
||||
#define FLASHC_CM0_CA_CMD_INV_Msk 0x1UL
|
||||
/* FLASHC.CM0_CA_STATUS0 */
|
||||
#define FLASHC_CM0_CA_STATUS0_VALID16_Pos 0UL
|
||||
#define FLASHC_CM0_CA_STATUS0_VALID16_Msk 0xFFFFUL
|
||||
/* FLASHC.CM0_CA_STATUS1 */
|
||||
#define FLASHC_CM0_CA_STATUS1_TAG_Pos 0UL
|
||||
#define FLASHC_CM0_CA_STATUS1_TAG_Msk 0xFFFFFFFFUL
|
||||
/* FLASHC.CM0_CA_STATUS2 */
|
||||
#define FLASHC_CM0_CA_STATUS2_LRU_Pos 0UL
|
||||
#define FLASHC_CM0_CA_STATUS2_LRU_Msk 0x3FUL
|
||||
/* FLASHC.CM4_CA_CTL0 */
|
||||
#define FLASHC_CM4_CA_CTL0_WAY_Pos 16UL
|
||||
#define FLASHC_CM4_CA_CTL0_WAY_Msk 0x30000UL
|
||||
#define FLASHC_CM4_CA_CTL0_SET_ADDR_Pos 24UL
|
||||
#define FLASHC_CM4_CA_CTL0_SET_ADDR_Msk 0x7000000UL
|
||||
#define FLASHC_CM4_CA_CTL0_PREF_EN_Pos 30UL
|
||||
#define FLASHC_CM4_CA_CTL0_PREF_EN_Msk 0x40000000UL
|
||||
#define FLASHC_CM4_CA_CTL0_ENABLED_Pos 31UL
|
||||
#define FLASHC_CM4_CA_CTL0_ENABLED_Msk 0x80000000UL
|
||||
/* FLASHC.CM4_CA_CTL1 */
|
||||
#define FLASHC_CM4_CA_CTL1_PWR_MODE_Pos 0UL
|
||||
#define FLASHC_CM4_CA_CTL1_PWR_MODE_Msk 0x3UL
|
||||
#define FLASHC_CM4_CA_CTL1_VECTKEYSTAT_Pos 16UL
|
||||
#define FLASHC_CM4_CA_CTL1_VECTKEYSTAT_Msk 0xFFFF0000UL
|
||||
/* FLASHC.CM4_CA_CTL2 */
|
||||
#define FLASHC_CM4_CA_CTL2_PWRUP_DELAY_Pos 0UL
|
||||
#define FLASHC_CM4_CA_CTL2_PWRUP_DELAY_Msk 0x3FFUL
|
||||
/* FLASHC.CM4_CA_CMD */
|
||||
#define FLASHC_CM4_CA_CMD_INV_Pos 0UL
|
||||
#define FLASHC_CM4_CA_CMD_INV_Msk 0x1UL
|
||||
/* FLASHC.CM4_CA_STATUS0 */
|
||||
#define FLASHC_CM4_CA_STATUS0_VALID16_Pos 0UL
|
||||
#define FLASHC_CM4_CA_STATUS0_VALID16_Msk 0xFFFFUL
|
||||
/* FLASHC.CM4_CA_STATUS1 */
|
||||
#define FLASHC_CM4_CA_STATUS1_TAG_Pos 0UL
|
||||
#define FLASHC_CM4_CA_STATUS1_TAG_Msk 0xFFFFFFFFUL
|
||||
/* FLASHC.CM4_CA_STATUS2 */
|
||||
#define FLASHC_CM4_CA_STATUS2_LRU_Pos 0UL
|
||||
#define FLASHC_CM4_CA_STATUS2_LRU_Msk 0x3FUL
|
||||
/* FLASHC.CRYPTO_BUFF_CTL */
|
||||
#define FLASHC_CRYPTO_BUFF_CTL_PREF_EN_Pos 30UL
|
||||
#define FLASHC_CRYPTO_BUFF_CTL_PREF_EN_Msk 0x40000000UL
|
||||
#define FLASHC_CRYPTO_BUFF_CTL_ENABLED_Pos 31UL
|
||||
#define FLASHC_CRYPTO_BUFF_CTL_ENABLED_Msk 0x80000000UL
|
||||
/* FLASHC.CRYPTO_BUFF_CMD */
|
||||
#define FLASHC_CRYPTO_BUFF_CMD_INV_Pos 0UL
|
||||
#define FLASHC_CRYPTO_BUFF_CMD_INV_Msk 0x1UL
|
||||
/* FLASHC.DW0_BUFF_CTL */
|
||||
#define FLASHC_DW0_BUFF_CTL_PREF_EN_Pos 30UL
|
||||
#define FLASHC_DW0_BUFF_CTL_PREF_EN_Msk 0x40000000UL
|
||||
#define FLASHC_DW0_BUFF_CTL_ENABLED_Pos 31UL
|
||||
#define FLASHC_DW0_BUFF_CTL_ENABLED_Msk 0x80000000UL
|
||||
/* FLASHC.DW0_BUFF_CMD */
|
||||
#define FLASHC_DW0_BUFF_CMD_INV_Pos 0UL
|
||||
#define FLASHC_DW0_BUFF_CMD_INV_Msk 0x1UL
|
||||
/* FLASHC.DW1_BUFF_CTL */
|
||||
#define FLASHC_DW1_BUFF_CTL_PREF_EN_Pos 30UL
|
||||
#define FLASHC_DW1_BUFF_CTL_PREF_EN_Msk 0x40000000UL
|
||||
#define FLASHC_DW1_BUFF_CTL_ENABLED_Pos 31UL
|
||||
#define FLASHC_DW1_BUFF_CTL_ENABLED_Msk 0x80000000UL
|
||||
/* FLASHC.DW1_BUFF_CMD */
|
||||
#define FLASHC_DW1_BUFF_CMD_INV_Pos 0UL
|
||||
#define FLASHC_DW1_BUFF_CMD_INV_Msk 0x1UL
|
||||
/* FLASHC.DAP_BUFF_CTL */
|
||||
#define FLASHC_DAP_BUFF_CTL_PREF_EN_Pos 30UL
|
||||
#define FLASHC_DAP_BUFF_CTL_PREF_EN_Msk 0x40000000UL
|
||||
#define FLASHC_DAP_BUFF_CTL_ENABLED_Pos 31UL
|
||||
#define FLASHC_DAP_BUFF_CTL_ENABLED_Msk 0x80000000UL
|
||||
/* FLASHC.DAP_BUFF_CMD */
|
||||
#define FLASHC_DAP_BUFF_CMD_INV_Pos 0UL
|
||||
#define FLASHC_DAP_BUFF_CMD_INV_Msk 0x1UL
|
||||
/* FLASHC.EXT_MS0_BUFF_CTL */
|
||||
#define FLASHC_EXT_MS0_BUFF_CTL_PREF_EN_Pos 30UL
|
||||
#define FLASHC_EXT_MS0_BUFF_CTL_PREF_EN_Msk 0x40000000UL
|
||||
#define FLASHC_EXT_MS0_BUFF_CTL_ENABLED_Pos 31UL
|
||||
#define FLASHC_EXT_MS0_BUFF_CTL_ENABLED_Msk 0x80000000UL
|
||||
/* FLASHC.EXT_MS0_BUFF_CMD */
|
||||
#define FLASHC_EXT_MS0_BUFF_CMD_INV_Pos 0UL
|
||||
#define FLASHC_EXT_MS0_BUFF_CMD_INV_Msk 0x1UL
|
||||
/* FLASHC.EXT_MS1_BUFF_CTL */
|
||||
#define FLASHC_EXT_MS1_BUFF_CTL_PREF_EN_Pos 30UL
|
||||
#define FLASHC_EXT_MS1_BUFF_CTL_PREF_EN_Msk 0x40000000UL
|
||||
#define FLASHC_EXT_MS1_BUFF_CTL_ENABLED_Pos 31UL
|
||||
#define FLASHC_EXT_MS1_BUFF_CTL_ENABLED_Msk 0x80000000UL
|
||||
/* FLASHC.EXT_MS1_BUFF_CMD */
|
||||
#define FLASHC_EXT_MS1_BUFF_CMD_INV_Pos 0UL
|
||||
#define FLASHC_EXT_MS1_BUFF_CMD_INV_Msk 0x1UL
|
||||
|
||||
|
||||
#endif /* _CYIP_FLASHC_H_ */
|
||||
|
||||
|
||||
/* [] END OF FILE */
|
||||
|
|
@ -1,773 +0,0 @@
|
|||
/***************************************************************************//**
|
||||
* \file cyip_flashc_v2.h
|
||||
*
|
||||
* \brief
|
||||
* FLASHC IP definitions
|
||||
*
|
||||
* \note
|
||||
* Generator version: 1.3.0.1146
|
||||
* Database revision: rev#1050929
|
||||
*
|
||||
********************************************************************************
|
||||
* \copyright
|
||||
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
|
||||
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _CYIP_FLASHC_V2_H_
|
||||
#define _CYIP_FLASHC_V2_H_
|
||||
|
||||
#include "cyip_headers.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* FLASHC
|
||||
*******************************************************************************/
|
||||
|
||||
#define FLASHC_FM_CTL_V2_SECTION_SIZE 0x00001000UL
|
||||
#define FLASHC_V2_SECTION_SIZE 0x00010000UL
|
||||
|
||||
/**
|
||||
* \brief Flash Macro Registers (FLASHC_FM_CTL)
|
||||
*/
|
||||
typedef struct {
|
||||
__IOM uint32_t FM_CTL; /*!< 0x00000000 Flash macro control */
|
||||
__IM uint32_t STATUS; /*!< 0x00000004 Status */
|
||||
__IOM uint32_t FM_ADDR; /*!< 0x00000008 Flash macro address */
|
||||
__IOM uint32_t BOOKMARK; /*!< 0x0000000C Bookmark register - keeps the current FW HV seq */
|
||||
__IM uint32_t GEOMETRY; /*!< 0x00000010 Regular flash geometry */
|
||||
__IM uint32_t GEOMETRY_SUPERVISORY; /*!< 0x00000014 Supervisory flash geometry */
|
||||
__IOM uint32_t ANA_CTL0; /*!< 0x00000018 Analog control 0 */
|
||||
__IOM uint32_t ANA_CTL1; /*!< 0x0000001C Analog control 1 */
|
||||
__IM uint32_t RESERVED[2];
|
||||
__IOM uint32_t WAIT_CTL; /*!< 0x00000028 Wait State control */
|
||||
__IM uint32_t RESERVED1[2];
|
||||
__IOM uint32_t TIMER_CLK_CTL; /*!< 0x00000034 Timer prescaler (clk_t to timer clock frequency divider) */
|
||||
__IOM uint32_t TIMER_CTL; /*!< 0x00000038 Timer control */
|
||||
__OM uint32_t ACLK_CTL; /*!< 0x0000003C MPCON clock */
|
||||
__IOM uint32_t INTR; /*!< 0x00000040 Interrupt */
|
||||
__IOM uint32_t INTR_SET; /*!< 0x00000044 Interrupt set */
|
||||
__IOM uint32_t INTR_MASK; /*!< 0x00000048 Interrupt mask */
|
||||
__IM uint32_t INTR_MASKED; /*!< 0x0000004C Interrupt masked */
|
||||
__IOM uint32_t CAL_CTL0; /*!< 0x00000050 Cal control BG LO trim bits */
|
||||
__IOM uint32_t CAL_CTL1; /*!< 0x00000054 Cal control BG HI trim bits */
|
||||
__IOM uint32_t CAL_CTL2; /*!< 0x00000058 Cal control BG LO&HI trim bits */
|
||||
__IOM uint32_t CAL_CTL3; /*!< 0x0000005C Cal control osc trim bits, idac, sdac, itim */
|
||||
__IOM uint32_t CAL_CTL4; /*!< 0x00000060 Cal Control Vlim, SA, fdiv, reg_act */
|
||||
__IOM uint32_t CAL_CTL5; /*!< 0x00000064 Cal control */
|
||||
__IOM uint32_t CAL_CTL6; /*!< 0x00000068 SA trim LP/ULP */
|
||||
__IOM uint32_t CAL_CTL7; /*!< 0x0000006C Cal control */
|
||||
__IM uint32_t RESERVED2[4];
|
||||
__IOM uint32_t RED_CTL01; /*!< 0x00000080 Redundancy Control normal sectors 0,1 */
|
||||
__IOM uint32_t RED_CTL23; /*!< 0x00000084 Redundancy Control normal sectors 2,3 */
|
||||
__IOM uint32_t RED_CTL45; /*!< 0x00000088 Redundancy Control normal sectors 4,5 */
|
||||
__IOM uint32_t RED_CTL67; /*!< 0x0000008C Redundancy Control normal sectors 6,7 */
|
||||
__IOM uint32_t RED_CTL_SM01; /*!< 0x00000090 Redundancy Control special sectors 0,1 */
|
||||
__IM uint32_t RESERVED3;
|
||||
__IOM uint32_t RGRANT_DELAY; /*!< 0x00000098 R-grant delay */
|
||||
__IM uint32_t RESERVED4;
|
||||
__IOM uint32_t PW_SEQ12; /*!< 0x000000A0 HV Pulse Delay for seq 1&2 pre */
|
||||
__IOM uint32_t PW_SEQ23; /*!< 0x000000A4 HV Pulse Delay for seq2 post & seq3 */
|
||||
__IM uint32_t RESERVED5[469];
|
||||
__IOM uint32_t FM_PL_WRDATA_ALL; /*!< 0x000007FC Flash macro write page latches all */
|
||||
__IOM uint32_t FM_PL_DATA[256]; /*!< 0x00000800 Flash macro Page Latches data */
|
||||
__IM uint32_t FM_MEM_DATA[256]; /*!< 0x00000C00 Flash macro memory sense amplifier and column decoder data */
|
||||
} FLASHC_FM_CTL_V2_Type; /*!< Size = 4096 (0x1000) */
|
||||
|
||||
/**
|
||||
* \brief Flash controller (FLASHC)
|
||||
*/
|
||||
typedef struct {
|
||||
__IOM uint32_t FLASH_CTL; /*!< 0x00000000 Control */
|
||||
__IOM uint32_t FLASH_PWR_CTL; /*!< 0x00000004 Flash power control */
|
||||
__IOM uint32_t FLASH_CMD; /*!< 0x00000008 Command */
|
||||
__IM uint32_t RESERVED[125];
|
||||
__IOM uint32_t BIST_CTL; /*!< 0x00000200 BIST control */
|
||||
__IOM uint32_t BIST_CMD; /*!< 0x00000204 BIST command */
|
||||
__IOM uint32_t BIST_ADDR_START; /*!< 0x00000208 BIST address start register */
|
||||
__IOM uint32_t BIST_DATA[8]; /*!< 0x0000020C BIST data register(s) */
|
||||
__IM uint32_t BIST_MAIN_DATA_ACT[8]; /*!< 0x0000022C BIST (main) data actual register(s) */
|
||||
__IM uint32_t BIST_MAIN_DATA_EXP[8]; /*!< 0x0000024C BIST (main) data expected register(s) */
|
||||
__IM uint32_t BIST_MAIN_DATA_ECC_ACT; /*!< 0x0000026C BIST (main) ECC data actual register */
|
||||
__IM uint32_t BIST_MAIN_DATA_ECC_EXP; /*!< 0x00000270 BIST (main) ECC data expected register */
|
||||
__IM uint32_t BIST_MAIN_ADDR; /*!< 0x00000274 BIST (main) address register */
|
||||
__IOM uint32_t BIST_MAIN_STATUS; /*!< 0x00000278 BIST (main) status register */
|
||||
__IM uint32_t BIST_WORK_DATA_ACT; /*!< 0x0000027C BIST (work) data actual register */
|
||||
__IM uint32_t BIST_WORK_DATA_EXP; /*!< 0x00000280 BIST (work) data expected register */
|
||||
__IM uint32_t BIST_WORK_DATA_ECC_ACT; /*!< 0x00000284 BIST (work) ECC data actual register */
|
||||
__IM uint32_t BIST_WORK_DATA_ECC_EXP; /*!< 0x00000288 BIST (work) ECC data expected register */
|
||||
__IM uint32_t BIST_WORK_ADDR; /*!< 0x0000028C BIST (work) address register */
|
||||
__IOM uint32_t BIST_WORK_STATUS; /*!< 0x00000290 BIST (work) status register */
|
||||
__IOM uint32_t BIST_ADDR_STOP; /*!< 0x00000294 BIST address stop register */
|
||||
__IM uint32_t RESERVED1[2];
|
||||
__IOM uint32_t ECC_CTL; /*!< 0x000002A0 ECC control */
|
||||
__IM uint32_t RESERVED2[3];
|
||||
__IOM uint32_t FM_SRAM_ECC_CTL0; /*!< 0x000002B0 eCT Flash SRAM ECC control 0 */
|
||||
__IOM uint32_t FM_SRAM_ECC_CTL1; /*!< 0x000002B4 eCT Flash SRAM ECC control 1 */
|
||||
__IM uint32_t FM_SRAM_ECC_CTL2; /*!< 0x000002B8 eCT Flash SRAM ECC control 2 */
|
||||
__IOM uint32_t FM_SRAM_ECC_CTL3; /*!< 0x000002BC eCT Flash SRAM ECC control 3 */
|
||||
__IM uint32_t RESERVED3[80];
|
||||
__IOM uint32_t CM0_CA_CTL0; /*!< 0x00000400 CM0+ cache control */
|
||||
__IOM uint32_t CM0_CA_CTL1; /*!< 0x00000404 CM0+ cache control */
|
||||
__IOM uint32_t CM0_CA_CTL2; /*!< 0x00000408 CM0+ cache control */
|
||||
__IM uint32_t RESERVED4[13];
|
||||
__IM uint32_t CM0_CA_STATUS0; /*!< 0x00000440 CM0+ cache status 0 */
|
||||
__IM uint32_t CM0_CA_STATUS1; /*!< 0x00000444 CM0+ cache status 1 */
|
||||
__IM uint32_t CM0_CA_STATUS2; /*!< 0x00000448 CM0+ cache status 2 */
|
||||
__IM uint32_t RESERVED5[5];
|
||||
__IOM uint32_t CM0_STATUS; /*!< 0x00000460 CM0+ interface status */
|
||||
__IM uint32_t RESERVED6[7];
|
||||
__IOM uint32_t CM4_CA_CTL0; /*!< 0x00000480 CM4 cache control */
|
||||
__IOM uint32_t CM4_CA_CTL1; /*!< 0x00000484 CM4 cache control */
|
||||
__IOM uint32_t CM4_CA_CTL2; /*!< 0x00000488 CM4 cache control */
|
||||
__IM uint32_t RESERVED7[13];
|
||||
__IM uint32_t CM4_CA_STATUS0; /*!< 0x000004C0 CM4 cache status 0 */
|
||||
__IM uint32_t CM4_CA_STATUS1; /*!< 0x000004C4 CM4 cache status 1 */
|
||||
__IM uint32_t CM4_CA_STATUS2; /*!< 0x000004C8 CM4 cache status 2 */
|
||||
__IM uint32_t RESERVED8[5];
|
||||
__IOM uint32_t CM4_STATUS; /*!< 0x000004E0 CM4 interface status */
|
||||
__IM uint32_t RESERVED9[7];
|
||||
__IOM uint32_t CRYPTO_BUFF_CTL; /*!< 0x00000500 Cryptography buffer control */
|
||||
__IM uint32_t RESERVED10[31];
|
||||
__IOM uint32_t DW0_BUFF_CTL; /*!< 0x00000580 Datawire 0 buffer control */
|
||||
__IM uint32_t RESERVED11[31];
|
||||
__IOM uint32_t DW1_BUFF_CTL; /*!< 0x00000600 Datawire 1 buffer control */
|
||||
__IM uint32_t RESERVED12[31];
|
||||
__IOM uint32_t DMAC_BUFF_CTL; /*!< 0x00000680 DMA controller buffer control */
|
||||
__IM uint32_t RESERVED13[31];
|
||||
__IOM uint32_t EXT_MS0_BUFF_CTL; /*!< 0x00000700 External master 0 buffer control */
|
||||
__IM uint32_t RESERVED14[31];
|
||||
__IOM uint32_t EXT_MS1_BUFF_CTL; /*!< 0x00000780 External master 1 buffer control */
|
||||
__IM uint32_t RESERVED15[14879];
|
||||
FLASHC_FM_CTL_V2_Type FM_CTL; /*!< 0x0000F000 Flash Macro Registers */
|
||||
} FLASHC_V2_Type; /*!< Size = 65536 (0x10000) */
|
||||
|
||||
|
||||
/* FLASHC_FM_CTL.FM_CTL */
|
||||
#define FLASHC_FM_CTL_V2_FM_CTL_FM_MODE_Pos 0UL
|
||||
#define FLASHC_FM_CTL_V2_FM_CTL_FM_MODE_Msk 0xFUL
|
||||
#define FLASHC_FM_CTL_V2_FM_CTL_FM_SEQ_Pos 8UL
|
||||
#define FLASHC_FM_CTL_V2_FM_CTL_FM_SEQ_Msk 0x300UL
|
||||
#define FLASHC_FM_CTL_V2_FM_CTL_DAA_MUX_SEL_Pos 16UL
|
||||
#define FLASHC_FM_CTL_V2_FM_CTL_DAA_MUX_SEL_Msk 0x7F0000UL
|
||||
#define FLASHC_FM_CTL_V2_FM_CTL_IF_SEL_Pos 24UL
|
||||
#define FLASHC_FM_CTL_V2_FM_CTL_IF_SEL_Msk 0x1000000UL
|
||||
#define FLASHC_FM_CTL_V2_FM_CTL_WR_EN_Pos 25UL
|
||||
#define FLASHC_FM_CTL_V2_FM_CTL_WR_EN_Msk 0x2000000UL
|
||||
/* FLASHC_FM_CTL.STATUS */
|
||||
#define FLASHC_FM_CTL_V2_STATUS_TIMER_ENABLED_Pos 0UL
|
||||
#define FLASHC_FM_CTL_V2_STATUS_TIMER_ENABLED_Msk 0x1UL
|
||||
#define FLASHC_FM_CTL_V2_STATUS_HV_REGS_ISOLATED_Pos 1UL
|
||||
#define FLASHC_FM_CTL_V2_STATUS_HV_REGS_ISOLATED_Msk 0x2UL
|
||||
#define FLASHC_FM_CTL_V2_STATUS_ILLEGAL_HVOP_Pos 2UL
|
||||
#define FLASHC_FM_CTL_V2_STATUS_ILLEGAL_HVOP_Msk 0x4UL
|
||||
#define FLASHC_FM_CTL_V2_STATUS_TURBO_N_Pos 3UL
|
||||
#define FLASHC_FM_CTL_V2_STATUS_TURBO_N_Msk 0x8UL
|
||||
#define FLASHC_FM_CTL_V2_STATUS_WR_EN_MON_Pos 4UL
|
||||
#define FLASHC_FM_CTL_V2_STATUS_WR_EN_MON_Msk 0x10UL
|
||||
#define FLASHC_FM_CTL_V2_STATUS_IF_SEL_MON_Pos 5UL
|
||||
#define FLASHC_FM_CTL_V2_STATUS_IF_SEL_MON_Msk 0x20UL
|
||||
#define FLASHC_FM_CTL_V2_STATUS_TIMER_STATUS_Pos 6UL
|
||||
#define FLASHC_FM_CTL_V2_STATUS_TIMER_STATUS_Msk 0x40UL
|
||||
#define FLASHC_FM_CTL_V2_STATUS_R_GRANT_DELAY_STATUS_Pos 7UL
|
||||
#define FLASHC_FM_CTL_V2_STATUS_R_GRANT_DELAY_STATUS_Msk 0x80UL
|
||||
#define FLASHC_FM_CTL_V2_STATUS_FM_BUSY_Pos 8UL
|
||||
#define FLASHC_FM_CTL_V2_STATUS_FM_BUSY_Msk 0x100UL
|
||||
#define FLASHC_FM_CTL_V2_STATUS_FM_READY_Pos 9UL
|
||||
#define FLASHC_FM_CTL_V2_STATUS_FM_READY_Msk 0x200UL
|
||||
#define FLASHC_FM_CTL_V2_STATUS_POS_PUMP_VLO_Pos 10UL
|
||||
#define FLASHC_FM_CTL_V2_STATUS_POS_PUMP_VLO_Msk 0x400UL
|
||||
#define FLASHC_FM_CTL_V2_STATUS_NEG_PUMP_VHI_Pos 11UL
|
||||
#define FLASHC_FM_CTL_V2_STATUS_NEG_PUMP_VHI_Msk 0x800UL
|
||||
#define FLASHC_FM_CTL_V2_STATUS_RWW_Pos 12UL
|
||||
#define FLASHC_FM_CTL_V2_STATUS_RWW_Msk 0x1000UL
|
||||
#define FLASHC_FM_CTL_V2_STATUS_MAX_DOUT_WIDTH_Pos 13UL
|
||||
#define FLASHC_FM_CTL_V2_STATUS_MAX_DOUT_WIDTH_Msk 0x2000UL
|
||||
#define FLASHC_FM_CTL_V2_STATUS_SECTOR0_SR_Pos 14UL
|
||||
#define FLASHC_FM_CTL_V2_STATUS_SECTOR0_SR_Msk 0x4000UL
|
||||
#define FLASHC_FM_CTL_V2_STATUS_RESET_MM_Pos 15UL
|
||||
#define FLASHC_FM_CTL_V2_STATUS_RESET_MM_Msk 0x8000UL
|
||||
#define FLASHC_FM_CTL_V2_STATUS_ROW_ODD_Pos 16UL
|
||||
#define FLASHC_FM_CTL_V2_STATUS_ROW_ODD_Msk 0x10000UL
|
||||
#define FLASHC_FM_CTL_V2_STATUS_ROW_EVEN_Pos 17UL
|
||||
#define FLASHC_FM_CTL_V2_STATUS_ROW_EVEN_Msk 0x20000UL
|
||||
#define FLASHC_FM_CTL_V2_STATUS_HVOP_SUB_SECTOR_N_Pos 18UL
|
||||
#define FLASHC_FM_CTL_V2_STATUS_HVOP_SUB_SECTOR_N_Msk 0x40000UL
|
||||
#define FLASHC_FM_CTL_V2_STATUS_HVOP_SECTOR_Pos 19UL
|
||||
#define FLASHC_FM_CTL_V2_STATUS_HVOP_SECTOR_Msk 0x80000UL
|
||||
#define FLASHC_FM_CTL_V2_STATUS_HVOP_BULK_ALL_Pos 20UL
|
||||
#define FLASHC_FM_CTL_V2_STATUS_HVOP_BULK_ALL_Msk 0x100000UL
|
||||
#define FLASHC_FM_CTL_V2_STATUS_CBUS_RA_MATCH_Pos 21UL
|
||||
#define FLASHC_FM_CTL_V2_STATUS_CBUS_RA_MATCH_Msk 0x200000UL
|
||||
#define FLASHC_FM_CTL_V2_STATUS_CBUS_RED_ROW_EN_Pos 22UL
|
||||
#define FLASHC_FM_CTL_V2_STATUS_CBUS_RED_ROW_EN_Msk 0x400000UL
|
||||
#define FLASHC_FM_CTL_V2_STATUS_RQ_ERROR_Pos 23UL
|
||||
#define FLASHC_FM_CTL_V2_STATUS_RQ_ERROR_Msk 0x800000UL
|
||||
#define FLASHC_FM_CTL_V2_STATUS_PUMP_PDAC_Pos 24UL
|
||||
#define FLASHC_FM_CTL_V2_STATUS_PUMP_PDAC_Msk 0xF000000UL
|
||||
#define FLASHC_FM_CTL_V2_STATUS_PUMP_NDAC_Pos 28UL
|
||||
#define FLASHC_FM_CTL_V2_STATUS_PUMP_NDAC_Msk 0xF0000000UL
|
||||
/* FLASHC_FM_CTL.FM_ADDR */
|
||||
#define FLASHC_FM_CTL_V2_FM_ADDR_RA_Pos 0UL
|
||||
#define FLASHC_FM_CTL_V2_FM_ADDR_RA_Msk 0xFFFFUL
|
||||
#define FLASHC_FM_CTL_V2_FM_ADDR_BA_Pos 16UL
|
||||
#define FLASHC_FM_CTL_V2_FM_ADDR_BA_Msk 0xFF0000UL
|
||||
#define FLASHC_FM_CTL_V2_FM_ADDR_AXA_Pos 24UL
|
||||
#define FLASHC_FM_CTL_V2_FM_ADDR_AXA_Msk 0x1000000UL
|
||||
/* FLASHC_FM_CTL.BOOKMARK */
|
||||
#define FLASHC_FM_CTL_V2_BOOKMARK_BOOKMARK_Pos 0UL
|
||||
#define FLASHC_FM_CTL_V2_BOOKMARK_BOOKMARK_Msk 0xFFFFFFFFUL
|
||||
/* FLASHC_FM_CTL.GEOMETRY */
|
||||
#define FLASHC_FM_CTL_V2_GEOMETRY_ROW_COUNT_Pos 0UL
|
||||
#define FLASHC_FM_CTL_V2_GEOMETRY_ROW_COUNT_Msk 0xFFFFUL
|
||||
#define FLASHC_FM_CTL_V2_GEOMETRY_BANK_COUNT_Pos 16UL
|
||||
#define FLASHC_FM_CTL_V2_GEOMETRY_BANK_COUNT_Msk 0xFF0000UL
|
||||
#define FLASHC_FM_CTL_V2_GEOMETRY_WORD_SIZE_LOG2_Pos 24UL
|
||||
#define FLASHC_FM_CTL_V2_GEOMETRY_WORD_SIZE_LOG2_Msk 0xF000000UL
|
||||
#define FLASHC_FM_CTL_V2_GEOMETRY_PAGE_SIZE_LOG2_Pos 28UL
|
||||
#define FLASHC_FM_CTL_V2_GEOMETRY_PAGE_SIZE_LOG2_Msk 0xF0000000UL
|
||||
/* FLASHC_FM_CTL.GEOMETRY_SUPERVISORY */
|
||||
#define FLASHC_FM_CTL_V2_GEOMETRY_SUPERVISORY_ROW_COUNT_Pos 0UL
|
||||
#define FLASHC_FM_CTL_V2_GEOMETRY_SUPERVISORY_ROW_COUNT_Msk 0xFFFFUL
|
||||
#define FLASHC_FM_CTL_V2_GEOMETRY_SUPERVISORY_BANK_COUNT_Pos 16UL
|
||||
#define FLASHC_FM_CTL_V2_GEOMETRY_SUPERVISORY_BANK_COUNT_Msk 0xFF0000UL
|
||||
#define FLASHC_FM_CTL_V2_GEOMETRY_SUPERVISORY_WORD_SIZE_LOG2_Pos 24UL
|
||||
#define FLASHC_FM_CTL_V2_GEOMETRY_SUPERVISORY_WORD_SIZE_LOG2_Msk 0xF000000UL
|
||||
#define FLASHC_FM_CTL_V2_GEOMETRY_SUPERVISORY_PAGE_SIZE_LOG2_Pos 28UL
|
||||
#define FLASHC_FM_CTL_V2_GEOMETRY_SUPERVISORY_PAGE_SIZE_LOG2_Msk 0xF0000000UL
|
||||
/* FLASHC_FM_CTL.ANA_CTL0 */
|
||||
#define FLASHC_FM_CTL_V2_ANA_CTL0_MDAC_Pos 0UL
|
||||
#define FLASHC_FM_CTL_V2_ANA_CTL0_MDAC_Msk 0xFFUL
|
||||
#define FLASHC_FM_CTL_V2_ANA_CTL0_CSLDAC_Pos 8UL
|
||||
#define FLASHC_FM_CTL_V2_ANA_CTL0_CSLDAC_Msk 0x700UL
|
||||
#define FLASHC_FM_CTL_V2_ANA_CTL0_FLIP_AMUXBUS_AB_Pos 11UL
|
||||
#define FLASHC_FM_CTL_V2_ANA_CTL0_FLIP_AMUXBUS_AB_Msk 0x800UL
|
||||
#define FLASHC_FM_CTL_V2_ANA_CTL0_NDAC_MIN_Pos 12UL
|
||||
#define FLASHC_FM_CTL_V2_ANA_CTL0_NDAC_MIN_Msk 0xF000UL
|
||||
#define FLASHC_FM_CTL_V2_ANA_CTL0_PDAC_MIN_Pos 16UL
|
||||
#define FLASHC_FM_CTL_V2_ANA_CTL0_PDAC_MIN_Msk 0xF0000UL
|
||||
#define FLASHC_FM_CTL_V2_ANA_CTL0_SCALE_SEQ01_Pos 20UL
|
||||
#define FLASHC_FM_CTL_V2_ANA_CTL0_SCALE_SEQ01_Msk 0x300000UL
|
||||
#define FLASHC_FM_CTL_V2_ANA_CTL0_SCALE_SEQ12_Pos 22UL
|
||||
#define FLASHC_FM_CTL_V2_ANA_CTL0_SCALE_SEQ12_Msk 0xC00000UL
|
||||
#define FLASHC_FM_CTL_V2_ANA_CTL0_SCALE_SEQ23_Pos 24UL
|
||||
#define FLASHC_FM_CTL_V2_ANA_CTL0_SCALE_SEQ23_Msk 0x3000000UL
|
||||
#define FLASHC_FM_CTL_V2_ANA_CTL0_SCALE_SEQ30_Pos 26UL
|
||||
#define FLASHC_FM_CTL_V2_ANA_CTL0_SCALE_SEQ30_Msk 0xC000000UL
|
||||
#define FLASHC_FM_CTL_V2_ANA_CTL0_SCALE_PEON_Pos 28UL
|
||||
#define FLASHC_FM_CTL_V2_ANA_CTL0_SCALE_PEON_Msk 0x30000000UL
|
||||
#define FLASHC_FM_CTL_V2_ANA_CTL0_SCALE_PEOFF_Pos 30UL
|
||||
#define FLASHC_FM_CTL_V2_ANA_CTL0_SCALE_PEOFF_Msk 0xC0000000UL
|
||||
/* FLASHC_FM_CTL.ANA_CTL1 */
|
||||
#define FLASHC_FM_CTL_V2_ANA_CTL1_NDAC_MAX_Pos 0UL
|
||||
#define FLASHC_FM_CTL_V2_ANA_CTL1_NDAC_MAX_Msk 0xFUL
|
||||
#define FLASHC_FM_CTL_V2_ANA_CTL1_NDAC_STEP_Pos 4UL
|
||||
#define FLASHC_FM_CTL_V2_ANA_CTL1_NDAC_STEP_Msk 0xF0UL
|
||||
#define FLASHC_FM_CTL_V2_ANA_CTL1_PDAC_MAX_Pos 8UL
|
||||
#define FLASHC_FM_CTL_V2_ANA_CTL1_PDAC_MAX_Msk 0xF00UL
|
||||
#define FLASHC_FM_CTL_V2_ANA_CTL1_PDAC_STEP_Pos 12UL
|
||||
#define FLASHC_FM_CTL_V2_ANA_CTL1_PDAC_STEP_Msk 0xF000UL
|
||||
#define FLASHC_FM_CTL_V2_ANA_CTL1_NPDAC_STEP_TIME_Pos 16UL
|
||||
#define FLASHC_FM_CTL_V2_ANA_CTL1_NPDAC_STEP_TIME_Msk 0xFF0000UL
|
||||
#define FLASHC_FM_CTL_V2_ANA_CTL1_NPDAC_ZERO_TIME_Pos 24UL
|
||||
#define FLASHC_FM_CTL_V2_ANA_CTL1_NPDAC_ZERO_TIME_Msk 0xFF000000UL
|
||||
/* FLASHC_FM_CTL.WAIT_CTL */
|
||||
#define FLASHC_FM_CTL_V2_WAIT_CTL_WAIT_FM_MEM_RD_Pos 0UL
|
||||
#define FLASHC_FM_CTL_V2_WAIT_CTL_WAIT_FM_MEM_RD_Msk 0xFUL
|
||||
#define FLASHC_FM_CTL_V2_WAIT_CTL_WAIT_FM_HV_RD_Pos 8UL
|
||||
#define FLASHC_FM_CTL_V2_WAIT_CTL_WAIT_FM_HV_RD_Msk 0xF00UL
|
||||
#define FLASHC_FM_CTL_V2_WAIT_CTL_WAIT_FM_HV_WR_Pos 16UL
|
||||
#define FLASHC_FM_CTL_V2_WAIT_CTL_WAIT_FM_HV_WR_Msk 0x70000UL
|
||||
#define FLASHC_FM_CTL_V2_WAIT_CTL_LV_SPARE_1_Pos 24UL
|
||||
#define FLASHC_FM_CTL_V2_WAIT_CTL_LV_SPARE_1_Msk 0x3F000000UL
|
||||
/* FLASHC_FM_CTL.TIMER_CLK_CTL */
|
||||
#define FLASHC_FM_CTL_V2_TIMER_CLK_CTL_TIMER_CLOCK_FREQ_Pos 0UL
|
||||
#define FLASHC_FM_CTL_V2_TIMER_CLK_CTL_TIMER_CLOCK_FREQ_Msk 0xFFUL
|
||||
#define FLASHC_FM_CTL_V2_TIMER_CLK_CTL_RGRANT_DELAY_PEON_Pos 8UL
|
||||
#define FLASHC_FM_CTL_V2_TIMER_CLK_CTL_RGRANT_DELAY_PEON_Msk 0xFF00UL
|
||||
#define FLASHC_FM_CTL_V2_TIMER_CLK_CTL_RGRANT_DELAY_PEOFF_Pos 16UL
|
||||
#define FLASHC_FM_CTL_V2_TIMER_CLK_CTL_RGRANT_DELAY_PEOFF_Msk 0xFF0000UL
|
||||
#define FLASHC_FM_CTL_V2_TIMER_CLK_CTL_RGRANT_DELAY_SEQ01_Pos 24UL
|
||||
#define FLASHC_FM_CTL_V2_TIMER_CLK_CTL_RGRANT_DELAY_SEQ01_Msk 0xFF000000UL
|
||||
/* FLASHC_FM_CTL.TIMER_CTL */
|
||||
#define FLASHC_FM_CTL_V2_TIMER_CTL_PERIOD_Pos 0UL
|
||||
#define FLASHC_FM_CTL_V2_TIMER_CTL_PERIOD_Msk 0x7FFFUL
|
||||
#define FLASHC_FM_CTL_V2_TIMER_CTL_SCALE_Pos 15UL
|
||||
#define FLASHC_FM_CTL_V2_TIMER_CTL_SCALE_Msk 0x8000UL
|
||||
#define FLASHC_FM_CTL_V2_TIMER_CTL_AUTO_SEQUENCE_Pos 24UL
|
||||
#define FLASHC_FM_CTL_V2_TIMER_CTL_AUTO_SEQUENCE_Msk 0x1000000UL
|
||||
#define FLASHC_FM_CTL_V2_TIMER_CTL_PRE_PROG_Pos 25UL
|
||||
#define FLASHC_FM_CTL_V2_TIMER_CTL_PRE_PROG_Msk 0x2000000UL
|
||||
#define FLASHC_FM_CTL_V2_TIMER_CTL_PRE_PROG_CSL_Pos 26UL
|
||||
#define FLASHC_FM_CTL_V2_TIMER_CTL_PRE_PROG_CSL_Msk 0x4000000UL
|
||||
#define FLASHC_FM_CTL_V2_TIMER_CTL_PUMP_EN_Pos 29UL
|
||||
#define FLASHC_FM_CTL_V2_TIMER_CTL_PUMP_EN_Msk 0x20000000UL
|
||||
#define FLASHC_FM_CTL_V2_TIMER_CTL_ACLK_EN_Pos 30UL
|
||||
#define FLASHC_FM_CTL_V2_TIMER_CTL_ACLK_EN_Msk 0x40000000UL
|
||||
#define FLASHC_FM_CTL_V2_TIMER_CTL_TIMER_EN_Pos 31UL
|
||||
#define FLASHC_FM_CTL_V2_TIMER_CTL_TIMER_EN_Msk 0x80000000UL
|
||||
/* FLASHC_FM_CTL.ACLK_CTL */
|
||||
#define FLASHC_FM_CTL_V2_ACLK_CTL_ACLK_GEN_Pos 0UL
|
||||
#define FLASHC_FM_CTL_V2_ACLK_CTL_ACLK_GEN_Msk 0x1UL
|
||||
/* FLASHC_FM_CTL.INTR */
|
||||
#define FLASHC_FM_CTL_V2_INTR_TIMER_EXPIRED_Pos 0UL
|
||||
#define FLASHC_FM_CTL_V2_INTR_TIMER_EXPIRED_Msk 0x1UL
|
||||
/* FLASHC_FM_CTL.INTR_SET */
|
||||
#define FLASHC_FM_CTL_V2_INTR_SET_TIMER_EXPIRED_Pos 0UL
|
||||
#define FLASHC_FM_CTL_V2_INTR_SET_TIMER_EXPIRED_Msk 0x1UL
|
||||
/* FLASHC_FM_CTL.INTR_MASK */
|
||||
#define FLASHC_FM_CTL_V2_INTR_MASK_TIMER_EXPIRED_Pos 0UL
|
||||
#define FLASHC_FM_CTL_V2_INTR_MASK_TIMER_EXPIRED_Msk 0x1UL
|
||||
/* FLASHC_FM_CTL.INTR_MASKED */
|
||||
#define FLASHC_FM_CTL_V2_INTR_MASKED_TIMER_EXPIRED_Pos 0UL
|
||||
#define FLASHC_FM_CTL_V2_INTR_MASKED_TIMER_EXPIRED_Msk 0x1UL
|
||||
/* FLASHC_FM_CTL.CAL_CTL0 */
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL0_VCT_TRIM_LO_HV_Pos 0UL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL0_VCT_TRIM_LO_HV_Msk 0x1FUL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL0_CDAC_LO_HV_Pos 5UL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL0_CDAC_LO_HV_Msk 0xE0UL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL0_VBG_TRIM_LO_HV_Pos 8UL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL0_VBG_TRIM_LO_HV_Msk 0x1F00UL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL0_VBG_TC_TRIM_LO_HV_Pos 13UL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL0_VBG_TC_TRIM_LO_HV_Msk 0xE000UL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL0_ICREF_TC_TRIM_LO_HV_Pos 16UL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL0_ICREF_TC_TRIM_LO_HV_Msk 0x70000UL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL0_IPREF_TRIMA_LO_HV_Pos 19UL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL0_IPREF_TRIMA_LO_HV_Msk 0x80000UL
|
||||
/* FLASHC_FM_CTL.CAL_CTL1 */
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL1_VCT_TRIM_HI_HV_Pos 0UL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL1_VCT_TRIM_HI_HV_Msk 0x1FUL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL1_CDAC_HI_HV_Pos 5UL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL1_CDAC_HI_HV_Msk 0xE0UL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL1_VBG_TRIM_HI_HV_Pos 8UL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL1_VBG_TRIM_HI_HV_Msk 0x1F00UL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL1_VBG_TC_TRIM_HI_HV_Pos 13UL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL1_VBG_TC_TRIM_HI_HV_Msk 0xE000UL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL1_ICREF_TC_TRIM_HI_HV_Pos 16UL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL1_ICREF_TC_TRIM_HI_HV_Msk 0x70000UL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL1_IPREF_TRIMA_HI_HV_Pos 19UL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL1_IPREF_TRIMA_HI_HV_Msk 0x80000UL
|
||||
/* FLASHC_FM_CTL.CAL_CTL2 */
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL2_ICREF_TRIM_LO_HV_Pos 0UL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL2_ICREF_TRIM_LO_HV_Msk 0x1FUL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL2_ICREF_TRIM_HI_HV_Pos 5UL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL2_ICREF_TRIM_HI_HV_Msk 0x3E0UL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL2_IPREF_TRIM_LO_HV_Pos 10UL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL2_IPREF_TRIM_LO_HV_Msk 0x7C00UL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL2_IPREF_TRIM_HI_HV_Pos 15UL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL2_IPREF_TRIM_HI_HV_Msk 0xF8000UL
|
||||
/* FLASHC_FM_CTL.CAL_CTL3 */
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL3_OSC_TRIM_HV_Pos 0UL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL3_OSC_TRIM_HV_Msk 0xFUL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL3_OSC_RANGE_TRIM_HV_Pos 4UL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL3_OSC_RANGE_TRIM_HV_Msk 0x10UL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL3_VPROT_ACT_HV_Pos 5UL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL3_VPROT_ACT_HV_Msk 0x20UL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL3_IPREF_TC_HV_Pos 6UL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL3_IPREF_TC_HV_Msk 0x40UL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL3_VREF_SEL_HV_Pos 7UL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL3_VREF_SEL_HV_Msk 0x80UL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL3_IREF_SEL_HV_Pos 8UL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL3_IREF_SEL_HV_Msk 0x100UL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL3_REG_ACT_HV_Pos 9UL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL3_REG_ACT_HV_Msk 0x200UL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL3_FDIV_TRIM_HV_Pos 10UL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL3_FDIV_TRIM_HV_Msk 0xC00UL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL3_VDDHI_HV_Pos 12UL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL3_VDDHI_HV_Msk 0x1000UL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL3_TURBO_PULSEW_HV_Pos 13UL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL3_TURBO_PULSEW_HV_Msk 0x6000UL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL3_BGLO_EN_HV_Pos 15UL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL3_BGLO_EN_HV_Msk 0x8000UL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL3_BGHI_EN_HV_Pos 16UL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL3_BGHI_EN_HV_Msk 0x10000UL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL3_CL_ISO_DIS_HV_Pos 17UL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL3_CL_ISO_DIS_HV_Msk 0x20000UL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL3_R_GRANT_EN_HV_Pos 18UL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL3_R_GRANT_EN_HV_Msk 0x40000UL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL3_LP_ULP_SW_HV_Pos 19UL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL3_LP_ULP_SW_HV_Msk 0x80000UL
|
||||
/* FLASHC_FM_CTL.CAL_CTL4 */
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL4_VLIM_TRIM_ULP_HV_Pos 0UL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL4_VLIM_TRIM_ULP_HV_Msk 0x3UL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL4_IDAC_ULP_HV_Pos 2UL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL4_IDAC_ULP_HV_Msk 0x3CUL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL4_SDAC_ULP_HV_Pos 6UL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL4_SDAC_ULP_HV_Msk 0xC0UL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL4_ITIM_ULP_HV_Pos 8UL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL4_ITIM_ULP_HV_Msk 0x1F00UL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL4_FM_READY_DEL_ULP_HV_Pos 13UL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL4_FM_READY_DEL_ULP_HV_Msk 0x2000UL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL4_SPARE451_ULP_HV_Pos 14UL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL4_SPARE451_ULP_HV_Msk 0xC000UL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL4_READY_RESTART_N_HV_Pos 16UL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL4_READY_RESTART_N_HV_Msk 0x10000UL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL4_SPARE41_HV_Pos 17UL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL4_SPARE41_HV_Msk 0x20000UL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL4_AUTO_HVPULSE_HV_Pos 18UL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL4_AUTO_HVPULSE_HV_Msk 0x40000UL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL4_UGB_EN_HV_Pos 19UL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL4_UGB_EN_HV_Msk 0x80000UL
|
||||
/* FLASHC_FM_CTL.CAL_CTL5 */
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL5_VLIM_TRIM_LP_HV_Pos 0UL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL5_VLIM_TRIM_LP_HV_Msk 0x3UL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL5_IDAC_LP_HV_Pos 2UL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL5_IDAC_LP_HV_Msk 0x3CUL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL5_SDAC_LP_HV_Pos 6UL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL5_SDAC_LP_HV_Msk 0xC0UL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL5_ITIM_LP_HV_Pos 8UL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL5_ITIM_LP_HV_Msk 0x1F00UL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL5_FM_READY_DEL_LP_HV_Pos 13UL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL5_FM_READY_DEL_LP_HV_Msk 0x2000UL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL5_SPARE451_LP_HV_Pos 14UL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL5_SPARE451_LP_HV_Msk 0xC000UL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL5_SPARE52_HV_Pos 16UL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL5_SPARE52_HV_Msk 0x30000UL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL5_AMUX_SEL_HV_Pos 18UL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL5_AMUX_SEL_HV_Msk 0xC0000UL
|
||||
/* FLASHC_FM_CTL.CAL_CTL6 */
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL6_SA_CTL_TRIM_T1_ULP_HV_Pos 0UL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL6_SA_CTL_TRIM_T1_ULP_HV_Msk 0x1UL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL6_SA_CTL_TRIM_T4_ULP_HV_Pos 1UL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL6_SA_CTL_TRIM_T4_ULP_HV_Msk 0xEUL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL6_SA_CTL_TRIM_T5_ULP_HV_Pos 4UL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL6_SA_CTL_TRIM_T5_ULP_HV_Msk 0x70UL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL6_SA_CTL_TRIM_T6_ULP_HV_Pos 7UL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL6_SA_CTL_TRIM_T6_ULP_HV_Msk 0x180UL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL6_SA_CTL_TRIM_T8_ULP_HV_Pos 9UL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL6_SA_CTL_TRIM_T8_ULP_HV_Msk 0x200UL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL6_SA_CTL_TRIM_T1_LP_HV_Pos 10UL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL6_SA_CTL_TRIM_T1_LP_HV_Msk 0x400UL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL6_SA_CTL_TRIM_T4_LP_HV_Pos 11UL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL6_SA_CTL_TRIM_T4_LP_HV_Msk 0x3800UL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL6_SA_CTL_TRIM_T5_LP_HV_Pos 14UL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL6_SA_CTL_TRIM_T5_LP_HV_Msk 0x1C000UL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL6_SA_CTL_TRIM_T6_LP_HV_Pos 17UL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL6_SA_CTL_TRIM_T6_LP_HV_Msk 0x60000UL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL6_SA_CTL_TRIM_T8_LP_HV_Pos 19UL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL6_SA_CTL_TRIM_T8_LP_HV_Msk 0x80000UL
|
||||
/* FLASHC_FM_CTL.CAL_CTL7 */
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL7_ERSX8_CLK_SEL_HV_Pos 0UL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL7_ERSX8_CLK_SEL_HV_Msk 0x3UL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL7_FM_ACTIVE_HV_Pos 2UL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL7_FM_ACTIVE_HV_Msk 0x4UL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL7_TURBO_EXT_HV_Pos 3UL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL7_TURBO_EXT_HV_Msk 0x8UL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL7_NPDAC_HWCTL_DIS_HV_Pos 4UL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL7_NPDAC_HWCTL_DIS_HV_Msk 0x10UL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL7_FM_READY_DIS_HV_Pos 5UL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL7_FM_READY_DIS_HV_Msk 0x20UL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL7_ERSX8_EN_ALL_HV_Pos 6UL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL7_ERSX8_EN_ALL_HV_Msk 0x40UL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL7_SPARE7_HV_Pos 7UL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL7_SPARE7_HV_Msk 0x380UL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL7_SPARE7_ULP_HV_Pos 10UL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL7_SPARE7_ULP_HV_Msk 0x7C00UL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL7_SPARE7_LP_HV_Pos 15UL
|
||||
#define FLASHC_FM_CTL_V2_CAL_CTL7_SPARE7_LP_HV_Msk 0xF8000UL
|
||||
/* FLASHC_FM_CTL.RED_CTL01 */
|
||||
#define FLASHC_FM_CTL_V2_RED_CTL01_RED_ADDR_0_Pos 0UL
|
||||
#define FLASHC_FM_CTL_V2_RED_CTL01_RED_ADDR_0_Msk 0xFFUL
|
||||
#define FLASHC_FM_CTL_V2_RED_CTL01_RED_EN_0_Pos 8UL
|
||||
#define FLASHC_FM_CTL_V2_RED_CTL01_RED_EN_0_Msk 0x100UL
|
||||
#define FLASHC_FM_CTL_V2_RED_CTL01_RED_ADDR_1_Pos 16UL
|
||||
#define FLASHC_FM_CTL_V2_RED_CTL01_RED_ADDR_1_Msk 0xFF0000UL
|
||||
#define FLASHC_FM_CTL_V2_RED_CTL01_RED_EN_1_Pos 24UL
|
||||
#define FLASHC_FM_CTL_V2_RED_CTL01_RED_EN_1_Msk 0x1000000UL
|
||||
/* FLASHC_FM_CTL.RED_CTL23 */
|
||||
#define FLASHC_FM_CTL_V2_RED_CTL23_RED_ADDR_2_Pos 0UL
|
||||
#define FLASHC_FM_CTL_V2_RED_CTL23_RED_ADDR_2_Msk 0xFFUL
|
||||
#define FLASHC_FM_CTL_V2_RED_CTL23_RED_EN_2_Pos 8UL
|
||||
#define FLASHC_FM_CTL_V2_RED_CTL23_RED_EN_2_Msk 0x100UL
|
||||
#define FLASHC_FM_CTL_V2_RED_CTL23_RED_ADDR_3_Pos 16UL
|
||||
#define FLASHC_FM_CTL_V2_RED_CTL23_RED_ADDR_3_Msk 0xFF0000UL
|
||||
#define FLASHC_FM_CTL_V2_RED_CTL23_RED_EN_3_Pos 24UL
|
||||
#define FLASHC_FM_CTL_V2_RED_CTL23_RED_EN_3_Msk 0x1000000UL
|
||||
/* FLASHC_FM_CTL.RED_CTL45 */
|
||||
#define FLASHC_FM_CTL_V2_RED_CTL45_RED_ADDR_4_Pos 0UL
|
||||
#define FLASHC_FM_CTL_V2_RED_CTL45_RED_ADDR_4_Msk 0xFFUL
|
||||
#define FLASHC_FM_CTL_V2_RED_CTL45_RED_EN_4_Pos 8UL
|
||||
#define FLASHC_FM_CTL_V2_RED_CTL45_RED_EN_4_Msk 0x100UL
|
||||
#define FLASHC_FM_CTL_V2_RED_CTL45_RED_ADDR_5_Pos 16UL
|
||||
#define FLASHC_FM_CTL_V2_RED_CTL45_RED_ADDR_5_Msk 0xFF0000UL
|
||||
#define FLASHC_FM_CTL_V2_RED_CTL45_RED_EN_5_Pos 24UL
|
||||
#define FLASHC_FM_CTL_V2_RED_CTL45_RED_EN_5_Msk 0x1000000UL
|
||||
/* FLASHC_FM_CTL.RED_CTL67 */
|
||||
#define FLASHC_FM_CTL_V2_RED_CTL67_RED_ADDR_6_Pos 0UL
|
||||
#define FLASHC_FM_CTL_V2_RED_CTL67_RED_ADDR_6_Msk 0xFFUL
|
||||
#define FLASHC_FM_CTL_V2_RED_CTL67_RED_EN_6_Pos 8UL
|
||||
#define FLASHC_FM_CTL_V2_RED_CTL67_RED_EN_6_Msk 0x100UL
|
||||
#define FLASHC_FM_CTL_V2_RED_CTL67_RED_ADDR_7_Pos 16UL
|
||||
#define FLASHC_FM_CTL_V2_RED_CTL67_RED_ADDR_7_Msk 0xFF0000UL
|
||||
#define FLASHC_FM_CTL_V2_RED_CTL67_RED_EN_7_Pos 24UL
|
||||
#define FLASHC_FM_CTL_V2_RED_CTL67_RED_EN_7_Msk 0x1000000UL
|
||||
/* FLASHC_FM_CTL.RED_CTL_SM01 */
|
||||
#define FLASHC_FM_CTL_V2_RED_CTL_SM01_RED_ADDR_SM0_Pos 0UL
|
||||
#define FLASHC_FM_CTL_V2_RED_CTL_SM01_RED_ADDR_SM0_Msk 0xFFUL
|
||||
#define FLASHC_FM_CTL_V2_RED_CTL_SM01_RED_EN_SM0_Pos 8UL
|
||||
#define FLASHC_FM_CTL_V2_RED_CTL_SM01_RED_EN_SM0_Msk 0x100UL
|
||||
#define FLASHC_FM_CTL_V2_RED_CTL_SM01_RED_ADDR_SM1_Pos 16UL
|
||||
#define FLASHC_FM_CTL_V2_RED_CTL_SM01_RED_ADDR_SM1_Msk 0xFF0000UL
|
||||
#define FLASHC_FM_CTL_V2_RED_CTL_SM01_RED_EN_SM1_Pos 24UL
|
||||
#define FLASHC_FM_CTL_V2_RED_CTL_SM01_RED_EN_SM1_Msk 0x1000000UL
|
||||
/* FLASHC_FM_CTL.RGRANT_DELAY */
|
||||
#define FLASHC_FM_CTL_V2_RGRANT_DELAY_RGRANT_DELAY_SEQ12_Pos 0UL
|
||||
#define FLASHC_FM_CTL_V2_RGRANT_DELAY_RGRANT_DELAY_SEQ12_Msk 0xFFUL
|
||||
#define FLASHC_FM_CTL_V2_RGRANT_DELAY_RGRANT_DELAY_SEQ23_Pos 8UL
|
||||
#define FLASHC_FM_CTL_V2_RGRANT_DELAY_RGRANT_DELAY_SEQ23_Msk 0xFF00UL
|
||||
#define FLASHC_FM_CTL_V2_RGRANT_DELAY_RGRANT_DELAY_SEQ30_Pos 16UL
|
||||
#define FLASHC_FM_CTL_V2_RGRANT_DELAY_RGRANT_DELAY_SEQ30_Msk 0xFF0000UL
|
||||
#define FLASHC_FM_CTL_V2_RGRANT_DELAY_RGRANT_DELAY_CLK_Pos 24UL
|
||||
#define FLASHC_FM_CTL_V2_RGRANT_DELAY_RGRANT_DELAY_CLK_Msk 0xF000000UL
|
||||
#define FLASHC_FM_CTL_V2_RGRANT_DELAY_HV_PARAMS_LOADED_Pos 31UL
|
||||
#define FLASHC_FM_CTL_V2_RGRANT_DELAY_HV_PARAMS_LOADED_Msk 0x80000000UL
|
||||
/* FLASHC_FM_CTL.PW_SEQ12 */
|
||||
#define FLASHC_FM_CTL_V2_PW_SEQ12_PW_SEQ1_Pos 0UL
|
||||
#define FLASHC_FM_CTL_V2_PW_SEQ12_PW_SEQ1_Msk 0xFFFFUL
|
||||
#define FLASHC_FM_CTL_V2_PW_SEQ12_PW_SEQ2_PRE_Pos 16UL
|
||||
#define FLASHC_FM_CTL_V2_PW_SEQ12_PW_SEQ2_PRE_Msk 0xFFFF0000UL
|
||||
/* FLASHC_FM_CTL.PW_SEQ23 */
|
||||
#define FLASHC_FM_CTL_V2_PW_SEQ23_PW_SEQ2_POST_Pos 0UL
|
||||
#define FLASHC_FM_CTL_V2_PW_SEQ23_PW_SEQ2_POST_Msk 0xFFFFUL
|
||||
#define FLASHC_FM_CTL_V2_PW_SEQ23_PW_SEQ3_Pos 16UL
|
||||
#define FLASHC_FM_CTL_V2_PW_SEQ23_PW_SEQ3_Msk 0xFFFF0000UL
|
||||
/* FLASHC_FM_CTL.FM_PL_WRDATA_ALL */
|
||||
#define FLASHC_FM_CTL_V2_FM_PL_WRDATA_ALL_DATA32_Pos 0UL
|
||||
#define FLASHC_FM_CTL_V2_FM_PL_WRDATA_ALL_DATA32_Msk 0xFFFFFFFFUL
|
||||
/* FLASHC_FM_CTL.FM_PL_DATA */
|
||||
#define FLASHC_FM_CTL_V2_FM_PL_DATA_DATA32_Pos 0UL
|
||||
#define FLASHC_FM_CTL_V2_FM_PL_DATA_DATA32_Msk 0xFFFFFFFFUL
|
||||
/* FLASHC_FM_CTL.FM_MEM_DATA */
|
||||
#define FLASHC_FM_CTL_V2_FM_MEM_DATA_DATA32_Pos 0UL
|
||||
#define FLASHC_FM_CTL_V2_FM_MEM_DATA_DATA32_Msk 0xFFFFFFFFUL
|
||||
|
||||
|
||||
/* FLASHC.FLASH_CTL */
|
||||
#define FLASHC_V2_FLASH_CTL_MAIN_WS_Pos 0UL
|
||||
#define FLASHC_V2_FLASH_CTL_MAIN_WS_Msk 0xFUL
|
||||
#define FLASHC_V2_FLASH_CTL_MAIN_MAP_Pos 8UL
|
||||
#define FLASHC_V2_FLASH_CTL_MAIN_MAP_Msk 0x100UL
|
||||
#define FLASHC_V2_FLASH_CTL_WORK_MAP_Pos 9UL
|
||||
#define FLASHC_V2_FLASH_CTL_WORK_MAP_Msk 0x200UL
|
||||
#define FLASHC_V2_FLASH_CTL_MAIN_BANK_MODE_Pos 12UL
|
||||
#define FLASHC_V2_FLASH_CTL_MAIN_BANK_MODE_Msk 0x1000UL
|
||||
#define FLASHC_V2_FLASH_CTL_WORK_BANK_MODE_Pos 13UL
|
||||
#define FLASHC_V2_FLASH_CTL_WORK_BANK_MODE_Msk 0x2000UL
|
||||
#define FLASHC_V2_FLASH_CTL_MAIN_ECC_EN_Pos 16UL
|
||||
#define FLASHC_V2_FLASH_CTL_MAIN_ECC_EN_Msk 0x10000UL
|
||||
#define FLASHC_V2_FLASH_CTL_MAIN_ECC_INJ_EN_Pos 17UL
|
||||
#define FLASHC_V2_FLASH_CTL_MAIN_ECC_INJ_EN_Msk 0x20000UL
|
||||
#define FLASHC_V2_FLASH_CTL_MAIN_ERR_SILENT_Pos 18UL
|
||||
#define FLASHC_V2_FLASH_CTL_MAIN_ERR_SILENT_Msk 0x40000UL
|
||||
#define FLASHC_V2_FLASH_CTL_WORK_ECC_EN_Pos 20UL
|
||||
#define FLASHC_V2_FLASH_CTL_WORK_ECC_EN_Msk 0x100000UL
|
||||
#define FLASHC_V2_FLASH_CTL_WORK_ECC_INJ_EN_Pos 21UL
|
||||
#define FLASHC_V2_FLASH_CTL_WORK_ECC_INJ_EN_Msk 0x200000UL
|
||||
#define FLASHC_V2_FLASH_CTL_WORK_ERR_SILENT_Pos 22UL
|
||||
#define FLASHC_V2_FLASH_CTL_WORK_ERR_SILENT_Msk 0x400000UL
|
||||
/* FLASHC.FLASH_PWR_CTL */
|
||||
#define FLASHC_V2_FLASH_PWR_CTL_ENABLE_Pos 0UL
|
||||
#define FLASHC_V2_FLASH_PWR_CTL_ENABLE_Msk 0x1UL
|
||||
#define FLASHC_V2_FLASH_PWR_CTL_ENABLE_HV_Pos 1UL
|
||||
#define FLASHC_V2_FLASH_PWR_CTL_ENABLE_HV_Msk 0x2UL
|
||||
/* FLASHC.FLASH_CMD */
|
||||
#define FLASHC_V2_FLASH_CMD_INV_Pos 0UL
|
||||
#define FLASHC_V2_FLASH_CMD_INV_Msk 0x1UL
|
||||
#define FLASHC_V2_FLASH_CMD_BUFF_INV_Pos 1UL
|
||||
#define FLASHC_V2_FLASH_CMD_BUFF_INV_Msk 0x2UL
|
||||
/* FLASHC.BIST_CTL */
|
||||
#define FLASHC_V2_BIST_CTL_OPCODE_Pos 0UL
|
||||
#define FLASHC_V2_BIST_CTL_OPCODE_Msk 0x3UL
|
||||
#define FLASHC_V2_BIST_CTL_UP_Pos 2UL
|
||||
#define FLASHC_V2_BIST_CTL_UP_Msk 0x4UL
|
||||
#define FLASHC_V2_BIST_CTL_ROW_FIRST_Pos 3UL
|
||||
#define FLASHC_V2_BIST_CTL_ROW_FIRST_Msk 0x8UL
|
||||
#define FLASHC_V2_BIST_CTL_ADDR_START_ENABLED_Pos 4UL
|
||||
#define FLASHC_V2_BIST_CTL_ADDR_START_ENABLED_Msk 0x10UL
|
||||
#define FLASHC_V2_BIST_CTL_ADDR_COMPLIMENT_ENABLED_Pos 5UL
|
||||
#define FLASHC_V2_BIST_CTL_ADDR_COMPLIMENT_ENABLED_Msk 0x20UL
|
||||
#define FLASHC_V2_BIST_CTL_INCR_DECR_BOTH_Pos 6UL
|
||||
#define FLASHC_V2_BIST_CTL_INCR_DECR_BOTH_Msk 0x40UL
|
||||
#define FLASHC_V2_BIST_CTL_STOP_ON_ERROR_Pos 7UL
|
||||
#define FLASHC_V2_BIST_CTL_STOP_ON_ERROR_Msk 0x80UL
|
||||
#define FLASHC_V2_BIST_CTL_FM_REGION_TYPE_Pos 8UL
|
||||
#define FLASHC_V2_BIST_CTL_FM_REGION_TYPE_Msk 0x300UL
|
||||
#define FLASHC_V2_BIST_CTL_ECC_EN_Pos 12UL
|
||||
#define FLASHC_V2_BIST_CTL_ECC_EN_Msk 0x1000UL
|
||||
#define FLASHC_V2_BIST_CTL_ADDR_STOP_ENABLED_Pos 16UL
|
||||
#define FLASHC_V2_BIST_CTL_ADDR_STOP_ENABLED_Msk 0x10000UL
|
||||
/* FLASHC.BIST_CMD */
|
||||
#define FLASHC_V2_BIST_CMD_MAIN_START_Pos 0UL
|
||||
#define FLASHC_V2_BIST_CMD_MAIN_START_Msk 0x1UL
|
||||
#define FLASHC_V2_BIST_CMD_WORK_START_Pos 1UL
|
||||
#define FLASHC_V2_BIST_CMD_WORK_START_Msk 0x2UL
|
||||
/* FLASHC.BIST_ADDR_START */
|
||||
#define FLASHC_V2_BIST_ADDR_START_COL_ADDR_START_Pos 0UL
|
||||
#define FLASHC_V2_BIST_ADDR_START_COL_ADDR_START_Msk 0xFFFFUL
|
||||
#define FLASHC_V2_BIST_ADDR_START_ROW_ADDR_START_Pos 16UL
|
||||
#define FLASHC_V2_BIST_ADDR_START_ROW_ADDR_START_Msk 0xFFFF0000UL
|
||||
/* FLASHC.BIST_DATA */
|
||||
#define FLASHC_V2_BIST_DATA_DATA_Pos 0UL
|
||||
#define FLASHC_V2_BIST_DATA_DATA_Msk 0xFFFFFFFFUL
|
||||
/* FLASHC.BIST_MAIN_DATA_ACT */
|
||||
#define FLASHC_V2_BIST_MAIN_DATA_ACT_DATA_Pos 0UL
|
||||
#define FLASHC_V2_BIST_MAIN_DATA_ACT_DATA_Msk 0xFFFFFFFFUL
|
||||
/* FLASHC.BIST_MAIN_DATA_EXP */
|
||||
#define FLASHC_V2_BIST_MAIN_DATA_EXP_DATA_Pos 0UL
|
||||
#define FLASHC_V2_BIST_MAIN_DATA_EXP_DATA_Msk 0xFFFFFFFFUL
|
||||
/* FLASHC.BIST_MAIN_DATA_ECC_ACT */
|
||||
#define FLASHC_V2_BIST_MAIN_DATA_ECC_ACT_DATA_Pos 0UL
|
||||
#define FLASHC_V2_BIST_MAIN_DATA_ECC_ACT_DATA_Msk 0xFFFFFFFFUL
|
||||
/* FLASHC.BIST_MAIN_DATA_ECC_EXP */
|
||||
#define FLASHC_V2_BIST_MAIN_DATA_ECC_EXP_DATA_Pos 0UL
|
||||
#define FLASHC_V2_BIST_MAIN_DATA_ECC_EXP_DATA_Msk 0xFFFFFFFFUL
|
||||
/* FLASHC.BIST_MAIN_ADDR */
|
||||
#define FLASHC_V2_BIST_MAIN_ADDR_COL_ADDR_Pos 0UL
|
||||
#define FLASHC_V2_BIST_MAIN_ADDR_COL_ADDR_Msk 0xFFFFUL
|
||||
#define FLASHC_V2_BIST_MAIN_ADDR_ROW_ADDR_Pos 16UL
|
||||
#define FLASHC_V2_BIST_MAIN_ADDR_ROW_ADDR_Msk 0xFFFF0000UL
|
||||
/* FLASHC.BIST_MAIN_STATUS */
|
||||
#define FLASHC_V2_BIST_MAIN_STATUS_FAIL_Pos 0UL
|
||||
#define FLASHC_V2_BIST_MAIN_STATUS_FAIL_Msk 0x1UL
|
||||
/* FLASHC.BIST_WORK_DATA_ACT */
|
||||
#define FLASHC_V2_BIST_WORK_DATA_ACT_DATA_Pos 0UL
|
||||
#define FLASHC_V2_BIST_WORK_DATA_ACT_DATA_Msk 0xFFFFFFFFUL
|
||||
/* FLASHC.BIST_WORK_DATA_EXP */
|
||||
#define FLASHC_V2_BIST_WORK_DATA_EXP_DATA_Pos 0UL
|
||||
#define FLASHC_V2_BIST_WORK_DATA_EXP_DATA_Msk 0xFFFFFFFFUL
|
||||
/* FLASHC.BIST_WORK_DATA_ECC_ACT */
|
||||
#define FLASHC_V2_BIST_WORK_DATA_ECC_ACT_DATA_ECC_Pos 0UL
|
||||
#define FLASHC_V2_BIST_WORK_DATA_ECC_ACT_DATA_ECC_Msk 0x7FUL
|
||||
/* FLASHC.BIST_WORK_DATA_ECC_EXP */
|
||||
#define FLASHC_V2_BIST_WORK_DATA_ECC_EXP_DATA_ECC_Pos 0UL
|
||||
#define FLASHC_V2_BIST_WORK_DATA_ECC_EXP_DATA_ECC_Msk 0x7FUL
|
||||
/* FLASHC.BIST_WORK_ADDR */
|
||||
#define FLASHC_V2_BIST_WORK_ADDR_COL_ADDR_Pos 0UL
|
||||
#define FLASHC_V2_BIST_WORK_ADDR_COL_ADDR_Msk 0xFFFFUL
|
||||
#define FLASHC_V2_BIST_WORK_ADDR_ROW_ADDR_Pos 16UL
|
||||
#define FLASHC_V2_BIST_WORK_ADDR_ROW_ADDR_Msk 0xFFFF0000UL
|
||||
/* FLASHC.BIST_WORK_STATUS */
|
||||
#define FLASHC_V2_BIST_WORK_STATUS_FAIL_Pos 0UL
|
||||
#define FLASHC_V2_BIST_WORK_STATUS_FAIL_Msk 0x1UL
|
||||
/* FLASHC.BIST_ADDR_STOP */
|
||||
#define FLASHC_V2_BIST_ADDR_STOP_COL_ADDR_STOP_Pos 0UL
|
||||
#define FLASHC_V2_BIST_ADDR_STOP_COL_ADDR_STOP_Msk 0xFFFFUL
|
||||
#define FLASHC_V2_BIST_ADDR_STOP_ROW_ADDR_STOP_Pos 16UL
|
||||
#define FLASHC_V2_BIST_ADDR_STOP_ROW_ADDR_STOP_Msk 0xFFFF0000UL
|
||||
/* FLASHC.ECC_CTL */
|
||||
#define FLASHC_V2_ECC_CTL_WORD_ADDR_Pos 0UL
|
||||
#define FLASHC_V2_ECC_CTL_WORD_ADDR_Msk 0xFFFFFFUL
|
||||
#define FLASHC_V2_ECC_CTL_PARITY_Pos 24UL
|
||||
#define FLASHC_V2_ECC_CTL_PARITY_Msk 0xFF000000UL
|
||||
/* FLASHC.FM_SRAM_ECC_CTL0 */
|
||||
#define FLASHC_V2_FM_SRAM_ECC_CTL0_ECC_INJ_DATA_Pos 0UL
|
||||
#define FLASHC_V2_FM_SRAM_ECC_CTL0_ECC_INJ_DATA_Msk 0xFFFFFFFFUL
|
||||
/* FLASHC.FM_SRAM_ECC_CTL1 */
|
||||
#define FLASHC_V2_FM_SRAM_ECC_CTL1_ECC_INJ_PARITY_Pos 0UL
|
||||
#define FLASHC_V2_FM_SRAM_ECC_CTL1_ECC_INJ_PARITY_Msk 0x7FUL
|
||||
/* FLASHC.FM_SRAM_ECC_CTL2 */
|
||||
#define FLASHC_V2_FM_SRAM_ECC_CTL2_CORRECTED_DATA_Pos 0UL
|
||||
#define FLASHC_V2_FM_SRAM_ECC_CTL2_CORRECTED_DATA_Msk 0xFFFFFFFFUL
|
||||
/* FLASHC.FM_SRAM_ECC_CTL3 */
|
||||
#define FLASHC_V2_FM_SRAM_ECC_CTL3_ECC_ENABLE_Pos 0UL
|
||||
#define FLASHC_V2_FM_SRAM_ECC_CTL3_ECC_ENABLE_Msk 0x1UL
|
||||
#define FLASHC_V2_FM_SRAM_ECC_CTL3_ECC_INJ_EN_Pos 4UL
|
||||
#define FLASHC_V2_FM_SRAM_ECC_CTL3_ECC_INJ_EN_Msk 0x10UL
|
||||
#define FLASHC_V2_FM_SRAM_ECC_CTL3_ECC_TEST_FAIL_Pos 8UL
|
||||
#define FLASHC_V2_FM_SRAM_ECC_CTL3_ECC_TEST_FAIL_Msk 0x100UL
|
||||
/* FLASHC.CM0_CA_CTL0 */
|
||||
#define FLASHC_V2_CM0_CA_CTL0_RAM_ECC_EN_Pos 0UL
|
||||
#define FLASHC_V2_CM0_CA_CTL0_RAM_ECC_EN_Msk 0x1UL
|
||||
#define FLASHC_V2_CM0_CA_CTL0_RAM_ECC_INJ_EN_Pos 1UL
|
||||
#define FLASHC_V2_CM0_CA_CTL0_RAM_ECC_INJ_EN_Msk 0x2UL
|
||||
#define FLASHC_V2_CM0_CA_CTL0_WAY_Pos 16UL
|
||||
#define FLASHC_V2_CM0_CA_CTL0_WAY_Msk 0x30000UL
|
||||
#define FLASHC_V2_CM0_CA_CTL0_SET_ADDR_Pos 24UL
|
||||
#define FLASHC_V2_CM0_CA_CTL0_SET_ADDR_Msk 0x7000000UL
|
||||
#define FLASHC_V2_CM0_CA_CTL0_PREF_EN_Pos 30UL
|
||||
#define FLASHC_V2_CM0_CA_CTL0_PREF_EN_Msk 0x40000000UL
|
||||
#define FLASHC_V2_CM0_CA_CTL0_CA_EN_Pos 31UL
|
||||
#define FLASHC_V2_CM0_CA_CTL0_CA_EN_Msk 0x80000000UL
|
||||
/* FLASHC.CM0_CA_CTL1 */
|
||||
#define FLASHC_V2_CM0_CA_CTL1_PWR_MODE_Pos 0UL
|
||||
#define FLASHC_V2_CM0_CA_CTL1_PWR_MODE_Msk 0x3UL
|
||||
#define FLASHC_V2_CM0_CA_CTL1_VECTKEYSTAT_Pos 16UL
|
||||
#define FLASHC_V2_CM0_CA_CTL1_VECTKEYSTAT_Msk 0xFFFF0000UL
|
||||
/* FLASHC.CM0_CA_CTL2 */
|
||||
#define FLASHC_V2_CM0_CA_CTL2_PWRUP_DELAY_Pos 0UL
|
||||
#define FLASHC_V2_CM0_CA_CTL2_PWRUP_DELAY_Msk 0x3FFUL
|
||||
/* FLASHC.CM0_CA_STATUS0 */
|
||||
#define FLASHC_V2_CM0_CA_STATUS0_VALID32_Pos 0UL
|
||||
#define FLASHC_V2_CM0_CA_STATUS0_VALID32_Msk 0xFFFFFFFFUL
|
||||
/* FLASHC.CM0_CA_STATUS1 */
|
||||
#define FLASHC_V2_CM0_CA_STATUS1_TAG_Pos 0UL
|
||||
#define FLASHC_V2_CM0_CA_STATUS1_TAG_Msk 0xFFFFFFFFUL
|
||||
/* FLASHC.CM0_CA_STATUS2 */
|
||||
#define FLASHC_V2_CM0_CA_STATUS2_LRU_Pos 0UL
|
||||
#define FLASHC_V2_CM0_CA_STATUS2_LRU_Msk 0x3FUL
|
||||
/* FLASHC.CM0_STATUS */
|
||||
#define FLASHC_V2_CM0_STATUS_MAIN_INTERNAL_ERR_Pos 0UL
|
||||
#define FLASHC_V2_CM0_STATUS_MAIN_INTERNAL_ERR_Msk 0x1UL
|
||||
#define FLASHC_V2_CM0_STATUS_WORK_INTERNAL_ERR_Pos 1UL
|
||||
#define FLASHC_V2_CM0_STATUS_WORK_INTERNAL_ERR_Msk 0x2UL
|
||||
/* FLASHC.CM4_CA_CTL0 */
|
||||
#define FLASHC_V2_CM4_CA_CTL0_RAM_ECC_EN_Pos 0UL
|
||||
#define FLASHC_V2_CM4_CA_CTL0_RAM_ECC_EN_Msk 0x1UL
|
||||
#define FLASHC_V2_CM4_CA_CTL0_RAM_ECC_INJ_EN_Pos 1UL
|
||||
#define FLASHC_V2_CM4_CA_CTL0_RAM_ECC_INJ_EN_Msk 0x2UL
|
||||
#define FLASHC_V2_CM4_CA_CTL0_WAY_Pos 16UL
|
||||
#define FLASHC_V2_CM4_CA_CTL0_WAY_Msk 0x30000UL
|
||||
#define FLASHC_V2_CM4_CA_CTL0_SET_ADDR_Pos 24UL
|
||||
#define FLASHC_V2_CM4_CA_CTL0_SET_ADDR_Msk 0x7000000UL
|
||||
#define FLASHC_V2_CM4_CA_CTL0_PREF_EN_Pos 30UL
|
||||
#define FLASHC_V2_CM4_CA_CTL0_PREF_EN_Msk 0x40000000UL
|
||||
#define FLASHC_V2_CM4_CA_CTL0_CA_EN_Pos 31UL
|
||||
#define FLASHC_V2_CM4_CA_CTL0_CA_EN_Msk 0x80000000UL
|
||||
/* FLASHC.CM4_CA_CTL1 */
|
||||
#define FLASHC_V2_CM4_CA_CTL1_PWR_MODE_Pos 0UL
|
||||
#define FLASHC_V2_CM4_CA_CTL1_PWR_MODE_Msk 0x3UL
|
||||
#define FLASHC_V2_CM4_CA_CTL1_VECTKEYSTAT_Pos 16UL
|
||||
#define FLASHC_V2_CM4_CA_CTL1_VECTKEYSTAT_Msk 0xFFFF0000UL
|
||||
/* FLASHC.CM4_CA_CTL2 */
|
||||
#define FLASHC_V2_CM4_CA_CTL2_PWRUP_DELAY_Pos 0UL
|
||||
#define FLASHC_V2_CM4_CA_CTL2_PWRUP_DELAY_Msk 0x3FFUL
|
||||
/* FLASHC.CM4_CA_STATUS0 */
|
||||
#define FLASHC_V2_CM4_CA_STATUS0_VALID32_Pos 0UL
|
||||
#define FLASHC_V2_CM4_CA_STATUS0_VALID32_Msk 0xFFFFFFFFUL
|
||||
/* FLASHC.CM4_CA_STATUS1 */
|
||||
#define FLASHC_V2_CM4_CA_STATUS1_TAG_Pos 0UL
|
||||
#define FLASHC_V2_CM4_CA_STATUS1_TAG_Msk 0xFFFFFFFFUL
|
||||
/* FLASHC.CM4_CA_STATUS2 */
|
||||
#define FLASHC_V2_CM4_CA_STATUS2_LRU_Pos 0UL
|
||||
#define FLASHC_V2_CM4_CA_STATUS2_LRU_Msk 0x3FUL
|
||||
/* FLASHC.CM4_STATUS */
|
||||
#define FLASHC_V2_CM4_STATUS_MAIN_INTERNAL_ERR_Pos 0UL
|
||||
#define FLASHC_V2_CM4_STATUS_MAIN_INTERNAL_ERR_Msk 0x1UL
|
||||
#define FLASHC_V2_CM4_STATUS_WORK_INTERNAL_ERR_Pos 1UL
|
||||
#define FLASHC_V2_CM4_STATUS_WORK_INTERNAL_ERR_Msk 0x2UL
|
||||
/* FLASHC.CRYPTO_BUFF_CTL */
|
||||
#define FLASHC_V2_CRYPTO_BUFF_CTL_PREF_EN_Pos 30UL
|
||||
#define FLASHC_V2_CRYPTO_BUFF_CTL_PREF_EN_Msk 0x40000000UL
|
||||
/* FLASHC.DW0_BUFF_CTL */
|
||||
#define FLASHC_V2_DW0_BUFF_CTL_PREF_EN_Pos 30UL
|
||||
#define FLASHC_V2_DW0_BUFF_CTL_PREF_EN_Msk 0x40000000UL
|
||||
/* FLASHC.DW1_BUFF_CTL */
|
||||
#define FLASHC_V2_DW1_BUFF_CTL_PREF_EN_Pos 30UL
|
||||
#define FLASHC_V2_DW1_BUFF_CTL_PREF_EN_Msk 0x40000000UL
|
||||
/* FLASHC.DMAC_BUFF_CTL */
|
||||
#define FLASHC_V2_DMAC_BUFF_CTL_PREF_EN_Pos 30UL
|
||||
#define FLASHC_V2_DMAC_BUFF_CTL_PREF_EN_Msk 0x40000000UL
|
||||
/* FLASHC.EXT_MS0_BUFF_CTL */
|
||||
#define FLASHC_V2_EXT_MS0_BUFF_CTL_PREF_EN_Pos 30UL
|
||||
#define FLASHC_V2_EXT_MS0_BUFF_CTL_PREF_EN_Msk 0x40000000UL
|
||||
/* FLASHC.EXT_MS1_BUFF_CTL */
|
||||
#define FLASHC_V2_EXT_MS1_BUFF_CTL_PREF_EN_Pos 30UL
|
||||
#define FLASHC_V2_EXT_MS1_BUFF_CTL_PREF_EN_Msk 0x40000000UL
|
||||
|
||||
|
||||
#endif /* _CYIP_FLASHC_V2_H_ */
|
||||
|
||||
|
||||
/* [] END OF FILE */
|
||||
|
|
@ -1,469 +0,0 @@
|
|||
/***************************************************************************//**
|
||||
* \file cyip_gpio.h
|
||||
*
|
||||
* \brief
|
||||
* GPIO IP definitions
|
||||
*
|
||||
* \note
|
||||
* Generator version: 1.3.0.1146
|
||||
* Database revision: rev#1050929
|
||||
*
|
||||
********************************************************************************
|
||||
* \copyright
|
||||
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
|
||||
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _CYIP_GPIO_H_
|
||||
#define _CYIP_GPIO_H_
|
||||
|
||||
#include "cyip_headers.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* GPIO
|
||||
*******************************************************************************/
|
||||
|
||||
#define GPIO_PRT_SECTION_SIZE 0x00000080UL
|
||||
#define GPIO_SECTION_SIZE 0x00010000UL
|
||||
|
||||
/**
|
||||
* \brief GPIO port registers (GPIO_PRT)
|
||||
*/
|
||||
typedef struct {
|
||||
__IOM uint32_t OUT; /*!< 0x00000000 Port output data register */
|
||||
__IOM uint32_t OUT_CLR; /*!< 0x00000004 Port output data set register */
|
||||
__IOM uint32_t OUT_SET; /*!< 0x00000008 Port output data clear register */
|
||||
__IOM uint32_t OUT_INV; /*!< 0x0000000C Port output data invert register */
|
||||
__IM uint32_t IN; /*!< 0x00000010 Port input state register */
|
||||
__IOM uint32_t INTR; /*!< 0x00000014 Port interrupt status register */
|
||||
__IOM uint32_t INTR_MASK; /*!< 0x00000018 Port interrupt mask register */
|
||||
__IM uint32_t INTR_MASKED; /*!< 0x0000001C Port interrupt masked status register */
|
||||
__IOM uint32_t INTR_SET; /*!< 0x00000020 Port interrupt set register */
|
||||
__IOM uint32_t INTR_CFG; /*!< 0x00000024 Port interrupt configuration register */
|
||||
__IOM uint32_t CFG; /*!< 0x00000028 Port configuration register */
|
||||
__IOM uint32_t CFG_IN; /*!< 0x0000002C Port input buffer configuration register */
|
||||
__IOM uint32_t CFG_OUT; /*!< 0x00000030 Port output buffer configuration register */
|
||||
__IOM uint32_t CFG_SIO; /*!< 0x00000034 Port SIO configuration register */
|
||||
__IM uint32_t RESERVED;
|
||||
__IOM uint32_t CFG_IN_GPIO5V; /*!< 0x0000003C Port GPIO5V input buffer configuration register */
|
||||
__IM uint32_t RESERVED1[16];
|
||||
} GPIO_PRT_V1_Type; /*!< Size = 128 (0x80) */
|
||||
|
||||
/**
|
||||
* \brief GPIO port control/configuration (GPIO)
|
||||
*/
|
||||
typedef struct {
|
||||
GPIO_PRT_V1_Type PRT[128]; /*!< 0x00000000 GPIO port registers */
|
||||
__IM uint32_t INTR_CAUSE0; /*!< 0x00004000 Interrupt port cause register 0 */
|
||||
__IM uint32_t INTR_CAUSE1; /*!< 0x00004004 Interrupt port cause register 1 */
|
||||
__IM uint32_t INTR_CAUSE2; /*!< 0x00004008 Interrupt port cause register 2 */
|
||||
__IM uint32_t INTR_CAUSE3; /*!< 0x0000400C Interrupt port cause register 3 */
|
||||
__IM uint32_t VDD_ACTIVE; /*!< 0x00004010 Extern power supply detection register */
|
||||
__IOM uint32_t VDD_INTR; /*!< 0x00004014 Supply detection interrupt register */
|
||||
__IOM uint32_t VDD_INTR_MASK; /*!< 0x00004018 Supply detection interrupt mask register */
|
||||
__IM uint32_t VDD_INTR_MASKED; /*!< 0x0000401C Supply detection interrupt masked register */
|
||||
__IOM uint32_t VDD_INTR_SET; /*!< 0x00004020 Supply detection interrupt set register */
|
||||
} GPIO_V1_Type; /*!< Size = 16420 (0x4024) */
|
||||
|
||||
|
||||
/* GPIO_PRT.OUT */
|
||||
#define GPIO_PRT_OUT_OUT0_Pos 0UL
|
||||
#define GPIO_PRT_OUT_OUT0_Msk 0x1UL
|
||||
#define GPIO_PRT_OUT_OUT1_Pos 1UL
|
||||
#define GPIO_PRT_OUT_OUT1_Msk 0x2UL
|
||||
#define GPIO_PRT_OUT_OUT2_Pos 2UL
|
||||
#define GPIO_PRT_OUT_OUT2_Msk 0x4UL
|
||||
#define GPIO_PRT_OUT_OUT3_Pos 3UL
|
||||
#define GPIO_PRT_OUT_OUT3_Msk 0x8UL
|
||||
#define GPIO_PRT_OUT_OUT4_Pos 4UL
|
||||
#define GPIO_PRT_OUT_OUT4_Msk 0x10UL
|
||||
#define GPIO_PRT_OUT_OUT5_Pos 5UL
|
||||
#define GPIO_PRT_OUT_OUT5_Msk 0x20UL
|
||||
#define GPIO_PRT_OUT_OUT6_Pos 6UL
|
||||
#define GPIO_PRT_OUT_OUT6_Msk 0x40UL
|
||||
#define GPIO_PRT_OUT_OUT7_Pos 7UL
|
||||
#define GPIO_PRT_OUT_OUT7_Msk 0x80UL
|
||||
/* GPIO_PRT.OUT_CLR */
|
||||
#define GPIO_PRT_OUT_CLR_OUT0_Pos 0UL
|
||||
#define GPIO_PRT_OUT_CLR_OUT0_Msk 0x1UL
|
||||
#define GPIO_PRT_OUT_CLR_OUT1_Pos 1UL
|
||||
#define GPIO_PRT_OUT_CLR_OUT1_Msk 0x2UL
|
||||
#define GPIO_PRT_OUT_CLR_OUT2_Pos 2UL
|
||||
#define GPIO_PRT_OUT_CLR_OUT2_Msk 0x4UL
|
||||
#define GPIO_PRT_OUT_CLR_OUT3_Pos 3UL
|
||||
#define GPIO_PRT_OUT_CLR_OUT3_Msk 0x8UL
|
||||
#define GPIO_PRT_OUT_CLR_OUT4_Pos 4UL
|
||||
#define GPIO_PRT_OUT_CLR_OUT4_Msk 0x10UL
|
||||
#define GPIO_PRT_OUT_CLR_OUT5_Pos 5UL
|
||||
#define GPIO_PRT_OUT_CLR_OUT5_Msk 0x20UL
|
||||
#define GPIO_PRT_OUT_CLR_OUT6_Pos 6UL
|
||||
#define GPIO_PRT_OUT_CLR_OUT6_Msk 0x40UL
|
||||
#define GPIO_PRT_OUT_CLR_OUT7_Pos 7UL
|
||||
#define GPIO_PRT_OUT_CLR_OUT7_Msk 0x80UL
|
||||
/* GPIO_PRT.OUT_SET */
|
||||
#define GPIO_PRT_OUT_SET_OUT0_Pos 0UL
|
||||
#define GPIO_PRT_OUT_SET_OUT0_Msk 0x1UL
|
||||
#define GPIO_PRT_OUT_SET_OUT1_Pos 1UL
|
||||
#define GPIO_PRT_OUT_SET_OUT1_Msk 0x2UL
|
||||
#define GPIO_PRT_OUT_SET_OUT2_Pos 2UL
|
||||
#define GPIO_PRT_OUT_SET_OUT2_Msk 0x4UL
|
||||
#define GPIO_PRT_OUT_SET_OUT3_Pos 3UL
|
||||
#define GPIO_PRT_OUT_SET_OUT3_Msk 0x8UL
|
||||
#define GPIO_PRT_OUT_SET_OUT4_Pos 4UL
|
||||
#define GPIO_PRT_OUT_SET_OUT4_Msk 0x10UL
|
||||
#define GPIO_PRT_OUT_SET_OUT5_Pos 5UL
|
||||
#define GPIO_PRT_OUT_SET_OUT5_Msk 0x20UL
|
||||
#define GPIO_PRT_OUT_SET_OUT6_Pos 6UL
|
||||
#define GPIO_PRT_OUT_SET_OUT6_Msk 0x40UL
|
||||
#define GPIO_PRT_OUT_SET_OUT7_Pos 7UL
|
||||
#define GPIO_PRT_OUT_SET_OUT7_Msk 0x80UL
|
||||
/* GPIO_PRT.OUT_INV */
|
||||
#define GPIO_PRT_OUT_INV_OUT0_Pos 0UL
|
||||
#define GPIO_PRT_OUT_INV_OUT0_Msk 0x1UL
|
||||
#define GPIO_PRT_OUT_INV_OUT1_Pos 1UL
|
||||
#define GPIO_PRT_OUT_INV_OUT1_Msk 0x2UL
|
||||
#define GPIO_PRT_OUT_INV_OUT2_Pos 2UL
|
||||
#define GPIO_PRT_OUT_INV_OUT2_Msk 0x4UL
|
||||
#define GPIO_PRT_OUT_INV_OUT3_Pos 3UL
|
||||
#define GPIO_PRT_OUT_INV_OUT3_Msk 0x8UL
|
||||
#define GPIO_PRT_OUT_INV_OUT4_Pos 4UL
|
||||
#define GPIO_PRT_OUT_INV_OUT4_Msk 0x10UL
|
||||
#define GPIO_PRT_OUT_INV_OUT5_Pos 5UL
|
||||
#define GPIO_PRT_OUT_INV_OUT5_Msk 0x20UL
|
||||
#define GPIO_PRT_OUT_INV_OUT6_Pos 6UL
|
||||
#define GPIO_PRT_OUT_INV_OUT6_Msk 0x40UL
|
||||
#define GPIO_PRT_OUT_INV_OUT7_Pos 7UL
|
||||
#define GPIO_PRT_OUT_INV_OUT7_Msk 0x80UL
|
||||
/* GPIO_PRT.IN */
|
||||
#define GPIO_PRT_IN_IN0_Pos 0UL
|
||||
#define GPIO_PRT_IN_IN0_Msk 0x1UL
|
||||
#define GPIO_PRT_IN_IN1_Pos 1UL
|
||||
#define GPIO_PRT_IN_IN1_Msk 0x2UL
|
||||
#define GPIO_PRT_IN_IN2_Pos 2UL
|
||||
#define GPIO_PRT_IN_IN2_Msk 0x4UL
|
||||
#define GPIO_PRT_IN_IN3_Pos 3UL
|
||||
#define GPIO_PRT_IN_IN3_Msk 0x8UL
|
||||
#define GPIO_PRT_IN_IN4_Pos 4UL
|
||||
#define GPIO_PRT_IN_IN4_Msk 0x10UL
|
||||
#define GPIO_PRT_IN_IN5_Pos 5UL
|
||||
#define GPIO_PRT_IN_IN5_Msk 0x20UL
|
||||
#define GPIO_PRT_IN_IN6_Pos 6UL
|
||||
#define GPIO_PRT_IN_IN6_Msk 0x40UL
|
||||
#define GPIO_PRT_IN_IN7_Pos 7UL
|
||||
#define GPIO_PRT_IN_IN7_Msk 0x80UL
|
||||
#define GPIO_PRT_IN_FLT_IN_Pos 8UL
|
||||
#define GPIO_PRT_IN_FLT_IN_Msk 0x100UL
|
||||
/* GPIO_PRT.INTR */
|
||||
#define GPIO_PRT_INTR_EDGE0_Pos 0UL
|
||||
#define GPIO_PRT_INTR_EDGE0_Msk 0x1UL
|
||||
#define GPIO_PRT_INTR_EDGE1_Pos 1UL
|
||||
#define GPIO_PRT_INTR_EDGE1_Msk 0x2UL
|
||||
#define GPIO_PRT_INTR_EDGE2_Pos 2UL
|
||||
#define GPIO_PRT_INTR_EDGE2_Msk 0x4UL
|
||||
#define GPIO_PRT_INTR_EDGE3_Pos 3UL
|
||||
#define GPIO_PRT_INTR_EDGE3_Msk 0x8UL
|
||||
#define GPIO_PRT_INTR_EDGE4_Pos 4UL
|
||||
#define GPIO_PRT_INTR_EDGE4_Msk 0x10UL
|
||||
#define GPIO_PRT_INTR_EDGE5_Pos 5UL
|
||||
#define GPIO_PRT_INTR_EDGE5_Msk 0x20UL
|
||||
#define GPIO_PRT_INTR_EDGE6_Pos 6UL
|
||||
#define GPIO_PRT_INTR_EDGE6_Msk 0x40UL
|
||||
#define GPIO_PRT_INTR_EDGE7_Pos 7UL
|
||||
#define GPIO_PRT_INTR_EDGE7_Msk 0x80UL
|
||||
#define GPIO_PRT_INTR_FLT_EDGE_Pos 8UL
|
||||
#define GPIO_PRT_INTR_FLT_EDGE_Msk 0x100UL
|
||||
#define GPIO_PRT_INTR_IN_IN0_Pos 16UL
|
||||
#define GPIO_PRT_INTR_IN_IN0_Msk 0x10000UL
|
||||
#define GPIO_PRT_INTR_IN_IN1_Pos 17UL
|
||||
#define GPIO_PRT_INTR_IN_IN1_Msk 0x20000UL
|
||||
#define GPIO_PRT_INTR_IN_IN2_Pos 18UL
|
||||
#define GPIO_PRT_INTR_IN_IN2_Msk 0x40000UL
|
||||
#define GPIO_PRT_INTR_IN_IN3_Pos 19UL
|
||||
#define GPIO_PRT_INTR_IN_IN3_Msk 0x80000UL
|
||||
#define GPIO_PRT_INTR_IN_IN4_Pos 20UL
|
||||
#define GPIO_PRT_INTR_IN_IN4_Msk 0x100000UL
|
||||
#define GPIO_PRT_INTR_IN_IN5_Pos 21UL
|
||||
#define GPIO_PRT_INTR_IN_IN5_Msk 0x200000UL
|
||||
#define GPIO_PRT_INTR_IN_IN6_Pos 22UL
|
||||
#define GPIO_PRT_INTR_IN_IN6_Msk 0x400000UL
|
||||
#define GPIO_PRT_INTR_IN_IN7_Pos 23UL
|
||||
#define GPIO_PRT_INTR_IN_IN7_Msk 0x800000UL
|
||||
#define GPIO_PRT_INTR_FLT_IN_IN_Pos 24UL
|
||||
#define GPIO_PRT_INTR_FLT_IN_IN_Msk 0x1000000UL
|
||||
/* GPIO_PRT.INTR_MASK */
|
||||
#define GPIO_PRT_INTR_MASK_EDGE0_Pos 0UL
|
||||
#define GPIO_PRT_INTR_MASK_EDGE0_Msk 0x1UL
|
||||
#define GPIO_PRT_INTR_MASK_EDGE1_Pos 1UL
|
||||
#define GPIO_PRT_INTR_MASK_EDGE1_Msk 0x2UL
|
||||
#define GPIO_PRT_INTR_MASK_EDGE2_Pos 2UL
|
||||
#define GPIO_PRT_INTR_MASK_EDGE2_Msk 0x4UL
|
||||
#define GPIO_PRT_INTR_MASK_EDGE3_Pos 3UL
|
||||
#define GPIO_PRT_INTR_MASK_EDGE3_Msk 0x8UL
|
||||
#define GPIO_PRT_INTR_MASK_EDGE4_Pos 4UL
|
||||
#define GPIO_PRT_INTR_MASK_EDGE4_Msk 0x10UL
|
||||
#define GPIO_PRT_INTR_MASK_EDGE5_Pos 5UL
|
||||
#define GPIO_PRT_INTR_MASK_EDGE5_Msk 0x20UL
|
||||
#define GPIO_PRT_INTR_MASK_EDGE6_Pos 6UL
|
||||
#define GPIO_PRT_INTR_MASK_EDGE6_Msk 0x40UL
|
||||
#define GPIO_PRT_INTR_MASK_EDGE7_Pos 7UL
|
||||
#define GPIO_PRT_INTR_MASK_EDGE7_Msk 0x80UL
|
||||
#define GPIO_PRT_INTR_MASK_FLT_EDGE_Pos 8UL
|
||||
#define GPIO_PRT_INTR_MASK_FLT_EDGE_Msk 0x100UL
|
||||
/* GPIO_PRT.INTR_MASKED */
|
||||
#define GPIO_PRT_INTR_MASKED_EDGE0_Pos 0UL
|
||||
#define GPIO_PRT_INTR_MASKED_EDGE0_Msk 0x1UL
|
||||
#define GPIO_PRT_INTR_MASKED_EDGE1_Pos 1UL
|
||||
#define GPIO_PRT_INTR_MASKED_EDGE1_Msk 0x2UL
|
||||
#define GPIO_PRT_INTR_MASKED_EDGE2_Pos 2UL
|
||||
#define GPIO_PRT_INTR_MASKED_EDGE2_Msk 0x4UL
|
||||
#define GPIO_PRT_INTR_MASKED_EDGE3_Pos 3UL
|
||||
#define GPIO_PRT_INTR_MASKED_EDGE3_Msk 0x8UL
|
||||
#define GPIO_PRT_INTR_MASKED_EDGE4_Pos 4UL
|
||||
#define GPIO_PRT_INTR_MASKED_EDGE4_Msk 0x10UL
|
||||
#define GPIO_PRT_INTR_MASKED_EDGE5_Pos 5UL
|
||||
#define GPIO_PRT_INTR_MASKED_EDGE5_Msk 0x20UL
|
||||
#define GPIO_PRT_INTR_MASKED_EDGE6_Pos 6UL
|
||||
#define GPIO_PRT_INTR_MASKED_EDGE6_Msk 0x40UL
|
||||
#define GPIO_PRT_INTR_MASKED_EDGE7_Pos 7UL
|
||||
#define GPIO_PRT_INTR_MASKED_EDGE7_Msk 0x80UL
|
||||
#define GPIO_PRT_INTR_MASKED_FLT_EDGE_Pos 8UL
|
||||
#define GPIO_PRT_INTR_MASKED_FLT_EDGE_Msk 0x100UL
|
||||
/* GPIO_PRT.INTR_SET */
|
||||
#define GPIO_PRT_INTR_SET_EDGE0_Pos 0UL
|
||||
#define GPIO_PRT_INTR_SET_EDGE0_Msk 0x1UL
|
||||
#define GPIO_PRT_INTR_SET_EDGE1_Pos 1UL
|
||||
#define GPIO_PRT_INTR_SET_EDGE1_Msk 0x2UL
|
||||
#define GPIO_PRT_INTR_SET_EDGE2_Pos 2UL
|
||||
#define GPIO_PRT_INTR_SET_EDGE2_Msk 0x4UL
|
||||
#define GPIO_PRT_INTR_SET_EDGE3_Pos 3UL
|
||||
#define GPIO_PRT_INTR_SET_EDGE3_Msk 0x8UL
|
||||
#define GPIO_PRT_INTR_SET_EDGE4_Pos 4UL
|
||||
#define GPIO_PRT_INTR_SET_EDGE4_Msk 0x10UL
|
||||
#define GPIO_PRT_INTR_SET_EDGE5_Pos 5UL
|
||||
#define GPIO_PRT_INTR_SET_EDGE5_Msk 0x20UL
|
||||
#define GPIO_PRT_INTR_SET_EDGE6_Pos 6UL
|
||||
#define GPIO_PRT_INTR_SET_EDGE6_Msk 0x40UL
|
||||
#define GPIO_PRT_INTR_SET_EDGE7_Pos 7UL
|
||||
#define GPIO_PRT_INTR_SET_EDGE7_Msk 0x80UL
|
||||
#define GPIO_PRT_INTR_SET_FLT_EDGE_Pos 8UL
|
||||
#define GPIO_PRT_INTR_SET_FLT_EDGE_Msk 0x100UL
|
||||
/* GPIO_PRT.INTR_CFG */
|
||||
#define GPIO_PRT_INTR_CFG_EDGE0_SEL_Pos 0UL
|
||||
#define GPIO_PRT_INTR_CFG_EDGE0_SEL_Msk 0x3UL
|
||||
#define GPIO_PRT_INTR_CFG_EDGE1_SEL_Pos 2UL
|
||||
#define GPIO_PRT_INTR_CFG_EDGE1_SEL_Msk 0xCUL
|
||||
#define GPIO_PRT_INTR_CFG_EDGE2_SEL_Pos 4UL
|
||||
#define GPIO_PRT_INTR_CFG_EDGE2_SEL_Msk 0x30UL
|
||||
#define GPIO_PRT_INTR_CFG_EDGE3_SEL_Pos 6UL
|
||||
#define GPIO_PRT_INTR_CFG_EDGE3_SEL_Msk 0xC0UL
|
||||
#define GPIO_PRT_INTR_CFG_EDGE4_SEL_Pos 8UL
|
||||
#define GPIO_PRT_INTR_CFG_EDGE4_SEL_Msk 0x300UL
|
||||
#define GPIO_PRT_INTR_CFG_EDGE5_SEL_Pos 10UL
|
||||
#define GPIO_PRT_INTR_CFG_EDGE5_SEL_Msk 0xC00UL
|
||||
#define GPIO_PRT_INTR_CFG_EDGE6_SEL_Pos 12UL
|
||||
#define GPIO_PRT_INTR_CFG_EDGE6_SEL_Msk 0x3000UL
|
||||
#define GPIO_PRT_INTR_CFG_EDGE7_SEL_Pos 14UL
|
||||
#define GPIO_PRT_INTR_CFG_EDGE7_SEL_Msk 0xC000UL
|
||||
#define GPIO_PRT_INTR_CFG_FLT_EDGE_SEL_Pos 16UL
|
||||
#define GPIO_PRT_INTR_CFG_FLT_EDGE_SEL_Msk 0x30000UL
|
||||
#define GPIO_PRT_INTR_CFG_FLT_SEL_Pos 18UL
|
||||
#define GPIO_PRT_INTR_CFG_FLT_SEL_Msk 0x1C0000UL
|
||||
/* GPIO_PRT.CFG */
|
||||
#define GPIO_PRT_CFG_DRIVE_MODE0_Pos 0UL
|
||||
#define GPIO_PRT_CFG_DRIVE_MODE0_Msk 0x7UL
|
||||
#define GPIO_PRT_CFG_IN_EN0_Pos 3UL
|
||||
#define GPIO_PRT_CFG_IN_EN0_Msk 0x8UL
|
||||
#define GPIO_PRT_CFG_DRIVE_MODE1_Pos 4UL
|
||||
#define GPIO_PRT_CFG_DRIVE_MODE1_Msk 0x70UL
|
||||
#define GPIO_PRT_CFG_IN_EN1_Pos 7UL
|
||||
#define GPIO_PRT_CFG_IN_EN1_Msk 0x80UL
|
||||
#define GPIO_PRT_CFG_DRIVE_MODE2_Pos 8UL
|
||||
#define GPIO_PRT_CFG_DRIVE_MODE2_Msk 0x700UL
|
||||
#define GPIO_PRT_CFG_IN_EN2_Pos 11UL
|
||||
#define GPIO_PRT_CFG_IN_EN2_Msk 0x800UL
|
||||
#define GPIO_PRT_CFG_DRIVE_MODE3_Pos 12UL
|
||||
#define GPIO_PRT_CFG_DRIVE_MODE3_Msk 0x7000UL
|
||||
#define GPIO_PRT_CFG_IN_EN3_Pos 15UL
|
||||
#define GPIO_PRT_CFG_IN_EN3_Msk 0x8000UL
|
||||
#define GPIO_PRT_CFG_DRIVE_MODE4_Pos 16UL
|
||||
#define GPIO_PRT_CFG_DRIVE_MODE4_Msk 0x70000UL
|
||||
#define GPIO_PRT_CFG_IN_EN4_Pos 19UL
|
||||
#define GPIO_PRT_CFG_IN_EN4_Msk 0x80000UL
|
||||
#define GPIO_PRT_CFG_DRIVE_MODE5_Pos 20UL
|
||||
#define GPIO_PRT_CFG_DRIVE_MODE5_Msk 0x700000UL
|
||||
#define GPIO_PRT_CFG_IN_EN5_Pos 23UL
|
||||
#define GPIO_PRT_CFG_IN_EN5_Msk 0x800000UL
|
||||
#define GPIO_PRT_CFG_DRIVE_MODE6_Pos 24UL
|
||||
#define GPIO_PRT_CFG_DRIVE_MODE6_Msk 0x7000000UL
|
||||
#define GPIO_PRT_CFG_IN_EN6_Pos 27UL
|
||||
#define GPIO_PRT_CFG_IN_EN6_Msk 0x8000000UL
|
||||
#define GPIO_PRT_CFG_DRIVE_MODE7_Pos 28UL
|
||||
#define GPIO_PRT_CFG_DRIVE_MODE7_Msk 0x70000000UL
|
||||
#define GPIO_PRT_CFG_IN_EN7_Pos 31UL
|
||||
#define GPIO_PRT_CFG_IN_EN7_Msk 0x80000000UL
|
||||
/* GPIO_PRT.CFG_IN */
|
||||
#define GPIO_PRT_CFG_IN_VTRIP_SEL0_0_Pos 0UL
|
||||
#define GPIO_PRT_CFG_IN_VTRIP_SEL0_0_Msk 0x1UL
|
||||
#define GPIO_PRT_CFG_IN_VTRIP_SEL1_0_Pos 1UL
|
||||
#define GPIO_PRT_CFG_IN_VTRIP_SEL1_0_Msk 0x2UL
|
||||
#define GPIO_PRT_CFG_IN_VTRIP_SEL2_0_Pos 2UL
|
||||
#define GPIO_PRT_CFG_IN_VTRIP_SEL2_0_Msk 0x4UL
|
||||
#define GPIO_PRT_CFG_IN_VTRIP_SEL3_0_Pos 3UL
|
||||
#define GPIO_PRT_CFG_IN_VTRIP_SEL3_0_Msk 0x8UL
|
||||
#define GPIO_PRT_CFG_IN_VTRIP_SEL4_0_Pos 4UL
|
||||
#define GPIO_PRT_CFG_IN_VTRIP_SEL4_0_Msk 0x10UL
|
||||
#define GPIO_PRT_CFG_IN_VTRIP_SEL5_0_Pos 5UL
|
||||
#define GPIO_PRT_CFG_IN_VTRIP_SEL5_0_Msk 0x20UL
|
||||
#define GPIO_PRT_CFG_IN_VTRIP_SEL6_0_Pos 6UL
|
||||
#define GPIO_PRT_CFG_IN_VTRIP_SEL6_0_Msk 0x40UL
|
||||
#define GPIO_PRT_CFG_IN_VTRIP_SEL7_0_Pos 7UL
|
||||
#define GPIO_PRT_CFG_IN_VTRIP_SEL7_0_Msk 0x80UL
|
||||
/* GPIO_PRT.CFG_OUT */
|
||||
#define GPIO_PRT_CFG_OUT_SLOW0_Pos 0UL
|
||||
#define GPIO_PRT_CFG_OUT_SLOW0_Msk 0x1UL
|
||||
#define GPIO_PRT_CFG_OUT_SLOW1_Pos 1UL
|
||||
#define GPIO_PRT_CFG_OUT_SLOW1_Msk 0x2UL
|
||||
#define GPIO_PRT_CFG_OUT_SLOW2_Pos 2UL
|
||||
#define GPIO_PRT_CFG_OUT_SLOW2_Msk 0x4UL
|
||||
#define GPIO_PRT_CFG_OUT_SLOW3_Pos 3UL
|
||||
#define GPIO_PRT_CFG_OUT_SLOW3_Msk 0x8UL
|
||||
#define GPIO_PRT_CFG_OUT_SLOW4_Pos 4UL
|
||||
#define GPIO_PRT_CFG_OUT_SLOW4_Msk 0x10UL
|
||||
#define GPIO_PRT_CFG_OUT_SLOW5_Pos 5UL
|
||||
#define GPIO_PRT_CFG_OUT_SLOW5_Msk 0x20UL
|
||||
#define GPIO_PRT_CFG_OUT_SLOW6_Pos 6UL
|
||||
#define GPIO_PRT_CFG_OUT_SLOW6_Msk 0x40UL
|
||||
#define GPIO_PRT_CFG_OUT_SLOW7_Pos 7UL
|
||||
#define GPIO_PRT_CFG_OUT_SLOW7_Msk 0x80UL
|
||||
#define GPIO_PRT_CFG_OUT_DRIVE_SEL0_Pos 16UL
|
||||
#define GPIO_PRT_CFG_OUT_DRIVE_SEL0_Msk 0x30000UL
|
||||
#define GPIO_PRT_CFG_OUT_DRIVE_SEL1_Pos 18UL
|
||||
#define GPIO_PRT_CFG_OUT_DRIVE_SEL1_Msk 0xC0000UL
|
||||
#define GPIO_PRT_CFG_OUT_DRIVE_SEL2_Pos 20UL
|
||||
#define GPIO_PRT_CFG_OUT_DRIVE_SEL2_Msk 0x300000UL
|
||||
#define GPIO_PRT_CFG_OUT_DRIVE_SEL3_Pos 22UL
|
||||
#define GPIO_PRT_CFG_OUT_DRIVE_SEL3_Msk 0xC00000UL
|
||||
#define GPIO_PRT_CFG_OUT_DRIVE_SEL4_Pos 24UL
|
||||
#define GPIO_PRT_CFG_OUT_DRIVE_SEL4_Msk 0x3000000UL
|
||||
#define GPIO_PRT_CFG_OUT_DRIVE_SEL5_Pos 26UL
|
||||
#define GPIO_PRT_CFG_OUT_DRIVE_SEL5_Msk 0xC000000UL
|
||||
#define GPIO_PRT_CFG_OUT_DRIVE_SEL6_Pos 28UL
|
||||
#define GPIO_PRT_CFG_OUT_DRIVE_SEL6_Msk 0x30000000UL
|
||||
#define GPIO_PRT_CFG_OUT_DRIVE_SEL7_Pos 30UL
|
||||
#define GPIO_PRT_CFG_OUT_DRIVE_SEL7_Msk 0xC0000000UL
|
||||
/* GPIO_PRT.CFG_SIO */
|
||||
#define GPIO_PRT_CFG_SIO_VREG_EN01_Pos 0UL
|
||||
#define GPIO_PRT_CFG_SIO_VREG_EN01_Msk 0x1UL
|
||||
#define GPIO_PRT_CFG_SIO_IBUF_SEL01_Pos 1UL
|
||||
#define GPIO_PRT_CFG_SIO_IBUF_SEL01_Msk 0x2UL
|
||||
#define GPIO_PRT_CFG_SIO_VTRIP_SEL01_Pos 2UL
|
||||
#define GPIO_PRT_CFG_SIO_VTRIP_SEL01_Msk 0x4UL
|
||||
#define GPIO_PRT_CFG_SIO_VREF_SEL01_Pos 3UL
|
||||
#define GPIO_PRT_CFG_SIO_VREF_SEL01_Msk 0x18UL
|
||||
#define GPIO_PRT_CFG_SIO_VOH_SEL01_Pos 5UL
|
||||
#define GPIO_PRT_CFG_SIO_VOH_SEL01_Msk 0xE0UL
|
||||
#define GPIO_PRT_CFG_SIO_VREG_EN23_Pos 8UL
|
||||
#define GPIO_PRT_CFG_SIO_VREG_EN23_Msk 0x100UL
|
||||
#define GPIO_PRT_CFG_SIO_IBUF_SEL23_Pos 9UL
|
||||
#define GPIO_PRT_CFG_SIO_IBUF_SEL23_Msk 0x200UL
|
||||
#define GPIO_PRT_CFG_SIO_VTRIP_SEL23_Pos 10UL
|
||||
#define GPIO_PRT_CFG_SIO_VTRIP_SEL23_Msk 0x400UL
|
||||
#define GPIO_PRT_CFG_SIO_VREF_SEL23_Pos 11UL
|
||||
#define GPIO_PRT_CFG_SIO_VREF_SEL23_Msk 0x1800UL
|
||||
#define GPIO_PRT_CFG_SIO_VOH_SEL23_Pos 13UL
|
||||
#define GPIO_PRT_CFG_SIO_VOH_SEL23_Msk 0xE000UL
|
||||
#define GPIO_PRT_CFG_SIO_VREG_EN45_Pos 16UL
|
||||
#define GPIO_PRT_CFG_SIO_VREG_EN45_Msk 0x10000UL
|
||||
#define GPIO_PRT_CFG_SIO_IBUF_SEL45_Pos 17UL
|
||||
#define GPIO_PRT_CFG_SIO_IBUF_SEL45_Msk 0x20000UL
|
||||
#define GPIO_PRT_CFG_SIO_VTRIP_SEL45_Pos 18UL
|
||||
#define GPIO_PRT_CFG_SIO_VTRIP_SEL45_Msk 0x40000UL
|
||||
#define GPIO_PRT_CFG_SIO_VREF_SEL45_Pos 19UL
|
||||
#define GPIO_PRT_CFG_SIO_VREF_SEL45_Msk 0x180000UL
|
||||
#define GPIO_PRT_CFG_SIO_VOH_SEL45_Pos 21UL
|
||||
#define GPIO_PRT_CFG_SIO_VOH_SEL45_Msk 0xE00000UL
|
||||
#define GPIO_PRT_CFG_SIO_VREG_EN67_Pos 24UL
|
||||
#define GPIO_PRT_CFG_SIO_VREG_EN67_Msk 0x1000000UL
|
||||
#define GPIO_PRT_CFG_SIO_IBUF_SEL67_Pos 25UL
|
||||
#define GPIO_PRT_CFG_SIO_IBUF_SEL67_Msk 0x2000000UL
|
||||
#define GPIO_PRT_CFG_SIO_VTRIP_SEL67_Pos 26UL
|
||||
#define GPIO_PRT_CFG_SIO_VTRIP_SEL67_Msk 0x4000000UL
|
||||
#define GPIO_PRT_CFG_SIO_VREF_SEL67_Pos 27UL
|
||||
#define GPIO_PRT_CFG_SIO_VREF_SEL67_Msk 0x18000000UL
|
||||
#define GPIO_PRT_CFG_SIO_VOH_SEL67_Pos 29UL
|
||||
#define GPIO_PRT_CFG_SIO_VOH_SEL67_Msk 0xE0000000UL
|
||||
/* GPIO_PRT.CFG_IN_GPIO5V */
|
||||
#define GPIO_PRT_CFG_IN_GPIO5V_VTRIP_SEL0_1_Pos 0UL
|
||||
#define GPIO_PRT_CFG_IN_GPIO5V_VTRIP_SEL0_1_Msk 0x1UL
|
||||
#define GPIO_PRT_CFG_IN_GPIO5V_VTRIP_SEL1_1_Pos 1UL
|
||||
#define GPIO_PRT_CFG_IN_GPIO5V_VTRIP_SEL1_1_Msk 0x2UL
|
||||
#define GPIO_PRT_CFG_IN_GPIO5V_VTRIP_SEL2_1_Pos 2UL
|
||||
#define GPIO_PRT_CFG_IN_GPIO5V_VTRIP_SEL2_1_Msk 0x4UL
|
||||
#define GPIO_PRT_CFG_IN_GPIO5V_VTRIP_SEL3_1_Pos 3UL
|
||||
#define GPIO_PRT_CFG_IN_GPIO5V_VTRIP_SEL3_1_Msk 0x8UL
|
||||
#define GPIO_PRT_CFG_IN_GPIO5V_VTRIP_SEL4_1_Pos 4UL
|
||||
#define GPIO_PRT_CFG_IN_GPIO5V_VTRIP_SEL4_1_Msk 0x10UL
|
||||
#define GPIO_PRT_CFG_IN_GPIO5V_VTRIP_SEL5_1_Pos 5UL
|
||||
#define GPIO_PRT_CFG_IN_GPIO5V_VTRIP_SEL5_1_Msk 0x20UL
|
||||
#define GPIO_PRT_CFG_IN_GPIO5V_VTRIP_SEL6_1_Pos 6UL
|
||||
#define GPIO_PRT_CFG_IN_GPIO5V_VTRIP_SEL6_1_Msk 0x40UL
|
||||
#define GPIO_PRT_CFG_IN_GPIO5V_VTRIP_SEL7_1_Pos 7UL
|
||||
#define GPIO_PRT_CFG_IN_GPIO5V_VTRIP_SEL7_1_Msk 0x80UL
|
||||
|
||||
|
||||
/* GPIO.INTR_CAUSE0 */
|
||||
#define GPIO_INTR_CAUSE0_PORT_INT_Pos 0UL
|
||||
#define GPIO_INTR_CAUSE0_PORT_INT_Msk 0xFFFFFFFFUL
|
||||
/* GPIO.INTR_CAUSE1 */
|
||||
#define GPIO_INTR_CAUSE1_PORT_INT_Pos 0UL
|
||||
#define GPIO_INTR_CAUSE1_PORT_INT_Msk 0xFFFFFFFFUL
|
||||
/* GPIO.INTR_CAUSE2 */
|
||||
#define GPIO_INTR_CAUSE2_PORT_INT_Pos 0UL
|
||||
#define GPIO_INTR_CAUSE2_PORT_INT_Msk 0xFFFFFFFFUL
|
||||
/* GPIO.INTR_CAUSE3 */
|
||||
#define GPIO_INTR_CAUSE3_PORT_INT_Pos 0UL
|
||||
#define GPIO_INTR_CAUSE3_PORT_INT_Msk 0xFFFFFFFFUL
|
||||
/* GPIO.VDD_ACTIVE */
|
||||
#define GPIO_VDD_ACTIVE_VDDIO_ACTIVE_Pos 0UL
|
||||
#define GPIO_VDD_ACTIVE_VDDIO_ACTIVE_Msk 0xFFFFUL
|
||||
#define GPIO_VDD_ACTIVE_VDDA_ACTIVE_Pos 30UL
|
||||
#define GPIO_VDD_ACTIVE_VDDA_ACTIVE_Msk 0x40000000UL
|
||||
#define GPIO_VDD_ACTIVE_VDDD_ACTIVE_Pos 31UL
|
||||
#define GPIO_VDD_ACTIVE_VDDD_ACTIVE_Msk 0x80000000UL
|
||||
/* GPIO.VDD_INTR */
|
||||
#define GPIO_VDD_INTR_VDDIO_ACTIVE_Pos 0UL
|
||||
#define GPIO_VDD_INTR_VDDIO_ACTIVE_Msk 0xFFFFUL
|
||||
#define GPIO_VDD_INTR_VDDA_ACTIVE_Pos 30UL
|
||||
#define GPIO_VDD_INTR_VDDA_ACTIVE_Msk 0x40000000UL
|
||||
#define GPIO_VDD_INTR_VDDD_ACTIVE_Pos 31UL
|
||||
#define GPIO_VDD_INTR_VDDD_ACTIVE_Msk 0x80000000UL
|
||||
/* GPIO.VDD_INTR_MASK */
|
||||
#define GPIO_VDD_INTR_MASK_VDDIO_ACTIVE_Pos 0UL
|
||||
#define GPIO_VDD_INTR_MASK_VDDIO_ACTIVE_Msk 0xFFFFUL
|
||||
#define GPIO_VDD_INTR_MASK_VDDA_ACTIVE_Pos 30UL
|
||||
#define GPIO_VDD_INTR_MASK_VDDA_ACTIVE_Msk 0x40000000UL
|
||||
#define GPIO_VDD_INTR_MASK_VDDD_ACTIVE_Pos 31UL
|
||||
#define GPIO_VDD_INTR_MASK_VDDD_ACTIVE_Msk 0x80000000UL
|
||||
/* GPIO.VDD_INTR_MASKED */
|
||||
#define GPIO_VDD_INTR_MASKED_VDDIO_ACTIVE_Pos 0UL
|
||||
#define GPIO_VDD_INTR_MASKED_VDDIO_ACTIVE_Msk 0xFFFFUL
|
||||
#define GPIO_VDD_INTR_MASKED_VDDA_ACTIVE_Pos 30UL
|
||||
#define GPIO_VDD_INTR_MASKED_VDDA_ACTIVE_Msk 0x40000000UL
|
||||
#define GPIO_VDD_INTR_MASKED_VDDD_ACTIVE_Pos 31UL
|
||||
#define GPIO_VDD_INTR_MASKED_VDDD_ACTIVE_Msk 0x80000000UL
|
||||
/* GPIO.VDD_INTR_SET */
|
||||
#define GPIO_VDD_INTR_SET_VDDIO_ACTIVE_Pos 0UL
|
||||
#define GPIO_VDD_INTR_SET_VDDIO_ACTIVE_Msk 0xFFFFUL
|
||||
#define GPIO_VDD_INTR_SET_VDDA_ACTIVE_Pos 30UL
|
||||
#define GPIO_VDD_INTR_SET_VDDA_ACTIVE_Msk 0x40000000UL
|
||||
#define GPIO_VDD_INTR_SET_VDDD_ACTIVE_Pos 31UL
|
||||
#define GPIO_VDD_INTR_SET_VDDD_ACTIVE_Msk 0x80000000UL
|
||||
|
||||
|
||||
#endif /* _CYIP_GPIO_H_ */
|
||||
|
||||
|
||||
/* [] END OF FILE */
|
||||
|
|
@ -1,470 +0,0 @@
|
|||
/***************************************************************************//**
|
||||
* \file cyip_gpio_v2.h
|
||||
*
|
||||
* \brief
|
||||
* GPIO IP definitions
|
||||
*
|
||||
* \note
|
||||
* Generator version: 1.3.0.1146
|
||||
* Database revision: rev#1050929
|
||||
*
|
||||
********************************************************************************
|
||||
* \copyright
|
||||
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
|
||||
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _CYIP_GPIO_V2_H_
|
||||
#define _CYIP_GPIO_V2_H_
|
||||
|
||||
#include "cyip_headers.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* GPIO
|
||||
*******************************************************************************/
|
||||
|
||||
#define GPIO_PRT_V2_SECTION_SIZE 0x00000080UL
|
||||
#define GPIO_V2_SECTION_SIZE 0x00010000UL
|
||||
|
||||
/**
|
||||
* \brief GPIO port registers (GPIO_PRT)
|
||||
*/
|
||||
typedef struct {
|
||||
__IOM uint32_t OUT; /*!< 0x00000000 Port output data register */
|
||||
__IOM uint32_t OUT_CLR; /*!< 0x00000004 Port output data set register */
|
||||
__IOM uint32_t OUT_SET; /*!< 0x00000008 Port output data clear register */
|
||||
__IOM uint32_t OUT_INV; /*!< 0x0000000C Port output data invert register */
|
||||
__IM uint32_t IN; /*!< 0x00000010 Port input state register */
|
||||
__IOM uint32_t INTR; /*!< 0x00000014 Port interrupt status register */
|
||||
__IOM uint32_t INTR_MASK; /*!< 0x00000018 Port interrupt mask register */
|
||||
__IM uint32_t INTR_MASKED; /*!< 0x0000001C Port interrupt masked status register */
|
||||
__IOM uint32_t INTR_SET; /*!< 0x00000020 Port interrupt set register */
|
||||
__IM uint32_t RESERVED[7];
|
||||
__IOM uint32_t INTR_CFG; /*!< 0x00000040 Port interrupt configuration register */
|
||||
__IOM uint32_t CFG; /*!< 0x00000044 Port configuration register */
|
||||
__IOM uint32_t CFG_IN; /*!< 0x00000048 Port input buffer configuration register */
|
||||
__IOM uint32_t CFG_OUT; /*!< 0x0000004C Port output buffer configuration register */
|
||||
__IOM uint32_t CFG_SIO; /*!< 0x00000050 Port SIO configuration register */
|
||||
__IM uint32_t RESERVED1;
|
||||
__IOM uint32_t CFG_IN_AUTOLVL; /*!< 0x00000058 Port GPIO5V input buffer configuration register */
|
||||
__IM uint32_t RESERVED2[9];
|
||||
} GPIO_PRT_V2_Type; /*!< Size = 128 (0x80) */
|
||||
|
||||
/**
|
||||
* \brief GPIO port control/configuration (GPIO)
|
||||
*/
|
||||
typedef struct {
|
||||
GPIO_PRT_V2_Type PRT[128]; /*!< 0x00000000 GPIO port registers */
|
||||
__IM uint32_t INTR_CAUSE0; /*!< 0x00004000 Interrupt port cause register 0 */
|
||||
__IM uint32_t INTR_CAUSE1; /*!< 0x00004004 Interrupt port cause register 1 */
|
||||
__IM uint32_t INTR_CAUSE2; /*!< 0x00004008 Interrupt port cause register 2 */
|
||||
__IM uint32_t INTR_CAUSE3; /*!< 0x0000400C Interrupt port cause register 3 */
|
||||
__IM uint32_t VDD_ACTIVE; /*!< 0x00004010 Extern power supply detection register */
|
||||
__IOM uint32_t VDD_INTR; /*!< 0x00004014 Supply detection interrupt register */
|
||||
__IOM uint32_t VDD_INTR_MASK; /*!< 0x00004018 Supply detection interrupt mask register */
|
||||
__IM uint32_t VDD_INTR_MASKED; /*!< 0x0000401C Supply detection interrupt masked register */
|
||||
__IOM uint32_t VDD_INTR_SET; /*!< 0x00004020 Supply detection interrupt set register */
|
||||
} GPIO_V2_Type; /*!< Size = 16420 (0x4024) */
|
||||
|
||||
|
||||
/* GPIO_PRT.OUT */
|
||||
#define GPIO_PRT_V2_OUT_OUT0_Pos 0UL
|
||||
#define GPIO_PRT_V2_OUT_OUT0_Msk 0x1UL
|
||||
#define GPIO_PRT_V2_OUT_OUT1_Pos 1UL
|
||||
#define GPIO_PRT_V2_OUT_OUT1_Msk 0x2UL
|
||||
#define GPIO_PRT_V2_OUT_OUT2_Pos 2UL
|
||||
#define GPIO_PRT_V2_OUT_OUT2_Msk 0x4UL
|
||||
#define GPIO_PRT_V2_OUT_OUT3_Pos 3UL
|
||||
#define GPIO_PRT_V2_OUT_OUT3_Msk 0x8UL
|
||||
#define GPIO_PRT_V2_OUT_OUT4_Pos 4UL
|
||||
#define GPIO_PRT_V2_OUT_OUT4_Msk 0x10UL
|
||||
#define GPIO_PRT_V2_OUT_OUT5_Pos 5UL
|
||||
#define GPIO_PRT_V2_OUT_OUT5_Msk 0x20UL
|
||||
#define GPIO_PRT_V2_OUT_OUT6_Pos 6UL
|
||||
#define GPIO_PRT_V2_OUT_OUT6_Msk 0x40UL
|
||||
#define GPIO_PRT_V2_OUT_OUT7_Pos 7UL
|
||||
#define GPIO_PRT_V2_OUT_OUT7_Msk 0x80UL
|
||||
/* GPIO_PRT.OUT_CLR */
|
||||
#define GPIO_PRT_V2_OUT_CLR_OUT0_Pos 0UL
|
||||
#define GPIO_PRT_V2_OUT_CLR_OUT0_Msk 0x1UL
|
||||
#define GPIO_PRT_V2_OUT_CLR_OUT1_Pos 1UL
|
||||
#define GPIO_PRT_V2_OUT_CLR_OUT1_Msk 0x2UL
|
||||
#define GPIO_PRT_V2_OUT_CLR_OUT2_Pos 2UL
|
||||
#define GPIO_PRT_V2_OUT_CLR_OUT2_Msk 0x4UL
|
||||
#define GPIO_PRT_V2_OUT_CLR_OUT3_Pos 3UL
|
||||
#define GPIO_PRT_V2_OUT_CLR_OUT3_Msk 0x8UL
|
||||
#define GPIO_PRT_V2_OUT_CLR_OUT4_Pos 4UL
|
||||
#define GPIO_PRT_V2_OUT_CLR_OUT4_Msk 0x10UL
|
||||
#define GPIO_PRT_V2_OUT_CLR_OUT5_Pos 5UL
|
||||
#define GPIO_PRT_V2_OUT_CLR_OUT5_Msk 0x20UL
|
||||
#define GPIO_PRT_V2_OUT_CLR_OUT6_Pos 6UL
|
||||
#define GPIO_PRT_V2_OUT_CLR_OUT6_Msk 0x40UL
|
||||
#define GPIO_PRT_V2_OUT_CLR_OUT7_Pos 7UL
|
||||
#define GPIO_PRT_V2_OUT_CLR_OUT7_Msk 0x80UL
|
||||
/* GPIO_PRT.OUT_SET */
|
||||
#define GPIO_PRT_V2_OUT_SET_OUT0_Pos 0UL
|
||||
#define GPIO_PRT_V2_OUT_SET_OUT0_Msk 0x1UL
|
||||
#define GPIO_PRT_V2_OUT_SET_OUT1_Pos 1UL
|
||||
#define GPIO_PRT_V2_OUT_SET_OUT1_Msk 0x2UL
|
||||
#define GPIO_PRT_V2_OUT_SET_OUT2_Pos 2UL
|
||||
#define GPIO_PRT_V2_OUT_SET_OUT2_Msk 0x4UL
|
||||
#define GPIO_PRT_V2_OUT_SET_OUT3_Pos 3UL
|
||||
#define GPIO_PRT_V2_OUT_SET_OUT3_Msk 0x8UL
|
||||
#define GPIO_PRT_V2_OUT_SET_OUT4_Pos 4UL
|
||||
#define GPIO_PRT_V2_OUT_SET_OUT4_Msk 0x10UL
|
||||
#define GPIO_PRT_V2_OUT_SET_OUT5_Pos 5UL
|
||||
#define GPIO_PRT_V2_OUT_SET_OUT5_Msk 0x20UL
|
||||
#define GPIO_PRT_V2_OUT_SET_OUT6_Pos 6UL
|
||||
#define GPIO_PRT_V2_OUT_SET_OUT6_Msk 0x40UL
|
||||
#define GPIO_PRT_V2_OUT_SET_OUT7_Pos 7UL
|
||||
#define GPIO_PRT_V2_OUT_SET_OUT7_Msk 0x80UL
|
||||
/* GPIO_PRT.OUT_INV */
|
||||
#define GPIO_PRT_V2_OUT_INV_OUT0_Pos 0UL
|
||||
#define GPIO_PRT_V2_OUT_INV_OUT0_Msk 0x1UL
|
||||
#define GPIO_PRT_V2_OUT_INV_OUT1_Pos 1UL
|
||||
#define GPIO_PRT_V2_OUT_INV_OUT1_Msk 0x2UL
|
||||
#define GPIO_PRT_V2_OUT_INV_OUT2_Pos 2UL
|
||||
#define GPIO_PRT_V2_OUT_INV_OUT2_Msk 0x4UL
|
||||
#define GPIO_PRT_V2_OUT_INV_OUT3_Pos 3UL
|
||||
#define GPIO_PRT_V2_OUT_INV_OUT3_Msk 0x8UL
|
||||
#define GPIO_PRT_V2_OUT_INV_OUT4_Pos 4UL
|
||||
#define GPIO_PRT_V2_OUT_INV_OUT4_Msk 0x10UL
|
||||
#define GPIO_PRT_V2_OUT_INV_OUT5_Pos 5UL
|
||||
#define GPIO_PRT_V2_OUT_INV_OUT5_Msk 0x20UL
|
||||
#define GPIO_PRT_V2_OUT_INV_OUT6_Pos 6UL
|
||||
#define GPIO_PRT_V2_OUT_INV_OUT6_Msk 0x40UL
|
||||
#define GPIO_PRT_V2_OUT_INV_OUT7_Pos 7UL
|
||||
#define GPIO_PRT_V2_OUT_INV_OUT7_Msk 0x80UL
|
||||
/* GPIO_PRT.IN */
|
||||
#define GPIO_PRT_V2_IN_IN0_Pos 0UL
|
||||
#define GPIO_PRT_V2_IN_IN0_Msk 0x1UL
|
||||
#define GPIO_PRT_V2_IN_IN1_Pos 1UL
|
||||
#define GPIO_PRT_V2_IN_IN1_Msk 0x2UL
|
||||
#define GPIO_PRT_V2_IN_IN2_Pos 2UL
|
||||
#define GPIO_PRT_V2_IN_IN2_Msk 0x4UL
|
||||
#define GPIO_PRT_V2_IN_IN3_Pos 3UL
|
||||
#define GPIO_PRT_V2_IN_IN3_Msk 0x8UL
|
||||
#define GPIO_PRT_V2_IN_IN4_Pos 4UL
|
||||
#define GPIO_PRT_V2_IN_IN4_Msk 0x10UL
|
||||
#define GPIO_PRT_V2_IN_IN5_Pos 5UL
|
||||
#define GPIO_PRT_V2_IN_IN5_Msk 0x20UL
|
||||
#define GPIO_PRT_V2_IN_IN6_Pos 6UL
|
||||
#define GPIO_PRT_V2_IN_IN6_Msk 0x40UL
|
||||
#define GPIO_PRT_V2_IN_IN7_Pos 7UL
|
||||
#define GPIO_PRT_V2_IN_IN7_Msk 0x80UL
|
||||
#define GPIO_PRT_V2_IN_FLT_IN_Pos 8UL
|
||||
#define GPIO_PRT_V2_IN_FLT_IN_Msk 0x100UL
|
||||
/* GPIO_PRT.INTR */
|
||||
#define GPIO_PRT_V2_INTR_EDGE0_Pos 0UL
|
||||
#define GPIO_PRT_V2_INTR_EDGE0_Msk 0x1UL
|
||||
#define GPIO_PRT_V2_INTR_EDGE1_Pos 1UL
|
||||
#define GPIO_PRT_V2_INTR_EDGE1_Msk 0x2UL
|
||||
#define GPIO_PRT_V2_INTR_EDGE2_Pos 2UL
|
||||
#define GPIO_PRT_V2_INTR_EDGE2_Msk 0x4UL
|
||||
#define GPIO_PRT_V2_INTR_EDGE3_Pos 3UL
|
||||
#define GPIO_PRT_V2_INTR_EDGE3_Msk 0x8UL
|
||||
#define GPIO_PRT_V2_INTR_EDGE4_Pos 4UL
|
||||
#define GPIO_PRT_V2_INTR_EDGE4_Msk 0x10UL
|
||||
#define GPIO_PRT_V2_INTR_EDGE5_Pos 5UL
|
||||
#define GPIO_PRT_V2_INTR_EDGE5_Msk 0x20UL
|
||||
#define GPIO_PRT_V2_INTR_EDGE6_Pos 6UL
|
||||
#define GPIO_PRT_V2_INTR_EDGE6_Msk 0x40UL
|
||||
#define GPIO_PRT_V2_INTR_EDGE7_Pos 7UL
|
||||
#define GPIO_PRT_V2_INTR_EDGE7_Msk 0x80UL
|
||||
#define GPIO_PRT_V2_INTR_FLT_EDGE_Pos 8UL
|
||||
#define GPIO_PRT_V2_INTR_FLT_EDGE_Msk 0x100UL
|
||||
#define GPIO_PRT_V2_INTR_IN_IN0_Pos 16UL
|
||||
#define GPIO_PRT_V2_INTR_IN_IN0_Msk 0x10000UL
|
||||
#define GPIO_PRT_V2_INTR_IN_IN1_Pos 17UL
|
||||
#define GPIO_PRT_V2_INTR_IN_IN1_Msk 0x20000UL
|
||||
#define GPIO_PRT_V2_INTR_IN_IN2_Pos 18UL
|
||||
#define GPIO_PRT_V2_INTR_IN_IN2_Msk 0x40000UL
|
||||
#define GPIO_PRT_V2_INTR_IN_IN3_Pos 19UL
|
||||
#define GPIO_PRT_V2_INTR_IN_IN3_Msk 0x80000UL
|
||||
#define GPIO_PRT_V2_INTR_IN_IN4_Pos 20UL
|
||||
#define GPIO_PRT_V2_INTR_IN_IN4_Msk 0x100000UL
|
||||
#define GPIO_PRT_V2_INTR_IN_IN5_Pos 21UL
|
||||
#define GPIO_PRT_V2_INTR_IN_IN5_Msk 0x200000UL
|
||||
#define GPIO_PRT_V2_INTR_IN_IN6_Pos 22UL
|
||||
#define GPIO_PRT_V2_INTR_IN_IN6_Msk 0x400000UL
|
||||
#define GPIO_PRT_V2_INTR_IN_IN7_Pos 23UL
|
||||
#define GPIO_PRT_V2_INTR_IN_IN7_Msk 0x800000UL
|
||||
#define GPIO_PRT_V2_INTR_FLT_IN_IN_Pos 24UL
|
||||
#define GPIO_PRT_V2_INTR_FLT_IN_IN_Msk 0x1000000UL
|
||||
/* GPIO_PRT.INTR_MASK */
|
||||
#define GPIO_PRT_V2_INTR_MASK_EDGE0_Pos 0UL
|
||||
#define GPIO_PRT_V2_INTR_MASK_EDGE0_Msk 0x1UL
|
||||
#define GPIO_PRT_V2_INTR_MASK_EDGE1_Pos 1UL
|
||||
#define GPIO_PRT_V2_INTR_MASK_EDGE1_Msk 0x2UL
|
||||
#define GPIO_PRT_V2_INTR_MASK_EDGE2_Pos 2UL
|
||||
#define GPIO_PRT_V2_INTR_MASK_EDGE2_Msk 0x4UL
|
||||
#define GPIO_PRT_V2_INTR_MASK_EDGE3_Pos 3UL
|
||||
#define GPIO_PRT_V2_INTR_MASK_EDGE3_Msk 0x8UL
|
||||
#define GPIO_PRT_V2_INTR_MASK_EDGE4_Pos 4UL
|
||||
#define GPIO_PRT_V2_INTR_MASK_EDGE4_Msk 0x10UL
|
||||
#define GPIO_PRT_V2_INTR_MASK_EDGE5_Pos 5UL
|
||||
#define GPIO_PRT_V2_INTR_MASK_EDGE5_Msk 0x20UL
|
||||
#define GPIO_PRT_V2_INTR_MASK_EDGE6_Pos 6UL
|
||||
#define GPIO_PRT_V2_INTR_MASK_EDGE6_Msk 0x40UL
|
||||
#define GPIO_PRT_V2_INTR_MASK_EDGE7_Pos 7UL
|
||||
#define GPIO_PRT_V2_INTR_MASK_EDGE7_Msk 0x80UL
|
||||
#define GPIO_PRT_V2_INTR_MASK_FLT_EDGE_Pos 8UL
|
||||
#define GPIO_PRT_V2_INTR_MASK_FLT_EDGE_Msk 0x100UL
|
||||
/* GPIO_PRT.INTR_MASKED */
|
||||
#define GPIO_PRT_V2_INTR_MASKED_EDGE0_Pos 0UL
|
||||
#define GPIO_PRT_V2_INTR_MASKED_EDGE0_Msk 0x1UL
|
||||
#define GPIO_PRT_V2_INTR_MASKED_EDGE1_Pos 1UL
|
||||
#define GPIO_PRT_V2_INTR_MASKED_EDGE1_Msk 0x2UL
|
||||
#define GPIO_PRT_V2_INTR_MASKED_EDGE2_Pos 2UL
|
||||
#define GPIO_PRT_V2_INTR_MASKED_EDGE2_Msk 0x4UL
|
||||
#define GPIO_PRT_V2_INTR_MASKED_EDGE3_Pos 3UL
|
||||
#define GPIO_PRT_V2_INTR_MASKED_EDGE3_Msk 0x8UL
|
||||
#define GPIO_PRT_V2_INTR_MASKED_EDGE4_Pos 4UL
|
||||
#define GPIO_PRT_V2_INTR_MASKED_EDGE4_Msk 0x10UL
|
||||
#define GPIO_PRT_V2_INTR_MASKED_EDGE5_Pos 5UL
|
||||
#define GPIO_PRT_V2_INTR_MASKED_EDGE5_Msk 0x20UL
|
||||
#define GPIO_PRT_V2_INTR_MASKED_EDGE6_Pos 6UL
|
||||
#define GPIO_PRT_V2_INTR_MASKED_EDGE6_Msk 0x40UL
|
||||
#define GPIO_PRT_V2_INTR_MASKED_EDGE7_Pos 7UL
|
||||
#define GPIO_PRT_V2_INTR_MASKED_EDGE7_Msk 0x80UL
|
||||
#define GPIO_PRT_V2_INTR_MASKED_FLT_EDGE_Pos 8UL
|
||||
#define GPIO_PRT_V2_INTR_MASKED_FLT_EDGE_Msk 0x100UL
|
||||
/* GPIO_PRT.INTR_SET */
|
||||
#define GPIO_PRT_V2_INTR_SET_EDGE0_Pos 0UL
|
||||
#define GPIO_PRT_V2_INTR_SET_EDGE0_Msk 0x1UL
|
||||
#define GPIO_PRT_V2_INTR_SET_EDGE1_Pos 1UL
|
||||
#define GPIO_PRT_V2_INTR_SET_EDGE1_Msk 0x2UL
|
||||
#define GPIO_PRT_V2_INTR_SET_EDGE2_Pos 2UL
|
||||
#define GPIO_PRT_V2_INTR_SET_EDGE2_Msk 0x4UL
|
||||
#define GPIO_PRT_V2_INTR_SET_EDGE3_Pos 3UL
|
||||
#define GPIO_PRT_V2_INTR_SET_EDGE3_Msk 0x8UL
|
||||
#define GPIO_PRT_V2_INTR_SET_EDGE4_Pos 4UL
|
||||
#define GPIO_PRT_V2_INTR_SET_EDGE4_Msk 0x10UL
|
||||
#define GPIO_PRT_V2_INTR_SET_EDGE5_Pos 5UL
|
||||
#define GPIO_PRT_V2_INTR_SET_EDGE5_Msk 0x20UL
|
||||
#define GPIO_PRT_V2_INTR_SET_EDGE6_Pos 6UL
|
||||
#define GPIO_PRT_V2_INTR_SET_EDGE6_Msk 0x40UL
|
||||
#define GPIO_PRT_V2_INTR_SET_EDGE7_Pos 7UL
|
||||
#define GPIO_PRT_V2_INTR_SET_EDGE7_Msk 0x80UL
|
||||
#define GPIO_PRT_V2_INTR_SET_FLT_EDGE_Pos 8UL
|
||||
#define GPIO_PRT_V2_INTR_SET_FLT_EDGE_Msk 0x100UL
|
||||
/* GPIO_PRT.INTR_CFG */
|
||||
#define GPIO_PRT_V2_INTR_CFG_EDGE0_SEL_Pos 0UL
|
||||
#define GPIO_PRT_V2_INTR_CFG_EDGE0_SEL_Msk 0x3UL
|
||||
#define GPIO_PRT_V2_INTR_CFG_EDGE1_SEL_Pos 2UL
|
||||
#define GPIO_PRT_V2_INTR_CFG_EDGE1_SEL_Msk 0xCUL
|
||||
#define GPIO_PRT_V2_INTR_CFG_EDGE2_SEL_Pos 4UL
|
||||
#define GPIO_PRT_V2_INTR_CFG_EDGE2_SEL_Msk 0x30UL
|
||||
#define GPIO_PRT_V2_INTR_CFG_EDGE3_SEL_Pos 6UL
|
||||
#define GPIO_PRT_V2_INTR_CFG_EDGE3_SEL_Msk 0xC0UL
|
||||
#define GPIO_PRT_V2_INTR_CFG_EDGE4_SEL_Pos 8UL
|
||||
#define GPIO_PRT_V2_INTR_CFG_EDGE4_SEL_Msk 0x300UL
|
||||
#define GPIO_PRT_V2_INTR_CFG_EDGE5_SEL_Pos 10UL
|
||||
#define GPIO_PRT_V2_INTR_CFG_EDGE5_SEL_Msk 0xC00UL
|
||||
#define GPIO_PRT_V2_INTR_CFG_EDGE6_SEL_Pos 12UL
|
||||
#define GPIO_PRT_V2_INTR_CFG_EDGE6_SEL_Msk 0x3000UL
|
||||
#define GPIO_PRT_V2_INTR_CFG_EDGE7_SEL_Pos 14UL
|
||||
#define GPIO_PRT_V2_INTR_CFG_EDGE7_SEL_Msk 0xC000UL
|
||||
#define GPIO_PRT_V2_INTR_CFG_FLT_EDGE_SEL_Pos 16UL
|
||||
#define GPIO_PRT_V2_INTR_CFG_FLT_EDGE_SEL_Msk 0x30000UL
|
||||
#define GPIO_PRT_V2_INTR_CFG_FLT_SEL_Pos 18UL
|
||||
#define GPIO_PRT_V2_INTR_CFG_FLT_SEL_Msk 0x1C0000UL
|
||||
/* GPIO_PRT.CFG */
|
||||
#define GPIO_PRT_V2_CFG_DRIVE_MODE0_Pos 0UL
|
||||
#define GPIO_PRT_V2_CFG_DRIVE_MODE0_Msk 0x7UL
|
||||
#define GPIO_PRT_V2_CFG_IN_EN0_Pos 3UL
|
||||
#define GPIO_PRT_V2_CFG_IN_EN0_Msk 0x8UL
|
||||
#define GPIO_PRT_V2_CFG_DRIVE_MODE1_Pos 4UL
|
||||
#define GPIO_PRT_V2_CFG_DRIVE_MODE1_Msk 0x70UL
|
||||
#define GPIO_PRT_V2_CFG_IN_EN1_Pos 7UL
|
||||
#define GPIO_PRT_V2_CFG_IN_EN1_Msk 0x80UL
|
||||
#define GPIO_PRT_V2_CFG_DRIVE_MODE2_Pos 8UL
|
||||
#define GPIO_PRT_V2_CFG_DRIVE_MODE2_Msk 0x700UL
|
||||
#define GPIO_PRT_V2_CFG_IN_EN2_Pos 11UL
|
||||
#define GPIO_PRT_V2_CFG_IN_EN2_Msk 0x800UL
|
||||
#define GPIO_PRT_V2_CFG_DRIVE_MODE3_Pos 12UL
|
||||
#define GPIO_PRT_V2_CFG_DRIVE_MODE3_Msk 0x7000UL
|
||||
#define GPIO_PRT_V2_CFG_IN_EN3_Pos 15UL
|
||||
#define GPIO_PRT_V2_CFG_IN_EN3_Msk 0x8000UL
|
||||
#define GPIO_PRT_V2_CFG_DRIVE_MODE4_Pos 16UL
|
||||
#define GPIO_PRT_V2_CFG_DRIVE_MODE4_Msk 0x70000UL
|
||||
#define GPIO_PRT_V2_CFG_IN_EN4_Pos 19UL
|
||||
#define GPIO_PRT_V2_CFG_IN_EN4_Msk 0x80000UL
|
||||
#define GPIO_PRT_V2_CFG_DRIVE_MODE5_Pos 20UL
|
||||
#define GPIO_PRT_V2_CFG_DRIVE_MODE5_Msk 0x700000UL
|
||||
#define GPIO_PRT_V2_CFG_IN_EN5_Pos 23UL
|
||||
#define GPIO_PRT_V2_CFG_IN_EN5_Msk 0x800000UL
|
||||
#define GPIO_PRT_V2_CFG_DRIVE_MODE6_Pos 24UL
|
||||
#define GPIO_PRT_V2_CFG_DRIVE_MODE6_Msk 0x7000000UL
|
||||
#define GPIO_PRT_V2_CFG_IN_EN6_Pos 27UL
|
||||
#define GPIO_PRT_V2_CFG_IN_EN6_Msk 0x8000000UL
|
||||
#define GPIO_PRT_V2_CFG_DRIVE_MODE7_Pos 28UL
|
||||
#define GPIO_PRT_V2_CFG_DRIVE_MODE7_Msk 0x70000000UL
|
||||
#define GPIO_PRT_V2_CFG_IN_EN7_Pos 31UL
|
||||
#define GPIO_PRT_V2_CFG_IN_EN7_Msk 0x80000000UL
|
||||
/* GPIO_PRT.CFG_IN */
|
||||
#define GPIO_PRT_V2_CFG_IN_VTRIP_SEL0_0_Pos 0UL
|
||||
#define GPIO_PRT_V2_CFG_IN_VTRIP_SEL0_0_Msk 0x1UL
|
||||
#define GPIO_PRT_V2_CFG_IN_VTRIP_SEL1_0_Pos 1UL
|
||||
#define GPIO_PRT_V2_CFG_IN_VTRIP_SEL1_0_Msk 0x2UL
|
||||
#define GPIO_PRT_V2_CFG_IN_VTRIP_SEL2_0_Pos 2UL
|
||||
#define GPIO_PRT_V2_CFG_IN_VTRIP_SEL2_0_Msk 0x4UL
|
||||
#define GPIO_PRT_V2_CFG_IN_VTRIP_SEL3_0_Pos 3UL
|
||||
#define GPIO_PRT_V2_CFG_IN_VTRIP_SEL3_0_Msk 0x8UL
|
||||
#define GPIO_PRT_V2_CFG_IN_VTRIP_SEL4_0_Pos 4UL
|
||||
#define GPIO_PRT_V2_CFG_IN_VTRIP_SEL4_0_Msk 0x10UL
|
||||
#define GPIO_PRT_V2_CFG_IN_VTRIP_SEL5_0_Pos 5UL
|
||||
#define GPIO_PRT_V2_CFG_IN_VTRIP_SEL5_0_Msk 0x20UL
|
||||
#define GPIO_PRT_V2_CFG_IN_VTRIP_SEL6_0_Pos 6UL
|
||||
#define GPIO_PRT_V2_CFG_IN_VTRIP_SEL6_0_Msk 0x40UL
|
||||
#define GPIO_PRT_V2_CFG_IN_VTRIP_SEL7_0_Pos 7UL
|
||||
#define GPIO_PRT_V2_CFG_IN_VTRIP_SEL7_0_Msk 0x80UL
|
||||
/* GPIO_PRT.CFG_OUT */
|
||||
#define GPIO_PRT_V2_CFG_OUT_SLOW0_Pos 0UL
|
||||
#define GPIO_PRT_V2_CFG_OUT_SLOW0_Msk 0x1UL
|
||||
#define GPIO_PRT_V2_CFG_OUT_SLOW1_Pos 1UL
|
||||
#define GPIO_PRT_V2_CFG_OUT_SLOW1_Msk 0x2UL
|
||||
#define GPIO_PRT_V2_CFG_OUT_SLOW2_Pos 2UL
|
||||
#define GPIO_PRT_V2_CFG_OUT_SLOW2_Msk 0x4UL
|
||||
#define GPIO_PRT_V2_CFG_OUT_SLOW3_Pos 3UL
|
||||
#define GPIO_PRT_V2_CFG_OUT_SLOW3_Msk 0x8UL
|
||||
#define GPIO_PRT_V2_CFG_OUT_SLOW4_Pos 4UL
|
||||
#define GPIO_PRT_V2_CFG_OUT_SLOW4_Msk 0x10UL
|
||||
#define GPIO_PRT_V2_CFG_OUT_SLOW5_Pos 5UL
|
||||
#define GPIO_PRT_V2_CFG_OUT_SLOW5_Msk 0x20UL
|
||||
#define GPIO_PRT_V2_CFG_OUT_SLOW6_Pos 6UL
|
||||
#define GPIO_PRT_V2_CFG_OUT_SLOW6_Msk 0x40UL
|
||||
#define GPIO_PRT_V2_CFG_OUT_SLOW7_Pos 7UL
|
||||
#define GPIO_PRT_V2_CFG_OUT_SLOW7_Msk 0x80UL
|
||||
#define GPIO_PRT_V2_CFG_OUT_DRIVE_SEL0_Pos 16UL
|
||||
#define GPIO_PRT_V2_CFG_OUT_DRIVE_SEL0_Msk 0x30000UL
|
||||
#define GPIO_PRT_V2_CFG_OUT_DRIVE_SEL1_Pos 18UL
|
||||
#define GPIO_PRT_V2_CFG_OUT_DRIVE_SEL1_Msk 0xC0000UL
|
||||
#define GPIO_PRT_V2_CFG_OUT_DRIVE_SEL2_Pos 20UL
|
||||
#define GPIO_PRT_V2_CFG_OUT_DRIVE_SEL2_Msk 0x300000UL
|
||||
#define GPIO_PRT_V2_CFG_OUT_DRIVE_SEL3_Pos 22UL
|
||||
#define GPIO_PRT_V2_CFG_OUT_DRIVE_SEL3_Msk 0xC00000UL
|
||||
#define GPIO_PRT_V2_CFG_OUT_DRIVE_SEL4_Pos 24UL
|
||||
#define GPIO_PRT_V2_CFG_OUT_DRIVE_SEL4_Msk 0x3000000UL
|
||||
#define GPIO_PRT_V2_CFG_OUT_DRIVE_SEL5_Pos 26UL
|
||||
#define GPIO_PRT_V2_CFG_OUT_DRIVE_SEL5_Msk 0xC000000UL
|
||||
#define GPIO_PRT_V2_CFG_OUT_DRIVE_SEL6_Pos 28UL
|
||||
#define GPIO_PRT_V2_CFG_OUT_DRIVE_SEL6_Msk 0x30000000UL
|
||||
#define GPIO_PRT_V2_CFG_OUT_DRIVE_SEL7_Pos 30UL
|
||||
#define GPIO_PRT_V2_CFG_OUT_DRIVE_SEL7_Msk 0xC0000000UL
|
||||
/* GPIO_PRT.CFG_SIO */
|
||||
#define GPIO_PRT_V2_CFG_SIO_VREG_EN01_Pos 0UL
|
||||
#define GPIO_PRT_V2_CFG_SIO_VREG_EN01_Msk 0x1UL
|
||||
#define GPIO_PRT_V2_CFG_SIO_IBUF_SEL01_Pos 1UL
|
||||
#define GPIO_PRT_V2_CFG_SIO_IBUF_SEL01_Msk 0x2UL
|
||||
#define GPIO_PRT_V2_CFG_SIO_VTRIP_SEL01_Pos 2UL
|
||||
#define GPIO_PRT_V2_CFG_SIO_VTRIP_SEL01_Msk 0x4UL
|
||||
#define GPIO_PRT_V2_CFG_SIO_VREF_SEL01_Pos 3UL
|
||||
#define GPIO_PRT_V2_CFG_SIO_VREF_SEL01_Msk 0x18UL
|
||||
#define GPIO_PRT_V2_CFG_SIO_VOH_SEL01_Pos 5UL
|
||||
#define GPIO_PRT_V2_CFG_SIO_VOH_SEL01_Msk 0xE0UL
|
||||
#define GPIO_PRT_V2_CFG_SIO_VREG_EN23_Pos 8UL
|
||||
#define GPIO_PRT_V2_CFG_SIO_VREG_EN23_Msk 0x100UL
|
||||
#define GPIO_PRT_V2_CFG_SIO_IBUF_SEL23_Pos 9UL
|
||||
#define GPIO_PRT_V2_CFG_SIO_IBUF_SEL23_Msk 0x200UL
|
||||
#define GPIO_PRT_V2_CFG_SIO_VTRIP_SEL23_Pos 10UL
|
||||
#define GPIO_PRT_V2_CFG_SIO_VTRIP_SEL23_Msk 0x400UL
|
||||
#define GPIO_PRT_V2_CFG_SIO_VREF_SEL23_Pos 11UL
|
||||
#define GPIO_PRT_V2_CFG_SIO_VREF_SEL23_Msk 0x1800UL
|
||||
#define GPIO_PRT_V2_CFG_SIO_VOH_SEL23_Pos 13UL
|
||||
#define GPIO_PRT_V2_CFG_SIO_VOH_SEL23_Msk 0xE000UL
|
||||
#define GPIO_PRT_V2_CFG_SIO_VREG_EN45_Pos 16UL
|
||||
#define GPIO_PRT_V2_CFG_SIO_VREG_EN45_Msk 0x10000UL
|
||||
#define GPIO_PRT_V2_CFG_SIO_IBUF_SEL45_Pos 17UL
|
||||
#define GPIO_PRT_V2_CFG_SIO_IBUF_SEL45_Msk 0x20000UL
|
||||
#define GPIO_PRT_V2_CFG_SIO_VTRIP_SEL45_Pos 18UL
|
||||
#define GPIO_PRT_V2_CFG_SIO_VTRIP_SEL45_Msk 0x40000UL
|
||||
#define GPIO_PRT_V2_CFG_SIO_VREF_SEL45_Pos 19UL
|
||||
#define GPIO_PRT_V2_CFG_SIO_VREF_SEL45_Msk 0x180000UL
|
||||
#define GPIO_PRT_V2_CFG_SIO_VOH_SEL45_Pos 21UL
|
||||
#define GPIO_PRT_V2_CFG_SIO_VOH_SEL45_Msk 0xE00000UL
|
||||
#define GPIO_PRT_V2_CFG_SIO_VREG_EN67_Pos 24UL
|
||||
#define GPIO_PRT_V2_CFG_SIO_VREG_EN67_Msk 0x1000000UL
|
||||
#define GPIO_PRT_V2_CFG_SIO_IBUF_SEL67_Pos 25UL
|
||||
#define GPIO_PRT_V2_CFG_SIO_IBUF_SEL67_Msk 0x2000000UL
|
||||
#define GPIO_PRT_V2_CFG_SIO_VTRIP_SEL67_Pos 26UL
|
||||
#define GPIO_PRT_V2_CFG_SIO_VTRIP_SEL67_Msk 0x4000000UL
|
||||
#define GPIO_PRT_V2_CFG_SIO_VREF_SEL67_Pos 27UL
|
||||
#define GPIO_PRT_V2_CFG_SIO_VREF_SEL67_Msk 0x18000000UL
|
||||
#define GPIO_PRT_V2_CFG_SIO_VOH_SEL67_Pos 29UL
|
||||
#define GPIO_PRT_V2_CFG_SIO_VOH_SEL67_Msk 0xE0000000UL
|
||||
/* GPIO_PRT.CFG_IN_AUTOLVL */
|
||||
#define GPIO_PRT_V2_CFG_IN_AUTOLVL_VTRIP_SEL0_1_Pos 0UL
|
||||
#define GPIO_PRT_V2_CFG_IN_AUTOLVL_VTRIP_SEL0_1_Msk 0x1UL
|
||||
#define GPIO_PRT_V2_CFG_IN_AUTOLVL_VTRIP_SEL1_1_Pos 1UL
|
||||
#define GPIO_PRT_V2_CFG_IN_AUTOLVL_VTRIP_SEL1_1_Msk 0x2UL
|
||||
#define GPIO_PRT_V2_CFG_IN_AUTOLVL_VTRIP_SEL2_1_Pos 2UL
|
||||
#define GPIO_PRT_V2_CFG_IN_AUTOLVL_VTRIP_SEL2_1_Msk 0x4UL
|
||||
#define GPIO_PRT_V2_CFG_IN_AUTOLVL_VTRIP_SEL3_1_Pos 3UL
|
||||
#define GPIO_PRT_V2_CFG_IN_AUTOLVL_VTRIP_SEL3_1_Msk 0x8UL
|
||||
#define GPIO_PRT_V2_CFG_IN_AUTOLVL_VTRIP_SEL4_1_Pos 4UL
|
||||
#define GPIO_PRT_V2_CFG_IN_AUTOLVL_VTRIP_SEL4_1_Msk 0x10UL
|
||||
#define GPIO_PRT_V2_CFG_IN_AUTOLVL_VTRIP_SEL5_1_Pos 5UL
|
||||
#define GPIO_PRT_V2_CFG_IN_AUTOLVL_VTRIP_SEL5_1_Msk 0x20UL
|
||||
#define GPIO_PRT_V2_CFG_IN_AUTOLVL_VTRIP_SEL6_1_Pos 6UL
|
||||
#define GPIO_PRT_V2_CFG_IN_AUTOLVL_VTRIP_SEL6_1_Msk 0x40UL
|
||||
#define GPIO_PRT_V2_CFG_IN_AUTOLVL_VTRIP_SEL7_1_Pos 7UL
|
||||
#define GPIO_PRT_V2_CFG_IN_AUTOLVL_VTRIP_SEL7_1_Msk 0x80UL
|
||||
|
||||
|
||||
/* GPIO.INTR_CAUSE0 */
|
||||
#define GPIO_V2_INTR_CAUSE0_PORT_INT_Pos 0UL
|
||||
#define GPIO_V2_INTR_CAUSE0_PORT_INT_Msk 0xFFFFFFFFUL
|
||||
/* GPIO.INTR_CAUSE1 */
|
||||
#define GPIO_V2_INTR_CAUSE1_PORT_INT_Pos 0UL
|
||||
#define GPIO_V2_INTR_CAUSE1_PORT_INT_Msk 0xFFFFFFFFUL
|
||||
/* GPIO.INTR_CAUSE2 */
|
||||
#define GPIO_V2_INTR_CAUSE2_PORT_INT_Pos 0UL
|
||||
#define GPIO_V2_INTR_CAUSE2_PORT_INT_Msk 0xFFFFFFFFUL
|
||||
/* GPIO.INTR_CAUSE3 */
|
||||
#define GPIO_V2_INTR_CAUSE3_PORT_INT_Pos 0UL
|
||||
#define GPIO_V2_INTR_CAUSE3_PORT_INT_Msk 0xFFFFFFFFUL
|
||||
/* GPIO.VDD_ACTIVE */
|
||||
#define GPIO_V2_VDD_ACTIVE_VDDIO_ACTIVE_Pos 0UL
|
||||
#define GPIO_V2_VDD_ACTIVE_VDDIO_ACTIVE_Msk 0xFFFFUL
|
||||
#define GPIO_V2_VDD_ACTIVE_VDDA_ACTIVE_Pos 30UL
|
||||
#define GPIO_V2_VDD_ACTIVE_VDDA_ACTIVE_Msk 0x40000000UL
|
||||
#define GPIO_V2_VDD_ACTIVE_VDDD_ACTIVE_Pos 31UL
|
||||
#define GPIO_V2_VDD_ACTIVE_VDDD_ACTIVE_Msk 0x80000000UL
|
||||
/* GPIO.VDD_INTR */
|
||||
#define GPIO_V2_VDD_INTR_VDDIO_ACTIVE_Pos 0UL
|
||||
#define GPIO_V2_VDD_INTR_VDDIO_ACTIVE_Msk 0xFFFFUL
|
||||
#define GPIO_V2_VDD_INTR_VDDA_ACTIVE_Pos 30UL
|
||||
#define GPIO_V2_VDD_INTR_VDDA_ACTIVE_Msk 0x40000000UL
|
||||
#define GPIO_V2_VDD_INTR_VDDD_ACTIVE_Pos 31UL
|
||||
#define GPIO_V2_VDD_INTR_VDDD_ACTIVE_Msk 0x80000000UL
|
||||
/* GPIO.VDD_INTR_MASK */
|
||||
#define GPIO_V2_VDD_INTR_MASK_VDDIO_ACTIVE_Pos 0UL
|
||||
#define GPIO_V2_VDD_INTR_MASK_VDDIO_ACTIVE_Msk 0xFFFFUL
|
||||
#define GPIO_V2_VDD_INTR_MASK_VDDA_ACTIVE_Pos 30UL
|
||||
#define GPIO_V2_VDD_INTR_MASK_VDDA_ACTIVE_Msk 0x40000000UL
|
||||
#define GPIO_V2_VDD_INTR_MASK_VDDD_ACTIVE_Pos 31UL
|
||||
#define GPIO_V2_VDD_INTR_MASK_VDDD_ACTIVE_Msk 0x80000000UL
|
||||
/* GPIO.VDD_INTR_MASKED */
|
||||
#define GPIO_V2_VDD_INTR_MASKED_VDDIO_ACTIVE_Pos 0UL
|
||||
#define GPIO_V2_VDD_INTR_MASKED_VDDIO_ACTIVE_Msk 0xFFFFUL
|
||||
#define GPIO_V2_VDD_INTR_MASKED_VDDA_ACTIVE_Pos 30UL
|
||||
#define GPIO_V2_VDD_INTR_MASKED_VDDA_ACTIVE_Msk 0x40000000UL
|
||||
#define GPIO_V2_VDD_INTR_MASKED_VDDD_ACTIVE_Pos 31UL
|
||||
#define GPIO_V2_VDD_INTR_MASKED_VDDD_ACTIVE_Msk 0x80000000UL
|
||||
/* GPIO.VDD_INTR_SET */
|
||||
#define GPIO_V2_VDD_INTR_SET_VDDIO_ACTIVE_Pos 0UL
|
||||
#define GPIO_V2_VDD_INTR_SET_VDDIO_ACTIVE_Msk 0xFFFFUL
|
||||
#define GPIO_V2_VDD_INTR_SET_VDDA_ACTIVE_Pos 30UL
|
||||
#define GPIO_V2_VDD_INTR_SET_VDDA_ACTIVE_Msk 0x40000000UL
|
||||
#define GPIO_V2_VDD_INTR_SET_VDDD_ACTIVE_Pos 31UL
|
||||
#define GPIO_V2_VDD_INTR_SET_VDDD_ACTIVE_Msk 0x80000000UL
|
||||
|
||||
|
||||
#endif /* _CYIP_GPIO_V2_H_ */
|
||||
|
||||
|
||||
/* [] END OF FILE */
|
||||
|
|
@ -1,35 +0,0 @@
|
|||
/***************************************************************************//**
|
||||
* \file cyip_headers.h
|
||||
*
|
||||
* \brief
|
||||
* Common header file to be included by all IP definition headers
|
||||
*
|
||||
********************************************************************************
|
||||
* \copyright
|
||||
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
|
||||
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _CYIP_HEADERS_H_
|
||||
#define _CYIP_HEADERS_H_
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/* These are CMSIS-CORE defines used for structure members definitions */
|
||||
#ifndef __IM
|
||||
#define __IM volatile const /*! Defines 'read only' structure member permissions */
|
||||
#endif
|
||||
#ifndef __OM
|
||||
#define __OM volatile /*! Defines 'write only' structure member permissions */
|
||||
#endif
|
||||
#ifndef __IOM
|
||||
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
|
||||
#endif
|
||||
|
||||
#endif /* _CYIP_HEADERS_H_ */
|
||||
|
||||
|
||||
/* [] END OF FILE */
|
||||
|
|
@ -1,89 +0,0 @@
|
|||
/***************************************************************************//**
|
||||
* \file cyip_hsiom.h
|
||||
*
|
||||
* \brief
|
||||
* HSIOM IP definitions
|
||||
*
|
||||
* \note
|
||||
* Generator version: 1.3.0.1146
|
||||
* Database revision: rev#1050929
|
||||
*
|
||||
********************************************************************************
|
||||
* \copyright
|
||||
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
|
||||
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _CYIP_HSIOM_H_
|
||||
#define _CYIP_HSIOM_H_
|
||||
|
||||
#include "cyip_headers.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* HSIOM
|
||||
*******************************************************************************/
|
||||
|
||||
#define HSIOM_PRT_SECTION_SIZE 0x00000010UL
|
||||
#define HSIOM_SECTION_SIZE 0x00004000UL
|
||||
|
||||
/**
|
||||
* \brief HSIOM port registers (HSIOM_PRT)
|
||||
*/
|
||||
typedef struct {
|
||||
__IOM uint32_t PORT_SEL0; /*!< 0x00000000 Port selection 0 */
|
||||
__IOM uint32_t PORT_SEL1; /*!< 0x00000004 Port selection 1 */
|
||||
__IM uint32_t RESERVED[2];
|
||||
} HSIOM_PRT_V1_Type; /*!< Size = 16 (0x10) */
|
||||
|
||||
/**
|
||||
* \brief High Speed IO Matrix (HSIOM) (HSIOM)
|
||||
*/
|
||||
typedef struct {
|
||||
HSIOM_PRT_V1_Type PRT[128]; /*!< 0x00000000 HSIOM port registers */
|
||||
__IM uint32_t RESERVED[1536];
|
||||
__IOM uint32_t AMUX_SPLIT_CTL[64]; /*!< 0x00002000 AMUX splitter cell control */
|
||||
} HSIOM_V1_Type; /*!< Size = 8448 (0x2100) */
|
||||
|
||||
|
||||
/* HSIOM_PRT.PORT_SEL0 */
|
||||
#define HSIOM_PRT_PORT_SEL0_IO0_SEL_Pos 0UL
|
||||
#define HSIOM_PRT_PORT_SEL0_IO0_SEL_Msk 0x1FUL
|
||||
#define HSIOM_PRT_PORT_SEL0_IO1_SEL_Pos 8UL
|
||||
#define HSIOM_PRT_PORT_SEL0_IO1_SEL_Msk 0x1F00UL
|
||||
#define HSIOM_PRT_PORT_SEL0_IO2_SEL_Pos 16UL
|
||||
#define HSIOM_PRT_PORT_SEL0_IO2_SEL_Msk 0x1F0000UL
|
||||
#define HSIOM_PRT_PORT_SEL0_IO3_SEL_Pos 24UL
|
||||
#define HSIOM_PRT_PORT_SEL0_IO3_SEL_Msk 0x1F000000UL
|
||||
/* HSIOM_PRT.PORT_SEL1 */
|
||||
#define HSIOM_PRT_PORT_SEL1_IO4_SEL_Pos 0UL
|
||||
#define HSIOM_PRT_PORT_SEL1_IO4_SEL_Msk 0x1FUL
|
||||
#define HSIOM_PRT_PORT_SEL1_IO5_SEL_Pos 8UL
|
||||
#define HSIOM_PRT_PORT_SEL1_IO5_SEL_Msk 0x1F00UL
|
||||
#define HSIOM_PRT_PORT_SEL1_IO6_SEL_Pos 16UL
|
||||
#define HSIOM_PRT_PORT_SEL1_IO6_SEL_Msk 0x1F0000UL
|
||||
#define HSIOM_PRT_PORT_SEL1_IO7_SEL_Pos 24UL
|
||||
#define HSIOM_PRT_PORT_SEL1_IO7_SEL_Msk 0x1F000000UL
|
||||
|
||||
|
||||
/* HSIOM.AMUX_SPLIT_CTL */
|
||||
#define HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SL_Pos 0UL
|
||||
#define HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SL_Msk 0x1UL
|
||||
#define HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SR_Pos 1UL
|
||||
#define HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_SR_Msk 0x2UL
|
||||
#define HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_S0_Pos 2UL
|
||||
#define HSIOM_AMUX_SPLIT_CTL_SWITCH_AA_S0_Msk 0x4UL
|
||||
#define HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SL_Pos 4UL
|
||||
#define HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SL_Msk 0x10UL
|
||||
#define HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SR_Pos 5UL
|
||||
#define HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_SR_Msk 0x20UL
|
||||
#define HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_S0_Pos 6UL
|
||||
#define HSIOM_AMUX_SPLIT_CTL_SWITCH_BB_S0_Msk 0x40UL
|
||||
|
||||
|
||||
#endif /* _CYIP_HSIOM_H_ */
|
||||
|
||||
|
||||
/* [] END OF FILE */
|
||||
|
|
@ -1,111 +0,0 @@
|
|||
/***************************************************************************//**
|
||||
* \file cyip_hsiom_v2.h
|
||||
*
|
||||
* \brief
|
||||
* HSIOM IP definitions
|
||||
*
|
||||
* \note
|
||||
* Generator version: 1.3.0.1146
|
||||
* Database revision: rev#1050929
|
||||
*
|
||||
********************************************************************************
|
||||
* \copyright
|
||||
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
|
||||
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _CYIP_HSIOM_V2_H_
|
||||
#define _CYIP_HSIOM_V2_H_
|
||||
|
||||
#include "cyip_headers.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* HSIOM
|
||||
*******************************************************************************/
|
||||
|
||||
#define HSIOM_PRT_V2_SECTION_SIZE 0x00000010UL
|
||||
#define HSIOM_V2_SECTION_SIZE 0x00004000UL
|
||||
|
||||
/**
|
||||
* \brief HSIOM port registers (HSIOM_PRT)
|
||||
*/
|
||||
typedef struct {
|
||||
__IOM uint32_t PORT_SEL0; /*!< 0x00000000 Port selection 0 */
|
||||
__IOM uint32_t PORT_SEL1; /*!< 0x00000004 Port selection 1 */
|
||||
__IM uint32_t RESERVED[2];
|
||||
} HSIOM_PRT_V2_Type; /*!< Size = 16 (0x10) */
|
||||
|
||||
/**
|
||||
* \brief High Speed IO Matrix (HSIOM) (HSIOM)
|
||||
*/
|
||||
typedef struct {
|
||||
HSIOM_PRT_V2_Type PRT[128]; /*!< 0x00000000 HSIOM port registers */
|
||||
__IM uint32_t RESERVED[1536];
|
||||
__IOM uint32_t AMUX_SPLIT_CTL[64]; /*!< 0x00002000 AMUX splitter cell control */
|
||||
__IM uint32_t RESERVED1[64];
|
||||
__IOM uint32_t MONITOR_CTL_0; /*!< 0x00002200 Power/Ground Monitor cell control 0 */
|
||||
__IOM uint32_t MONITOR_CTL_1; /*!< 0x00002204 Power/Ground Monitor cell control 1 */
|
||||
__IOM uint32_t MONITOR_CTL_2; /*!< 0x00002208 Power/Ground Monitor cell control 2 */
|
||||
__IOM uint32_t MONITOR_CTL_3; /*!< 0x0000220C Power/Ground Monitor cell control 3 */
|
||||
__IM uint32_t RESERVED2[12];
|
||||
__IOM uint32_t ALT_JTAG_EN; /*!< 0x00002240 Alternate JTAG IF selection register */
|
||||
} HSIOM_V2_Type; /*!< Size = 8772 (0x2244) */
|
||||
|
||||
|
||||
/* HSIOM_PRT.PORT_SEL0 */
|
||||
#define HSIOM_PRT_V2_PORT_SEL0_IO0_SEL_Pos 0UL
|
||||
#define HSIOM_PRT_V2_PORT_SEL0_IO0_SEL_Msk 0x1FUL
|
||||
#define HSIOM_PRT_V2_PORT_SEL0_IO1_SEL_Pos 8UL
|
||||
#define HSIOM_PRT_V2_PORT_SEL0_IO1_SEL_Msk 0x1F00UL
|
||||
#define HSIOM_PRT_V2_PORT_SEL0_IO2_SEL_Pos 16UL
|
||||
#define HSIOM_PRT_V2_PORT_SEL0_IO2_SEL_Msk 0x1F0000UL
|
||||
#define HSIOM_PRT_V2_PORT_SEL0_IO3_SEL_Pos 24UL
|
||||
#define HSIOM_PRT_V2_PORT_SEL0_IO3_SEL_Msk 0x1F000000UL
|
||||
/* HSIOM_PRT.PORT_SEL1 */
|
||||
#define HSIOM_PRT_V2_PORT_SEL1_IO4_SEL_Pos 0UL
|
||||
#define HSIOM_PRT_V2_PORT_SEL1_IO4_SEL_Msk 0x1FUL
|
||||
#define HSIOM_PRT_V2_PORT_SEL1_IO5_SEL_Pos 8UL
|
||||
#define HSIOM_PRT_V2_PORT_SEL1_IO5_SEL_Msk 0x1F00UL
|
||||
#define HSIOM_PRT_V2_PORT_SEL1_IO6_SEL_Pos 16UL
|
||||
#define HSIOM_PRT_V2_PORT_SEL1_IO6_SEL_Msk 0x1F0000UL
|
||||
#define HSIOM_PRT_V2_PORT_SEL1_IO7_SEL_Pos 24UL
|
||||
#define HSIOM_PRT_V2_PORT_SEL1_IO7_SEL_Msk 0x1F000000UL
|
||||
|
||||
|
||||
/* HSIOM.AMUX_SPLIT_CTL */
|
||||
#define HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_AA_SL_Pos 0UL
|
||||
#define HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_AA_SL_Msk 0x1UL
|
||||
#define HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_AA_SR_Pos 1UL
|
||||
#define HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_AA_SR_Msk 0x2UL
|
||||
#define HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_AA_S0_Pos 2UL
|
||||
#define HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_AA_S0_Msk 0x4UL
|
||||
#define HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_BB_SL_Pos 4UL
|
||||
#define HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_BB_SL_Msk 0x10UL
|
||||
#define HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_BB_SR_Pos 5UL
|
||||
#define HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_BB_SR_Msk 0x20UL
|
||||
#define HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_BB_S0_Pos 6UL
|
||||
#define HSIOM_V2_AMUX_SPLIT_CTL_SWITCH_BB_S0_Msk 0x40UL
|
||||
/* HSIOM.MONITOR_CTL_0 */
|
||||
#define HSIOM_V2_MONITOR_CTL_0_MONITOR_EN_Pos 0UL
|
||||
#define HSIOM_V2_MONITOR_CTL_0_MONITOR_EN_Msk 0xFFFFFFFFUL
|
||||
/* HSIOM.MONITOR_CTL_1 */
|
||||
#define HSIOM_V2_MONITOR_CTL_1_MONITOR_EN_Pos 0UL
|
||||
#define HSIOM_V2_MONITOR_CTL_1_MONITOR_EN_Msk 0xFFFFFFFFUL
|
||||
/* HSIOM.MONITOR_CTL_2 */
|
||||
#define HSIOM_V2_MONITOR_CTL_2_MONITOR_EN_Pos 0UL
|
||||
#define HSIOM_V2_MONITOR_CTL_2_MONITOR_EN_Msk 0xFFFFFFFFUL
|
||||
/* HSIOM.MONITOR_CTL_3 */
|
||||
#define HSIOM_V2_MONITOR_CTL_3_MONITOR_EN_Pos 0UL
|
||||
#define HSIOM_V2_MONITOR_CTL_3_MONITOR_EN_Msk 0xFFFFFFFFUL
|
||||
/* HSIOM.ALT_JTAG_EN */
|
||||
#define HSIOM_V2_ALT_JTAG_EN_ENABLE_Pos 31UL
|
||||
#define HSIOM_V2_ALT_JTAG_EN_ENABLE_Msk 0x80000000UL
|
||||
|
||||
|
||||
#endif /* _CYIP_HSIOM_V2_H_ */
|
||||
|
||||
|
||||
/* [] END OF FILE */
|
||||
|
|
@ -1,281 +0,0 @@
|
|||
/***************************************************************************//**
|
||||
* \file cyip_i2s.h
|
||||
*
|
||||
* \brief
|
||||
* I2S IP definitions
|
||||
*
|
||||
* \note
|
||||
* Generator version: 1.3.0.1146
|
||||
* Database revision: rev#1050929
|
||||
*
|
||||
********************************************************************************
|
||||
* \copyright
|
||||
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
|
||||
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _CYIP_I2S_H_
|
||||
#define _CYIP_I2S_H_
|
||||
|
||||
#include "cyip_headers.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* I2S
|
||||
*******************************************************************************/
|
||||
|
||||
#define I2S_SECTION_SIZE 0x00001000UL
|
||||
|
||||
/**
|
||||
* \brief I2S registers (I2S)
|
||||
*/
|
||||
typedef struct {
|
||||
__IOM uint32_t CTL; /*!< 0x00000000 Control */
|
||||
__IM uint32_t RESERVED[3];
|
||||
__IOM uint32_t CLOCK_CTL; /*!< 0x00000010 Clock control */
|
||||
__IM uint32_t RESERVED1[3];
|
||||
__IOM uint32_t CMD; /*!< 0x00000020 Command */
|
||||
__IM uint32_t RESERVED2[7];
|
||||
__IOM uint32_t TR_CTL; /*!< 0x00000040 Trigger control */
|
||||
__IM uint32_t RESERVED3[15];
|
||||
__IOM uint32_t TX_CTL; /*!< 0x00000080 Transmitter control */
|
||||
__IOM uint32_t TX_WATCHDOG; /*!< 0x00000084 Transmitter watchdog */
|
||||
__IM uint32_t RESERVED4[6];
|
||||
__IOM uint32_t RX_CTL; /*!< 0x000000A0 Receiver control */
|
||||
__IOM uint32_t RX_WATCHDOG; /*!< 0x000000A4 Receiver watchdog */
|
||||
__IM uint32_t RESERVED5[86];
|
||||
__IOM uint32_t TX_FIFO_CTL; /*!< 0x00000200 TX FIFO control */
|
||||
__IM uint32_t TX_FIFO_STATUS; /*!< 0x00000204 TX FIFO status */
|
||||
__OM uint32_t TX_FIFO_WR; /*!< 0x00000208 TX FIFO write */
|
||||
__IM uint32_t RESERVED6[61];
|
||||
__IOM uint32_t RX_FIFO_CTL; /*!< 0x00000300 RX FIFO control */
|
||||
__IM uint32_t RX_FIFO_STATUS; /*!< 0x00000304 RX FIFO status */
|
||||
__IM uint32_t RX_FIFO_RD; /*!< 0x00000308 RX FIFO read */
|
||||
__IM uint32_t RX_FIFO_RD_SILENT; /*!< 0x0000030C RX FIFO silent read */
|
||||
__IM uint32_t RESERVED7[764];
|
||||
__IOM uint32_t INTR; /*!< 0x00000F00 Interrupt register */
|
||||
__IOM uint32_t INTR_SET; /*!< 0x00000F04 Interrupt set register */
|
||||
__IOM uint32_t INTR_MASK; /*!< 0x00000F08 Interrupt mask register */
|
||||
__IM uint32_t INTR_MASKED; /*!< 0x00000F0C Interrupt masked register */
|
||||
} I2S_V1_Type; /*!< Size = 3856 (0xF10) */
|
||||
|
||||
|
||||
/* I2S.CTL */
|
||||
#define I2S_CTL_TX_ENABLED_Pos 30UL
|
||||
#define I2S_CTL_TX_ENABLED_Msk 0x40000000UL
|
||||
#define I2S_CTL_RX_ENABLED_Pos 31UL
|
||||
#define I2S_CTL_RX_ENABLED_Msk 0x80000000UL
|
||||
/* I2S.CLOCK_CTL */
|
||||
#define I2S_CLOCK_CTL_CLOCK_DIV_Pos 0UL
|
||||
#define I2S_CLOCK_CTL_CLOCK_DIV_Msk 0x3FUL
|
||||
#define I2S_CLOCK_CTL_CLOCK_SEL_Pos 8UL
|
||||
#define I2S_CLOCK_CTL_CLOCK_SEL_Msk 0x100UL
|
||||
/* I2S.CMD */
|
||||
#define I2S_CMD_TX_START_Pos 0UL
|
||||
#define I2S_CMD_TX_START_Msk 0x1UL
|
||||
#define I2S_CMD_TX_PAUSE_Pos 8UL
|
||||
#define I2S_CMD_TX_PAUSE_Msk 0x100UL
|
||||
#define I2S_CMD_RX_START_Pos 16UL
|
||||
#define I2S_CMD_RX_START_Msk 0x10000UL
|
||||
/* I2S.TR_CTL */
|
||||
#define I2S_TR_CTL_TX_REQ_EN_Pos 0UL
|
||||
#define I2S_TR_CTL_TX_REQ_EN_Msk 0x1UL
|
||||
#define I2S_TR_CTL_RX_REQ_EN_Pos 16UL
|
||||
#define I2S_TR_CTL_RX_REQ_EN_Msk 0x10000UL
|
||||
/* I2S.TX_CTL */
|
||||
#define I2S_TX_CTL_B_CLOCK_INV_Pos 3UL
|
||||
#define I2S_TX_CTL_B_CLOCK_INV_Msk 0x8UL
|
||||
#define I2S_TX_CTL_CH_NR_Pos 4UL
|
||||
#define I2S_TX_CTL_CH_NR_Msk 0x70UL
|
||||
#define I2S_TX_CTL_MS_Pos 7UL
|
||||
#define I2S_TX_CTL_MS_Msk 0x80UL
|
||||
#define I2S_TX_CTL_I2S_MODE_Pos 8UL
|
||||
#define I2S_TX_CTL_I2S_MODE_Msk 0x300UL
|
||||
#define I2S_TX_CTL_WS_PULSE_Pos 10UL
|
||||
#define I2S_TX_CTL_WS_PULSE_Msk 0x400UL
|
||||
#define I2S_TX_CTL_OVHDATA_Pos 12UL
|
||||
#define I2S_TX_CTL_OVHDATA_Msk 0x1000UL
|
||||
#define I2S_TX_CTL_WD_EN_Pos 13UL
|
||||
#define I2S_TX_CTL_WD_EN_Msk 0x2000UL
|
||||
#define I2S_TX_CTL_CH_LEN_Pos 16UL
|
||||
#define I2S_TX_CTL_CH_LEN_Msk 0x70000UL
|
||||
#define I2S_TX_CTL_WORD_LEN_Pos 20UL
|
||||
#define I2S_TX_CTL_WORD_LEN_Msk 0x700000UL
|
||||
#define I2S_TX_CTL_SCKO_POL_Pos 24UL
|
||||
#define I2S_TX_CTL_SCKO_POL_Msk 0x1000000UL
|
||||
#define I2S_TX_CTL_SCKI_POL_Pos 25UL
|
||||
#define I2S_TX_CTL_SCKI_POL_Msk 0x2000000UL
|
||||
/* I2S.TX_WATCHDOG */
|
||||
#define I2S_TX_WATCHDOG_WD_COUNTER_Pos 0UL
|
||||
#define I2S_TX_WATCHDOG_WD_COUNTER_Msk 0xFFFFFFFFUL
|
||||
/* I2S.RX_CTL */
|
||||
#define I2S_RX_CTL_B_CLOCK_INV_Pos 3UL
|
||||
#define I2S_RX_CTL_B_CLOCK_INV_Msk 0x8UL
|
||||
#define I2S_RX_CTL_CH_NR_Pos 4UL
|
||||
#define I2S_RX_CTL_CH_NR_Msk 0x70UL
|
||||
#define I2S_RX_CTL_MS_Pos 7UL
|
||||
#define I2S_RX_CTL_MS_Msk 0x80UL
|
||||
#define I2S_RX_CTL_I2S_MODE_Pos 8UL
|
||||
#define I2S_RX_CTL_I2S_MODE_Msk 0x300UL
|
||||
#define I2S_RX_CTL_WS_PULSE_Pos 10UL
|
||||
#define I2S_RX_CTL_WS_PULSE_Msk 0x400UL
|
||||
#define I2S_RX_CTL_WD_EN_Pos 13UL
|
||||
#define I2S_RX_CTL_WD_EN_Msk 0x2000UL
|
||||
#define I2S_RX_CTL_CH_LEN_Pos 16UL
|
||||
#define I2S_RX_CTL_CH_LEN_Msk 0x70000UL
|
||||
#define I2S_RX_CTL_WORD_LEN_Pos 20UL
|
||||
#define I2S_RX_CTL_WORD_LEN_Msk 0x700000UL
|
||||
#define I2S_RX_CTL_BIT_EXTENSION_Pos 23UL
|
||||
#define I2S_RX_CTL_BIT_EXTENSION_Msk 0x800000UL
|
||||
#define I2S_RX_CTL_SCKO_POL_Pos 24UL
|
||||
#define I2S_RX_CTL_SCKO_POL_Msk 0x1000000UL
|
||||
#define I2S_RX_CTL_SCKI_POL_Pos 25UL
|
||||
#define I2S_RX_CTL_SCKI_POL_Msk 0x2000000UL
|
||||
/* I2S.RX_WATCHDOG */
|
||||
#define I2S_RX_WATCHDOG_WD_COUNTER_Pos 0UL
|
||||
#define I2S_RX_WATCHDOG_WD_COUNTER_Msk 0xFFFFFFFFUL
|
||||
/* I2S.TX_FIFO_CTL */
|
||||
#define I2S_TX_FIFO_CTL_TRIGGER_LEVEL_Pos 0UL
|
||||
#define I2S_TX_FIFO_CTL_TRIGGER_LEVEL_Msk 0xFFUL
|
||||
#define I2S_TX_FIFO_CTL_CLEAR_Pos 16UL
|
||||
#define I2S_TX_FIFO_CTL_CLEAR_Msk 0x10000UL
|
||||
#define I2S_TX_FIFO_CTL_FREEZE_Pos 17UL
|
||||
#define I2S_TX_FIFO_CTL_FREEZE_Msk 0x20000UL
|
||||
/* I2S.TX_FIFO_STATUS */
|
||||
#define I2S_TX_FIFO_STATUS_USED_Pos 0UL
|
||||
#define I2S_TX_FIFO_STATUS_USED_Msk 0x1FFUL
|
||||
#define I2S_TX_FIFO_STATUS_RD_PTR_Pos 16UL
|
||||
#define I2S_TX_FIFO_STATUS_RD_PTR_Msk 0xFF0000UL
|
||||
#define I2S_TX_FIFO_STATUS_WR_PTR_Pos 24UL
|
||||
#define I2S_TX_FIFO_STATUS_WR_PTR_Msk 0xFF000000UL
|
||||
/* I2S.TX_FIFO_WR */
|
||||
#define I2S_TX_FIFO_WR_DATA_Pos 0UL
|
||||
#define I2S_TX_FIFO_WR_DATA_Msk 0xFFFFFFFFUL
|
||||
/* I2S.RX_FIFO_CTL */
|
||||
#define I2S_RX_FIFO_CTL_TRIGGER_LEVEL_Pos 0UL
|
||||
#define I2S_RX_FIFO_CTL_TRIGGER_LEVEL_Msk 0xFFUL
|
||||
#define I2S_RX_FIFO_CTL_CLEAR_Pos 16UL
|
||||
#define I2S_RX_FIFO_CTL_CLEAR_Msk 0x10000UL
|
||||
#define I2S_RX_FIFO_CTL_FREEZE_Pos 17UL
|
||||
#define I2S_RX_FIFO_CTL_FREEZE_Msk 0x20000UL
|
||||
/* I2S.RX_FIFO_STATUS */
|
||||
#define I2S_RX_FIFO_STATUS_USED_Pos 0UL
|
||||
#define I2S_RX_FIFO_STATUS_USED_Msk 0x1FFUL
|
||||
#define I2S_RX_FIFO_STATUS_RD_PTR_Pos 16UL
|
||||
#define I2S_RX_FIFO_STATUS_RD_PTR_Msk 0xFF0000UL
|
||||
#define I2S_RX_FIFO_STATUS_WR_PTR_Pos 24UL
|
||||
#define I2S_RX_FIFO_STATUS_WR_PTR_Msk 0xFF000000UL
|
||||
/* I2S.RX_FIFO_RD */
|
||||
#define I2S_RX_FIFO_RD_DATA_Pos 0UL
|
||||
#define I2S_RX_FIFO_RD_DATA_Msk 0xFFFFFFFFUL
|
||||
/* I2S.RX_FIFO_RD_SILENT */
|
||||
#define I2S_RX_FIFO_RD_SILENT_DATA_Pos 0UL
|
||||
#define I2S_RX_FIFO_RD_SILENT_DATA_Msk 0xFFFFFFFFUL
|
||||
/* I2S.INTR */
|
||||
#define I2S_INTR_TX_TRIGGER_Pos 0UL
|
||||
#define I2S_INTR_TX_TRIGGER_Msk 0x1UL
|
||||
#define I2S_INTR_TX_NOT_FULL_Pos 1UL
|
||||
#define I2S_INTR_TX_NOT_FULL_Msk 0x2UL
|
||||
#define I2S_INTR_TX_EMPTY_Pos 4UL
|
||||
#define I2S_INTR_TX_EMPTY_Msk 0x10UL
|
||||
#define I2S_INTR_TX_OVERFLOW_Pos 5UL
|
||||
#define I2S_INTR_TX_OVERFLOW_Msk 0x20UL
|
||||
#define I2S_INTR_TX_UNDERFLOW_Pos 6UL
|
||||
#define I2S_INTR_TX_UNDERFLOW_Msk 0x40UL
|
||||
#define I2S_INTR_TX_WD_Pos 8UL
|
||||
#define I2S_INTR_TX_WD_Msk 0x100UL
|
||||
#define I2S_INTR_RX_TRIGGER_Pos 16UL
|
||||
#define I2S_INTR_RX_TRIGGER_Msk 0x10000UL
|
||||
#define I2S_INTR_RX_NOT_EMPTY_Pos 18UL
|
||||
#define I2S_INTR_RX_NOT_EMPTY_Msk 0x40000UL
|
||||
#define I2S_INTR_RX_FULL_Pos 19UL
|
||||
#define I2S_INTR_RX_FULL_Msk 0x80000UL
|
||||
#define I2S_INTR_RX_OVERFLOW_Pos 21UL
|
||||
#define I2S_INTR_RX_OVERFLOW_Msk 0x200000UL
|
||||
#define I2S_INTR_RX_UNDERFLOW_Pos 22UL
|
||||
#define I2S_INTR_RX_UNDERFLOW_Msk 0x400000UL
|
||||
#define I2S_INTR_RX_WD_Pos 24UL
|
||||
#define I2S_INTR_RX_WD_Msk 0x1000000UL
|
||||
/* I2S.INTR_SET */
|
||||
#define I2S_INTR_SET_TX_TRIGGER_Pos 0UL
|
||||
#define I2S_INTR_SET_TX_TRIGGER_Msk 0x1UL
|
||||
#define I2S_INTR_SET_TX_NOT_FULL_Pos 1UL
|
||||
#define I2S_INTR_SET_TX_NOT_FULL_Msk 0x2UL
|
||||
#define I2S_INTR_SET_TX_EMPTY_Pos 4UL
|
||||
#define I2S_INTR_SET_TX_EMPTY_Msk 0x10UL
|
||||
#define I2S_INTR_SET_TX_OVERFLOW_Pos 5UL
|
||||
#define I2S_INTR_SET_TX_OVERFLOW_Msk 0x20UL
|
||||
#define I2S_INTR_SET_TX_UNDERFLOW_Pos 6UL
|
||||
#define I2S_INTR_SET_TX_UNDERFLOW_Msk 0x40UL
|
||||
#define I2S_INTR_SET_TX_WD_Pos 8UL
|
||||
#define I2S_INTR_SET_TX_WD_Msk 0x100UL
|
||||
#define I2S_INTR_SET_RX_TRIGGER_Pos 16UL
|
||||
#define I2S_INTR_SET_RX_TRIGGER_Msk 0x10000UL
|
||||
#define I2S_INTR_SET_RX_NOT_EMPTY_Pos 18UL
|
||||
#define I2S_INTR_SET_RX_NOT_EMPTY_Msk 0x40000UL
|
||||
#define I2S_INTR_SET_RX_FULL_Pos 19UL
|
||||
#define I2S_INTR_SET_RX_FULL_Msk 0x80000UL
|
||||
#define I2S_INTR_SET_RX_OVERFLOW_Pos 21UL
|
||||
#define I2S_INTR_SET_RX_OVERFLOW_Msk 0x200000UL
|
||||
#define I2S_INTR_SET_RX_UNDERFLOW_Pos 22UL
|
||||
#define I2S_INTR_SET_RX_UNDERFLOW_Msk 0x400000UL
|
||||
#define I2S_INTR_SET_RX_WD_Pos 24UL
|
||||
#define I2S_INTR_SET_RX_WD_Msk 0x1000000UL
|
||||
/* I2S.INTR_MASK */
|
||||
#define I2S_INTR_MASK_TX_TRIGGER_Pos 0UL
|
||||
#define I2S_INTR_MASK_TX_TRIGGER_Msk 0x1UL
|
||||
#define I2S_INTR_MASK_TX_NOT_FULL_Pos 1UL
|
||||
#define I2S_INTR_MASK_TX_NOT_FULL_Msk 0x2UL
|
||||
#define I2S_INTR_MASK_TX_EMPTY_Pos 4UL
|
||||
#define I2S_INTR_MASK_TX_EMPTY_Msk 0x10UL
|
||||
#define I2S_INTR_MASK_TX_OVERFLOW_Pos 5UL
|
||||
#define I2S_INTR_MASK_TX_OVERFLOW_Msk 0x20UL
|
||||
#define I2S_INTR_MASK_TX_UNDERFLOW_Pos 6UL
|
||||
#define I2S_INTR_MASK_TX_UNDERFLOW_Msk 0x40UL
|
||||
#define I2S_INTR_MASK_TX_WD_Pos 8UL
|
||||
#define I2S_INTR_MASK_TX_WD_Msk 0x100UL
|
||||
#define I2S_INTR_MASK_RX_TRIGGER_Pos 16UL
|
||||
#define I2S_INTR_MASK_RX_TRIGGER_Msk 0x10000UL
|
||||
#define I2S_INTR_MASK_RX_NOT_EMPTY_Pos 18UL
|
||||
#define I2S_INTR_MASK_RX_NOT_EMPTY_Msk 0x40000UL
|
||||
#define I2S_INTR_MASK_RX_FULL_Pos 19UL
|
||||
#define I2S_INTR_MASK_RX_FULL_Msk 0x80000UL
|
||||
#define I2S_INTR_MASK_RX_OVERFLOW_Pos 21UL
|
||||
#define I2S_INTR_MASK_RX_OVERFLOW_Msk 0x200000UL
|
||||
#define I2S_INTR_MASK_RX_UNDERFLOW_Pos 22UL
|
||||
#define I2S_INTR_MASK_RX_UNDERFLOW_Msk 0x400000UL
|
||||
#define I2S_INTR_MASK_RX_WD_Pos 24UL
|
||||
#define I2S_INTR_MASK_RX_WD_Msk 0x1000000UL
|
||||
/* I2S.INTR_MASKED */
|
||||
#define I2S_INTR_MASKED_TX_TRIGGER_Pos 0UL
|
||||
#define I2S_INTR_MASKED_TX_TRIGGER_Msk 0x1UL
|
||||
#define I2S_INTR_MASKED_TX_NOT_FULL_Pos 1UL
|
||||
#define I2S_INTR_MASKED_TX_NOT_FULL_Msk 0x2UL
|
||||
#define I2S_INTR_MASKED_TX_EMPTY_Pos 4UL
|
||||
#define I2S_INTR_MASKED_TX_EMPTY_Msk 0x10UL
|
||||
#define I2S_INTR_MASKED_TX_OVERFLOW_Pos 5UL
|
||||
#define I2S_INTR_MASKED_TX_OVERFLOW_Msk 0x20UL
|
||||
#define I2S_INTR_MASKED_TX_UNDERFLOW_Pos 6UL
|
||||
#define I2S_INTR_MASKED_TX_UNDERFLOW_Msk 0x40UL
|
||||
#define I2S_INTR_MASKED_TX_WD_Pos 8UL
|
||||
#define I2S_INTR_MASKED_TX_WD_Msk 0x100UL
|
||||
#define I2S_INTR_MASKED_RX_TRIGGER_Pos 16UL
|
||||
#define I2S_INTR_MASKED_RX_TRIGGER_Msk 0x10000UL
|
||||
#define I2S_INTR_MASKED_RX_NOT_EMPTY_Pos 18UL
|
||||
#define I2S_INTR_MASKED_RX_NOT_EMPTY_Msk 0x40000UL
|
||||
#define I2S_INTR_MASKED_RX_FULL_Pos 19UL
|
||||
#define I2S_INTR_MASKED_RX_FULL_Msk 0x80000UL
|
||||
#define I2S_INTR_MASKED_RX_OVERFLOW_Pos 21UL
|
||||
#define I2S_INTR_MASKED_RX_OVERFLOW_Msk 0x200000UL
|
||||
#define I2S_INTR_MASKED_RX_UNDERFLOW_Pos 22UL
|
||||
#define I2S_INTR_MASKED_RX_UNDERFLOW_Msk 0x400000UL
|
||||
#define I2S_INTR_MASKED_RX_WD_Pos 24UL
|
||||
#define I2S_INTR_MASKED_RX_WD_Msk 0x1000000UL
|
||||
|
||||
|
||||
#endif /* _CYIP_I2S_H_ */
|
||||
|
||||
|
||||
/* [] END OF FILE */
|
||||
|
|
@ -1,124 +0,0 @@
|
|||
/***************************************************************************//**
|
||||
* \file cyip_ipc.h
|
||||
*
|
||||
* \brief
|
||||
* IPC IP definitions
|
||||
*
|
||||
* \note
|
||||
* Generator version: 1.3.0.1146
|
||||
* Database revision: rev#1050929
|
||||
*
|
||||
********************************************************************************
|
||||
* \copyright
|
||||
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
|
||||
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _CYIP_IPC_H_
|
||||
#define _CYIP_IPC_H_
|
||||
|
||||
#include "cyip_headers.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* IPC
|
||||
*******************************************************************************/
|
||||
|
||||
#define IPC_STRUCT_SECTION_SIZE 0x00000020UL
|
||||
#define IPC_INTR_STRUCT_SECTION_SIZE 0x00000020UL
|
||||
#define IPC_SECTION_SIZE 0x00010000UL
|
||||
|
||||
/**
|
||||
* \brief IPC structure (IPC_STRUCT)
|
||||
*/
|
||||
typedef struct {
|
||||
__IM uint32_t ACQUIRE; /*!< 0x00000000 IPC acquire */
|
||||
__OM uint32_t RELEASE; /*!< 0x00000004 IPC release */
|
||||
__OM uint32_t NOTIFY; /*!< 0x00000008 IPC notification */
|
||||
__IOM uint32_t DATA; /*!< 0x0000000C IPC data */
|
||||
__IM uint32_t LOCK_STATUS; /*!< 0x00000010 IPC lock status */
|
||||
__IM uint32_t RESERVED[3];
|
||||
} IPC_STRUCT_V1_Type; /*!< Size = 32 (0x20) */
|
||||
|
||||
/**
|
||||
* \brief IPC interrupt structure (IPC_INTR_STRUCT)
|
||||
*/
|
||||
typedef struct {
|
||||
__IOM uint32_t INTR; /*!< 0x00000000 Interrupt */
|
||||
__IOM uint32_t INTR_SET; /*!< 0x00000004 Interrupt set */
|
||||
__IOM uint32_t INTR_MASK; /*!< 0x00000008 Interrupt mask */
|
||||
__IM uint32_t INTR_MASKED; /*!< 0x0000000C Interrupt masked */
|
||||
__IM uint32_t RESERVED[4];
|
||||
} IPC_INTR_STRUCT_V1_Type; /*!< Size = 32 (0x20) */
|
||||
|
||||
/**
|
||||
* \brief IPC (IPC)
|
||||
*/
|
||||
typedef struct {
|
||||
IPC_STRUCT_V1_Type STRUCT[16]; /*!< 0x00000000 IPC structure */
|
||||
__IM uint32_t RESERVED[896];
|
||||
IPC_INTR_STRUCT_V1_Type INTR_STRUCT[16]; /*!< 0x00001000 IPC interrupt structure */
|
||||
} IPC_V1_Type; /*!< Size = 4608 (0x1200) */
|
||||
|
||||
|
||||
/* IPC_STRUCT.ACQUIRE */
|
||||
#define IPC_STRUCT_ACQUIRE_P_Pos 0UL
|
||||
#define IPC_STRUCT_ACQUIRE_P_Msk 0x1UL
|
||||
#define IPC_STRUCT_ACQUIRE_NS_Pos 1UL
|
||||
#define IPC_STRUCT_ACQUIRE_NS_Msk 0x2UL
|
||||
#define IPC_STRUCT_ACQUIRE_PC_Pos 4UL
|
||||
#define IPC_STRUCT_ACQUIRE_PC_Msk 0xF0UL
|
||||
#define IPC_STRUCT_ACQUIRE_MS_Pos 8UL
|
||||
#define IPC_STRUCT_ACQUIRE_MS_Msk 0xF00UL
|
||||
#define IPC_STRUCT_ACQUIRE_SUCCESS_Pos 31UL
|
||||
#define IPC_STRUCT_ACQUIRE_SUCCESS_Msk 0x80000000UL
|
||||
/* IPC_STRUCT.RELEASE */
|
||||
#define IPC_STRUCT_RELEASE_INTR_RELEASE_Pos 0UL
|
||||
#define IPC_STRUCT_RELEASE_INTR_RELEASE_Msk 0xFFFFUL
|
||||
/* IPC_STRUCT.NOTIFY */
|
||||
#define IPC_STRUCT_NOTIFY_INTR_NOTIFY_Pos 0UL
|
||||
#define IPC_STRUCT_NOTIFY_INTR_NOTIFY_Msk 0xFFFFUL
|
||||
/* IPC_STRUCT.DATA */
|
||||
#define IPC_STRUCT_DATA_DATA_Pos 0UL
|
||||
#define IPC_STRUCT_DATA_DATA_Msk 0xFFFFFFFFUL
|
||||
/* IPC_STRUCT.LOCK_STATUS */
|
||||
#define IPC_STRUCT_LOCK_STATUS_P_Pos 0UL
|
||||
#define IPC_STRUCT_LOCK_STATUS_P_Msk 0x1UL
|
||||
#define IPC_STRUCT_LOCK_STATUS_NS_Pos 1UL
|
||||
#define IPC_STRUCT_LOCK_STATUS_NS_Msk 0x2UL
|
||||
#define IPC_STRUCT_LOCK_STATUS_PC_Pos 4UL
|
||||
#define IPC_STRUCT_LOCK_STATUS_PC_Msk 0xF0UL
|
||||
#define IPC_STRUCT_LOCK_STATUS_MS_Pos 8UL
|
||||
#define IPC_STRUCT_LOCK_STATUS_MS_Msk 0xF00UL
|
||||
#define IPC_STRUCT_LOCK_STATUS_ACQUIRED_Pos 31UL
|
||||
#define IPC_STRUCT_LOCK_STATUS_ACQUIRED_Msk 0x80000000UL
|
||||
|
||||
|
||||
/* IPC_INTR_STRUCT.INTR */
|
||||
#define IPC_INTR_STRUCT_INTR_RELEASE_Pos 0UL
|
||||
#define IPC_INTR_STRUCT_INTR_RELEASE_Msk 0xFFFFUL
|
||||
#define IPC_INTR_STRUCT_INTR_NOTIFY_Pos 16UL
|
||||
#define IPC_INTR_STRUCT_INTR_NOTIFY_Msk 0xFFFF0000UL
|
||||
/* IPC_INTR_STRUCT.INTR_SET */
|
||||
#define IPC_INTR_STRUCT_INTR_SET_RELEASE_Pos 0UL
|
||||
#define IPC_INTR_STRUCT_INTR_SET_RELEASE_Msk 0xFFFFUL
|
||||
#define IPC_INTR_STRUCT_INTR_SET_NOTIFY_Pos 16UL
|
||||
#define IPC_INTR_STRUCT_INTR_SET_NOTIFY_Msk 0xFFFF0000UL
|
||||
/* IPC_INTR_STRUCT.INTR_MASK */
|
||||
#define IPC_INTR_STRUCT_INTR_MASK_RELEASE_Pos 0UL
|
||||
#define IPC_INTR_STRUCT_INTR_MASK_RELEASE_Msk 0xFFFFUL
|
||||
#define IPC_INTR_STRUCT_INTR_MASK_NOTIFY_Pos 16UL
|
||||
#define IPC_INTR_STRUCT_INTR_MASK_NOTIFY_Msk 0xFFFF0000UL
|
||||
/* IPC_INTR_STRUCT.INTR_MASKED */
|
||||
#define IPC_INTR_STRUCT_INTR_MASKED_RELEASE_Pos 0UL
|
||||
#define IPC_INTR_STRUCT_INTR_MASKED_RELEASE_Msk 0xFFFFUL
|
||||
#define IPC_INTR_STRUCT_INTR_MASKED_NOTIFY_Pos 16UL
|
||||
#define IPC_INTR_STRUCT_INTR_MASKED_NOTIFY_Msk 0xFFFF0000UL
|
||||
|
||||
|
||||
#endif /* _CYIP_IPC_H_ */
|
||||
|
||||
|
||||
/* [] END OF FILE */
|
||||
|
|
@ -1,128 +0,0 @@
|
|||
/***************************************************************************//**
|
||||
* \file cyip_ipc_v2.h
|
||||
*
|
||||
* \brief
|
||||
* IPC IP definitions
|
||||
*
|
||||
* \note
|
||||
* Generator version: 1.3.0.1146
|
||||
* Database revision: rev#1050929
|
||||
*
|
||||
********************************************************************************
|
||||
* \copyright
|
||||
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
|
||||
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _CYIP_IPC_V2_H_
|
||||
#define _CYIP_IPC_V2_H_
|
||||
|
||||
#include "cyip_headers.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* IPC
|
||||
*******************************************************************************/
|
||||
|
||||
#define IPC_STRUCT_V2_SECTION_SIZE 0x00000020UL
|
||||
#define IPC_INTR_STRUCT_V2_SECTION_SIZE 0x00000020UL
|
||||
#define IPC_V2_SECTION_SIZE 0x00010000UL
|
||||
|
||||
/**
|
||||
* \brief IPC structure (IPC_STRUCT)
|
||||
*/
|
||||
typedef struct {
|
||||
__IM uint32_t ACQUIRE; /*!< 0x00000000 IPC acquire */
|
||||
__OM uint32_t RELEASE; /*!< 0x00000004 IPC release */
|
||||
__OM uint32_t NOTIFY; /*!< 0x00000008 IPC notification */
|
||||
__IOM uint32_t DATA0; /*!< 0x0000000C IPC data 0 */
|
||||
__IOM uint32_t DATA1; /*!< 0x00000010 IPC data 1 */
|
||||
__IM uint32_t RESERVED[2];
|
||||
__IM uint32_t LOCK_STATUS; /*!< 0x0000001C IPC lock status */
|
||||
} IPC_STRUCT_V2_Type; /*!< Size = 32 (0x20) */
|
||||
|
||||
/**
|
||||
* \brief IPC interrupt structure (IPC_INTR_STRUCT)
|
||||
*/
|
||||
typedef struct {
|
||||
__IOM uint32_t INTR; /*!< 0x00000000 Interrupt */
|
||||
__IOM uint32_t INTR_SET; /*!< 0x00000004 Interrupt set */
|
||||
__IOM uint32_t INTR_MASK; /*!< 0x00000008 Interrupt mask */
|
||||
__IM uint32_t INTR_MASKED; /*!< 0x0000000C Interrupt masked */
|
||||
__IM uint32_t RESERVED[4];
|
||||
} IPC_INTR_STRUCT_V2_Type; /*!< Size = 32 (0x20) */
|
||||
|
||||
/**
|
||||
* \brief IPC (IPC)
|
||||
*/
|
||||
typedef struct {
|
||||
IPC_STRUCT_V2_Type STRUCT[16]; /*!< 0x00000000 IPC structure */
|
||||
__IM uint32_t RESERVED[896];
|
||||
IPC_INTR_STRUCT_V2_Type INTR_STRUCT[16]; /*!< 0x00001000 IPC interrupt structure */
|
||||
} IPC_V2_Type; /*!< Size = 4608 (0x1200) */
|
||||
|
||||
|
||||
/* IPC_STRUCT.ACQUIRE */
|
||||
#define IPC_STRUCT_V2_ACQUIRE_P_Pos 0UL
|
||||
#define IPC_STRUCT_V2_ACQUIRE_P_Msk 0x1UL
|
||||
#define IPC_STRUCT_V2_ACQUIRE_NS_Pos 1UL
|
||||
#define IPC_STRUCT_V2_ACQUIRE_NS_Msk 0x2UL
|
||||
#define IPC_STRUCT_V2_ACQUIRE_PC_Pos 4UL
|
||||
#define IPC_STRUCT_V2_ACQUIRE_PC_Msk 0xF0UL
|
||||
#define IPC_STRUCT_V2_ACQUIRE_MS_Pos 8UL
|
||||
#define IPC_STRUCT_V2_ACQUIRE_MS_Msk 0xF00UL
|
||||
#define IPC_STRUCT_V2_ACQUIRE_SUCCESS_Pos 31UL
|
||||
#define IPC_STRUCT_V2_ACQUIRE_SUCCESS_Msk 0x80000000UL
|
||||
/* IPC_STRUCT.RELEASE */
|
||||
#define IPC_STRUCT_V2_RELEASE_INTR_RELEASE_Pos 0UL
|
||||
#define IPC_STRUCT_V2_RELEASE_INTR_RELEASE_Msk 0xFFFFUL
|
||||
/* IPC_STRUCT.NOTIFY */
|
||||
#define IPC_STRUCT_V2_NOTIFY_INTR_NOTIFY_Pos 0UL
|
||||
#define IPC_STRUCT_V2_NOTIFY_INTR_NOTIFY_Msk 0xFFFFUL
|
||||
/* IPC_STRUCT.DATA0 */
|
||||
#define IPC_STRUCT_V2_DATA0_DATA_Pos 0UL
|
||||
#define IPC_STRUCT_V2_DATA0_DATA_Msk 0xFFFFFFFFUL
|
||||
/* IPC_STRUCT.DATA1 */
|
||||
#define IPC_STRUCT_V2_DATA1_DATA_Pos 0UL
|
||||
#define IPC_STRUCT_V2_DATA1_DATA_Msk 0xFFFFFFFFUL
|
||||
/* IPC_STRUCT.LOCK_STATUS */
|
||||
#define IPC_STRUCT_V2_LOCK_STATUS_P_Pos 0UL
|
||||
#define IPC_STRUCT_V2_LOCK_STATUS_P_Msk 0x1UL
|
||||
#define IPC_STRUCT_V2_LOCK_STATUS_NS_Pos 1UL
|
||||
#define IPC_STRUCT_V2_LOCK_STATUS_NS_Msk 0x2UL
|
||||
#define IPC_STRUCT_V2_LOCK_STATUS_PC_Pos 4UL
|
||||
#define IPC_STRUCT_V2_LOCK_STATUS_PC_Msk 0xF0UL
|
||||
#define IPC_STRUCT_V2_LOCK_STATUS_MS_Pos 8UL
|
||||
#define IPC_STRUCT_V2_LOCK_STATUS_MS_Msk 0xF00UL
|
||||
#define IPC_STRUCT_V2_LOCK_STATUS_ACQUIRED_Pos 31UL
|
||||
#define IPC_STRUCT_V2_LOCK_STATUS_ACQUIRED_Msk 0x80000000UL
|
||||
|
||||
|
||||
/* IPC_INTR_STRUCT.INTR */
|
||||
#define IPC_INTR_STRUCT_V2_INTR_RELEASE_Pos 0UL
|
||||
#define IPC_INTR_STRUCT_V2_INTR_RELEASE_Msk 0xFFFFUL
|
||||
#define IPC_INTR_STRUCT_V2_INTR_NOTIFY_Pos 16UL
|
||||
#define IPC_INTR_STRUCT_V2_INTR_NOTIFY_Msk 0xFFFF0000UL
|
||||
/* IPC_INTR_STRUCT.INTR_SET */
|
||||
#define IPC_INTR_STRUCT_V2_INTR_SET_RELEASE_Pos 0UL
|
||||
#define IPC_INTR_STRUCT_V2_INTR_SET_RELEASE_Msk 0xFFFFUL
|
||||
#define IPC_INTR_STRUCT_V2_INTR_SET_NOTIFY_Pos 16UL
|
||||
#define IPC_INTR_STRUCT_V2_INTR_SET_NOTIFY_Msk 0xFFFF0000UL
|
||||
/* IPC_INTR_STRUCT.INTR_MASK */
|
||||
#define IPC_INTR_STRUCT_V2_INTR_MASK_RELEASE_Pos 0UL
|
||||
#define IPC_INTR_STRUCT_V2_INTR_MASK_RELEASE_Msk 0xFFFFUL
|
||||
#define IPC_INTR_STRUCT_V2_INTR_MASK_NOTIFY_Pos 16UL
|
||||
#define IPC_INTR_STRUCT_V2_INTR_MASK_NOTIFY_Msk 0xFFFF0000UL
|
||||
/* IPC_INTR_STRUCT.INTR_MASKED */
|
||||
#define IPC_INTR_STRUCT_V2_INTR_MASKED_RELEASE_Pos 0UL
|
||||
#define IPC_INTR_STRUCT_V2_INTR_MASKED_RELEASE_Msk 0xFFFFUL
|
||||
#define IPC_INTR_STRUCT_V2_INTR_MASKED_NOTIFY_Pos 16UL
|
||||
#define IPC_INTR_STRUCT_V2_INTR_MASKED_NOTIFY_Msk 0xFFFF0000UL
|
||||
|
||||
|
||||
#endif /* _CYIP_IPC_V2_H_ */
|
||||
|
||||
|
||||
/* [] END OF FILE */
|
||||
|
|
@ -1,93 +0,0 @@
|
|||
/***************************************************************************//**
|
||||
* \file cyip_lcd.h
|
||||
*
|
||||
* \brief
|
||||
* LCD IP definitions
|
||||
*
|
||||
* \note
|
||||
* Generator version: 1.3.0.1146
|
||||
* Database revision: rev#1050929
|
||||
*
|
||||
********************************************************************************
|
||||
* \copyright
|
||||
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
|
||||
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _CYIP_LCD_H_
|
||||
#define _CYIP_LCD_H_
|
||||
|
||||
#include "cyip_headers.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* LCD
|
||||
*******************************************************************************/
|
||||
|
||||
#define LCD_SECTION_SIZE 0x00010000UL
|
||||
|
||||
/**
|
||||
* \brief LCD Controller Block (LCD)
|
||||
*/
|
||||
typedef struct {
|
||||
__IM uint32_t ID; /*!< 0x00000000 ID & Revision */
|
||||
__IOM uint32_t DIVIDER; /*!< 0x00000004 LCD Divider Register */
|
||||
__IOM uint32_t CONTROL; /*!< 0x00000008 LCD Configuration Register */
|
||||
__IM uint32_t RESERVED[61];
|
||||
__IOM uint32_t DATA0[8]; /*!< 0x00000100 LCD Pin Data Registers */
|
||||
__IM uint32_t RESERVED1[56];
|
||||
__IOM uint32_t DATA1[8]; /*!< 0x00000200 LCD Pin Data Registers */
|
||||
__IM uint32_t RESERVED2[56];
|
||||
__IOM uint32_t DATA2[8]; /*!< 0x00000300 LCD Pin Data Registers */
|
||||
__IM uint32_t RESERVED3[56];
|
||||
__IOM uint32_t DATA3[8]; /*!< 0x00000400 LCD Pin Data Registers */
|
||||
} LCD_V1_Type; /*!< Size = 1056 (0x420) */
|
||||
|
||||
|
||||
/* LCD.ID */
|
||||
#define LCD_ID_ID_Pos 0UL
|
||||
#define LCD_ID_ID_Msk 0xFFFFUL
|
||||
#define LCD_ID_REVISION_Pos 16UL
|
||||
#define LCD_ID_REVISION_Msk 0xFFFF0000UL
|
||||
/* LCD.DIVIDER */
|
||||
#define LCD_DIVIDER_SUBFR_DIV_Pos 0UL
|
||||
#define LCD_DIVIDER_SUBFR_DIV_Msk 0xFFFFUL
|
||||
#define LCD_DIVIDER_DEAD_DIV_Pos 16UL
|
||||
#define LCD_DIVIDER_DEAD_DIV_Msk 0xFFFF0000UL
|
||||
/* LCD.CONTROL */
|
||||
#define LCD_CONTROL_LS_EN_Pos 0UL
|
||||
#define LCD_CONTROL_LS_EN_Msk 0x1UL
|
||||
#define LCD_CONTROL_HS_EN_Pos 1UL
|
||||
#define LCD_CONTROL_HS_EN_Msk 0x2UL
|
||||
#define LCD_CONTROL_LCD_MODE_Pos 2UL
|
||||
#define LCD_CONTROL_LCD_MODE_Msk 0x4UL
|
||||
#define LCD_CONTROL_TYPE_Pos 3UL
|
||||
#define LCD_CONTROL_TYPE_Msk 0x8UL
|
||||
#define LCD_CONTROL_OP_MODE_Pos 4UL
|
||||
#define LCD_CONTROL_OP_MODE_Msk 0x10UL
|
||||
#define LCD_CONTROL_BIAS_Pos 5UL
|
||||
#define LCD_CONTROL_BIAS_Msk 0x60UL
|
||||
#define LCD_CONTROL_COM_NUM_Pos 8UL
|
||||
#define LCD_CONTROL_COM_NUM_Msk 0xF00UL
|
||||
#define LCD_CONTROL_LS_EN_STAT_Pos 31UL
|
||||
#define LCD_CONTROL_LS_EN_STAT_Msk 0x80000000UL
|
||||
/* LCD.DATA0 */
|
||||
#define LCD_DATA0_DATA_Pos 0UL
|
||||
#define LCD_DATA0_DATA_Msk 0xFFFFFFFFUL
|
||||
/* LCD.DATA1 */
|
||||
#define LCD_DATA1_DATA_Pos 0UL
|
||||
#define LCD_DATA1_DATA_Msk 0xFFFFFFFFUL
|
||||
/* LCD.DATA2 */
|
||||
#define LCD_DATA2_DATA_Pos 0UL
|
||||
#define LCD_DATA2_DATA_Msk 0xFFFFFFFFUL
|
||||
/* LCD.DATA3 */
|
||||
#define LCD_DATA3_DATA_Pos 0UL
|
||||
#define LCD_DATA3_DATA_Msk 0xFFFFFFFFUL
|
||||
|
||||
|
||||
#endif /* _CYIP_LCD_H_ */
|
||||
|
||||
|
||||
/* [] END OF FILE */
|
||||
|
|
@ -1,172 +0,0 @@
|
|||
/***************************************************************************//**
|
||||
* \file cyip_lpcomp.h
|
||||
*
|
||||
* \brief
|
||||
* LPCOMP IP definitions
|
||||
*
|
||||
* \note
|
||||
* Generator version: 1.3.0.1146
|
||||
* Database revision: rev#1050929
|
||||
*
|
||||
********************************************************************************
|
||||
* \copyright
|
||||
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
|
||||
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _CYIP_LPCOMP_H_
|
||||
#define _CYIP_LPCOMP_H_
|
||||
|
||||
#include "cyip_headers.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* LPCOMP
|
||||
*******************************************************************************/
|
||||
|
||||
#define LPCOMP_SECTION_SIZE 0x00010000UL
|
||||
|
||||
/**
|
||||
* \brief Low Power Comparators (LPCOMP)
|
||||
*/
|
||||
typedef struct {
|
||||
__IOM uint32_t CONFIG; /*!< 0x00000000 LPCOMP Configuration Register */
|
||||
__IM uint32_t STATUS; /*!< 0x00000004 LPCOMP Status Register */
|
||||
__IM uint32_t RESERVED[2];
|
||||
__IOM uint32_t INTR; /*!< 0x00000010 LPCOMP Interrupt request register */
|
||||
__IOM uint32_t INTR_SET; /*!< 0x00000014 LPCOMP Interrupt set register */
|
||||
__IOM uint32_t INTR_MASK; /*!< 0x00000018 LPCOMP Interrupt request mask */
|
||||
__IM uint32_t INTR_MASKED; /*!< 0x0000001C LPCOMP Interrupt request masked */
|
||||
__IM uint32_t RESERVED1[8];
|
||||
__IOM uint32_t CMP0_CTRL; /*!< 0x00000040 Comparator 0 control Register */
|
||||
__IM uint32_t RESERVED2[3];
|
||||
__IOM uint32_t CMP0_SW; /*!< 0x00000050 Comparator 0 switch control */
|
||||
__IOM uint32_t CMP0_SW_CLEAR; /*!< 0x00000054 Comparator 0 switch control clear */
|
||||
__IM uint32_t RESERVED3[10];
|
||||
__IOM uint32_t CMP1_CTRL; /*!< 0x00000080 Comparator 1 control Register */
|
||||
__IM uint32_t RESERVED4[3];
|
||||
__IOM uint32_t CMP1_SW; /*!< 0x00000090 Comparator 1 switch control */
|
||||
__IOM uint32_t CMP1_SW_CLEAR; /*!< 0x00000094 Comparator 1 switch control clear */
|
||||
} LPCOMP_V1_Type; /*!< Size = 152 (0x98) */
|
||||
|
||||
|
||||
/* LPCOMP.CONFIG */
|
||||
#define LPCOMP_CONFIG_LPREF_EN_Pos 30UL
|
||||
#define LPCOMP_CONFIG_LPREF_EN_Msk 0x40000000UL
|
||||
#define LPCOMP_CONFIG_ENABLED_Pos 31UL
|
||||
#define LPCOMP_CONFIG_ENABLED_Msk 0x80000000UL
|
||||
/* LPCOMP.STATUS */
|
||||
#define LPCOMP_STATUS_OUT0_Pos 0UL
|
||||
#define LPCOMP_STATUS_OUT0_Msk 0x1UL
|
||||
#define LPCOMP_STATUS_OUT1_Pos 16UL
|
||||
#define LPCOMP_STATUS_OUT1_Msk 0x10000UL
|
||||
/* LPCOMP.INTR */
|
||||
#define LPCOMP_INTR_COMP0_Pos 0UL
|
||||
#define LPCOMP_INTR_COMP0_Msk 0x1UL
|
||||
#define LPCOMP_INTR_COMP1_Pos 1UL
|
||||
#define LPCOMP_INTR_COMP1_Msk 0x2UL
|
||||
/* LPCOMP.INTR_SET */
|
||||
#define LPCOMP_INTR_SET_COMP0_Pos 0UL
|
||||
#define LPCOMP_INTR_SET_COMP0_Msk 0x1UL
|
||||
#define LPCOMP_INTR_SET_COMP1_Pos 1UL
|
||||
#define LPCOMP_INTR_SET_COMP1_Msk 0x2UL
|
||||
/* LPCOMP.INTR_MASK */
|
||||
#define LPCOMP_INTR_MASK_COMP0_MASK_Pos 0UL
|
||||
#define LPCOMP_INTR_MASK_COMP0_MASK_Msk 0x1UL
|
||||
#define LPCOMP_INTR_MASK_COMP1_MASK_Pos 1UL
|
||||
#define LPCOMP_INTR_MASK_COMP1_MASK_Msk 0x2UL
|
||||
/* LPCOMP.INTR_MASKED */
|
||||
#define LPCOMP_INTR_MASKED_COMP0_MASKED_Pos 0UL
|
||||
#define LPCOMP_INTR_MASKED_COMP0_MASKED_Msk 0x1UL
|
||||
#define LPCOMP_INTR_MASKED_COMP1_MASKED_Pos 1UL
|
||||
#define LPCOMP_INTR_MASKED_COMP1_MASKED_Msk 0x2UL
|
||||
/* LPCOMP.CMP0_CTRL */
|
||||
#define LPCOMP_CMP0_CTRL_MODE0_Pos 0UL
|
||||
#define LPCOMP_CMP0_CTRL_MODE0_Msk 0x3UL
|
||||
#define LPCOMP_CMP0_CTRL_HYST0_Pos 5UL
|
||||
#define LPCOMP_CMP0_CTRL_HYST0_Msk 0x20UL
|
||||
#define LPCOMP_CMP0_CTRL_INTTYPE0_Pos 6UL
|
||||
#define LPCOMP_CMP0_CTRL_INTTYPE0_Msk 0xC0UL
|
||||
#define LPCOMP_CMP0_CTRL_DSI_BYPASS0_Pos 10UL
|
||||
#define LPCOMP_CMP0_CTRL_DSI_BYPASS0_Msk 0x400UL
|
||||
#define LPCOMP_CMP0_CTRL_DSI_LEVEL0_Pos 11UL
|
||||
#define LPCOMP_CMP0_CTRL_DSI_LEVEL0_Msk 0x800UL
|
||||
/* LPCOMP.CMP0_SW */
|
||||
#define LPCOMP_CMP0_SW_CMP0_IP0_Pos 0UL
|
||||
#define LPCOMP_CMP0_SW_CMP0_IP0_Msk 0x1UL
|
||||
#define LPCOMP_CMP0_SW_CMP0_AP0_Pos 1UL
|
||||
#define LPCOMP_CMP0_SW_CMP0_AP0_Msk 0x2UL
|
||||
#define LPCOMP_CMP0_SW_CMP0_BP0_Pos 2UL
|
||||
#define LPCOMP_CMP0_SW_CMP0_BP0_Msk 0x4UL
|
||||
#define LPCOMP_CMP0_SW_CMP0_IN0_Pos 4UL
|
||||
#define LPCOMP_CMP0_SW_CMP0_IN0_Msk 0x10UL
|
||||
#define LPCOMP_CMP0_SW_CMP0_AN0_Pos 5UL
|
||||
#define LPCOMP_CMP0_SW_CMP0_AN0_Msk 0x20UL
|
||||
#define LPCOMP_CMP0_SW_CMP0_BN0_Pos 6UL
|
||||
#define LPCOMP_CMP0_SW_CMP0_BN0_Msk 0x40UL
|
||||
#define LPCOMP_CMP0_SW_CMP0_VN0_Pos 7UL
|
||||
#define LPCOMP_CMP0_SW_CMP0_VN0_Msk 0x80UL
|
||||
/* LPCOMP.CMP0_SW_CLEAR */
|
||||
#define LPCOMP_CMP0_SW_CLEAR_CMP0_IP0_Pos 0UL
|
||||
#define LPCOMP_CMP0_SW_CLEAR_CMP0_IP0_Msk 0x1UL
|
||||
#define LPCOMP_CMP0_SW_CLEAR_CMP0_AP0_Pos 1UL
|
||||
#define LPCOMP_CMP0_SW_CLEAR_CMP0_AP0_Msk 0x2UL
|
||||
#define LPCOMP_CMP0_SW_CLEAR_CMP0_BP0_Pos 2UL
|
||||
#define LPCOMP_CMP0_SW_CLEAR_CMP0_BP0_Msk 0x4UL
|
||||
#define LPCOMP_CMP0_SW_CLEAR_CMP0_IN0_Pos 4UL
|
||||
#define LPCOMP_CMP0_SW_CLEAR_CMP0_IN0_Msk 0x10UL
|
||||
#define LPCOMP_CMP0_SW_CLEAR_CMP0_AN0_Pos 5UL
|
||||
#define LPCOMP_CMP0_SW_CLEAR_CMP0_AN0_Msk 0x20UL
|
||||
#define LPCOMP_CMP0_SW_CLEAR_CMP0_BN0_Pos 6UL
|
||||
#define LPCOMP_CMP0_SW_CLEAR_CMP0_BN0_Msk 0x40UL
|
||||
#define LPCOMP_CMP0_SW_CLEAR_CMP0_VN0_Pos 7UL
|
||||
#define LPCOMP_CMP0_SW_CLEAR_CMP0_VN0_Msk 0x80UL
|
||||
/* LPCOMP.CMP1_CTRL */
|
||||
#define LPCOMP_CMP1_CTRL_MODE1_Pos 0UL
|
||||
#define LPCOMP_CMP1_CTRL_MODE1_Msk 0x3UL
|
||||
#define LPCOMP_CMP1_CTRL_HYST1_Pos 5UL
|
||||
#define LPCOMP_CMP1_CTRL_HYST1_Msk 0x20UL
|
||||
#define LPCOMP_CMP1_CTRL_INTTYPE1_Pos 6UL
|
||||
#define LPCOMP_CMP1_CTRL_INTTYPE1_Msk 0xC0UL
|
||||
#define LPCOMP_CMP1_CTRL_DSI_BYPASS1_Pos 10UL
|
||||
#define LPCOMP_CMP1_CTRL_DSI_BYPASS1_Msk 0x400UL
|
||||
#define LPCOMP_CMP1_CTRL_DSI_LEVEL1_Pos 11UL
|
||||
#define LPCOMP_CMP1_CTRL_DSI_LEVEL1_Msk 0x800UL
|
||||
/* LPCOMP.CMP1_SW */
|
||||
#define LPCOMP_CMP1_SW_CMP1_IP1_Pos 0UL
|
||||
#define LPCOMP_CMP1_SW_CMP1_IP1_Msk 0x1UL
|
||||
#define LPCOMP_CMP1_SW_CMP1_AP1_Pos 1UL
|
||||
#define LPCOMP_CMP1_SW_CMP1_AP1_Msk 0x2UL
|
||||
#define LPCOMP_CMP1_SW_CMP1_BP1_Pos 2UL
|
||||
#define LPCOMP_CMP1_SW_CMP1_BP1_Msk 0x4UL
|
||||
#define LPCOMP_CMP1_SW_CMP1_IN1_Pos 4UL
|
||||
#define LPCOMP_CMP1_SW_CMP1_IN1_Msk 0x10UL
|
||||
#define LPCOMP_CMP1_SW_CMP1_AN1_Pos 5UL
|
||||
#define LPCOMP_CMP1_SW_CMP1_AN1_Msk 0x20UL
|
||||
#define LPCOMP_CMP1_SW_CMP1_BN1_Pos 6UL
|
||||
#define LPCOMP_CMP1_SW_CMP1_BN1_Msk 0x40UL
|
||||
#define LPCOMP_CMP1_SW_CMP1_VN1_Pos 7UL
|
||||
#define LPCOMP_CMP1_SW_CMP1_VN1_Msk 0x80UL
|
||||
/* LPCOMP.CMP1_SW_CLEAR */
|
||||
#define LPCOMP_CMP1_SW_CLEAR_CMP1_IP1_Pos 0UL
|
||||
#define LPCOMP_CMP1_SW_CLEAR_CMP1_IP1_Msk 0x1UL
|
||||
#define LPCOMP_CMP1_SW_CLEAR_CMP1_AP1_Pos 1UL
|
||||
#define LPCOMP_CMP1_SW_CLEAR_CMP1_AP1_Msk 0x2UL
|
||||
#define LPCOMP_CMP1_SW_CLEAR_CMP1_BP1_Pos 2UL
|
||||
#define LPCOMP_CMP1_SW_CLEAR_CMP1_BP1_Msk 0x4UL
|
||||
#define LPCOMP_CMP1_SW_CLEAR_CMP1_IN1_Pos 4UL
|
||||
#define LPCOMP_CMP1_SW_CLEAR_CMP1_IN1_Msk 0x10UL
|
||||
#define LPCOMP_CMP1_SW_CLEAR_CMP1_AN1_Pos 5UL
|
||||
#define LPCOMP_CMP1_SW_CLEAR_CMP1_AN1_Msk 0x20UL
|
||||
#define LPCOMP_CMP1_SW_CLEAR_CMP1_BN1_Pos 6UL
|
||||
#define LPCOMP_CMP1_SW_CLEAR_CMP1_BN1_Msk 0x40UL
|
||||
#define LPCOMP_CMP1_SW_CLEAR_CMP1_VN1_Pos 7UL
|
||||
#define LPCOMP_CMP1_SW_CLEAR_CMP1_VN1_Msk 0x80UL
|
||||
|
||||
|
||||
#endif /* _CYIP_LPCOMP_H_ */
|
||||
|
||||
|
||||
/* [] END OF FILE */
|
||||
|
|
@ -1,131 +0,0 @@
|
|||
/***************************************************************************//**
|
||||
* \file cyip_pass.h
|
||||
*
|
||||
* \brief
|
||||
* PASS IP definitions
|
||||
*
|
||||
* \note
|
||||
* Generator version: 1.3.0.1146
|
||||
* Database revision: rev#1050929
|
||||
*
|
||||
********************************************************************************
|
||||
* \copyright
|
||||
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
|
||||
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _CYIP_PASS_H_
|
||||
#define _CYIP_PASS_H_
|
||||
|
||||
#include "cyip_headers.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* PASS
|
||||
*******************************************************************************/
|
||||
|
||||
#define PASS_AREF_SECTION_SIZE 0x00000100UL
|
||||
#define PASS_SECTION_SIZE 0x00010000UL
|
||||
|
||||
/**
|
||||
* \brief AREF configuration (PASS_AREF)
|
||||
*/
|
||||
typedef struct {
|
||||
__IOM uint32_t AREF_CTRL; /*!< 0x00000000 global AREF control */
|
||||
__IM uint32_t RESERVED[63];
|
||||
} PASS_AREF_V1_Type; /*!< Size = 256 (0x100) */
|
||||
|
||||
/**
|
||||
* \brief PASS top-level MMIO (DSABv2, INTR) (PASS)
|
||||
*/
|
||||
typedef struct {
|
||||
__IM uint32_t INTR_CAUSE; /*!< 0x00000000 Interrupt cause register */
|
||||
__IM uint32_t RESERVED[895];
|
||||
PASS_AREF_V1_Type AREF; /*!< 0x00000E00 AREF configuration */
|
||||
__IOM uint32_t VREF_TRIM0; /*!< 0x00000F00 VREF Trim bits */
|
||||
__IOM uint32_t VREF_TRIM1; /*!< 0x00000F04 VREF Trim bits */
|
||||
__IOM uint32_t VREF_TRIM2; /*!< 0x00000F08 VREF Trim bits */
|
||||
__IOM uint32_t VREF_TRIM3; /*!< 0x00000F0C VREF Trim bits */
|
||||
__IOM uint32_t IZTAT_TRIM0; /*!< 0x00000F10 IZTAT Trim bits */
|
||||
__IOM uint32_t IZTAT_TRIM1; /*!< 0x00000F14 IZTAT Trim bits */
|
||||
__IOM uint32_t IPTAT_TRIM0; /*!< 0x00000F18 IPTAT Trim bits */
|
||||
__IOM uint32_t ICTAT_TRIM0; /*!< 0x00000F1C ICTAT Trim bits */
|
||||
} PASS_V1_Type; /*!< Size = 3872 (0xF20) */
|
||||
|
||||
|
||||
/* PASS_AREF.AREF_CTRL */
|
||||
#define PASS_AREF_AREF_CTRL_AREF_MODE_Pos 0UL
|
||||
#define PASS_AREF_AREF_CTRL_AREF_MODE_Msk 0x1UL
|
||||
#define PASS_AREF_AREF_CTRL_AREF_BIAS_SCALE_Pos 2UL
|
||||
#define PASS_AREF_AREF_CTRL_AREF_BIAS_SCALE_Msk 0xCUL
|
||||
#define PASS_AREF_AREF_CTRL_AREF_RMB_Pos 4UL
|
||||
#define PASS_AREF_AREF_CTRL_AREF_RMB_Msk 0x70UL
|
||||
#define PASS_AREF_AREF_CTRL_CTB_IPTAT_SCALE_Pos 7UL
|
||||
#define PASS_AREF_AREF_CTRL_CTB_IPTAT_SCALE_Msk 0x80UL
|
||||
#define PASS_AREF_AREF_CTRL_CTB_IPTAT_REDIRECT_Pos 8UL
|
||||
#define PASS_AREF_AREF_CTRL_CTB_IPTAT_REDIRECT_Msk 0xFF00UL
|
||||
#define PASS_AREF_AREF_CTRL_IZTAT_SEL_Pos 16UL
|
||||
#define PASS_AREF_AREF_CTRL_IZTAT_SEL_Msk 0x10000UL
|
||||
#define PASS_AREF_AREF_CTRL_CLOCK_PUMP_PERI_SEL_Pos 19UL
|
||||
#define PASS_AREF_AREF_CTRL_CLOCK_PUMP_PERI_SEL_Msk 0x80000UL
|
||||
#define PASS_AREF_AREF_CTRL_VREF_SEL_Pos 20UL
|
||||
#define PASS_AREF_AREF_CTRL_VREF_SEL_Msk 0x300000UL
|
||||
#define PASS_AREF_AREF_CTRL_DEEPSLEEP_MODE_Pos 28UL
|
||||
#define PASS_AREF_AREF_CTRL_DEEPSLEEP_MODE_Msk 0x30000000UL
|
||||
#define PASS_AREF_AREF_CTRL_DEEPSLEEP_ON_Pos 30UL
|
||||
#define PASS_AREF_AREF_CTRL_DEEPSLEEP_ON_Msk 0x40000000UL
|
||||
#define PASS_AREF_AREF_CTRL_ENABLED_Pos 31UL
|
||||
#define PASS_AREF_AREF_CTRL_ENABLED_Msk 0x80000000UL
|
||||
|
||||
|
||||
/* PASS.INTR_CAUSE */
|
||||
#define PASS_INTR_CAUSE_CTB0_INT_Pos 0UL
|
||||
#define PASS_INTR_CAUSE_CTB0_INT_Msk 0x1UL
|
||||
#define PASS_INTR_CAUSE_CTB1_INT_Pos 1UL
|
||||
#define PASS_INTR_CAUSE_CTB1_INT_Msk 0x2UL
|
||||
#define PASS_INTR_CAUSE_CTB2_INT_Pos 2UL
|
||||
#define PASS_INTR_CAUSE_CTB2_INT_Msk 0x4UL
|
||||
#define PASS_INTR_CAUSE_CTB3_INT_Pos 3UL
|
||||
#define PASS_INTR_CAUSE_CTB3_INT_Msk 0x8UL
|
||||
#define PASS_INTR_CAUSE_CTDAC0_INT_Pos 4UL
|
||||
#define PASS_INTR_CAUSE_CTDAC0_INT_Msk 0x10UL
|
||||
#define PASS_INTR_CAUSE_CTDAC1_INT_Pos 5UL
|
||||
#define PASS_INTR_CAUSE_CTDAC1_INT_Msk 0x20UL
|
||||
#define PASS_INTR_CAUSE_CTDAC2_INT_Pos 6UL
|
||||
#define PASS_INTR_CAUSE_CTDAC2_INT_Msk 0x40UL
|
||||
#define PASS_INTR_CAUSE_CTDAC3_INT_Pos 7UL
|
||||
#define PASS_INTR_CAUSE_CTDAC3_INT_Msk 0x80UL
|
||||
/* PASS.VREF_TRIM0 */
|
||||
#define PASS_VREF_TRIM0_VREF_ABS_TRIM_Pos 0UL
|
||||
#define PASS_VREF_TRIM0_VREF_ABS_TRIM_Msk 0xFFUL
|
||||
/* PASS.VREF_TRIM1 */
|
||||
#define PASS_VREF_TRIM1_VREF_TEMPCO_TRIM_Pos 0UL
|
||||
#define PASS_VREF_TRIM1_VREF_TEMPCO_TRIM_Msk 0xFFUL
|
||||
/* PASS.VREF_TRIM2 */
|
||||
#define PASS_VREF_TRIM2_VREF_CURV_TRIM_Pos 0UL
|
||||
#define PASS_VREF_TRIM2_VREF_CURV_TRIM_Msk 0xFFUL
|
||||
/* PASS.VREF_TRIM3 */
|
||||
#define PASS_VREF_TRIM3_VREF_ATTEN_TRIM_Pos 0UL
|
||||
#define PASS_VREF_TRIM3_VREF_ATTEN_TRIM_Msk 0xFUL
|
||||
/* PASS.IZTAT_TRIM0 */
|
||||
#define PASS_IZTAT_TRIM0_IZTAT_ABS_TRIM_Pos 0UL
|
||||
#define PASS_IZTAT_TRIM0_IZTAT_ABS_TRIM_Msk 0xFFUL
|
||||
/* PASS.IZTAT_TRIM1 */
|
||||
#define PASS_IZTAT_TRIM1_IZTAT_TC_TRIM_Pos 0UL
|
||||
#define PASS_IZTAT_TRIM1_IZTAT_TC_TRIM_Msk 0xFFUL
|
||||
/* PASS.IPTAT_TRIM0 */
|
||||
#define PASS_IPTAT_TRIM0_IPTAT_CORE_TRIM_Pos 0UL
|
||||
#define PASS_IPTAT_TRIM0_IPTAT_CORE_TRIM_Msk 0xFUL
|
||||
#define PASS_IPTAT_TRIM0_IPTAT_CTBM_TRIM_Pos 4UL
|
||||
#define PASS_IPTAT_TRIM0_IPTAT_CTBM_TRIM_Msk 0xF0UL
|
||||
/* PASS.ICTAT_TRIM0 */
|
||||
#define PASS_ICTAT_TRIM0_ICTAT_TRIM_Pos 0UL
|
||||
#define PASS_ICTAT_TRIM0_ICTAT_TRIM_Msk 0xFUL
|
||||
|
||||
|
||||
#endif /* _CYIP_PASS_H_ */
|
||||
|
||||
|
||||
/* [] END OF FILE */
|
||||
|
|
@ -1,162 +0,0 @@
|
|||
/***************************************************************************//**
|
||||
* \file cyip_pdm.h
|
||||
*
|
||||
* \brief
|
||||
* PDM IP definitions
|
||||
*
|
||||
* \note
|
||||
* Generator version: 1.3.0.1146
|
||||
* Database revision: rev#1050929
|
||||
*
|
||||
********************************************************************************
|
||||
* \copyright
|
||||
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
|
||||
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _CYIP_PDM_H_
|
||||
#define _CYIP_PDM_H_
|
||||
|
||||
#include "cyip_headers.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* PDM
|
||||
*******************************************************************************/
|
||||
|
||||
#define PDM_SECTION_SIZE 0x00001000UL
|
||||
|
||||
/**
|
||||
* \brief PDM registers (PDM)
|
||||
*/
|
||||
typedef struct {
|
||||
__IOM uint32_t CTL; /*!< 0x00000000 Control */
|
||||
__IM uint32_t RESERVED[3];
|
||||
__IOM uint32_t CLOCK_CTL; /*!< 0x00000010 Clock control */
|
||||
__IOM uint32_t MODE_CTL; /*!< 0x00000014 Mode control */
|
||||
__IOM uint32_t DATA_CTL; /*!< 0x00000018 Data control */
|
||||
__IM uint32_t RESERVED1;
|
||||
__IOM uint32_t CMD; /*!< 0x00000020 Command */
|
||||
__IM uint32_t RESERVED2[7];
|
||||
__IOM uint32_t TR_CTL; /*!< 0x00000040 Trigger control */
|
||||
__IM uint32_t RESERVED3[175];
|
||||
__IOM uint32_t RX_FIFO_CTL; /*!< 0x00000300 RX FIFO control */
|
||||
__IM uint32_t RX_FIFO_STATUS; /*!< 0x00000304 RX FIFO status */
|
||||
__IM uint32_t RX_FIFO_RD; /*!< 0x00000308 RX FIFO read */
|
||||
__IM uint32_t RX_FIFO_RD_SILENT; /*!< 0x0000030C RX FIFO silent read */
|
||||
__IM uint32_t RESERVED4[764];
|
||||
__IOM uint32_t INTR; /*!< 0x00000F00 Interrupt register */
|
||||
__IOM uint32_t INTR_SET; /*!< 0x00000F04 Interrupt set register */
|
||||
__IOM uint32_t INTR_MASK; /*!< 0x00000F08 Interrupt mask register */
|
||||
__IM uint32_t INTR_MASKED; /*!< 0x00000F0C Interrupt masked register */
|
||||
} PDM_V1_Type; /*!< Size = 3856 (0xF10) */
|
||||
|
||||
|
||||
/* PDM.CTL */
|
||||
#define PDM_CTL_PGA_R_Pos 0UL
|
||||
#define PDM_CTL_PGA_R_Msk 0xFUL
|
||||
#define PDM_CTL_PGA_L_Pos 8UL
|
||||
#define PDM_CTL_PGA_L_Msk 0xF00UL
|
||||
#define PDM_CTL_SOFT_MUTE_Pos 16UL
|
||||
#define PDM_CTL_SOFT_MUTE_Msk 0x10000UL
|
||||
#define PDM_CTL_STEP_SEL_Pos 17UL
|
||||
#define PDM_CTL_STEP_SEL_Msk 0x20000UL
|
||||
#define PDM_CTL_ENABLED_Pos 31UL
|
||||
#define PDM_CTL_ENABLED_Msk 0x80000000UL
|
||||
/* PDM.CLOCK_CTL */
|
||||
#define PDM_CLOCK_CTL_CLK_CLOCK_DIV_Pos 0UL
|
||||
#define PDM_CLOCK_CTL_CLK_CLOCK_DIV_Msk 0x3UL
|
||||
#define PDM_CLOCK_CTL_MCLKQ_CLOCK_DIV_Pos 4UL
|
||||
#define PDM_CLOCK_CTL_MCLKQ_CLOCK_DIV_Msk 0x30UL
|
||||
#define PDM_CLOCK_CTL_CKO_CLOCK_DIV_Pos 8UL
|
||||
#define PDM_CLOCK_CTL_CKO_CLOCK_DIV_Msk 0xF00UL
|
||||
#define PDM_CLOCK_CTL_SINC_RATE_Pos 16UL
|
||||
#define PDM_CLOCK_CTL_SINC_RATE_Msk 0x7F0000UL
|
||||
/* PDM.MODE_CTL */
|
||||
#define PDM_MODE_CTL_PCM_CH_SET_Pos 0UL
|
||||
#define PDM_MODE_CTL_PCM_CH_SET_Msk 0x3UL
|
||||
#define PDM_MODE_CTL_SWAP_LR_Pos 2UL
|
||||
#define PDM_MODE_CTL_SWAP_LR_Msk 0x4UL
|
||||
#define PDM_MODE_CTL_S_CYCLES_Pos 8UL
|
||||
#define PDM_MODE_CTL_S_CYCLES_Msk 0x700UL
|
||||
#define PDM_MODE_CTL_CKO_DELAY_Pos 16UL
|
||||
#define PDM_MODE_CTL_CKO_DELAY_Msk 0x70000UL
|
||||
#define PDM_MODE_CTL_HPF_GAIN_Pos 24UL
|
||||
#define PDM_MODE_CTL_HPF_GAIN_Msk 0xF000000UL
|
||||
#define PDM_MODE_CTL_HPF_EN_N_Pos 28UL
|
||||
#define PDM_MODE_CTL_HPF_EN_N_Msk 0x10000000UL
|
||||
/* PDM.DATA_CTL */
|
||||
#define PDM_DATA_CTL_WORD_LEN_Pos 0UL
|
||||
#define PDM_DATA_CTL_WORD_LEN_Msk 0x3UL
|
||||
#define PDM_DATA_CTL_BIT_EXTENSION_Pos 8UL
|
||||
#define PDM_DATA_CTL_BIT_EXTENSION_Msk 0x100UL
|
||||
/* PDM.CMD */
|
||||
#define PDM_CMD_STREAM_EN_Pos 0UL
|
||||
#define PDM_CMD_STREAM_EN_Msk 0x1UL
|
||||
/* PDM.TR_CTL */
|
||||
#define PDM_TR_CTL_RX_REQ_EN_Pos 16UL
|
||||
#define PDM_TR_CTL_RX_REQ_EN_Msk 0x10000UL
|
||||
/* PDM.RX_FIFO_CTL */
|
||||
#define PDM_RX_FIFO_CTL_TRIGGER_LEVEL_Pos 0UL
|
||||
#define PDM_RX_FIFO_CTL_TRIGGER_LEVEL_Msk 0xFFUL
|
||||
#define PDM_RX_FIFO_CTL_CLEAR_Pos 16UL
|
||||
#define PDM_RX_FIFO_CTL_CLEAR_Msk 0x10000UL
|
||||
#define PDM_RX_FIFO_CTL_FREEZE_Pos 17UL
|
||||
#define PDM_RX_FIFO_CTL_FREEZE_Msk 0x20000UL
|
||||
/* PDM.RX_FIFO_STATUS */
|
||||
#define PDM_RX_FIFO_STATUS_USED_Pos 0UL
|
||||
#define PDM_RX_FIFO_STATUS_USED_Msk 0xFFUL
|
||||
#define PDM_RX_FIFO_STATUS_RD_PTR_Pos 16UL
|
||||
#define PDM_RX_FIFO_STATUS_RD_PTR_Msk 0xFF0000UL
|
||||
#define PDM_RX_FIFO_STATUS_WR_PTR_Pos 24UL
|
||||
#define PDM_RX_FIFO_STATUS_WR_PTR_Msk 0xFF000000UL
|
||||
/* PDM.RX_FIFO_RD */
|
||||
#define PDM_RX_FIFO_RD_DATA_Pos 0UL
|
||||
#define PDM_RX_FIFO_RD_DATA_Msk 0xFFFFFFFFUL
|
||||
/* PDM.RX_FIFO_RD_SILENT */
|
||||
#define PDM_RX_FIFO_RD_SILENT_DATA_Pos 0UL
|
||||
#define PDM_RX_FIFO_RD_SILENT_DATA_Msk 0xFFFFFFFFUL
|
||||
/* PDM.INTR */
|
||||
#define PDM_INTR_RX_TRIGGER_Pos 16UL
|
||||
#define PDM_INTR_RX_TRIGGER_Msk 0x10000UL
|
||||
#define PDM_INTR_RX_NOT_EMPTY_Pos 18UL
|
||||
#define PDM_INTR_RX_NOT_EMPTY_Msk 0x40000UL
|
||||
#define PDM_INTR_RX_OVERFLOW_Pos 21UL
|
||||
#define PDM_INTR_RX_OVERFLOW_Msk 0x200000UL
|
||||
#define PDM_INTR_RX_UNDERFLOW_Pos 22UL
|
||||
#define PDM_INTR_RX_UNDERFLOW_Msk 0x400000UL
|
||||
/* PDM.INTR_SET */
|
||||
#define PDM_INTR_SET_RX_TRIGGER_Pos 16UL
|
||||
#define PDM_INTR_SET_RX_TRIGGER_Msk 0x10000UL
|
||||
#define PDM_INTR_SET_RX_NOT_EMPTY_Pos 18UL
|
||||
#define PDM_INTR_SET_RX_NOT_EMPTY_Msk 0x40000UL
|
||||
#define PDM_INTR_SET_RX_OVERFLOW_Pos 21UL
|
||||
#define PDM_INTR_SET_RX_OVERFLOW_Msk 0x200000UL
|
||||
#define PDM_INTR_SET_RX_UNDERFLOW_Pos 22UL
|
||||
#define PDM_INTR_SET_RX_UNDERFLOW_Msk 0x400000UL
|
||||
/* PDM.INTR_MASK */
|
||||
#define PDM_INTR_MASK_RX_TRIGGER_Pos 16UL
|
||||
#define PDM_INTR_MASK_RX_TRIGGER_Msk 0x10000UL
|
||||
#define PDM_INTR_MASK_RX_NOT_EMPTY_Pos 18UL
|
||||
#define PDM_INTR_MASK_RX_NOT_EMPTY_Msk 0x40000UL
|
||||
#define PDM_INTR_MASK_RX_OVERFLOW_Pos 21UL
|
||||
#define PDM_INTR_MASK_RX_OVERFLOW_Msk 0x200000UL
|
||||
#define PDM_INTR_MASK_RX_UNDERFLOW_Pos 22UL
|
||||
#define PDM_INTR_MASK_RX_UNDERFLOW_Msk 0x400000UL
|
||||
/* PDM.INTR_MASKED */
|
||||
#define PDM_INTR_MASKED_RX_TRIGGER_Pos 16UL
|
||||
#define PDM_INTR_MASKED_RX_TRIGGER_Msk 0x10000UL
|
||||
#define PDM_INTR_MASKED_RX_NOT_EMPTY_Pos 18UL
|
||||
#define PDM_INTR_MASKED_RX_NOT_EMPTY_Msk 0x40000UL
|
||||
#define PDM_INTR_MASKED_RX_OVERFLOW_Pos 21UL
|
||||
#define PDM_INTR_MASKED_RX_OVERFLOW_Msk 0x200000UL
|
||||
#define PDM_INTR_MASKED_RX_UNDERFLOW_Pos 22UL
|
||||
#define PDM_INTR_MASKED_RX_UNDERFLOW_Msk 0x400000UL
|
||||
|
||||
|
||||
#endif /* _CYIP_PDM_H_ */
|
||||
|
||||
|
||||
/* [] END OF FILE */
|
||||
|
|
@ -1,483 +0,0 @@
|
|||
/***************************************************************************//**
|
||||
* \file cyip_peri.h
|
||||
*
|
||||
* \brief
|
||||
* PERI IP definitions
|
||||
*
|
||||
* \note
|
||||
* Generator version: 1.3.0.1146
|
||||
* Database revision: rev#1050929
|
||||
*
|
||||
********************************************************************************
|
||||
* \copyright
|
||||
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
|
||||
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _CYIP_PERI_H_
|
||||
#define _CYIP_PERI_H_
|
||||
|
||||
#include "cyip_headers.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* PERI
|
||||
*******************************************************************************/
|
||||
|
||||
#define PERI_GR_SECTION_SIZE 0x00000040UL
|
||||
#define PERI_TR_GR_SECTION_SIZE 0x00000200UL
|
||||
#define PERI_PPU_PR_SECTION_SIZE 0x00000040UL
|
||||
#define PERI_PPU_GR_SECTION_SIZE 0x00000040UL
|
||||
#define PERI_GR_PPU_SL_SECTION_SIZE 0x00000040UL
|
||||
#define PERI_GR_PPU_RG_SECTION_SIZE 0x00000040UL
|
||||
#define PERI_SECTION_SIZE 0x00010000UL
|
||||
|
||||
/**
|
||||
* \brief Peripheral group structure (PERI_GR)
|
||||
*/
|
||||
typedef struct {
|
||||
__IOM uint32_t CLOCK_CTL; /*!< 0x00000000 Clock control */
|
||||
__IM uint32_t RESERVED[7];
|
||||
__IOM uint32_t SL_CTL; /*!< 0x00000020 Slave control */
|
||||
__IOM uint32_t TIMEOUT_CTL; /*!< 0x00000024 Timeout control */
|
||||
__IM uint32_t RESERVED1[6];
|
||||
} PERI_GR_V1_Type; /*!< Size = 64 (0x40) */
|
||||
|
||||
/**
|
||||
* \brief Trigger group (PERI_TR_GR)
|
||||
*/
|
||||
typedef struct {
|
||||
__IOM uint32_t TR_OUT_CTL[128]; /*!< 0x00000000 Trigger control register */
|
||||
} PERI_TR_GR_V1_Type; /*!< Size = 512 (0x200) */
|
||||
|
||||
/**
|
||||
* \brief PPU structure with programmable address (PERI_PPU_PR)
|
||||
*/
|
||||
typedef struct {
|
||||
__IOM uint32_t ADDR0; /*!< 0x00000000 PPU region address 0 (slave structure) */
|
||||
__IOM uint32_t ATT0; /*!< 0x00000004 PPU region attributes 0 (slave structure) */
|
||||
__IM uint32_t RESERVED[6];
|
||||
__IM uint32_t ADDR1; /*!< 0x00000020 PPU region address 1 (master structure) */
|
||||
__IOM uint32_t ATT1; /*!< 0x00000024 PPU region attributes 1 (master structure) */
|
||||
__IM uint32_t RESERVED1[6];
|
||||
} PERI_PPU_PR_V1_Type; /*!< Size = 64 (0x40) */
|
||||
|
||||
/**
|
||||
* \brief PPU structure with fixed/constant address for a peripheral group (PERI_PPU_GR)
|
||||
*/
|
||||
typedef struct {
|
||||
__IM uint32_t ADDR0; /*!< 0x00000000 PPU region address 0 (slave structure) */
|
||||
__IOM uint32_t ATT0; /*!< 0x00000004 PPU region attributes 0 (slave structure) */
|
||||
__IM uint32_t RESERVED[6];
|
||||
__IM uint32_t ADDR1; /*!< 0x00000020 PPU region address 1 (master structure) */
|
||||
__IOM uint32_t ATT1; /*!< 0x00000024 PPU region attributes 1 (master structure) */
|
||||
__IM uint32_t RESERVED1[6];
|
||||
} PERI_PPU_GR_V1_Type; /*!< Size = 64 (0x40) */
|
||||
|
||||
/**
|
||||
* \brief PPU structure with fixed/constant address for a specific slave (PERI_GR_PPU_SL)
|
||||
*/
|
||||
typedef struct {
|
||||
__IM uint32_t ADDR0; /*!< 0x00000000 PPU region address 0 (slave structure) */
|
||||
__IOM uint32_t ATT0; /*!< 0x00000004 PPU region attributes 0 (slave structure) */
|
||||
__IM uint32_t RESERVED[6];
|
||||
__IM uint32_t ADDR1; /*!< 0x00000020 PPU region address 1 (master structure) */
|
||||
__IOM uint32_t ATT1; /*!< 0x00000024 PPU region attributes 1 (master structure) */
|
||||
__IM uint32_t RESERVED1[6];
|
||||
} PERI_GR_PPU_SL_V1_Type; /*!< Size = 64 (0x40) */
|
||||
|
||||
/**
|
||||
* \brief PPU structure with fixed/constant address for a specific region (PERI_GR_PPU_RG)
|
||||
*/
|
||||
typedef struct {
|
||||
__IM uint32_t ADDR0; /*!< 0x00000000 PPU region address 0 (slave structure) */
|
||||
__IOM uint32_t ATT0; /*!< 0x00000004 PPU region attributes 0 (slave structure) */
|
||||
__IM uint32_t RESERVED[6];
|
||||
__IM uint32_t ADDR1; /*!< 0x00000020 PPU region address 1 (master structure) */
|
||||
__IOM uint32_t ATT1; /*!< 0x00000024 PPU region attributes 1 (master structure) */
|
||||
__IM uint32_t RESERVED1[6];
|
||||
} PERI_GR_PPU_RG_V1_Type; /*!< Size = 64 (0x40) */
|
||||
|
||||
/**
|
||||
* \brief Peripheral interconnect (PERI)
|
||||
*/
|
||||
typedef struct {
|
||||
PERI_GR_V1_Type GR[16]; /*!< 0x00000000 Peripheral group structure */
|
||||
__IOM uint32_t DIV_CMD; /*!< 0x00000400 Divider command register */
|
||||
__IM uint32_t RESERVED[255];
|
||||
__IOM uint32_t DIV_8_CTL[64]; /*!< 0x00000800 Divider control register (for 8.0 divider) */
|
||||
__IOM uint32_t DIV_16_CTL[64]; /*!< 0x00000900 Divider control register (for 16.0 divider) */
|
||||
__IOM uint32_t DIV_16_5_CTL[64]; /*!< 0x00000A00 Divider control register (for 16.5 divider) */
|
||||
__IOM uint32_t DIV_24_5_CTL[63]; /*!< 0x00000B00 Divider control register (for 24.5 divider) */
|
||||
__IM uint32_t RESERVED1;
|
||||
__IOM uint32_t CLOCK_CTL[128]; /*!< 0x00000C00 Clock control register */
|
||||
__IM uint32_t RESERVED2[128];
|
||||
__IOM uint32_t TR_CMD; /*!< 0x00001000 Trigger command register */
|
||||
__IM uint32_t RESERVED3[1023];
|
||||
PERI_TR_GR_V1_Type TR_GR[16]; /*!< 0x00002000 Trigger group */
|
||||
PERI_PPU_PR_V1_Type PPU_PR[32]; /*!< 0x00004000 PPU structure with programmable address */
|
||||
__IM uint32_t RESERVED4[512];
|
||||
PERI_PPU_GR_V1_Type PPU_GR[16]; /*!< 0x00005000 PPU structure with fixed/constant address for a peripheral
|
||||
group */
|
||||
} PERI_V1_Type; /*!< Size = 21504 (0x5400) */
|
||||
|
||||
|
||||
/* PERI_GR.CLOCK_CTL */
|
||||
#define PERI_GR_CLOCK_CTL_INT8_DIV_Pos 8UL
|
||||
#define PERI_GR_CLOCK_CTL_INT8_DIV_Msk 0xFF00UL
|
||||
/* PERI_GR.SL_CTL */
|
||||
#define PERI_GR_SL_CTL_ENABLED_0_Pos 0UL
|
||||
#define PERI_GR_SL_CTL_ENABLED_0_Msk 0x1UL
|
||||
#define PERI_GR_SL_CTL_ENABLED_1_Pos 1UL
|
||||
#define PERI_GR_SL_CTL_ENABLED_1_Msk 0x2UL
|
||||
#define PERI_GR_SL_CTL_ENABLED_2_Pos 2UL
|
||||
#define PERI_GR_SL_CTL_ENABLED_2_Msk 0x4UL
|
||||
#define PERI_GR_SL_CTL_ENABLED_3_Pos 3UL
|
||||
#define PERI_GR_SL_CTL_ENABLED_3_Msk 0x8UL
|
||||
#define PERI_GR_SL_CTL_ENABLED_4_Pos 4UL
|
||||
#define PERI_GR_SL_CTL_ENABLED_4_Msk 0x10UL
|
||||
#define PERI_GR_SL_CTL_ENABLED_5_Pos 5UL
|
||||
#define PERI_GR_SL_CTL_ENABLED_5_Msk 0x20UL
|
||||
#define PERI_GR_SL_CTL_ENABLED_6_Pos 6UL
|
||||
#define PERI_GR_SL_CTL_ENABLED_6_Msk 0x40UL
|
||||
#define PERI_GR_SL_CTL_ENABLED_7_Pos 7UL
|
||||
#define PERI_GR_SL_CTL_ENABLED_7_Msk 0x80UL
|
||||
#define PERI_GR_SL_CTL_ENABLED_8_Pos 8UL
|
||||
#define PERI_GR_SL_CTL_ENABLED_8_Msk 0x100UL
|
||||
#define PERI_GR_SL_CTL_ENABLED_9_Pos 9UL
|
||||
#define PERI_GR_SL_CTL_ENABLED_9_Msk 0x200UL
|
||||
#define PERI_GR_SL_CTL_ENABLED_10_Pos 10UL
|
||||
#define PERI_GR_SL_CTL_ENABLED_10_Msk 0x400UL
|
||||
#define PERI_GR_SL_CTL_ENABLED_11_Pos 11UL
|
||||
#define PERI_GR_SL_CTL_ENABLED_11_Msk 0x800UL
|
||||
#define PERI_GR_SL_CTL_ENABLED_12_Pos 12UL
|
||||
#define PERI_GR_SL_CTL_ENABLED_12_Msk 0x1000UL
|
||||
#define PERI_GR_SL_CTL_ENABLED_13_Pos 13UL
|
||||
#define PERI_GR_SL_CTL_ENABLED_13_Msk 0x2000UL
|
||||
#define PERI_GR_SL_CTL_ENABLED_14_Pos 14UL
|
||||
#define PERI_GR_SL_CTL_ENABLED_14_Msk 0x4000UL
|
||||
#define PERI_GR_SL_CTL_ENABLED_15_Pos 15UL
|
||||
#define PERI_GR_SL_CTL_ENABLED_15_Msk 0x8000UL
|
||||
/* PERI_GR.TIMEOUT_CTL */
|
||||
#define PERI_GR_TIMEOUT_CTL_TIMEOUT_Pos 0UL
|
||||
#define PERI_GR_TIMEOUT_CTL_TIMEOUT_Msk 0xFFFFUL
|
||||
|
||||
|
||||
/* PERI_TR_GR.TR_OUT_CTL */
|
||||
#define PERI_TR_GR_TR_OUT_CTL_TR_SEL_Pos 0UL
|
||||
#define PERI_TR_GR_TR_OUT_CTL_TR_SEL_Msk 0xFFUL
|
||||
#define PERI_TR_GR_TR_OUT_CTL_TR_INV_Pos 8UL
|
||||
#define PERI_TR_GR_TR_OUT_CTL_TR_INV_Msk 0x100UL
|
||||
#define PERI_TR_GR_TR_OUT_CTL_TR_EDGE_Pos 9UL
|
||||
#define PERI_TR_GR_TR_OUT_CTL_TR_EDGE_Msk 0x200UL
|
||||
|
||||
|
||||
/* PERI_PPU_PR.ADDR0 */
|
||||
#define PERI_PPU_PR_ADDR0_SUBREGION_DISABLE_Pos 0UL
|
||||
#define PERI_PPU_PR_ADDR0_SUBREGION_DISABLE_Msk 0xFFUL
|
||||
#define PERI_PPU_PR_ADDR0_ADDR24_Pos 8UL
|
||||
#define PERI_PPU_PR_ADDR0_ADDR24_Msk 0xFFFFFF00UL
|
||||
/* PERI_PPU_PR.ATT0 */
|
||||
#define PERI_PPU_PR_ATT0_UR_Pos 0UL
|
||||
#define PERI_PPU_PR_ATT0_UR_Msk 0x1UL
|
||||
#define PERI_PPU_PR_ATT0_UW_Pos 1UL
|
||||
#define PERI_PPU_PR_ATT0_UW_Msk 0x2UL
|
||||
#define PERI_PPU_PR_ATT0_UX_Pos 2UL
|
||||
#define PERI_PPU_PR_ATT0_UX_Msk 0x4UL
|
||||
#define PERI_PPU_PR_ATT0_PR_Pos 3UL
|
||||
#define PERI_PPU_PR_ATT0_PR_Msk 0x8UL
|
||||
#define PERI_PPU_PR_ATT0_PW_Pos 4UL
|
||||
#define PERI_PPU_PR_ATT0_PW_Msk 0x10UL
|
||||
#define PERI_PPU_PR_ATT0_PX_Pos 5UL
|
||||
#define PERI_PPU_PR_ATT0_PX_Msk 0x20UL
|
||||
#define PERI_PPU_PR_ATT0_NS_Pos 6UL
|
||||
#define PERI_PPU_PR_ATT0_NS_Msk 0x40UL
|
||||
#define PERI_PPU_PR_ATT0_PC_MASK_0_Pos 8UL
|
||||
#define PERI_PPU_PR_ATT0_PC_MASK_0_Msk 0x100UL
|
||||
#define PERI_PPU_PR_ATT0_PC_MASK_15_TO_1_Pos 9UL
|
||||
#define PERI_PPU_PR_ATT0_PC_MASK_15_TO_1_Msk 0xFFFE00UL
|
||||
#define PERI_PPU_PR_ATT0_REGION_SIZE_Pos 24UL
|
||||
#define PERI_PPU_PR_ATT0_REGION_SIZE_Msk 0x1F000000UL
|
||||
#define PERI_PPU_PR_ATT0_PC_MATCH_Pos 30UL
|
||||
#define PERI_PPU_PR_ATT0_PC_MATCH_Msk 0x40000000UL
|
||||
#define PERI_PPU_PR_ATT0_ENABLED_Pos 31UL
|
||||
#define PERI_PPU_PR_ATT0_ENABLED_Msk 0x80000000UL
|
||||
/* PERI_PPU_PR.ADDR1 */
|
||||
#define PERI_PPU_PR_ADDR1_SUBREGION_DISABLE_Pos 0UL
|
||||
#define PERI_PPU_PR_ADDR1_SUBREGION_DISABLE_Msk 0xFFUL
|
||||
#define PERI_PPU_PR_ADDR1_ADDR24_Pos 8UL
|
||||
#define PERI_PPU_PR_ADDR1_ADDR24_Msk 0xFFFFFF00UL
|
||||
/* PERI_PPU_PR.ATT1 */
|
||||
#define PERI_PPU_PR_ATT1_UR_Pos 0UL
|
||||
#define PERI_PPU_PR_ATT1_UR_Msk 0x1UL
|
||||
#define PERI_PPU_PR_ATT1_UW_Pos 1UL
|
||||
#define PERI_PPU_PR_ATT1_UW_Msk 0x2UL
|
||||
#define PERI_PPU_PR_ATT1_UX_Pos 2UL
|
||||
#define PERI_PPU_PR_ATT1_UX_Msk 0x4UL
|
||||
#define PERI_PPU_PR_ATT1_PR_Pos 3UL
|
||||
#define PERI_PPU_PR_ATT1_PR_Msk 0x8UL
|
||||
#define PERI_PPU_PR_ATT1_PW_Pos 4UL
|
||||
#define PERI_PPU_PR_ATT1_PW_Msk 0x10UL
|
||||
#define PERI_PPU_PR_ATT1_PX_Pos 5UL
|
||||
#define PERI_PPU_PR_ATT1_PX_Msk 0x20UL
|
||||
#define PERI_PPU_PR_ATT1_NS_Pos 6UL
|
||||
#define PERI_PPU_PR_ATT1_NS_Msk 0x40UL
|
||||
#define PERI_PPU_PR_ATT1_PC_MASK_0_Pos 8UL
|
||||
#define PERI_PPU_PR_ATT1_PC_MASK_0_Msk 0x100UL
|
||||
#define PERI_PPU_PR_ATT1_PC_MASK_15_TO_1_Pos 9UL
|
||||
#define PERI_PPU_PR_ATT1_PC_MASK_15_TO_1_Msk 0xFFFE00UL
|
||||
#define PERI_PPU_PR_ATT1_REGION_SIZE_Pos 24UL
|
||||
#define PERI_PPU_PR_ATT1_REGION_SIZE_Msk 0x1F000000UL
|
||||
#define PERI_PPU_PR_ATT1_PC_MATCH_Pos 30UL
|
||||
#define PERI_PPU_PR_ATT1_PC_MATCH_Msk 0x40000000UL
|
||||
#define PERI_PPU_PR_ATT1_ENABLED_Pos 31UL
|
||||
#define PERI_PPU_PR_ATT1_ENABLED_Msk 0x80000000UL
|
||||
|
||||
|
||||
/* PERI_PPU_GR.ADDR0 */
|
||||
#define PERI_PPU_GR_ADDR0_SUBREGION_DISABLE_Pos 0UL
|
||||
#define PERI_PPU_GR_ADDR0_SUBREGION_DISABLE_Msk 0xFFUL
|
||||
#define PERI_PPU_GR_ADDR0_ADDR24_Pos 8UL
|
||||
#define PERI_PPU_GR_ADDR0_ADDR24_Msk 0xFFFFFF00UL
|
||||
/* PERI_PPU_GR.ATT0 */
|
||||
#define PERI_PPU_GR_ATT0_UR_Pos 0UL
|
||||
#define PERI_PPU_GR_ATT0_UR_Msk 0x1UL
|
||||
#define PERI_PPU_GR_ATT0_UW_Pos 1UL
|
||||
#define PERI_PPU_GR_ATT0_UW_Msk 0x2UL
|
||||
#define PERI_PPU_GR_ATT0_UX_Pos 2UL
|
||||
#define PERI_PPU_GR_ATT0_UX_Msk 0x4UL
|
||||
#define PERI_PPU_GR_ATT0_PR_Pos 3UL
|
||||
#define PERI_PPU_GR_ATT0_PR_Msk 0x8UL
|
||||
#define PERI_PPU_GR_ATT0_PW_Pos 4UL
|
||||
#define PERI_PPU_GR_ATT0_PW_Msk 0x10UL
|
||||
#define PERI_PPU_GR_ATT0_PX_Pos 5UL
|
||||
#define PERI_PPU_GR_ATT0_PX_Msk 0x20UL
|
||||
#define PERI_PPU_GR_ATT0_NS_Pos 6UL
|
||||
#define PERI_PPU_GR_ATT0_NS_Msk 0x40UL
|
||||
#define PERI_PPU_GR_ATT0_PC_MASK_0_Pos 8UL
|
||||
#define PERI_PPU_GR_ATT0_PC_MASK_0_Msk 0x100UL
|
||||
#define PERI_PPU_GR_ATT0_PC_MASK_15_TO_1_Pos 9UL
|
||||
#define PERI_PPU_GR_ATT0_PC_MASK_15_TO_1_Msk 0xFFFE00UL
|
||||
#define PERI_PPU_GR_ATT0_REGION_SIZE_Pos 24UL
|
||||
#define PERI_PPU_GR_ATT0_REGION_SIZE_Msk 0x1F000000UL
|
||||
#define PERI_PPU_GR_ATT0_PC_MATCH_Pos 30UL
|
||||
#define PERI_PPU_GR_ATT0_PC_MATCH_Msk 0x40000000UL
|
||||
#define PERI_PPU_GR_ATT0_ENABLED_Pos 31UL
|
||||
#define PERI_PPU_GR_ATT0_ENABLED_Msk 0x80000000UL
|
||||
/* PERI_PPU_GR.ADDR1 */
|
||||
#define PERI_PPU_GR_ADDR1_SUBREGION_DISABLE_Pos 0UL
|
||||
#define PERI_PPU_GR_ADDR1_SUBREGION_DISABLE_Msk 0xFFUL
|
||||
#define PERI_PPU_GR_ADDR1_ADDR24_Pos 8UL
|
||||
#define PERI_PPU_GR_ADDR1_ADDR24_Msk 0xFFFFFF00UL
|
||||
/* PERI_PPU_GR.ATT1 */
|
||||
#define PERI_PPU_GR_ATT1_UR_Pos 0UL
|
||||
#define PERI_PPU_GR_ATT1_UR_Msk 0x1UL
|
||||
#define PERI_PPU_GR_ATT1_UW_Pos 1UL
|
||||
#define PERI_PPU_GR_ATT1_UW_Msk 0x2UL
|
||||
#define PERI_PPU_GR_ATT1_UX_Pos 2UL
|
||||
#define PERI_PPU_GR_ATT1_UX_Msk 0x4UL
|
||||
#define PERI_PPU_GR_ATT1_PR_Pos 3UL
|
||||
#define PERI_PPU_GR_ATT1_PR_Msk 0x8UL
|
||||
#define PERI_PPU_GR_ATT1_PW_Pos 4UL
|
||||
#define PERI_PPU_GR_ATT1_PW_Msk 0x10UL
|
||||
#define PERI_PPU_GR_ATT1_PX_Pos 5UL
|
||||
#define PERI_PPU_GR_ATT1_PX_Msk 0x20UL
|
||||
#define PERI_PPU_GR_ATT1_NS_Pos 6UL
|
||||
#define PERI_PPU_GR_ATT1_NS_Msk 0x40UL
|
||||
#define PERI_PPU_GR_ATT1_PC_MASK_0_Pos 8UL
|
||||
#define PERI_PPU_GR_ATT1_PC_MASK_0_Msk 0x100UL
|
||||
#define PERI_PPU_GR_ATT1_PC_MASK_15_TO_1_Pos 9UL
|
||||
#define PERI_PPU_GR_ATT1_PC_MASK_15_TO_1_Msk 0xFFFE00UL
|
||||
#define PERI_PPU_GR_ATT1_REGION_SIZE_Pos 24UL
|
||||
#define PERI_PPU_GR_ATT1_REGION_SIZE_Msk 0x1F000000UL
|
||||
#define PERI_PPU_GR_ATT1_PC_MATCH_Pos 30UL
|
||||
#define PERI_PPU_GR_ATT1_PC_MATCH_Msk 0x40000000UL
|
||||
#define PERI_PPU_GR_ATT1_ENABLED_Pos 31UL
|
||||
#define PERI_PPU_GR_ATT1_ENABLED_Msk 0x80000000UL
|
||||
|
||||
|
||||
/* PERI_GR_PPU_SL.ADDR0 */
|
||||
#define PERI_GR_PPU_SL_ADDR0_SUBREGION_DISABLE_Pos 0UL
|
||||
#define PERI_GR_PPU_SL_ADDR0_SUBREGION_DISABLE_Msk 0xFFUL
|
||||
#define PERI_GR_PPU_SL_ADDR0_ADDR24_Pos 8UL
|
||||
#define PERI_GR_PPU_SL_ADDR0_ADDR24_Msk 0xFFFFFF00UL
|
||||
/* PERI_GR_PPU_SL.ATT0 */
|
||||
#define PERI_GR_PPU_SL_ATT0_UR_Pos 0UL
|
||||
#define PERI_GR_PPU_SL_ATT0_UR_Msk 0x1UL
|
||||
#define PERI_GR_PPU_SL_ATT0_UW_Pos 1UL
|
||||
#define PERI_GR_PPU_SL_ATT0_UW_Msk 0x2UL
|
||||
#define PERI_GR_PPU_SL_ATT0_UX_Pos 2UL
|
||||
#define PERI_GR_PPU_SL_ATT0_UX_Msk 0x4UL
|
||||
#define PERI_GR_PPU_SL_ATT0_PR_Pos 3UL
|
||||
#define PERI_GR_PPU_SL_ATT0_PR_Msk 0x8UL
|
||||
#define PERI_GR_PPU_SL_ATT0_PW_Pos 4UL
|
||||
#define PERI_GR_PPU_SL_ATT0_PW_Msk 0x10UL
|
||||
#define PERI_GR_PPU_SL_ATT0_PX_Pos 5UL
|
||||
#define PERI_GR_PPU_SL_ATT0_PX_Msk 0x20UL
|
||||
#define PERI_GR_PPU_SL_ATT0_NS_Pos 6UL
|
||||
#define PERI_GR_PPU_SL_ATT0_NS_Msk 0x40UL
|
||||
#define PERI_GR_PPU_SL_ATT0_PC_MASK_0_Pos 8UL
|
||||
#define PERI_GR_PPU_SL_ATT0_PC_MASK_0_Msk 0x100UL
|
||||
#define PERI_GR_PPU_SL_ATT0_PC_MASK_15_TO_1_Pos 9UL
|
||||
#define PERI_GR_PPU_SL_ATT0_PC_MASK_15_TO_1_Msk 0xFFFE00UL
|
||||
#define PERI_GR_PPU_SL_ATT0_REGION_SIZE_Pos 24UL
|
||||
#define PERI_GR_PPU_SL_ATT0_REGION_SIZE_Msk 0x1F000000UL
|
||||
#define PERI_GR_PPU_SL_ATT0_PC_MATCH_Pos 30UL
|
||||
#define PERI_GR_PPU_SL_ATT0_PC_MATCH_Msk 0x40000000UL
|
||||
#define PERI_GR_PPU_SL_ATT0_ENABLED_Pos 31UL
|
||||
#define PERI_GR_PPU_SL_ATT0_ENABLED_Msk 0x80000000UL
|
||||
/* PERI_GR_PPU_SL.ADDR1 */
|
||||
#define PERI_GR_PPU_SL_ADDR1_SUBREGION_DISABLE_Pos 0UL
|
||||
#define PERI_GR_PPU_SL_ADDR1_SUBREGION_DISABLE_Msk 0xFFUL
|
||||
#define PERI_GR_PPU_SL_ADDR1_ADDR24_Pos 8UL
|
||||
#define PERI_GR_PPU_SL_ADDR1_ADDR24_Msk 0xFFFFFF00UL
|
||||
/* PERI_GR_PPU_SL.ATT1 */
|
||||
#define PERI_GR_PPU_SL_ATT1_UR_Pos 0UL
|
||||
#define PERI_GR_PPU_SL_ATT1_UR_Msk 0x1UL
|
||||
#define PERI_GR_PPU_SL_ATT1_UW_Pos 1UL
|
||||
#define PERI_GR_PPU_SL_ATT1_UW_Msk 0x2UL
|
||||
#define PERI_GR_PPU_SL_ATT1_UX_Pos 2UL
|
||||
#define PERI_GR_PPU_SL_ATT1_UX_Msk 0x4UL
|
||||
#define PERI_GR_PPU_SL_ATT1_PR_Pos 3UL
|
||||
#define PERI_GR_PPU_SL_ATT1_PR_Msk 0x8UL
|
||||
#define PERI_GR_PPU_SL_ATT1_PW_Pos 4UL
|
||||
#define PERI_GR_PPU_SL_ATT1_PW_Msk 0x10UL
|
||||
#define PERI_GR_PPU_SL_ATT1_PX_Pos 5UL
|
||||
#define PERI_GR_PPU_SL_ATT1_PX_Msk 0x20UL
|
||||
#define PERI_GR_PPU_SL_ATT1_NS_Pos 6UL
|
||||
#define PERI_GR_PPU_SL_ATT1_NS_Msk 0x40UL
|
||||
#define PERI_GR_PPU_SL_ATT1_PC_MASK_0_Pos 8UL
|
||||
#define PERI_GR_PPU_SL_ATT1_PC_MASK_0_Msk 0x100UL
|
||||
#define PERI_GR_PPU_SL_ATT1_PC_MASK_15_TO_1_Pos 9UL
|
||||
#define PERI_GR_PPU_SL_ATT1_PC_MASK_15_TO_1_Msk 0xFFFE00UL
|
||||
#define PERI_GR_PPU_SL_ATT1_REGION_SIZE_Pos 24UL
|
||||
#define PERI_GR_PPU_SL_ATT1_REGION_SIZE_Msk 0x1F000000UL
|
||||
#define PERI_GR_PPU_SL_ATT1_PC_MATCH_Pos 30UL
|
||||
#define PERI_GR_PPU_SL_ATT1_PC_MATCH_Msk 0x40000000UL
|
||||
#define PERI_GR_PPU_SL_ATT1_ENABLED_Pos 31UL
|
||||
#define PERI_GR_PPU_SL_ATT1_ENABLED_Msk 0x80000000UL
|
||||
|
||||
|
||||
/* PERI_GR_PPU_RG.ADDR0 */
|
||||
#define PERI_GR_PPU_RG_ADDR0_SUBREGION_DISABLE_Pos 0UL
|
||||
#define PERI_GR_PPU_RG_ADDR0_SUBREGION_DISABLE_Msk 0xFFUL
|
||||
#define PERI_GR_PPU_RG_ADDR0_ADDR24_Pos 8UL
|
||||
#define PERI_GR_PPU_RG_ADDR0_ADDR24_Msk 0xFFFFFF00UL
|
||||
/* PERI_GR_PPU_RG.ATT0 */
|
||||
#define PERI_GR_PPU_RG_ATT0_UR_Pos 0UL
|
||||
#define PERI_GR_PPU_RG_ATT0_UR_Msk 0x1UL
|
||||
#define PERI_GR_PPU_RG_ATT0_UW_Pos 1UL
|
||||
#define PERI_GR_PPU_RG_ATT0_UW_Msk 0x2UL
|
||||
#define PERI_GR_PPU_RG_ATT0_UX_Pos 2UL
|
||||
#define PERI_GR_PPU_RG_ATT0_UX_Msk 0x4UL
|
||||
#define PERI_GR_PPU_RG_ATT0_PR_Pos 3UL
|
||||
#define PERI_GR_PPU_RG_ATT0_PR_Msk 0x8UL
|
||||
#define PERI_GR_PPU_RG_ATT0_PW_Pos 4UL
|
||||
#define PERI_GR_PPU_RG_ATT0_PW_Msk 0x10UL
|
||||
#define PERI_GR_PPU_RG_ATT0_PX_Pos 5UL
|
||||
#define PERI_GR_PPU_RG_ATT0_PX_Msk 0x20UL
|
||||
#define PERI_GR_PPU_RG_ATT0_NS_Pos 6UL
|
||||
#define PERI_GR_PPU_RG_ATT0_NS_Msk 0x40UL
|
||||
#define PERI_GR_PPU_RG_ATT0_PC_MASK_0_Pos 8UL
|
||||
#define PERI_GR_PPU_RG_ATT0_PC_MASK_0_Msk 0x100UL
|
||||
#define PERI_GR_PPU_RG_ATT0_PC_MASK_15_TO_1_Pos 9UL
|
||||
#define PERI_GR_PPU_RG_ATT0_PC_MASK_15_TO_1_Msk 0xFFFE00UL
|
||||
#define PERI_GR_PPU_RG_ATT0_REGION_SIZE_Pos 24UL
|
||||
#define PERI_GR_PPU_RG_ATT0_REGION_SIZE_Msk 0x1F000000UL
|
||||
#define PERI_GR_PPU_RG_ATT0_PC_MATCH_Pos 30UL
|
||||
#define PERI_GR_PPU_RG_ATT0_PC_MATCH_Msk 0x40000000UL
|
||||
#define PERI_GR_PPU_RG_ATT0_ENABLED_Pos 31UL
|
||||
#define PERI_GR_PPU_RG_ATT0_ENABLED_Msk 0x80000000UL
|
||||
/* PERI_GR_PPU_RG.ADDR1 */
|
||||
#define PERI_GR_PPU_RG_ADDR1_SUBREGION_DISABLE_Pos 0UL
|
||||
#define PERI_GR_PPU_RG_ADDR1_SUBREGION_DISABLE_Msk 0xFFUL
|
||||
#define PERI_GR_PPU_RG_ADDR1_ADDR24_Pos 8UL
|
||||
#define PERI_GR_PPU_RG_ADDR1_ADDR24_Msk 0xFFFFFF00UL
|
||||
/* PERI_GR_PPU_RG.ATT1 */
|
||||
#define PERI_GR_PPU_RG_ATT1_UR_Pos 0UL
|
||||
#define PERI_GR_PPU_RG_ATT1_UR_Msk 0x1UL
|
||||
#define PERI_GR_PPU_RG_ATT1_UW_Pos 1UL
|
||||
#define PERI_GR_PPU_RG_ATT1_UW_Msk 0x2UL
|
||||
#define PERI_GR_PPU_RG_ATT1_UX_Pos 2UL
|
||||
#define PERI_GR_PPU_RG_ATT1_UX_Msk 0x4UL
|
||||
#define PERI_GR_PPU_RG_ATT1_PR_Pos 3UL
|
||||
#define PERI_GR_PPU_RG_ATT1_PR_Msk 0x8UL
|
||||
#define PERI_GR_PPU_RG_ATT1_PW_Pos 4UL
|
||||
#define PERI_GR_PPU_RG_ATT1_PW_Msk 0x10UL
|
||||
#define PERI_GR_PPU_RG_ATT1_PX_Pos 5UL
|
||||
#define PERI_GR_PPU_RG_ATT1_PX_Msk 0x20UL
|
||||
#define PERI_GR_PPU_RG_ATT1_NS_Pos 6UL
|
||||
#define PERI_GR_PPU_RG_ATT1_NS_Msk 0x40UL
|
||||
#define PERI_GR_PPU_RG_ATT1_PC_MASK_0_Pos 8UL
|
||||
#define PERI_GR_PPU_RG_ATT1_PC_MASK_0_Msk 0x100UL
|
||||
#define PERI_GR_PPU_RG_ATT1_PC_MASK_15_TO_1_Pos 9UL
|
||||
#define PERI_GR_PPU_RG_ATT1_PC_MASK_15_TO_1_Msk 0xFFFE00UL
|
||||
#define PERI_GR_PPU_RG_ATT1_REGION_SIZE_Pos 24UL
|
||||
#define PERI_GR_PPU_RG_ATT1_REGION_SIZE_Msk 0x1F000000UL
|
||||
#define PERI_GR_PPU_RG_ATT1_PC_MATCH_Pos 30UL
|
||||
#define PERI_GR_PPU_RG_ATT1_PC_MATCH_Msk 0x40000000UL
|
||||
#define PERI_GR_PPU_RG_ATT1_ENABLED_Pos 31UL
|
||||
#define PERI_GR_PPU_RG_ATT1_ENABLED_Msk 0x80000000UL
|
||||
|
||||
|
||||
/* PERI.DIV_CMD */
|
||||
#define PERI_DIV_CMD_DIV_SEL_Pos 0UL
|
||||
#define PERI_DIV_CMD_DIV_SEL_Msk 0x3FUL
|
||||
#define PERI_DIV_CMD_TYPE_SEL_Pos 6UL
|
||||
#define PERI_DIV_CMD_TYPE_SEL_Msk 0xC0UL
|
||||
#define PERI_DIV_CMD_PA_DIV_SEL_Pos 8UL
|
||||
#define PERI_DIV_CMD_PA_DIV_SEL_Msk 0x3F00UL
|
||||
#define PERI_DIV_CMD_PA_TYPE_SEL_Pos 14UL
|
||||
#define PERI_DIV_CMD_PA_TYPE_SEL_Msk 0xC000UL
|
||||
#define PERI_DIV_CMD_DISABLE_Pos 30UL
|
||||
#define PERI_DIV_CMD_DISABLE_Msk 0x40000000UL
|
||||
#define PERI_DIV_CMD_ENABLE_Pos 31UL
|
||||
#define PERI_DIV_CMD_ENABLE_Msk 0x80000000UL
|
||||
/* PERI.DIV_8_CTL */
|
||||
#define PERI_DIV_8_CTL_EN_Pos 0UL
|
||||
#define PERI_DIV_8_CTL_EN_Msk 0x1UL
|
||||
#define PERI_DIV_8_CTL_INT8_DIV_Pos 8UL
|
||||
#define PERI_DIV_8_CTL_INT8_DIV_Msk 0xFF00UL
|
||||
/* PERI.DIV_16_CTL */
|
||||
#define PERI_DIV_16_CTL_EN_Pos 0UL
|
||||
#define PERI_DIV_16_CTL_EN_Msk 0x1UL
|
||||
#define PERI_DIV_16_CTL_INT16_DIV_Pos 8UL
|
||||
#define PERI_DIV_16_CTL_INT16_DIV_Msk 0xFFFF00UL
|
||||
/* PERI.DIV_16_5_CTL */
|
||||
#define PERI_DIV_16_5_CTL_EN_Pos 0UL
|
||||
#define PERI_DIV_16_5_CTL_EN_Msk 0x1UL
|
||||
#define PERI_DIV_16_5_CTL_FRAC5_DIV_Pos 3UL
|
||||
#define PERI_DIV_16_5_CTL_FRAC5_DIV_Msk 0xF8UL
|
||||
#define PERI_DIV_16_5_CTL_INT16_DIV_Pos 8UL
|
||||
#define PERI_DIV_16_5_CTL_INT16_DIV_Msk 0xFFFF00UL
|
||||
/* PERI.DIV_24_5_CTL */
|
||||
#define PERI_DIV_24_5_CTL_EN_Pos 0UL
|
||||
#define PERI_DIV_24_5_CTL_EN_Msk 0x1UL
|
||||
#define PERI_DIV_24_5_CTL_FRAC5_DIV_Pos 3UL
|
||||
#define PERI_DIV_24_5_CTL_FRAC5_DIV_Msk 0xF8UL
|
||||
#define PERI_DIV_24_5_CTL_INT24_DIV_Pos 8UL
|
||||
#define PERI_DIV_24_5_CTL_INT24_DIV_Msk 0xFFFFFF00UL
|
||||
/* PERI.CLOCK_CTL */
|
||||
#define PERI_CLOCK_CTL_DIV_SEL_Pos 0UL
|
||||
#define PERI_CLOCK_CTL_DIV_SEL_Msk 0x3FUL
|
||||
#define PERI_CLOCK_CTL_TYPE_SEL_Pos 6UL
|
||||
#define PERI_CLOCK_CTL_TYPE_SEL_Msk 0xC0UL
|
||||
/* PERI.TR_CMD */
|
||||
#define PERI_TR_CMD_TR_SEL_Pos 0UL
|
||||
#define PERI_TR_CMD_TR_SEL_Msk 0xFFUL
|
||||
#define PERI_TR_CMD_GROUP_SEL_Pos 8UL
|
||||
#define PERI_TR_CMD_GROUP_SEL_Msk 0xF00UL
|
||||
#define PERI_TR_CMD_COUNT_Pos 16UL
|
||||
#define PERI_TR_CMD_COUNT_Msk 0xFF0000UL
|
||||
#define PERI_TR_CMD_OUT_SEL_Pos 30UL
|
||||
#define PERI_TR_CMD_OUT_SEL_Msk 0x40000000UL
|
||||
#define PERI_TR_CMD_ACTIVATE_Pos 31UL
|
||||
#define PERI_TR_CMD_ACTIVATE_Msk 0x80000000UL
|
||||
|
||||
|
||||
#endif /* _CYIP_PERI_H_ */
|
||||
|
||||
|
||||
/* [] END OF FILE */
|
||||
|
|
@ -1,777 +0,0 @@
|
|||
/***************************************************************************//**
|
||||
* \file cyip_peri_ms_v2.h
|
||||
*
|
||||
* \brief
|
||||
* PERI_MS IP definitions
|
||||
*
|
||||
* \note
|
||||
* Generator version: 1.3.0.1146
|
||||
* Database revision: rev#1050929
|
||||
*
|
||||
********************************************************************************
|
||||
* \copyright
|
||||
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
|
||||
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _CYIP_PERI_MS_V2_H_
|
||||
#define _CYIP_PERI_MS_V2_H_
|
||||
|
||||
#include "cyip_headers.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* PERI_MS
|
||||
*******************************************************************************/
|
||||
|
||||
#define PERI_MS_PPU_PR_V2_SECTION_SIZE 0x00000040UL
|
||||
#define PERI_MS_PPU_FX_V2_SECTION_SIZE 0x00000040UL
|
||||
#define PERI_MS_V2_SECTION_SIZE 0x00010000UL
|
||||
|
||||
/**
|
||||
* \brief Programmable protection structure pair (PERI_MS_PPU_PR)
|
||||
*/
|
||||
typedef struct {
|
||||
__IOM uint32_t SL_ADDR; /*!< 0x00000000 Slave region, base address */
|
||||
__IOM uint32_t SL_SIZE; /*!< 0x00000004 Slave region, size */
|
||||
__IM uint32_t RESERVED[2];
|
||||
__IOM uint32_t SL_ATT0; /*!< 0x00000010 Slave attributes 0 */
|
||||
__IOM uint32_t SL_ATT1; /*!< 0x00000014 Slave attributes 1 */
|
||||
__IOM uint32_t SL_ATT2; /*!< 0x00000018 Slave attributes 2 */
|
||||
__IOM uint32_t SL_ATT3; /*!< 0x0000001C Slave attributes 3 */
|
||||
__IM uint32_t MS_ADDR; /*!< 0x00000020 Master region, base address */
|
||||
__IM uint32_t MS_SIZE; /*!< 0x00000024 Master region, size */
|
||||
__IM uint32_t RESERVED1[2];
|
||||
__IOM uint32_t MS_ATT0; /*!< 0x00000030 Master attributes 0 */
|
||||
__IOM uint32_t MS_ATT1; /*!< 0x00000034 Master attributes 1 */
|
||||
__IOM uint32_t MS_ATT2; /*!< 0x00000038 Master attributes 2 */
|
||||
__IOM uint32_t MS_ATT3; /*!< 0x0000003C Master attributes 3 */
|
||||
} PERI_MS_PPU_PR_V2_Type; /*!< Size = 64 (0x40) */
|
||||
|
||||
/**
|
||||
* \brief Fixed protection structure pair (PERI_MS_PPU_FX)
|
||||
*/
|
||||
typedef struct {
|
||||
__IM uint32_t SL_ADDR; /*!< 0x00000000 Slave region, base address */
|
||||
__IM uint32_t SL_SIZE; /*!< 0x00000004 Slave region, size */
|
||||
__IM uint32_t RESERVED[2];
|
||||
__IOM uint32_t SL_ATT0; /*!< 0x00000010 Slave attributes 0 */
|
||||
__IOM uint32_t SL_ATT1; /*!< 0x00000014 Slave attributes 1 */
|
||||
__IOM uint32_t SL_ATT2; /*!< 0x00000018 Slave attributes 2 */
|
||||
__IOM uint32_t SL_ATT3; /*!< 0x0000001C Slave attributes 3 */
|
||||
__IM uint32_t MS_ADDR; /*!< 0x00000020 Master region, base address */
|
||||
__IM uint32_t MS_SIZE; /*!< 0x00000024 Master region, size */
|
||||
__IM uint32_t RESERVED1[2];
|
||||
__IOM uint32_t MS_ATT0; /*!< 0x00000030 Master attributes 0 */
|
||||
__IOM uint32_t MS_ATT1; /*!< 0x00000034 Master attributes 1 */
|
||||
__IOM uint32_t MS_ATT2; /*!< 0x00000038 Master attributes 2 */
|
||||
__IOM uint32_t MS_ATT3; /*!< 0x0000003C Master attributes 3 */
|
||||
} PERI_MS_PPU_FX_V2_Type; /*!< Size = 64 (0x40) */
|
||||
|
||||
/**
|
||||
* \brief Peripheral interconnect, master interface (PERI_MS)
|
||||
*/
|
||||
typedef struct {
|
||||
PERI_MS_PPU_PR_V2_Type PPU_PR[32]; /*!< 0x00000000 Programmable protection structure pair */
|
||||
PERI_MS_PPU_FX_V2_Type PPU_FX[992]; /*!< 0x00000800 Fixed protection structure pair */
|
||||
} PERI_MS_V2_Type; /*!< Size = 65536 (0x10000) */
|
||||
|
||||
|
||||
/* PERI_MS_PPU_PR.SL_ADDR */
|
||||
#define PERI_MS_PPU_PR_V2_SL_ADDR_ADDR30_Pos 2UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ADDR_ADDR30_Msk 0xFFFFFFFCUL
|
||||
/* PERI_MS_PPU_PR.SL_SIZE */
|
||||
#define PERI_MS_PPU_PR_V2_SL_SIZE_REGION_SIZE_Pos 24UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_SIZE_REGION_SIZE_Msk 0x1F000000UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_SIZE_VALID_Pos 31UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_SIZE_VALID_Msk 0x80000000UL
|
||||
/* PERI_MS_PPU_PR.SL_ATT0 */
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT0_PC0_UR_Pos 0UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT0_PC0_UR_Msk 0x1UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT0_PC0_UW_Pos 1UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT0_PC0_UW_Msk 0x2UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT0_PC0_PR_Pos 2UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT0_PC0_PR_Msk 0x4UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT0_PC0_PW_Pos 3UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT0_PC0_PW_Msk 0x8UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT0_PC0_NS_Pos 4UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT0_PC0_NS_Msk 0x10UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT0_PC1_UR_Pos 8UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT0_PC1_UR_Msk 0x100UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT0_PC1_UW_Pos 9UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT0_PC1_UW_Msk 0x200UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT0_PC1_PR_Pos 10UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT0_PC1_PR_Msk 0x400UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT0_PC1_PW_Pos 11UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT0_PC1_PW_Msk 0x800UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT0_PC1_NS_Pos 12UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT0_PC1_NS_Msk 0x1000UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT0_PC2_UR_Pos 16UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT0_PC2_UR_Msk 0x10000UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT0_PC2_UW_Pos 17UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT0_PC2_UW_Msk 0x20000UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT0_PC2_PR_Pos 18UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT0_PC2_PR_Msk 0x40000UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT0_PC2_PW_Pos 19UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT0_PC2_PW_Msk 0x80000UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT0_PC2_NS_Pos 20UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT0_PC2_NS_Msk 0x100000UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT0_PC3_UR_Pos 24UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT0_PC3_UR_Msk 0x1000000UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT0_PC3_UW_Pos 25UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT0_PC3_UW_Msk 0x2000000UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT0_PC3_PR_Pos 26UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT0_PC3_PR_Msk 0x4000000UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT0_PC3_PW_Pos 27UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT0_PC3_PW_Msk 0x8000000UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT0_PC3_NS_Pos 28UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT0_PC3_NS_Msk 0x10000000UL
|
||||
/* PERI_MS_PPU_PR.SL_ATT1 */
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT1_PC4_UR_Pos 0UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT1_PC4_UR_Msk 0x1UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT1_PC4_UW_Pos 1UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT1_PC4_UW_Msk 0x2UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT1_PC4_PR_Pos 2UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT1_PC4_PR_Msk 0x4UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT1_PC4_PW_Pos 3UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT1_PC4_PW_Msk 0x8UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT1_PC4_NS_Pos 4UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT1_PC4_NS_Msk 0x10UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT1_PC5_UR_Pos 8UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT1_PC5_UR_Msk 0x100UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT1_PC5_UW_Pos 9UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT1_PC5_UW_Msk 0x200UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT1_PC5_PR_Pos 10UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT1_PC5_PR_Msk 0x400UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT1_PC5_PW_Pos 11UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT1_PC5_PW_Msk 0x800UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT1_PC5_NS_Pos 12UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT1_PC5_NS_Msk 0x1000UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT1_PC6_UR_Pos 16UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT1_PC6_UR_Msk 0x10000UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT1_PC6_UW_Pos 17UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT1_PC6_UW_Msk 0x20000UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT1_PC6_PR_Pos 18UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT1_PC6_PR_Msk 0x40000UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT1_PC6_PW_Pos 19UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT1_PC6_PW_Msk 0x80000UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT1_PC6_NS_Pos 20UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT1_PC6_NS_Msk 0x100000UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT1_PC7_UR_Pos 24UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT1_PC7_UR_Msk 0x1000000UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT1_PC7_UW_Pos 25UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT1_PC7_UW_Msk 0x2000000UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT1_PC7_PR_Pos 26UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT1_PC7_PR_Msk 0x4000000UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT1_PC7_PW_Pos 27UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT1_PC7_PW_Msk 0x8000000UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT1_PC7_NS_Pos 28UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT1_PC7_NS_Msk 0x10000000UL
|
||||
/* PERI_MS_PPU_PR.SL_ATT2 */
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT2_PC8_UR_Pos 0UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT2_PC8_UR_Msk 0x1UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT2_PC8_UW_Pos 1UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT2_PC8_UW_Msk 0x2UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT2_PC8_PR_Pos 2UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT2_PC8_PR_Msk 0x4UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT2_PC8_PW_Pos 3UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT2_PC8_PW_Msk 0x8UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT2_PC8_NS_Pos 4UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT2_PC8_NS_Msk 0x10UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT2_PC9_UR_Pos 8UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT2_PC9_UR_Msk 0x100UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT2_PC9_UW_Pos 9UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT2_PC9_UW_Msk 0x200UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT2_PC9_PR_Pos 10UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT2_PC9_PR_Msk 0x400UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT2_PC9_PW_Pos 11UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT2_PC9_PW_Msk 0x800UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT2_PC9_NS_Pos 12UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT2_PC9_NS_Msk 0x1000UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT2_PC10_UR_Pos 16UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT2_PC10_UR_Msk 0x10000UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT2_PC10_UW_Pos 17UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT2_PC10_UW_Msk 0x20000UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT2_PC10_PR_Pos 18UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT2_PC10_PR_Msk 0x40000UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT2_PC10_PW_Pos 19UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT2_PC10_PW_Msk 0x80000UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT2_PC10_NS_Pos 20UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT2_PC10_NS_Msk 0x100000UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT2_PC11_UR_Pos 24UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT2_PC11_UR_Msk 0x1000000UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT2_PC11_UW_Pos 25UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT2_PC11_UW_Msk 0x2000000UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT2_PC11_PR_Pos 26UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT2_PC11_PR_Msk 0x4000000UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT2_PC11_PW_Pos 27UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT2_PC11_PW_Msk 0x8000000UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT2_PC11_NS_Pos 28UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT2_PC11_NS_Msk 0x10000000UL
|
||||
/* PERI_MS_PPU_PR.SL_ATT3 */
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT3_PC12_UR_Pos 0UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT3_PC12_UR_Msk 0x1UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT3_PC12_UW_Pos 1UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT3_PC12_UW_Msk 0x2UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT3_PC12_PR_Pos 2UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT3_PC12_PR_Msk 0x4UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT3_PC12_PW_Pos 3UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT3_PC12_PW_Msk 0x8UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT3_PC12_NS_Pos 4UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT3_PC12_NS_Msk 0x10UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT3_PC13_UR_Pos 8UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT3_PC13_UR_Msk 0x100UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT3_PC13_UW_Pos 9UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT3_PC13_UW_Msk 0x200UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT3_PC13_PR_Pos 10UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT3_PC13_PR_Msk 0x400UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT3_PC13_PW_Pos 11UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT3_PC13_PW_Msk 0x800UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT3_PC13_NS_Pos 12UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT3_PC13_NS_Msk 0x1000UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT3_PC14_UR_Pos 16UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT3_PC14_UR_Msk 0x10000UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT3_PC14_UW_Pos 17UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT3_PC14_UW_Msk 0x20000UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT3_PC14_PR_Pos 18UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT3_PC14_PR_Msk 0x40000UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT3_PC14_PW_Pos 19UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT3_PC14_PW_Msk 0x80000UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT3_PC14_NS_Pos 20UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT3_PC14_NS_Msk 0x100000UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT3_PC15_UR_Pos 24UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT3_PC15_UR_Msk 0x1000000UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT3_PC15_UW_Pos 25UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT3_PC15_UW_Msk 0x2000000UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT3_PC15_PR_Pos 26UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT3_PC15_PR_Msk 0x4000000UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT3_PC15_PW_Pos 27UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT3_PC15_PW_Msk 0x8000000UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT3_PC15_NS_Pos 28UL
|
||||
#define PERI_MS_PPU_PR_V2_SL_ATT3_PC15_NS_Msk 0x10000000UL
|
||||
/* PERI_MS_PPU_PR.MS_ADDR */
|
||||
#define PERI_MS_PPU_PR_V2_MS_ADDR_ADDR26_Pos 6UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ADDR_ADDR26_Msk 0xFFFFFFC0UL
|
||||
/* PERI_MS_PPU_PR.MS_SIZE */
|
||||
#define PERI_MS_PPU_PR_V2_MS_SIZE_REGION_SIZE_Pos 24UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_SIZE_REGION_SIZE_Msk 0x1F000000UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_SIZE_VALID_Pos 31UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_SIZE_VALID_Msk 0x80000000UL
|
||||
/* PERI_MS_PPU_PR.MS_ATT0 */
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT0_PC0_UR_Pos 0UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT0_PC0_UR_Msk 0x1UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT0_PC0_UW_Pos 1UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT0_PC0_UW_Msk 0x2UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT0_PC0_PR_Pos 2UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT0_PC0_PR_Msk 0x4UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT0_PC0_PW_Pos 3UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT0_PC0_PW_Msk 0x8UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT0_PC0_NS_Pos 4UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT0_PC0_NS_Msk 0x10UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT0_PC1_UR_Pos 8UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT0_PC1_UR_Msk 0x100UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT0_PC1_UW_Pos 9UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT0_PC1_UW_Msk 0x200UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT0_PC1_PR_Pos 10UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT0_PC1_PR_Msk 0x400UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT0_PC1_PW_Pos 11UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT0_PC1_PW_Msk 0x800UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT0_PC1_NS_Pos 12UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT0_PC1_NS_Msk 0x1000UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT0_PC2_UR_Pos 16UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT0_PC2_UR_Msk 0x10000UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT0_PC2_UW_Pos 17UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT0_PC2_UW_Msk 0x20000UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT0_PC2_PR_Pos 18UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT0_PC2_PR_Msk 0x40000UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT0_PC2_PW_Pos 19UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT0_PC2_PW_Msk 0x80000UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT0_PC2_NS_Pos 20UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT0_PC2_NS_Msk 0x100000UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT0_PC3_UR_Pos 24UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT0_PC3_UR_Msk 0x1000000UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT0_PC3_UW_Pos 25UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT0_PC3_UW_Msk 0x2000000UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT0_PC3_PR_Pos 26UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT0_PC3_PR_Msk 0x4000000UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT0_PC3_PW_Pos 27UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT0_PC3_PW_Msk 0x8000000UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT0_PC3_NS_Pos 28UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT0_PC3_NS_Msk 0x10000000UL
|
||||
/* PERI_MS_PPU_PR.MS_ATT1 */
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT1_PC4_UR_Pos 0UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT1_PC4_UR_Msk 0x1UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT1_PC4_UW_Pos 1UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT1_PC4_UW_Msk 0x2UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT1_PC4_PR_Pos 2UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT1_PC4_PR_Msk 0x4UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT1_PC4_PW_Pos 3UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT1_PC4_PW_Msk 0x8UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT1_PC4_NS_Pos 4UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT1_PC4_NS_Msk 0x10UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT1_PC5_UR_Pos 8UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT1_PC5_UR_Msk 0x100UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT1_PC5_UW_Pos 9UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT1_PC5_UW_Msk 0x200UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT1_PC5_PR_Pos 10UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT1_PC5_PR_Msk 0x400UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT1_PC5_PW_Pos 11UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT1_PC5_PW_Msk 0x800UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT1_PC5_NS_Pos 12UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT1_PC5_NS_Msk 0x1000UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT1_PC6_UR_Pos 16UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT1_PC6_UR_Msk 0x10000UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT1_PC6_UW_Pos 17UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT1_PC6_UW_Msk 0x20000UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT1_PC6_PR_Pos 18UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT1_PC6_PR_Msk 0x40000UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT1_PC6_PW_Pos 19UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT1_PC6_PW_Msk 0x80000UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT1_PC6_NS_Pos 20UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT1_PC6_NS_Msk 0x100000UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT1_PC7_UR_Pos 24UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT1_PC7_UR_Msk 0x1000000UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT1_PC7_UW_Pos 25UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT1_PC7_UW_Msk 0x2000000UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT1_PC7_PR_Pos 26UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT1_PC7_PR_Msk 0x4000000UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT1_PC7_PW_Pos 27UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT1_PC7_PW_Msk 0x8000000UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT1_PC7_NS_Pos 28UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT1_PC7_NS_Msk 0x10000000UL
|
||||
/* PERI_MS_PPU_PR.MS_ATT2 */
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT2_PC8_UR_Pos 0UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT2_PC8_UR_Msk 0x1UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT2_PC8_UW_Pos 1UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT2_PC8_UW_Msk 0x2UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT2_PC8_PR_Pos 2UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT2_PC8_PR_Msk 0x4UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT2_PC8_PW_Pos 3UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT2_PC8_PW_Msk 0x8UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT2_PC8_NS_Pos 4UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT2_PC8_NS_Msk 0x10UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT2_PC9_UR_Pos 8UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT2_PC9_UR_Msk 0x100UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT2_PC9_UW_Pos 9UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT2_PC9_UW_Msk 0x200UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT2_PC9_PR_Pos 10UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT2_PC9_PR_Msk 0x400UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT2_PC9_PW_Pos 11UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT2_PC9_PW_Msk 0x800UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT2_PC9_NS_Pos 12UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT2_PC9_NS_Msk 0x1000UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT2_PC10_UR_Pos 16UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT2_PC10_UR_Msk 0x10000UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT2_PC10_UW_Pos 17UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT2_PC10_UW_Msk 0x20000UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT2_PC10_PR_Pos 18UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT2_PC10_PR_Msk 0x40000UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT2_PC10_PW_Pos 19UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT2_PC10_PW_Msk 0x80000UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT2_PC10_NS_Pos 20UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT2_PC10_NS_Msk 0x100000UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT2_PC11_UR_Pos 24UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT2_PC11_UR_Msk 0x1000000UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT2_PC11_UW_Pos 25UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT2_PC11_UW_Msk 0x2000000UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT2_PC11_PR_Pos 26UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT2_PC11_PR_Msk 0x4000000UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT2_PC11_PW_Pos 27UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT2_PC11_PW_Msk 0x8000000UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT2_PC11_NS_Pos 28UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT2_PC11_NS_Msk 0x10000000UL
|
||||
/* PERI_MS_PPU_PR.MS_ATT3 */
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT3_PC12_UR_Pos 0UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT3_PC12_UR_Msk 0x1UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT3_PC12_UW_Pos 1UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT3_PC12_UW_Msk 0x2UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT3_PC12_PR_Pos 2UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT3_PC12_PR_Msk 0x4UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT3_PC12_PW_Pos 3UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT3_PC12_PW_Msk 0x8UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT3_PC12_NS_Pos 4UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT3_PC12_NS_Msk 0x10UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT3_PC13_UR_Pos 8UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT3_PC13_UR_Msk 0x100UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT3_PC13_UW_Pos 9UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT3_PC13_UW_Msk 0x200UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT3_PC13_PR_Pos 10UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT3_PC13_PR_Msk 0x400UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT3_PC13_PW_Pos 11UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT3_PC13_PW_Msk 0x800UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT3_PC13_NS_Pos 12UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT3_PC13_NS_Msk 0x1000UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT3_PC14_UR_Pos 16UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT3_PC14_UR_Msk 0x10000UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT3_PC14_UW_Pos 17UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT3_PC14_UW_Msk 0x20000UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT3_PC14_PR_Pos 18UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT3_PC14_PR_Msk 0x40000UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT3_PC14_PW_Pos 19UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT3_PC14_PW_Msk 0x80000UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT3_PC14_NS_Pos 20UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT3_PC14_NS_Msk 0x100000UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT3_PC15_UR_Pos 24UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT3_PC15_UR_Msk 0x1000000UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT3_PC15_UW_Pos 25UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT3_PC15_UW_Msk 0x2000000UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT3_PC15_PR_Pos 26UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT3_PC15_PR_Msk 0x4000000UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT3_PC15_PW_Pos 27UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT3_PC15_PW_Msk 0x8000000UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT3_PC15_NS_Pos 28UL
|
||||
#define PERI_MS_PPU_PR_V2_MS_ATT3_PC15_NS_Msk 0x10000000UL
|
||||
|
||||
|
||||
/* PERI_MS_PPU_FX.SL_ADDR */
|
||||
#define PERI_MS_PPU_FX_V2_SL_ADDR_ADDR30_Pos 2UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ADDR_ADDR30_Msk 0xFFFFFFFCUL
|
||||
/* PERI_MS_PPU_FX.SL_SIZE */
|
||||
#define PERI_MS_PPU_FX_V2_SL_SIZE_REGION_SIZE_Pos 24UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_SIZE_REGION_SIZE_Msk 0x1F000000UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_SIZE_VALID_Pos 31UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_SIZE_VALID_Msk 0x80000000UL
|
||||
/* PERI_MS_PPU_FX.SL_ATT0 */
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT0_PC0_UR_Pos 0UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT0_PC0_UR_Msk 0x1UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT0_PC0_UW_Pos 1UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT0_PC0_UW_Msk 0x2UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT0_PC0_PR_Pos 2UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT0_PC0_PR_Msk 0x4UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT0_PC0_PW_Pos 3UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT0_PC0_PW_Msk 0x8UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT0_PC0_NS_Pos 4UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT0_PC0_NS_Msk 0x10UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT0_PC1_UR_Pos 8UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT0_PC1_UR_Msk 0x100UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT0_PC1_UW_Pos 9UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT0_PC1_UW_Msk 0x200UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT0_PC1_PR_Pos 10UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT0_PC1_PR_Msk 0x400UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT0_PC1_PW_Pos 11UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT0_PC1_PW_Msk 0x800UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT0_PC1_NS_Pos 12UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT0_PC1_NS_Msk 0x1000UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT0_PC2_UR_Pos 16UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT0_PC2_UR_Msk 0x10000UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT0_PC2_UW_Pos 17UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT0_PC2_UW_Msk 0x20000UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT0_PC2_PR_Pos 18UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT0_PC2_PR_Msk 0x40000UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT0_PC2_PW_Pos 19UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT0_PC2_PW_Msk 0x80000UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT0_PC2_NS_Pos 20UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT0_PC2_NS_Msk 0x100000UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT0_PC3_UR_Pos 24UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT0_PC3_UR_Msk 0x1000000UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT0_PC3_UW_Pos 25UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT0_PC3_UW_Msk 0x2000000UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT0_PC3_PR_Pos 26UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT0_PC3_PR_Msk 0x4000000UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT0_PC3_PW_Pos 27UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT0_PC3_PW_Msk 0x8000000UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT0_PC3_NS_Pos 28UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT0_PC3_NS_Msk 0x10000000UL
|
||||
/* PERI_MS_PPU_FX.SL_ATT1 */
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT1_PC4_UR_Pos 0UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT1_PC4_UR_Msk 0x1UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT1_PC4_UW_Pos 1UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT1_PC4_UW_Msk 0x2UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT1_PC4_PR_Pos 2UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT1_PC4_PR_Msk 0x4UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT1_PC4_PW_Pos 3UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT1_PC4_PW_Msk 0x8UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT1_PC4_NS_Pos 4UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT1_PC4_NS_Msk 0x10UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT1_PC5_UR_Pos 8UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT1_PC5_UR_Msk 0x100UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT1_PC5_UW_Pos 9UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT1_PC5_UW_Msk 0x200UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT1_PC5_PR_Pos 10UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT1_PC5_PR_Msk 0x400UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT1_PC5_PW_Pos 11UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT1_PC5_PW_Msk 0x800UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT1_PC5_NS_Pos 12UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT1_PC5_NS_Msk 0x1000UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT1_PC6_UR_Pos 16UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT1_PC6_UR_Msk 0x10000UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT1_PC6_UW_Pos 17UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT1_PC6_UW_Msk 0x20000UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT1_PC6_PR_Pos 18UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT1_PC6_PR_Msk 0x40000UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT1_PC6_PW_Pos 19UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT1_PC6_PW_Msk 0x80000UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT1_PC6_NS_Pos 20UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT1_PC6_NS_Msk 0x100000UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT1_PC7_UR_Pos 24UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT1_PC7_UR_Msk 0x1000000UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT1_PC7_UW_Pos 25UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT1_PC7_UW_Msk 0x2000000UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT1_PC7_PR_Pos 26UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT1_PC7_PR_Msk 0x4000000UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT1_PC7_PW_Pos 27UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT1_PC7_PW_Msk 0x8000000UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT1_PC7_NS_Pos 28UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT1_PC7_NS_Msk 0x10000000UL
|
||||
/* PERI_MS_PPU_FX.SL_ATT2 */
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT2_PC8_UR_Pos 0UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT2_PC8_UR_Msk 0x1UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT2_PC8_UW_Pos 1UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT2_PC8_UW_Msk 0x2UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT2_PC8_PR_Pos 2UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT2_PC8_PR_Msk 0x4UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT2_PC8_PW_Pos 3UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT2_PC8_PW_Msk 0x8UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT2_PC8_NS_Pos 4UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT2_PC8_NS_Msk 0x10UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT2_PC9_UR_Pos 8UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT2_PC9_UR_Msk 0x100UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT2_PC9_UW_Pos 9UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT2_PC9_UW_Msk 0x200UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT2_PC9_PR_Pos 10UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT2_PC9_PR_Msk 0x400UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT2_PC9_PW_Pos 11UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT2_PC9_PW_Msk 0x800UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT2_PC9_NS_Pos 12UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT2_PC9_NS_Msk 0x1000UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT2_PC10_UR_Pos 16UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT2_PC10_UR_Msk 0x10000UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT2_PC10_UW_Pos 17UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT2_PC10_UW_Msk 0x20000UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT2_PC10_PR_Pos 18UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT2_PC10_PR_Msk 0x40000UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT2_PC10_PW_Pos 19UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT2_PC10_PW_Msk 0x80000UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT2_PC10_NS_Pos 20UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT2_PC10_NS_Msk 0x100000UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT2_PC11_UR_Pos 24UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT2_PC11_UR_Msk 0x1000000UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT2_PC11_UW_Pos 25UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT2_PC11_UW_Msk 0x2000000UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT2_PC11_PR_Pos 26UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT2_PC11_PR_Msk 0x4000000UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT2_PC11_PW_Pos 27UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT2_PC11_PW_Msk 0x8000000UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT2_PC11_NS_Pos 28UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT2_PC11_NS_Msk 0x10000000UL
|
||||
/* PERI_MS_PPU_FX.SL_ATT3 */
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT3_PC12_UR_Pos 0UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT3_PC12_UR_Msk 0x1UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT3_PC12_UW_Pos 1UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT3_PC12_UW_Msk 0x2UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT3_PC12_PR_Pos 2UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT3_PC12_PR_Msk 0x4UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT3_PC12_PW_Pos 3UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT3_PC12_PW_Msk 0x8UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT3_PC12_NS_Pos 4UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT3_PC12_NS_Msk 0x10UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT3_PC13_UR_Pos 8UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT3_PC13_UR_Msk 0x100UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT3_PC13_UW_Pos 9UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT3_PC13_UW_Msk 0x200UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT3_PC13_PR_Pos 10UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT3_PC13_PR_Msk 0x400UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT3_PC13_PW_Pos 11UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT3_PC13_PW_Msk 0x800UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT3_PC13_NS_Pos 12UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT3_PC13_NS_Msk 0x1000UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT3_PC14_UR_Pos 16UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT3_PC14_UR_Msk 0x10000UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT3_PC14_UW_Pos 17UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT3_PC14_UW_Msk 0x20000UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT3_PC14_PR_Pos 18UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT3_PC14_PR_Msk 0x40000UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT3_PC14_PW_Pos 19UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT3_PC14_PW_Msk 0x80000UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT3_PC14_NS_Pos 20UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT3_PC14_NS_Msk 0x100000UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT3_PC15_UR_Pos 24UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT3_PC15_UR_Msk 0x1000000UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT3_PC15_UW_Pos 25UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT3_PC15_UW_Msk 0x2000000UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT3_PC15_PR_Pos 26UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT3_PC15_PR_Msk 0x4000000UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT3_PC15_PW_Pos 27UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT3_PC15_PW_Msk 0x8000000UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT3_PC15_NS_Pos 28UL
|
||||
#define PERI_MS_PPU_FX_V2_SL_ATT3_PC15_NS_Msk 0x10000000UL
|
||||
/* PERI_MS_PPU_FX.MS_ADDR */
|
||||
#define PERI_MS_PPU_FX_V2_MS_ADDR_ADDR26_Pos 6UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ADDR_ADDR26_Msk 0xFFFFFFC0UL
|
||||
/* PERI_MS_PPU_FX.MS_SIZE */
|
||||
#define PERI_MS_PPU_FX_V2_MS_SIZE_REGION_SIZE_Pos 24UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_SIZE_REGION_SIZE_Msk 0x1F000000UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_SIZE_VALID_Pos 31UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_SIZE_VALID_Msk 0x80000000UL
|
||||
/* PERI_MS_PPU_FX.MS_ATT0 */
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT0_PC0_UR_Pos 0UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT0_PC0_UR_Msk 0x1UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT0_PC0_UW_Pos 1UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT0_PC0_UW_Msk 0x2UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT0_PC0_PR_Pos 2UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT0_PC0_PR_Msk 0x4UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT0_PC0_PW_Pos 3UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT0_PC0_PW_Msk 0x8UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT0_PC0_NS_Pos 4UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT0_PC0_NS_Msk 0x10UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT0_PC1_UR_Pos 8UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT0_PC1_UR_Msk 0x100UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT0_PC1_UW_Pos 9UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT0_PC1_UW_Msk 0x200UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT0_PC1_PR_Pos 10UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT0_PC1_PR_Msk 0x400UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT0_PC1_PW_Pos 11UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT0_PC1_PW_Msk 0x800UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT0_PC1_NS_Pos 12UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT0_PC1_NS_Msk 0x1000UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT0_PC2_UR_Pos 16UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT0_PC2_UR_Msk 0x10000UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT0_PC2_UW_Pos 17UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT0_PC2_UW_Msk 0x20000UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT0_PC2_PR_Pos 18UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT0_PC2_PR_Msk 0x40000UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT0_PC2_PW_Pos 19UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT0_PC2_PW_Msk 0x80000UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT0_PC2_NS_Pos 20UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT0_PC2_NS_Msk 0x100000UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT0_PC3_UR_Pos 24UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT0_PC3_UR_Msk 0x1000000UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT0_PC3_UW_Pos 25UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT0_PC3_UW_Msk 0x2000000UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT0_PC3_PR_Pos 26UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT0_PC3_PR_Msk 0x4000000UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT0_PC3_PW_Pos 27UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT0_PC3_PW_Msk 0x8000000UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT0_PC3_NS_Pos 28UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT0_PC3_NS_Msk 0x10000000UL
|
||||
/* PERI_MS_PPU_FX.MS_ATT1 */
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT1_PC4_UR_Pos 0UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT1_PC4_UR_Msk 0x1UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT1_PC4_UW_Pos 1UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT1_PC4_UW_Msk 0x2UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT1_PC4_PR_Pos 2UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT1_PC4_PR_Msk 0x4UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT1_PC4_PW_Pos 3UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT1_PC4_PW_Msk 0x8UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT1_PC4_NS_Pos 4UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT1_PC4_NS_Msk 0x10UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT1_PC5_UR_Pos 8UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT1_PC5_UR_Msk 0x100UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT1_PC5_UW_Pos 9UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT1_PC5_UW_Msk 0x200UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT1_PC5_PR_Pos 10UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT1_PC5_PR_Msk 0x400UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT1_PC5_PW_Pos 11UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT1_PC5_PW_Msk 0x800UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT1_PC5_NS_Pos 12UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT1_PC5_NS_Msk 0x1000UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT1_PC6_UR_Pos 16UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT1_PC6_UR_Msk 0x10000UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT1_PC6_UW_Pos 17UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT1_PC6_UW_Msk 0x20000UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT1_PC6_PR_Pos 18UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT1_PC6_PR_Msk 0x40000UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT1_PC6_PW_Pos 19UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT1_PC6_PW_Msk 0x80000UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT1_PC6_NS_Pos 20UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT1_PC6_NS_Msk 0x100000UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT1_PC7_UR_Pos 24UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT1_PC7_UR_Msk 0x1000000UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT1_PC7_UW_Pos 25UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT1_PC7_UW_Msk 0x2000000UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT1_PC7_PR_Pos 26UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT1_PC7_PR_Msk 0x4000000UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT1_PC7_PW_Pos 27UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT1_PC7_PW_Msk 0x8000000UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT1_PC7_NS_Pos 28UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT1_PC7_NS_Msk 0x10000000UL
|
||||
/* PERI_MS_PPU_FX.MS_ATT2 */
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT2_PC8_UR_Pos 0UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT2_PC8_UR_Msk 0x1UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT2_PC8_UW_Pos 1UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT2_PC8_UW_Msk 0x2UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT2_PC8_PR_Pos 2UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT2_PC8_PR_Msk 0x4UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT2_PC8_PW_Pos 3UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT2_PC8_PW_Msk 0x8UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT2_PC8_NS_Pos 4UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT2_PC8_NS_Msk 0x10UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT2_PC9_UR_Pos 8UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT2_PC9_UR_Msk 0x100UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT2_PC9_UW_Pos 9UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT2_PC9_UW_Msk 0x200UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT2_PC9_PR_Pos 10UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT2_PC9_PR_Msk 0x400UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT2_PC9_PW_Pos 11UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT2_PC9_PW_Msk 0x800UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT2_PC9_NS_Pos 12UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT2_PC9_NS_Msk 0x1000UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT2_PC10_UR_Pos 16UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT2_PC10_UR_Msk 0x10000UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT2_PC10_UW_Pos 17UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT2_PC10_UW_Msk 0x20000UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT2_PC10_PR_Pos 18UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT2_PC10_PR_Msk 0x40000UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT2_PC10_PW_Pos 19UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT2_PC10_PW_Msk 0x80000UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT2_PC10_NS_Pos 20UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT2_PC10_NS_Msk 0x100000UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT2_PC11_UR_Pos 24UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT2_PC11_UR_Msk 0x1000000UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT2_PC11_UW_Pos 25UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT2_PC11_UW_Msk 0x2000000UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT2_PC11_PR_Pos 26UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT2_PC11_PR_Msk 0x4000000UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT2_PC11_PW_Pos 27UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT2_PC11_PW_Msk 0x8000000UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT2_PC11_NS_Pos 28UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT2_PC11_NS_Msk 0x10000000UL
|
||||
/* PERI_MS_PPU_FX.MS_ATT3 */
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT3_PC12_UR_Pos 0UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT3_PC12_UR_Msk 0x1UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT3_PC12_UW_Pos 1UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT3_PC12_UW_Msk 0x2UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT3_PC12_PR_Pos 2UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT3_PC12_PR_Msk 0x4UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT3_PC12_PW_Pos 3UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT3_PC12_PW_Msk 0x8UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT3_PC12_NS_Pos 4UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT3_PC12_NS_Msk 0x10UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT3_PC13_UR_Pos 8UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT3_PC13_UR_Msk 0x100UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT3_PC13_UW_Pos 9UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT3_PC13_UW_Msk 0x200UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT3_PC13_PR_Pos 10UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT3_PC13_PR_Msk 0x400UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT3_PC13_PW_Pos 11UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT3_PC13_PW_Msk 0x800UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT3_PC13_NS_Pos 12UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT3_PC13_NS_Msk 0x1000UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT3_PC14_UR_Pos 16UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT3_PC14_UR_Msk 0x10000UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT3_PC14_UW_Pos 17UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT3_PC14_UW_Msk 0x20000UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT3_PC14_PR_Pos 18UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT3_PC14_PR_Msk 0x40000UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT3_PC14_PW_Pos 19UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT3_PC14_PW_Msk 0x80000UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT3_PC14_NS_Pos 20UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT3_PC14_NS_Msk 0x100000UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT3_PC15_UR_Pos 24UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT3_PC15_UR_Msk 0x1000000UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT3_PC15_UW_Pos 25UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT3_PC15_UW_Msk 0x2000000UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT3_PC15_PR_Pos 26UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT3_PC15_PR_Msk 0x4000000UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT3_PC15_PW_Pos 27UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT3_PC15_PW_Msk 0x8000000UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT3_PC15_NS_Pos 28UL
|
||||
#define PERI_MS_PPU_FX_V2_MS_ATT3_PC15_NS_Msk 0x10000000UL
|
||||
|
||||
|
||||
#endif /* _CYIP_PERI_MS_V2_H_ */
|
||||
|
||||
|
||||
/* [] END OF FILE */
|
||||
|
|
@ -1,246 +0,0 @@
|
|||
/***************************************************************************//**
|
||||
* \file cyip_peri_v2.h
|
||||
*
|
||||
* \brief
|
||||
* PERI IP definitions
|
||||
*
|
||||
* \note
|
||||
* Generator version: 1.3.0.1146
|
||||
* Database revision: rev#1050929
|
||||
*
|
||||
********************************************************************************
|
||||
* \copyright
|
||||
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
|
||||
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _CYIP_PERI_V2_H_
|
||||
#define _CYIP_PERI_V2_H_
|
||||
|
||||
#include "cyip_headers.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* PERI
|
||||
*******************************************************************************/
|
||||
|
||||
#define PERI_GR_V2_SECTION_SIZE 0x00000020UL
|
||||
#define PERI_TR_GR_V2_SECTION_SIZE 0x00000400UL
|
||||
#define PERI_TR_1TO1_GR_V2_SECTION_SIZE 0x00000400UL
|
||||
#define PERI_V2_SECTION_SIZE 0x00010000UL
|
||||
|
||||
/**
|
||||
* \brief Peripheral group structure (PERI_GR)
|
||||
*/
|
||||
typedef struct {
|
||||
__IOM uint32_t CLOCK_CTL; /*!< 0x00000000 Clock control */
|
||||
__IM uint32_t RESERVED[3];
|
||||
__IOM uint32_t SL_CTL; /*!< 0x00000010 Slave control */
|
||||
__IM uint32_t RESERVED1[3];
|
||||
} PERI_GR_V2_Type; /*!< Size = 32 (0x20) */
|
||||
|
||||
/**
|
||||
* \brief Trigger group (PERI_TR_GR)
|
||||
*/
|
||||
typedef struct {
|
||||
__IOM uint32_t TR_CTL[256]; /*!< 0x00000000 Trigger control register */
|
||||
} PERI_TR_GR_V2_Type; /*!< Size = 1024 (0x400) */
|
||||
|
||||
/**
|
||||
* \brief Trigger 1-to-1 group (PERI_TR_1TO1_GR)
|
||||
*/
|
||||
typedef struct {
|
||||
__IOM uint32_t TR_CTL[256]; /*!< 0x00000000 Trigger control register */
|
||||
} PERI_TR_1TO1_GR_V2_Type; /*!< Size = 1024 (0x400) */
|
||||
|
||||
/**
|
||||
* \brief Peripheral interconnect (PERI)
|
||||
*/
|
||||
typedef struct {
|
||||
__IM uint32_t RESERVED[128];
|
||||
__IOM uint32_t TIMEOUT_CTL; /*!< 0x00000200 Timeout control */
|
||||
__IM uint32_t RESERVED1[7];
|
||||
__IOM uint32_t TR_CMD; /*!< 0x00000220 Trigger command */
|
||||
__IM uint32_t RESERVED2[119];
|
||||
__IOM uint32_t DIV_CMD; /*!< 0x00000400 Divider command */
|
||||
__IM uint32_t RESERVED3[511];
|
||||
__IOM uint32_t CLOCK_CTL[256]; /*!< 0x00000C00 Clock control */
|
||||
__IOM uint32_t DIV_8_CTL[256]; /*!< 0x00001000 Divider control (for 8.0 divider) */
|
||||
__IOM uint32_t DIV_16_CTL[256]; /*!< 0x00001400 Divider control (for 16.0 divider) */
|
||||
__IOM uint32_t DIV_16_5_CTL[256]; /*!< 0x00001800 Divider control (for 16.5 divider) */
|
||||
__IOM uint32_t DIV_24_5_CTL[255]; /*!< 0x00001C00 Divider control (for 24.5 divider) */
|
||||
__IM uint32_t RESERVED4;
|
||||
__IOM uint32_t ECC_CTL; /*!< 0x00002000 ECC control */
|
||||
__IM uint32_t RESERVED5[2047];
|
||||
PERI_GR_V2_Type GR[16]; /*!< 0x00004000 Peripheral group structure */
|
||||
__IM uint32_t RESERVED6[3968];
|
||||
PERI_TR_GR_V2_Type TR_GR[16]; /*!< 0x00008000 Trigger group */
|
||||
PERI_TR_1TO1_GR_V2_Type TR_1TO1_GR[16]; /*!< 0x0000C000 Trigger 1-to-1 group */
|
||||
} PERI_V2_Type; /*!< Size = 65536 (0x10000) */
|
||||
|
||||
|
||||
/* PERI_GR.CLOCK_CTL */
|
||||
#define PERI_GR_V2_CLOCK_CTL_INT8_DIV_Pos 8UL
|
||||
#define PERI_GR_V2_CLOCK_CTL_INT8_DIV_Msk 0xFF00UL
|
||||
/* PERI_GR.SL_CTL */
|
||||
#define PERI_GR_V2_SL_CTL_ENABLED_0_Pos 0UL
|
||||
#define PERI_GR_V2_SL_CTL_ENABLED_0_Msk 0x1UL
|
||||
#define PERI_GR_V2_SL_CTL_ENABLED_1_Pos 1UL
|
||||
#define PERI_GR_V2_SL_CTL_ENABLED_1_Msk 0x2UL
|
||||
#define PERI_GR_V2_SL_CTL_ENABLED_2_Pos 2UL
|
||||
#define PERI_GR_V2_SL_CTL_ENABLED_2_Msk 0x4UL
|
||||
#define PERI_GR_V2_SL_CTL_ENABLED_3_Pos 3UL
|
||||
#define PERI_GR_V2_SL_CTL_ENABLED_3_Msk 0x8UL
|
||||
#define PERI_GR_V2_SL_CTL_ENABLED_4_Pos 4UL
|
||||
#define PERI_GR_V2_SL_CTL_ENABLED_4_Msk 0x10UL
|
||||
#define PERI_GR_V2_SL_CTL_ENABLED_5_Pos 5UL
|
||||
#define PERI_GR_V2_SL_CTL_ENABLED_5_Msk 0x20UL
|
||||
#define PERI_GR_V2_SL_CTL_ENABLED_6_Pos 6UL
|
||||
#define PERI_GR_V2_SL_CTL_ENABLED_6_Msk 0x40UL
|
||||
#define PERI_GR_V2_SL_CTL_ENABLED_7_Pos 7UL
|
||||
#define PERI_GR_V2_SL_CTL_ENABLED_7_Msk 0x80UL
|
||||
#define PERI_GR_V2_SL_CTL_ENABLED_8_Pos 8UL
|
||||
#define PERI_GR_V2_SL_CTL_ENABLED_8_Msk 0x100UL
|
||||
#define PERI_GR_V2_SL_CTL_ENABLED_9_Pos 9UL
|
||||
#define PERI_GR_V2_SL_CTL_ENABLED_9_Msk 0x200UL
|
||||
#define PERI_GR_V2_SL_CTL_ENABLED_10_Pos 10UL
|
||||
#define PERI_GR_V2_SL_CTL_ENABLED_10_Msk 0x400UL
|
||||
#define PERI_GR_V2_SL_CTL_ENABLED_11_Pos 11UL
|
||||
#define PERI_GR_V2_SL_CTL_ENABLED_11_Msk 0x800UL
|
||||
#define PERI_GR_V2_SL_CTL_ENABLED_12_Pos 12UL
|
||||
#define PERI_GR_V2_SL_CTL_ENABLED_12_Msk 0x1000UL
|
||||
#define PERI_GR_V2_SL_CTL_ENABLED_13_Pos 13UL
|
||||
#define PERI_GR_V2_SL_CTL_ENABLED_13_Msk 0x2000UL
|
||||
#define PERI_GR_V2_SL_CTL_ENABLED_14_Pos 14UL
|
||||
#define PERI_GR_V2_SL_CTL_ENABLED_14_Msk 0x4000UL
|
||||
#define PERI_GR_V2_SL_CTL_ENABLED_15_Pos 15UL
|
||||
#define PERI_GR_V2_SL_CTL_ENABLED_15_Msk 0x8000UL
|
||||
#define PERI_GR_V2_SL_CTL_DISABLED_0_Pos 16UL
|
||||
#define PERI_GR_V2_SL_CTL_DISABLED_0_Msk 0x10000UL
|
||||
#define PERI_GR_V2_SL_CTL_DISABLED_1_Pos 17UL
|
||||
#define PERI_GR_V2_SL_CTL_DISABLED_1_Msk 0x20000UL
|
||||
#define PERI_GR_V2_SL_CTL_DISABLED_2_Pos 18UL
|
||||
#define PERI_GR_V2_SL_CTL_DISABLED_2_Msk 0x40000UL
|
||||
#define PERI_GR_V2_SL_CTL_DISABLED_3_Pos 19UL
|
||||
#define PERI_GR_V2_SL_CTL_DISABLED_3_Msk 0x80000UL
|
||||
#define PERI_GR_V2_SL_CTL_DISABLED_4_Pos 20UL
|
||||
#define PERI_GR_V2_SL_CTL_DISABLED_4_Msk 0x100000UL
|
||||
#define PERI_GR_V2_SL_CTL_DISABLED_5_Pos 21UL
|
||||
#define PERI_GR_V2_SL_CTL_DISABLED_5_Msk 0x200000UL
|
||||
#define PERI_GR_V2_SL_CTL_DISABLED_6_Pos 22UL
|
||||
#define PERI_GR_V2_SL_CTL_DISABLED_6_Msk 0x400000UL
|
||||
#define PERI_GR_V2_SL_CTL_DISABLED_7_Pos 23UL
|
||||
#define PERI_GR_V2_SL_CTL_DISABLED_7_Msk 0x800000UL
|
||||
#define PERI_GR_V2_SL_CTL_DISABLED_8_Pos 24UL
|
||||
#define PERI_GR_V2_SL_CTL_DISABLED_8_Msk 0x1000000UL
|
||||
#define PERI_GR_V2_SL_CTL_DISABLED_9_Pos 25UL
|
||||
#define PERI_GR_V2_SL_CTL_DISABLED_9_Msk 0x2000000UL
|
||||
#define PERI_GR_V2_SL_CTL_DISABLED_10_Pos 26UL
|
||||
#define PERI_GR_V2_SL_CTL_DISABLED_10_Msk 0x4000000UL
|
||||
#define PERI_GR_V2_SL_CTL_DISABLED_11_Pos 27UL
|
||||
#define PERI_GR_V2_SL_CTL_DISABLED_11_Msk 0x8000000UL
|
||||
#define PERI_GR_V2_SL_CTL_DISABLED_12_Pos 28UL
|
||||
#define PERI_GR_V2_SL_CTL_DISABLED_12_Msk 0x10000000UL
|
||||
#define PERI_GR_V2_SL_CTL_DISABLED_13_Pos 29UL
|
||||
#define PERI_GR_V2_SL_CTL_DISABLED_13_Msk 0x20000000UL
|
||||
#define PERI_GR_V2_SL_CTL_DISABLED_14_Pos 30UL
|
||||
#define PERI_GR_V2_SL_CTL_DISABLED_14_Msk 0x40000000UL
|
||||
#define PERI_GR_V2_SL_CTL_DISABLED_15_Pos 31UL
|
||||
#define PERI_GR_V2_SL_CTL_DISABLED_15_Msk 0x80000000UL
|
||||
|
||||
|
||||
/* PERI_TR_GR.TR_CTL */
|
||||
#define PERI_TR_GR_V2_TR_CTL_TR_SEL_Pos 0UL
|
||||
#define PERI_TR_GR_V2_TR_CTL_TR_SEL_Msk 0xFFUL
|
||||
#define PERI_TR_GR_V2_TR_CTL_TR_INV_Pos 8UL
|
||||
#define PERI_TR_GR_V2_TR_CTL_TR_INV_Msk 0x100UL
|
||||
#define PERI_TR_GR_V2_TR_CTL_TR_EDGE_Pos 9UL
|
||||
#define PERI_TR_GR_V2_TR_CTL_TR_EDGE_Msk 0x200UL
|
||||
#define PERI_TR_GR_V2_TR_CTL_DBG_FREEZE_EN_Pos 12UL
|
||||
#define PERI_TR_GR_V2_TR_CTL_DBG_FREEZE_EN_Msk 0x1000UL
|
||||
|
||||
|
||||
/* PERI_TR_1TO1_GR.TR_CTL */
|
||||
#define PERI_TR_1TO1_GR_V2_TR_CTL_TR_SEL_Pos 0UL
|
||||
#define PERI_TR_1TO1_GR_V2_TR_CTL_TR_SEL_Msk 0x1UL
|
||||
#define PERI_TR_1TO1_GR_V2_TR_CTL_TR_INV_Pos 8UL
|
||||
#define PERI_TR_1TO1_GR_V2_TR_CTL_TR_INV_Msk 0x100UL
|
||||
#define PERI_TR_1TO1_GR_V2_TR_CTL_TR_EDGE_Pos 9UL
|
||||
#define PERI_TR_1TO1_GR_V2_TR_CTL_TR_EDGE_Msk 0x200UL
|
||||
#define PERI_TR_1TO1_GR_V2_TR_CTL_DBG_FREEZE_EN_Pos 12UL
|
||||
#define PERI_TR_1TO1_GR_V2_TR_CTL_DBG_FREEZE_EN_Msk 0x1000UL
|
||||
|
||||
|
||||
/* PERI.TIMEOUT_CTL */
|
||||
#define PERI_V2_TIMEOUT_CTL_TIMEOUT_Pos 0UL
|
||||
#define PERI_V2_TIMEOUT_CTL_TIMEOUT_Msk 0xFFFFUL
|
||||
/* PERI.TR_CMD */
|
||||
#define PERI_V2_TR_CMD_TR_SEL_Pos 0UL
|
||||
#define PERI_V2_TR_CMD_TR_SEL_Msk 0xFFUL
|
||||
#define PERI_V2_TR_CMD_GROUP_SEL_Pos 8UL
|
||||
#define PERI_V2_TR_CMD_GROUP_SEL_Msk 0x1F00UL
|
||||
#define PERI_V2_TR_CMD_TR_EDGE_Pos 29UL
|
||||
#define PERI_V2_TR_CMD_TR_EDGE_Msk 0x20000000UL
|
||||
#define PERI_V2_TR_CMD_OUT_SEL_Pos 30UL
|
||||
#define PERI_V2_TR_CMD_OUT_SEL_Msk 0x40000000UL
|
||||
#define PERI_V2_TR_CMD_ACTIVATE_Pos 31UL
|
||||
#define PERI_V2_TR_CMD_ACTIVATE_Msk 0x80000000UL
|
||||
/* PERI.DIV_CMD */
|
||||
#define PERI_V2_DIV_CMD_DIV_SEL_Pos 0UL
|
||||
#define PERI_V2_DIV_CMD_DIV_SEL_Msk 0xFFUL
|
||||
#define PERI_V2_DIV_CMD_TYPE_SEL_Pos 8UL
|
||||
#define PERI_V2_DIV_CMD_TYPE_SEL_Msk 0x300UL
|
||||
#define PERI_V2_DIV_CMD_PA_DIV_SEL_Pos 16UL
|
||||
#define PERI_V2_DIV_CMD_PA_DIV_SEL_Msk 0xFF0000UL
|
||||
#define PERI_V2_DIV_CMD_PA_TYPE_SEL_Pos 24UL
|
||||
#define PERI_V2_DIV_CMD_PA_TYPE_SEL_Msk 0x3000000UL
|
||||
#define PERI_V2_DIV_CMD_DISABLE_Pos 30UL
|
||||
#define PERI_V2_DIV_CMD_DISABLE_Msk 0x40000000UL
|
||||
#define PERI_V2_DIV_CMD_ENABLE_Pos 31UL
|
||||
#define PERI_V2_DIV_CMD_ENABLE_Msk 0x80000000UL
|
||||
/* PERI.CLOCK_CTL */
|
||||
#define PERI_V2_CLOCK_CTL_DIV_SEL_Pos 0UL
|
||||
#define PERI_V2_CLOCK_CTL_DIV_SEL_Msk 0xFFUL
|
||||
#define PERI_V2_CLOCK_CTL_TYPE_SEL_Pos 8UL
|
||||
#define PERI_V2_CLOCK_CTL_TYPE_SEL_Msk 0x300UL
|
||||
/* PERI.DIV_8_CTL */
|
||||
#define PERI_V2_DIV_8_CTL_EN_Pos 0UL
|
||||
#define PERI_V2_DIV_8_CTL_EN_Msk 0x1UL
|
||||
#define PERI_V2_DIV_8_CTL_INT8_DIV_Pos 8UL
|
||||
#define PERI_V2_DIV_8_CTL_INT8_DIV_Msk 0xFF00UL
|
||||
/* PERI.DIV_16_CTL */
|
||||
#define PERI_V2_DIV_16_CTL_EN_Pos 0UL
|
||||
#define PERI_V2_DIV_16_CTL_EN_Msk 0x1UL
|
||||
#define PERI_V2_DIV_16_CTL_INT16_DIV_Pos 8UL
|
||||
#define PERI_V2_DIV_16_CTL_INT16_DIV_Msk 0xFFFF00UL
|
||||
/* PERI.DIV_16_5_CTL */
|
||||
#define PERI_V2_DIV_16_5_CTL_EN_Pos 0UL
|
||||
#define PERI_V2_DIV_16_5_CTL_EN_Msk 0x1UL
|
||||
#define PERI_V2_DIV_16_5_CTL_FRAC5_DIV_Pos 3UL
|
||||
#define PERI_V2_DIV_16_5_CTL_FRAC5_DIV_Msk 0xF8UL
|
||||
#define PERI_V2_DIV_16_5_CTL_INT16_DIV_Pos 8UL
|
||||
#define PERI_V2_DIV_16_5_CTL_INT16_DIV_Msk 0xFFFF00UL
|
||||
/* PERI.DIV_24_5_CTL */
|
||||
#define PERI_V2_DIV_24_5_CTL_EN_Pos 0UL
|
||||
#define PERI_V2_DIV_24_5_CTL_EN_Msk 0x1UL
|
||||
#define PERI_V2_DIV_24_5_CTL_FRAC5_DIV_Pos 3UL
|
||||
#define PERI_V2_DIV_24_5_CTL_FRAC5_DIV_Msk 0xF8UL
|
||||
#define PERI_V2_DIV_24_5_CTL_INT24_DIV_Pos 8UL
|
||||
#define PERI_V2_DIV_24_5_CTL_INT24_DIV_Msk 0xFFFFFF00UL
|
||||
/* PERI.ECC_CTL */
|
||||
#define PERI_V2_ECC_CTL_WORD_ADDR_Pos 0UL
|
||||
#define PERI_V2_ECC_CTL_WORD_ADDR_Msk 0x7FFUL
|
||||
#define PERI_V2_ECC_CTL_ECC_EN_Pos 16UL
|
||||
#define PERI_V2_ECC_CTL_ECC_EN_Msk 0x10000UL
|
||||
#define PERI_V2_ECC_CTL_ECC_INJ_EN_Pos 18UL
|
||||
#define PERI_V2_ECC_CTL_ECC_INJ_EN_Msk 0x40000UL
|
||||
#define PERI_V2_ECC_CTL_PARITY_Pos 24UL
|
||||
#define PERI_V2_ECC_CTL_PARITY_Msk 0xFF000000UL
|
||||
|
||||
|
||||
#endif /* _CYIP_PERI_V2_H_ */
|
||||
|
||||
|
||||
/* [] END OF FILE */
|
||||
|
|
@ -1,106 +0,0 @@
|
|||
/***************************************************************************//**
|
||||
* \file cyip_profile.h
|
||||
*
|
||||
* \brief
|
||||
* PROFILE IP definitions
|
||||
*
|
||||
* \note
|
||||
* Generator version: 1.3.0.1146
|
||||
* Database revision: rev#1050929
|
||||
*
|
||||
********************************************************************************
|
||||
* \copyright
|
||||
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
|
||||
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _CYIP_PROFILE_H_
|
||||
#define _CYIP_PROFILE_H_
|
||||
|
||||
#include "cyip_headers.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* PROFILE
|
||||
*******************************************************************************/
|
||||
|
||||
#define PROFILE_CNT_STRUCT_SECTION_SIZE 0x00000010UL
|
||||
#define PROFILE_SECTION_SIZE 0x00010000UL
|
||||
|
||||
/**
|
||||
* \brief Profile counter structure (PROFILE_CNT_STRUCT)
|
||||
*/
|
||||
typedef struct {
|
||||
__IOM uint32_t CTL; /*!< 0x00000000 Profile counter configuration */
|
||||
__IM uint32_t RESERVED;
|
||||
__IOM uint32_t CNT; /*!< 0x00000008 Profile counter value */
|
||||
__IM uint32_t RESERVED1;
|
||||
} PROFILE_CNT_STRUCT_V1_Type; /*!< Size = 16 (0x10) */
|
||||
|
||||
/**
|
||||
* \brief Energy Profiler IP (PROFILE)
|
||||
*/
|
||||
typedef struct {
|
||||
__IOM uint32_t CTL; /*!< 0x00000000 Profile control */
|
||||
__IM uint32_t STATUS; /*!< 0x00000004 Profile status */
|
||||
__IM uint32_t RESERVED[2];
|
||||
__IOM uint32_t CMD; /*!< 0x00000010 Profile command */
|
||||
__IM uint32_t RESERVED1[491];
|
||||
__IOM uint32_t INTR; /*!< 0x000007C0 Profile interrupt */
|
||||
__IOM uint32_t INTR_SET; /*!< 0x000007C4 Profile interrupt set */
|
||||
__IOM uint32_t INTR_MASK; /*!< 0x000007C8 Profile interrupt mask */
|
||||
__IM uint32_t INTR_MASKED; /*!< 0x000007CC Profile interrupt masked */
|
||||
__IM uint32_t RESERVED2[12];
|
||||
PROFILE_CNT_STRUCT_V1_Type CNT_STRUCT[16]; /*!< 0x00000800 Profile counter structure */
|
||||
} PROFILE_V1_Type; /*!< Size = 2304 (0x900) */
|
||||
|
||||
|
||||
/* PROFILE_CNT_STRUCT.CTL */
|
||||
#define PROFILE_CNT_STRUCT_CTL_CNT_DURATION_Pos 0UL
|
||||
#define PROFILE_CNT_STRUCT_CTL_CNT_DURATION_Msk 0x1UL
|
||||
#define PROFILE_CNT_STRUCT_CTL_REF_CLK_SEL_Pos 4UL
|
||||
#define PROFILE_CNT_STRUCT_CTL_REF_CLK_SEL_Msk 0x70UL
|
||||
#define PROFILE_CNT_STRUCT_CTL_MON_SEL_Pos 16UL
|
||||
#define PROFILE_CNT_STRUCT_CTL_MON_SEL_Msk 0x7F0000UL
|
||||
#define PROFILE_CNT_STRUCT_CTL_ENABLED_Pos 31UL
|
||||
#define PROFILE_CNT_STRUCT_CTL_ENABLED_Msk 0x80000000UL
|
||||
/* PROFILE_CNT_STRUCT.CNT */
|
||||
#define PROFILE_CNT_STRUCT_CNT_CNT_Pos 0UL
|
||||
#define PROFILE_CNT_STRUCT_CNT_CNT_Msk 0xFFFFFFFFUL
|
||||
|
||||
|
||||
/* PROFILE.CTL */
|
||||
#define PROFILE_CTL_WIN_MODE_Pos 0UL
|
||||
#define PROFILE_CTL_WIN_MODE_Msk 0x1UL
|
||||
#define PROFILE_CTL_ENABLED_Pos 31UL
|
||||
#define PROFILE_CTL_ENABLED_Msk 0x80000000UL
|
||||
/* PROFILE.STATUS */
|
||||
#define PROFILE_STATUS_WIN_ACTIVE_Pos 0UL
|
||||
#define PROFILE_STATUS_WIN_ACTIVE_Msk 0x1UL
|
||||
/* PROFILE.CMD */
|
||||
#define PROFILE_CMD_START_TR_Pos 0UL
|
||||
#define PROFILE_CMD_START_TR_Msk 0x1UL
|
||||
#define PROFILE_CMD_STOP_TR_Pos 1UL
|
||||
#define PROFILE_CMD_STOP_TR_Msk 0x2UL
|
||||
#define PROFILE_CMD_CLR_ALL_CNT_Pos 8UL
|
||||
#define PROFILE_CMD_CLR_ALL_CNT_Msk 0x100UL
|
||||
/* PROFILE.INTR */
|
||||
#define PROFILE_INTR_CNT_OVFLW_Pos 0UL
|
||||
#define PROFILE_INTR_CNT_OVFLW_Msk 0xFFFFFFFFUL
|
||||
/* PROFILE.INTR_SET */
|
||||
#define PROFILE_INTR_SET_CNT_OVFLW_Pos 0UL
|
||||
#define PROFILE_INTR_SET_CNT_OVFLW_Msk 0xFFFFFFFFUL
|
||||
/* PROFILE.INTR_MASK */
|
||||
#define PROFILE_INTR_MASK_CNT_OVFLW_Pos 0UL
|
||||
#define PROFILE_INTR_MASK_CNT_OVFLW_Msk 0xFFFFFFFFUL
|
||||
/* PROFILE.INTR_MASKED */
|
||||
#define PROFILE_INTR_MASKED_CNT_OVFLW_Pos 0UL
|
||||
#define PROFILE_INTR_MASKED_CNT_OVFLW_Msk 0xFFFFFFFFUL
|
||||
|
||||
|
||||
#endif /* _CYIP_PROFILE_H_ */
|
||||
|
||||
|
||||
/* [] END OF FILE */
|
||||
|
|
@ -1,375 +0,0 @@
|
|||
/***************************************************************************//**
|
||||
* \file cyip_prot.h
|
||||
*
|
||||
* \brief
|
||||
* PROT IP definitions
|
||||
*
|
||||
* \note
|
||||
* Generator version: 1.3.0.1146
|
||||
* Database revision: rev#1050929
|
||||
*
|
||||
********************************************************************************
|
||||
* \copyright
|
||||
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
|
||||
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _CYIP_PROT_H_
|
||||
#define _CYIP_PROT_H_
|
||||
|
||||
#include "cyip_headers.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* PROT
|
||||
*******************************************************************************/
|
||||
|
||||
#define PROT_SMPU_SMPU_STRUCT_SECTION_SIZE 0x00000040UL
|
||||
#define PROT_SMPU_SECTION_SIZE 0x00004000UL
|
||||
#define PROT_MPU_MPU_STRUCT_SECTION_SIZE 0x00000020UL
|
||||
#define PROT_MPU_SECTION_SIZE 0x00000400UL
|
||||
#define PROT_SECTION_SIZE 0x00010000UL
|
||||
|
||||
/**
|
||||
* \brief SMPU structure (PROT_SMPU_SMPU_STRUCT)
|
||||
*/
|
||||
typedef struct {
|
||||
__IOM uint32_t ADDR0; /*!< 0x00000000 SMPU region address 0 (slave structure) */
|
||||
__IOM uint32_t ATT0; /*!< 0x00000004 SMPU region attributes 0 (slave structure) */
|
||||
__IM uint32_t RESERVED[6];
|
||||
__IM uint32_t ADDR1; /*!< 0x00000020 SMPU region address 1 (master structure) */
|
||||
__IOM uint32_t ATT1; /*!< 0x00000024 SMPU region attributes 1 (master structure) */
|
||||
__IM uint32_t RESERVED1[6];
|
||||
} PROT_SMPU_SMPU_STRUCT_V1_Type; /*!< Size = 64 (0x40) */
|
||||
|
||||
/**
|
||||
* \brief SMPU (PROT_SMPU)
|
||||
*/
|
||||
typedef struct {
|
||||
__IOM uint32_t MS0_CTL; /*!< 0x00000000 Master 0 protection context control */
|
||||
__IOM uint32_t MS1_CTL; /*!< 0x00000004 Master 1 protection context control */
|
||||
__IOM uint32_t MS2_CTL; /*!< 0x00000008 Master 2 protection context control */
|
||||
__IOM uint32_t MS3_CTL; /*!< 0x0000000C Master 3 protection context control */
|
||||
__IOM uint32_t MS4_CTL; /*!< 0x00000010 Master 4 protection context control */
|
||||
__IOM uint32_t MS5_CTL; /*!< 0x00000014 Master 5 protection context control */
|
||||
__IOM uint32_t MS6_CTL; /*!< 0x00000018 Master 6 protection context control */
|
||||
__IOM uint32_t MS7_CTL; /*!< 0x0000001C Master 7 protection context control */
|
||||
__IOM uint32_t MS8_CTL; /*!< 0x00000020 Master 8 protection context control */
|
||||
__IOM uint32_t MS9_CTL; /*!< 0x00000024 Master 9 protection context control */
|
||||
__IOM uint32_t MS10_CTL; /*!< 0x00000028 Master 10 protection context control */
|
||||
__IOM uint32_t MS11_CTL; /*!< 0x0000002C Master 11 protection context control */
|
||||
__IOM uint32_t MS12_CTL; /*!< 0x00000030 Master 12 protection context control */
|
||||
__IOM uint32_t MS13_CTL; /*!< 0x00000034 Master 13 protection context control */
|
||||
__IOM uint32_t MS14_CTL; /*!< 0x00000038 Master 14 protection context control */
|
||||
__IOM uint32_t MS15_CTL; /*!< 0x0000003C Master 15 protection context control */
|
||||
__IM uint32_t RESERVED[2032];
|
||||
PROT_SMPU_SMPU_STRUCT_V1_Type SMPU_STRUCT[32]; /*!< 0x00002000 SMPU structure */
|
||||
__IM uint32_t RESERVED1[1536];
|
||||
} PROT_SMPU_V1_Type; /*!< Size = 16384 (0x4000) */
|
||||
|
||||
/**
|
||||
* \brief MPU structure (PROT_MPU_MPU_STRUCT)
|
||||
*/
|
||||
typedef struct {
|
||||
__IOM uint32_t ADDR; /*!< 0x00000000 MPU region address */
|
||||
__IOM uint32_t ATT; /*!< 0x00000004 MPU region attrributes */
|
||||
__IM uint32_t RESERVED[6];
|
||||
} PROT_MPU_MPU_STRUCT_V1_Type; /*!< Size = 32 (0x20) */
|
||||
|
||||
/**
|
||||
* \brief MPU (PROT_MPU)
|
||||
*/
|
||||
typedef struct {
|
||||
__IOM uint32_t MS_CTL; /*!< 0x00000000 Master control */
|
||||
__IM uint32_t RESERVED[127];
|
||||
PROT_MPU_MPU_STRUCT_V1_Type MPU_STRUCT[16]; /*!< 0x00000200 MPU structure */
|
||||
} PROT_MPU_V1_Type; /*!< Size = 1024 (0x400) */
|
||||
|
||||
/**
|
||||
* \brief Protection (PROT)
|
||||
*/
|
||||
typedef struct {
|
||||
PROT_SMPU_V1_Type SMPU; /*!< 0x00000000 SMPU */
|
||||
PROT_MPU_V1_Type CYMPU[16]; /*!< 0x00004000 MPU */
|
||||
} PROT_V1_Type; /*!< Size = 32768 (0x8000) */
|
||||
|
||||
|
||||
/* PROT_SMPU_SMPU_STRUCT.ADDR0 */
|
||||
#define PROT_SMPU_SMPU_STRUCT_ADDR0_SUBREGION_DISABLE_Pos 0UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_ADDR0_SUBREGION_DISABLE_Msk 0xFFUL
|
||||
#define PROT_SMPU_SMPU_STRUCT_ADDR0_ADDR24_Pos 8UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_ADDR0_ADDR24_Msk 0xFFFFFF00UL
|
||||
/* PROT_SMPU_SMPU_STRUCT.ATT0 */
|
||||
#define PROT_SMPU_SMPU_STRUCT_ATT0_UR_Pos 0UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_ATT0_UR_Msk 0x1UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_ATT0_UW_Pos 1UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_ATT0_UW_Msk 0x2UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_ATT0_UX_Pos 2UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_ATT0_UX_Msk 0x4UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_ATT0_PR_Pos 3UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_ATT0_PR_Msk 0x8UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_ATT0_PW_Pos 4UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_ATT0_PW_Msk 0x10UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_ATT0_PX_Pos 5UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_ATT0_PX_Msk 0x20UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_ATT0_NS_Pos 6UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_ATT0_NS_Msk 0x40UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_ATT0_PC_MASK_0_Pos 8UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_ATT0_PC_MASK_0_Msk 0x100UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_ATT0_PC_MASK_15_TO_1_Pos 9UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_ATT0_PC_MASK_15_TO_1_Msk 0xFFFE00UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_ATT0_REGION_SIZE_Pos 24UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_ATT0_REGION_SIZE_Msk 0x1F000000UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_ATT0_PC_MATCH_Pos 30UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_ATT0_PC_MATCH_Msk 0x40000000UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_ATT0_ENABLED_Pos 31UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_ATT0_ENABLED_Msk 0x80000000UL
|
||||
/* PROT_SMPU_SMPU_STRUCT.ADDR1 */
|
||||
#define PROT_SMPU_SMPU_STRUCT_ADDR1_SUBREGION_DISABLE_Pos 0UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_ADDR1_SUBREGION_DISABLE_Msk 0xFFUL
|
||||
#define PROT_SMPU_SMPU_STRUCT_ADDR1_ADDR24_Pos 8UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_ADDR1_ADDR24_Msk 0xFFFFFF00UL
|
||||
/* PROT_SMPU_SMPU_STRUCT.ATT1 */
|
||||
#define PROT_SMPU_SMPU_STRUCT_ATT1_UR_Pos 0UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_ATT1_UR_Msk 0x1UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_ATT1_UW_Pos 1UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_ATT1_UW_Msk 0x2UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_ATT1_UX_Pos 2UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_ATT1_UX_Msk 0x4UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_ATT1_PR_Pos 3UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_ATT1_PR_Msk 0x8UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_ATT1_PW_Pos 4UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_ATT1_PW_Msk 0x10UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_ATT1_PX_Pos 5UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_ATT1_PX_Msk 0x20UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_ATT1_NS_Pos 6UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_ATT1_NS_Msk 0x40UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_ATT1_PC_MASK_0_Pos 8UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_ATT1_PC_MASK_0_Msk 0x100UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_ATT1_PC_MASK_15_TO_1_Pos 9UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_ATT1_PC_MASK_15_TO_1_Msk 0xFFFE00UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_ATT1_REGION_SIZE_Pos 24UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_ATT1_REGION_SIZE_Msk 0x1F000000UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_ATT1_PC_MATCH_Pos 30UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_ATT1_PC_MATCH_Msk 0x40000000UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_ATT1_ENABLED_Pos 31UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_ATT1_ENABLED_Msk 0x80000000UL
|
||||
|
||||
|
||||
/* PROT_SMPU.MS0_CTL */
|
||||
#define PROT_SMPU_MS0_CTL_P_Pos 0UL
|
||||
#define PROT_SMPU_MS0_CTL_P_Msk 0x1UL
|
||||
#define PROT_SMPU_MS0_CTL_NS_Pos 1UL
|
||||
#define PROT_SMPU_MS0_CTL_NS_Msk 0x2UL
|
||||
#define PROT_SMPU_MS0_CTL_PRIO_Pos 8UL
|
||||
#define PROT_SMPU_MS0_CTL_PRIO_Msk 0x300UL
|
||||
#define PROT_SMPU_MS0_CTL_PC_MASK_0_Pos 16UL
|
||||
#define PROT_SMPU_MS0_CTL_PC_MASK_0_Msk 0x10000UL
|
||||
#define PROT_SMPU_MS0_CTL_PC_MASK_15_TO_1_Pos 17UL
|
||||
#define PROT_SMPU_MS0_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL
|
||||
/* PROT_SMPU.MS1_CTL */
|
||||
#define PROT_SMPU_MS1_CTL_P_Pos 0UL
|
||||
#define PROT_SMPU_MS1_CTL_P_Msk 0x1UL
|
||||
#define PROT_SMPU_MS1_CTL_NS_Pos 1UL
|
||||
#define PROT_SMPU_MS1_CTL_NS_Msk 0x2UL
|
||||
#define PROT_SMPU_MS1_CTL_PRIO_Pos 8UL
|
||||
#define PROT_SMPU_MS1_CTL_PRIO_Msk 0x300UL
|
||||
#define PROT_SMPU_MS1_CTL_PC_MASK_0_Pos 16UL
|
||||
#define PROT_SMPU_MS1_CTL_PC_MASK_0_Msk 0x10000UL
|
||||
#define PROT_SMPU_MS1_CTL_PC_MASK_15_TO_1_Pos 17UL
|
||||
#define PROT_SMPU_MS1_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL
|
||||
/* PROT_SMPU.MS2_CTL */
|
||||
#define PROT_SMPU_MS2_CTL_P_Pos 0UL
|
||||
#define PROT_SMPU_MS2_CTL_P_Msk 0x1UL
|
||||
#define PROT_SMPU_MS2_CTL_NS_Pos 1UL
|
||||
#define PROT_SMPU_MS2_CTL_NS_Msk 0x2UL
|
||||
#define PROT_SMPU_MS2_CTL_PRIO_Pos 8UL
|
||||
#define PROT_SMPU_MS2_CTL_PRIO_Msk 0x300UL
|
||||
#define PROT_SMPU_MS2_CTL_PC_MASK_0_Pos 16UL
|
||||
#define PROT_SMPU_MS2_CTL_PC_MASK_0_Msk 0x10000UL
|
||||
#define PROT_SMPU_MS2_CTL_PC_MASK_15_TO_1_Pos 17UL
|
||||
#define PROT_SMPU_MS2_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL
|
||||
/* PROT_SMPU.MS3_CTL */
|
||||
#define PROT_SMPU_MS3_CTL_P_Pos 0UL
|
||||
#define PROT_SMPU_MS3_CTL_P_Msk 0x1UL
|
||||
#define PROT_SMPU_MS3_CTL_NS_Pos 1UL
|
||||
#define PROT_SMPU_MS3_CTL_NS_Msk 0x2UL
|
||||
#define PROT_SMPU_MS3_CTL_PRIO_Pos 8UL
|
||||
#define PROT_SMPU_MS3_CTL_PRIO_Msk 0x300UL
|
||||
#define PROT_SMPU_MS3_CTL_PC_MASK_0_Pos 16UL
|
||||
#define PROT_SMPU_MS3_CTL_PC_MASK_0_Msk 0x10000UL
|
||||
#define PROT_SMPU_MS3_CTL_PC_MASK_15_TO_1_Pos 17UL
|
||||
#define PROT_SMPU_MS3_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL
|
||||
/* PROT_SMPU.MS4_CTL */
|
||||
#define PROT_SMPU_MS4_CTL_P_Pos 0UL
|
||||
#define PROT_SMPU_MS4_CTL_P_Msk 0x1UL
|
||||
#define PROT_SMPU_MS4_CTL_NS_Pos 1UL
|
||||
#define PROT_SMPU_MS4_CTL_NS_Msk 0x2UL
|
||||
#define PROT_SMPU_MS4_CTL_PRIO_Pos 8UL
|
||||
#define PROT_SMPU_MS4_CTL_PRIO_Msk 0x300UL
|
||||
#define PROT_SMPU_MS4_CTL_PC_MASK_0_Pos 16UL
|
||||
#define PROT_SMPU_MS4_CTL_PC_MASK_0_Msk 0x10000UL
|
||||
#define PROT_SMPU_MS4_CTL_PC_MASK_15_TO_1_Pos 17UL
|
||||
#define PROT_SMPU_MS4_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL
|
||||
/* PROT_SMPU.MS5_CTL */
|
||||
#define PROT_SMPU_MS5_CTL_P_Pos 0UL
|
||||
#define PROT_SMPU_MS5_CTL_P_Msk 0x1UL
|
||||
#define PROT_SMPU_MS5_CTL_NS_Pos 1UL
|
||||
#define PROT_SMPU_MS5_CTL_NS_Msk 0x2UL
|
||||
#define PROT_SMPU_MS5_CTL_PRIO_Pos 8UL
|
||||
#define PROT_SMPU_MS5_CTL_PRIO_Msk 0x300UL
|
||||
#define PROT_SMPU_MS5_CTL_PC_MASK_0_Pos 16UL
|
||||
#define PROT_SMPU_MS5_CTL_PC_MASK_0_Msk 0x10000UL
|
||||
#define PROT_SMPU_MS5_CTL_PC_MASK_15_TO_1_Pos 17UL
|
||||
#define PROT_SMPU_MS5_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL
|
||||
/* PROT_SMPU.MS6_CTL */
|
||||
#define PROT_SMPU_MS6_CTL_P_Pos 0UL
|
||||
#define PROT_SMPU_MS6_CTL_P_Msk 0x1UL
|
||||
#define PROT_SMPU_MS6_CTL_NS_Pos 1UL
|
||||
#define PROT_SMPU_MS6_CTL_NS_Msk 0x2UL
|
||||
#define PROT_SMPU_MS6_CTL_PRIO_Pos 8UL
|
||||
#define PROT_SMPU_MS6_CTL_PRIO_Msk 0x300UL
|
||||
#define PROT_SMPU_MS6_CTL_PC_MASK_0_Pos 16UL
|
||||
#define PROT_SMPU_MS6_CTL_PC_MASK_0_Msk 0x10000UL
|
||||
#define PROT_SMPU_MS6_CTL_PC_MASK_15_TO_1_Pos 17UL
|
||||
#define PROT_SMPU_MS6_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL
|
||||
/* PROT_SMPU.MS7_CTL */
|
||||
#define PROT_SMPU_MS7_CTL_P_Pos 0UL
|
||||
#define PROT_SMPU_MS7_CTL_P_Msk 0x1UL
|
||||
#define PROT_SMPU_MS7_CTL_NS_Pos 1UL
|
||||
#define PROT_SMPU_MS7_CTL_NS_Msk 0x2UL
|
||||
#define PROT_SMPU_MS7_CTL_PRIO_Pos 8UL
|
||||
#define PROT_SMPU_MS7_CTL_PRIO_Msk 0x300UL
|
||||
#define PROT_SMPU_MS7_CTL_PC_MASK_0_Pos 16UL
|
||||
#define PROT_SMPU_MS7_CTL_PC_MASK_0_Msk 0x10000UL
|
||||
#define PROT_SMPU_MS7_CTL_PC_MASK_15_TO_1_Pos 17UL
|
||||
#define PROT_SMPU_MS7_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL
|
||||
/* PROT_SMPU.MS8_CTL */
|
||||
#define PROT_SMPU_MS8_CTL_P_Pos 0UL
|
||||
#define PROT_SMPU_MS8_CTL_P_Msk 0x1UL
|
||||
#define PROT_SMPU_MS8_CTL_NS_Pos 1UL
|
||||
#define PROT_SMPU_MS8_CTL_NS_Msk 0x2UL
|
||||
#define PROT_SMPU_MS8_CTL_PRIO_Pos 8UL
|
||||
#define PROT_SMPU_MS8_CTL_PRIO_Msk 0x300UL
|
||||
#define PROT_SMPU_MS8_CTL_PC_MASK_0_Pos 16UL
|
||||
#define PROT_SMPU_MS8_CTL_PC_MASK_0_Msk 0x10000UL
|
||||
#define PROT_SMPU_MS8_CTL_PC_MASK_15_TO_1_Pos 17UL
|
||||
#define PROT_SMPU_MS8_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL
|
||||
/* PROT_SMPU.MS9_CTL */
|
||||
#define PROT_SMPU_MS9_CTL_P_Pos 0UL
|
||||
#define PROT_SMPU_MS9_CTL_P_Msk 0x1UL
|
||||
#define PROT_SMPU_MS9_CTL_NS_Pos 1UL
|
||||
#define PROT_SMPU_MS9_CTL_NS_Msk 0x2UL
|
||||
#define PROT_SMPU_MS9_CTL_PRIO_Pos 8UL
|
||||
#define PROT_SMPU_MS9_CTL_PRIO_Msk 0x300UL
|
||||
#define PROT_SMPU_MS9_CTL_PC_MASK_0_Pos 16UL
|
||||
#define PROT_SMPU_MS9_CTL_PC_MASK_0_Msk 0x10000UL
|
||||
#define PROT_SMPU_MS9_CTL_PC_MASK_15_TO_1_Pos 17UL
|
||||
#define PROT_SMPU_MS9_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL
|
||||
/* PROT_SMPU.MS10_CTL */
|
||||
#define PROT_SMPU_MS10_CTL_P_Pos 0UL
|
||||
#define PROT_SMPU_MS10_CTL_P_Msk 0x1UL
|
||||
#define PROT_SMPU_MS10_CTL_NS_Pos 1UL
|
||||
#define PROT_SMPU_MS10_CTL_NS_Msk 0x2UL
|
||||
#define PROT_SMPU_MS10_CTL_PRIO_Pos 8UL
|
||||
#define PROT_SMPU_MS10_CTL_PRIO_Msk 0x300UL
|
||||
#define PROT_SMPU_MS10_CTL_PC_MASK_0_Pos 16UL
|
||||
#define PROT_SMPU_MS10_CTL_PC_MASK_0_Msk 0x10000UL
|
||||
#define PROT_SMPU_MS10_CTL_PC_MASK_15_TO_1_Pos 17UL
|
||||
#define PROT_SMPU_MS10_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL
|
||||
/* PROT_SMPU.MS11_CTL */
|
||||
#define PROT_SMPU_MS11_CTL_P_Pos 0UL
|
||||
#define PROT_SMPU_MS11_CTL_P_Msk 0x1UL
|
||||
#define PROT_SMPU_MS11_CTL_NS_Pos 1UL
|
||||
#define PROT_SMPU_MS11_CTL_NS_Msk 0x2UL
|
||||
#define PROT_SMPU_MS11_CTL_PRIO_Pos 8UL
|
||||
#define PROT_SMPU_MS11_CTL_PRIO_Msk 0x300UL
|
||||
#define PROT_SMPU_MS11_CTL_PC_MASK_0_Pos 16UL
|
||||
#define PROT_SMPU_MS11_CTL_PC_MASK_0_Msk 0x10000UL
|
||||
#define PROT_SMPU_MS11_CTL_PC_MASK_15_TO_1_Pos 17UL
|
||||
#define PROT_SMPU_MS11_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL
|
||||
/* PROT_SMPU.MS12_CTL */
|
||||
#define PROT_SMPU_MS12_CTL_P_Pos 0UL
|
||||
#define PROT_SMPU_MS12_CTL_P_Msk 0x1UL
|
||||
#define PROT_SMPU_MS12_CTL_NS_Pos 1UL
|
||||
#define PROT_SMPU_MS12_CTL_NS_Msk 0x2UL
|
||||
#define PROT_SMPU_MS12_CTL_PRIO_Pos 8UL
|
||||
#define PROT_SMPU_MS12_CTL_PRIO_Msk 0x300UL
|
||||
#define PROT_SMPU_MS12_CTL_PC_MASK_0_Pos 16UL
|
||||
#define PROT_SMPU_MS12_CTL_PC_MASK_0_Msk 0x10000UL
|
||||
#define PROT_SMPU_MS12_CTL_PC_MASK_15_TO_1_Pos 17UL
|
||||
#define PROT_SMPU_MS12_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL
|
||||
/* PROT_SMPU.MS13_CTL */
|
||||
#define PROT_SMPU_MS13_CTL_P_Pos 0UL
|
||||
#define PROT_SMPU_MS13_CTL_P_Msk 0x1UL
|
||||
#define PROT_SMPU_MS13_CTL_NS_Pos 1UL
|
||||
#define PROT_SMPU_MS13_CTL_NS_Msk 0x2UL
|
||||
#define PROT_SMPU_MS13_CTL_PRIO_Pos 8UL
|
||||
#define PROT_SMPU_MS13_CTL_PRIO_Msk 0x300UL
|
||||
#define PROT_SMPU_MS13_CTL_PC_MASK_0_Pos 16UL
|
||||
#define PROT_SMPU_MS13_CTL_PC_MASK_0_Msk 0x10000UL
|
||||
#define PROT_SMPU_MS13_CTL_PC_MASK_15_TO_1_Pos 17UL
|
||||
#define PROT_SMPU_MS13_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL
|
||||
/* PROT_SMPU.MS14_CTL */
|
||||
#define PROT_SMPU_MS14_CTL_P_Pos 0UL
|
||||
#define PROT_SMPU_MS14_CTL_P_Msk 0x1UL
|
||||
#define PROT_SMPU_MS14_CTL_NS_Pos 1UL
|
||||
#define PROT_SMPU_MS14_CTL_NS_Msk 0x2UL
|
||||
#define PROT_SMPU_MS14_CTL_PRIO_Pos 8UL
|
||||
#define PROT_SMPU_MS14_CTL_PRIO_Msk 0x300UL
|
||||
#define PROT_SMPU_MS14_CTL_PC_MASK_0_Pos 16UL
|
||||
#define PROT_SMPU_MS14_CTL_PC_MASK_0_Msk 0x10000UL
|
||||
#define PROT_SMPU_MS14_CTL_PC_MASK_15_TO_1_Pos 17UL
|
||||
#define PROT_SMPU_MS14_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL
|
||||
/* PROT_SMPU.MS15_CTL */
|
||||
#define PROT_SMPU_MS15_CTL_P_Pos 0UL
|
||||
#define PROT_SMPU_MS15_CTL_P_Msk 0x1UL
|
||||
#define PROT_SMPU_MS15_CTL_NS_Pos 1UL
|
||||
#define PROT_SMPU_MS15_CTL_NS_Msk 0x2UL
|
||||
#define PROT_SMPU_MS15_CTL_PRIO_Pos 8UL
|
||||
#define PROT_SMPU_MS15_CTL_PRIO_Msk 0x300UL
|
||||
#define PROT_SMPU_MS15_CTL_PC_MASK_0_Pos 16UL
|
||||
#define PROT_SMPU_MS15_CTL_PC_MASK_0_Msk 0x10000UL
|
||||
#define PROT_SMPU_MS15_CTL_PC_MASK_15_TO_1_Pos 17UL
|
||||
#define PROT_SMPU_MS15_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL
|
||||
|
||||
|
||||
/* PROT_MPU_MPU_STRUCT.ADDR */
|
||||
#define PROT_MPU_MPU_STRUCT_ADDR_SUBREGION_DISABLE_Pos 0UL
|
||||
#define PROT_MPU_MPU_STRUCT_ADDR_SUBREGION_DISABLE_Msk 0xFFUL
|
||||
#define PROT_MPU_MPU_STRUCT_ADDR_ADDR24_Pos 8UL
|
||||
#define PROT_MPU_MPU_STRUCT_ADDR_ADDR24_Msk 0xFFFFFF00UL
|
||||
/* PROT_MPU_MPU_STRUCT.ATT */
|
||||
#define PROT_MPU_MPU_STRUCT_ATT_UR_Pos 0UL
|
||||
#define PROT_MPU_MPU_STRUCT_ATT_UR_Msk 0x1UL
|
||||
#define PROT_MPU_MPU_STRUCT_ATT_UW_Pos 1UL
|
||||
#define PROT_MPU_MPU_STRUCT_ATT_UW_Msk 0x2UL
|
||||
#define PROT_MPU_MPU_STRUCT_ATT_UX_Pos 2UL
|
||||
#define PROT_MPU_MPU_STRUCT_ATT_UX_Msk 0x4UL
|
||||
#define PROT_MPU_MPU_STRUCT_ATT_PR_Pos 3UL
|
||||
#define PROT_MPU_MPU_STRUCT_ATT_PR_Msk 0x8UL
|
||||
#define PROT_MPU_MPU_STRUCT_ATT_PW_Pos 4UL
|
||||
#define PROT_MPU_MPU_STRUCT_ATT_PW_Msk 0x10UL
|
||||
#define PROT_MPU_MPU_STRUCT_ATT_PX_Pos 5UL
|
||||
#define PROT_MPU_MPU_STRUCT_ATT_PX_Msk 0x20UL
|
||||
#define PROT_MPU_MPU_STRUCT_ATT_NS_Pos 6UL
|
||||
#define PROT_MPU_MPU_STRUCT_ATT_NS_Msk 0x40UL
|
||||
#define PROT_MPU_MPU_STRUCT_ATT_REGION_SIZE_Pos 24UL
|
||||
#define PROT_MPU_MPU_STRUCT_ATT_REGION_SIZE_Msk 0x1F000000UL
|
||||
#define PROT_MPU_MPU_STRUCT_ATT_ENABLED_Pos 31UL
|
||||
#define PROT_MPU_MPU_STRUCT_ATT_ENABLED_Msk 0x80000000UL
|
||||
|
||||
|
||||
/* PROT_MPU.MS_CTL */
|
||||
#define PROT_MPU_MS_CTL_PC_Pos 0UL
|
||||
#define PROT_MPU_MS_CTL_PC_Msk 0xFUL
|
||||
#define PROT_MPU_MS_CTL_PC_SAVED_Pos 16UL
|
||||
#define PROT_MPU_MS_CTL_PC_SAVED_Msk 0xF0000UL
|
||||
|
||||
|
||||
#endif /* _CYIP_PROT_H_ */
|
||||
|
||||
|
||||
/* [] END OF FILE */
|
||||
|
|
@ -1,375 +0,0 @@
|
|||
/***************************************************************************//**
|
||||
* \file cyip_prot_v2.h
|
||||
*
|
||||
* \brief
|
||||
* PROT IP definitions
|
||||
*
|
||||
* \note
|
||||
* Generator version: 1.3.0.1146
|
||||
* Database revision: rev#1050929
|
||||
*
|
||||
********************************************************************************
|
||||
* \copyright
|
||||
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
|
||||
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _CYIP_PROT_V2_H_
|
||||
#define _CYIP_PROT_V2_H_
|
||||
|
||||
#include "cyip_headers.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* PROT
|
||||
*******************************************************************************/
|
||||
|
||||
#define PROT_SMPU_SMPU_STRUCT_V2_SECTION_SIZE 0x00000040UL
|
||||
#define PROT_SMPU_V2_SECTION_SIZE 0x00004000UL
|
||||
#define PROT_MPU_MPU_STRUCT_V2_SECTION_SIZE 0x00000020UL
|
||||
#define PROT_MPU_V2_SECTION_SIZE 0x00000400UL
|
||||
#define PROT_V2_SECTION_SIZE 0x00010000UL
|
||||
|
||||
/**
|
||||
* \brief SMPU structure (PROT_SMPU_SMPU_STRUCT)
|
||||
*/
|
||||
typedef struct {
|
||||
__IOM uint32_t ADDR0; /*!< 0x00000000 SMPU region address 0 (slave structure) */
|
||||
__IOM uint32_t ATT0; /*!< 0x00000004 SMPU region attributes 0 (slave structure) */
|
||||
__IM uint32_t RESERVED[6];
|
||||
__IM uint32_t ADDR1; /*!< 0x00000020 SMPU region address 1 (master structure) */
|
||||
__IOM uint32_t ATT1; /*!< 0x00000024 SMPU region attributes 1 (master structure) */
|
||||
__IM uint32_t RESERVED1[6];
|
||||
} PROT_SMPU_SMPU_STRUCT_V2_Type; /*!< Size = 64 (0x40) */
|
||||
|
||||
/**
|
||||
* \brief SMPU (PROT_SMPU)
|
||||
*/
|
||||
typedef struct {
|
||||
__IOM uint32_t MS0_CTL; /*!< 0x00000000 Master 0 protection context control */
|
||||
__IOM uint32_t MS1_CTL; /*!< 0x00000004 Master 1 protection context control */
|
||||
__IOM uint32_t MS2_CTL; /*!< 0x00000008 Master 2 protection context control */
|
||||
__IOM uint32_t MS3_CTL; /*!< 0x0000000C Master 3 protection context control */
|
||||
__IOM uint32_t MS4_CTL; /*!< 0x00000010 Master 4 protection context control */
|
||||
__IOM uint32_t MS5_CTL; /*!< 0x00000014 Master 5 protection context control */
|
||||
__IOM uint32_t MS6_CTL; /*!< 0x00000018 Master 6 protection context control */
|
||||
__IOM uint32_t MS7_CTL; /*!< 0x0000001C Master 7 protection context control */
|
||||
__IOM uint32_t MS8_CTL; /*!< 0x00000020 Master 8 protection context control */
|
||||
__IOM uint32_t MS9_CTL; /*!< 0x00000024 Master 9 protection context control */
|
||||
__IOM uint32_t MS10_CTL; /*!< 0x00000028 Master 10 protection context control */
|
||||
__IOM uint32_t MS11_CTL; /*!< 0x0000002C Master 11 protection context control */
|
||||
__IOM uint32_t MS12_CTL; /*!< 0x00000030 Master 12 protection context control */
|
||||
__IOM uint32_t MS13_CTL; /*!< 0x00000034 Master 13 protection context control */
|
||||
__IOM uint32_t MS14_CTL; /*!< 0x00000038 Master 14 protection context control */
|
||||
__IOM uint32_t MS15_CTL; /*!< 0x0000003C Master 15 protection context control */
|
||||
__IM uint32_t RESERVED[2032];
|
||||
PROT_SMPU_SMPU_STRUCT_V2_Type SMPU_STRUCT[32]; /*!< 0x00002000 SMPU structure */
|
||||
__IM uint32_t RESERVED1[1536];
|
||||
} PROT_SMPU_V2_Type; /*!< Size = 16384 (0x4000) */
|
||||
|
||||
/**
|
||||
* \brief MPU structure (PROT_MPU_MPU_STRUCT)
|
||||
*/
|
||||
typedef struct {
|
||||
__IOM uint32_t ADDR; /*!< 0x00000000 MPU region address */
|
||||
__IOM uint32_t ATT; /*!< 0x00000004 MPU region attrributes */
|
||||
__IM uint32_t RESERVED[6];
|
||||
} PROT_MPU_MPU_STRUCT_V2_Type; /*!< Size = 32 (0x20) */
|
||||
|
||||
/**
|
||||
* \brief MPU (PROT_MPU)
|
||||
*/
|
||||
typedef struct {
|
||||
__IOM uint32_t MS_CTL; /*!< 0x00000000 Master control */
|
||||
__IM uint32_t RESERVED[127];
|
||||
PROT_MPU_MPU_STRUCT_V2_Type MPU_STRUCT[16]; /*!< 0x00000200 MPU structure */
|
||||
} PROT_MPU_V2_Type; /*!< Size = 1024 (0x400) */
|
||||
|
||||
/**
|
||||
* \brief Protection (PROT)
|
||||
*/
|
||||
typedef struct {
|
||||
PROT_SMPU_V2_Type SMPU; /*!< 0x00000000 SMPU */
|
||||
PROT_MPU_V2_Type CYMPU[16]; /*!< 0x00004000 MPU */
|
||||
} PROT_V2_Type; /*!< Size = 32768 (0x8000) */
|
||||
|
||||
|
||||
/* PROT_SMPU_SMPU_STRUCT.ADDR0 */
|
||||
#define PROT_SMPU_SMPU_STRUCT_V2_ADDR0_SUBREGION_DISABLE_Pos 0UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_V2_ADDR0_SUBREGION_DISABLE_Msk 0xFFUL
|
||||
#define PROT_SMPU_SMPU_STRUCT_V2_ADDR0_ADDR24_Pos 8UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_V2_ADDR0_ADDR24_Msk 0xFFFFFF00UL
|
||||
/* PROT_SMPU_SMPU_STRUCT.ATT0 */
|
||||
#define PROT_SMPU_SMPU_STRUCT_V2_ATT0_UR_Pos 0UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_V2_ATT0_UR_Msk 0x1UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_V2_ATT0_UW_Pos 1UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_V2_ATT0_UW_Msk 0x2UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_V2_ATT0_UX_Pos 2UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_V2_ATT0_UX_Msk 0x4UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_V2_ATT0_PR_Pos 3UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_V2_ATT0_PR_Msk 0x8UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_V2_ATT0_PW_Pos 4UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_V2_ATT0_PW_Msk 0x10UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_V2_ATT0_PX_Pos 5UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_V2_ATT0_PX_Msk 0x20UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_V2_ATT0_NS_Pos 6UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_V2_ATT0_NS_Msk 0x40UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_V2_ATT0_PC_MASK_0_Pos 8UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_V2_ATT0_PC_MASK_0_Msk 0x100UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_V2_ATT0_PC_MASK_15_TO_1_Pos 9UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_V2_ATT0_PC_MASK_15_TO_1_Msk 0xFFFE00UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_V2_ATT0_REGION_SIZE_Pos 24UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_V2_ATT0_REGION_SIZE_Msk 0x1F000000UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_V2_ATT0_PC_MATCH_Pos 30UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_V2_ATT0_PC_MATCH_Msk 0x40000000UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_V2_ATT0_ENABLED_Pos 31UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_V2_ATT0_ENABLED_Msk 0x80000000UL
|
||||
/* PROT_SMPU_SMPU_STRUCT.ADDR1 */
|
||||
#define PROT_SMPU_SMPU_STRUCT_V2_ADDR1_SUBREGION_DISABLE_Pos 0UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_V2_ADDR1_SUBREGION_DISABLE_Msk 0xFFUL
|
||||
#define PROT_SMPU_SMPU_STRUCT_V2_ADDR1_ADDR24_Pos 8UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_V2_ADDR1_ADDR24_Msk 0xFFFFFF00UL
|
||||
/* PROT_SMPU_SMPU_STRUCT.ATT1 */
|
||||
#define PROT_SMPU_SMPU_STRUCT_V2_ATT1_UR_Pos 0UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_V2_ATT1_UR_Msk 0x1UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_V2_ATT1_UW_Pos 1UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_V2_ATT1_UW_Msk 0x2UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_V2_ATT1_UX_Pos 2UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_V2_ATT1_UX_Msk 0x4UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_V2_ATT1_PR_Pos 3UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_V2_ATT1_PR_Msk 0x8UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_V2_ATT1_PW_Pos 4UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_V2_ATT1_PW_Msk 0x10UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_V2_ATT1_PX_Pos 5UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_V2_ATT1_PX_Msk 0x20UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_V2_ATT1_NS_Pos 6UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_V2_ATT1_NS_Msk 0x40UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_V2_ATT1_PC_MASK_0_Pos 8UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_V2_ATT1_PC_MASK_0_Msk 0x100UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_V2_ATT1_PC_MASK_15_TO_1_Pos 9UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_V2_ATT1_PC_MASK_15_TO_1_Msk 0xFFFE00UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_V2_ATT1_REGION_SIZE_Pos 24UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_V2_ATT1_REGION_SIZE_Msk 0x1F000000UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_V2_ATT1_PC_MATCH_Pos 30UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_V2_ATT1_PC_MATCH_Msk 0x40000000UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_V2_ATT1_ENABLED_Pos 31UL
|
||||
#define PROT_SMPU_SMPU_STRUCT_V2_ATT1_ENABLED_Msk 0x80000000UL
|
||||
|
||||
|
||||
/* PROT_SMPU.MS0_CTL */
|
||||
#define PROT_SMPU_V2_MS0_CTL_P_Pos 0UL
|
||||
#define PROT_SMPU_V2_MS0_CTL_P_Msk 0x1UL
|
||||
#define PROT_SMPU_V2_MS0_CTL_NS_Pos 1UL
|
||||
#define PROT_SMPU_V2_MS0_CTL_NS_Msk 0x2UL
|
||||
#define PROT_SMPU_V2_MS0_CTL_PRIO_Pos 8UL
|
||||
#define PROT_SMPU_V2_MS0_CTL_PRIO_Msk 0x300UL
|
||||
#define PROT_SMPU_V2_MS0_CTL_PC_MASK_0_Pos 16UL
|
||||
#define PROT_SMPU_V2_MS0_CTL_PC_MASK_0_Msk 0x10000UL
|
||||
#define PROT_SMPU_V2_MS0_CTL_PC_MASK_15_TO_1_Pos 17UL
|
||||
#define PROT_SMPU_V2_MS0_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL
|
||||
/* PROT_SMPU.MS1_CTL */
|
||||
#define PROT_SMPU_V2_MS1_CTL_P_Pos 0UL
|
||||
#define PROT_SMPU_V2_MS1_CTL_P_Msk 0x1UL
|
||||
#define PROT_SMPU_V2_MS1_CTL_NS_Pos 1UL
|
||||
#define PROT_SMPU_V2_MS1_CTL_NS_Msk 0x2UL
|
||||
#define PROT_SMPU_V2_MS1_CTL_PRIO_Pos 8UL
|
||||
#define PROT_SMPU_V2_MS1_CTL_PRIO_Msk 0x300UL
|
||||
#define PROT_SMPU_V2_MS1_CTL_PC_MASK_0_Pos 16UL
|
||||
#define PROT_SMPU_V2_MS1_CTL_PC_MASK_0_Msk 0x10000UL
|
||||
#define PROT_SMPU_V2_MS1_CTL_PC_MASK_15_TO_1_Pos 17UL
|
||||
#define PROT_SMPU_V2_MS1_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL
|
||||
/* PROT_SMPU.MS2_CTL */
|
||||
#define PROT_SMPU_V2_MS2_CTL_P_Pos 0UL
|
||||
#define PROT_SMPU_V2_MS2_CTL_P_Msk 0x1UL
|
||||
#define PROT_SMPU_V2_MS2_CTL_NS_Pos 1UL
|
||||
#define PROT_SMPU_V2_MS2_CTL_NS_Msk 0x2UL
|
||||
#define PROT_SMPU_V2_MS2_CTL_PRIO_Pos 8UL
|
||||
#define PROT_SMPU_V2_MS2_CTL_PRIO_Msk 0x300UL
|
||||
#define PROT_SMPU_V2_MS2_CTL_PC_MASK_0_Pos 16UL
|
||||
#define PROT_SMPU_V2_MS2_CTL_PC_MASK_0_Msk 0x10000UL
|
||||
#define PROT_SMPU_V2_MS2_CTL_PC_MASK_15_TO_1_Pos 17UL
|
||||
#define PROT_SMPU_V2_MS2_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL
|
||||
/* PROT_SMPU.MS3_CTL */
|
||||
#define PROT_SMPU_V2_MS3_CTL_P_Pos 0UL
|
||||
#define PROT_SMPU_V2_MS3_CTL_P_Msk 0x1UL
|
||||
#define PROT_SMPU_V2_MS3_CTL_NS_Pos 1UL
|
||||
#define PROT_SMPU_V2_MS3_CTL_NS_Msk 0x2UL
|
||||
#define PROT_SMPU_V2_MS3_CTL_PRIO_Pos 8UL
|
||||
#define PROT_SMPU_V2_MS3_CTL_PRIO_Msk 0x300UL
|
||||
#define PROT_SMPU_V2_MS3_CTL_PC_MASK_0_Pos 16UL
|
||||
#define PROT_SMPU_V2_MS3_CTL_PC_MASK_0_Msk 0x10000UL
|
||||
#define PROT_SMPU_V2_MS3_CTL_PC_MASK_15_TO_1_Pos 17UL
|
||||
#define PROT_SMPU_V2_MS3_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL
|
||||
/* PROT_SMPU.MS4_CTL */
|
||||
#define PROT_SMPU_V2_MS4_CTL_P_Pos 0UL
|
||||
#define PROT_SMPU_V2_MS4_CTL_P_Msk 0x1UL
|
||||
#define PROT_SMPU_V2_MS4_CTL_NS_Pos 1UL
|
||||
#define PROT_SMPU_V2_MS4_CTL_NS_Msk 0x2UL
|
||||
#define PROT_SMPU_V2_MS4_CTL_PRIO_Pos 8UL
|
||||
#define PROT_SMPU_V2_MS4_CTL_PRIO_Msk 0x300UL
|
||||
#define PROT_SMPU_V2_MS4_CTL_PC_MASK_0_Pos 16UL
|
||||
#define PROT_SMPU_V2_MS4_CTL_PC_MASK_0_Msk 0x10000UL
|
||||
#define PROT_SMPU_V2_MS4_CTL_PC_MASK_15_TO_1_Pos 17UL
|
||||
#define PROT_SMPU_V2_MS4_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL
|
||||
/* PROT_SMPU.MS5_CTL */
|
||||
#define PROT_SMPU_V2_MS5_CTL_P_Pos 0UL
|
||||
#define PROT_SMPU_V2_MS5_CTL_P_Msk 0x1UL
|
||||
#define PROT_SMPU_V2_MS5_CTL_NS_Pos 1UL
|
||||
#define PROT_SMPU_V2_MS5_CTL_NS_Msk 0x2UL
|
||||
#define PROT_SMPU_V2_MS5_CTL_PRIO_Pos 8UL
|
||||
#define PROT_SMPU_V2_MS5_CTL_PRIO_Msk 0x300UL
|
||||
#define PROT_SMPU_V2_MS5_CTL_PC_MASK_0_Pos 16UL
|
||||
#define PROT_SMPU_V2_MS5_CTL_PC_MASK_0_Msk 0x10000UL
|
||||
#define PROT_SMPU_V2_MS5_CTL_PC_MASK_15_TO_1_Pos 17UL
|
||||
#define PROT_SMPU_V2_MS5_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL
|
||||
/* PROT_SMPU.MS6_CTL */
|
||||
#define PROT_SMPU_V2_MS6_CTL_P_Pos 0UL
|
||||
#define PROT_SMPU_V2_MS6_CTL_P_Msk 0x1UL
|
||||
#define PROT_SMPU_V2_MS6_CTL_NS_Pos 1UL
|
||||
#define PROT_SMPU_V2_MS6_CTL_NS_Msk 0x2UL
|
||||
#define PROT_SMPU_V2_MS6_CTL_PRIO_Pos 8UL
|
||||
#define PROT_SMPU_V2_MS6_CTL_PRIO_Msk 0x300UL
|
||||
#define PROT_SMPU_V2_MS6_CTL_PC_MASK_0_Pos 16UL
|
||||
#define PROT_SMPU_V2_MS6_CTL_PC_MASK_0_Msk 0x10000UL
|
||||
#define PROT_SMPU_V2_MS6_CTL_PC_MASK_15_TO_1_Pos 17UL
|
||||
#define PROT_SMPU_V2_MS6_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL
|
||||
/* PROT_SMPU.MS7_CTL */
|
||||
#define PROT_SMPU_V2_MS7_CTL_P_Pos 0UL
|
||||
#define PROT_SMPU_V2_MS7_CTL_P_Msk 0x1UL
|
||||
#define PROT_SMPU_V2_MS7_CTL_NS_Pos 1UL
|
||||
#define PROT_SMPU_V2_MS7_CTL_NS_Msk 0x2UL
|
||||
#define PROT_SMPU_V2_MS7_CTL_PRIO_Pos 8UL
|
||||
#define PROT_SMPU_V2_MS7_CTL_PRIO_Msk 0x300UL
|
||||
#define PROT_SMPU_V2_MS7_CTL_PC_MASK_0_Pos 16UL
|
||||
#define PROT_SMPU_V2_MS7_CTL_PC_MASK_0_Msk 0x10000UL
|
||||
#define PROT_SMPU_V2_MS7_CTL_PC_MASK_15_TO_1_Pos 17UL
|
||||
#define PROT_SMPU_V2_MS7_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL
|
||||
/* PROT_SMPU.MS8_CTL */
|
||||
#define PROT_SMPU_V2_MS8_CTL_P_Pos 0UL
|
||||
#define PROT_SMPU_V2_MS8_CTL_P_Msk 0x1UL
|
||||
#define PROT_SMPU_V2_MS8_CTL_NS_Pos 1UL
|
||||
#define PROT_SMPU_V2_MS8_CTL_NS_Msk 0x2UL
|
||||
#define PROT_SMPU_V2_MS8_CTL_PRIO_Pos 8UL
|
||||
#define PROT_SMPU_V2_MS8_CTL_PRIO_Msk 0x300UL
|
||||
#define PROT_SMPU_V2_MS8_CTL_PC_MASK_0_Pos 16UL
|
||||
#define PROT_SMPU_V2_MS8_CTL_PC_MASK_0_Msk 0x10000UL
|
||||
#define PROT_SMPU_V2_MS8_CTL_PC_MASK_15_TO_1_Pos 17UL
|
||||
#define PROT_SMPU_V2_MS8_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL
|
||||
/* PROT_SMPU.MS9_CTL */
|
||||
#define PROT_SMPU_V2_MS9_CTL_P_Pos 0UL
|
||||
#define PROT_SMPU_V2_MS9_CTL_P_Msk 0x1UL
|
||||
#define PROT_SMPU_V2_MS9_CTL_NS_Pos 1UL
|
||||
#define PROT_SMPU_V2_MS9_CTL_NS_Msk 0x2UL
|
||||
#define PROT_SMPU_V2_MS9_CTL_PRIO_Pos 8UL
|
||||
#define PROT_SMPU_V2_MS9_CTL_PRIO_Msk 0x300UL
|
||||
#define PROT_SMPU_V2_MS9_CTL_PC_MASK_0_Pos 16UL
|
||||
#define PROT_SMPU_V2_MS9_CTL_PC_MASK_0_Msk 0x10000UL
|
||||
#define PROT_SMPU_V2_MS9_CTL_PC_MASK_15_TO_1_Pos 17UL
|
||||
#define PROT_SMPU_V2_MS9_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL
|
||||
/* PROT_SMPU.MS10_CTL */
|
||||
#define PROT_SMPU_V2_MS10_CTL_P_Pos 0UL
|
||||
#define PROT_SMPU_V2_MS10_CTL_P_Msk 0x1UL
|
||||
#define PROT_SMPU_V2_MS10_CTL_NS_Pos 1UL
|
||||
#define PROT_SMPU_V2_MS10_CTL_NS_Msk 0x2UL
|
||||
#define PROT_SMPU_V2_MS10_CTL_PRIO_Pos 8UL
|
||||
#define PROT_SMPU_V2_MS10_CTL_PRIO_Msk 0x300UL
|
||||
#define PROT_SMPU_V2_MS10_CTL_PC_MASK_0_Pos 16UL
|
||||
#define PROT_SMPU_V2_MS10_CTL_PC_MASK_0_Msk 0x10000UL
|
||||
#define PROT_SMPU_V2_MS10_CTL_PC_MASK_15_TO_1_Pos 17UL
|
||||
#define PROT_SMPU_V2_MS10_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL
|
||||
/* PROT_SMPU.MS11_CTL */
|
||||
#define PROT_SMPU_V2_MS11_CTL_P_Pos 0UL
|
||||
#define PROT_SMPU_V2_MS11_CTL_P_Msk 0x1UL
|
||||
#define PROT_SMPU_V2_MS11_CTL_NS_Pos 1UL
|
||||
#define PROT_SMPU_V2_MS11_CTL_NS_Msk 0x2UL
|
||||
#define PROT_SMPU_V2_MS11_CTL_PRIO_Pos 8UL
|
||||
#define PROT_SMPU_V2_MS11_CTL_PRIO_Msk 0x300UL
|
||||
#define PROT_SMPU_V2_MS11_CTL_PC_MASK_0_Pos 16UL
|
||||
#define PROT_SMPU_V2_MS11_CTL_PC_MASK_0_Msk 0x10000UL
|
||||
#define PROT_SMPU_V2_MS11_CTL_PC_MASK_15_TO_1_Pos 17UL
|
||||
#define PROT_SMPU_V2_MS11_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL
|
||||
/* PROT_SMPU.MS12_CTL */
|
||||
#define PROT_SMPU_V2_MS12_CTL_P_Pos 0UL
|
||||
#define PROT_SMPU_V2_MS12_CTL_P_Msk 0x1UL
|
||||
#define PROT_SMPU_V2_MS12_CTL_NS_Pos 1UL
|
||||
#define PROT_SMPU_V2_MS12_CTL_NS_Msk 0x2UL
|
||||
#define PROT_SMPU_V2_MS12_CTL_PRIO_Pos 8UL
|
||||
#define PROT_SMPU_V2_MS12_CTL_PRIO_Msk 0x300UL
|
||||
#define PROT_SMPU_V2_MS12_CTL_PC_MASK_0_Pos 16UL
|
||||
#define PROT_SMPU_V2_MS12_CTL_PC_MASK_0_Msk 0x10000UL
|
||||
#define PROT_SMPU_V2_MS12_CTL_PC_MASK_15_TO_1_Pos 17UL
|
||||
#define PROT_SMPU_V2_MS12_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL
|
||||
/* PROT_SMPU.MS13_CTL */
|
||||
#define PROT_SMPU_V2_MS13_CTL_P_Pos 0UL
|
||||
#define PROT_SMPU_V2_MS13_CTL_P_Msk 0x1UL
|
||||
#define PROT_SMPU_V2_MS13_CTL_NS_Pos 1UL
|
||||
#define PROT_SMPU_V2_MS13_CTL_NS_Msk 0x2UL
|
||||
#define PROT_SMPU_V2_MS13_CTL_PRIO_Pos 8UL
|
||||
#define PROT_SMPU_V2_MS13_CTL_PRIO_Msk 0x300UL
|
||||
#define PROT_SMPU_V2_MS13_CTL_PC_MASK_0_Pos 16UL
|
||||
#define PROT_SMPU_V2_MS13_CTL_PC_MASK_0_Msk 0x10000UL
|
||||
#define PROT_SMPU_V2_MS13_CTL_PC_MASK_15_TO_1_Pos 17UL
|
||||
#define PROT_SMPU_V2_MS13_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL
|
||||
/* PROT_SMPU.MS14_CTL */
|
||||
#define PROT_SMPU_V2_MS14_CTL_P_Pos 0UL
|
||||
#define PROT_SMPU_V2_MS14_CTL_P_Msk 0x1UL
|
||||
#define PROT_SMPU_V2_MS14_CTL_NS_Pos 1UL
|
||||
#define PROT_SMPU_V2_MS14_CTL_NS_Msk 0x2UL
|
||||
#define PROT_SMPU_V2_MS14_CTL_PRIO_Pos 8UL
|
||||
#define PROT_SMPU_V2_MS14_CTL_PRIO_Msk 0x300UL
|
||||
#define PROT_SMPU_V2_MS14_CTL_PC_MASK_0_Pos 16UL
|
||||
#define PROT_SMPU_V2_MS14_CTL_PC_MASK_0_Msk 0x10000UL
|
||||
#define PROT_SMPU_V2_MS14_CTL_PC_MASK_15_TO_1_Pos 17UL
|
||||
#define PROT_SMPU_V2_MS14_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL
|
||||
/* PROT_SMPU.MS15_CTL */
|
||||
#define PROT_SMPU_V2_MS15_CTL_P_Pos 0UL
|
||||
#define PROT_SMPU_V2_MS15_CTL_P_Msk 0x1UL
|
||||
#define PROT_SMPU_V2_MS15_CTL_NS_Pos 1UL
|
||||
#define PROT_SMPU_V2_MS15_CTL_NS_Msk 0x2UL
|
||||
#define PROT_SMPU_V2_MS15_CTL_PRIO_Pos 8UL
|
||||
#define PROT_SMPU_V2_MS15_CTL_PRIO_Msk 0x300UL
|
||||
#define PROT_SMPU_V2_MS15_CTL_PC_MASK_0_Pos 16UL
|
||||
#define PROT_SMPU_V2_MS15_CTL_PC_MASK_0_Msk 0x10000UL
|
||||
#define PROT_SMPU_V2_MS15_CTL_PC_MASK_15_TO_1_Pos 17UL
|
||||
#define PROT_SMPU_V2_MS15_CTL_PC_MASK_15_TO_1_Msk 0xFFFE0000UL
|
||||
|
||||
|
||||
/* PROT_MPU_MPU_STRUCT.ADDR */
|
||||
#define PROT_MPU_MPU_STRUCT_V2_ADDR_SUBREGION_DISABLE_Pos 0UL
|
||||
#define PROT_MPU_MPU_STRUCT_V2_ADDR_SUBREGION_DISABLE_Msk 0xFFUL
|
||||
#define PROT_MPU_MPU_STRUCT_V2_ADDR_ADDR24_Pos 8UL
|
||||
#define PROT_MPU_MPU_STRUCT_V2_ADDR_ADDR24_Msk 0xFFFFFF00UL
|
||||
/* PROT_MPU_MPU_STRUCT.ATT */
|
||||
#define PROT_MPU_MPU_STRUCT_V2_ATT_UR_Pos 0UL
|
||||
#define PROT_MPU_MPU_STRUCT_V2_ATT_UR_Msk 0x1UL
|
||||
#define PROT_MPU_MPU_STRUCT_V2_ATT_UW_Pos 1UL
|
||||
#define PROT_MPU_MPU_STRUCT_V2_ATT_UW_Msk 0x2UL
|
||||
#define PROT_MPU_MPU_STRUCT_V2_ATT_UX_Pos 2UL
|
||||
#define PROT_MPU_MPU_STRUCT_V2_ATT_UX_Msk 0x4UL
|
||||
#define PROT_MPU_MPU_STRUCT_V2_ATT_PR_Pos 3UL
|
||||
#define PROT_MPU_MPU_STRUCT_V2_ATT_PR_Msk 0x8UL
|
||||
#define PROT_MPU_MPU_STRUCT_V2_ATT_PW_Pos 4UL
|
||||
#define PROT_MPU_MPU_STRUCT_V2_ATT_PW_Msk 0x10UL
|
||||
#define PROT_MPU_MPU_STRUCT_V2_ATT_PX_Pos 5UL
|
||||
#define PROT_MPU_MPU_STRUCT_V2_ATT_PX_Msk 0x20UL
|
||||
#define PROT_MPU_MPU_STRUCT_V2_ATT_NS_Pos 6UL
|
||||
#define PROT_MPU_MPU_STRUCT_V2_ATT_NS_Msk 0x40UL
|
||||
#define PROT_MPU_MPU_STRUCT_V2_ATT_REGION_SIZE_Pos 24UL
|
||||
#define PROT_MPU_MPU_STRUCT_V2_ATT_REGION_SIZE_Msk 0x1F000000UL
|
||||
#define PROT_MPU_MPU_STRUCT_V2_ATT_ENABLED_Pos 31UL
|
||||
#define PROT_MPU_MPU_STRUCT_V2_ATT_ENABLED_Msk 0x80000000UL
|
||||
|
||||
|
||||
/* PROT_MPU.MS_CTL */
|
||||
#define PROT_MPU_V2_MS_CTL_PC_Pos 0UL
|
||||
#define PROT_MPU_V2_MS_CTL_PC_Msk 0xFUL
|
||||
#define PROT_MPU_V2_MS_CTL_PC_SAVED_Pos 16UL
|
||||
#define PROT_MPU_V2_MS_CTL_PC_SAVED_Msk 0xF0000UL
|
||||
|
||||
|
||||
#endif /* _CYIP_PROT_V2_H_ */
|
||||
|
||||
|
||||
/* [] END OF FILE */
|
||||
|
|
@ -1,628 +0,0 @@
|
|||
/***************************************************************************//**
|
||||
* \file cyip_sar.h
|
||||
*
|
||||
* \brief
|
||||
* SAR IP definitions
|
||||
*
|
||||
* \note
|
||||
* Generator version: 1.3.0.1146
|
||||
* Database revision: rev#1050929
|
||||
*
|
||||
********************************************************************************
|
||||
* \copyright
|
||||
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
|
||||
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _CYIP_SAR_H_
|
||||
#define _CYIP_SAR_H_
|
||||
|
||||
#include "cyip_headers.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* SAR
|
||||
*******************************************************************************/
|
||||
|
||||
#define SAR_SECTION_SIZE 0x00010000UL
|
||||
|
||||
/**
|
||||
* \brief SAR ADC with Sequencer (SAR)
|
||||
*/
|
||||
typedef struct {
|
||||
__IOM uint32_t CTRL; /*!< 0x00000000 Analog control register. */
|
||||
__IOM uint32_t SAMPLE_CTRL; /*!< 0x00000004 Sample control register. */
|
||||
__IM uint32_t RESERVED[2];
|
||||
__IOM uint32_t SAMPLE_TIME01; /*!< 0x00000010 Sample time specification ST0 and ST1 */
|
||||
__IOM uint32_t SAMPLE_TIME23; /*!< 0x00000014 Sample time specification ST2 and ST3 */
|
||||
__IOM uint32_t RANGE_THRES; /*!< 0x00000018 Global range detect threshold register. */
|
||||
__IOM uint32_t RANGE_COND; /*!< 0x0000001C Global range detect mode register. */
|
||||
__IOM uint32_t CHAN_EN; /*!< 0x00000020 Enable bits for the channels */
|
||||
__IOM uint32_t START_CTRL; /*!< 0x00000024 Start control register (firmware trigger). */
|
||||
__IM uint32_t RESERVED1[22];
|
||||
__IOM uint32_t CHAN_CONFIG[16]; /*!< 0x00000080 Channel configuration register. */
|
||||
__IM uint32_t RESERVED2[16];
|
||||
__IM uint32_t CHAN_WORK[16]; /*!< 0x00000100 Channel working data register */
|
||||
__IM uint32_t RESERVED3[16];
|
||||
__IM uint32_t CHAN_RESULT[16]; /*!< 0x00000180 Channel result data register */
|
||||
__IM uint32_t RESERVED4[16];
|
||||
__IM uint32_t CHAN_WORK_UPDATED; /*!< 0x00000200 Channel working data register 'updated' bits */
|
||||
__IM uint32_t CHAN_RESULT_UPDATED; /*!< 0x00000204 Channel result data register 'updated' bits */
|
||||
__IM uint32_t CHAN_WORK_NEWVALUE; /*!< 0x00000208 Channel working data register 'new value' bits */
|
||||
__IM uint32_t CHAN_RESULT_NEWVALUE; /*!< 0x0000020C Channel result data register 'new value' bits */
|
||||
__IOM uint32_t INTR; /*!< 0x00000210 Interrupt request register. */
|
||||
__IOM uint32_t INTR_SET; /*!< 0x00000214 Interrupt set request register */
|
||||
__IOM uint32_t INTR_MASK; /*!< 0x00000218 Interrupt mask register. */
|
||||
__IM uint32_t INTR_MASKED; /*!< 0x0000021C Interrupt masked request register */
|
||||
__IOM uint32_t SATURATE_INTR; /*!< 0x00000220 Saturate interrupt request register. */
|
||||
__IOM uint32_t SATURATE_INTR_SET; /*!< 0x00000224 Saturate interrupt set request register */
|
||||
__IOM uint32_t SATURATE_INTR_MASK; /*!< 0x00000228 Saturate interrupt mask register. */
|
||||
__IM uint32_t SATURATE_INTR_MASKED; /*!< 0x0000022C Saturate interrupt masked request register */
|
||||
__IOM uint32_t RANGE_INTR; /*!< 0x00000230 Range detect interrupt request register. */
|
||||
__IOM uint32_t RANGE_INTR_SET; /*!< 0x00000234 Range detect interrupt set request register */
|
||||
__IOM uint32_t RANGE_INTR_MASK; /*!< 0x00000238 Range detect interrupt mask register. */
|
||||
__IM uint32_t RANGE_INTR_MASKED; /*!< 0x0000023C Range interrupt masked request register */
|
||||
__IM uint32_t INTR_CAUSE; /*!< 0x00000240 Interrupt cause register */
|
||||
__IM uint32_t RESERVED5[15];
|
||||
__IOM uint32_t INJ_CHAN_CONFIG; /*!< 0x00000280 Injection channel configuration register. */
|
||||
__IM uint32_t RESERVED6[3];
|
||||
__IM uint32_t INJ_RESULT; /*!< 0x00000290 Injection channel result register */
|
||||
__IM uint32_t RESERVED7[3];
|
||||
__IM uint32_t STATUS; /*!< 0x000002A0 Current status of internal SAR registers (mostly for debug) */
|
||||
__IM uint32_t AVG_STAT; /*!< 0x000002A4 Current averaging status (for debug) */
|
||||
__IM uint32_t RESERVED8[22];
|
||||
__IOM uint32_t MUX_SWITCH0; /*!< 0x00000300 SARMUX Firmware switch controls */
|
||||
__IOM uint32_t MUX_SWITCH_CLEAR0; /*!< 0x00000304 SARMUX Firmware switch control clear */
|
||||
__IM uint32_t RESERVED9[14];
|
||||
__IOM uint32_t MUX_SWITCH_DS_CTRL; /*!< 0x00000340 SARMUX switch DSI control */
|
||||
__IOM uint32_t MUX_SWITCH_SQ_CTRL; /*!< 0x00000344 SARMUX switch Sar Sequencer control */
|
||||
__IM uint32_t MUX_SWITCH_STATUS; /*!< 0x00000348 SARMUX switch status */
|
||||
__IM uint32_t RESERVED10[749];
|
||||
__IOM uint32_t ANA_TRIM0; /*!< 0x00000F00 Analog trim register. */
|
||||
__IOM uint32_t ANA_TRIM1; /*!< 0x00000F04 Analog trim register. */
|
||||
} SAR_V1_Type; /*!< Size = 3848 (0xF08) */
|
||||
|
||||
|
||||
/* SAR.CTRL */
|
||||
#define SAR_CTRL_PWR_CTRL_VREF_Pos 0UL
|
||||
#define SAR_CTRL_PWR_CTRL_VREF_Msk 0x7UL
|
||||
#define SAR_CTRL_VREF_SEL_Pos 4UL
|
||||
#define SAR_CTRL_VREF_SEL_Msk 0x70UL
|
||||
#define SAR_CTRL_VREF_BYP_CAP_EN_Pos 7UL
|
||||
#define SAR_CTRL_VREF_BYP_CAP_EN_Msk 0x80UL
|
||||
#define SAR_CTRL_NEG_SEL_Pos 9UL
|
||||
#define SAR_CTRL_NEG_SEL_Msk 0xE00UL
|
||||
#define SAR_CTRL_SAR_HW_CTRL_NEGVREF_Pos 13UL
|
||||
#define SAR_CTRL_SAR_HW_CTRL_NEGVREF_Msk 0x2000UL
|
||||
#define SAR_CTRL_COMP_DLY_Pos 14UL
|
||||
#define SAR_CTRL_COMP_DLY_Msk 0xC000UL
|
||||
#define SAR_CTRL_SPARE_Pos 16UL
|
||||
#define SAR_CTRL_SPARE_Msk 0xF0000UL
|
||||
#define SAR_CTRL_BOOSTPUMP_EN_Pos 20UL
|
||||
#define SAR_CTRL_BOOSTPUMP_EN_Msk 0x100000UL
|
||||
#define SAR_CTRL_REFBUF_EN_Pos 21UL
|
||||
#define SAR_CTRL_REFBUF_EN_Msk 0x200000UL
|
||||
#define SAR_CTRL_COMP_PWR_Pos 24UL
|
||||
#define SAR_CTRL_COMP_PWR_Msk 0x7000000UL
|
||||
#define SAR_CTRL_DEEPSLEEP_ON_Pos 27UL
|
||||
#define SAR_CTRL_DEEPSLEEP_ON_Msk 0x8000000UL
|
||||
#define SAR_CTRL_DSI_SYNC_CONFIG_Pos 28UL
|
||||
#define SAR_CTRL_DSI_SYNC_CONFIG_Msk 0x10000000UL
|
||||
#define SAR_CTRL_DSI_MODE_Pos 29UL
|
||||
#define SAR_CTRL_DSI_MODE_Msk 0x20000000UL
|
||||
#define SAR_CTRL_SWITCH_DISABLE_Pos 30UL
|
||||
#define SAR_CTRL_SWITCH_DISABLE_Msk 0x40000000UL
|
||||
#define SAR_CTRL_ENABLED_Pos 31UL
|
||||
#define SAR_CTRL_ENABLED_Msk 0x80000000UL
|
||||
/* SAR.SAMPLE_CTRL */
|
||||
#define SAR_SAMPLE_CTRL_LEFT_ALIGN_Pos 1UL
|
||||
#define SAR_SAMPLE_CTRL_LEFT_ALIGN_Msk 0x2UL
|
||||
#define SAR_SAMPLE_CTRL_SINGLE_ENDED_SIGNED_Pos 2UL
|
||||
#define SAR_SAMPLE_CTRL_SINGLE_ENDED_SIGNED_Msk 0x4UL
|
||||
#define SAR_SAMPLE_CTRL_DIFFERENTIAL_SIGNED_Pos 3UL
|
||||
#define SAR_SAMPLE_CTRL_DIFFERENTIAL_SIGNED_Msk 0x8UL
|
||||
#define SAR_SAMPLE_CTRL_AVG_CNT_Pos 4UL
|
||||
#define SAR_SAMPLE_CTRL_AVG_CNT_Msk 0x70UL
|
||||
#define SAR_SAMPLE_CTRL_AVG_SHIFT_Pos 7UL
|
||||
#define SAR_SAMPLE_CTRL_AVG_SHIFT_Msk 0x80UL
|
||||
#define SAR_SAMPLE_CTRL_AVG_MODE_Pos 8UL
|
||||
#define SAR_SAMPLE_CTRL_AVG_MODE_Msk 0x100UL
|
||||
#define SAR_SAMPLE_CTRL_CONTINUOUS_Pos 16UL
|
||||
#define SAR_SAMPLE_CTRL_CONTINUOUS_Msk 0x10000UL
|
||||
#define SAR_SAMPLE_CTRL_DSI_TRIGGER_EN_Pos 17UL
|
||||
#define SAR_SAMPLE_CTRL_DSI_TRIGGER_EN_Msk 0x20000UL
|
||||
#define SAR_SAMPLE_CTRL_DSI_TRIGGER_LEVEL_Pos 18UL
|
||||
#define SAR_SAMPLE_CTRL_DSI_TRIGGER_LEVEL_Msk 0x40000UL
|
||||
#define SAR_SAMPLE_CTRL_DSI_SYNC_TRIGGER_Pos 19UL
|
||||
#define SAR_SAMPLE_CTRL_DSI_SYNC_TRIGGER_Msk 0x80000UL
|
||||
#define SAR_SAMPLE_CTRL_UAB_SCAN_MODE_Pos 22UL
|
||||
#define SAR_SAMPLE_CTRL_UAB_SCAN_MODE_Msk 0x400000UL
|
||||
#define SAR_SAMPLE_CTRL_REPEAT_INVALID_Pos 23UL
|
||||
#define SAR_SAMPLE_CTRL_REPEAT_INVALID_Msk 0x800000UL
|
||||
#define SAR_SAMPLE_CTRL_VALID_SEL_Pos 24UL
|
||||
#define SAR_SAMPLE_CTRL_VALID_SEL_Msk 0x7000000UL
|
||||
#define SAR_SAMPLE_CTRL_VALID_SEL_EN_Pos 27UL
|
||||
#define SAR_SAMPLE_CTRL_VALID_SEL_EN_Msk 0x8000000UL
|
||||
#define SAR_SAMPLE_CTRL_VALID_IGNORE_Pos 28UL
|
||||
#define SAR_SAMPLE_CTRL_VALID_IGNORE_Msk 0x10000000UL
|
||||
#define SAR_SAMPLE_CTRL_TRIGGER_OUT_EN_Pos 30UL
|
||||
#define SAR_SAMPLE_CTRL_TRIGGER_OUT_EN_Msk 0x40000000UL
|
||||
#define SAR_SAMPLE_CTRL_EOS_DSI_OUT_EN_Pos 31UL
|
||||
#define SAR_SAMPLE_CTRL_EOS_DSI_OUT_EN_Msk 0x80000000UL
|
||||
/* SAR.SAMPLE_TIME01 */
|
||||
#define SAR_SAMPLE_TIME01_SAMPLE_TIME0_Pos 0UL
|
||||
#define SAR_SAMPLE_TIME01_SAMPLE_TIME0_Msk 0x3FFUL
|
||||
#define SAR_SAMPLE_TIME01_SAMPLE_TIME1_Pos 16UL
|
||||
#define SAR_SAMPLE_TIME01_SAMPLE_TIME1_Msk 0x3FF0000UL
|
||||
/* SAR.SAMPLE_TIME23 */
|
||||
#define SAR_SAMPLE_TIME23_SAMPLE_TIME2_Pos 0UL
|
||||
#define SAR_SAMPLE_TIME23_SAMPLE_TIME2_Msk 0x3FFUL
|
||||
#define SAR_SAMPLE_TIME23_SAMPLE_TIME3_Pos 16UL
|
||||
#define SAR_SAMPLE_TIME23_SAMPLE_TIME3_Msk 0x3FF0000UL
|
||||
/* SAR.RANGE_THRES */
|
||||
#define SAR_RANGE_THRES_RANGE_LOW_Pos 0UL
|
||||
#define SAR_RANGE_THRES_RANGE_LOW_Msk 0xFFFFUL
|
||||
#define SAR_RANGE_THRES_RANGE_HIGH_Pos 16UL
|
||||
#define SAR_RANGE_THRES_RANGE_HIGH_Msk 0xFFFF0000UL
|
||||
/* SAR.RANGE_COND */
|
||||
#define SAR_RANGE_COND_RANGE_COND_Pos 30UL
|
||||
#define SAR_RANGE_COND_RANGE_COND_Msk 0xC0000000UL
|
||||
/* SAR.CHAN_EN */
|
||||
#define SAR_CHAN_EN_CHAN_EN_Pos 0UL
|
||||
#define SAR_CHAN_EN_CHAN_EN_Msk 0xFFFFUL
|
||||
/* SAR.START_CTRL */
|
||||
#define SAR_START_CTRL_FW_TRIGGER_Pos 0UL
|
||||
#define SAR_START_CTRL_FW_TRIGGER_Msk 0x1UL
|
||||
/* SAR.CHAN_CONFIG */
|
||||
#define SAR_CHAN_CONFIG_POS_PIN_ADDR_Pos 0UL
|
||||
#define SAR_CHAN_CONFIG_POS_PIN_ADDR_Msk 0x7UL
|
||||
#define SAR_CHAN_CONFIG_POS_PORT_ADDR_Pos 4UL
|
||||
#define SAR_CHAN_CONFIG_POS_PORT_ADDR_Msk 0x70UL
|
||||
#define SAR_CHAN_CONFIG_DIFFERENTIAL_EN_Pos 8UL
|
||||
#define SAR_CHAN_CONFIG_DIFFERENTIAL_EN_Msk 0x100UL
|
||||
#define SAR_CHAN_CONFIG_AVG_EN_Pos 10UL
|
||||
#define SAR_CHAN_CONFIG_AVG_EN_Msk 0x400UL
|
||||
#define SAR_CHAN_CONFIG_SAMPLE_TIME_SEL_Pos 12UL
|
||||
#define SAR_CHAN_CONFIG_SAMPLE_TIME_SEL_Msk 0x3000UL
|
||||
#define SAR_CHAN_CONFIG_NEG_PIN_ADDR_Pos 16UL
|
||||
#define SAR_CHAN_CONFIG_NEG_PIN_ADDR_Msk 0x70000UL
|
||||
#define SAR_CHAN_CONFIG_NEG_PORT_ADDR_Pos 20UL
|
||||
#define SAR_CHAN_CONFIG_NEG_PORT_ADDR_Msk 0x700000UL
|
||||
#define SAR_CHAN_CONFIG_NEG_ADDR_EN_Pos 24UL
|
||||
#define SAR_CHAN_CONFIG_NEG_ADDR_EN_Msk 0x1000000UL
|
||||
#define SAR_CHAN_CONFIG_DSI_OUT_EN_Pos 31UL
|
||||
#define SAR_CHAN_CONFIG_DSI_OUT_EN_Msk 0x80000000UL
|
||||
/* SAR.CHAN_WORK */
|
||||
#define SAR_CHAN_WORK_WORK_Pos 0UL
|
||||
#define SAR_CHAN_WORK_WORK_Msk 0xFFFFUL
|
||||
#define SAR_CHAN_WORK_CHAN_WORK_NEWVALUE_MIR_Pos 27UL
|
||||
#define SAR_CHAN_WORK_CHAN_WORK_NEWVALUE_MIR_Msk 0x8000000UL
|
||||
#define SAR_CHAN_WORK_CHAN_WORK_UPDATED_MIR_Pos 31UL
|
||||
#define SAR_CHAN_WORK_CHAN_WORK_UPDATED_MIR_Msk 0x80000000UL
|
||||
/* SAR.CHAN_RESULT */
|
||||
#define SAR_CHAN_RESULT_RESULT_Pos 0UL
|
||||
#define SAR_CHAN_RESULT_RESULT_Msk 0xFFFFUL
|
||||
#define SAR_CHAN_RESULT_CHAN_RESULT_NEWVALUE_MIR_Pos 27UL
|
||||
#define SAR_CHAN_RESULT_CHAN_RESULT_NEWVALUE_MIR_Msk 0x8000000UL
|
||||
#define SAR_CHAN_RESULT_SATURATE_INTR_MIR_Pos 29UL
|
||||
#define SAR_CHAN_RESULT_SATURATE_INTR_MIR_Msk 0x20000000UL
|
||||
#define SAR_CHAN_RESULT_RANGE_INTR_MIR_Pos 30UL
|
||||
#define SAR_CHAN_RESULT_RANGE_INTR_MIR_Msk 0x40000000UL
|
||||
#define SAR_CHAN_RESULT_CHAN_RESULT_UPDATED_MIR_Pos 31UL
|
||||
#define SAR_CHAN_RESULT_CHAN_RESULT_UPDATED_MIR_Msk 0x80000000UL
|
||||
/* SAR.CHAN_WORK_UPDATED */
|
||||
#define SAR_CHAN_WORK_UPDATED_CHAN_WORK_UPDATED_Pos 0UL
|
||||
#define SAR_CHAN_WORK_UPDATED_CHAN_WORK_UPDATED_Msk 0xFFFFUL
|
||||
/* SAR.CHAN_RESULT_UPDATED */
|
||||
#define SAR_CHAN_RESULT_UPDATED_CHAN_RESULT_UPDATED_Pos 0UL
|
||||
#define SAR_CHAN_RESULT_UPDATED_CHAN_RESULT_UPDATED_Msk 0xFFFFUL
|
||||
/* SAR.CHAN_WORK_NEWVALUE */
|
||||
#define SAR_CHAN_WORK_NEWVALUE_CHAN_WORK_NEWVALUE_Pos 0UL
|
||||
#define SAR_CHAN_WORK_NEWVALUE_CHAN_WORK_NEWVALUE_Msk 0xFFFFUL
|
||||
/* SAR.CHAN_RESULT_NEWVALUE */
|
||||
#define SAR_CHAN_RESULT_NEWVALUE_CHAN_RESULT_NEWVALUE_Pos 0UL
|
||||
#define SAR_CHAN_RESULT_NEWVALUE_CHAN_RESULT_NEWVALUE_Msk 0xFFFFUL
|
||||
/* SAR.INTR */
|
||||
#define SAR_INTR_EOS_INTR_Pos 0UL
|
||||
#define SAR_INTR_EOS_INTR_Msk 0x1UL
|
||||
#define SAR_INTR_OVERFLOW_INTR_Pos 1UL
|
||||
#define SAR_INTR_OVERFLOW_INTR_Msk 0x2UL
|
||||
#define SAR_INTR_FW_COLLISION_INTR_Pos 2UL
|
||||
#define SAR_INTR_FW_COLLISION_INTR_Msk 0x4UL
|
||||
#define SAR_INTR_DSI_COLLISION_INTR_Pos 3UL
|
||||
#define SAR_INTR_DSI_COLLISION_INTR_Msk 0x8UL
|
||||
#define SAR_INTR_INJ_EOC_INTR_Pos 4UL
|
||||
#define SAR_INTR_INJ_EOC_INTR_Msk 0x10UL
|
||||
#define SAR_INTR_INJ_SATURATE_INTR_Pos 5UL
|
||||
#define SAR_INTR_INJ_SATURATE_INTR_Msk 0x20UL
|
||||
#define SAR_INTR_INJ_RANGE_INTR_Pos 6UL
|
||||
#define SAR_INTR_INJ_RANGE_INTR_Msk 0x40UL
|
||||
#define SAR_INTR_INJ_COLLISION_INTR_Pos 7UL
|
||||
#define SAR_INTR_INJ_COLLISION_INTR_Msk 0x80UL
|
||||
/* SAR.INTR_SET */
|
||||
#define SAR_INTR_SET_EOS_SET_Pos 0UL
|
||||
#define SAR_INTR_SET_EOS_SET_Msk 0x1UL
|
||||
#define SAR_INTR_SET_OVERFLOW_SET_Pos 1UL
|
||||
#define SAR_INTR_SET_OVERFLOW_SET_Msk 0x2UL
|
||||
#define SAR_INTR_SET_FW_COLLISION_SET_Pos 2UL
|
||||
#define SAR_INTR_SET_FW_COLLISION_SET_Msk 0x4UL
|
||||
#define SAR_INTR_SET_DSI_COLLISION_SET_Pos 3UL
|
||||
#define SAR_INTR_SET_DSI_COLLISION_SET_Msk 0x8UL
|
||||
#define SAR_INTR_SET_INJ_EOC_SET_Pos 4UL
|
||||
#define SAR_INTR_SET_INJ_EOC_SET_Msk 0x10UL
|
||||
#define SAR_INTR_SET_INJ_SATURATE_SET_Pos 5UL
|
||||
#define SAR_INTR_SET_INJ_SATURATE_SET_Msk 0x20UL
|
||||
#define SAR_INTR_SET_INJ_RANGE_SET_Pos 6UL
|
||||
#define SAR_INTR_SET_INJ_RANGE_SET_Msk 0x40UL
|
||||
#define SAR_INTR_SET_INJ_COLLISION_SET_Pos 7UL
|
||||
#define SAR_INTR_SET_INJ_COLLISION_SET_Msk 0x80UL
|
||||
/* SAR.INTR_MASK */
|
||||
#define SAR_INTR_MASK_EOS_MASK_Pos 0UL
|
||||
#define SAR_INTR_MASK_EOS_MASK_Msk 0x1UL
|
||||
#define SAR_INTR_MASK_OVERFLOW_MASK_Pos 1UL
|
||||
#define SAR_INTR_MASK_OVERFLOW_MASK_Msk 0x2UL
|
||||
#define SAR_INTR_MASK_FW_COLLISION_MASK_Pos 2UL
|
||||
#define SAR_INTR_MASK_FW_COLLISION_MASK_Msk 0x4UL
|
||||
#define SAR_INTR_MASK_DSI_COLLISION_MASK_Pos 3UL
|
||||
#define SAR_INTR_MASK_DSI_COLLISION_MASK_Msk 0x8UL
|
||||
#define SAR_INTR_MASK_INJ_EOC_MASK_Pos 4UL
|
||||
#define SAR_INTR_MASK_INJ_EOC_MASK_Msk 0x10UL
|
||||
#define SAR_INTR_MASK_INJ_SATURATE_MASK_Pos 5UL
|
||||
#define SAR_INTR_MASK_INJ_SATURATE_MASK_Msk 0x20UL
|
||||
#define SAR_INTR_MASK_INJ_RANGE_MASK_Pos 6UL
|
||||
#define SAR_INTR_MASK_INJ_RANGE_MASK_Msk 0x40UL
|
||||
#define SAR_INTR_MASK_INJ_COLLISION_MASK_Pos 7UL
|
||||
#define SAR_INTR_MASK_INJ_COLLISION_MASK_Msk 0x80UL
|
||||
/* SAR.INTR_MASKED */
|
||||
#define SAR_INTR_MASKED_EOS_MASKED_Pos 0UL
|
||||
#define SAR_INTR_MASKED_EOS_MASKED_Msk 0x1UL
|
||||
#define SAR_INTR_MASKED_OVERFLOW_MASKED_Pos 1UL
|
||||
#define SAR_INTR_MASKED_OVERFLOW_MASKED_Msk 0x2UL
|
||||
#define SAR_INTR_MASKED_FW_COLLISION_MASKED_Pos 2UL
|
||||
#define SAR_INTR_MASKED_FW_COLLISION_MASKED_Msk 0x4UL
|
||||
#define SAR_INTR_MASKED_DSI_COLLISION_MASKED_Pos 3UL
|
||||
#define SAR_INTR_MASKED_DSI_COLLISION_MASKED_Msk 0x8UL
|
||||
#define SAR_INTR_MASKED_INJ_EOC_MASKED_Pos 4UL
|
||||
#define SAR_INTR_MASKED_INJ_EOC_MASKED_Msk 0x10UL
|
||||
#define SAR_INTR_MASKED_INJ_SATURATE_MASKED_Pos 5UL
|
||||
#define SAR_INTR_MASKED_INJ_SATURATE_MASKED_Msk 0x20UL
|
||||
#define SAR_INTR_MASKED_INJ_RANGE_MASKED_Pos 6UL
|
||||
#define SAR_INTR_MASKED_INJ_RANGE_MASKED_Msk 0x40UL
|
||||
#define SAR_INTR_MASKED_INJ_COLLISION_MASKED_Pos 7UL
|
||||
#define SAR_INTR_MASKED_INJ_COLLISION_MASKED_Msk 0x80UL
|
||||
/* SAR.SATURATE_INTR */
|
||||
#define SAR_SATURATE_INTR_SATURATE_INTR_Pos 0UL
|
||||
#define SAR_SATURATE_INTR_SATURATE_INTR_Msk 0xFFFFUL
|
||||
/* SAR.SATURATE_INTR_SET */
|
||||
#define SAR_SATURATE_INTR_SET_SATURATE_SET_Pos 0UL
|
||||
#define SAR_SATURATE_INTR_SET_SATURATE_SET_Msk 0xFFFFUL
|
||||
/* SAR.SATURATE_INTR_MASK */
|
||||
#define SAR_SATURATE_INTR_MASK_SATURATE_MASK_Pos 0UL
|
||||
#define SAR_SATURATE_INTR_MASK_SATURATE_MASK_Msk 0xFFFFUL
|
||||
/* SAR.SATURATE_INTR_MASKED */
|
||||
#define SAR_SATURATE_INTR_MASKED_SATURATE_MASKED_Pos 0UL
|
||||
#define SAR_SATURATE_INTR_MASKED_SATURATE_MASKED_Msk 0xFFFFUL
|
||||
/* SAR.RANGE_INTR */
|
||||
#define SAR_RANGE_INTR_RANGE_INTR_Pos 0UL
|
||||
#define SAR_RANGE_INTR_RANGE_INTR_Msk 0xFFFFUL
|
||||
/* SAR.RANGE_INTR_SET */
|
||||
#define SAR_RANGE_INTR_SET_RANGE_SET_Pos 0UL
|
||||
#define SAR_RANGE_INTR_SET_RANGE_SET_Msk 0xFFFFUL
|
||||
/* SAR.RANGE_INTR_MASK */
|
||||
#define SAR_RANGE_INTR_MASK_RANGE_MASK_Pos 0UL
|
||||
#define SAR_RANGE_INTR_MASK_RANGE_MASK_Msk 0xFFFFUL
|
||||
/* SAR.RANGE_INTR_MASKED */
|
||||
#define SAR_RANGE_INTR_MASKED_RANGE_MASKED_Pos 0UL
|
||||
#define SAR_RANGE_INTR_MASKED_RANGE_MASKED_Msk 0xFFFFUL
|
||||
/* SAR.INTR_CAUSE */
|
||||
#define SAR_INTR_CAUSE_EOS_MASKED_MIR_Pos 0UL
|
||||
#define SAR_INTR_CAUSE_EOS_MASKED_MIR_Msk 0x1UL
|
||||
#define SAR_INTR_CAUSE_OVERFLOW_MASKED_MIR_Pos 1UL
|
||||
#define SAR_INTR_CAUSE_OVERFLOW_MASKED_MIR_Msk 0x2UL
|
||||
#define SAR_INTR_CAUSE_FW_COLLISION_MASKED_MIR_Pos 2UL
|
||||
#define SAR_INTR_CAUSE_FW_COLLISION_MASKED_MIR_Msk 0x4UL
|
||||
#define SAR_INTR_CAUSE_DSI_COLLISION_MASKED_MIR_Pos 3UL
|
||||
#define SAR_INTR_CAUSE_DSI_COLLISION_MASKED_MIR_Msk 0x8UL
|
||||
#define SAR_INTR_CAUSE_INJ_EOC_MASKED_MIR_Pos 4UL
|
||||
#define SAR_INTR_CAUSE_INJ_EOC_MASKED_MIR_Msk 0x10UL
|
||||
#define SAR_INTR_CAUSE_INJ_SATURATE_MASKED_MIR_Pos 5UL
|
||||
#define SAR_INTR_CAUSE_INJ_SATURATE_MASKED_MIR_Msk 0x20UL
|
||||
#define SAR_INTR_CAUSE_INJ_RANGE_MASKED_MIR_Pos 6UL
|
||||
#define SAR_INTR_CAUSE_INJ_RANGE_MASKED_MIR_Msk 0x40UL
|
||||
#define SAR_INTR_CAUSE_INJ_COLLISION_MASKED_MIR_Pos 7UL
|
||||
#define SAR_INTR_CAUSE_INJ_COLLISION_MASKED_MIR_Msk 0x80UL
|
||||
#define SAR_INTR_CAUSE_SATURATE_MASKED_RED_Pos 30UL
|
||||
#define SAR_INTR_CAUSE_SATURATE_MASKED_RED_Msk 0x40000000UL
|
||||
#define SAR_INTR_CAUSE_RANGE_MASKED_RED_Pos 31UL
|
||||
#define SAR_INTR_CAUSE_RANGE_MASKED_RED_Msk 0x80000000UL
|
||||
/* SAR.INJ_CHAN_CONFIG */
|
||||
#define SAR_INJ_CHAN_CONFIG_INJ_PIN_ADDR_Pos 0UL
|
||||
#define SAR_INJ_CHAN_CONFIG_INJ_PIN_ADDR_Msk 0x7UL
|
||||
#define SAR_INJ_CHAN_CONFIG_INJ_PORT_ADDR_Pos 4UL
|
||||
#define SAR_INJ_CHAN_CONFIG_INJ_PORT_ADDR_Msk 0x70UL
|
||||
#define SAR_INJ_CHAN_CONFIG_INJ_DIFFERENTIAL_EN_Pos 8UL
|
||||
#define SAR_INJ_CHAN_CONFIG_INJ_DIFFERENTIAL_EN_Msk 0x100UL
|
||||
#define SAR_INJ_CHAN_CONFIG_INJ_AVG_EN_Pos 10UL
|
||||
#define SAR_INJ_CHAN_CONFIG_INJ_AVG_EN_Msk 0x400UL
|
||||
#define SAR_INJ_CHAN_CONFIG_INJ_SAMPLE_TIME_SEL_Pos 12UL
|
||||
#define SAR_INJ_CHAN_CONFIG_INJ_SAMPLE_TIME_SEL_Msk 0x3000UL
|
||||
#define SAR_INJ_CHAN_CONFIG_INJ_TAILGATING_Pos 30UL
|
||||
#define SAR_INJ_CHAN_CONFIG_INJ_TAILGATING_Msk 0x40000000UL
|
||||
#define SAR_INJ_CHAN_CONFIG_INJ_START_EN_Pos 31UL
|
||||
#define SAR_INJ_CHAN_CONFIG_INJ_START_EN_Msk 0x80000000UL
|
||||
/* SAR.INJ_RESULT */
|
||||
#define SAR_INJ_RESULT_INJ_RESULT_Pos 0UL
|
||||
#define SAR_INJ_RESULT_INJ_RESULT_Msk 0xFFFFUL
|
||||
#define SAR_INJ_RESULT_INJ_NEWVALUE_Pos 27UL
|
||||
#define SAR_INJ_RESULT_INJ_NEWVALUE_Msk 0x8000000UL
|
||||
#define SAR_INJ_RESULT_INJ_COLLISION_INTR_MIR_Pos 28UL
|
||||
#define SAR_INJ_RESULT_INJ_COLLISION_INTR_MIR_Msk 0x10000000UL
|
||||
#define SAR_INJ_RESULT_INJ_SATURATE_INTR_MIR_Pos 29UL
|
||||
#define SAR_INJ_RESULT_INJ_SATURATE_INTR_MIR_Msk 0x20000000UL
|
||||
#define SAR_INJ_RESULT_INJ_RANGE_INTR_MIR_Pos 30UL
|
||||
#define SAR_INJ_RESULT_INJ_RANGE_INTR_MIR_Msk 0x40000000UL
|
||||
#define SAR_INJ_RESULT_INJ_EOC_INTR_MIR_Pos 31UL
|
||||
#define SAR_INJ_RESULT_INJ_EOC_INTR_MIR_Msk 0x80000000UL
|
||||
/* SAR.STATUS */
|
||||
#define SAR_STATUS_CUR_CHAN_Pos 0UL
|
||||
#define SAR_STATUS_CUR_CHAN_Msk 0x1FUL
|
||||
#define SAR_STATUS_SW_VREF_NEG_Pos 30UL
|
||||
#define SAR_STATUS_SW_VREF_NEG_Msk 0x40000000UL
|
||||
#define SAR_STATUS_BUSY_Pos 31UL
|
||||
#define SAR_STATUS_BUSY_Msk 0x80000000UL
|
||||
/* SAR.AVG_STAT */
|
||||
#define SAR_AVG_STAT_CUR_AVG_ACCU_Pos 0UL
|
||||
#define SAR_AVG_STAT_CUR_AVG_ACCU_Msk 0xFFFFFUL
|
||||
#define SAR_AVG_STAT_INTRLV_BUSY_Pos 23UL
|
||||
#define SAR_AVG_STAT_INTRLV_BUSY_Msk 0x800000UL
|
||||
#define SAR_AVG_STAT_CUR_AVG_CNT_Pos 24UL
|
||||
#define SAR_AVG_STAT_CUR_AVG_CNT_Msk 0xFF000000UL
|
||||
/* SAR.MUX_SWITCH0 */
|
||||
#define SAR_MUX_SWITCH0_MUX_FW_P0_VPLUS_Pos 0UL
|
||||
#define SAR_MUX_SWITCH0_MUX_FW_P0_VPLUS_Msk 0x1UL
|
||||
#define SAR_MUX_SWITCH0_MUX_FW_P1_VPLUS_Pos 1UL
|
||||
#define SAR_MUX_SWITCH0_MUX_FW_P1_VPLUS_Msk 0x2UL
|
||||
#define SAR_MUX_SWITCH0_MUX_FW_P2_VPLUS_Pos 2UL
|
||||
#define SAR_MUX_SWITCH0_MUX_FW_P2_VPLUS_Msk 0x4UL
|
||||
#define SAR_MUX_SWITCH0_MUX_FW_P3_VPLUS_Pos 3UL
|
||||
#define SAR_MUX_SWITCH0_MUX_FW_P3_VPLUS_Msk 0x8UL
|
||||
#define SAR_MUX_SWITCH0_MUX_FW_P4_VPLUS_Pos 4UL
|
||||
#define SAR_MUX_SWITCH0_MUX_FW_P4_VPLUS_Msk 0x10UL
|
||||
#define SAR_MUX_SWITCH0_MUX_FW_P5_VPLUS_Pos 5UL
|
||||
#define SAR_MUX_SWITCH0_MUX_FW_P5_VPLUS_Msk 0x20UL
|
||||
#define SAR_MUX_SWITCH0_MUX_FW_P6_VPLUS_Pos 6UL
|
||||
#define SAR_MUX_SWITCH0_MUX_FW_P6_VPLUS_Msk 0x40UL
|
||||
#define SAR_MUX_SWITCH0_MUX_FW_P7_VPLUS_Pos 7UL
|
||||
#define SAR_MUX_SWITCH0_MUX_FW_P7_VPLUS_Msk 0x80UL
|
||||
#define SAR_MUX_SWITCH0_MUX_FW_P0_VMINUS_Pos 8UL
|
||||
#define SAR_MUX_SWITCH0_MUX_FW_P0_VMINUS_Msk 0x100UL
|
||||
#define SAR_MUX_SWITCH0_MUX_FW_P1_VMINUS_Pos 9UL
|
||||
#define SAR_MUX_SWITCH0_MUX_FW_P1_VMINUS_Msk 0x200UL
|
||||
#define SAR_MUX_SWITCH0_MUX_FW_P2_VMINUS_Pos 10UL
|
||||
#define SAR_MUX_SWITCH0_MUX_FW_P2_VMINUS_Msk 0x400UL
|
||||
#define SAR_MUX_SWITCH0_MUX_FW_P3_VMINUS_Pos 11UL
|
||||
#define SAR_MUX_SWITCH0_MUX_FW_P3_VMINUS_Msk 0x800UL
|
||||
#define SAR_MUX_SWITCH0_MUX_FW_P4_VMINUS_Pos 12UL
|
||||
#define SAR_MUX_SWITCH0_MUX_FW_P4_VMINUS_Msk 0x1000UL
|
||||
#define SAR_MUX_SWITCH0_MUX_FW_P5_VMINUS_Pos 13UL
|
||||
#define SAR_MUX_SWITCH0_MUX_FW_P5_VMINUS_Msk 0x2000UL
|
||||
#define SAR_MUX_SWITCH0_MUX_FW_P6_VMINUS_Pos 14UL
|
||||
#define SAR_MUX_SWITCH0_MUX_FW_P6_VMINUS_Msk 0x4000UL
|
||||
#define SAR_MUX_SWITCH0_MUX_FW_P7_VMINUS_Pos 15UL
|
||||
#define SAR_MUX_SWITCH0_MUX_FW_P7_VMINUS_Msk 0x8000UL
|
||||
#define SAR_MUX_SWITCH0_MUX_FW_VSSA_VMINUS_Pos 16UL
|
||||
#define SAR_MUX_SWITCH0_MUX_FW_VSSA_VMINUS_Msk 0x10000UL
|
||||
#define SAR_MUX_SWITCH0_MUX_FW_TEMP_VPLUS_Pos 17UL
|
||||
#define SAR_MUX_SWITCH0_MUX_FW_TEMP_VPLUS_Msk 0x20000UL
|
||||
#define SAR_MUX_SWITCH0_MUX_FW_AMUXBUSA_VPLUS_Pos 18UL
|
||||
#define SAR_MUX_SWITCH0_MUX_FW_AMUXBUSA_VPLUS_Msk 0x40000UL
|
||||
#define SAR_MUX_SWITCH0_MUX_FW_AMUXBUSB_VPLUS_Pos 19UL
|
||||
#define SAR_MUX_SWITCH0_MUX_FW_AMUXBUSB_VPLUS_Msk 0x80000UL
|
||||
#define SAR_MUX_SWITCH0_MUX_FW_AMUXBUSA_VMINUS_Pos 20UL
|
||||
#define SAR_MUX_SWITCH0_MUX_FW_AMUXBUSA_VMINUS_Msk 0x100000UL
|
||||
#define SAR_MUX_SWITCH0_MUX_FW_AMUXBUSB_VMINUS_Pos 21UL
|
||||
#define SAR_MUX_SWITCH0_MUX_FW_AMUXBUSB_VMINUS_Msk 0x200000UL
|
||||
#define SAR_MUX_SWITCH0_MUX_FW_SARBUS0_VPLUS_Pos 22UL
|
||||
#define SAR_MUX_SWITCH0_MUX_FW_SARBUS0_VPLUS_Msk 0x400000UL
|
||||
#define SAR_MUX_SWITCH0_MUX_FW_SARBUS1_VPLUS_Pos 23UL
|
||||
#define SAR_MUX_SWITCH0_MUX_FW_SARBUS1_VPLUS_Msk 0x800000UL
|
||||
#define SAR_MUX_SWITCH0_MUX_FW_SARBUS0_VMINUS_Pos 24UL
|
||||
#define SAR_MUX_SWITCH0_MUX_FW_SARBUS0_VMINUS_Msk 0x1000000UL
|
||||
#define SAR_MUX_SWITCH0_MUX_FW_SARBUS1_VMINUS_Pos 25UL
|
||||
#define SAR_MUX_SWITCH0_MUX_FW_SARBUS1_VMINUS_Msk 0x2000000UL
|
||||
#define SAR_MUX_SWITCH0_MUX_FW_P4_COREIO0_Pos 26UL
|
||||
#define SAR_MUX_SWITCH0_MUX_FW_P4_COREIO0_Msk 0x4000000UL
|
||||
#define SAR_MUX_SWITCH0_MUX_FW_P5_COREIO1_Pos 27UL
|
||||
#define SAR_MUX_SWITCH0_MUX_FW_P5_COREIO1_Msk 0x8000000UL
|
||||
#define SAR_MUX_SWITCH0_MUX_FW_P6_COREIO2_Pos 28UL
|
||||
#define SAR_MUX_SWITCH0_MUX_FW_P6_COREIO2_Msk 0x10000000UL
|
||||
#define SAR_MUX_SWITCH0_MUX_FW_P7_COREIO3_Pos 29UL
|
||||
#define SAR_MUX_SWITCH0_MUX_FW_P7_COREIO3_Msk 0x20000000UL
|
||||
/* SAR.MUX_SWITCH_CLEAR0 */
|
||||
#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P0_VPLUS_Pos 0UL
|
||||
#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P0_VPLUS_Msk 0x1UL
|
||||
#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P1_VPLUS_Pos 1UL
|
||||
#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P1_VPLUS_Msk 0x2UL
|
||||
#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P2_VPLUS_Pos 2UL
|
||||
#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P2_VPLUS_Msk 0x4UL
|
||||
#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P3_VPLUS_Pos 3UL
|
||||
#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P3_VPLUS_Msk 0x8UL
|
||||
#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P4_VPLUS_Pos 4UL
|
||||
#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P4_VPLUS_Msk 0x10UL
|
||||
#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P5_VPLUS_Pos 5UL
|
||||
#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P5_VPLUS_Msk 0x20UL
|
||||
#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P6_VPLUS_Pos 6UL
|
||||
#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P6_VPLUS_Msk 0x40UL
|
||||
#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P7_VPLUS_Pos 7UL
|
||||
#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P7_VPLUS_Msk 0x80UL
|
||||
#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P0_VMINUS_Pos 8UL
|
||||
#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P0_VMINUS_Msk 0x100UL
|
||||
#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P1_VMINUS_Pos 9UL
|
||||
#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P1_VMINUS_Msk 0x200UL
|
||||
#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P2_VMINUS_Pos 10UL
|
||||
#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P2_VMINUS_Msk 0x400UL
|
||||
#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P3_VMINUS_Pos 11UL
|
||||
#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P3_VMINUS_Msk 0x800UL
|
||||
#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P4_VMINUS_Pos 12UL
|
||||
#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P4_VMINUS_Msk 0x1000UL
|
||||
#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P5_VMINUS_Pos 13UL
|
||||
#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P5_VMINUS_Msk 0x2000UL
|
||||
#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P6_VMINUS_Pos 14UL
|
||||
#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P6_VMINUS_Msk 0x4000UL
|
||||
#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P7_VMINUS_Pos 15UL
|
||||
#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P7_VMINUS_Msk 0x8000UL
|
||||
#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_VSSA_VMINUS_Pos 16UL
|
||||
#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_VSSA_VMINUS_Msk 0x10000UL
|
||||
#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_TEMP_VPLUS_Pos 17UL
|
||||
#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_TEMP_VPLUS_Msk 0x20000UL
|
||||
#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_AMUXBUSA_VPLUS_Pos 18UL
|
||||
#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_AMUXBUSA_VPLUS_Msk 0x40000UL
|
||||
#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_AMUXBUSB_VPLUS_Pos 19UL
|
||||
#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_AMUXBUSB_VPLUS_Msk 0x80000UL
|
||||
#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_AMUXBUSA_VMINUS_Pos 20UL
|
||||
#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_AMUXBUSA_VMINUS_Msk 0x100000UL
|
||||
#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_AMUXBUSB_VMINUS_Pos 21UL
|
||||
#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_AMUXBUSB_VMINUS_Msk 0x200000UL
|
||||
#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_SARBUS0_VPLUS_Pos 22UL
|
||||
#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_SARBUS0_VPLUS_Msk 0x400000UL
|
||||
#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_SARBUS1_VPLUS_Pos 23UL
|
||||
#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_SARBUS1_VPLUS_Msk 0x800000UL
|
||||
#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_SARBUS0_VMINUS_Pos 24UL
|
||||
#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_SARBUS0_VMINUS_Msk 0x1000000UL
|
||||
#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_SARBUS1_VMINUS_Pos 25UL
|
||||
#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_SARBUS1_VMINUS_Msk 0x2000000UL
|
||||
#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P4_COREIO0_Pos 26UL
|
||||
#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P4_COREIO0_Msk 0x4000000UL
|
||||
#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P5_COREIO1_Pos 27UL
|
||||
#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P5_COREIO1_Msk 0x8000000UL
|
||||
#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P6_COREIO2_Pos 28UL
|
||||
#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P6_COREIO2_Msk 0x10000000UL
|
||||
#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P7_COREIO3_Pos 29UL
|
||||
#define SAR_MUX_SWITCH_CLEAR0_MUX_FW_P7_COREIO3_Msk 0x20000000UL
|
||||
/* SAR.MUX_SWITCH_DS_CTRL */
|
||||
#define SAR_MUX_SWITCH_DS_CTRL_MUX_DS_CTRL_P0_Pos 0UL
|
||||
#define SAR_MUX_SWITCH_DS_CTRL_MUX_DS_CTRL_P0_Msk 0x1UL
|
||||
#define SAR_MUX_SWITCH_DS_CTRL_MUX_DS_CTRL_P1_Pos 1UL
|
||||
#define SAR_MUX_SWITCH_DS_CTRL_MUX_DS_CTRL_P1_Msk 0x2UL
|
||||
#define SAR_MUX_SWITCH_DS_CTRL_MUX_DS_CTRL_P2_Pos 2UL
|
||||
#define SAR_MUX_SWITCH_DS_CTRL_MUX_DS_CTRL_P2_Msk 0x4UL
|
||||
#define SAR_MUX_SWITCH_DS_CTRL_MUX_DS_CTRL_P3_Pos 3UL
|
||||
#define SAR_MUX_SWITCH_DS_CTRL_MUX_DS_CTRL_P3_Msk 0x8UL
|
||||
#define SAR_MUX_SWITCH_DS_CTRL_MUX_DS_CTRL_P4_Pos 4UL
|
||||
#define SAR_MUX_SWITCH_DS_CTRL_MUX_DS_CTRL_P4_Msk 0x10UL
|
||||
#define SAR_MUX_SWITCH_DS_CTRL_MUX_DS_CTRL_P5_Pos 5UL
|
||||
#define SAR_MUX_SWITCH_DS_CTRL_MUX_DS_CTRL_P5_Msk 0x20UL
|
||||
#define SAR_MUX_SWITCH_DS_CTRL_MUX_DS_CTRL_P6_Pos 6UL
|
||||
#define SAR_MUX_SWITCH_DS_CTRL_MUX_DS_CTRL_P6_Msk 0x40UL
|
||||
#define SAR_MUX_SWITCH_DS_CTRL_MUX_DS_CTRL_P7_Pos 7UL
|
||||
#define SAR_MUX_SWITCH_DS_CTRL_MUX_DS_CTRL_P7_Msk 0x80UL
|
||||
#define SAR_MUX_SWITCH_DS_CTRL_MUX_DS_CTRL_VSSA_Pos 16UL
|
||||
#define SAR_MUX_SWITCH_DS_CTRL_MUX_DS_CTRL_VSSA_Msk 0x10000UL
|
||||
#define SAR_MUX_SWITCH_DS_CTRL_MUX_DS_CTRL_TEMP_Pos 17UL
|
||||
#define SAR_MUX_SWITCH_DS_CTRL_MUX_DS_CTRL_TEMP_Msk 0x20000UL
|
||||
#define SAR_MUX_SWITCH_DS_CTRL_MUX_DS_CTRL_AMUXBUSA_Pos 18UL
|
||||
#define SAR_MUX_SWITCH_DS_CTRL_MUX_DS_CTRL_AMUXBUSA_Msk 0x40000UL
|
||||
#define SAR_MUX_SWITCH_DS_CTRL_MUX_DS_CTRL_AMUXBUSB_Pos 19UL
|
||||
#define SAR_MUX_SWITCH_DS_CTRL_MUX_DS_CTRL_AMUXBUSB_Msk 0x80000UL
|
||||
#define SAR_MUX_SWITCH_DS_CTRL_MUX_DS_CTRL_SARBUS0_Pos 22UL
|
||||
#define SAR_MUX_SWITCH_DS_CTRL_MUX_DS_CTRL_SARBUS0_Msk 0x400000UL
|
||||
#define SAR_MUX_SWITCH_DS_CTRL_MUX_DS_CTRL_SARBUS1_Pos 23UL
|
||||
#define SAR_MUX_SWITCH_DS_CTRL_MUX_DS_CTRL_SARBUS1_Msk 0x800000UL
|
||||
/* SAR.MUX_SWITCH_SQ_CTRL */
|
||||
#define SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P0_Pos 0UL
|
||||
#define SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P0_Msk 0x1UL
|
||||
#define SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P1_Pos 1UL
|
||||
#define SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P1_Msk 0x2UL
|
||||
#define SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P2_Pos 2UL
|
||||
#define SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P2_Msk 0x4UL
|
||||
#define SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P3_Pos 3UL
|
||||
#define SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P3_Msk 0x8UL
|
||||
#define SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P4_Pos 4UL
|
||||
#define SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P4_Msk 0x10UL
|
||||
#define SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P5_Pos 5UL
|
||||
#define SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P5_Msk 0x20UL
|
||||
#define SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P6_Pos 6UL
|
||||
#define SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P6_Msk 0x40UL
|
||||
#define SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P7_Pos 7UL
|
||||
#define SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P7_Msk 0x80UL
|
||||
#define SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_VSSA_Pos 16UL
|
||||
#define SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_VSSA_Msk 0x10000UL
|
||||
#define SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_TEMP_Pos 17UL
|
||||
#define SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_TEMP_Msk 0x20000UL
|
||||
#define SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_AMUXBUSA_Pos 18UL
|
||||
#define SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_AMUXBUSA_Msk 0x40000UL
|
||||
#define SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_AMUXBUSB_Pos 19UL
|
||||
#define SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_AMUXBUSB_Msk 0x80000UL
|
||||
#define SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_SARBUS0_Pos 22UL
|
||||
#define SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_SARBUS0_Msk 0x400000UL
|
||||
#define SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_SARBUS1_Pos 23UL
|
||||
#define SAR_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_SARBUS1_Msk 0x800000UL
|
||||
/* SAR.MUX_SWITCH_STATUS */
|
||||
#define SAR_MUX_SWITCH_STATUS_MUX_FW_P0_VPLUS_Pos 0UL
|
||||
#define SAR_MUX_SWITCH_STATUS_MUX_FW_P0_VPLUS_Msk 0x1UL
|
||||
#define SAR_MUX_SWITCH_STATUS_MUX_FW_P1_VPLUS_Pos 1UL
|
||||
#define SAR_MUX_SWITCH_STATUS_MUX_FW_P1_VPLUS_Msk 0x2UL
|
||||
#define SAR_MUX_SWITCH_STATUS_MUX_FW_P2_VPLUS_Pos 2UL
|
||||
#define SAR_MUX_SWITCH_STATUS_MUX_FW_P2_VPLUS_Msk 0x4UL
|
||||
#define SAR_MUX_SWITCH_STATUS_MUX_FW_P3_VPLUS_Pos 3UL
|
||||
#define SAR_MUX_SWITCH_STATUS_MUX_FW_P3_VPLUS_Msk 0x8UL
|
||||
#define SAR_MUX_SWITCH_STATUS_MUX_FW_P4_VPLUS_Pos 4UL
|
||||
#define SAR_MUX_SWITCH_STATUS_MUX_FW_P4_VPLUS_Msk 0x10UL
|
||||
#define SAR_MUX_SWITCH_STATUS_MUX_FW_P5_VPLUS_Pos 5UL
|
||||
#define SAR_MUX_SWITCH_STATUS_MUX_FW_P5_VPLUS_Msk 0x20UL
|
||||
#define SAR_MUX_SWITCH_STATUS_MUX_FW_P6_VPLUS_Pos 6UL
|
||||
#define SAR_MUX_SWITCH_STATUS_MUX_FW_P6_VPLUS_Msk 0x40UL
|
||||
#define SAR_MUX_SWITCH_STATUS_MUX_FW_P7_VPLUS_Pos 7UL
|
||||
#define SAR_MUX_SWITCH_STATUS_MUX_FW_P7_VPLUS_Msk 0x80UL
|
||||
#define SAR_MUX_SWITCH_STATUS_MUX_FW_P0_VMINUS_Pos 8UL
|
||||
#define SAR_MUX_SWITCH_STATUS_MUX_FW_P0_VMINUS_Msk 0x100UL
|
||||
#define SAR_MUX_SWITCH_STATUS_MUX_FW_P1_VMINUS_Pos 9UL
|
||||
#define SAR_MUX_SWITCH_STATUS_MUX_FW_P1_VMINUS_Msk 0x200UL
|
||||
#define SAR_MUX_SWITCH_STATUS_MUX_FW_P2_VMINUS_Pos 10UL
|
||||
#define SAR_MUX_SWITCH_STATUS_MUX_FW_P2_VMINUS_Msk 0x400UL
|
||||
#define SAR_MUX_SWITCH_STATUS_MUX_FW_P3_VMINUS_Pos 11UL
|
||||
#define SAR_MUX_SWITCH_STATUS_MUX_FW_P3_VMINUS_Msk 0x800UL
|
||||
#define SAR_MUX_SWITCH_STATUS_MUX_FW_P4_VMINUS_Pos 12UL
|
||||
#define SAR_MUX_SWITCH_STATUS_MUX_FW_P4_VMINUS_Msk 0x1000UL
|
||||
#define SAR_MUX_SWITCH_STATUS_MUX_FW_P5_VMINUS_Pos 13UL
|
||||
#define SAR_MUX_SWITCH_STATUS_MUX_FW_P5_VMINUS_Msk 0x2000UL
|
||||
#define SAR_MUX_SWITCH_STATUS_MUX_FW_P6_VMINUS_Pos 14UL
|
||||
#define SAR_MUX_SWITCH_STATUS_MUX_FW_P6_VMINUS_Msk 0x4000UL
|
||||
#define SAR_MUX_SWITCH_STATUS_MUX_FW_P7_VMINUS_Pos 15UL
|
||||
#define SAR_MUX_SWITCH_STATUS_MUX_FW_P7_VMINUS_Msk 0x8000UL
|
||||
#define SAR_MUX_SWITCH_STATUS_MUX_FW_VSSA_VMINUS_Pos 16UL
|
||||
#define SAR_MUX_SWITCH_STATUS_MUX_FW_VSSA_VMINUS_Msk 0x10000UL
|
||||
#define SAR_MUX_SWITCH_STATUS_MUX_FW_TEMP_VPLUS_Pos 17UL
|
||||
#define SAR_MUX_SWITCH_STATUS_MUX_FW_TEMP_VPLUS_Msk 0x20000UL
|
||||
#define SAR_MUX_SWITCH_STATUS_MUX_FW_AMUXBUSA_VPLUS_Pos 18UL
|
||||
#define SAR_MUX_SWITCH_STATUS_MUX_FW_AMUXBUSA_VPLUS_Msk 0x40000UL
|
||||
#define SAR_MUX_SWITCH_STATUS_MUX_FW_AMUXBUSB_VPLUS_Pos 19UL
|
||||
#define SAR_MUX_SWITCH_STATUS_MUX_FW_AMUXBUSB_VPLUS_Msk 0x80000UL
|
||||
#define SAR_MUX_SWITCH_STATUS_MUX_FW_AMUXBUSA_VMINUS_Pos 20UL
|
||||
#define SAR_MUX_SWITCH_STATUS_MUX_FW_AMUXBUSA_VMINUS_Msk 0x100000UL
|
||||
#define SAR_MUX_SWITCH_STATUS_MUX_FW_AMUXBUSB_VMINUS_Pos 21UL
|
||||
#define SAR_MUX_SWITCH_STATUS_MUX_FW_AMUXBUSB_VMINUS_Msk 0x200000UL
|
||||
#define SAR_MUX_SWITCH_STATUS_MUX_FW_SARBUS0_VPLUS_Pos 22UL
|
||||
#define SAR_MUX_SWITCH_STATUS_MUX_FW_SARBUS0_VPLUS_Msk 0x400000UL
|
||||
#define SAR_MUX_SWITCH_STATUS_MUX_FW_SARBUS1_VPLUS_Pos 23UL
|
||||
#define SAR_MUX_SWITCH_STATUS_MUX_FW_SARBUS1_VPLUS_Msk 0x800000UL
|
||||
#define SAR_MUX_SWITCH_STATUS_MUX_FW_SARBUS0_VMINUS_Pos 24UL
|
||||
#define SAR_MUX_SWITCH_STATUS_MUX_FW_SARBUS0_VMINUS_Msk 0x1000000UL
|
||||
#define SAR_MUX_SWITCH_STATUS_MUX_FW_SARBUS1_VMINUS_Pos 25UL
|
||||
#define SAR_MUX_SWITCH_STATUS_MUX_FW_SARBUS1_VMINUS_Msk 0x2000000UL
|
||||
/* SAR.ANA_TRIM0 */
|
||||
#define SAR_ANA_TRIM0_CAP_TRIM_Pos 0UL
|
||||
#define SAR_ANA_TRIM0_CAP_TRIM_Msk 0x1FUL
|
||||
#define SAR_ANA_TRIM0_TRIMUNIT_Pos 5UL
|
||||
#define SAR_ANA_TRIM0_TRIMUNIT_Msk 0x20UL
|
||||
/* SAR.ANA_TRIM1 */
|
||||
#define SAR_ANA_TRIM1_SAR_REF_BUF_TRIM_Pos 0UL
|
||||
#define SAR_ANA_TRIM1_SAR_REF_BUF_TRIM_Msk 0x3FUL
|
||||
|
||||
|
||||
#endif /* _CYIP_SAR_H_ */
|
||||
|
||||
|
||||
/* [] END OF FILE */
|
||||
|
|
@ -1,758 +0,0 @@
|
|||
/***************************************************************************//**
|
||||
* \file cyip_scb.h
|
||||
*
|
||||
* \brief
|
||||
* SCB IP definitions
|
||||
*
|
||||
* \note
|
||||
* Generator version: 1.3.0.1146
|
||||
* Database revision: rev#1050929
|
||||
*
|
||||
********************************************************************************
|
||||
* \copyright
|
||||
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
|
||||
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _CYIP_SCB_H_
|
||||
#define _CYIP_SCB_H_
|
||||
|
||||
#include "cyip_headers.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* SCB
|
||||
*******************************************************************************/
|
||||
|
||||
#define SCB_SECTION_SIZE 0x00010000UL
|
||||
|
||||
/**
|
||||
* \brief Serial Communications Block (SPI/UART/I2C) (CySCB)
|
||||
*/
|
||||
typedef struct {
|
||||
__IOM uint32_t CTRL; /*!< 0x00000000 Generic control */
|
||||
__IM uint32_t STATUS; /*!< 0x00000004 Generic status */
|
||||
__IOM uint32_t CMD_RESP_CTRL; /*!< 0x00000008 Command/response control */
|
||||
__IM uint32_t CMD_RESP_STATUS; /*!< 0x0000000C Command/response status */
|
||||
__IM uint32_t RESERVED[4];
|
||||
__IOM uint32_t SPI_CTRL; /*!< 0x00000020 SPI control */
|
||||
__IM uint32_t SPI_STATUS; /*!< 0x00000024 SPI status */
|
||||
__IM uint32_t RESERVED1[6];
|
||||
__IOM uint32_t UART_CTRL; /*!< 0x00000040 UART control */
|
||||
__IOM uint32_t UART_TX_CTRL; /*!< 0x00000044 UART transmitter control */
|
||||
__IOM uint32_t UART_RX_CTRL; /*!< 0x00000048 UART receiver control */
|
||||
__IM uint32_t UART_RX_STATUS; /*!< 0x0000004C UART receiver status */
|
||||
__IOM uint32_t UART_FLOW_CTRL; /*!< 0x00000050 UART flow control */
|
||||
__IM uint32_t RESERVED2[3];
|
||||
__IOM uint32_t I2C_CTRL; /*!< 0x00000060 I2C control */
|
||||
__IM uint32_t I2C_STATUS; /*!< 0x00000064 I2C status */
|
||||
__IOM uint32_t I2C_M_CMD; /*!< 0x00000068 I2C master command */
|
||||
__IOM uint32_t I2C_S_CMD; /*!< 0x0000006C I2C slave command */
|
||||
__IOM uint32_t I2C_CFG; /*!< 0x00000070 I2C configuration */
|
||||
__IM uint32_t RESERVED3[35];
|
||||
__IOM uint32_t DDFT_CTRL; /*!< 0x00000100 Digital DfT control */
|
||||
__IM uint32_t RESERVED4[63];
|
||||
__IOM uint32_t TX_CTRL; /*!< 0x00000200 Transmitter control */
|
||||
__IOM uint32_t TX_FIFO_CTRL; /*!< 0x00000204 Transmitter FIFO control */
|
||||
__IM uint32_t TX_FIFO_STATUS; /*!< 0x00000208 Transmitter FIFO status */
|
||||
__IM uint32_t RESERVED5[13];
|
||||
__OM uint32_t TX_FIFO_WR; /*!< 0x00000240 Transmitter FIFO write */
|
||||
__IM uint32_t RESERVED6[47];
|
||||
__IOM uint32_t RX_CTRL; /*!< 0x00000300 Receiver control */
|
||||
__IOM uint32_t RX_FIFO_CTRL; /*!< 0x00000304 Receiver FIFO control */
|
||||
__IM uint32_t RX_FIFO_STATUS; /*!< 0x00000308 Receiver FIFO status */
|
||||
__IM uint32_t RESERVED7;
|
||||
__IOM uint32_t RX_MATCH; /*!< 0x00000310 Slave address and mask */
|
||||
__IM uint32_t RESERVED8[11];
|
||||
__IM uint32_t RX_FIFO_RD; /*!< 0x00000340 Receiver FIFO read */
|
||||
__IM uint32_t RX_FIFO_RD_SILENT; /*!< 0x00000344 Receiver FIFO read silent */
|
||||
__IM uint32_t RESERVED9[46];
|
||||
__IOM uint32_t EZ_DATA[512]; /*!< 0x00000400 Memory buffer */
|
||||
__IM uint32_t RESERVED10[128];
|
||||
__IM uint32_t INTR_CAUSE; /*!< 0x00000E00 Active clocked interrupt signal */
|
||||
__IM uint32_t RESERVED11[31];
|
||||
__IOM uint32_t INTR_I2C_EC; /*!< 0x00000E80 Externally clocked I2C interrupt request */
|
||||
__IM uint32_t RESERVED12;
|
||||
__IOM uint32_t INTR_I2C_EC_MASK; /*!< 0x00000E88 Externally clocked I2C interrupt mask */
|
||||
__IM uint32_t INTR_I2C_EC_MASKED; /*!< 0x00000E8C Externally clocked I2C interrupt masked */
|
||||
__IM uint32_t RESERVED13[12];
|
||||
__IOM uint32_t INTR_SPI_EC; /*!< 0x00000EC0 Externally clocked SPI interrupt request */
|
||||
__IM uint32_t RESERVED14;
|
||||
__IOM uint32_t INTR_SPI_EC_MASK; /*!< 0x00000EC8 Externally clocked SPI interrupt mask */
|
||||
__IM uint32_t INTR_SPI_EC_MASKED; /*!< 0x00000ECC Externally clocked SPI interrupt masked */
|
||||
__IM uint32_t RESERVED15[12];
|
||||
__IOM uint32_t INTR_M; /*!< 0x00000F00 Master interrupt request */
|
||||
__IOM uint32_t INTR_M_SET; /*!< 0x00000F04 Master interrupt set request */
|
||||
__IOM uint32_t INTR_M_MASK; /*!< 0x00000F08 Master interrupt mask */
|
||||
__IM uint32_t INTR_M_MASKED; /*!< 0x00000F0C Master interrupt masked request */
|
||||
__IM uint32_t RESERVED16[12];
|
||||
__IOM uint32_t INTR_S; /*!< 0x00000F40 Slave interrupt request */
|
||||
__IOM uint32_t INTR_S_SET; /*!< 0x00000F44 Slave interrupt set request */
|
||||
__IOM uint32_t INTR_S_MASK; /*!< 0x00000F48 Slave interrupt mask */
|
||||
__IM uint32_t INTR_S_MASKED; /*!< 0x00000F4C Slave interrupt masked request */
|
||||
__IM uint32_t RESERVED17[12];
|
||||
__IOM uint32_t INTR_TX; /*!< 0x00000F80 Transmitter interrupt request */
|
||||
__IOM uint32_t INTR_TX_SET; /*!< 0x00000F84 Transmitter interrupt set request */
|
||||
__IOM uint32_t INTR_TX_MASK; /*!< 0x00000F88 Transmitter interrupt mask */
|
||||
__IM uint32_t INTR_TX_MASKED; /*!< 0x00000F8C Transmitter interrupt masked request */
|
||||
__IM uint32_t RESERVED18[12];
|
||||
__IOM uint32_t INTR_RX; /*!< 0x00000FC0 Receiver interrupt request */
|
||||
__IOM uint32_t INTR_RX_SET; /*!< 0x00000FC4 Receiver interrupt set request */
|
||||
__IOM uint32_t INTR_RX_MASK; /*!< 0x00000FC8 Receiver interrupt mask */
|
||||
__IM uint32_t INTR_RX_MASKED; /*!< 0x00000FCC Receiver interrupt masked request */
|
||||
} CySCB_V1_Type; /*!< Size = 4048 (0xFD0) */
|
||||
|
||||
|
||||
/* SCB.CTRL */
|
||||
#define SCB_CTRL_OVS_Pos 0UL
|
||||
#define SCB_CTRL_OVS_Msk 0xFUL
|
||||
#define SCB_CTRL_EC_AM_MODE_Pos 8UL
|
||||
#define SCB_CTRL_EC_AM_MODE_Msk 0x100UL
|
||||
#define SCB_CTRL_EC_OP_MODE_Pos 9UL
|
||||
#define SCB_CTRL_EC_OP_MODE_Msk 0x200UL
|
||||
#define SCB_CTRL_EZ_MODE_Pos 10UL
|
||||
#define SCB_CTRL_EZ_MODE_Msk 0x400UL
|
||||
#define SCB_CTRL_BYTE_MODE_Pos 11UL
|
||||
#define SCB_CTRL_BYTE_MODE_Msk 0x800UL
|
||||
#define SCB_CTRL_CMD_RESP_MODE_Pos 12UL
|
||||
#define SCB_CTRL_CMD_RESP_MODE_Msk 0x1000UL
|
||||
#define SCB_CTRL_ADDR_ACCEPT_Pos 16UL
|
||||
#define SCB_CTRL_ADDR_ACCEPT_Msk 0x10000UL
|
||||
#define SCB_CTRL_BLOCK_Pos 17UL
|
||||
#define SCB_CTRL_BLOCK_Msk 0x20000UL
|
||||
#define SCB_CTRL_MODE_Pos 24UL
|
||||
#define SCB_CTRL_MODE_Msk 0x3000000UL
|
||||
#define SCB_CTRL_ENABLED_Pos 31UL
|
||||
#define SCB_CTRL_ENABLED_Msk 0x80000000UL
|
||||
/* SCB.STATUS */
|
||||
#define SCB_STATUS_EC_BUSY_Pos 0UL
|
||||
#define SCB_STATUS_EC_BUSY_Msk 0x1UL
|
||||
/* SCB.CMD_RESP_CTRL */
|
||||
#define SCB_CMD_RESP_CTRL_BASE_RD_ADDR_Pos 0UL
|
||||
#define SCB_CMD_RESP_CTRL_BASE_RD_ADDR_Msk 0x1FFUL
|
||||
#define SCB_CMD_RESP_CTRL_BASE_WR_ADDR_Pos 16UL
|
||||
#define SCB_CMD_RESP_CTRL_BASE_WR_ADDR_Msk 0x1FF0000UL
|
||||
/* SCB.CMD_RESP_STATUS */
|
||||
#define SCB_CMD_RESP_STATUS_CURR_RD_ADDR_Pos 0UL
|
||||
#define SCB_CMD_RESP_STATUS_CURR_RD_ADDR_Msk 0x1FFUL
|
||||
#define SCB_CMD_RESP_STATUS_CURR_WR_ADDR_Pos 16UL
|
||||
#define SCB_CMD_RESP_STATUS_CURR_WR_ADDR_Msk 0x1FF0000UL
|
||||
#define SCB_CMD_RESP_STATUS_CMD_RESP_EC_BUS_BUSY_Pos 30UL
|
||||
#define SCB_CMD_RESP_STATUS_CMD_RESP_EC_BUS_BUSY_Msk 0x40000000UL
|
||||
#define SCB_CMD_RESP_STATUS_CMD_RESP_EC_BUSY_Pos 31UL
|
||||
#define SCB_CMD_RESP_STATUS_CMD_RESP_EC_BUSY_Msk 0x80000000UL
|
||||
/* SCB.SPI_CTRL */
|
||||
#define SCB_SPI_CTRL_SSEL_CONTINUOUS_Pos 0UL
|
||||
#define SCB_SPI_CTRL_SSEL_CONTINUOUS_Msk 0x1UL
|
||||
#define SCB_SPI_CTRL_SELECT_PRECEDE_Pos 1UL
|
||||
#define SCB_SPI_CTRL_SELECT_PRECEDE_Msk 0x2UL
|
||||
#define SCB_SPI_CTRL_CPHA_Pos 2UL
|
||||
#define SCB_SPI_CTRL_CPHA_Msk 0x4UL
|
||||
#define SCB_SPI_CTRL_CPOL_Pos 3UL
|
||||
#define SCB_SPI_CTRL_CPOL_Msk 0x8UL
|
||||
#define SCB_SPI_CTRL_LATE_MISO_SAMPLE_Pos 4UL
|
||||
#define SCB_SPI_CTRL_LATE_MISO_SAMPLE_Msk 0x10UL
|
||||
#define SCB_SPI_CTRL_SCLK_CONTINUOUS_Pos 5UL
|
||||
#define SCB_SPI_CTRL_SCLK_CONTINUOUS_Msk 0x20UL
|
||||
#define SCB_SPI_CTRL_SSEL_POLARITY0_Pos 8UL
|
||||
#define SCB_SPI_CTRL_SSEL_POLARITY0_Msk 0x100UL
|
||||
#define SCB_SPI_CTRL_SSEL_POLARITY1_Pos 9UL
|
||||
#define SCB_SPI_CTRL_SSEL_POLARITY1_Msk 0x200UL
|
||||
#define SCB_SPI_CTRL_SSEL_POLARITY2_Pos 10UL
|
||||
#define SCB_SPI_CTRL_SSEL_POLARITY2_Msk 0x400UL
|
||||
#define SCB_SPI_CTRL_SSEL_POLARITY3_Pos 11UL
|
||||
#define SCB_SPI_CTRL_SSEL_POLARITY3_Msk 0x800UL
|
||||
#define SCB_SPI_CTRL_LOOPBACK_Pos 16UL
|
||||
#define SCB_SPI_CTRL_LOOPBACK_Msk 0x10000UL
|
||||
#define SCB_SPI_CTRL_MODE_Pos 24UL
|
||||
#define SCB_SPI_CTRL_MODE_Msk 0x3000000UL
|
||||
#define SCB_SPI_CTRL_SSEL_Pos 26UL
|
||||
#define SCB_SPI_CTRL_SSEL_Msk 0xC000000UL
|
||||
#define SCB_SPI_CTRL_MASTER_MODE_Pos 31UL
|
||||
#define SCB_SPI_CTRL_MASTER_MODE_Msk 0x80000000UL
|
||||
/* SCB.SPI_STATUS */
|
||||
#define SCB_SPI_STATUS_BUS_BUSY_Pos 0UL
|
||||
#define SCB_SPI_STATUS_BUS_BUSY_Msk 0x1UL
|
||||
#define SCB_SPI_STATUS_SPI_EC_BUSY_Pos 1UL
|
||||
#define SCB_SPI_STATUS_SPI_EC_BUSY_Msk 0x2UL
|
||||
#define SCB_SPI_STATUS_CURR_EZ_ADDR_Pos 8UL
|
||||
#define SCB_SPI_STATUS_CURR_EZ_ADDR_Msk 0xFF00UL
|
||||
#define SCB_SPI_STATUS_BASE_EZ_ADDR_Pos 16UL
|
||||
#define SCB_SPI_STATUS_BASE_EZ_ADDR_Msk 0xFF0000UL
|
||||
/* SCB.UART_CTRL */
|
||||
#define SCB_UART_CTRL_LOOPBACK_Pos 16UL
|
||||
#define SCB_UART_CTRL_LOOPBACK_Msk 0x10000UL
|
||||
#define SCB_UART_CTRL_MODE_Pos 24UL
|
||||
#define SCB_UART_CTRL_MODE_Msk 0x3000000UL
|
||||
/* SCB.UART_TX_CTRL */
|
||||
#define SCB_UART_TX_CTRL_STOP_BITS_Pos 0UL
|
||||
#define SCB_UART_TX_CTRL_STOP_BITS_Msk 0x7UL
|
||||
#define SCB_UART_TX_CTRL_PARITY_Pos 4UL
|
||||
#define SCB_UART_TX_CTRL_PARITY_Msk 0x10UL
|
||||
#define SCB_UART_TX_CTRL_PARITY_ENABLED_Pos 5UL
|
||||
#define SCB_UART_TX_CTRL_PARITY_ENABLED_Msk 0x20UL
|
||||
#define SCB_UART_TX_CTRL_RETRY_ON_NACK_Pos 8UL
|
||||
#define SCB_UART_TX_CTRL_RETRY_ON_NACK_Msk 0x100UL
|
||||
/* SCB.UART_RX_CTRL */
|
||||
#define SCB_UART_RX_CTRL_STOP_BITS_Pos 0UL
|
||||
#define SCB_UART_RX_CTRL_STOP_BITS_Msk 0x7UL
|
||||
#define SCB_UART_RX_CTRL_PARITY_Pos 4UL
|
||||
#define SCB_UART_RX_CTRL_PARITY_Msk 0x10UL
|
||||
#define SCB_UART_RX_CTRL_PARITY_ENABLED_Pos 5UL
|
||||
#define SCB_UART_RX_CTRL_PARITY_ENABLED_Msk 0x20UL
|
||||
#define SCB_UART_RX_CTRL_POLARITY_Pos 6UL
|
||||
#define SCB_UART_RX_CTRL_POLARITY_Msk 0x40UL
|
||||
#define SCB_UART_RX_CTRL_DROP_ON_PARITY_ERROR_Pos 8UL
|
||||
#define SCB_UART_RX_CTRL_DROP_ON_PARITY_ERROR_Msk 0x100UL
|
||||
#define SCB_UART_RX_CTRL_DROP_ON_FRAME_ERROR_Pos 9UL
|
||||
#define SCB_UART_RX_CTRL_DROP_ON_FRAME_ERROR_Msk 0x200UL
|
||||
#define SCB_UART_RX_CTRL_MP_MODE_Pos 10UL
|
||||
#define SCB_UART_RX_CTRL_MP_MODE_Msk 0x400UL
|
||||
#define SCB_UART_RX_CTRL_LIN_MODE_Pos 12UL
|
||||
#define SCB_UART_RX_CTRL_LIN_MODE_Msk 0x1000UL
|
||||
#define SCB_UART_RX_CTRL_SKIP_START_Pos 13UL
|
||||
#define SCB_UART_RX_CTRL_SKIP_START_Msk 0x2000UL
|
||||
#define SCB_UART_RX_CTRL_BREAK_WIDTH_Pos 16UL
|
||||
#define SCB_UART_RX_CTRL_BREAK_WIDTH_Msk 0xF0000UL
|
||||
/* SCB.UART_RX_STATUS */
|
||||
#define SCB_UART_RX_STATUS_BR_COUNTER_Pos 0UL
|
||||
#define SCB_UART_RX_STATUS_BR_COUNTER_Msk 0xFFFUL
|
||||
/* SCB.UART_FLOW_CTRL */
|
||||
#define SCB_UART_FLOW_CTRL_TRIGGER_LEVEL_Pos 0UL
|
||||
#define SCB_UART_FLOW_CTRL_TRIGGER_LEVEL_Msk 0xFFUL
|
||||
#define SCB_UART_FLOW_CTRL_RTS_POLARITY_Pos 16UL
|
||||
#define SCB_UART_FLOW_CTRL_RTS_POLARITY_Msk 0x10000UL
|
||||
#define SCB_UART_FLOW_CTRL_CTS_POLARITY_Pos 24UL
|
||||
#define SCB_UART_FLOW_CTRL_CTS_POLARITY_Msk 0x1000000UL
|
||||
#define SCB_UART_FLOW_CTRL_CTS_ENABLED_Pos 25UL
|
||||
#define SCB_UART_FLOW_CTRL_CTS_ENABLED_Msk 0x2000000UL
|
||||
/* SCB.I2C_CTRL */
|
||||
#define SCB_I2C_CTRL_HIGH_PHASE_OVS_Pos 0UL
|
||||
#define SCB_I2C_CTRL_HIGH_PHASE_OVS_Msk 0xFUL
|
||||
#define SCB_I2C_CTRL_LOW_PHASE_OVS_Pos 4UL
|
||||
#define SCB_I2C_CTRL_LOW_PHASE_OVS_Msk 0xF0UL
|
||||
#define SCB_I2C_CTRL_M_READY_DATA_ACK_Pos 8UL
|
||||
#define SCB_I2C_CTRL_M_READY_DATA_ACK_Msk 0x100UL
|
||||
#define SCB_I2C_CTRL_M_NOT_READY_DATA_NACK_Pos 9UL
|
||||
#define SCB_I2C_CTRL_M_NOT_READY_DATA_NACK_Msk 0x200UL
|
||||
#define SCB_I2C_CTRL_S_GENERAL_IGNORE_Pos 11UL
|
||||
#define SCB_I2C_CTRL_S_GENERAL_IGNORE_Msk 0x800UL
|
||||
#define SCB_I2C_CTRL_S_READY_ADDR_ACK_Pos 12UL
|
||||
#define SCB_I2C_CTRL_S_READY_ADDR_ACK_Msk 0x1000UL
|
||||
#define SCB_I2C_CTRL_S_READY_DATA_ACK_Pos 13UL
|
||||
#define SCB_I2C_CTRL_S_READY_DATA_ACK_Msk 0x2000UL
|
||||
#define SCB_I2C_CTRL_S_NOT_READY_ADDR_NACK_Pos 14UL
|
||||
#define SCB_I2C_CTRL_S_NOT_READY_ADDR_NACK_Msk 0x4000UL
|
||||
#define SCB_I2C_CTRL_S_NOT_READY_DATA_NACK_Pos 15UL
|
||||
#define SCB_I2C_CTRL_S_NOT_READY_DATA_NACK_Msk 0x8000UL
|
||||
#define SCB_I2C_CTRL_LOOPBACK_Pos 16UL
|
||||
#define SCB_I2C_CTRL_LOOPBACK_Msk 0x10000UL
|
||||
#define SCB_I2C_CTRL_SLAVE_MODE_Pos 30UL
|
||||
#define SCB_I2C_CTRL_SLAVE_MODE_Msk 0x40000000UL
|
||||
#define SCB_I2C_CTRL_MASTER_MODE_Pos 31UL
|
||||
#define SCB_I2C_CTRL_MASTER_MODE_Msk 0x80000000UL
|
||||
/* SCB.I2C_STATUS */
|
||||
#define SCB_I2C_STATUS_BUS_BUSY_Pos 0UL
|
||||
#define SCB_I2C_STATUS_BUS_BUSY_Msk 0x1UL
|
||||
#define SCB_I2C_STATUS_I2C_EC_BUSY_Pos 1UL
|
||||
#define SCB_I2C_STATUS_I2C_EC_BUSY_Msk 0x2UL
|
||||
#define SCB_I2C_STATUS_S_READ_Pos 4UL
|
||||
#define SCB_I2C_STATUS_S_READ_Msk 0x10UL
|
||||
#define SCB_I2C_STATUS_M_READ_Pos 5UL
|
||||
#define SCB_I2C_STATUS_M_READ_Msk 0x20UL
|
||||
#define SCB_I2C_STATUS_CURR_EZ_ADDR_Pos 8UL
|
||||
#define SCB_I2C_STATUS_CURR_EZ_ADDR_Msk 0xFF00UL
|
||||
#define SCB_I2C_STATUS_BASE_EZ_ADDR_Pos 16UL
|
||||
#define SCB_I2C_STATUS_BASE_EZ_ADDR_Msk 0xFF0000UL
|
||||
/* SCB.I2C_M_CMD */
|
||||
#define SCB_I2C_M_CMD_M_START_Pos 0UL
|
||||
#define SCB_I2C_M_CMD_M_START_Msk 0x1UL
|
||||
#define SCB_I2C_M_CMD_M_START_ON_IDLE_Pos 1UL
|
||||
#define SCB_I2C_M_CMD_M_START_ON_IDLE_Msk 0x2UL
|
||||
#define SCB_I2C_M_CMD_M_ACK_Pos 2UL
|
||||
#define SCB_I2C_M_CMD_M_ACK_Msk 0x4UL
|
||||
#define SCB_I2C_M_CMD_M_NACK_Pos 3UL
|
||||
#define SCB_I2C_M_CMD_M_NACK_Msk 0x8UL
|
||||
#define SCB_I2C_M_CMD_M_STOP_Pos 4UL
|
||||
#define SCB_I2C_M_CMD_M_STOP_Msk 0x10UL
|
||||
/* SCB.I2C_S_CMD */
|
||||
#define SCB_I2C_S_CMD_S_ACK_Pos 0UL
|
||||
#define SCB_I2C_S_CMD_S_ACK_Msk 0x1UL
|
||||
#define SCB_I2C_S_CMD_S_NACK_Pos 1UL
|
||||
#define SCB_I2C_S_CMD_S_NACK_Msk 0x2UL
|
||||
/* SCB.I2C_CFG */
|
||||
#define SCB_I2C_CFG_SDA_IN_FILT_TRIM_Pos 0UL
|
||||
#define SCB_I2C_CFG_SDA_IN_FILT_TRIM_Msk 0x3UL
|
||||
#define SCB_I2C_CFG_SDA_IN_FILT_SEL_Pos 4UL
|
||||
#define SCB_I2C_CFG_SDA_IN_FILT_SEL_Msk 0x10UL
|
||||
#define SCB_I2C_CFG_SCL_IN_FILT_TRIM_Pos 8UL
|
||||
#define SCB_I2C_CFG_SCL_IN_FILT_TRIM_Msk 0x300UL
|
||||
#define SCB_I2C_CFG_SCL_IN_FILT_SEL_Pos 12UL
|
||||
#define SCB_I2C_CFG_SCL_IN_FILT_SEL_Msk 0x1000UL
|
||||
#define SCB_I2C_CFG_SDA_OUT_FILT0_TRIM_Pos 16UL
|
||||
#define SCB_I2C_CFG_SDA_OUT_FILT0_TRIM_Msk 0x30000UL
|
||||
#define SCB_I2C_CFG_SDA_OUT_FILT1_TRIM_Pos 18UL
|
||||
#define SCB_I2C_CFG_SDA_OUT_FILT1_TRIM_Msk 0xC0000UL
|
||||
#define SCB_I2C_CFG_SDA_OUT_FILT2_TRIM_Pos 20UL
|
||||
#define SCB_I2C_CFG_SDA_OUT_FILT2_TRIM_Msk 0x300000UL
|
||||
#define SCB_I2C_CFG_SDA_OUT_FILT_SEL_Pos 28UL
|
||||
#define SCB_I2C_CFG_SDA_OUT_FILT_SEL_Msk 0x30000000UL
|
||||
/* SCB.DDFT_CTRL */
|
||||
#define SCB_DDFT_CTRL_DDFT_IN0_SEL_Pos 0UL
|
||||
#define SCB_DDFT_CTRL_DDFT_IN0_SEL_Msk 0x1UL
|
||||
#define SCB_DDFT_CTRL_DDFT_IN1_SEL_Pos 4UL
|
||||
#define SCB_DDFT_CTRL_DDFT_IN1_SEL_Msk 0x10UL
|
||||
#define SCB_DDFT_CTRL_DDFT_OUT0_SEL_Pos 16UL
|
||||
#define SCB_DDFT_CTRL_DDFT_OUT0_SEL_Msk 0x70000UL
|
||||
#define SCB_DDFT_CTRL_DDFT_OUT1_SEL_Pos 20UL
|
||||
#define SCB_DDFT_CTRL_DDFT_OUT1_SEL_Msk 0x700000UL
|
||||
/* SCB.TX_CTRL */
|
||||
#define SCB_TX_CTRL_DATA_WIDTH_Pos 0UL
|
||||
#define SCB_TX_CTRL_DATA_WIDTH_Msk 0xFUL
|
||||
#define SCB_TX_CTRL_MSB_FIRST_Pos 8UL
|
||||
#define SCB_TX_CTRL_MSB_FIRST_Msk 0x100UL
|
||||
#define SCB_TX_CTRL_OPEN_DRAIN_Pos 16UL
|
||||
#define SCB_TX_CTRL_OPEN_DRAIN_Msk 0x10000UL
|
||||
/* SCB.TX_FIFO_CTRL */
|
||||
#define SCB_TX_FIFO_CTRL_TRIGGER_LEVEL_Pos 0UL
|
||||
#define SCB_TX_FIFO_CTRL_TRIGGER_LEVEL_Msk 0xFFUL
|
||||
#define SCB_TX_FIFO_CTRL_CLEAR_Pos 16UL
|
||||
#define SCB_TX_FIFO_CTRL_CLEAR_Msk 0x10000UL
|
||||
#define SCB_TX_FIFO_CTRL_FREEZE_Pos 17UL
|
||||
#define SCB_TX_FIFO_CTRL_FREEZE_Msk 0x20000UL
|
||||
/* SCB.TX_FIFO_STATUS */
|
||||
#define SCB_TX_FIFO_STATUS_USED_Pos 0UL
|
||||
#define SCB_TX_FIFO_STATUS_USED_Msk 0x1FFUL
|
||||
#define SCB_TX_FIFO_STATUS_SR_VALID_Pos 15UL
|
||||
#define SCB_TX_FIFO_STATUS_SR_VALID_Msk 0x8000UL
|
||||
#define SCB_TX_FIFO_STATUS_RD_PTR_Pos 16UL
|
||||
#define SCB_TX_FIFO_STATUS_RD_PTR_Msk 0xFF0000UL
|
||||
#define SCB_TX_FIFO_STATUS_WR_PTR_Pos 24UL
|
||||
#define SCB_TX_FIFO_STATUS_WR_PTR_Msk 0xFF000000UL
|
||||
/* SCB.TX_FIFO_WR */
|
||||
#define SCB_TX_FIFO_WR_DATA_Pos 0UL
|
||||
#define SCB_TX_FIFO_WR_DATA_Msk 0xFFFFUL
|
||||
/* SCB.RX_CTRL */
|
||||
#define SCB_RX_CTRL_DATA_WIDTH_Pos 0UL
|
||||
#define SCB_RX_CTRL_DATA_WIDTH_Msk 0xFUL
|
||||
#define SCB_RX_CTRL_MSB_FIRST_Pos 8UL
|
||||
#define SCB_RX_CTRL_MSB_FIRST_Msk 0x100UL
|
||||
#define SCB_RX_CTRL_MEDIAN_Pos 9UL
|
||||
#define SCB_RX_CTRL_MEDIAN_Msk 0x200UL
|
||||
/* SCB.RX_FIFO_CTRL */
|
||||
#define SCB_RX_FIFO_CTRL_TRIGGER_LEVEL_Pos 0UL
|
||||
#define SCB_RX_FIFO_CTRL_TRIGGER_LEVEL_Msk 0xFFUL
|
||||
#define SCB_RX_FIFO_CTRL_CLEAR_Pos 16UL
|
||||
#define SCB_RX_FIFO_CTRL_CLEAR_Msk 0x10000UL
|
||||
#define SCB_RX_FIFO_CTRL_FREEZE_Pos 17UL
|
||||
#define SCB_RX_FIFO_CTRL_FREEZE_Msk 0x20000UL
|
||||
/* SCB.RX_FIFO_STATUS */
|
||||
#define SCB_RX_FIFO_STATUS_USED_Pos 0UL
|
||||
#define SCB_RX_FIFO_STATUS_USED_Msk 0x1FFUL
|
||||
#define SCB_RX_FIFO_STATUS_SR_VALID_Pos 15UL
|
||||
#define SCB_RX_FIFO_STATUS_SR_VALID_Msk 0x8000UL
|
||||
#define SCB_RX_FIFO_STATUS_RD_PTR_Pos 16UL
|
||||
#define SCB_RX_FIFO_STATUS_RD_PTR_Msk 0xFF0000UL
|
||||
#define SCB_RX_FIFO_STATUS_WR_PTR_Pos 24UL
|
||||
#define SCB_RX_FIFO_STATUS_WR_PTR_Msk 0xFF000000UL
|
||||
/* SCB.RX_MATCH */
|
||||
#define SCB_RX_MATCH_ADDR_Pos 0UL
|
||||
#define SCB_RX_MATCH_ADDR_Msk 0xFFUL
|
||||
#define SCB_RX_MATCH_MASK_Pos 16UL
|
||||
#define SCB_RX_MATCH_MASK_Msk 0xFF0000UL
|
||||
/* SCB.RX_FIFO_RD */
|
||||
#define SCB_RX_FIFO_RD_DATA_Pos 0UL
|
||||
#define SCB_RX_FIFO_RD_DATA_Msk 0xFFFFUL
|
||||
/* SCB.RX_FIFO_RD_SILENT */
|
||||
#define SCB_RX_FIFO_RD_SILENT_DATA_Pos 0UL
|
||||
#define SCB_RX_FIFO_RD_SILENT_DATA_Msk 0xFFFFUL
|
||||
/* SCB.EZ_DATA */
|
||||
#define SCB_EZ_DATA_EZ_DATA_Pos 0UL
|
||||
#define SCB_EZ_DATA_EZ_DATA_Msk 0xFFUL
|
||||
/* SCB.INTR_CAUSE */
|
||||
#define SCB_INTR_CAUSE_M_Pos 0UL
|
||||
#define SCB_INTR_CAUSE_M_Msk 0x1UL
|
||||
#define SCB_INTR_CAUSE_S_Pos 1UL
|
||||
#define SCB_INTR_CAUSE_S_Msk 0x2UL
|
||||
#define SCB_INTR_CAUSE_TX_Pos 2UL
|
||||
#define SCB_INTR_CAUSE_TX_Msk 0x4UL
|
||||
#define SCB_INTR_CAUSE_RX_Pos 3UL
|
||||
#define SCB_INTR_CAUSE_RX_Msk 0x8UL
|
||||
#define SCB_INTR_CAUSE_I2C_EC_Pos 4UL
|
||||
#define SCB_INTR_CAUSE_I2C_EC_Msk 0x10UL
|
||||
#define SCB_INTR_CAUSE_SPI_EC_Pos 5UL
|
||||
#define SCB_INTR_CAUSE_SPI_EC_Msk 0x20UL
|
||||
/* SCB.INTR_I2C_EC */
|
||||
#define SCB_INTR_I2C_EC_WAKE_UP_Pos 0UL
|
||||
#define SCB_INTR_I2C_EC_WAKE_UP_Msk 0x1UL
|
||||
#define SCB_INTR_I2C_EC_EZ_STOP_Pos 1UL
|
||||
#define SCB_INTR_I2C_EC_EZ_STOP_Msk 0x2UL
|
||||
#define SCB_INTR_I2C_EC_EZ_WRITE_STOP_Pos 2UL
|
||||
#define SCB_INTR_I2C_EC_EZ_WRITE_STOP_Msk 0x4UL
|
||||
#define SCB_INTR_I2C_EC_EZ_READ_STOP_Pos 3UL
|
||||
#define SCB_INTR_I2C_EC_EZ_READ_STOP_Msk 0x8UL
|
||||
/* SCB.INTR_I2C_EC_MASK */
|
||||
#define SCB_INTR_I2C_EC_MASK_WAKE_UP_Pos 0UL
|
||||
#define SCB_INTR_I2C_EC_MASK_WAKE_UP_Msk 0x1UL
|
||||
#define SCB_INTR_I2C_EC_MASK_EZ_STOP_Pos 1UL
|
||||
#define SCB_INTR_I2C_EC_MASK_EZ_STOP_Msk 0x2UL
|
||||
#define SCB_INTR_I2C_EC_MASK_EZ_WRITE_STOP_Pos 2UL
|
||||
#define SCB_INTR_I2C_EC_MASK_EZ_WRITE_STOP_Msk 0x4UL
|
||||
#define SCB_INTR_I2C_EC_MASK_EZ_READ_STOP_Pos 3UL
|
||||
#define SCB_INTR_I2C_EC_MASK_EZ_READ_STOP_Msk 0x8UL
|
||||
/* SCB.INTR_I2C_EC_MASKED */
|
||||
#define SCB_INTR_I2C_EC_MASKED_WAKE_UP_Pos 0UL
|
||||
#define SCB_INTR_I2C_EC_MASKED_WAKE_UP_Msk 0x1UL
|
||||
#define SCB_INTR_I2C_EC_MASKED_EZ_STOP_Pos 1UL
|
||||
#define SCB_INTR_I2C_EC_MASKED_EZ_STOP_Msk 0x2UL
|
||||
#define SCB_INTR_I2C_EC_MASKED_EZ_WRITE_STOP_Pos 2UL
|
||||
#define SCB_INTR_I2C_EC_MASKED_EZ_WRITE_STOP_Msk 0x4UL
|
||||
#define SCB_INTR_I2C_EC_MASKED_EZ_READ_STOP_Pos 3UL
|
||||
#define SCB_INTR_I2C_EC_MASKED_EZ_READ_STOP_Msk 0x8UL
|
||||
/* SCB.INTR_SPI_EC */
|
||||
#define SCB_INTR_SPI_EC_WAKE_UP_Pos 0UL
|
||||
#define SCB_INTR_SPI_EC_WAKE_UP_Msk 0x1UL
|
||||
#define SCB_INTR_SPI_EC_EZ_STOP_Pos 1UL
|
||||
#define SCB_INTR_SPI_EC_EZ_STOP_Msk 0x2UL
|
||||
#define SCB_INTR_SPI_EC_EZ_WRITE_STOP_Pos 2UL
|
||||
#define SCB_INTR_SPI_EC_EZ_WRITE_STOP_Msk 0x4UL
|
||||
#define SCB_INTR_SPI_EC_EZ_READ_STOP_Pos 3UL
|
||||
#define SCB_INTR_SPI_EC_EZ_READ_STOP_Msk 0x8UL
|
||||
/* SCB.INTR_SPI_EC_MASK */
|
||||
#define SCB_INTR_SPI_EC_MASK_WAKE_UP_Pos 0UL
|
||||
#define SCB_INTR_SPI_EC_MASK_WAKE_UP_Msk 0x1UL
|
||||
#define SCB_INTR_SPI_EC_MASK_EZ_STOP_Pos 1UL
|
||||
#define SCB_INTR_SPI_EC_MASK_EZ_STOP_Msk 0x2UL
|
||||
#define SCB_INTR_SPI_EC_MASK_EZ_WRITE_STOP_Pos 2UL
|
||||
#define SCB_INTR_SPI_EC_MASK_EZ_WRITE_STOP_Msk 0x4UL
|
||||
#define SCB_INTR_SPI_EC_MASK_EZ_READ_STOP_Pos 3UL
|
||||
#define SCB_INTR_SPI_EC_MASK_EZ_READ_STOP_Msk 0x8UL
|
||||
/* SCB.INTR_SPI_EC_MASKED */
|
||||
#define SCB_INTR_SPI_EC_MASKED_WAKE_UP_Pos 0UL
|
||||
#define SCB_INTR_SPI_EC_MASKED_WAKE_UP_Msk 0x1UL
|
||||
#define SCB_INTR_SPI_EC_MASKED_EZ_STOP_Pos 1UL
|
||||
#define SCB_INTR_SPI_EC_MASKED_EZ_STOP_Msk 0x2UL
|
||||
#define SCB_INTR_SPI_EC_MASKED_EZ_WRITE_STOP_Pos 2UL
|
||||
#define SCB_INTR_SPI_EC_MASKED_EZ_WRITE_STOP_Msk 0x4UL
|
||||
#define SCB_INTR_SPI_EC_MASKED_EZ_READ_STOP_Pos 3UL
|
||||
#define SCB_INTR_SPI_EC_MASKED_EZ_READ_STOP_Msk 0x8UL
|
||||
/* SCB.INTR_M */
|
||||
#define SCB_INTR_M_I2C_ARB_LOST_Pos 0UL
|
||||
#define SCB_INTR_M_I2C_ARB_LOST_Msk 0x1UL
|
||||
#define SCB_INTR_M_I2C_NACK_Pos 1UL
|
||||
#define SCB_INTR_M_I2C_NACK_Msk 0x2UL
|
||||
#define SCB_INTR_M_I2C_ACK_Pos 2UL
|
||||
#define SCB_INTR_M_I2C_ACK_Msk 0x4UL
|
||||
#define SCB_INTR_M_I2C_STOP_Pos 4UL
|
||||
#define SCB_INTR_M_I2C_STOP_Msk 0x10UL
|
||||
#define SCB_INTR_M_I2C_BUS_ERROR_Pos 8UL
|
||||
#define SCB_INTR_M_I2C_BUS_ERROR_Msk 0x100UL
|
||||
#define SCB_INTR_M_SPI_DONE_Pos 9UL
|
||||
#define SCB_INTR_M_SPI_DONE_Msk 0x200UL
|
||||
/* SCB.INTR_M_SET */
|
||||
#define SCB_INTR_M_SET_I2C_ARB_LOST_Pos 0UL
|
||||
#define SCB_INTR_M_SET_I2C_ARB_LOST_Msk 0x1UL
|
||||
#define SCB_INTR_M_SET_I2C_NACK_Pos 1UL
|
||||
#define SCB_INTR_M_SET_I2C_NACK_Msk 0x2UL
|
||||
#define SCB_INTR_M_SET_I2C_ACK_Pos 2UL
|
||||
#define SCB_INTR_M_SET_I2C_ACK_Msk 0x4UL
|
||||
#define SCB_INTR_M_SET_I2C_STOP_Pos 4UL
|
||||
#define SCB_INTR_M_SET_I2C_STOP_Msk 0x10UL
|
||||
#define SCB_INTR_M_SET_I2C_BUS_ERROR_Pos 8UL
|
||||
#define SCB_INTR_M_SET_I2C_BUS_ERROR_Msk 0x100UL
|
||||
#define SCB_INTR_M_SET_SPI_DONE_Pos 9UL
|
||||
#define SCB_INTR_M_SET_SPI_DONE_Msk 0x200UL
|
||||
/* SCB.INTR_M_MASK */
|
||||
#define SCB_INTR_M_MASK_I2C_ARB_LOST_Pos 0UL
|
||||
#define SCB_INTR_M_MASK_I2C_ARB_LOST_Msk 0x1UL
|
||||
#define SCB_INTR_M_MASK_I2C_NACK_Pos 1UL
|
||||
#define SCB_INTR_M_MASK_I2C_NACK_Msk 0x2UL
|
||||
#define SCB_INTR_M_MASK_I2C_ACK_Pos 2UL
|
||||
#define SCB_INTR_M_MASK_I2C_ACK_Msk 0x4UL
|
||||
#define SCB_INTR_M_MASK_I2C_STOP_Pos 4UL
|
||||
#define SCB_INTR_M_MASK_I2C_STOP_Msk 0x10UL
|
||||
#define SCB_INTR_M_MASK_I2C_BUS_ERROR_Pos 8UL
|
||||
#define SCB_INTR_M_MASK_I2C_BUS_ERROR_Msk 0x100UL
|
||||
#define SCB_INTR_M_MASK_SPI_DONE_Pos 9UL
|
||||
#define SCB_INTR_M_MASK_SPI_DONE_Msk 0x200UL
|
||||
/* SCB.INTR_M_MASKED */
|
||||
#define SCB_INTR_M_MASKED_I2C_ARB_LOST_Pos 0UL
|
||||
#define SCB_INTR_M_MASKED_I2C_ARB_LOST_Msk 0x1UL
|
||||
#define SCB_INTR_M_MASKED_I2C_NACK_Pos 1UL
|
||||
#define SCB_INTR_M_MASKED_I2C_NACK_Msk 0x2UL
|
||||
#define SCB_INTR_M_MASKED_I2C_ACK_Pos 2UL
|
||||
#define SCB_INTR_M_MASKED_I2C_ACK_Msk 0x4UL
|
||||
#define SCB_INTR_M_MASKED_I2C_STOP_Pos 4UL
|
||||
#define SCB_INTR_M_MASKED_I2C_STOP_Msk 0x10UL
|
||||
#define SCB_INTR_M_MASKED_I2C_BUS_ERROR_Pos 8UL
|
||||
#define SCB_INTR_M_MASKED_I2C_BUS_ERROR_Msk 0x100UL
|
||||
#define SCB_INTR_M_MASKED_SPI_DONE_Pos 9UL
|
||||
#define SCB_INTR_M_MASKED_SPI_DONE_Msk 0x200UL
|
||||
/* SCB.INTR_S */
|
||||
#define SCB_INTR_S_I2C_ARB_LOST_Pos 0UL
|
||||
#define SCB_INTR_S_I2C_ARB_LOST_Msk 0x1UL
|
||||
#define SCB_INTR_S_I2C_NACK_Pos 1UL
|
||||
#define SCB_INTR_S_I2C_NACK_Msk 0x2UL
|
||||
#define SCB_INTR_S_I2C_ACK_Pos 2UL
|
||||
#define SCB_INTR_S_I2C_ACK_Msk 0x4UL
|
||||
#define SCB_INTR_S_I2C_WRITE_STOP_Pos 3UL
|
||||
#define SCB_INTR_S_I2C_WRITE_STOP_Msk 0x8UL
|
||||
#define SCB_INTR_S_I2C_STOP_Pos 4UL
|
||||
#define SCB_INTR_S_I2C_STOP_Msk 0x10UL
|
||||
#define SCB_INTR_S_I2C_START_Pos 5UL
|
||||
#define SCB_INTR_S_I2C_START_Msk 0x20UL
|
||||
#define SCB_INTR_S_I2C_ADDR_MATCH_Pos 6UL
|
||||
#define SCB_INTR_S_I2C_ADDR_MATCH_Msk 0x40UL
|
||||
#define SCB_INTR_S_I2C_GENERAL_Pos 7UL
|
||||
#define SCB_INTR_S_I2C_GENERAL_Msk 0x80UL
|
||||
#define SCB_INTR_S_I2C_BUS_ERROR_Pos 8UL
|
||||
#define SCB_INTR_S_I2C_BUS_ERROR_Msk 0x100UL
|
||||
#define SCB_INTR_S_SPI_EZ_WRITE_STOP_Pos 9UL
|
||||
#define SCB_INTR_S_SPI_EZ_WRITE_STOP_Msk 0x200UL
|
||||
#define SCB_INTR_S_SPI_EZ_STOP_Pos 10UL
|
||||
#define SCB_INTR_S_SPI_EZ_STOP_Msk 0x400UL
|
||||
#define SCB_INTR_S_SPI_BUS_ERROR_Pos 11UL
|
||||
#define SCB_INTR_S_SPI_BUS_ERROR_Msk 0x800UL
|
||||
/* SCB.INTR_S_SET */
|
||||
#define SCB_INTR_S_SET_I2C_ARB_LOST_Pos 0UL
|
||||
#define SCB_INTR_S_SET_I2C_ARB_LOST_Msk 0x1UL
|
||||
#define SCB_INTR_S_SET_I2C_NACK_Pos 1UL
|
||||
#define SCB_INTR_S_SET_I2C_NACK_Msk 0x2UL
|
||||
#define SCB_INTR_S_SET_I2C_ACK_Pos 2UL
|
||||
#define SCB_INTR_S_SET_I2C_ACK_Msk 0x4UL
|
||||
#define SCB_INTR_S_SET_I2C_WRITE_STOP_Pos 3UL
|
||||
#define SCB_INTR_S_SET_I2C_WRITE_STOP_Msk 0x8UL
|
||||
#define SCB_INTR_S_SET_I2C_STOP_Pos 4UL
|
||||
#define SCB_INTR_S_SET_I2C_STOP_Msk 0x10UL
|
||||
#define SCB_INTR_S_SET_I2C_START_Pos 5UL
|
||||
#define SCB_INTR_S_SET_I2C_START_Msk 0x20UL
|
||||
#define SCB_INTR_S_SET_I2C_ADDR_MATCH_Pos 6UL
|
||||
#define SCB_INTR_S_SET_I2C_ADDR_MATCH_Msk 0x40UL
|
||||
#define SCB_INTR_S_SET_I2C_GENERAL_Pos 7UL
|
||||
#define SCB_INTR_S_SET_I2C_GENERAL_Msk 0x80UL
|
||||
#define SCB_INTR_S_SET_I2C_BUS_ERROR_Pos 8UL
|
||||
#define SCB_INTR_S_SET_I2C_BUS_ERROR_Msk 0x100UL
|
||||
#define SCB_INTR_S_SET_SPI_EZ_WRITE_STOP_Pos 9UL
|
||||
#define SCB_INTR_S_SET_SPI_EZ_WRITE_STOP_Msk 0x200UL
|
||||
#define SCB_INTR_S_SET_SPI_EZ_STOP_Pos 10UL
|
||||
#define SCB_INTR_S_SET_SPI_EZ_STOP_Msk 0x400UL
|
||||
#define SCB_INTR_S_SET_SPI_BUS_ERROR_Pos 11UL
|
||||
#define SCB_INTR_S_SET_SPI_BUS_ERROR_Msk 0x800UL
|
||||
/* SCB.INTR_S_MASK */
|
||||
#define SCB_INTR_S_MASK_I2C_ARB_LOST_Pos 0UL
|
||||
#define SCB_INTR_S_MASK_I2C_ARB_LOST_Msk 0x1UL
|
||||
#define SCB_INTR_S_MASK_I2C_NACK_Pos 1UL
|
||||
#define SCB_INTR_S_MASK_I2C_NACK_Msk 0x2UL
|
||||
#define SCB_INTR_S_MASK_I2C_ACK_Pos 2UL
|
||||
#define SCB_INTR_S_MASK_I2C_ACK_Msk 0x4UL
|
||||
#define SCB_INTR_S_MASK_I2C_WRITE_STOP_Pos 3UL
|
||||
#define SCB_INTR_S_MASK_I2C_WRITE_STOP_Msk 0x8UL
|
||||
#define SCB_INTR_S_MASK_I2C_STOP_Pos 4UL
|
||||
#define SCB_INTR_S_MASK_I2C_STOP_Msk 0x10UL
|
||||
#define SCB_INTR_S_MASK_I2C_START_Pos 5UL
|
||||
#define SCB_INTR_S_MASK_I2C_START_Msk 0x20UL
|
||||
#define SCB_INTR_S_MASK_I2C_ADDR_MATCH_Pos 6UL
|
||||
#define SCB_INTR_S_MASK_I2C_ADDR_MATCH_Msk 0x40UL
|
||||
#define SCB_INTR_S_MASK_I2C_GENERAL_Pos 7UL
|
||||
#define SCB_INTR_S_MASK_I2C_GENERAL_Msk 0x80UL
|
||||
#define SCB_INTR_S_MASK_I2C_BUS_ERROR_Pos 8UL
|
||||
#define SCB_INTR_S_MASK_I2C_BUS_ERROR_Msk 0x100UL
|
||||
#define SCB_INTR_S_MASK_SPI_EZ_WRITE_STOP_Pos 9UL
|
||||
#define SCB_INTR_S_MASK_SPI_EZ_WRITE_STOP_Msk 0x200UL
|
||||
#define SCB_INTR_S_MASK_SPI_EZ_STOP_Pos 10UL
|
||||
#define SCB_INTR_S_MASK_SPI_EZ_STOP_Msk 0x400UL
|
||||
#define SCB_INTR_S_MASK_SPI_BUS_ERROR_Pos 11UL
|
||||
#define SCB_INTR_S_MASK_SPI_BUS_ERROR_Msk 0x800UL
|
||||
/* SCB.INTR_S_MASKED */
|
||||
#define SCB_INTR_S_MASKED_I2C_ARB_LOST_Pos 0UL
|
||||
#define SCB_INTR_S_MASKED_I2C_ARB_LOST_Msk 0x1UL
|
||||
#define SCB_INTR_S_MASKED_I2C_NACK_Pos 1UL
|
||||
#define SCB_INTR_S_MASKED_I2C_NACK_Msk 0x2UL
|
||||
#define SCB_INTR_S_MASKED_I2C_ACK_Pos 2UL
|
||||
#define SCB_INTR_S_MASKED_I2C_ACK_Msk 0x4UL
|
||||
#define SCB_INTR_S_MASKED_I2C_WRITE_STOP_Pos 3UL
|
||||
#define SCB_INTR_S_MASKED_I2C_WRITE_STOP_Msk 0x8UL
|
||||
#define SCB_INTR_S_MASKED_I2C_STOP_Pos 4UL
|
||||
#define SCB_INTR_S_MASKED_I2C_STOP_Msk 0x10UL
|
||||
#define SCB_INTR_S_MASKED_I2C_START_Pos 5UL
|
||||
#define SCB_INTR_S_MASKED_I2C_START_Msk 0x20UL
|
||||
#define SCB_INTR_S_MASKED_I2C_ADDR_MATCH_Pos 6UL
|
||||
#define SCB_INTR_S_MASKED_I2C_ADDR_MATCH_Msk 0x40UL
|
||||
#define SCB_INTR_S_MASKED_I2C_GENERAL_Pos 7UL
|
||||
#define SCB_INTR_S_MASKED_I2C_GENERAL_Msk 0x80UL
|
||||
#define SCB_INTR_S_MASKED_I2C_BUS_ERROR_Pos 8UL
|
||||
#define SCB_INTR_S_MASKED_I2C_BUS_ERROR_Msk 0x100UL
|
||||
#define SCB_INTR_S_MASKED_SPI_EZ_WRITE_STOP_Pos 9UL
|
||||
#define SCB_INTR_S_MASKED_SPI_EZ_WRITE_STOP_Msk 0x200UL
|
||||
#define SCB_INTR_S_MASKED_SPI_EZ_STOP_Pos 10UL
|
||||
#define SCB_INTR_S_MASKED_SPI_EZ_STOP_Msk 0x400UL
|
||||
#define SCB_INTR_S_MASKED_SPI_BUS_ERROR_Pos 11UL
|
||||
#define SCB_INTR_S_MASKED_SPI_BUS_ERROR_Msk 0x800UL
|
||||
/* SCB.INTR_TX */
|
||||
#define SCB_INTR_TX_TRIGGER_Pos 0UL
|
||||
#define SCB_INTR_TX_TRIGGER_Msk 0x1UL
|
||||
#define SCB_INTR_TX_NOT_FULL_Pos 1UL
|
||||
#define SCB_INTR_TX_NOT_FULL_Msk 0x2UL
|
||||
#define SCB_INTR_TX_EMPTY_Pos 4UL
|
||||
#define SCB_INTR_TX_EMPTY_Msk 0x10UL
|
||||
#define SCB_INTR_TX_OVERFLOW_Pos 5UL
|
||||
#define SCB_INTR_TX_OVERFLOW_Msk 0x20UL
|
||||
#define SCB_INTR_TX_UNDERFLOW_Pos 6UL
|
||||
#define SCB_INTR_TX_UNDERFLOW_Msk 0x40UL
|
||||
#define SCB_INTR_TX_BLOCKED_Pos 7UL
|
||||
#define SCB_INTR_TX_BLOCKED_Msk 0x80UL
|
||||
#define SCB_INTR_TX_UART_NACK_Pos 8UL
|
||||
#define SCB_INTR_TX_UART_NACK_Msk 0x100UL
|
||||
#define SCB_INTR_TX_UART_DONE_Pos 9UL
|
||||
#define SCB_INTR_TX_UART_DONE_Msk 0x200UL
|
||||
#define SCB_INTR_TX_UART_ARB_LOST_Pos 10UL
|
||||
#define SCB_INTR_TX_UART_ARB_LOST_Msk 0x400UL
|
||||
/* SCB.INTR_TX_SET */
|
||||
#define SCB_INTR_TX_SET_TRIGGER_Pos 0UL
|
||||
#define SCB_INTR_TX_SET_TRIGGER_Msk 0x1UL
|
||||
#define SCB_INTR_TX_SET_NOT_FULL_Pos 1UL
|
||||
#define SCB_INTR_TX_SET_NOT_FULL_Msk 0x2UL
|
||||
#define SCB_INTR_TX_SET_EMPTY_Pos 4UL
|
||||
#define SCB_INTR_TX_SET_EMPTY_Msk 0x10UL
|
||||
#define SCB_INTR_TX_SET_OVERFLOW_Pos 5UL
|
||||
#define SCB_INTR_TX_SET_OVERFLOW_Msk 0x20UL
|
||||
#define SCB_INTR_TX_SET_UNDERFLOW_Pos 6UL
|
||||
#define SCB_INTR_TX_SET_UNDERFLOW_Msk 0x40UL
|
||||
#define SCB_INTR_TX_SET_BLOCKED_Pos 7UL
|
||||
#define SCB_INTR_TX_SET_BLOCKED_Msk 0x80UL
|
||||
#define SCB_INTR_TX_SET_UART_NACK_Pos 8UL
|
||||
#define SCB_INTR_TX_SET_UART_NACK_Msk 0x100UL
|
||||
#define SCB_INTR_TX_SET_UART_DONE_Pos 9UL
|
||||
#define SCB_INTR_TX_SET_UART_DONE_Msk 0x200UL
|
||||
#define SCB_INTR_TX_SET_UART_ARB_LOST_Pos 10UL
|
||||
#define SCB_INTR_TX_SET_UART_ARB_LOST_Msk 0x400UL
|
||||
/* SCB.INTR_TX_MASK */
|
||||
#define SCB_INTR_TX_MASK_TRIGGER_Pos 0UL
|
||||
#define SCB_INTR_TX_MASK_TRIGGER_Msk 0x1UL
|
||||
#define SCB_INTR_TX_MASK_NOT_FULL_Pos 1UL
|
||||
#define SCB_INTR_TX_MASK_NOT_FULL_Msk 0x2UL
|
||||
#define SCB_INTR_TX_MASK_EMPTY_Pos 4UL
|
||||
#define SCB_INTR_TX_MASK_EMPTY_Msk 0x10UL
|
||||
#define SCB_INTR_TX_MASK_OVERFLOW_Pos 5UL
|
||||
#define SCB_INTR_TX_MASK_OVERFLOW_Msk 0x20UL
|
||||
#define SCB_INTR_TX_MASK_UNDERFLOW_Pos 6UL
|
||||
#define SCB_INTR_TX_MASK_UNDERFLOW_Msk 0x40UL
|
||||
#define SCB_INTR_TX_MASK_BLOCKED_Pos 7UL
|
||||
#define SCB_INTR_TX_MASK_BLOCKED_Msk 0x80UL
|
||||
#define SCB_INTR_TX_MASK_UART_NACK_Pos 8UL
|
||||
#define SCB_INTR_TX_MASK_UART_NACK_Msk 0x100UL
|
||||
#define SCB_INTR_TX_MASK_UART_DONE_Pos 9UL
|
||||
#define SCB_INTR_TX_MASK_UART_DONE_Msk 0x200UL
|
||||
#define SCB_INTR_TX_MASK_UART_ARB_LOST_Pos 10UL
|
||||
#define SCB_INTR_TX_MASK_UART_ARB_LOST_Msk 0x400UL
|
||||
/* SCB.INTR_TX_MASKED */
|
||||
#define SCB_INTR_TX_MASKED_TRIGGER_Pos 0UL
|
||||
#define SCB_INTR_TX_MASKED_TRIGGER_Msk 0x1UL
|
||||
#define SCB_INTR_TX_MASKED_NOT_FULL_Pos 1UL
|
||||
#define SCB_INTR_TX_MASKED_NOT_FULL_Msk 0x2UL
|
||||
#define SCB_INTR_TX_MASKED_EMPTY_Pos 4UL
|
||||
#define SCB_INTR_TX_MASKED_EMPTY_Msk 0x10UL
|
||||
#define SCB_INTR_TX_MASKED_OVERFLOW_Pos 5UL
|
||||
#define SCB_INTR_TX_MASKED_OVERFLOW_Msk 0x20UL
|
||||
#define SCB_INTR_TX_MASKED_UNDERFLOW_Pos 6UL
|
||||
#define SCB_INTR_TX_MASKED_UNDERFLOW_Msk 0x40UL
|
||||
#define SCB_INTR_TX_MASKED_BLOCKED_Pos 7UL
|
||||
#define SCB_INTR_TX_MASKED_BLOCKED_Msk 0x80UL
|
||||
#define SCB_INTR_TX_MASKED_UART_NACK_Pos 8UL
|
||||
#define SCB_INTR_TX_MASKED_UART_NACK_Msk 0x100UL
|
||||
#define SCB_INTR_TX_MASKED_UART_DONE_Pos 9UL
|
||||
#define SCB_INTR_TX_MASKED_UART_DONE_Msk 0x200UL
|
||||
#define SCB_INTR_TX_MASKED_UART_ARB_LOST_Pos 10UL
|
||||
#define SCB_INTR_TX_MASKED_UART_ARB_LOST_Msk 0x400UL
|
||||
/* SCB.INTR_RX */
|
||||
#define SCB_INTR_RX_TRIGGER_Pos 0UL
|
||||
#define SCB_INTR_RX_TRIGGER_Msk 0x1UL
|
||||
#define SCB_INTR_RX_NOT_EMPTY_Pos 2UL
|
||||
#define SCB_INTR_RX_NOT_EMPTY_Msk 0x4UL
|
||||
#define SCB_INTR_RX_FULL_Pos 3UL
|
||||
#define SCB_INTR_RX_FULL_Msk 0x8UL
|
||||
#define SCB_INTR_RX_OVERFLOW_Pos 5UL
|
||||
#define SCB_INTR_RX_OVERFLOW_Msk 0x20UL
|
||||
#define SCB_INTR_RX_UNDERFLOW_Pos 6UL
|
||||
#define SCB_INTR_RX_UNDERFLOW_Msk 0x40UL
|
||||
#define SCB_INTR_RX_BLOCKED_Pos 7UL
|
||||
#define SCB_INTR_RX_BLOCKED_Msk 0x80UL
|
||||
#define SCB_INTR_RX_FRAME_ERROR_Pos 8UL
|
||||
#define SCB_INTR_RX_FRAME_ERROR_Msk 0x100UL
|
||||
#define SCB_INTR_RX_PARITY_ERROR_Pos 9UL
|
||||
#define SCB_INTR_RX_PARITY_ERROR_Msk 0x200UL
|
||||
#define SCB_INTR_RX_BAUD_DETECT_Pos 10UL
|
||||
#define SCB_INTR_RX_BAUD_DETECT_Msk 0x400UL
|
||||
#define SCB_INTR_RX_BREAK_DETECT_Pos 11UL
|
||||
#define SCB_INTR_RX_BREAK_DETECT_Msk 0x800UL
|
||||
/* SCB.INTR_RX_SET */
|
||||
#define SCB_INTR_RX_SET_TRIGGER_Pos 0UL
|
||||
#define SCB_INTR_RX_SET_TRIGGER_Msk 0x1UL
|
||||
#define SCB_INTR_RX_SET_NOT_EMPTY_Pos 2UL
|
||||
#define SCB_INTR_RX_SET_NOT_EMPTY_Msk 0x4UL
|
||||
#define SCB_INTR_RX_SET_FULL_Pos 3UL
|
||||
#define SCB_INTR_RX_SET_FULL_Msk 0x8UL
|
||||
#define SCB_INTR_RX_SET_OVERFLOW_Pos 5UL
|
||||
#define SCB_INTR_RX_SET_OVERFLOW_Msk 0x20UL
|
||||
#define SCB_INTR_RX_SET_UNDERFLOW_Pos 6UL
|
||||
#define SCB_INTR_RX_SET_UNDERFLOW_Msk 0x40UL
|
||||
#define SCB_INTR_RX_SET_BLOCKED_Pos 7UL
|
||||
#define SCB_INTR_RX_SET_BLOCKED_Msk 0x80UL
|
||||
#define SCB_INTR_RX_SET_FRAME_ERROR_Pos 8UL
|
||||
#define SCB_INTR_RX_SET_FRAME_ERROR_Msk 0x100UL
|
||||
#define SCB_INTR_RX_SET_PARITY_ERROR_Pos 9UL
|
||||
#define SCB_INTR_RX_SET_PARITY_ERROR_Msk 0x200UL
|
||||
#define SCB_INTR_RX_SET_BAUD_DETECT_Pos 10UL
|
||||
#define SCB_INTR_RX_SET_BAUD_DETECT_Msk 0x400UL
|
||||
#define SCB_INTR_RX_SET_BREAK_DETECT_Pos 11UL
|
||||
#define SCB_INTR_RX_SET_BREAK_DETECT_Msk 0x800UL
|
||||
/* SCB.INTR_RX_MASK */
|
||||
#define SCB_INTR_RX_MASK_TRIGGER_Pos 0UL
|
||||
#define SCB_INTR_RX_MASK_TRIGGER_Msk 0x1UL
|
||||
#define SCB_INTR_RX_MASK_NOT_EMPTY_Pos 2UL
|
||||
#define SCB_INTR_RX_MASK_NOT_EMPTY_Msk 0x4UL
|
||||
#define SCB_INTR_RX_MASK_FULL_Pos 3UL
|
||||
#define SCB_INTR_RX_MASK_FULL_Msk 0x8UL
|
||||
#define SCB_INTR_RX_MASK_OVERFLOW_Pos 5UL
|
||||
#define SCB_INTR_RX_MASK_OVERFLOW_Msk 0x20UL
|
||||
#define SCB_INTR_RX_MASK_UNDERFLOW_Pos 6UL
|
||||
#define SCB_INTR_RX_MASK_UNDERFLOW_Msk 0x40UL
|
||||
#define SCB_INTR_RX_MASK_BLOCKED_Pos 7UL
|
||||
#define SCB_INTR_RX_MASK_BLOCKED_Msk 0x80UL
|
||||
#define SCB_INTR_RX_MASK_FRAME_ERROR_Pos 8UL
|
||||
#define SCB_INTR_RX_MASK_FRAME_ERROR_Msk 0x100UL
|
||||
#define SCB_INTR_RX_MASK_PARITY_ERROR_Pos 9UL
|
||||
#define SCB_INTR_RX_MASK_PARITY_ERROR_Msk 0x200UL
|
||||
#define SCB_INTR_RX_MASK_BAUD_DETECT_Pos 10UL
|
||||
#define SCB_INTR_RX_MASK_BAUD_DETECT_Msk 0x400UL
|
||||
#define SCB_INTR_RX_MASK_BREAK_DETECT_Pos 11UL
|
||||
#define SCB_INTR_RX_MASK_BREAK_DETECT_Msk 0x800UL
|
||||
/* SCB.INTR_RX_MASKED */
|
||||
#define SCB_INTR_RX_MASKED_TRIGGER_Pos 0UL
|
||||
#define SCB_INTR_RX_MASKED_TRIGGER_Msk 0x1UL
|
||||
#define SCB_INTR_RX_MASKED_NOT_EMPTY_Pos 2UL
|
||||
#define SCB_INTR_RX_MASKED_NOT_EMPTY_Msk 0x4UL
|
||||
#define SCB_INTR_RX_MASKED_FULL_Pos 3UL
|
||||
#define SCB_INTR_RX_MASKED_FULL_Msk 0x8UL
|
||||
#define SCB_INTR_RX_MASKED_OVERFLOW_Pos 5UL
|
||||
#define SCB_INTR_RX_MASKED_OVERFLOW_Msk 0x20UL
|
||||
#define SCB_INTR_RX_MASKED_UNDERFLOW_Pos 6UL
|
||||
#define SCB_INTR_RX_MASKED_UNDERFLOW_Msk 0x40UL
|
||||
#define SCB_INTR_RX_MASKED_BLOCKED_Pos 7UL
|
||||
#define SCB_INTR_RX_MASKED_BLOCKED_Msk 0x80UL
|
||||
#define SCB_INTR_RX_MASKED_FRAME_ERROR_Pos 8UL
|
||||
#define SCB_INTR_RX_MASKED_FRAME_ERROR_Msk 0x100UL
|
||||
#define SCB_INTR_RX_MASKED_PARITY_ERROR_Pos 9UL
|
||||
#define SCB_INTR_RX_MASKED_PARITY_ERROR_Msk 0x200UL
|
||||
#define SCB_INTR_RX_MASKED_BAUD_DETECT_Pos 10UL
|
||||
#define SCB_INTR_RX_MASKED_BAUD_DETECT_Msk 0x400UL
|
||||
#define SCB_INTR_RX_MASKED_BREAK_DETECT_Pos 11UL
|
||||
#define SCB_INTR_RX_MASKED_BREAK_DETECT_Msk 0x800UL
|
||||
|
||||
|
||||
#endif /* _CYIP_SCB_H_ */
|
||||
|
||||
|
||||
/* [] END OF FILE */
|
||||
File diff suppressed because it is too large
Load diff
|
|
@ -1,477 +0,0 @@
|
|||
/***************************************************************************//**
|
||||
* \file cyip_sflash.h
|
||||
*
|
||||
* \brief
|
||||
* SFLASH IP definitions
|
||||
*
|
||||
* \note
|
||||
* Generator version: 1.3.0.1146
|
||||
* Database revision: rev#1050929
|
||||
*
|
||||
********************************************************************************
|
||||
* \copyright
|
||||
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
|
||||
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _CYIP_SFLASH_H_
|
||||
#define _CYIP_SFLASH_H_
|
||||
|
||||
#include "cyip_headers.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* SFLASH
|
||||
*******************************************************************************/
|
||||
|
||||
#define SFLASH_SECTION_SIZE 0x00008000UL
|
||||
|
||||
/**
|
||||
* \brief FLASH Supervisory Region (SFLASH)
|
||||
*/
|
||||
typedef struct {
|
||||
__IM uint8_t RESERVED;
|
||||
__IOM uint8_t SI_REVISION_ID; /*!< 0x00000001 Indicates Silicon Revision ID of the device */
|
||||
__IOM uint16_t SILICON_ID; /*!< 0x00000002 Indicates Silicon ID of the device */
|
||||
__IM uint32_t RESERVED1[2];
|
||||
__IOM uint16_t FAMILY_ID; /*!< 0x0000000C Indicates Family ID of the device */
|
||||
__IM uint16_t RESERVED2[761];
|
||||
__IOM uint8_t DIE_LOT[3]; /*!< 0x00000600 Lot Number (3 bytes) */
|
||||
__IOM uint8_t DIE_WAFER; /*!< 0x00000603 Wafer Number */
|
||||
__IOM uint8_t DIE_X; /*!< 0x00000604 X Position on Wafer, CRI Pass/Fail Bin */
|
||||
__IOM uint8_t DIE_Y; /*!< 0x00000605 Y Position on Wafer, CHI Pass/Fail Bin */
|
||||
__IOM uint8_t DIE_SORT; /*!< 0x00000606 Sort1/2/3 Pass/Fail Bin */
|
||||
__IOM uint8_t DIE_MINOR; /*!< 0x00000607 Minor Revision Number */
|
||||
__IOM uint8_t DIE_DAY; /*!< 0x00000608 Day number */
|
||||
__IOM uint8_t DIE_MONTH; /*!< 0x00000609 Month number */
|
||||
__IOM uint8_t DIE_YEAR; /*!< 0x0000060A Year number */
|
||||
__IM uint8_t RESERVED3[61];
|
||||
__IOM uint16_t SAR_TEMP_MULTIPLIER; /*!< 0x00000648 SAR Temperature Sensor Multiplication Factor */
|
||||
__IOM uint16_t SAR_TEMP_OFFSET; /*!< 0x0000064A SAR Temperature Sensor Offset */
|
||||
__IM uint32_t RESERVED4[8];
|
||||
__IOM uint32_t CSP_PANEL_ID; /*!< 0x0000066C CSP Panel Id to record panel ID of CSP die */
|
||||
__IM uint32_t RESERVED5[52];
|
||||
__IOM uint8_t LDO_0P9V_TRIM; /*!< 0x00000740 LDO_0P9V_TRIM */
|
||||
__IOM uint8_t LDO_1P1V_TRIM; /*!< 0x00000741 LDO_1P1V_TRIM */
|
||||
__IM uint16_t RESERVED6[95];
|
||||
__IOM uint32_t BLE_DEVICE_ADDRESS[128]; /*!< 0x00000800 BLE_DEVICE_ADDRESS */
|
||||
__IOM uint32_t USER_FREE_ROW1[128]; /*!< 0x00000A00 USER_FREE_ROW1 */
|
||||
__IOM uint32_t USER_FREE_ROW2[128]; /*!< 0x00000C00 USER_FREE_ROW2 */
|
||||
__IOM uint32_t USER_FREE_ROW3[128]; /*!< 0x00000E00 USER_FREE_ROW3 */
|
||||
__IM uint32_t RESERVED7[302];
|
||||
__IOM uint8_t DEVICE_UID[16]; /*!< 0x000014B8 Unique Identifier Number for each device */
|
||||
__IOM uint8_t MASTER_KEY[16]; /*!< 0x000014C8 Master key to change other keys */
|
||||
__IOM uint32_t STANDARD_SMPU_STRUCT_SLAVE_ADDR[16]; /*!< 0x000014D8 Standard SMPU STRUCT Slave Address value */
|
||||
__IOM uint32_t STANDARD_SMPU_STRUCT_SLAVE_ATTR[16]; /*!< 0x00001518 Standard SMPU STRUCT Slave Attribute value */
|
||||
__IOM uint32_t STANDARD_SMPU_STRUCT_MASTER_ATTR[16]; /*!< 0x00001558 Standard SMPU STRUCT Master Attribute value */
|
||||
__IOM uint32_t STANDARD_MPU_STRUCT[16]; /*!< 0x00001598 Standard MPU STRUCT */
|
||||
__IOM uint32_t STANDARD_PPU_STRUCT[16]; /*!< 0x000015D8 Standard PPU STRUCT */
|
||||
__IM uint32_t RESERVED8[122];
|
||||
__IOM uint16_t PILO_FREQ_STEP; /*!< 0x00001800 Resolution step for PILO at class in BCD format */
|
||||
__IM uint16_t RESERVED9;
|
||||
__IOM uint32_t CSDV2_CSD0_ADC_VREF0; /*!< 0x00001804 CSD 1p2 & 1p6 voltage levels for accuracy */
|
||||
__IOM uint32_t CSDV2_CSD0_ADC_VREF1; /*!< 0x00001808 CSD 2p3 & 0p8 voltage levels for accuracy */
|
||||
__IOM uint32_t CSDV2_CSD0_ADC_VREF2; /*!< 0x0000180C CSD calibration spare voltage level for accuracy */
|
||||
__IOM uint32_t PWR_TRIM_WAKE_CTL; /*!< 0x00001810 Wakeup delay */
|
||||
__IM uint16_t RESERVED10;
|
||||
__IOM uint16_t RADIO_LDO_TRIMS; /*!< 0x00001816 Radio LDO Trims */
|
||||
__IOM uint32_t CPUSS_TRIM_ROM_CTL_ULP; /*!< 0x00001818 CPUSS TRIM ROM CTL ULP value */
|
||||
__IOM uint32_t CPUSS_TRIM_RAM_CTL_ULP; /*!< 0x0000181C CPUSS TRIM RAM CTL ULP value */
|
||||
__IOM uint32_t CPUSS_TRIM_ROM_CTL_LP; /*!< 0x00001820 CPUSS TRIM ROM CTL LP value */
|
||||
__IOM uint32_t CPUSS_TRIM_RAM_CTL_LP; /*!< 0x00001824 CPUSS TRIM RAM CTL LP value */
|
||||
__IM uint32_t RESERVED11[7];
|
||||
__IOM uint32_t CPUSS_TRIM_ROM_CTL_HALF_ULP; /*!< 0x00001844 CPUSS TRIM ROM CTL HALF ULP value */
|
||||
__IOM uint32_t CPUSS_TRIM_RAM_CTL_HALF_ULP; /*!< 0x00001848 CPUSS TRIM RAM CTL HALF ULP value */
|
||||
__IOM uint32_t CPUSS_TRIM_ROM_CTL_HALF_LP; /*!< 0x0000184C CPUSS TRIM ROM CTL HALF LP value */
|
||||
__IOM uint32_t CPUSS_TRIM_RAM_CTL_HALF_LP; /*!< 0x00001850 CPUSS TRIM RAM CTL HALF LP value */
|
||||
__IM uint32_t RESERVED12[491];
|
||||
__IOM uint32_t FLASH_BOOT_OBJECT_SIZE; /*!< 0x00002000 Flash Boot - Object Size */
|
||||
__IOM uint32_t FLASH_BOOT_APP_ID; /*!< 0x00002004 Flash Boot - Application ID/Version */
|
||||
__IOM uint32_t FLASH_BOOT_ATTRIBUTE; /*!< 0x00002008 N/A */
|
||||
__IOM uint32_t FLASH_BOOT_N_CORES; /*!< 0x0000200C Flash Boot - Number of Cores(N) */
|
||||
__IOM uint32_t FLASH_BOOT_VT_OFFSET; /*!< 0x00002010 Flash Boot - Core Vector Table offset */
|
||||
__IOM uint32_t FLASH_BOOT_CORE_CPUID; /*!< 0x00002014 Flash Boot - Core CPU ID/Core Index */
|
||||
__IM uint32_t RESERVED13[48];
|
||||
__IOM uint8_t FLASH_BOOT_CODE[8488]; /*!< 0x000020D8 Flash Boot - Code and Data */
|
||||
__IM uint32_t RESERVED14[1536];
|
||||
__IOM uint8_t PUBLIC_KEY[3072]; /*!< 0x00005A00 Public key for signature verification (max RSA key size 4096) */
|
||||
__IOM uint32_t BOOT_PROT_SETTINGS[384]; /*!< 0x00006600 Boot protection settings (not present in PSOC6ABLE2) */
|
||||
__IM uint32_t RESERVED15[768];
|
||||
__IOM uint32_t TOC1_OBJECT_SIZE; /*!< 0x00007800 Object size in bytes for CRC calculation starting from offset
|
||||
0x00 */
|
||||
__IOM uint32_t TOC1_MAGIC_NUMBER; /*!< 0x00007804 Magic number(0x01211219) */
|
||||
__IOM uint32_t TOC1_FHASH_OBJECTS; /*!< 0x00007808 Number of objects starting from offset 0xC to be verified for
|
||||
FACTORY_HASH */
|
||||
__IOM uint32_t TOC1_SFLASH_GENERAL_TRIM_ADDR; /*!< 0x0000780C Address of trims stored in SFLASH */
|
||||
__IOM uint32_t TOC1_UNIQUE_ID_ADDR; /*!< 0x00007810 Address of Unique ID stored in SFLASH */
|
||||
__IOM uint32_t TOC1_FB_OBJECT_ADDR; /*!< 0x00007814 Addresss of FLASH Boot(FB) object that include FLASH patch also */
|
||||
__IOM uint32_t TOC1_SYSCALL_TABLE_ADDR; /*!< 0x00007818 Address of SYSCALL_TABLE entry in SFLASH */
|
||||
__IOM uint32_t TOC1_BOOT_PROTECTION_ADDR; /*!< 0x0000781C Address of boot protection object */
|
||||
__IM uint32_t RESERVED16[119];
|
||||
__IOM uint32_t TOC1_CRC_ADDR; /*!< 0x000079FC Upper 2 bytes contain CRC16-CCITT and lower 2 bytes are 0 */
|
||||
__IOM uint32_t RTOC1_OBJECT_SIZE; /*!< 0x00007A00 Redundant Object size in bytes for CRC calculation starting
|
||||
from offset 0x00 */
|
||||
__IOM uint32_t RTOC1_MAGIC_NUMBER; /*!< 0x00007A04 Redundant Magic number(0x01211219) */
|
||||
__IOM uint32_t RTOC1_FHASH_OBJECTS; /*!< 0x00007A08 Redundant Number of objects starting from offset 0xC to be
|
||||
verified for FACTORY_HASH */
|
||||
__IOM uint32_t RTOC1_SFLASH_GENERAL_TRIM_ADDR; /*!< 0x00007A0C Redundant Address of trims stored in SFLASH */
|
||||
__IOM uint32_t RTOC1_UNIQUE_ID_ADDR; /*!< 0x00007A10 Redundant Address of Unique ID stored in SFLASH */
|
||||
__IOM uint32_t RTOC1_FB_OBJECT_ADDR; /*!< 0x00007A14 Redundant Addresss of FLASH Boot(FB) object that include FLASH
|
||||
patch also */
|
||||
__IOM uint32_t RTOC1_SYSCALL_TABLE_ADDR; /*!< 0x00007A18 Redundant Address of SYSCALL_TABLE entry in SFLASH */
|
||||
__IM uint32_t RESERVED17[120];
|
||||
__IOM uint32_t RTOC1_CRC_ADDR; /*!< 0x00007BFC Redundant CRC,Upper 2 bytes contain CRC16-CCITT and lower 2
|
||||
bytes are 0 */
|
||||
__IOM uint32_t TOC2_OBJECT_SIZE; /*!< 0x00007C00 Object size in bytes for CRC calculation starting from offset
|
||||
0x00 */
|
||||
__IOM uint32_t TOC2_MAGIC_NUMBER; /*!< 0x00007C04 Magic number(0x01211220) */
|
||||
__IOM uint32_t TOC2_KEY_BLOCK_ADDR; /*!< 0x00007C08 Address of Key Storage FLASH blocks */
|
||||
__IOM uint32_t TOC2_SMIF_CFG_STRUCT_ADDR; /*!< 0x00007C0C Null terminated table of pointers representing the SMIF
|
||||
configuration structure */
|
||||
__IOM uint32_t TOC2_FIRST_USER_APP_ADDR; /*!< 0x00007C10 Address of First User Application Object */
|
||||
__IOM uint32_t TOC2_FIRST_USER_APP_FORMAT; /*!< 0x00007C14 Format of First User Application Object. 0 - Basic, 1 - Cypress
|
||||
standard & 2 - Simplified */
|
||||
__IOM uint32_t TOC2_SECOND_USER_APP_ADDR; /*!< 0x00007C18 Address of Second User Application Object */
|
||||
__IOM uint32_t TOC2_SECOND_USER_APP_FORMAT; /*!< 0x00007C1C Format of Second User Application Object. 0 - Basic, 1 -
|
||||
Cypress standard & 2 - Simplified */
|
||||
__IOM uint32_t TOC2_SHASH_OBJECTS; /*!< 0x00007C20 Number of additional objects(in addition to objects covered by
|
||||
FACORY_CAMC) starting from offset 0x24 to be verified for
|
||||
SECURE_HASH(SHASH) */
|
||||
__IOM uint32_t TOC2_SIGNATURE_VERIF_KEY; /*!< 0x00007C24 Address of signature verification key (0 if none).The object is
|
||||
signature specific key. It is the public key in case of RSA */
|
||||
__IM uint32_t RESERVED18[116];
|
||||
__IOM uint32_t TOC2_FLAGS; /*!< 0x00007DF8 TOC2_FLAGS */
|
||||
__IOM uint32_t TOC2_CRC_ADDR; /*!< 0x00007DFC CRC,Upper 2 bytes contain CRC16-CCITT and lower 2 bytes are 0 */
|
||||
__IOM uint32_t RTOC2_OBJECT_SIZE; /*!< 0x00007E00 Redundant Object size in bytes for CRC calculation starting
|
||||
from offset 0x00 */
|
||||
__IOM uint32_t RTOC2_MAGIC_NUMBER; /*!< 0x00007E04 Redundant Magic number(0x01211220) */
|
||||
__IOM uint32_t RTOC2_KEY_BLOCK_ADDR; /*!< 0x00007E08 Redundant Address of Key Storage FLASH blocks */
|
||||
__IOM uint32_t RTOC2_SMIF_CFG_STRUCT_ADDR; /*!< 0x00007E0C Redundant Null terminated table of pointers representing the
|
||||
SMIF configuration structure */
|
||||
__IOM uint32_t RTOC2_FIRST_USER_APP_ADDR; /*!< 0x00007E10 Redundant Address of First User Application Object */
|
||||
__IOM uint32_t RTOC2_FIRST_USER_APP_FORMAT; /*!< 0x00007E14 Redundant Format of First User Application Object. 0 - Basic, 1
|
||||
- Cypress standard & 2 - Simplified */
|
||||
__IOM uint32_t RTOC2_SECOND_USER_APP_ADDR; /*!< 0x00007E18 Redundant Address of Second User Application Object */
|
||||
__IOM uint32_t RTOC2_SECOND_USER_APP_FORMAT; /*!< 0x00007E1C Redundant Format of Second User Application Object. 0 - Basic,
|
||||
1 - Cypress standard & 2 - Simplified */
|
||||
__IOM uint32_t RTOC2_SHASH_OBJECTS; /*!< 0x00007E20 Redundant Number of additional objects(in addition to objects
|
||||
covered by FACORY_CAMC) starting from offset 0x24 to be verified
|
||||
for SECURE_HASH(SHASH) */
|
||||
__IOM uint32_t RTOC2_SIGNATURE_VERIF_KEY; /*!< 0x00007E24 Redundant Address of signature verification key (0 if none).The
|
||||
object is signature specific key. It is the public key in case
|
||||
of RSA */
|
||||
__IM uint32_t RESERVED19[116];
|
||||
__IOM uint32_t RTOC2_FLAGS; /*!< 0x00007FF8 RTOC2_FLAGS */
|
||||
__IOM uint32_t RTOC2_CRC_ADDR; /*!< 0x00007FFC Redundant CRC,Upper 2 bytes contain CRC16-CCITT and lower 2
|
||||
bytes are 0 */
|
||||
} SFLASH_V1_Type; /*!< Size = 32768 (0x8000) */
|
||||
|
||||
|
||||
/* SFLASH.SI_REVISION_ID */
|
||||
#define SFLASH_SI_REVISION_ID_SI_REVISION_ID_Pos 0UL
|
||||
#define SFLASH_SI_REVISION_ID_SI_REVISION_ID_Msk 0xFFUL
|
||||
/* SFLASH.SILICON_ID */
|
||||
#define SFLASH_SILICON_ID_ID_Pos 0UL
|
||||
#define SFLASH_SILICON_ID_ID_Msk 0xFFFFUL
|
||||
/* SFLASH.FAMILY_ID */
|
||||
#define SFLASH_FAMILY_ID_FAMILY_ID_Pos 0UL
|
||||
#define SFLASH_FAMILY_ID_FAMILY_ID_Msk 0xFFFFUL
|
||||
/* SFLASH.DIE_LOT */
|
||||
#define SFLASH_DIE_LOT_LOT_Pos 0UL
|
||||
#define SFLASH_DIE_LOT_LOT_Msk 0xFFUL
|
||||
/* SFLASH.DIE_WAFER */
|
||||
#define SFLASH_DIE_WAFER_WAFER_Pos 0UL
|
||||
#define SFLASH_DIE_WAFER_WAFER_Msk 0xFFUL
|
||||
/* SFLASH.DIE_X */
|
||||
#define SFLASH_DIE_X_X_Pos 0UL
|
||||
#define SFLASH_DIE_X_X_Msk 0xFFUL
|
||||
/* SFLASH.DIE_Y */
|
||||
#define SFLASH_DIE_Y_Y_Pos 0UL
|
||||
#define SFLASH_DIE_Y_Y_Msk 0xFFUL
|
||||
/* SFLASH.DIE_SORT */
|
||||
#define SFLASH_DIE_SORT_S1_PASS_Pos 0UL
|
||||
#define SFLASH_DIE_SORT_S1_PASS_Msk 0x1UL
|
||||
#define SFLASH_DIE_SORT_S2_PASS_Pos 1UL
|
||||
#define SFLASH_DIE_SORT_S2_PASS_Msk 0x2UL
|
||||
#define SFLASH_DIE_SORT_S3_PASS_Pos 2UL
|
||||
#define SFLASH_DIE_SORT_S3_PASS_Msk 0x4UL
|
||||
#define SFLASH_DIE_SORT_CRI_PASS_Pos 3UL
|
||||
#define SFLASH_DIE_SORT_CRI_PASS_Msk 0x8UL
|
||||
#define SFLASH_DIE_SORT_CHI_PASS_Pos 4UL
|
||||
#define SFLASH_DIE_SORT_CHI_PASS_Msk 0x10UL
|
||||
#define SFLASH_DIE_SORT_ENG_PASS_Pos 5UL
|
||||
#define SFLASH_DIE_SORT_ENG_PASS_Msk 0x20UL
|
||||
/* SFLASH.DIE_MINOR */
|
||||
#define SFLASH_DIE_MINOR_MINOR_Pos 0UL
|
||||
#define SFLASH_DIE_MINOR_MINOR_Msk 0xFFUL
|
||||
/* SFLASH.DIE_DAY */
|
||||
#define SFLASH_DIE_DAY_MINOR_Pos 0UL
|
||||
#define SFLASH_DIE_DAY_MINOR_Msk 0xFFUL
|
||||
/* SFLASH.DIE_MONTH */
|
||||
#define SFLASH_DIE_MONTH_MINOR_Pos 0UL
|
||||
#define SFLASH_DIE_MONTH_MINOR_Msk 0xFFUL
|
||||
/* SFLASH.DIE_YEAR */
|
||||
#define SFLASH_DIE_YEAR_MINOR_Pos 0UL
|
||||
#define SFLASH_DIE_YEAR_MINOR_Msk 0xFFUL
|
||||
/* SFLASH.SAR_TEMP_MULTIPLIER */
|
||||
#define SFLASH_SAR_TEMP_MULTIPLIER_TEMP_MULTIPLIER_Pos 0UL
|
||||
#define SFLASH_SAR_TEMP_MULTIPLIER_TEMP_MULTIPLIER_Msk 0xFFFFUL
|
||||
/* SFLASH.SAR_TEMP_OFFSET */
|
||||
#define SFLASH_SAR_TEMP_OFFSET_TEMP_OFFSET_Pos 0UL
|
||||
#define SFLASH_SAR_TEMP_OFFSET_TEMP_OFFSET_Msk 0xFFFFUL
|
||||
/* SFLASH.CSP_PANEL_ID */
|
||||
#define SFLASH_CSP_PANEL_ID_DATA32_Pos 0UL
|
||||
#define SFLASH_CSP_PANEL_ID_DATA32_Msk 0xFFFFFFFFUL
|
||||
/* SFLASH.LDO_0P9V_TRIM */
|
||||
#define SFLASH_LDO_0P9V_TRIM_DATA8_Pos 0UL
|
||||
#define SFLASH_LDO_0P9V_TRIM_DATA8_Msk 0xFFUL
|
||||
/* SFLASH.LDO_1P1V_TRIM */
|
||||
#define SFLASH_LDO_1P1V_TRIM_DATA8_Pos 0UL
|
||||
#define SFLASH_LDO_1P1V_TRIM_DATA8_Msk 0xFFUL
|
||||
/* SFLASH.BLE_DEVICE_ADDRESS */
|
||||
#define SFLASH_BLE_DEVICE_ADDRESS_ADDR_Pos 0UL
|
||||
#define SFLASH_BLE_DEVICE_ADDRESS_ADDR_Msk 0xFFFFFFFFUL
|
||||
/* SFLASH.USER_FREE_ROW1 */
|
||||
#define SFLASH_USER_FREE_ROW1_DATA32_Pos 0UL
|
||||
#define SFLASH_USER_FREE_ROW1_DATA32_Msk 0xFFFFFFFFUL
|
||||
/* SFLASH.USER_FREE_ROW2 */
|
||||
#define SFLASH_USER_FREE_ROW2_DATA32_Pos 0UL
|
||||
#define SFLASH_USER_FREE_ROW2_DATA32_Msk 0xFFFFFFFFUL
|
||||
/* SFLASH.USER_FREE_ROW3 */
|
||||
#define SFLASH_USER_FREE_ROW3_DATA32_Pos 0UL
|
||||
#define SFLASH_USER_FREE_ROW3_DATA32_Msk 0xFFFFFFFFUL
|
||||
/* SFLASH.DEVICE_UID */
|
||||
#define SFLASH_DEVICE_UID_DATA8_Pos 0UL
|
||||
#define SFLASH_DEVICE_UID_DATA8_Msk 0xFFUL
|
||||
/* SFLASH.MASTER_KEY */
|
||||
#define SFLASH_MASTER_KEY_DATA8_Pos 0UL
|
||||
#define SFLASH_MASTER_KEY_DATA8_Msk 0xFFUL
|
||||
/* SFLASH.STANDARD_SMPU_STRUCT_SLAVE_ADDR */
|
||||
#define SFLASH_STANDARD_SMPU_STRUCT_SLAVE_ADDR_DATA32_Pos 0UL
|
||||
#define SFLASH_STANDARD_SMPU_STRUCT_SLAVE_ADDR_DATA32_Msk 0xFFFFFFFFUL
|
||||
/* SFLASH.STANDARD_SMPU_STRUCT_SLAVE_ATTR */
|
||||
#define SFLASH_STANDARD_SMPU_STRUCT_SLAVE_ATTR_DATA32_Pos 0UL
|
||||
#define SFLASH_STANDARD_SMPU_STRUCT_SLAVE_ATTR_DATA32_Msk 0xFFFFFFFFUL
|
||||
/* SFLASH.STANDARD_SMPU_STRUCT_MASTER_ATTR */
|
||||
#define SFLASH_STANDARD_SMPU_STRUCT_MASTER_ATTR_DATA32_Pos 0UL
|
||||
#define SFLASH_STANDARD_SMPU_STRUCT_MASTER_ATTR_DATA32_Msk 0xFFFFFFFFUL
|
||||
/* SFLASH.STANDARD_MPU_STRUCT */
|
||||
#define SFLASH_STANDARD_MPU_STRUCT_DATA32_Pos 0UL
|
||||
#define SFLASH_STANDARD_MPU_STRUCT_DATA32_Msk 0xFFFFFFFFUL
|
||||
/* SFLASH.STANDARD_PPU_STRUCT */
|
||||
#define SFLASH_STANDARD_PPU_STRUCT_DATA32_Pos 0UL
|
||||
#define SFLASH_STANDARD_PPU_STRUCT_DATA32_Msk 0xFFFFFFFFUL
|
||||
/* SFLASH.PILO_FREQ_STEP */
|
||||
#define SFLASH_PILO_FREQ_STEP_STEP_Pos 0UL
|
||||
#define SFLASH_PILO_FREQ_STEP_STEP_Msk 0xFFFFUL
|
||||
/* SFLASH.CSDV2_CSD0_ADC_VREF0 */
|
||||
#define SFLASH_CSDV2_CSD0_ADC_VREF0_VREF_HI_LEVELS_1P2_Pos 0UL
|
||||
#define SFLASH_CSDV2_CSD0_ADC_VREF0_VREF_HI_LEVELS_1P2_Msk 0xFFFFUL
|
||||
#define SFLASH_CSDV2_CSD0_ADC_VREF0_VREF_HI_LEVELS_1P6_Pos 16UL
|
||||
#define SFLASH_CSDV2_CSD0_ADC_VREF0_VREF_HI_LEVELS_1P6_Msk 0xFFFF0000UL
|
||||
/* SFLASH.CSDV2_CSD0_ADC_VREF1 */
|
||||
#define SFLASH_CSDV2_CSD0_ADC_VREF1_VREF_HI_LEVELS_2P1_Pos 0UL
|
||||
#define SFLASH_CSDV2_CSD0_ADC_VREF1_VREF_HI_LEVELS_2P1_Msk 0xFFFFUL
|
||||
#define SFLASH_CSDV2_CSD0_ADC_VREF1_VREF_HI_LEVELS_0P8_Pos 16UL
|
||||
#define SFLASH_CSDV2_CSD0_ADC_VREF1_VREF_HI_LEVELS_0P8_Msk 0xFFFF0000UL
|
||||
/* SFLASH.CSDV2_CSD0_ADC_VREF2 */
|
||||
#define SFLASH_CSDV2_CSD0_ADC_VREF2_VREF_HI_LEVELS_2P6_Pos 0UL
|
||||
#define SFLASH_CSDV2_CSD0_ADC_VREF2_VREF_HI_LEVELS_2P6_Msk 0xFFFFUL
|
||||
/* SFLASH.PWR_TRIM_WAKE_CTL */
|
||||
#define SFLASH_PWR_TRIM_WAKE_CTL_WAKE_DELAY_Pos 0UL
|
||||
#define SFLASH_PWR_TRIM_WAKE_CTL_WAKE_DELAY_Msk 0xFFUL
|
||||
/* SFLASH.RADIO_LDO_TRIMS */
|
||||
#define SFLASH_RADIO_LDO_TRIMS_LDO_ACT_Pos 0UL
|
||||
#define SFLASH_RADIO_LDO_TRIMS_LDO_ACT_Msk 0xFUL
|
||||
#define SFLASH_RADIO_LDO_TRIMS_LDO_LNA_Pos 4UL
|
||||
#define SFLASH_RADIO_LDO_TRIMS_LDO_LNA_Msk 0x30UL
|
||||
#define SFLASH_RADIO_LDO_TRIMS_LDO_IF_Pos 6UL
|
||||
#define SFLASH_RADIO_LDO_TRIMS_LDO_IF_Msk 0xC0UL
|
||||
#define SFLASH_RADIO_LDO_TRIMS_LDO_DIG_Pos 8UL
|
||||
#define SFLASH_RADIO_LDO_TRIMS_LDO_DIG_Msk 0x300UL
|
||||
/* SFLASH.CPUSS_TRIM_ROM_CTL_ULP */
|
||||
#define SFLASH_CPUSS_TRIM_ROM_CTL_ULP_DATA32_Pos 0UL
|
||||
#define SFLASH_CPUSS_TRIM_ROM_CTL_ULP_DATA32_Msk 0xFFFFFFFFUL
|
||||
/* SFLASH.CPUSS_TRIM_RAM_CTL_ULP */
|
||||
#define SFLASH_CPUSS_TRIM_RAM_CTL_ULP_DATA32_Pos 0UL
|
||||
#define SFLASH_CPUSS_TRIM_RAM_CTL_ULP_DATA32_Msk 0xFFFFFFFFUL
|
||||
/* SFLASH.CPUSS_TRIM_ROM_CTL_LP */
|
||||
#define SFLASH_CPUSS_TRIM_ROM_CTL_LP_DATA32_Pos 0UL
|
||||
#define SFLASH_CPUSS_TRIM_ROM_CTL_LP_DATA32_Msk 0xFFFFFFFFUL
|
||||
/* SFLASH.CPUSS_TRIM_RAM_CTL_LP */
|
||||
#define SFLASH_CPUSS_TRIM_RAM_CTL_LP_DATA32_Pos 0UL
|
||||
#define SFLASH_CPUSS_TRIM_RAM_CTL_LP_DATA32_Msk 0xFFFFFFFFUL
|
||||
/* SFLASH.CPUSS_TRIM_ROM_CTL_HALF_ULP */
|
||||
#define SFLASH_CPUSS_TRIM_ROM_CTL_HALF_ULP_DATA32_Pos 0UL
|
||||
#define SFLASH_CPUSS_TRIM_ROM_CTL_HALF_ULP_DATA32_Msk 0xFFFFFFFFUL
|
||||
/* SFLASH.CPUSS_TRIM_RAM_CTL_HALF_ULP */
|
||||
#define SFLASH_CPUSS_TRIM_RAM_CTL_HALF_ULP_DATA32_Pos 0UL
|
||||
#define SFLASH_CPUSS_TRIM_RAM_CTL_HALF_ULP_DATA32_Msk 0xFFFFFFFFUL
|
||||
/* SFLASH.CPUSS_TRIM_ROM_CTL_HALF_LP */
|
||||
#define SFLASH_CPUSS_TRIM_ROM_CTL_HALF_LP_DATA32_Pos 0UL
|
||||
#define SFLASH_CPUSS_TRIM_ROM_CTL_HALF_LP_DATA32_Msk 0xFFFFFFFFUL
|
||||
/* SFLASH.CPUSS_TRIM_RAM_CTL_HALF_LP */
|
||||
#define SFLASH_CPUSS_TRIM_RAM_CTL_HALF_LP_DATA32_Pos 0UL
|
||||
#define SFLASH_CPUSS_TRIM_RAM_CTL_HALF_LP_DATA32_Msk 0xFFFFFFFFUL
|
||||
/* SFLASH.FLASH_BOOT_OBJECT_SIZE */
|
||||
#define SFLASH_FLASH_BOOT_OBJECT_SIZE_DATA32_Pos 0UL
|
||||
#define SFLASH_FLASH_BOOT_OBJECT_SIZE_DATA32_Msk 0xFFFFFFFFUL
|
||||
/* SFLASH.FLASH_BOOT_APP_ID */
|
||||
#define SFLASH_FLASH_BOOT_APP_ID_APP_ID_Pos 0UL
|
||||
#define SFLASH_FLASH_BOOT_APP_ID_APP_ID_Msk 0xFFFFUL
|
||||
#define SFLASH_FLASH_BOOT_APP_ID_MINOR_VERSION_Pos 16UL
|
||||
#define SFLASH_FLASH_BOOT_APP_ID_MINOR_VERSION_Msk 0xFF0000UL
|
||||
#define SFLASH_FLASH_BOOT_APP_ID_MAJOR_VERSION_Pos 24UL
|
||||
#define SFLASH_FLASH_BOOT_APP_ID_MAJOR_VERSION_Msk 0xF000000UL
|
||||
/* SFLASH.FLASH_BOOT_ATTRIBUTE */
|
||||
#define SFLASH_FLASH_BOOT_ATTRIBUTE_DATA32_Pos 0UL
|
||||
#define SFLASH_FLASH_BOOT_ATTRIBUTE_DATA32_Msk 0xFFFFFFFFUL
|
||||
/* SFLASH.FLASH_BOOT_N_CORES */
|
||||
#define SFLASH_FLASH_BOOT_N_CORES_DATA32_Pos 0UL
|
||||
#define SFLASH_FLASH_BOOT_N_CORES_DATA32_Msk 0xFFFFFFFFUL
|
||||
/* SFLASH.FLASH_BOOT_VT_OFFSET */
|
||||
#define SFLASH_FLASH_BOOT_VT_OFFSET_DATA32_Pos 0UL
|
||||
#define SFLASH_FLASH_BOOT_VT_OFFSET_DATA32_Msk 0xFFFFFFFFUL
|
||||
/* SFLASH.FLASH_BOOT_CORE_CPUID */
|
||||
#define SFLASH_FLASH_BOOT_CORE_CPUID_DATA32_Pos 0UL
|
||||
#define SFLASH_FLASH_BOOT_CORE_CPUID_DATA32_Msk 0xFFFFFFFFUL
|
||||
/* SFLASH.FLASH_BOOT_CODE */
|
||||
#define SFLASH_FLASH_BOOT_CODE_DATA32_Pos 0UL
|
||||
#define SFLASH_FLASH_BOOT_CODE_DATA32_Msk 0xFFFFFFFFUL
|
||||
/* SFLASH.PUBLIC_KEY */
|
||||
#define SFLASH_PUBLIC_KEY_DATA_Pos 0UL
|
||||
#define SFLASH_PUBLIC_KEY_DATA_Msk 0xFFUL
|
||||
/* SFLASH.BOOT_PROT_SETTINGS */
|
||||
#define SFLASH_BOOT_PROT_SETTINGS_DATA32_Pos 0UL
|
||||
#define SFLASH_BOOT_PROT_SETTINGS_DATA32_Msk 0xFFFFFFFFUL
|
||||
/* SFLASH.TOC1_OBJECT_SIZE */
|
||||
#define SFLASH_TOC1_OBJECT_SIZE_DATA32_Pos 0UL
|
||||
#define SFLASH_TOC1_OBJECT_SIZE_DATA32_Msk 0xFFFFFFFFUL
|
||||
/* SFLASH.TOC1_MAGIC_NUMBER */
|
||||
#define SFLASH_TOC1_MAGIC_NUMBER_DATA32_Pos 0UL
|
||||
#define SFLASH_TOC1_MAGIC_NUMBER_DATA32_Msk 0xFFFFFFFFUL
|
||||
/* SFLASH.TOC1_FHASH_OBJECTS */
|
||||
#define SFLASH_TOC1_FHASH_OBJECTS_DATA32_Pos 0UL
|
||||
#define SFLASH_TOC1_FHASH_OBJECTS_DATA32_Msk 0xFFFFFFFFUL
|
||||
/* SFLASH.TOC1_SFLASH_GENERAL_TRIM_ADDR */
|
||||
#define SFLASH_TOC1_SFLASH_GENERAL_TRIM_ADDR_DATA32_Pos 0UL
|
||||
#define SFLASH_TOC1_SFLASH_GENERAL_TRIM_ADDR_DATA32_Msk 0xFFFFFFFFUL
|
||||
/* SFLASH.TOC1_UNIQUE_ID_ADDR */
|
||||
#define SFLASH_TOC1_UNIQUE_ID_ADDR_DATA32_Pos 0UL
|
||||
#define SFLASH_TOC1_UNIQUE_ID_ADDR_DATA32_Msk 0xFFFFFFFFUL
|
||||
/* SFLASH.TOC1_FB_OBJECT_ADDR */
|
||||
#define SFLASH_TOC1_FB_OBJECT_ADDR_DATA32_Pos 0UL
|
||||
#define SFLASH_TOC1_FB_OBJECT_ADDR_DATA32_Msk 0xFFFFFFFFUL
|
||||
/* SFLASH.TOC1_SYSCALL_TABLE_ADDR */
|
||||
#define SFLASH_TOC1_SYSCALL_TABLE_ADDR_DATA32_Pos 0UL
|
||||
#define SFLASH_TOC1_SYSCALL_TABLE_ADDR_DATA32_Msk 0xFFFFFFFFUL
|
||||
/* SFLASH.TOC1_BOOT_PROTECTION_ADDR */
|
||||
#define SFLASH_TOC1_BOOT_PROTECTION_ADDR_DATA32_Pos 0UL
|
||||
#define SFLASH_TOC1_BOOT_PROTECTION_ADDR_DATA32_Msk 0xFFFFFFFFUL
|
||||
/* SFLASH.TOC1_CRC_ADDR */
|
||||
#define SFLASH_TOC1_CRC_ADDR_DATA32_Pos 0UL
|
||||
#define SFLASH_TOC1_CRC_ADDR_DATA32_Msk 0xFFFFFFFFUL
|
||||
/* SFLASH.RTOC1_OBJECT_SIZE */
|
||||
#define SFLASH_RTOC1_OBJECT_SIZE_DATA32_Pos 0UL
|
||||
#define SFLASH_RTOC1_OBJECT_SIZE_DATA32_Msk 0xFFFFFFFFUL
|
||||
/* SFLASH.RTOC1_MAGIC_NUMBER */
|
||||
#define SFLASH_RTOC1_MAGIC_NUMBER_DATA32_Pos 0UL
|
||||
#define SFLASH_RTOC1_MAGIC_NUMBER_DATA32_Msk 0xFFFFFFFFUL
|
||||
/* SFLASH.RTOC1_FHASH_OBJECTS */
|
||||
#define SFLASH_RTOC1_FHASH_OBJECTS_DATA32_Pos 0UL
|
||||
#define SFLASH_RTOC1_FHASH_OBJECTS_DATA32_Msk 0xFFFFFFFFUL
|
||||
/* SFLASH.RTOC1_SFLASH_GENERAL_TRIM_ADDR */
|
||||
#define SFLASH_RTOC1_SFLASH_GENERAL_TRIM_ADDR_DATA32_Pos 0UL
|
||||
#define SFLASH_RTOC1_SFLASH_GENERAL_TRIM_ADDR_DATA32_Msk 0xFFFFFFFFUL
|
||||
/* SFLASH.RTOC1_UNIQUE_ID_ADDR */
|
||||
#define SFLASH_RTOC1_UNIQUE_ID_ADDR_DATA32_Pos 0UL
|
||||
#define SFLASH_RTOC1_UNIQUE_ID_ADDR_DATA32_Msk 0xFFFFFFFFUL
|
||||
/* SFLASH.RTOC1_FB_OBJECT_ADDR */
|
||||
#define SFLASH_RTOC1_FB_OBJECT_ADDR_DATA32_Pos 0UL
|
||||
#define SFLASH_RTOC1_FB_OBJECT_ADDR_DATA32_Msk 0xFFFFFFFFUL
|
||||
/* SFLASH.RTOC1_SYSCALL_TABLE_ADDR */
|
||||
#define SFLASH_RTOC1_SYSCALL_TABLE_ADDR_DATA32_Pos 0UL
|
||||
#define SFLASH_RTOC1_SYSCALL_TABLE_ADDR_DATA32_Msk 0xFFFFFFFFUL
|
||||
/* SFLASH.RTOC1_CRC_ADDR */
|
||||
#define SFLASH_RTOC1_CRC_ADDR_DATA32_Pos 0UL
|
||||
#define SFLASH_RTOC1_CRC_ADDR_DATA32_Msk 0xFFFFFFFFUL
|
||||
/* SFLASH.TOC2_OBJECT_SIZE */
|
||||
#define SFLASH_TOC2_OBJECT_SIZE_DATA32_Pos 0UL
|
||||
#define SFLASH_TOC2_OBJECT_SIZE_DATA32_Msk 0xFFFFFFFFUL
|
||||
/* SFLASH.TOC2_MAGIC_NUMBER */
|
||||
#define SFLASH_TOC2_MAGIC_NUMBER_DATA32_Pos 0UL
|
||||
#define SFLASH_TOC2_MAGIC_NUMBER_DATA32_Msk 0xFFFFFFFFUL
|
||||
/* SFLASH.TOC2_KEY_BLOCK_ADDR */
|
||||
#define SFLASH_TOC2_KEY_BLOCK_ADDR_DATA32_Pos 0UL
|
||||
#define SFLASH_TOC2_KEY_BLOCK_ADDR_DATA32_Msk 0xFFFFFFFFUL
|
||||
/* SFLASH.TOC2_SMIF_CFG_STRUCT_ADDR */
|
||||
#define SFLASH_TOC2_SMIF_CFG_STRUCT_ADDR_DATA32_Pos 0UL
|
||||
#define SFLASH_TOC2_SMIF_CFG_STRUCT_ADDR_DATA32_Msk 0xFFFFFFFFUL
|
||||
/* SFLASH.TOC2_FIRST_USER_APP_ADDR */
|
||||
#define SFLASH_TOC2_FIRST_USER_APP_ADDR_DATA32_Pos 0UL
|
||||
#define SFLASH_TOC2_FIRST_USER_APP_ADDR_DATA32_Msk 0xFFFFFFFFUL
|
||||
/* SFLASH.TOC2_FIRST_USER_APP_FORMAT */
|
||||
#define SFLASH_TOC2_FIRST_USER_APP_FORMAT_DATA32_Pos 0UL
|
||||
#define SFLASH_TOC2_FIRST_USER_APP_FORMAT_DATA32_Msk 0xFFFFFFFFUL
|
||||
/* SFLASH.TOC2_SECOND_USER_APP_ADDR */
|
||||
#define SFLASH_TOC2_SECOND_USER_APP_ADDR_DATA32_Pos 0UL
|
||||
#define SFLASH_TOC2_SECOND_USER_APP_ADDR_DATA32_Msk 0xFFFFFFFFUL
|
||||
/* SFLASH.TOC2_SECOND_USER_APP_FORMAT */
|
||||
#define SFLASH_TOC2_SECOND_USER_APP_FORMAT_DATA32_Pos 0UL
|
||||
#define SFLASH_TOC2_SECOND_USER_APP_FORMAT_DATA32_Msk 0xFFFFFFFFUL
|
||||
/* SFLASH.TOC2_SHASH_OBJECTS */
|
||||
#define SFLASH_TOC2_SHASH_OBJECTS_DATA32_Pos 0UL
|
||||
#define SFLASH_TOC2_SHASH_OBJECTS_DATA32_Msk 0xFFFFFFFFUL
|
||||
/* SFLASH.TOC2_SIGNATURE_VERIF_KEY */
|
||||
#define SFLASH_TOC2_SIGNATURE_VERIF_KEY_DATA32_Pos 0UL
|
||||
#define SFLASH_TOC2_SIGNATURE_VERIF_KEY_DATA32_Msk 0xFFFFFFFFUL
|
||||
/* SFLASH.TOC2_FLAGS */
|
||||
#define SFLASH_TOC2_FLAGS_DATA32_Pos 0UL
|
||||
#define SFLASH_TOC2_FLAGS_DATA32_Msk 0xFFFFFFFFUL
|
||||
/* SFLASH.TOC2_CRC_ADDR */
|
||||
#define SFLASH_TOC2_CRC_ADDR_DATA32_Pos 0UL
|
||||
#define SFLASH_TOC2_CRC_ADDR_DATA32_Msk 0xFFFFFFFFUL
|
||||
/* SFLASH.RTOC2_OBJECT_SIZE */
|
||||
#define SFLASH_RTOC2_OBJECT_SIZE_DATA32_Pos 0UL
|
||||
#define SFLASH_RTOC2_OBJECT_SIZE_DATA32_Msk 0xFFFFFFFFUL
|
||||
/* SFLASH.RTOC2_MAGIC_NUMBER */
|
||||
#define SFLASH_RTOC2_MAGIC_NUMBER_DATA32_Pos 0UL
|
||||
#define SFLASH_RTOC2_MAGIC_NUMBER_DATA32_Msk 0xFFFFFFFFUL
|
||||
/* SFLASH.RTOC2_KEY_BLOCK_ADDR */
|
||||
#define SFLASH_RTOC2_KEY_BLOCK_ADDR_DATA32_Pos 0UL
|
||||
#define SFLASH_RTOC2_KEY_BLOCK_ADDR_DATA32_Msk 0xFFFFFFFFUL
|
||||
/* SFLASH.RTOC2_SMIF_CFG_STRUCT_ADDR */
|
||||
#define SFLASH_RTOC2_SMIF_CFG_STRUCT_ADDR_DATA32_Pos 0UL
|
||||
#define SFLASH_RTOC2_SMIF_CFG_STRUCT_ADDR_DATA32_Msk 0xFFFFFFFFUL
|
||||
/* SFLASH.RTOC2_FIRST_USER_APP_ADDR */
|
||||
#define SFLASH_RTOC2_FIRST_USER_APP_ADDR_DATA32_Pos 0UL
|
||||
#define SFLASH_RTOC2_FIRST_USER_APP_ADDR_DATA32_Msk 0xFFFFFFFFUL
|
||||
/* SFLASH.RTOC2_FIRST_USER_APP_FORMAT */
|
||||
#define SFLASH_RTOC2_FIRST_USER_APP_FORMAT_DATA32_Pos 0UL
|
||||
#define SFLASH_RTOC2_FIRST_USER_APP_FORMAT_DATA32_Msk 0xFFFFFFFFUL
|
||||
/* SFLASH.RTOC2_SECOND_USER_APP_ADDR */
|
||||
#define SFLASH_RTOC2_SECOND_USER_APP_ADDR_DATA32_Pos 0UL
|
||||
#define SFLASH_RTOC2_SECOND_USER_APP_ADDR_DATA32_Msk 0xFFFFFFFFUL
|
||||
/* SFLASH.RTOC2_SECOND_USER_APP_FORMAT */
|
||||
#define SFLASH_RTOC2_SECOND_USER_APP_FORMAT_DATA32_Pos 0UL
|
||||
#define SFLASH_RTOC2_SECOND_USER_APP_FORMAT_DATA32_Msk 0xFFFFFFFFUL
|
||||
/* SFLASH.RTOC2_SHASH_OBJECTS */
|
||||
#define SFLASH_RTOC2_SHASH_OBJECTS_DATA32_Pos 0UL
|
||||
#define SFLASH_RTOC2_SHASH_OBJECTS_DATA32_Msk 0xFFFFFFFFUL
|
||||
/* SFLASH.RTOC2_SIGNATURE_VERIF_KEY */
|
||||
#define SFLASH_RTOC2_SIGNATURE_VERIF_KEY_DATA32_Pos 0UL
|
||||
#define SFLASH_RTOC2_SIGNATURE_VERIF_KEY_DATA32_Msk 0xFFFFFFFFUL
|
||||
/* SFLASH.RTOC2_FLAGS */
|
||||
#define SFLASH_RTOC2_FLAGS_DATA32_Pos 0UL
|
||||
#define SFLASH_RTOC2_FLAGS_DATA32_Msk 0xFFFFFFFFUL
|
||||
/* SFLASH.RTOC2_CRC_ADDR */
|
||||
#define SFLASH_RTOC2_CRC_ADDR_DATA32_Pos 0UL
|
||||
#define SFLASH_RTOC2_CRC_ADDR_DATA32_Msk 0xFFFFFFFFUL
|
||||
|
||||
|
||||
#endif /* _CYIP_SFLASH_H_ */
|
||||
|
||||
|
||||
/* [] END OF FILE */
|
||||
|
|
@ -1,110 +0,0 @@
|
|||
/***************************************************************************//**
|
||||
* \file cyip_smartio.h
|
||||
*
|
||||
* \brief
|
||||
* SMARTIO IP definitions
|
||||
*
|
||||
* \note
|
||||
* Generator version: 1.3.0.1146
|
||||
* Database revision: rev#1050929
|
||||
*
|
||||
********************************************************************************
|
||||
* \copyright
|
||||
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
|
||||
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _CYIP_SMARTIO_H_
|
||||
#define _CYIP_SMARTIO_H_
|
||||
|
||||
#include "cyip_headers.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* SMARTIO
|
||||
*******************************************************************************/
|
||||
|
||||
#define SMARTIO_PRT_SECTION_SIZE 0x00000100UL
|
||||
#define SMARTIO_SECTION_SIZE 0x00010000UL
|
||||
|
||||
/**
|
||||
* \brief Programmable IO port registers (SMARTIO_PRT)
|
||||
*/
|
||||
typedef struct {
|
||||
__IOM uint32_t CTL; /*!< 0x00000000 Control register */
|
||||
__IM uint32_t RESERVED[3];
|
||||
__IOM uint32_t SYNC_CTL; /*!< 0x00000010 Synchronization control register */
|
||||
__IM uint32_t RESERVED1[3];
|
||||
__IOM uint32_t LUT_SEL[8]; /*!< 0x00000020 LUT component input selection */
|
||||
__IOM uint32_t LUT_CTL[8]; /*!< 0x00000040 LUT component control register */
|
||||
__IM uint32_t RESERVED2[24];
|
||||
__IOM uint32_t DU_SEL; /*!< 0x000000C0 Data unit component input selection */
|
||||
__IOM uint32_t DU_CTL; /*!< 0x000000C4 Data unit component control register */
|
||||
__IM uint32_t RESERVED3[10];
|
||||
__IOM uint32_t DATA; /*!< 0x000000F0 Data register */
|
||||
__IM uint32_t RESERVED4[3];
|
||||
} SMARTIO_PRT_V1_Type; /*!< Size = 256 (0x100) */
|
||||
|
||||
/**
|
||||
* \brief Programmable IO configuration (SMARTIO)
|
||||
*/
|
||||
typedef struct {
|
||||
SMARTIO_PRT_V1_Type PRT[128]; /*!< 0x00000000 Programmable IO port registers */
|
||||
} SMARTIO_V1_Type; /*!< Size = 32768 (0x8000) */
|
||||
|
||||
|
||||
/* SMARTIO_PRT.CTL */
|
||||
#define SMARTIO_PRT_CTL_BYPASS_Pos 0UL
|
||||
#define SMARTIO_PRT_CTL_BYPASS_Msk 0xFFUL
|
||||
#define SMARTIO_PRT_CTL_CLOCK_SRC_Pos 8UL
|
||||
#define SMARTIO_PRT_CTL_CLOCK_SRC_Msk 0x1F00UL
|
||||
#define SMARTIO_PRT_CTL_HLD_OVR_Pos 24UL
|
||||
#define SMARTIO_PRT_CTL_HLD_OVR_Msk 0x1000000UL
|
||||
#define SMARTIO_PRT_CTL_PIPELINE_EN_Pos 25UL
|
||||
#define SMARTIO_PRT_CTL_PIPELINE_EN_Msk 0x2000000UL
|
||||
#define SMARTIO_PRT_CTL_ENABLED_Pos 31UL
|
||||
#define SMARTIO_PRT_CTL_ENABLED_Msk 0x80000000UL
|
||||
/* SMARTIO_PRT.SYNC_CTL */
|
||||
#define SMARTIO_PRT_SYNC_CTL_IO_SYNC_EN_Pos 0UL
|
||||
#define SMARTIO_PRT_SYNC_CTL_IO_SYNC_EN_Msk 0xFFUL
|
||||
#define SMARTIO_PRT_SYNC_CTL_CHIP_SYNC_EN_Pos 8UL
|
||||
#define SMARTIO_PRT_SYNC_CTL_CHIP_SYNC_EN_Msk 0xFF00UL
|
||||
/* SMARTIO_PRT.LUT_SEL */
|
||||
#define SMARTIO_PRT_LUT_SEL_LUT_TR0_SEL_Pos 0UL
|
||||
#define SMARTIO_PRT_LUT_SEL_LUT_TR0_SEL_Msk 0xFUL
|
||||
#define SMARTIO_PRT_LUT_SEL_LUT_TR1_SEL_Pos 8UL
|
||||
#define SMARTIO_PRT_LUT_SEL_LUT_TR1_SEL_Msk 0xF00UL
|
||||
#define SMARTIO_PRT_LUT_SEL_LUT_TR2_SEL_Pos 16UL
|
||||
#define SMARTIO_PRT_LUT_SEL_LUT_TR2_SEL_Msk 0xF0000UL
|
||||
/* SMARTIO_PRT.LUT_CTL */
|
||||
#define SMARTIO_PRT_LUT_CTL_LUT_Pos 0UL
|
||||
#define SMARTIO_PRT_LUT_CTL_LUT_Msk 0xFFUL
|
||||
#define SMARTIO_PRT_LUT_CTL_LUT_OPC_Pos 8UL
|
||||
#define SMARTIO_PRT_LUT_CTL_LUT_OPC_Msk 0x300UL
|
||||
/* SMARTIO_PRT.DU_SEL */
|
||||
#define SMARTIO_PRT_DU_SEL_DU_TR0_SEL_Pos 0UL
|
||||
#define SMARTIO_PRT_DU_SEL_DU_TR0_SEL_Msk 0xFUL
|
||||
#define SMARTIO_PRT_DU_SEL_DU_TR1_SEL_Pos 8UL
|
||||
#define SMARTIO_PRT_DU_SEL_DU_TR1_SEL_Msk 0xF00UL
|
||||
#define SMARTIO_PRT_DU_SEL_DU_TR2_SEL_Pos 16UL
|
||||
#define SMARTIO_PRT_DU_SEL_DU_TR2_SEL_Msk 0xF0000UL
|
||||
#define SMARTIO_PRT_DU_SEL_DU_DATA0_SEL_Pos 24UL
|
||||
#define SMARTIO_PRT_DU_SEL_DU_DATA0_SEL_Msk 0x3000000UL
|
||||
#define SMARTIO_PRT_DU_SEL_DU_DATA1_SEL_Pos 28UL
|
||||
#define SMARTIO_PRT_DU_SEL_DU_DATA1_SEL_Msk 0x30000000UL
|
||||
/* SMARTIO_PRT.DU_CTL */
|
||||
#define SMARTIO_PRT_DU_CTL_DU_SIZE_Pos 0UL
|
||||
#define SMARTIO_PRT_DU_CTL_DU_SIZE_Msk 0x7UL
|
||||
#define SMARTIO_PRT_DU_CTL_DU_OPC_Pos 8UL
|
||||
#define SMARTIO_PRT_DU_CTL_DU_OPC_Msk 0xF00UL
|
||||
/* SMARTIO_PRT.DATA */
|
||||
#define SMARTIO_PRT_DATA_DATA_Pos 0UL
|
||||
#define SMARTIO_PRT_DATA_DATA_Msk 0xFFUL
|
||||
|
||||
|
||||
#endif /* _CYIP_SMARTIO_H_ */
|
||||
|
||||
|
||||
/* [] END OF FILE */
|
||||
|
|
@ -1,110 +0,0 @@
|
|||
/***************************************************************************//**
|
||||
* \file cyip_smartio_v2.h
|
||||
*
|
||||
* \brief
|
||||
* SMARTIO IP definitions
|
||||
*
|
||||
* \note
|
||||
* Generator version: 1.3.0.1146
|
||||
* Database revision: rev#1050929
|
||||
*
|
||||
********************************************************************************
|
||||
* \copyright
|
||||
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
|
||||
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _CYIP_SMARTIO_V2_H_
|
||||
#define _CYIP_SMARTIO_V2_H_
|
||||
|
||||
#include "cyip_headers.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* SMARTIO
|
||||
*******************************************************************************/
|
||||
|
||||
#define SMARTIO_PRT_V2_SECTION_SIZE 0x00000100UL
|
||||
#define SMARTIO_V2_SECTION_SIZE 0x00010000UL
|
||||
|
||||
/**
|
||||
* \brief Programmable IO port registers (SMARTIO_PRT)
|
||||
*/
|
||||
typedef struct {
|
||||
__IOM uint32_t CTL; /*!< 0x00000000 Control register */
|
||||
__IM uint32_t RESERVED[3];
|
||||
__IOM uint32_t SYNC_CTL; /*!< 0x00000010 Synchronization control register */
|
||||
__IM uint32_t RESERVED1[3];
|
||||
__IOM uint32_t LUT_SEL[8]; /*!< 0x00000020 LUT component input selection */
|
||||
__IOM uint32_t LUT_CTL[8]; /*!< 0x00000040 LUT component control register */
|
||||
__IM uint32_t RESERVED2[24];
|
||||
__IOM uint32_t DU_SEL; /*!< 0x000000C0 Data unit component input selection */
|
||||
__IOM uint32_t DU_CTL; /*!< 0x000000C4 Data unit component control register */
|
||||
__IM uint32_t RESERVED3[10];
|
||||
__IOM uint32_t DATA; /*!< 0x000000F0 Data register */
|
||||
__IM uint32_t RESERVED4[3];
|
||||
} SMARTIO_PRT_V2_Type; /*!< Size = 256 (0x100) */
|
||||
|
||||
/**
|
||||
* \brief Programmable IO configuration (SMARTIO)
|
||||
*/
|
||||
typedef struct {
|
||||
SMARTIO_PRT_V2_Type PRT[128]; /*!< 0x00000000 Programmable IO port registers */
|
||||
} SMARTIO_V2_Type; /*!< Size = 32768 (0x8000) */
|
||||
|
||||
|
||||
/* SMARTIO_PRT.CTL */
|
||||
#define SMARTIO_PRT_V2_CTL_BYPASS_Pos 0UL
|
||||
#define SMARTIO_PRT_V2_CTL_BYPASS_Msk 0xFFUL
|
||||
#define SMARTIO_PRT_V2_CTL_CLOCK_SRC_Pos 8UL
|
||||
#define SMARTIO_PRT_V2_CTL_CLOCK_SRC_Msk 0x1F00UL
|
||||
#define SMARTIO_PRT_V2_CTL_HLD_OVR_Pos 24UL
|
||||
#define SMARTIO_PRT_V2_CTL_HLD_OVR_Msk 0x1000000UL
|
||||
#define SMARTIO_PRT_V2_CTL_PIPELINE_EN_Pos 25UL
|
||||
#define SMARTIO_PRT_V2_CTL_PIPELINE_EN_Msk 0x2000000UL
|
||||
#define SMARTIO_PRT_V2_CTL_ENABLED_Pos 31UL
|
||||
#define SMARTIO_PRT_V2_CTL_ENABLED_Msk 0x80000000UL
|
||||
/* SMARTIO_PRT.SYNC_CTL */
|
||||
#define SMARTIO_PRT_V2_SYNC_CTL_IO_SYNC_EN_Pos 0UL
|
||||
#define SMARTIO_PRT_V2_SYNC_CTL_IO_SYNC_EN_Msk 0xFFUL
|
||||
#define SMARTIO_PRT_V2_SYNC_CTL_CHIP_SYNC_EN_Pos 8UL
|
||||
#define SMARTIO_PRT_V2_SYNC_CTL_CHIP_SYNC_EN_Msk 0xFF00UL
|
||||
/* SMARTIO_PRT.LUT_SEL */
|
||||
#define SMARTIO_PRT_V2_LUT_SEL_LUT_TR0_SEL_Pos 0UL
|
||||
#define SMARTIO_PRT_V2_LUT_SEL_LUT_TR0_SEL_Msk 0xFUL
|
||||
#define SMARTIO_PRT_V2_LUT_SEL_LUT_TR1_SEL_Pos 8UL
|
||||
#define SMARTIO_PRT_V2_LUT_SEL_LUT_TR1_SEL_Msk 0xF00UL
|
||||
#define SMARTIO_PRT_V2_LUT_SEL_LUT_TR2_SEL_Pos 16UL
|
||||
#define SMARTIO_PRT_V2_LUT_SEL_LUT_TR2_SEL_Msk 0xF0000UL
|
||||
/* SMARTIO_PRT.LUT_CTL */
|
||||
#define SMARTIO_PRT_V2_LUT_CTL_LUT_Pos 0UL
|
||||
#define SMARTIO_PRT_V2_LUT_CTL_LUT_Msk 0xFFUL
|
||||
#define SMARTIO_PRT_V2_LUT_CTL_LUT_OPC_Pos 8UL
|
||||
#define SMARTIO_PRT_V2_LUT_CTL_LUT_OPC_Msk 0x300UL
|
||||
/* SMARTIO_PRT.DU_SEL */
|
||||
#define SMARTIO_PRT_V2_DU_SEL_DU_TR0_SEL_Pos 0UL
|
||||
#define SMARTIO_PRT_V2_DU_SEL_DU_TR0_SEL_Msk 0xFUL
|
||||
#define SMARTIO_PRT_V2_DU_SEL_DU_TR1_SEL_Pos 8UL
|
||||
#define SMARTIO_PRT_V2_DU_SEL_DU_TR1_SEL_Msk 0xF00UL
|
||||
#define SMARTIO_PRT_V2_DU_SEL_DU_TR2_SEL_Pos 16UL
|
||||
#define SMARTIO_PRT_V2_DU_SEL_DU_TR2_SEL_Msk 0xF0000UL
|
||||
#define SMARTIO_PRT_V2_DU_SEL_DU_DATA0_SEL_Pos 24UL
|
||||
#define SMARTIO_PRT_V2_DU_SEL_DU_DATA0_SEL_Msk 0x3000000UL
|
||||
#define SMARTIO_PRT_V2_DU_SEL_DU_DATA1_SEL_Pos 28UL
|
||||
#define SMARTIO_PRT_V2_DU_SEL_DU_DATA1_SEL_Msk 0x30000000UL
|
||||
/* SMARTIO_PRT.DU_CTL */
|
||||
#define SMARTIO_PRT_V2_DU_CTL_DU_SIZE_Pos 0UL
|
||||
#define SMARTIO_PRT_V2_DU_CTL_DU_SIZE_Msk 0x7UL
|
||||
#define SMARTIO_PRT_V2_DU_CTL_DU_OPC_Pos 8UL
|
||||
#define SMARTIO_PRT_V2_DU_CTL_DU_OPC_Msk 0xF00UL
|
||||
/* SMARTIO_PRT.DATA */
|
||||
#define SMARTIO_PRT_V2_DATA_DATA_Pos 0UL
|
||||
#define SMARTIO_PRT_V2_DATA_DATA_Msk 0xFFUL
|
||||
|
||||
|
||||
#endif /* _CYIP_SMARTIO_V2_H_ */
|
||||
|
||||
|
||||
/* [] END OF FILE */
|
||||
|
|
@ -1,379 +0,0 @@
|
|||
/***************************************************************************//**
|
||||
* \file cyip_smif.h
|
||||
*
|
||||
* \brief
|
||||
* SMIF IP definitions
|
||||
*
|
||||
* \note
|
||||
* Generator version: 1.3.0.1146
|
||||
* Database revision: rev#1050929
|
||||
*
|
||||
********************************************************************************
|
||||
* \copyright
|
||||
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
|
||||
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _CYIP_SMIF_H_
|
||||
#define _CYIP_SMIF_H_
|
||||
|
||||
#include "cyip_headers.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* SMIF
|
||||
*******************************************************************************/
|
||||
|
||||
#define SMIF_DEVICE_SECTION_SIZE 0x00000080UL
|
||||
#define SMIF_SECTION_SIZE 0x00010000UL
|
||||
|
||||
/**
|
||||
* \brief Device (only used in XIP mode) (SMIF_DEVICE)
|
||||
*/
|
||||
typedef struct {
|
||||
__IOM uint32_t CTL; /*!< 0x00000000 Control */
|
||||
__IM uint32_t RESERVED;
|
||||
__IOM uint32_t ADDR; /*!< 0x00000008 Device region base address */
|
||||
__IOM uint32_t MASK; /*!< 0x0000000C Device region mask */
|
||||
__IM uint32_t RESERVED1[4];
|
||||
__IOM uint32_t ADDR_CTL; /*!< 0x00000020 Address control */
|
||||
__IM uint32_t RESERVED2[7];
|
||||
__IOM uint32_t RD_CMD_CTL; /*!< 0x00000040 Read command control */
|
||||
__IOM uint32_t RD_ADDR_CTL; /*!< 0x00000044 Read address control */
|
||||
__IOM uint32_t RD_MODE_CTL; /*!< 0x00000048 Read mode control */
|
||||
__IOM uint32_t RD_DUMMY_CTL; /*!< 0x0000004C Read dummy control */
|
||||
__IOM uint32_t RD_DATA_CTL; /*!< 0x00000050 Read data control */
|
||||
__IM uint32_t RESERVED3[3];
|
||||
__IOM uint32_t WR_CMD_CTL; /*!< 0x00000060 Write command control */
|
||||
__IOM uint32_t WR_ADDR_CTL; /*!< 0x00000064 Write address control */
|
||||
__IOM uint32_t WR_MODE_CTL; /*!< 0x00000068 Write mode control */
|
||||
__IOM uint32_t WR_DUMMY_CTL; /*!< 0x0000006C Write dummy control */
|
||||
__IOM uint32_t WR_DATA_CTL; /*!< 0x00000070 Write data control */
|
||||
__IM uint32_t RESERVED4[3];
|
||||
} SMIF_DEVICE_V1_Type; /*!< Size = 128 (0x80) */
|
||||
|
||||
/**
|
||||
* \brief Serial Memory Interface (SMIF)
|
||||
*/
|
||||
typedef struct {
|
||||
__IOM uint32_t CTL; /*!< 0x00000000 Control */
|
||||
__IM uint32_t STATUS; /*!< 0x00000004 Status */
|
||||
__IM uint32_t RESERVED[15];
|
||||
__IM uint32_t TX_CMD_FIFO_STATUS; /*!< 0x00000044 Transmitter command FIFO status */
|
||||
__IM uint32_t RESERVED1[2];
|
||||
__OM uint32_t TX_CMD_FIFO_WR; /*!< 0x00000050 Transmitter command FIFO write */
|
||||
__IM uint32_t RESERVED2[11];
|
||||
__IOM uint32_t TX_DATA_FIFO_CTL; /*!< 0x00000080 Transmitter data FIFO control */
|
||||
__IM uint32_t TX_DATA_FIFO_STATUS; /*!< 0x00000084 Transmitter data FIFO status */
|
||||
__IM uint32_t RESERVED3[2];
|
||||
__OM uint32_t TX_DATA_FIFO_WR1; /*!< 0x00000090 Transmitter data FIFO write */
|
||||
__OM uint32_t TX_DATA_FIFO_WR2; /*!< 0x00000094 Transmitter data FIFO write */
|
||||
__OM uint32_t TX_DATA_FIFO_WR4; /*!< 0x00000098 Transmitter data FIFO write */
|
||||
__IM uint32_t RESERVED4[9];
|
||||
__IOM uint32_t RX_DATA_FIFO_CTL; /*!< 0x000000C0 Receiver data FIFO control */
|
||||
__IM uint32_t RX_DATA_FIFO_STATUS; /*!< 0x000000C4 Receiver data FIFO status */
|
||||
__IM uint32_t RESERVED5[2];
|
||||
__IM uint32_t RX_DATA_FIFO_RD1; /*!< 0x000000D0 Receiver data FIFO read */
|
||||
__IM uint32_t RX_DATA_FIFO_RD2; /*!< 0x000000D4 Receiver data FIFO read */
|
||||
__IM uint32_t RX_DATA_FIFO_RD4; /*!< 0x000000D8 Receiver data FIFO read */
|
||||
__IM uint32_t RESERVED6;
|
||||
__IM uint32_t RX_DATA_FIFO_RD1_SILENT; /*!< 0x000000E0 Receiver data FIFO silent read */
|
||||
__IM uint32_t RESERVED7[7];
|
||||
__IOM uint32_t SLOW_CA_CTL; /*!< 0x00000100 Slow cache control */
|
||||
__IM uint32_t RESERVED8;
|
||||
__IOM uint32_t SLOW_CA_CMD; /*!< 0x00000108 Slow cache command */
|
||||
__IM uint32_t RESERVED9[29];
|
||||
__IOM uint32_t FAST_CA_CTL; /*!< 0x00000180 Fast cache control */
|
||||
__IM uint32_t RESERVED10;
|
||||
__IOM uint32_t FAST_CA_CMD; /*!< 0x00000188 Fast cache command */
|
||||
__IM uint32_t RESERVED11[29];
|
||||
__IOM uint32_t CRYPTO_CMD; /*!< 0x00000200 Cryptography Command */
|
||||
__IM uint32_t RESERVED12[7];
|
||||
__IOM uint32_t CRYPTO_INPUT0; /*!< 0x00000220 Cryptography input 0 */
|
||||
__IOM uint32_t CRYPTO_INPUT1; /*!< 0x00000224 Cryptography input 1 */
|
||||
__IOM uint32_t CRYPTO_INPUT2; /*!< 0x00000228 Cryptography input 2 */
|
||||
__IOM uint32_t CRYPTO_INPUT3; /*!< 0x0000022C Cryptography input 3 */
|
||||
__IM uint32_t RESERVED13[4];
|
||||
__OM uint32_t CRYPTO_KEY0; /*!< 0x00000240 Cryptography key 0 */
|
||||
__OM uint32_t CRYPTO_KEY1; /*!< 0x00000244 Cryptography key 1 */
|
||||
__OM uint32_t CRYPTO_KEY2; /*!< 0x00000248 Cryptography key 2 */
|
||||
__OM uint32_t CRYPTO_KEY3; /*!< 0x0000024C Cryptography key 3 */
|
||||
__IM uint32_t RESERVED14[4];
|
||||
__IOM uint32_t CRYPTO_OUTPUT0; /*!< 0x00000260 Cryptography output 0 */
|
||||
__IOM uint32_t CRYPTO_OUTPUT1; /*!< 0x00000264 Cryptography output 1 */
|
||||
__IOM uint32_t CRYPTO_OUTPUT2; /*!< 0x00000268 Cryptography output 2 */
|
||||
__IOM uint32_t CRYPTO_OUTPUT3; /*!< 0x0000026C Cryptography output 3 */
|
||||
__IM uint32_t RESERVED15[340];
|
||||
__IOM uint32_t INTR; /*!< 0x000007C0 Interrupt register */
|
||||
__IOM uint32_t INTR_SET; /*!< 0x000007C4 Interrupt set register */
|
||||
__IOM uint32_t INTR_MASK; /*!< 0x000007C8 Interrupt mask register */
|
||||
__IM uint32_t INTR_MASKED; /*!< 0x000007CC Interrupt masked register */
|
||||
__IM uint32_t RESERVED16[12];
|
||||
SMIF_DEVICE_V1_Type DEVICE[4]; /*!< 0x00000800 Device (only used in XIP mode) */
|
||||
} SMIF_V1_Type; /*!< Size = 2560 (0xA00) */
|
||||
|
||||
|
||||
/* SMIF_DEVICE.CTL */
|
||||
#define SMIF_DEVICE_CTL_WR_EN_Pos 0UL
|
||||
#define SMIF_DEVICE_CTL_WR_EN_Msk 0x1UL
|
||||
#define SMIF_DEVICE_CTL_CRYPTO_EN_Pos 8UL
|
||||
#define SMIF_DEVICE_CTL_CRYPTO_EN_Msk 0x100UL
|
||||
#define SMIF_DEVICE_CTL_DATA_SEL_Pos 16UL
|
||||
#define SMIF_DEVICE_CTL_DATA_SEL_Msk 0x30000UL
|
||||
#define SMIF_DEVICE_CTL_ENABLED_Pos 31UL
|
||||
#define SMIF_DEVICE_CTL_ENABLED_Msk 0x80000000UL
|
||||
/* SMIF_DEVICE.ADDR */
|
||||
#define SMIF_DEVICE_ADDR_ADDR_Pos 8UL
|
||||
#define SMIF_DEVICE_ADDR_ADDR_Msk 0xFFFFFF00UL
|
||||
/* SMIF_DEVICE.MASK */
|
||||
#define SMIF_DEVICE_MASK_MASK_Pos 8UL
|
||||
#define SMIF_DEVICE_MASK_MASK_Msk 0xFFFFFF00UL
|
||||
/* SMIF_DEVICE.ADDR_CTL */
|
||||
#define SMIF_DEVICE_ADDR_CTL_SIZE2_Pos 0UL
|
||||
#define SMIF_DEVICE_ADDR_CTL_SIZE2_Msk 0x3UL
|
||||
#define SMIF_DEVICE_ADDR_CTL_DIV2_Pos 8UL
|
||||
#define SMIF_DEVICE_ADDR_CTL_DIV2_Msk 0x100UL
|
||||
/* SMIF_DEVICE.RD_CMD_CTL */
|
||||
#define SMIF_DEVICE_RD_CMD_CTL_CODE_Pos 0UL
|
||||
#define SMIF_DEVICE_RD_CMD_CTL_CODE_Msk 0xFFUL
|
||||
#define SMIF_DEVICE_RD_CMD_CTL_WIDTH_Pos 16UL
|
||||
#define SMIF_DEVICE_RD_CMD_CTL_WIDTH_Msk 0x30000UL
|
||||
#define SMIF_DEVICE_RD_CMD_CTL_PRESENT_Pos 31UL
|
||||
#define SMIF_DEVICE_RD_CMD_CTL_PRESENT_Msk 0x80000000UL
|
||||
/* SMIF_DEVICE.RD_ADDR_CTL */
|
||||
#define SMIF_DEVICE_RD_ADDR_CTL_WIDTH_Pos 16UL
|
||||
#define SMIF_DEVICE_RD_ADDR_CTL_WIDTH_Msk 0x30000UL
|
||||
/* SMIF_DEVICE.RD_MODE_CTL */
|
||||
#define SMIF_DEVICE_RD_MODE_CTL_CODE_Pos 0UL
|
||||
#define SMIF_DEVICE_RD_MODE_CTL_CODE_Msk 0xFFUL
|
||||
#define SMIF_DEVICE_RD_MODE_CTL_WIDTH_Pos 16UL
|
||||
#define SMIF_DEVICE_RD_MODE_CTL_WIDTH_Msk 0x30000UL
|
||||
#define SMIF_DEVICE_RD_MODE_CTL_PRESENT_Pos 31UL
|
||||
#define SMIF_DEVICE_RD_MODE_CTL_PRESENT_Msk 0x80000000UL
|
||||
/* SMIF_DEVICE.RD_DUMMY_CTL */
|
||||
#define SMIF_DEVICE_RD_DUMMY_CTL_SIZE5_Pos 0UL
|
||||
#define SMIF_DEVICE_RD_DUMMY_CTL_SIZE5_Msk 0x1FUL
|
||||
#define SMIF_DEVICE_RD_DUMMY_CTL_PRESENT_Pos 31UL
|
||||
#define SMIF_DEVICE_RD_DUMMY_CTL_PRESENT_Msk 0x80000000UL
|
||||
/* SMIF_DEVICE.RD_DATA_CTL */
|
||||
#define SMIF_DEVICE_RD_DATA_CTL_WIDTH_Pos 16UL
|
||||
#define SMIF_DEVICE_RD_DATA_CTL_WIDTH_Msk 0x30000UL
|
||||
/* SMIF_DEVICE.WR_CMD_CTL */
|
||||
#define SMIF_DEVICE_WR_CMD_CTL_CODE_Pos 0UL
|
||||
#define SMIF_DEVICE_WR_CMD_CTL_CODE_Msk 0xFFUL
|
||||
#define SMIF_DEVICE_WR_CMD_CTL_WIDTH_Pos 16UL
|
||||
#define SMIF_DEVICE_WR_CMD_CTL_WIDTH_Msk 0x30000UL
|
||||
#define SMIF_DEVICE_WR_CMD_CTL_PRESENT_Pos 31UL
|
||||
#define SMIF_DEVICE_WR_CMD_CTL_PRESENT_Msk 0x80000000UL
|
||||
/* SMIF_DEVICE.WR_ADDR_CTL */
|
||||
#define SMIF_DEVICE_WR_ADDR_CTL_WIDTH_Pos 16UL
|
||||
#define SMIF_DEVICE_WR_ADDR_CTL_WIDTH_Msk 0x30000UL
|
||||
/* SMIF_DEVICE.WR_MODE_CTL */
|
||||
#define SMIF_DEVICE_WR_MODE_CTL_CODE_Pos 0UL
|
||||
#define SMIF_DEVICE_WR_MODE_CTL_CODE_Msk 0xFFUL
|
||||
#define SMIF_DEVICE_WR_MODE_CTL_WIDTH_Pos 16UL
|
||||
#define SMIF_DEVICE_WR_MODE_CTL_WIDTH_Msk 0x30000UL
|
||||
#define SMIF_DEVICE_WR_MODE_CTL_PRESENT_Pos 31UL
|
||||
#define SMIF_DEVICE_WR_MODE_CTL_PRESENT_Msk 0x80000000UL
|
||||
/* SMIF_DEVICE.WR_DUMMY_CTL */
|
||||
#define SMIF_DEVICE_WR_DUMMY_CTL_SIZE5_Pos 0UL
|
||||
#define SMIF_DEVICE_WR_DUMMY_CTL_SIZE5_Msk 0x1FUL
|
||||
#define SMIF_DEVICE_WR_DUMMY_CTL_PRESENT_Pos 31UL
|
||||
#define SMIF_DEVICE_WR_DUMMY_CTL_PRESENT_Msk 0x80000000UL
|
||||
/* SMIF_DEVICE.WR_DATA_CTL */
|
||||
#define SMIF_DEVICE_WR_DATA_CTL_WIDTH_Pos 16UL
|
||||
#define SMIF_DEVICE_WR_DATA_CTL_WIDTH_Msk 0x30000UL
|
||||
|
||||
|
||||
/* SMIF.CTL */
|
||||
#define SMIF_CTL_XIP_MODE_Pos 0UL
|
||||
#define SMIF_CTL_XIP_MODE_Msk 0x1UL
|
||||
#define SMIF_CTL_CLOCK_IF_RX_SEL_Pos 12UL
|
||||
#define SMIF_CTL_CLOCK_IF_RX_SEL_Msk 0x3000UL
|
||||
#define SMIF_CTL_DESELECT_DELAY_Pos 16UL
|
||||
#define SMIF_CTL_DESELECT_DELAY_Msk 0x70000UL
|
||||
#define SMIF_CTL_BLOCK_Pos 24UL
|
||||
#define SMIF_CTL_BLOCK_Msk 0x1000000UL
|
||||
#define SMIF_CTL_ENABLED_Pos 31UL
|
||||
#define SMIF_CTL_ENABLED_Msk 0x80000000UL
|
||||
/* SMIF.STATUS */
|
||||
#define SMIF_STATUS_BUSY_Pos 31UL
|
||||
#define SMIF_STATUS_BUSY_Msk 0x80000000UL
|
||||
/* SMIF.TX_CMD_FIFO_STATUS */
|
||||
#define SMIF_TX_CMD_FIFO_STATUS_USED3_Pos 0UL
|
||||
#define SMIF_TX_CMD_FIFO_STATUS_USED3_Msk 0x7UL
|
||||
/* SMIF.TX_CMD_FIFO_WR */
|
||||
#define SMIF_TX_CMD_FIFO_WR_DATA20_Pos 0UL
|
||||
#define SMIF_TX_CMD_FIFO_WR_DATA20_Msk 0xFFFFFUL
|
||||
/* SMIF.TX_DATA_FIFO_CTL */
|
||||
#define SMIF_TX_DATA_FIFO_CTL_TRIGGER_LEVEL_Pos 0UL
|
||||
#define SMIF_TX_DATA_FIFO_CTL_TRIGGER_LEVEL_Msk 0x7UL
|
||||
/* SMIF.TX_DATA_FIFO_STATUS */
|
||||
#define SMIF_TX_DATA_FIFO_STATUS_USED4_Pos 0UL
|
||||
#define SMIF_TX_DATA_FIFO_STATUS_USED4_Msk 0xFUL
|
||||
/* SMIF.TX_DATA_FIFO_WR1 */
|
||||
#define SMIF_TX_DATA_FIFO_WR1_DATA0_Pos 0UL
|
||||
#define SMIF_TX_DATA_FIFO_WR1_DATA0_Msk 0xFFUL
|
||||
/* SMIF.TX_DATA_FIFO_WR2 */
|
||||
#define SMIF_TX_DATA_FIFO_WR2_DATA0_Pos 0UL
|
||||
#define SMIF_TX_DATA_FIFO_WR2_DATA0_Msk 0xFFUL
|
||||
#define SMIF_TX_DATA_FIFO_WR2_DATA1_Pos 8UL
|
||||
#define SMIF_TX_DATA_FIFO_WR2_DATA1_Msk 0xFF00UL
|
||||
/* SMIF.TX_DATA_FIFO_WR4 */
|
||||
#define SMIF_TX_DATA_FIFO_WR4_DATA0_Pos 0UL
|
||||
#define SMIF_TX_DATA_FIFO_WR4_DATA0_Msk 0xFFUL
|
||||
#define SMIF_TX_DATA_FIFO_WR4_DATA1_Pos 8UL
|
||||
#define SMIF_TX_DATA_FIFO_WR4_DATA1_Msk 0xFF00UL
|
||||
#define SMIF_TX_DATA_FIFO_WR4_DATA2_Pos 16UL
|
||||
#define SMIF_TX_DATA_FIFO_WR4_DATA2_Msk 0xFF0000UL
|
||||
#define SMIF_TX_DATA_FIFO_WR4_DATA3_Pos 24UL
|
||||
#define SMIF_TX_DATA_FIFO_WR4_DATA3_Msk 0xFF000000UL
|
||||
/* SMIF.RX_DATA_FIFO_CTL */
|
||||
#define SMIF_RX_DATA_FIFO_CTL_TRIGGER_LEVEL_Pos 0UL
|
||||
#define SMIF_RX_DATA_FIFO_CTL_TRIGGER_LEVEL_Msk 0x7UL
|
||||
/* SMIF.RX_DATA_FIFO_STATUS */
|
||||
#define SMIF_RX_DATA_FIFO_STATUS_USED4_Pos 0UL
|
||||
#define SMIF_RX_DATA_FIFO_STATUS_USED4_Msk 0xFUL
|
||||
/* SMIF.RX_DATA_FIFO_RD1 */
|
||||
#define SMIF_RX_DATA_FIFO_RD1_DATA0_Pos 0UL
|
||||
#define SMIF_RX_DATA_FIFO_RD1_DATA0_Msk 0xFFUL
|
||||
/* SMIF.RX_DATA_FIFO_RD2 */
|
||||
#define SMIF_RX_DATA_FIFO_RD2_DATA0_Pos 0UL
|
||||
#define SMIF_RX_DATA_FIFO_RD2_DATA0_Msk 0xFFUL
|
||||
#define SMIF_RX_DATA_FIFO_RD2_DATA1_Pos 8UL
|
||||
#define SMIF_RX_DATA_FIFO_RD2_DATA1_Msk 0xFF00UL
|
||||
/* SMIF.RX_DATA_FIFO_RD4 */
|
||||
#define SMIF_RX_DATA_FIFO_RD4_DATA0_Pos 0UL
|
||||
#define SMIF_RX_DATA_FIFO_RD4_DATA0_Msk 0xFFUL
|
||||
#define SMIF_RX_DATA_FIFO_RD4_DATA1_Pos 8UL
|
||||
#define SMIF_RX_DATA_FIFO_RD4_DATA1_Msk 0xFF00UL
|
||||
#define SMIF_RX_DATA_FIFO_RD4_DATA2_Pos 16UL
|
||||
#define SMIF_RX_DATA_FIFO_RD4_DATA2_Msk 0xFF0000UL
|
||||
#define SMIF_RX_DATA_FIFO_RD4_DATA3_Pos 24UL
|
||||
#define SMIF_RX_DATA_FIFO_RD4_DATA3_Msk 0xFF000000UL
|
||||
/* SMIF.RX_DATA_FIFO_RD1_SILENT */
|
||||
#define SMIF_RX_DATA_FIFO_RD1_SILENT_DATA0_Pos 0UL
|
||||
#define SMIF_RX_DATA_FIFO_RD1_SILENT_DATA0_Msk 0xFFUL
|
||||
/* SMIF.SLOW_CA_CTL */
|
||||
#define SMIF_SLOW_CA_CTL_WAY_Pos 16UL
|
||||
#define SMIF_SLOW_CA_CTL_WAY_Msk 0x30000UL
|
||||
#define SMIF_SLOW_CA_CTL_SET_ADDR_Pos 24UL
|
||||
#define SMIF_SLOW_CA_CTL_SET_ADDR_Msk 0x3000000UL
|
||||
#define SMIF_SLOW_CA_CTL_PREF_EN_Pos 30UL
|
||||
#define SMIF_SLOW_CA_CTL_PREF_EN_Msk 0x40000000UL
|
||||
#define SMIF_SLOW_CA_CTL_ENABLED_Pos 31UL
|
||||
#define SMIF_SLOW_CA_CTL_ENABLED_Msk 0x80000000UL
|
||||
/* SMIF.SLOW_CA_CMD */
|
||||
#define SMIF_SLOW_CA_CMD_INV_Pos 0UL
|
||||
#define SMIF_SLOW_CA_CMD_INV_Msk 0x1UL
|
||||
/* SMIF.FAST_CA_CTL */
|
||||
#define SMIF_FAST_CA_CTL_WAY_Pos 16UL
|
||||
#define SMIF_FAST_CA_CTL_WAY_Msk 0x30000UL
|
||||
#define SMIF_FAST_CA_CTL_SET_ADDR_Pos 24UL
|
||||
#define SMIF_FAST_CA_CTL_SET_ADDR_Msk 0x3000000UL
|
||||
#define SMIF_FAST_CA_CTL_PREF_EN_Pos 30UL
|
||||
#define SMIF_FAST_CA_CTL_PREF_EN_Msk 0x40000000UL
|
||||
#define SMIF_FAST_CA_CTL_ENABLED_Pos 31UL
|
||||
#define SMIF_FAST_CA_CTL_ENABLED_Msk 0x80000000UL
|
||||
/* SMIF.FAST_CA_CMD */
|
||||
#define SMIF_FAST_CA_CMD_INV_Pos 0UL
|
||||
#define SMIF_FAST_CA_CMD_INV_Msk 0x1UL
|
||||
/* SMIF.CRYPTO_CMD */
|
||||
#define SMIF_CRYPTO_CMD_START_Pos 0UL
|
||||
#define SMIF_CRYPTO_CMD_START_Msk 0x1UL
|
||||
/* SMIF.CRYPTO_INPUT0 */
|
||||
#define SMIF_CRYPTO_INPUT0_INPUT_Pos 0UL
|
||||
#define SMIF_CRYPTO_INPUT0_INPUT_Msk 0xFFFFFFFFUL
|
||||
/* SMIF.CRYPTO_INPUT1 */
|
||||
#define SMIF_CRYPTO_INPUT1_INPUT_Pos 0UL
|
||||
#define SMIF_CRYPTO_INPUT1_INPUT_Msk 0xFFFFFFFFUL
|
||||
/* SMIF.CRYPTO_INPUT2 */
|
||||
#define SMIF_CRYPTO_INPUT2_INPUT_Pos 0UL
|
||||
#define SMIF_CRYPTO_INPUT2_INPUT_Msk 0xFFFFFFFFUL
|
||||
/* SMIF.CRYPTO_INPUT3 */
|
||||
#define SMIF_CRYPTO_INPUT3_INPUT_Pos 0UL
|
||||
#define SMIF_CRYPTO_INPUT3_INPUT_Msk 0xFFFFFFFFUL
|
||||
/* SMIF.CRYPTO_KEY0 */
|
||||
#define SMIF_CRYPTO_KEY0_KEY_Pos 0UL
|
||||
#define SMIF_CRYPTO_KEY0_KEY_Msk 0xFFFFFFFFUL
|
||||
/* SMIF.CRYPTO_KEY1 */
|
||||
#define SMIF_CRYPTO_KEY1_KEY_Pos 0UL
|
||||
#define SMIF_CRYPTO_KEY1_KEY_Msk 0xFFFFFFFFUL
|
||||
/* SMIF.CRYPTO_KEY2 */
|
||||
#define SMIF_CRYPTO_KEY2_KEY_Pos 0UL
|
||||
#define SMIF_CRYPTO_KEY2_KEY_Msk 0xFFFFFFFFUL
|
||||
/* SMIF.CRYPTO_KEY3 */
|
||||
#define SMIF_CRYPTO_KEY3_KEY_Pos 0UL
|
||||
#define SMIF_CRYPTO_KEY3_KEY_Msk 0xFFFFFFFFUL
|
||||
/* SMIF.CRYPTO_OUTPUT0 */
|
||||
#define SMIF_CRYPTO_OUTPUT0_OUTPUT_Pos 0UL
|
||||
#define SMIF_CRYPTO_OUTPUT0_OUTPUT_Msk 0xFFFFFFFFUL
|
||||
/* SMIF.CRYPTO_OUTPUT1 */
|
||||
#define SMIF_CRYPTO_OUTPUT1_OUTPUT_Pos 0UL
|
||||
#define SMIF_CRYPTO_OUTPUT1_OUTPUT_Msk 0xFFFFFFFFUL
|
||||
/* SMIF.CRYPTO_OUTPUT2 */
|
||||
#define SMIF_CRYPTO_OUTPUT2_OUTPUT_Pos 0UL
|
||||
#define SMIF_CRYPTO_OUTPUT2_OUTPUT_Msk 0xFFFFFFFFUL
|
||||
/* SMIF.CRYPTO_OUTPUT3 */
|
||||
#define SMIF_CRYPTO_OUTPUT3_OUTPUT_Pos 0UL
|
||||
#define SMIF_CRYPTO_OUTPUT3_OUTPUT_Msk 0xFFFFFFFFUL
|
||||
/* SMIF.INTR */
|
||||
#define SMIF_INTR_TR_TX_REQ_Pos 0UL
|
||||
#define SMIF_INTR_TR_TX_REQ_Msk 0x1UL
|
||||
#define SMIF_INTR_TR_RX_REQ_Pos 1UL
|
||||
#define SMIF_INTR_TR_RX_REQ_Msk 0x2UL
|
||||
#define SMIF_INTR_XIP_ALIGNMENT_ERROR_Pos 2UL
|
||||
#define SMIF_INTR_XIP_ALIGNMENT_ERROR_Msk 0x4UL
|
||||
#define SMIF_INTR_TX_CMD_FIFO_OVERFLOW_Pos 3UL
|
||||
#define SMIF_INTR_TX_CMD_FIFO_OVERFLOW_Msk 0x8UL
|
||||
#define SMIF_INTR_TX_DATA_FIFO_OVERFLOW_Pos 4UL
|
||||
#define SMIF_INTR_TX_DATA_FIFO_OVERFLOW_Msk 0x10UL
|
||||
#define SMIF_INTR_RX_DATA_FIFO_UNDERFLOW_Pos 5UL
|
||||
#define SMIF_INTR_RX_DATA_FIFO_UNDERFLOW_Msk 0x20UL
|
||||
/* SMIF.INTR_SET */
|
||||
#define SMIF_INTR_SET_TR_TX_REQ_Pos 0UL
|
||||
#define SMIF_INTR_SET_TR_TX_REQ_Msk 0x1UL
|
||||
#define SMIF_INTR_SET_TR_RX_REQ_Pos 1UL
|
||||
#define SMIF_INTR_SET_TR_RX_REQ_Msk 0x2UL
|
||||
#define SMIF_INTR_SET_XIP_ALIGNMENT_ERROR_Pos 2UL
|
||||
#define SMIF_INTR_SET_XIP_ALIGNMENT_ERROR_Msk 0x4UL
|
||||
#define SMIF_INTR_SET_TX_CMD_FIFO_OVERFLOW_Pos 3UL
|
||||
#define SMIF_INTR_SET_TX_CMD_FIFO_OVERFLOW_Msk 0x8UL
|
||||
#define SMIF_INTR_SET_TX_DATA_FIFO_OVERFLOW_Pos 4UL
|
||||
#define SMIF_INTR_SET_TX_DATA_FIFO_OVERFLOW_Msk 0x10UL
|
||||
#define SMIF_INTR_SET_RX_DATA_FIFO_UNDERFLOW_Pos 5UL
|
||||
#define SMIF_INTR_SET_RX_DATA_FIFO_UNDERFLOW_Msk 0x20UL
|
||||
/* SMIF.INTR_MASK */
|
||||
#define SMIF_INTR_MASK_TR_TX_REQ_Pos 0UL
|
||||
#define SMIF_INTR_MASK_TR_TX_REQ_Msk 0x1UL
|
||||
#define SMIF_INTR_MASK_TR_RX_REQ_Pos 1UL
|
||||
#define SMIF_INTR_MASK_TR_RX_REQ_Msk 0x2UL
|
||||
#define SMIF_INTR_MASK_XIP_ALIGNMENT_ERROR_Pos 2UL
|
||||
#define SMIF_INTR_MASK_XIP_ALIGNMENT_ERROR_Msk 0x4UL
|
||||
#define SMIF_INTR_MASK_TX_CMD_FIFO_OVERFLOW_Pos 3UL
|
||||
#define SMIF_INTR_MASK_TX_CMD_FIFO_OVERFLOW_Msk 0x8UL
|
||||
#define SMIF_INTR_MASK_TX_DATA_FIFO_OVERFLOW_Pos 4UL
|
||||
#define SMIF_INTR_MASK_TX_DATA_FIFO_OVERFLOW_Msk 0x10UL
|
||||
#define SMIF_INTR_MASK_RX_DATA_FIFO_UNDERFLOW_Pos 5UL
|
||||
#define SMIF_INTR_MASK_RX_DATA_FIFO_UNDERFLOW_Msk 0x20UL
|
||||
/* SMIF.INTR_MASKED */
|
||||
#define SMIF_INTR_MASKED_TR_TX_REQ_Pos 0UL
|
||||
#define SMIF_INTR_MASKED_TR_TX_REQ_Msk 0x1UL
|
||||
#define SMIF_INTR_MASKED_TR_RX_REQ_Pos 1UL
|
||||
#define SMIF_INTR_MASKED_TR_RX_REQ_Msk 0x2UL
|
||||
#define SMIF_INTR_MASKED_XIP_ALIGNMENT_ERROR_Pos 2UL
|
||||
#define SMIF_INTR_MASKED_XIP_ALIGNMENT_ERROR_Msk 0x4UL
|
||||
#define SMIF_INTR_MASKED_TX_CMD_FIFO_OVERFLOW_Pos 3UL
|
||||
#define SMIF_INTR_MASKED_TX_CMD_FIFO_OVERFLOW_Msk 0x8UL
|
||||
#define SMIF_INTR_MASKED_TX_DATA_FIFO_OVERFLOW_Pos 4UL
|
||||
#define SMIF_INTR_MASKED_TX_DATA_FIFO_OVERFLOW_Msk 0x10UL
|
||||
#define SMIF_INTR_MASKED_RX_DATA_FIFO_UNDERFLOW_Pos 5UL
|
||||
#define SMIF_INTR_MASKED_RX_DATA_FIFO_UNDERFLOW_Msk 0x20UL
|
||||
|
||||
|
||||
#endif /* _CYIP_SMIF_H_ */
|
||||
|
||||
|
||||
/* [] END OF FILE */
|
||||
|
|
@ -1,602 +0,0 @@
|
|||
/***************************************************************************//**
|
||||
* \file cyip_srss.h
|
||||
*
|
||||
* \brief
|
||||
* SRSS IP definitions
|
||||
*
|
||||
* \note
|
||||
* Generator version: 1.3.0.1146
|
||||
* Database revision: rev#1050929
|
||||
*
|
||||
********************************************************************************
|
||||
* \copyright
|
||||
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
|
||||
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _CYIP_SRSS_H_
|
||||
#define _CYIP_SRSS_H_
|
||||
|
||||
#include "cyip_headers.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* SRSS
|
||||
*******************************************************************************/
|
||||
|
||||
#define MCWDT_STRUCT_SECTION_SIZE 0x00000040UL
|
||||
#define SRSS_SECTION_SIZE 0x00010000UL
|
||||
|
||||
/**
|
||||
* \brief Multi-Counter Watchdog Timer (MCWDT_STRUCT)
|
||||
*/
|
||||
typedef struct {
|
||||
__IM uint32_t RESERVED;
|
||||
__IOM uint32_t MCWDT_CNTLOW; /*!< 0x00000004 Multi-Counter Watchdog Sub-counters 0/1 */
|
||||
__IOM uint32_t MCWDT_CNTHIGH; /*!< 0x00000008 Multi-Counter Watchdog Sub-counter 2 */
|
||||
__IOM uint32_t MCWDT_MATCH; /*!< 0x0000000C Multi-Counter Watchdog Counter Match Register */
|
||||
__IOM uint32_t MCWDT_CONFIG; /*!< 0x00000010 Multi-Counter Watchdog Counter Configuration */
|
||||
__IOM uint32_t MCWDT_CTL; /*!< 0x00000014 Multi-Counter Watchdog Counter Control */
|
||||
__IOM uint32_t MCWDT_INTR; /*!< 0x00000018 Multi-Counter Watchdog Counter Interrupt Register */
|
||||
__IOM uint32_t MCWDT_INTR_SET; /*!< 0x0000001C Multi-Counter Watchdog Counter Interrupt Set Register */
|
||||
__IOM uint32_t MCWDT_INTR_MASK; /*!< 0x00000020 Multi-Counter Watchdog Counter Interrupt Mask Register */
|
||||
__IM uint32_t MCWDT_INTR_MASKED; /*!< 0x00000024 Multi-Counter Watchdog Counter Interrupt Masked Register */
|
||||
__IOM uint32_t MCWDT_LOCK; /*!< 0x00000028 Multi-Counter Watchdog Counter Lock Register */
|
||||
__IM uint32_t RESERVED1[5];
|
||||
} MCWDT_STRUCT_V1_Type; /*!< Size = 64 (0x40) */
|
||||
|
||||
/**
|
||||
* \brief SRSS Core Registers (SRSS)
|
||||
*/
|
||||
typedef struct {
|
||||
__IOM uint32_t PWR_CTL; /*!< 0x00000000 Power Mode Control */
|
||||
__IOM uint32_t PWR_HIBERNATE; /*!< 0x00000004 HIBERNATE Mode Register */
|
||||
__IOM uint32_t PWR_LVD_CTL; /*!< 0x00000008 Low Voltage Detector (LVD) Configuration Register */
|
||||
__IM uint32_t RESERVED[2];
|
||||
__IOM uint32_t PWR_BUCK_CTL; /*!< 0x00000014 Buck Control Register */
|
||||
__IOM uint32_t PWR_BUCK_CTL2; /*!< 0x00000018 Buck Control Register 2 */
|
||||
__IM uint32_t PWR_LVD_STATUS; /*!< 0x0000001C Low Voltage Detector (LVD) Status Register */
|
||||
__IM uint32_t RESERVED1[24];
|
||||
__IOM uint32_t PWR_HIB_DATA[16]; /*!< 0x00000080 HIBERNATE Data Register */
|
||||
__IM uint32_t RESERVED2[48];
|
||||
__IOM uint32_t WDT_CTL; /*!< 0x00000180 Watchdog Counter Control Register */
|
||||
__IOM uint32_t WDT_CNT; /*!< 0x00000184 Watchdog Counter Count Register */
|
||||
__IOM uint32_t WDT_MATCH; /*!< 0x00000188 Watchdog Counter Match Register */
|
||||
__IM uint32_t RESERVED3[29];
|
||||
MCWDT_STRUCT_V1_Type MCWDT_STRUCT[4]; /*!< 0x00000200 Multi-Counter Watchdog Timer */
|
||||
__IOM uint32_t CLK_DSI_SELECT[16]; /*!< 0x00000300 Clock DSI Select Register */
|
||||
__IOM uint32_t CLK_PATH_SELECT[16]; /*!< 0x00000340 Clock Path Select Register */
|
||||
__IOM uint32_t CLK_ROOT_SELECT[16]; /*!< 0x00000380 Clock Root Select Register */
|
||||
__IM uint32_t RESERVED4[80];
|
||||
__IOM uint32_t CLK_SELECT; /*!< 0x00000500 Clock selection register */
|
||||
__IOM uint32_t CLK_TIMER_CTL; /*!< 0x00000504 Timer Clock Control Register */
|
||||
__IM uint32_t RESERVED5;
|
||||
__IOM uint32_t CLK_ILO_CONFIG; /*!< 0x0000050C ILO Configuration */
|
||||
__IOM uint32_t CLK_IMO_CONFIG; /*!< 0x00000510 IMO Configuration */
|
||||
__IOM uint32_t CLK_OUTPUT_FAST; /*!< 0x00000514 Fast Clock Output Select Register */
|
||||
__IOM uint32_t CLK_OUTPUT_SLOW; /*!< 0x00000518 Slow Clock Output Select Register */
|
||||
__IOM uint32_t CLK_CAL_CNT1; /*!< 0x0000051C Clock Calibration Counter 1 */
|
||||
__IM uint32_t CLK_CAL_CNT2; /*!< 0x00000520 Clock Calibration Counter 2 */
|
||||
__IM uint32_t RESERVED6[2];
|
||||
__IOM uint32_t CLK_ECO_CONFIG; /*!< 0x0000052C ECO Configuration Register */
|
||||
__IM uint32_t CLK_ECO_STATUS; /*!< 0x00000530 ECO Status Register */
|
||||
__IM uint32_t RESERVED7[2];
|
||||
__IOM uint32_t CLK_PILO_CONFIG; /*!< 0x0000053C Precision ILO Configuration Register */
|
||||
__IM uint32_t RESERVED8[16];
|
||||
__IOM uint32_t CLK_FLL_CONFIG; /*!< 0x00000580 FLL Configuration Register */
|
||||
__IOM uint32_t CLK_FLL_CONFIG2; /*!< 0x00000584 FLL Configuration Register 2 */
|
||||
__IOM uint32_t CLK_FLL_CONFIG3; /*!< 0x00000588 FLL Configuration Register 3 */
|
||||
__IOM uint32_t CLK_FLL_CONFIG4; /*!< 0x0000058C FLL Configuration Register 4 */
|
||||
__IOM uint32_t CLK_FLL_STATUS; /*!< 0x00000590 FLL Status Register */
|
||||
__IM uint32_t RESERVED9[27];
|
||||
__IOM uint32_t CLK_PLL_CONFIG[15]; /*!< 0x00000600 PLL Configuration Register */
|
||||
__IM uint32_t RESERVED10;
|
||||
__IOM uint32_t CLK_PLL_STATUS[15]; /*!< 0x00000640 PLL Status Register */
|
||||
__IM uint32_t RESERVED11[33];
|
||||
__IOM uint32_t SRSS_INTR; /*!< 0x00000700 SRSS Interrupt Register */
|
||||
__IOM uint32_t SRSS_INTR_SET; /*!< 0x00000704 SRSS Interrupt Set Register */
|
||||
__IOM uint32_t SRSS_INTR_MASK; /*!< 0x00000708 SRSS Interrupt Mask Register */
|
||||
__IM uint32_t SRSS_INTR_MASKED; /*!< 0x0000070C SRSS Interrupt Masked Register */
|
||||
__IOM uint32_t SRSS_INTR_CFG; /*!< 0x00000710 SRSS Interrupt Configuration Register */
|
||||
__IM uint32_t RESERVED12[59];
|
||||
__IOM uint32_t RES_CAUSE; /*!< 0x00000800 Reset Cause Observation Register */
|
||||
__IOM uint32_t RES_CAUSE2; /*!< 0x00000804 Reset Cause Observation Register 2 */
|
||||
__IM uint32_t RESERVED13[7614];
|
||||
__IOM uint32_t PWR_TRIM_REF_CTL; /*!< 0x00007F00 Reference Trim Register */
|
||||
__IOM uint32_t PWR_TRIM_BODOVP_CTL; /*!< 0x00007F04 BOD/OVP Trim Register */
|
||||
__IOM uint32_t CLK_TRIM_CCO_CTL; /*!< 0x00007F08 CCO Trim Register */
|
||||
__IOM uint32_t CLK_TRIM_CCO_CTL2; /*!< 0x00007F0C CCO Trim Register 2 */
|
||||
__IM uint32_t RESERVED14[8];
|
||||
__IOM uint32_t PWR_TRIM_WAKE_CTL; /*!< 0x00007F30 Wakeup Trim Register */
|
||||
__IM uint32_t RESERVED15[8183];
|
||||
__IOM uint32_t PWR_TRIM_LVD_CTL; /*!< 0x0000FF10 LVD Trim Register */
|
||||
__IM uint32_t RESERVED16;
|
||||
__IOM uint32_t CLK_TRIM_ILO_CTL; /*!< 0x0000FF18 ILO Trim Register */
|
||||
__IOM uint32_t PWR_TRIM_PWRSYS_CTL; /*!< 0x0000FF1C Power System Trim Register */
|
||||
__IOM uint32_t CLK_TRIM_ECO_CTL; /*!< 0x0000FF20 ECO Trim Register */
|
||||
__IOM uint32_t CLK_TRIM_PILO_CTL; /*!< 0x0000FF24 PILO Trim Register */
|
||||
__IOM uint32_t CLK_TRIM_PILO_CTL2; /*!< 0x0000FF28 PILO Trim Register 2 */
|
||||
__IOM uint32_t CLK_TRIM_PILO_CTL3; /*!< 0x0000FF2C PILO Trim Register 3 */
|
||||
} SRSS_V1_Type; /*!< Size = 65328 (0xFF30) */
|
||||
|
||||
|
||||
/* MCWDT_STRUCT.MCWDT_CNTLOW */
|
||||
#define MCWDT_STRUCT_MCWDT_CNTLOW_WDT_CTR0_Pos 0UL
|
||||
#define MCWDT_STRUCT_MCWDT_CNTLOW_WDT_CTR0_Msk 0xFFFFUL
|
||||
#define MCWDT_STRUCT_MCWDT_CNTLOW_WDT_CTR1_Pos 16UL
|
||||
#define MCWDT_STRUCT_MCWDT_CNTLOW_WDT_CTR1_Msk 0xFFFF0000UL
|
||||
/* MCWDT_STRUCT.MCWDT_CNTHIGH */
|
||||
#define MCWDT_STRUCT_MCWDT_CNTHIGH_WDT_CTR2_Pos 0UL
|
||||
#define MCWDT_STRUCT_MCWDT_CNTHIGH_WDT_CTR2_Msk 0xFFFFFFFFUL
|
||||
/* MCWDT_STRUCT.MCWDT_MATCH */
|
||||
#define MCWDT_STRUCT_MCWDT_MATCH_WDT_MATCH0_Pos 0UL
|
||||
#define MCWDT_STRUCT_MCWDT_MATCH_WDT_MATCH0_Msk 0xFFFFUL
|
||||
#define MCWDT_STRUCT_MCWDT_MATCH_WDT_MATCH1_Pos 16UL
|
||||
#define MCWDT_STRUCT_MCWDT_MATCH_WDT_MATCH1_Msk 0xFFFF0000UL
|
||||
/* MCWDT_STRUCT.MCWDT_CONFIG */
|
||||
#define MCWDT_STRUCT_MCWDT_CONFIG_WDT_MODE0_Pos 0UL
|
||||
#define MCWDT_STRUCT_MCWDT_CONFIG_WDT_MODE0_Msk 0x3UL
|
||||
#define MCWDT_STRUCT_MCWDT_CONFIG_WDT_CLEAR0_Pos 2UL
|
||||
#define MCWDT_STRUCT_MCWDT_CONFIG_WDT_CLEAR0_Msk 0x4UL
|
||||
#define MCWDT_STRUCT_MCWDT_CONFIG_WDT_CASCADE0_1_Pos 3UL
|
||||
#define MCWDT_STRUCT_MCWDT_CONFIG_WDT_CASCADE0_1_Msk 0x8UL
|
||||
#define MCWDT_STRUCT_MCWDT_CONFIG_WDT_MODE1_Pos 8UL
|
||||
#define MCWDT_STRUCT_MCWDT_CONFIG_WDT_MODE1_Msk 0x300UL
|
||||
#define MCWDT_STRUCT_MCWDT_CONFIG_WDT_CLEAR1_Pos 10UL
|
||||
#define MCWDT_STRUCT_MCWDT_CONFIG_WDT_CLEAR1_Msk 0x400UL
|
||||
#define MCWDT_STRUCT_MCWDT_CONFIG_WDT_CASCADE1_2_Pos 11UL
|
||||
#define MCWDT_STRUCT_MCWDT_CONFIG_WDT_CASCADE1_2_Msk 0x800UL
|
||||
#define MCWDT_STRUCT_MCWDT_CONFIG_WDT_MODE2_Pos 16UL
|
||||
#define MCWDT_STRUCT_MCWDT_CONFIG_WDT_MODE2_Msk 0x10000UL
|
||||
#define MCWDT_STRUCT_MCWDT_CONFIG_WDT_BITS2_Pos 24UL
|
||||
#define MCWDT_STRUCT_MCWDT_CONFIG_WDT_BITS2_Msk 0x1F000000UL
|
||||
/* MCWDT_STRUCT.MCWDT_CTL */
|
||||
#define MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLE0_Pos 0UL
|
||||
#define MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLE0_Msk 0x1UL
|
||||
#define MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLED0_Pos 1UL
|
||||
#define MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLED0_Msk 0x2UL
|
||||
#define MCWDT_STRUCT_MCWDT_CTL_WDT_RESET0_Pos 3UL
|
||||
#define MCWDT_STRUCT_MCWDT_CTL_WDT_RESET0_Msk 0x8UL
|
||||
#define MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLE1_Pos 8UL
|
||||
#define MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLE1_Msk 0x100UL
|
||||
#define MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLED1_Pos 9UL
|
||||
#define MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLED1_Msk 0x200UL
|
||||
#define MCWDT_STRUCT_MCWDT_CTL_WDT_RESET1_Pos 11UL
|
||||
#define MCWDT_STRUCT_MCWDT_CTL_WDT_RESET1_Msk 0x800UL
|
||||
#define MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLE2_Pos 16UL
|
||||
#define MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLE2_Msk 0x10000UL
|
||||
#define MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLED2_Pos 17UL
|
||||
#define MCWDT_STRUCT_MCWDT_CTL_WDT_ENABLED2_Msk 0x20000UL
|
||||
#define MCWDT_STRUCT_MCWDT_CTL_WDT_RESET2_Pos 19UL
|
||||
#define MCWDT_STRUCT_MCWDT_CTL_WDT_RESET2_Msk 0x80000UL
|
||||
/* MCWDT_STRUCT.MCWDT_INTR */
|
||||
#define MCWDT_STRUCT_MCWDT_INTR_MCWDT_INT0_Pos 0UL
|
||||
#define MCWDT_STRUCT_MCWDT_INTR_MCWDT_INT0_Msk 0x1UL
|
||||
#define MCWDT_STRUCT_MCWDT_INTR_MCWDT_INT1_Pos 1UL
|
||||
#define MCWDT_STRUCT_MCWDT_INTR_MCWDT_INT1_Msk 0x2UL
|
||||
#define MCWDT_STRUCT_MCWDT_INTR_MCWDT_INT2_Pos 2UL
|
||||
#define MCWDT_STRUCT_MCWDT_INTR_MCWDT_INT2_Msk 0x4UL
|
||||
/* MCWDT_STRUCT.MCWDT_INTR_SET */
|
||||
#define MCWDT_STRUCT_MCWDT_INTR_SET_MCWDT_INT0_Pos 0UL
|
||||
#define MCWDT_STRUCT_MCWDT_INTR_SET_MCWDT_INT0_Msk 0x1UL
|
||||
#define MCWDT_STRUCT_MCWDT_INTR_SET_MCWDT_INT1_Pos 1UL
|
||||
#define MCWDT_STRUCT_MCWDT_INTR_SET_MCWDT_INT1_Msk 0x2UL
|
||||
#define MCWDT_STRUCT_MCWDT_INTR_SET_MCWDT_INT2_Pos 2UL
|
||||
#define MCWDT_STRUCT_MCWDT_INTR_SET_MCWDT_INT2_Msk 0x4UL
|
||||
/* MCWDT_STRUCT.MCWDT_INTR_MASK */
|
||||
#define MCWDT_STRUCT_MCWDT_INTR_MASK_MCWDT_INT0_Pos 0UL
|
||||
#define MCWDT_STRUCT_MCWDT_INTR_MASK_MCWDT_INT0_Msk 0x1UL
|
||||
#define MCWDT_STRUCT_MCWDT_INTR_MASK_MCWDT_INT1_Pos 1UL
|
||||
#define MCWDT_STRUCT_MCWDT_INTR_MASK_MCWDT_INT1_Msk 0x2UL
|
||||
#define MCWDT_STRUCT_MCWDT_INTR_MASK_MCWDT_INT2_Pos 2UL
|
||||
#define MCWDT_STRUCT_MCWDT_INTR_MASK_MCWDT_INT2_Msk 0x4UL
|
||||
/* MCWDT_STRUCT.MCWDT_INTR_MASKED */
|
||||
#define MCWDT_STRUCT_MCWDT_INTR_MASKED_MCWDT_INT0_Pos 0UL
|
||||
#define MCWDT_STRUCT_MCWDT_INTR_MASKED_MCWDT_INT0_Msk 0x1UL
|
||||
#define MCWDT_STRUCT_MCWDT_INTR_MASKED_MCWDT_INT1_Pos 1UL
|
||||
#define MCWDT_STRUCT_MCWDT_INTR_MASKED_MCWDT_INT1_Msk 0x2UL
|
||||
#define MCWDT_STRUCT_MCWDT_INTR_MASKED_MCWDT_INT2_Pos 2UL
|
||||
#define MCWDT_STRUCT_MCWDT_INTR_MASKED_MCWDT_INT2_Msk 0x4UL
|
||||
/* MCWDT_STRUCT.MCWDT_LOCK */
|
||||
#define MCWDT_STRUCT_MCWDT_LOCK_MCWDT_LOCK_Pos 30UL
|
||||
#define MCWDT_STRUCT_MCWDT_LOCK_MCWDT_LOCK_Msk 0xC0000000UL
|
||||
|
||||
|
||||
/* SRSS.PWR_CTL */
|
||||
#define SRSS_PWR_CTL_POWER_MODE_Pos 0UL
|
||||
#define SRSS_PWR_CTL_POWER_MODE_Msk 0x3UL
|
||||
#define SRSS_PWR_CTL_DEBUG_SESSION_Pos 4UL
|
||||
#define SRSS_PWR_CTL_DEBUG_SESSION_Msk 0x10UL
|
||||
#define SRSS_PWR_CTL_LPM_READY_Pos 5UL
|
||||
#define SRSS_PWR_CTL_LPM_READY_Msk 0x20UL
|
||||
#define SRSS_PWR_CTL_IREF_LPMODE_Pos 18UL
|
||||
#define SRSS_PWR_CTL_IREF_LPMODE_Msk 0x40000UL
|
||||
#define SRSS_PWR_CTL_VREFBUF_OK_Pos 19UL
|
||||
#define SRSS_PWR_CTL_VREFBUF_OK_Msk 0x80000UL
|
||||
#define SRSS_PWR_CTL_DPSLP_REG_DIS_Pos 20UL
|
||||
#define SRSS_PWR_CTL_DPSLP_REG_DIS_Msk 0x100000UL
|
||||
#define SRSS_PWR_CTL_RET_REG_DIS_Pos 21UL
|
||||
#define SRSS_PWR_CTL_RET_REG_DIS_Msk 0x200000UL
|
||||
#define SRSS_PWR_CTL_NWELL_REG_DIS_Pos 22UL
|
||||
#define SRSS_PWR_CTL_NWELL_REG_DIS_Msk 0x400000UL
|
||||
#define SRSS_PWR_CTL_LINREG_DIS_Pos 23UL
|
||||
#define SRSS_PWR_CTL_LINREG_DIS_Msk 0x800000UL
|
||||
#define SRSS_PWR_CTL_LINREG_LPMODE_Pos 24UL
|
||||
#define SRSS_PWR_CTL_LINREG_LPMODE_Msk 0x1000000UL
|
||||
#define SRSS_PWR_CTL_PORBOD_LPMODE_Pos 25UL
|
||||
#define SRSS_PWR_CTL_PORBOD_LPMODE_Msk 0x2000000UL
|
||||
#define SRSS_PWR_CTL_BGREF_LPMODE_Pos 26UL
|
||||
#define SRSS_PWR_CTL_BGREF_LPMODE_Msk 0x4000000UL
|
||||
#define SRSS_PWR_CTL_PLL_LS_BYPASS_Pos 27UL
|
||||
#define SRSS_PWR_CTL_PLL_LS_BYPASS_Msk 0x8000000UL
|
||||
#define SRSS_PWR_CTL_VREFBUF_LPMODE_Pos 28UL
|
||||
#define SRSS_PWR_CTL_VREFBUF_LPMODE_Msk 0x10000000UL
|
||||
#define SRSS_PWR_CTL_VREFBUF_DIS_Pos 29UL
|
||||
#define SRSS_PWR_CTL_VREFBUF_DIS_Msk 0x20000000UL
|
||||
#define SRSS_PWR_CTL_ACT_REF_DIS_Pos 30UL
|
||||
#define SRSS_PWR_CTL_ACT_REF_DIS_Msk 0x40000000UL
|
||||
#define SRSS_PWR_CTL_ACT_REF_OK_Pos 31UL
|
||||
#define SRSS_PWR_CTL_ACT_REF_OK_Msk 0x80000000UL
|
||||
/* SRSS.PWR_HIBERNATE */
|
||||
#define SRSS_PWR_HIBERNATE_TOKEN_Pos 0UL
|
||||
#define SRSS_PWR_HIBERNATE_TOKEN_Msk 0xFFUL
|
||||
#define SRSS_PWR_HIBERNATE_UNLOCK_Pos 8UL
|
||||
#define SRSS_PWR_HIBERNATE_UNLOCK_Msk 0xFF00UL
|
||||
#define SRSS_PWR_HIBERNATE_FREEZE_Pos 17UL
|
||||
#define SRSS_PWR_HIBERNATE_FREEZE_Msk 0x20000UL
|
||||
#define SRSS_PWR_HIBERNATE_MASK_HIBALARM_Pos 18UL
|
||||
#define SRSS_PWR_HIBERNATE_MASK_HIBALARM_Msk 0x40000UL
|
||||
#define SRSS_PWR_HIBERNATE_MASK_HIBWDT_Pos 19UL
|
||||
#define SRSS_PWR_HIBERNATE_MASK_HIBWDT_Msk 0x80000UL
|
||||
#define SRSS_PWR_HIBERNATE_POLARITY_HIBPIN_Pos 20UL
|
||||
#define SRSS_PWR_HIBERNATE_POLARITY_HIBPIN_Msk 0xF00000UL
|
||||
#define SRSS_PWR_HIBERNATE_MASK_HIBPIN_Pos 24UL
|
||||
#define SRSS_PWR_HIBERNATE_MASK_HIBPIN_Msk 0xF000000UL
|
||||
#define SRSS_PWR_HIBERNATE_HIBERNATE_DISABLE_Pos 30UL
|
||||
#define SRSS_PWR_HIBERNATE_HIBERNATE_DISABLE_Msk 0x40000000UL
|
||||
#define SRSS_PWR_HIBERNATE_HIBERNATE_Pos 31UL
|
||||
#define SRSS_PWR_HIBERNATE_HIBERNATE_Msk 0x80000000UL
|
||||
/* SRSS.PWR_LVD_CTL */
|
||||
#define SRSS_PWR_LVD_CTL_HVLVD1_TRIPSEL_Pos 0UL
|
||||
#define SRSS_PWR_LVD_CTL_HVLVD1_TRIPSEL_Msk 0xFUL
|
||||
#define SRSS_PWR_LVD_CTL_HVLVD1_SRCSEL_Pos 4UL
|
||||
#define SRSS_PWR_LVD_CTL_HVLVD1_SRCSEL_Msk 0x70UL
|
||||
#define SRSS_PWR_LVD_CTL_HVLVD1_EN_Pos 7UL
|
||||
#define SRSS_PWR_LVD_CTL_HVLVD1_EN_Msk 0x80UL
|
||||
/* SRSS.PWR_BUCK_CTL */
|
||||
#define SRSS_PWR_BUCK_CTL_BUCK_OUT1_SEL_Pos 0UL
|
||||
#define SRSS_PWR_BUCK_CTL_BUCK_OUT1_SEL_Msk 0x7UL
|
||||
#define SRSS_PWR_BUCK_CTL_BUCK_EN_Pos 30UL
|
||||
#define SRSS_PWR_BUCK_CTL_BUCK_EN_Msk 0x40000000UL
|
||||
#define SRSS_PWR_BUCK_CTL_BUCK_OUT1_EN_Pos 31UL
|
||||
#define SRSS_PWR_BUCK_CTL_BUCK_OUT1_EN_Msk 0x80000000UL
|
||||
/* SRSS.PWR_BUCK_CTL2 */
|
||||
#define SRSS_PWR_BUCK_CTL2_BUCK_OUT2_SEL_Pos 0UL
|
||||
#define SRSS_PWR_BUCK_CTL2_BUCK_OUT2_SEL_Msk 0x7UL
|
||||
#define SRSS_PWR_BUCK_CTL2_BUCK_OUT2_HW_SEL_Pos 30UL
|
||||
#define SRSS_PWR_BUCK_CTL2_BUCK_OUT2_HW_SEL_Msk 0x40000000UL
|
||||
#define SRSS_PWR_BUCK_CTL2_BUCK_OUT2_EN_Pos 31UL
|
||||
#define SRSS_PWR_BUCK_CTL2_BUCK_OUT2_EN_Msk 0x80000000UL
|
||||
/* SRSS.PWR_LVD_STATUS */
|
||||
#define SRSS_PWR_LVD_STATUS_HVLVD1_OK_Pos 0UL
|
||||
#define SRSS_PWR_LVD_STATUS_HVLVD1_OK_Msk 0x1UL
|
||||
/* SRSS.PWR_HIB_DATA */
|
||||
#define SRSS_PWR_HIB_DATA_HIB_DATA_Pos 0UL
|
||||
#define SRSS_PWR_HIB_DATA_HIB_DATA_Msk 0xFFFFFFFFUL
|
||||
/* SRSS.WDT_CTL */
|
||||
#define SRSS_WDT_CTL_WDT_EN_Pos 0UL
|
||||
#define SRSS_WDT_CTL_WDT_EN_Msk 0x1UL
|
||||
#define SRSS_WDT_CTL_WDT_LOCK_Pos 30UL
|
||||
#define SRSS_WDT_CTL_WDT_LOCK_Msk 0xC0000000UL
|
||||
/* SRSS.WDT_CNT */
|
||||
#define SRSS_WDT_CNT_COUNTER_Pos 0UL
|
||||
#define SRSS_WDT_CNT_COUNTER_Msk 0xFFFFUL
|
||||
/* SRSS.WDT_MATCH */
|
||||
#define SRSS_WDT_MATCH_MATCH_Pos 0UL
|
||||
#define SRSS_WDT_MATCH_MATCH_Msk 0xFFFFUL
|
||||
#define SRSS_WDT_MATCH_IGNORE_BITS_Pos 16UL
|
||||
#define SRSS_WDT_MATCH_IGNORE_BITS_Msk 0xF0000UL
|
||||
/* SRSS.CLK_DSI_SELECT */
|
||||
#define SRSS_CLK_DSI_SELECT_DSI_MUX_Pos 0UL
|
||||
#define SRSS_CLK_DSI_SELECT_DSI_MUX_Msk 0x1FUL
|
||||
/* SRSS.CLK_PATH_SELECT */
|
||||
#define SRSS_CLK_PATH_SELECT_PATH_MUX_Pos 0UL
|
||||
#define SRSS_CLK_PATH_SELECT_PATH_MUX_Msk 0x7UL
|
||||
/* SRSS.CLK_ROOT_SELECT */
|
||||
#define SRSS_CLK_ROOT_SELECT_ROOT_MUX_Pos 0UL
|
||||
#define SRSS_CLK_ROOT_SELECT_ROOT_MUX_Msk 0xFUL
|
||||
#define SRSS_CLK_ROOT_SELECT_ROOT_DIV_Pos 4UL
|
||||
#define SRSS_CLK_ROOT_SELECT_ROOT_DIV_Msk 0x30UL
|
||||
#define SRSS_CLK_ROOT_SELECT_ENABLE_Pos 31UL
|
||||
#define SRSS_CLK_ROOT_SELECT_ENABLE_Msk 0x80000000UL
|
||||
/* SRSS.CLK_SELECT */
|
||||
#define SRSS_CLK_SELECT_LFCLK_SEL_Pos 0UL
|
||||
#define SRSS_CLK_SELECT_LFCLK_SEL_Msk 0x3UL
|
||||
#define SRSS_CLK_SELECT_PUMP_SEL_Pos 8UL
|
||||
#define SRSS_CLK_SELECT_PUMP_SEL_Msk 0xF00UL
|
||||
#define SRSS_CLK_SELECT_PUMP_DIV_Pos 12UL
|
||||
#define SRSS_CLK_SELECT_PUMP_DIV_Msk 0x7000UL
|
||||
#define SRSS_CLK_SELECT_PUMP_ENABLE_Pos 15UL
|
||||
#define SRSS_CLK_SELECT_PUMP_ENABLE_Msk 0x8000UL
|
||||
/* SRSS.CLK_TIMER_CTL */
|
||||
#define SRSS_CLK_TIMER_CTL_TIMER_SEL_Pos 0UL
|
||||
#define SRSS_CLK_TIMER_CTL_TIMER_SEL_Msk 0x1UL
|
||||
#define SRSS_CLK_TIMER_CTL_TIMER_HF0_DIV_Pos 8UL
|
||||
#define SRSS_CLK_TIMER_CTL_TIMER_HF0_DIV_Msk 0x300UL
|
||||
#define SRSS_CLK_TIMER_CTL_TIMER_DIV_Pos 16UL
|
||||
#define SRSS_CLK_TIMER_CTL_TIMER_DIV_Msk 0xFF0000UL
|
||||
#define SRSS_CLK_TIMER_CTL_ENABLE_Pos 31UL
|
||||
#define SRSS_CLK_TIMER_CTL_ENABLE_Msk 0x80000000UL
|
||||
/* SRSS.CLK_ILO_CONFIG */
|
||||
#define SRSS_CLK_ILO_CONFIG_ILO_BACKUP_Pos 0UL
|
||||
#define SRSS_CLK_ILO_CONFIG_ILO_BACKUP_Msk 0x1UL
|
||||
#define SRSS_CLK_ILO_CONFIG_ENABLE_Pos 31UL
|
||||
#define SRSS_CLK_ILO_CONFIG_ENABLE_Msk 0x80000000UL
|
||||
/* SRSS.CLK_IMO_CONFIG */
|
||||
#define SRSS_CLK_IMO_CONFIG_ENABLE_Pos 31UL
|
||||
#define SRSS_CLK_IMO_CONFIG_ENABLE_Msk 0x80000000UL
|
||||
/* SRSS.CLK_OUTPUT_FAST */
|
||||
#define SRSS_CLK_OUTPUT_FAST_FAST_SEL0_Pos 0UL
|
||||
#define SRSS_CLK_OUTPUT_FAST_FAST_SEL0_Msk 0xFUL
|
||||
#define SRSS_CLK_OUTPUT_FAST_PATH_SEL0_Pos 4UL
|
||||
#define SRSS_CLK_OUTPUT_FAST_PATH_SEL0_Msk 0xF0UL
|
||||
#define SRSS_CLK_OUTPUT_FAST_HFCLK_SEL0_Pos 8UL
|
||||
#define SRSS_CLK_OUTPUT_FAST_HFCLK_SEL0_Msk 0xF00UL
|
||||
#define SRSS_CLK_OUTPUT_FAST_FAST_SEL1_Pos 16UL
|
||||
#define SRSS_CLK_OUTPUT_FAST_FAST_SEL1_Msk 0xF0000UL
|
||||
#define SRSS_CLK_OUTPUT_FAST_PATH_SEL1_Pos 20UL
|
||||
#define SRSS_CLK_OUTPUT_FAST_PATH_SEL1_Msk 0xF00000UL
|
||||
#define SRSS_CLK_OUTPUT_FAST_HFCLK_SEL1_Pos 24UL
|
||||
#define SRSS_CLK_OUTPUT_FAST_HFCLK_SEL1_Msk 0xF000000UL
|
||||
/* SRSS.CLK_OUTPUT_SLOW */
|
||||
#define SRSS_CLK_OUTPUT_SLOW_SLOW_SEL0_Pos 0UL
|
||||
#define SRSS_CLK_OUTPUT_SLOW_SLOW_SEL0_Msk 0xFUL
|
||||
#define SRSS_CLK_OUTPUT_SLOW_SLOW_SEL1_Pos 4UL
|
||||
#define SRSS_CLK_OUTPUT_SLOW_SLOW_SEL1_Msk 0xF0UL
|
||||
/* SRSS.CLK_CAL_CNT1 */
|
||||
#define SRSS_CLK_CAL_CNT1_CAL_COUNTER1_Pos 0UL
|
||||
#define SRSS_CLK_CAL_CNT1_CAL_COUNTER1_Msk 0xFFFFFFUL
|
||||
#define SRSS_CLK_CAL_CNT1_CAL_COUNTER_DONE_Pos 31UL
|
||||
#define SRSS_CLK_CAL_CNT1_CAL_COUNTER_DONE_Msk 0x80000000UL
|
||||
/* SRSS.CLK_CAL_CNT2 */
|
||||
#define SRSS_CLK_CAL_CNT2_CAL_COUNTER2_Pos 0UL
|
||||
#define SRSS_CLK_CAL_CNT2_CAL_COUNTER2_Msk 0xFFFFFFUL
|
||||
/* SRSS.CLK_ECO_CONFIG */
|
||||
#define SRSS_CLK_ECO_CONFIG_AGC_EN_Pos 1UL
|
||||
#define SRSS_CLK_ECO_CONFIG_AGC_EN_Msk 0x2UL
|
||||
#define SRSS_CLK_ECO_CONFIG_ECO_EN_Pos 31UL
|
||||
#define SRSS_CLK_ECO_CONFIG_ECO_EN_Msk 0x80000000UL
|
||||
/* SRSS.CLK_ECO_STATUS */
|
||||
#define SRSS_CLK_ECO_STATUS_ECO_OK_Pos 0UL
|
||||
#define SRSS_CLK_ECO_STATUS_ECO_OK_Msk 0x1UL
|
||||
#define SRSS_CLK_ECO_STATUS_ECO_READY_Pos 1UL
|
||||
#define SRSS_CLK_ECO_STATUS_ECO_READY_Msk 0x2UL
|
||||
/* SRSS.CLK_PILO_CONFIG */
|
||||
#define SRSS_CLK_PILO_CONFIG_PILO_FFREQ_Pos 0UL
|
||||
#define SRSS_CLK_PILO_CONFIG_PILO_FFREQ_Msk 0x3FFUL
|
||||
#define SRSS_CLK_PILO_CONFIG_PILO_CLK_EN_Pos 29UL
|
||||
#define SRSS_CLK_PILO_CONFIG_PILO_CLK_EN_Msk 0x20000000UL
|
||||
#define SRSS_CLK_PILO_CONFIG_PILO_RESET_N_Pos 30UL
|
||||
#define SRSS_CLK_PILO_CONFIG_PILO_RESET_N_Msk 0x40000000UL
|
||||
#define SRSS_CLK_PILO_CONFIG_PILO_EN_Pos 31UL
|
||||
#define SRSS_CLK_PILO_CONFIG_PILO_EN_Msk 0x80000000UL
|
||||
/* SRSS.CLK_FLL_CONFIG */
|
||||
#define SRSS_CLK_FLL_CONFIG_FLL_MULT_Pos 0UL
|
||||
#define SRSS_CLK_FLL_CONFIG_FLL_MULT_Msk 0x3FFFFUL
|
||||
#define SRSS_CLK_FLL_CONFIG_FLL_OUTPUT_DIV_Pos 24UL
|
||||
#define SRSS_CLK_FLL_CONFIG_FLL_OUTPUT_DIV_Msk 0x1000000UL
|
||||
#define SRSS_CLK_FLL_CONFIG_FLL_ENABLE_Pos 31UL
|
||||
#define SRSS_CLK_FLL_CONFIG_FLL_ENABLE_Msk 0x80000000UL
|
||||
/* SRSS.CLK_FLL_CONFIG2 */
|
||||
#define SRSS_CLK_FLL_CONFIG2_FLL_REF_DIV_Pos 0UL
|
||||
#define SRSS_CLK_FLL_CONFIG2_FLL_REF_DIV_Msk 0x1FFFUL
|
||||
#define SRSS_CLK_FLL_CONFIG2_LOCK_TOL_Pos 16UL
|
||||
#define SRSS_CLK_FLL_CONFIG2_LOCK_TOL_Msk 0x1FF0000UL
|
||||
/* SRSS.CLK_FLL_CONFIG3 */
|
||||
#define SRSS_CLK_FLL_CONFIG3_FLL_LF_IGAIN_Pos 0UL
|
||||
#define SRSS_CLK_FLL_CONFIG3_FLL_LF_IGAIN_Msk 0xFUL
|
||||
#define SRSS_CLK_FLL_CONFIG3_FLL_LF_PGAIN_Pos 4UL
|
||||
#define SRSS_CLK_FLL_CONFIG3_FLL_LF_PGAIN_Msk 0xF0UL
|
||||
#define SRSS_CLK_FLL_CONFIG3_SETTLING_COUNT_Pos 8UL
|
||||
#define SRSS_CLK_FLL_CONFIG3_SETTLING_COUNT_Msk 0x1FFF00UL
|
||||
#define SRSS_CLK_FLL_CONFIG3_BYPASS_SEL_Pos 28UL
|
||||
#define SRSS_CLK_FLL_CONFIG3_BYPASS_SEL_Msk 0x30000000UL
|
||||
/* SRSS.CLK_FLL_CONFIG4 */
|
||||
#define SRSS_CLK_FLL_CONFIG4_CCO_LIMIT_Pos 0UL
|
||||
#define SRSS_CLK_FLL_CONFIG4_CCO_LIMIT_Msk 0xFFUL
|
||||
#define SRSS_CLK_FLL_CONFIG4_CCO_RANGE_Pos 8UL
|
||||
#define SRSS_CLK_FLL_CONFIG4_CCO_RANGE_Msk 0x700UL
|
||||
#define SRSS_CLK_FLL_CONFIG4_CCO_FREQ_Pos 16UL
|
||||
#define SRSS_CLK_FLL_CONFIG4_CCO_FREQ_Msk 0x1FF0000UL
|
||||
#define SRSS_CLK_FLL_CONFIG4_CCO_HW_UPDATE_DIS_Pos 30UL
|
||||
#define SRSS_CLK_FLL_CONFIG4_CCO_HW_UPDATE_DIS_Msk 0x40000000UL
|
||||
#define SRSS_CLK_FLL_CONFIG4_CCO_ENABLE_Pos 31UL
|
||||
#define SRSS_CLK_FLL_CONFIG4_CCO_ENABLE_Msk 0x80000000UL
|
||||
/* SRSS.CLK_FLL_STATUS */
|
||||
#define SRSS_CLK_FLL_STATUS_LOCKED_Pos 0UL
|
||||
#define SRSS_CLK_FLL_STATUS_LOCKED_Msk 0x1UL
|
||||
#define SRSS_CLK_FLL_STATUS_UNLOCK_OCCURRED_Pos 1UL
|
||||
#define SRSS_CLK_FLL_STATUS_UNLOCK_OCCURRED_Msk 0x2UL
|
||||
#define SRSS_CLK_FLL_STATUS_CCO_READY_Pos 2UL
|
||||
#define SRSS_CLK_FLL_STATUS_CCO_READY_Msk 0x4UL
|
||||
/* SRSS.CLK_PLL_CONFIG */
|
||||
#define SRSS_CLK_PLL_CONFIG_FEEDBACK_DIV_Pos 0UL
|
||||
#define SRSS_CLK_PLL_CONFIG_FEEDBACK_DIV_Msk 0x7FUL
|
||||
#define SRSS_CLK_PLL_CONFIG_REFERENCE_DIV_Pos 8UL
|
||||
#define SRSS_CLK_PLL_CONFIG_REFERENCE_DIV_Msk 0x1F00UL
|
||||
#define SRSS_CLK_PLL_CONFIG_OUTPUT_DIV_Pos 16UL
|
||||
#define SRSS_CLK_PLL_CONFIG_OUTPUT_DIV_Msk 0x1F0000UL
|
||||
#define SRSS_CLK_PLL_CONFIG_PLL_LF_MODE_Pos 27UL
|
||||
#define SRSS_CLK_PLL_CONFIG_PLL_LF_MODE_Msk 0x8000000UL
|
||||
#define SRSS_CLK_PLL_CONFIG_BYPASS_SEL_Pos 28UL
|
||||
#define SRSS_CLK_PLL_CONFIG_BYPASS_SEL_Msk 0x30000000UL
|
||||
#define SRSS_CLK_PLL_CONFIG_ENABLE_Pos 31UL
|
||||
#define SRSS_CLK_PLL_CONFIG_ENABLE_Msk 0x80000000UL
|
||||
/* SRSS.CLK_PLL_STATUS */
|
||||
#define SRSS_CLK_PLL_STATUS_LOCKED_Pos 0UL
|
||||
#define SRSS_CLK_PLL_STATUS_LOCKED_Msk 0x1UL
|
||||
#define SRSS_CLK_PLL_STATUS_UNLOCK_OCCURRED_Pos 1UL
|
||||
#define SRSS_CLK_PLL_STATUS_UNLOCK_OCCURRED_Msk 0x2UL
|
||||
/* SRSS.SRSS_INTR */
|
||||
#define SRSS_SRSS_INTR_WDT_MATCH_Pos 0UL
|
||||
#define SRSS_SRSS_INTR_WDT_MATCH_Msk 0x1UL
|
||||
#define SRSS_SRSS_INTR_HVLVD1_Pos 1UL
|
||||
#define SRSS_SRSS_INTR_HVLVD1_Msk 0x2UL
|
||||
#define SRSS_SRSS_INTR_CLK_CAL_Pos 5UL
|
||||
#define SRSS_SRSS_INTR_CLK_CAL_Msk 0x20UL
|
||||
/* SRSS.SRSS_INTR_SET */
|
||||
#define SRSS_SRSS_INTR_SET_WDT_MATCH_Pos 0UL
|
||||
#define SRSS_SRSS_INTR_SET_WDT_MATCH_Msk 0x1UL
|
||||
#define SRSS_SRSS_INTR_SET_HVLVD1_Pos 1UL
|
||||
#define SRSS_SRSS_INTR_SET_HVLVD1_Msk 0x2UL
|
||||
#define SRSS_SRSS_INTR_SET_CLK_CAL_Pos 5UL
|
||||
#define SRSS_SRSS_INTR_SET_CLK_CAL_Msk 0x20UL
|
||||
/* SRSS.SRSS_INTR_MASK */
|
||||
#define SRSS_SRSS_INTR_MASK_WDT_MATCH_Pos 0UL
|
||||
#define SRSS_SRSS_INTR_MASK_WDT_MATCH_Msk 0x1UL
|
||||
#define SRSS_SRSS_INTR_MASK_HVLVD1_Pos 1UL
|
||||
#define SRSS_SRSS_INTR_MASK_HVLVD1_Msk 0x2UL
|
||||
#define SRSS_SRSS_INTR_MASK_CLK_CAL_Pos 5UL
|
||||
#define SRSS_SRSS_INTR_MASK_CLK_CAL_Msk 0x20UL
|
||||
/* SRSS.SRSS_INTR_MASKED */
|
||||
#define SRSS_SRSS_INTR_MASKED_WDT_MATCH_Pos 0UL
|
||||
#define SRSS_SRSS_INTR_MASKED_WDT_MATCH_Msk 0x1UL
|
||||
#define SRSS_SRSS_INTR_MASKED_HVLVD1_Pos 1UL
|
||||
#define SRSS_SRSS_INTR_MASKED_HVLVD1_Msk 0x2UL
|
||||
#define SRSS_SRSS_INTR_MASKED_CLK_CAL_Pos 5UL
|
||||
#define SRSS_SRSS_INTR_MASKED_CLK_CAL_Msk 0x20UL
|
||||
/* SRSS.SRSS_INTR_CFG */
|
||||
#define SRSS_SRSS_INTR_CFG_HVLVD1_EDGE_SEL_Pos 0UL
|
||||
#define SRSS_SRSS_INTR_CFG_HVLVD1_EDGE_SEL_Msk 0x3UL
|
||||
/* SRSS.RES_CAUSE */
|
||||
#define SRSS_RES_CAUSE_RESET_WDT_Pos 0UL
|
||||
#define SRSS_RES_CAUSE_RESET_WDT_Msk 0x1UL
|
||||
#define SRSS_RES_CAUSE_RESET_ACT_FAULT_Pos 1UL
|
||||
#define SRSS_RES_CAUSE_RESET_ACT_FAULT_Msk 0x2UL
|
||||
#define SRSS_RES_CAUSE_RESET_DPSLP_FAULT_Pos 2UL
|
||||
#define SRSS_RES_CAUSE_RESET_DPSLP_FAULT_Msk 0x4UL
|
||||
#define SRSS_RES_CAUSE_RESET_CSV_WCO_LOSS_Pos 3UL
|
||||
#define SRSS_RES_CAUSE_RESET_CSV_WCO_LOSS_Msk 0x8UL
|
||||
#define SRSS_RES_CAUSE_RESET_SOFT_Pos 4UL
|
||||
#define SRSS_RES_CAUSE_RESET_SOFT_Msk 0x10UL
|
||||
#define SRSS_RES_CAUSE_RESET_MCWDT0_Pos 5UL
|
||||
#define SRSS_RES_CAUSE_RESET_MCWDT0_Msk 0x20UL
|
||||
#define SRSS_RES_CAUSE_RESET_MCWDT1_Pos 6UL
|
||||
#define SRSS_RES_CAUSE_RESET_MCWDT1_Msk 0x40UL
|
||||
#define SRSS_RES_CAUSE_RESET_MCWDT2_Pos 7UL
|
||||
#define SRSS_RES_CAUSE_RESET_MCWDT2_Msk 0x80UL
|
||||
#define SRSS_RES_CAUSE_RESET_MCWDT3_Pos 8UL
|
||||
#define SRSS_RES_CAUSE_RESET_MCWDT3_Msk 0x100UL
|
||||
/* SRSS.RES_CAUSE2 */
|
||||
#define SRSS_RES_CAUSE2_RESET_CSV_HF_LOSS_Pos 0UL
|
||||
#define SRSS_RES_CAUSE2_RESET_CSV_HF_LOSS_Msk 0xFFFFUL
|
||||
#define SRSS_RES_CAUSE2_RESET_CSV_HF_FREQ_Pos 16UL
|
||||
#define SRSS_RES_CAUSE2_RESET_CSV_HF_FREQ_Msk 0xFFFF0000UL
|
||||
/* SRSS.PWR_TRIM_REF_CTL */
|
||||
#define SRSS_PWR_TRIM_REF_CTL_ACT_REF_TCTRIM_Pos 0UL
|
||||
#define SRSS_PWR_TRIM_REF_CTL_ACT_REF_TCTRIM_Msk 0xFUL
|
||||
#define SRSS_PWR_TRIM_REF_CTL_ACT_REF_ITRIM_Pos 4UL
|
||||
#define SRSS_PWR_TRIM_REF_CTL_ACT_REF_ITRIM_Msk 0xF0UL
|
||||
#define SRSS_PWR_TRIM_REF_CTL_ACT_REF_ABSTRIM_Pos 8UL
|
||||
#define SRSS_PWR_TRIM_REF_CTL_ACT_REF_ABSTRIM_Msk 0x1F00UL
|
||||
#define SRSS_PWR_TRIM_REF_CTL_ACT_REF_IBOOST_Pos 14UL
|
||||
#define SRSS_PWR_TRIM_REF_CTL_ACT_REF_IBOOST_Msk 0x4000UL
|
||||
#define SRSS_PWR_TRIM_REF_CTL_DPSLP_REF_TCTRIM_Pos 16UL
|
||||
#define SRSS_PWR_TRIM_REF_CTL_DPSLP_REF_TCTRIM_Msk 0xF0000UL
|
||||
#define SRSS_PWR_TRIM_REF_CTL_DPSLP_REF_ABSTRIM_Pos 20UL
|
||||
#define SRSS_PWR_TRIM_REF_CTL_DPSLP_REF_ABSTRIM_Msk 0x1F00000UL
|
||||
#define SRSS_PWR_TRIM_REF_CTL_DPSLP_REF_ITRIM_Pos 28UL
|
||||
#define SRSS_PWR_TRIM_REF_CTL_DPSLP_REF_ITRIM_Msk 0xF0000000UL
|
||||
/* SRSS.PWR_TRIM_BODOVP_CTL */
|
||||
#define SRSS_PWR_TRIM_BODOVP_CTL_HVPORBOD_TRIPSEL_Pos 0UL
|
||||
#define SRSS_PWR_TRIM_BODOVP_CTL_HVPORBOD_TRIPSEL_Msk 0x7UL
|
||||
#define SRSS_PWR_TRIM_BODOVP_CTL_HVPORBOD_OFSTRIM_Pos 4UL
|
||||
#define SRSS_PWR_TRIM_BODOVP_CTL_HVPORBOD_OFSTRIM_Msk 0x70UL
|
||||
#define SRSS_PWR_TRIM_BODOVP_CTL_HVPORBOD_ITRIM_Pos 7UL
|
||||
#define SRSS_PWR_TRIM_BODOVP_CTL_HVPORBOD_ITRIM_Msk 0x380UL
|
||||
#define SRSS_PWR_TRIM_BODOVP_CTL_LVPORBOD_TRIPSEL_Pos 10UL
|
||||
#define SRSS_PWR_TRIM_BODOVP_CTL_LVPORBOD_TRIPSEL_Msk 0x1C00UL
|
||||
#define SRSS_PWR_TRIM_BODOVP_CTL_LVPORBOD_OFSTRIM_Pos 14UL
|
||||
#define SRSS_PWR_TRIM_BODOVP_CTL_LVPORBOD_OFSTRIM_Msk 0x1C000UL
|
||||
#define SRSS_PWR_TRIM_BODOVP_CTL_LVPORBOD_ITRIM_Pos 17UL
|
||||
#define SRSS_PWR_TRIM_BODOVP_CTL_LVPORBOD_ITRIM_Msk 0xE0000UL
|
||||
/* SRSS.CLK_TRIM_CCO_CTL */
|
||||
#define SRSS_CLK_TRIM_CCO_CTL_CCO_RCSTRIM_Pos 0UL
|
||||
#define SRSS_CLK_TRIM_CCO_CTL_CCO_RCSTRIM_Msk 0x3FUL
|
||||
#define SRSS_CLK_TRIM_CCO_CTL_CCO_STABLE_CNT_Pos 24UL
|
||||
#define SRSS_CLK_TRIM_CCO_CTL_CCO_STABLE_CNT_Msk 0x3F000000UL
|
||||
#define SRSS_CLK_TRIM_CCO_CTL_ENABLE_CNT_Pos 31UL
|
||||
#define SRSS_CLK_TRIM_CCO_CTL_ENABLE_CNT_Msk 0x80000000UL
|
||||
/* SRSS.CLK_TRIM_CCO_CTL2 */
|
||||
#define SRSS_CLK_TRIM_CCO_CTL2_CCO_FCTRIM1_Pos 0UL
|
||||
#define SRSS_CLK_TRIM_CCO_CTL2_CCO_FCTRIM1_Msk 0x1FUL
|
||||
#define SRSS_CLK_TRIM_CCO_CTL2_CCO_FCTRIM2_Pos 5UL
|
||||
#define SRSS_CLK_TRIM_CCO_CTL2_CCO_FCTRIM2_Msk 0x3E0UL
|
||||
#define SRSS_CLK_TRIM_CCO_CTL2_CCO_FCTRIM3_Pos 10UL
|
||||
#define SRSS_CLK_TRIM_CCO_CTL2_CCO_FCTRIM3_Msk 0x7C00UL
|
||||
#define SRSS_CLK_TRIM_CCO_CTL2_CCO_FCTRIM4_Pos 15UL
|
||||
#define SRSS_CLK_TRIM_CCO_CTL2_CCO_FCTRIM4_Msk 0xF8000UL
|
||||
#define SRSS_CLK_TRIM_CCO_CTL2_CCO_FCTRIM5_Pos 20UL
|
||||
#define SRSS_CLK_TRIM_CCO_CTL2_CCO_FCTRIM5_Msk 0x1F00000UL
|
||||
/* SRSS.PWR_TRIM_WAKE_CTL */
|
||||
#define SRSS_PWR_TRIM_WAKE_CTL_WAKE_DELAY_Pos 0UL
|
||||
#define SRSS_PWR_TRIM_WAKE_CTL_WAKE_DELAY_Msk 0xFFUL
|
||||
/* SRSS.PWR_TRIM_LVD_CTL */
|
||||
#define SRSS_PWR_TRIM_LVD_CTL_HVLVD1_OFSTRIM_Pos 0UL
|
||||
#define SRSS_PWR_TRIM_LVD_CTL_HVLVD1_OFSTRIM_Msk 0x7UL
|
||||
#define SRSS_PWR_TRIM_LVD_CTL_HVLVD1_ITRIM_Pos 4UL
|
||||
#define SRSS_PWR_TRIM_LVD_CTL_HVLVD1_ITRIM_Msk 0x70UL
|
||||
/* SRSS.CLK_TRIM_ILO_CTL */
|
||||
#define SRSS_CLK_TRIM_ILO_CTL_ILO_FTRIM_Pos 0UL
|
||||
#define SRSS_CLK_TRIM_ILO_CTL_ILO_FTRIM_Msk 0x3FUL
|
||||
/* SRSS.PWR_TRIM_PWRSYS_CTL */
|
||||
#define SRSS_PWR_TRIM_PWRSYS_CTL_ACT_REG_TRIM_Pos 0UL
|
||||
#define SRSS_PWR_TRIM_PWRSYS_CTL_ACT_REG_TRIM_Msk 0x1FUL
|
||||
#define SRSS_PWR_TRIM_PWRSYS_CTL_ACT_REG_BOOST_Pos 30UL
|
||||
#define SRSS_PWR_TRIM_PWRSYS_CTL_ACT_REG_BOOST_Msk 0xC0000000UL
|
||||
/* SRSS.CLK_TRIM_ECO_CTL */
|
||||
#define SRSS_CLK_TRIM_ECO_CTL_WDTRIM_Pos 0UL
|
||||
#define SRSS_CLK_TRIM_ECO_CTL_WDTRIM_Msk 0x7UL
|
||||
#define SRSS_CLK_TRIM_ECO_CTL_ATRIM_Pos 4UL
|
||||
#define SRSS_CLK_TRIM_ECO_CTL_ATRIM_Msk 0xF0UL
|
||||
#define SRSS_CLK_TRIM_ECO_CTL_FTRIM_Pos 8UL
|
||||
#define SRSS_CLK_TRIM_ECO_CTL_FTRIM_Msk 0x300UL
|
||||
#define SRSS_CLK_TRIM_ECO_CTL_RTRIM_Pos 10UL
|
||||
#define SRSS_CLK_TRIM_ECO_CTL_RTRIM_Msk 0xC00UL
|
||||
#define SRSS_CLK_TRIM_ECO_CTL_GTRIM_Pos 12UL
|
||||
#define SRSS_CLK_TRIM_ECO_CTL_GTRIM_Msk 0x3000UL
|
||||
#define SRSS_CLK_TRIM_ECO_CTL_ITRIM_Pos 16UL
|
||||
#define SRSS_CLK_TRIM_ECO_CTL_ITRIM_Msk 0x3F0000UL
|
||||
/* SRSS.CLK_TRIM_PILO_CTL */
|
||||
#define SRSS_CLK_TRIM_PILO_CTL_PILO_CFREQ_Pos 0UL
|
||||
#define SRSS_CLK_TRIM_PILO_CTL_PILO_CFREQ_Msk 0x3FUL
|
||||
#define SRSS_CLK_TRIM_PILO_CTL_PILO_OSC_TRIM_Pos 12UL
|
||||
#define SRSS_CLK_TRIM_PILO_CTL_PILO_OSC_TRIM_Msk 0x7000UL
|
||||
#define SRSS_CLK_TRIM_PILO_CTL_PILO_COMP_TRIM_Pos 16UL
|
||||
#define SRSS_CLK_TRIM_PILO_CTL_PILO_COMP_TRIM_Msk 0x30000UL
|
||||
#define SRSS_CLK_TRIM_PILO_CTL_PILO_NBIAS_TRIM_Pos 18UL
|
||||
#define SRSS_CLK_TRIM_PILO_CTL_PILO_NBIAS_TRIM_Msk 0xC0000UL
|
||||
#define SRSS_CLK_TRIM_PILO_CTL_PILO_RES_TRIM_Pos 20UL
|
||||
#define SRSS_CLK_TRIM_PILO_CTL_PILO_RES_TRIM_Msk 0x1F00000UL
|
||||
#define SRSS_CLK_TRIM_PILO_CTL_PILO_ISLOPE_TRIM_Pos 26UL
|
||||
#define SRSS_CLK_TRIM_PILO_CTL_PILO_ISLOPE_TRIM_Msk 0xC000000UL
|
||||
#define SRSS_CLK_TRIM_PILO_CTL_PILO_VTDIFF_TRIM_Pos 28UL
|
||||
#define SRSS_CLK_TRIM_PILO_CTL_PILO_VTDIFF_TRIM_Msk 0x70000000UL
|
||||
/* SRSS.CLK_TRIM_PILO_CTL2 */
|
||||
#define SRSS_CLK_TRIM_PILO_CTL2_PILO_VREF_TRIM_Pos 0UL
|
||||
#define SRSS_CLK_TRIM_PILO_CTL2_PILO_VREF_TRIM_Msk 0xFFUL
|
||||
#define SRSS_CLK_TRIM_PILO_CTL2_PILO_IREFBM_TRIM_Pos 8UL
|
||||
#define SRSS_CLK_TRIM_PILO_CTL2_PILO_IREFBM_TRIM_Msk 0x1F00UL
|
||||
#define SRSS_CLK_TRIM_PILO_CTL2_PILO_IREF_TRIM_Pos 16UL
|
||||
#define SRSS_CLK_TRIM_PILO_CTL2_PILO_IREF_TRIM_Msk 0xFF0000UL
|
||||
/* SRSS.CLK_TRIM_PILO_CTL3 */
|
||||
#define SRSS_CLK_TRIM_PILO_CTL3_PILO_ENGOPT_Pos 0UL
|
||||
#define SRSS_CLK_TRIM_PILO_CTL3_PILO_ENGOPT_Msk 0xFFFFUL
|
||||
|
||||
|
||||
#endif /* _CYIP_SRSS_H_ */
|
||||
|
||||
|
||||
/* [] END OF FILE */
|
||||
|
|
@ -1,192 +0,0 @@
|
|||
/***************************************************************************//**
|
||||
* \file cyip_tcpwm.h
|
||||
*
|
||||
* \brief
|
||||
* TCPWM IP definitions
|
||||
*
|
||||
* \note
|
||||
* Generator version: 1.3.0.1146
|
||||
* Database revision: rev#1050929
|
||||
*
|
||||
********************************************************************************
|
||||
* \copyright
|
||||
* Copyright 2016-2018, Cypress Semiconductor Corporation. All rights reserved.
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
|
||||
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef _CYIP_TCPWM_H_
|
||||
#define _CYIP_TCPWM_H_
|
||||
|
||||
#include "cyip_headers.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* TCPWM
|
||||
*******************************************************************************/
|
||||
|
||||
#define TCPWM_CNT_SECTION_SIZE 0x00000040UL
|
||||
#define TCPWM_SECTION_SIZE 0x00010000UL
|
||||
|
||||
/**
|
||||
* \brief Timer/Counter/PWM Counter Module (TCPWM_CNT)
|
||||
*/
|
||||
typedef struct {
|
||||
__IOM uint32_t CTRL; /*!< 0x00000000 Counter control register */
|
||||
__IM uint32_t STATUS; /*!< 0x00000004 Counter status register */
|
||||
__IOM uint32_t COUNTER; /*!< 0x00000008 Counter count register */
|
||||
__IOM uint32_t CC; /*!< 0x0000000C Counter compare/capture register */
|
||||
__IOM uint32_t CC_BUFF; /*!< 0x00000010 Counter buffered compare/capture register */
|
||||
__IOM uint32_t PERIOD; /*!< 0x00000014 Counter period register */
|
||||
__IOM uint32_t PERIOD_BUFF; /*!< 0x00000018 Counter buffered period register */
|
||||
__IM uint32_t RESERVED;
|
||||
__IOM uint32_t TR_CTRL0; /*!< 0x00000020 Counter trigger control register 0 */
|
||||
__IOM uint32_t TR_CTRL1; /*!< 0x00000024 Counter trigger control register 1 */
|
||||
__IOM uint32_t TR_CTRL2; /*!< 0x00000028 Counter trigger control register 2 */
|
||||
__IM uint32_t RESERVED1;
|
||||
__IOM uint32_t INTR; /*!< 0x00000030 Interrupt request register */
|
||||
__IOM uint32_t INTR_SET; /*!< 0x00000034 Interrupt set request register */
|
||||
__IOM uint32_t INTR_MASK; /*!< 0x00000038 Interrupt mask register */
|
||||
__IM uint32_t INTR_MASKED; /*!< 0x0000003C Interrupt masked request register */
|
||||
} TCPWM_CNT_V1_Type; /*!< Size = 64 (0x40) */
|
||||
|
||||
/**
|
||||
* \brief Timer/Counter/PWM (TCPWM)
|
||||
*/
|
||||
typedef struct {
|
||||
__IOM uint32_t CTRL; /*!< 0x00000000 TCPWM control register */
|
||||
__IOM uint32_t CTRL_CLR; /*!< 0x00000004 TCPWM control clear register */
|
||||
__IOM uint32_t CTRL_SET; /*!< 0x00000008 TCPWM control set register */
|
||||
__IOM uint32_t CMD_CAPTURE; /*!< 0x0000000C TCPWM capture command register */
|
||||
__IOM uint32_t CMD_RELOAD; /*!< 0x00000010 TCPWM reload command register */
|
||||
__IOM uint32_t CMD_STOP; /*!< 0x00000014 TCPWM stop command register */
|
||||
__IOM uint32_t CMD_START; /*!< 0x00000018 TCPWM start command register */
|
||||
__IM uint32_t INTR_CAUSE; /*!< 0x0000001C TCPWM Counter interrupt cause register */
|
||||
__IM uint32_t RESERVED[56];
|
||||
TCPWM_CNT_V1_Type CNT[32]; /*!< 0x00000100 Timer/Counter/PWM Counter Module */
|
||||
} TCPWM_V1_Type; /*!< Size = 2304 (0x900) */
|
||||
|
||||
|
||||
/* TCPWM_CNT.CTRL */
|
||||
#define TCPWM_CNT_CTRL_AUTO_RELOAD_CC_Pos 0UL
|
||||
#define TCPWM_CNT_CTRL_AUTO_RELOAD_CC_Msk 0x1UL
|
||||
#define TCPWM_CNT_CTRL_AUTO_RELOAD_PERIOD_Pos 1UL
|
||||
#define TCPWM_CNT_CTRL_AUTO_RELOAD_PERIOD_Msk 0x2UL
|
||||
#define TCPWM_CNT_CTRL_PWM_SYNC_KILL_Pos 2UL
|
||||
#define TCPWM_CNT_CTRL_PWM_SYNC_KILL_Msk 0x4UL
|
||||
#define TCPWM_CNT_CTRL_PWM_STOP_ON_KILL_Pos 3UL
|
||||
#define TCPWM_CNT_CTRL_PWM_STOP_ON_KILL_Msk 0x8UL
|
||||
#define TCPWM_CNT_CTRL_GENERIC_Pos 8UL
|
||||
#define TCPWM_CNT_CTRL_GENERIC_Msk 0xFF00UL
|
||||
#define TCPWM_CNT_CTRL_UP_DOWN_MODE_Pos 16UL
|
||||
#define TCPWM_CNT_CTRL_UP_DOWN_MODE_Msk 0x30000UL
|
||||
#define TCPWM_CNT_CTRL_ONE_SHOT_Pos 18UL
|
||||
#define TCPWM_CNT_CTRL_ONE_SHOT_Msk 0x40000UL
|
||||
#define TCPWM_CNT_CTRL_QUADRATURE_MODE_Pos 20UL
|
||||
#define TCPWM_CNT_CTRL_QUADRATURE_MODE_Msk 0x300000UL
|
||||
#define TCPWM_CNT_CTRL_MODE_Pos 24UL
|
||||
#define TCPWM_CNT_CTRL_MODE_Msk 0x7000000UL
|
||||
/* TCPWM_CNT.STATUS */
|
||||
#define TCPWM_CNT_STATUS_DOWN_Pos 0UL
|
||||
#define TCPWM_CNT_STATUS_DOWN_Msk 0x1UL
|
||||
#define TCPWM_CNT_STATUS_GENERIC_Pos 8UL
|
||||
#define TCPWM_CNT_STATUS_GENERIC_Msk 0xFF00UL
|
||||
#define TCPWM_CNT_STATUS_RUNNING_Pos 31UL
|
||||
#define TCPWM_CNT_STATUS_RUNNING_Msk 0x80000000UL
|
||||
/* TCPWM_CNT.COUNTER */
|
||||
#define TCPWM_CNT_COUNTER_COUNTER_Pos 0UL
|
||||
#define TCPWM_CNT_COUNTER_COUNTER_Msk 0xFFFFFFFFUL
|
||||
/* TCPWM_CNT.CC */
|
||||
#define TCPWM_CNT_CC_CC_Pos 0UL
|
||||
#define TCPWM_CNT_CC_CC_Msk 0xFFFFFFFFUL
|
||||
/* TCPWM_CNT.CC_BUFF */
|
||||
#define TCPWM_CNT_CC_BUFF_CC_Pos 0UL
|
||||
#define TCPWM_CNT_CC_BUFF_CC_Msk 0xFFFFFFFFUL
|
||||
/* TCPWM_CNT.PERIOD */
|
||||
#define TCPWM_CNT_PERIOD_PERIOD_Pos 0UL
|
||||
#define TCPWM_CNT_PERIOD_PERIOD_Msk 0xFFFFFFFFUL
|
||||
/* TCPWM_CNT.PERIOD_BUFF */
|
||||
#define TCPWM_CNT_PERIOD_BUFF_PERIOD_Pos 0UL
|
||||
#define TCPWM_CNT_PERIOD_BUFF_PERIOD_Msk 0xFFFFFFFFUL
|
||||
/* TCPWM_CNT.TR_CTRL0 */
|
||||
#define TCPWM_CNT_TR_CTRL0_CAPTURE_SEL_Pos 0UL
|
||||
#define TCPWM_CNT_TR_CTRL0_CAPTURE_SEL_Msk 0xFUL
|
||||
#define TCPWM_CNT_TR_CTRL0_COUNT_SEL_Pos 4UL
|
||||
#define TCPWM_CNT_TR_CTRL0_COUNT_SEL_Msk 0xF0UL
|
||||
#define TCPWM_CNT_TR_CTRL0_RELOAD_SEL_Pos 8UL
|
||||
#define TCPWM_CNT_TR_CTRL0_RELOAD_SEL_Msk 0xF00UL
|
||||
#define TCPWM_CNT_TR_CTRL0_STOP_SEL_Pos 12UL
|
||||
#define TCPWM_CNT_TR_CTRL0_STOP_SEL_Msk 0xF000UL
|
||||
#define TCPWM_CNT_TR_CTRL0_START_SEL_Pos 16UL
|
||||
#define TCPWM_CNT_TR_CTRL0_START_SEL_Msk 0xF0000UL
|
||||
/* TCPWM_CNT.TR_CTRL1 */
|
||||
#define TCPWM_CNT_TR_CTRL1_CAPTURE_EDGE_Pos 0UL
|
||||
#define TCPWM_CNT_TR_CTRL1_CAPTURE_EDGE_Msk 0x3UL
|
||||
#define TCPWM_CNT_TR_CTRL1_COUNT_EDGE_Pos 2UL
|
||||
#define TCPWM_CNT_TR_CTRL1_COUNT_EDGE_Msk 0xCUL
|
||||
#define TCPWM_CNT_TR_CTRL1_RELOAD_EDGE_Pos 4UL
|
||||
#define TCPWM_CNT_TR_CTRL1_RELOAD_EDGE_Msk 0x30UL
|
||||
#define TCPWM_CNT_TR_CTRL1_STOP_EDGE_Pos 6UL
|
||||
#define TCPWM_CNT_TR_CTRL1_STOP_EDGE_Msk 0xC0UL
|
||||
#define TCPWM_CNT_TR_CTRL1_START_EDGE_Pos 8UL
|
||||
#define TCPWM_CNT_TR_CTRL1_START_EDGE_Msk 0x300UL
|
||||
/* TCPWM_CNT.TR_CTRL2 */
|
||||
#define TCPWM_CNT_TR_CTRL2_CC_MATCH_MODE_Pos 0UL
|
||||
#define TCPWM_CNT_TR_CTRL2_CC_MATCH_MODE_Msk 0x3UL
|
||||
#define TCPWM_CNT_TR_CTRL2_OVERFLOW_MODE_Pos 2UL
|
||||
#define TCPWM_CNT_TR_CTRL2_OVERFLOW_MODE_Msk 0xCUL
|
||||
#define TCPWM_CNT_TR_CTRL2_UNDERFLOW_MODE_Pos 4UL
|
||||
#define TCPWM_CNT_TR_CTRL2_UNDERFLOW_MODE_Msk 0x30UL
|
||||
/* TCPWM_CNT.INTR */
|
||||
#define TCPWM_CNT_INTR_TC_Pos 0UL
|
||||
#define TCPWM_CNT_INTR_TC_Msk 0x1UL
|
||||
#define TCPWM_CNT_INTR_CC_MATCH_Pos 1UL
|
||||
#define TCPWM_CNT_INTR_CC_MATCH_Msk 0x2UL
|
||||
/* TCPWM_CNT.INTR_SET */
|
||||
#define TCPWM_CNT_INTR_SET_TC_Pos 0UL
|
||||
#define TCPWM_CNT_INTR_SET_TC_Msk 0x1UL
|
||||
#define TCPWM_CNT_INTR_SET_CC_MATCH_Pos 1UL
|
||||
#define TCPWM_CNT_INTR_SET_CC_MATCH_Msk 0x2UL
|
||||
/* TCPWM_CNT.INTR_MASK */
|
||||
#define TCPWM_CNT_INTR_MASK_TC_Pos 0UL
|
||||
#define TCPWM_CNT_INTR_MASK_TC_Msk 0x1UL
|
||||
#define TCPWM_CNT_INTR_MASK_CC_MATCH_Pos 1UL
|
||||
#define TCPWM_CNT_INTR_MASK_CC_MATCH_Msk 0x2UL
|
||||
/* TCPWM_CNT.INTR_MASKED */
|
||||
#define TCPWM_CNT_INTR_MASKED_TC_Pos 0UL
|
||||
#define TCPWM_CNT_INTR_MASKED_TC_Msk 0x1UL
|
||||
#define TCPWM_CNT_INTR_MASKED_CC_MATCH_Pos 1UL
|
||||
#define TCPWM_CNT_INTR_MASKED_CC_MATCH_Msk 0x2UL
|
||||
|
||||
|
||||
/* TCPWM.CTRL */
|
||||
#define TCPWM_CTRL_COUNTER_ENABLED_Pos 0UL
|
||||
#define TCPWM_CTRL_COUNTER_ENABLED_Msk 0xFFFFFFFFUL
|
||||
/* TCPWM.CTRL_CLR */
|
||||
#define TCPWM_CTRL_CLR_COUNTER_ENABLED_Pos 0UL
|
||||
#define TCPWM_CTRL_CLR_COUNTER_ENABLED_Msk 0xFFFFFFFFUL
|
||||
/* TCPWM.CTRL_SET */
|
||||
#define TCPWM_CTRL_SET_COUNTER_ENABLED_Pos 0UL
|
||||
#define TCPWM_CTRL_SET_COUNTER_ENABLED_Msk 0xFFFFFFFFUL
|
||||
/* TCPWM.CMD_CAPTURE */
|
||||
#define TCPWM_CMD_CAPTURE_COUNTER_CAPTURE_Pos 0UL
|
||||
#define TCPWM_CMD_CAPTURE_COUNTER_CAPTURE_Msk 0xFFFFFFFFUL
|
||||
/* TCPWM.CMD_RELOAD */
|
||||
#define TCPWM_CMD_RELOAD_COUNTER_RELOAD_Pos 0UL
|
||||
#define TCPWM_CMD_RELOAD_COUNTER_RELOAD_Msk 0xFFFFFFFFUL
|
||||
/* TCPWM.CMD_STOP */
|
||||
#define TCPWM_CMD_STOP_COUNTER_STOP_Pos 0UL
|
||||
#define TCPWM_CMD_STOP_COUNTER_STOP_Msk 0xFFFFFFFFUL
|
||||
/* TCPWM.CMD_START */
|
||||
#define TCPWM_CMD_START_COUNTER_START_Pos 0UL
|
||||
#define TCPWM_CMD_START_COUNTER_START_Msk 0xFFFFFFFFUL
|
||||
/* TCPWM.INTR_CAUSE */
|
||||
#define TCPWM_INTR_CAUSE_COUNTER_INT_Pos 0UL
|
||||
#define TCPWM_INTR_CAUSE_COUNTER_INT_Msk 0xFFFFFFFFUL
|
||||
|
||||
|
||||
#endif /* _CYIP_TCPWM_H_ */
|
||||
|
||||
|
||||
/* [] END OF FILE */
|
||||
File diff suppressed because it is too large
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File diff suppressed because it is too large
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