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cc3220sf: Add support for the TI CC3220SF SoC

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The CC3220SF is a replacement for the CC3200 SoC, comprising
a network coprocessor and Cortex-M4 MPU.

This leverages the CC3220 SDK driver peripheral library in ROM,
and some files built from ext/hal/ti/.

Jira: ZEP-1958

Change-Id: I892b212c178e05d84ff1d716dde593ced653ae6d
Signed-off-by: Gil Pitney <gil.pitney@linaro.org>
This commit is contained in:
Gil Pitney 2017-04-18 14:08:56 -07:00 • committed by Kumar Gala
commit c73a1eb806
5 changed files with 71 additions and 4 deletions
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10
arch/arm/soc/ti_simplelink/cc32xx/README
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@ -2,9 +2,17 @@ CC3200 Board and Bootloader info taken from:
* http://www.ti.com.cn/cn/lit/ug/swru367c/swru367c.pdf
* http://www.ti.com/lit/ug/swru369c/swru369c.pdf
Notes:
CC3220 Info taken from:
* http://www.ti.com/lit/ug/swru465/swru465.pdf
Notes for CC3200:
* CC3200 has no integrated flash Memory.
* TI bootloader takes first 16Kb of the 256Kb SRAM, so app must start at
0x20004000. CC3200 Kconfig must set SRAM size to 240Kb or less, since
Zephyr computes TOP_OF_MEMORY (used for stack) based on SRAM_BASE_ADDRESS
+ SRAM_SIZE.
Notes for CC3220SF:
* Text must start at 0x800 offset in flash. The first 0x800 bytes are
reserved for the flash header.
* See CONFIG_TEXT_SECTION_OFFSET.