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dts_fixups: Use DT_ prefix in all defined labels not related to Kconfig

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These changes were obtained by running a script  created by
Ulf Magnusson <Ulf.Magnusson@nordicsemi.no> for the following
specification:

1. Read the contents of all dts_fixup.h files in Zephyr
2. Check the left-hand side of the #define macros (i.e. the X in
   #define X Y)
3. Check if that name is also the name of a Kconfig option
   3.a If it is, then do nothing
   3.b If it is not, then replace CONFIG_ with DT_ or add DT_ if it
       has neither of these two prefixes
4. Replace the use of the changed #define in the code itself
   (.c, .h, .ld)

Additionally, some tweaks had to be added to this script to catch some
of the macros used in the code in a parameterized form, e.g.:
- CONFIG_GPIO_STM32_GPIO##__SUFFIX##_BASE_ADDRESS
- CONFIG_UART_##idx##_TX_PIN
- I2C_SBCON_##_num##_BASE_ADDR
and to prevent adding DT_ prefix to the following symbols:
- FLASH_START
- FLASH_SIZE
- SRAM_START
- SRAM_SIZE
- _ROM_ADDR
- _ROM_SIZE
- _RAM_ADDR
- _RAM_SIZE
which are surprisingly also defined in some dts_fixup.h files.

Finally, some manual corrections had to be done as well:
- name##_IRQ -> DT_##name##_IRQ in uart_stm32.c

Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
This commit is contained in:
Andrzej Głąbek 2018-11-13 15:15:23 +01:00 • committed by Kumar Gala
commit 20202902f2
304 changed files with 5118 additions and 5118 deletions
Download patch file Download diff file Expand all files Collapse all files

4
arch/arm/core/irq_manage.c
View file

@ -108,10 +108,10 @@ void _irq_priority_set(unsigned int irq, unsigned int prio, u32_t flags)
* affecting performance (can still be useful on systems with a * affecting performance (can still be useful on systems with a
* reduced set of priorities, like Cortex-M0/M0+). * reduced set of priorities, like Cortex-M0/M0+).
*/ */
__ASSERT(prio <= ((1 << CONFIG_NUM_IRQ_PRIO_BITS) - 1), __ASSERT(prio <= ((1 << DT_NUM_IRQ_PRIO_BITS) - 1),
"invalid priority %d! values must be less than %d\n", "invalid priority %d! values must be less than %d\n",
prio - _IRQ_PRIO_OFFSET, prio - _IRQ_PRIO_OFFSET,
(1 << CONFIG_NUM_IRQ_PRIO_BITS) - (_IRQ_PRIO_OFFSET)); (1 << DT_NUM_IRQ_PRIO_BITS) - (_IRQ_PRIO_OFFSET));
NVIC_SetPriority((IRQn_Type)irq, prio); NVIC_SetPriority((IRQn_Type)irq, prio);
} }

12
boards/arc/arduino_101_sss/dts_fixup.h
View file

@ -4,10 +4,10 @@
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
#define CONFIG_BMI160_SLAVE DT_SNPS_DESIGNWARE_SPI_80010100_BOSCH_BMI160_1_BASE_ADDRESS #define DT_BMI160_SLAVE DT_SNPS_DESIGNWARE_SPI_80010100_BOSCH_BMI160_1_BASE_ADDRESS
#define CONFIG_BMI160_SPI_PORT_NAME DT_SNPS_DESIGNWARE_SPI_80010100_BOSCH_BMI160_1_BUS_NAME #define DT_BMI160_SPI_PORT_NAME DT_SNPS_DESIGNWARE_SPI_80010100_BOSCH_BMI160_1_BUS_NAME
#define CONFIG_BMI160_GPIO_DEV_NAME DT_SNPS_DESIGNWARE_SPI_80010100_BOSCH_BMI160_1_INT_GPIOS_CONTROLLER #define DT_BMI160_GPIO_DEV_NAME DT_SNPS_DESIGNWARE_SPI_80010100_BOSCH_BMI160_1_INT_GPIOS_CONTROLLER
#define CONFIG_BMI160_GPIO_PIN_NUM DT_SNPS_DESIGNWARE_SPI_80010100_BOSCH_BMI160_1_INT_GPIOS_PIN #define DT_BMI160_GPIO_PIN_NUM DT_SNPS_DESIGNWARE_SPI_80010100_BOSCH_BMI160_1_INT_GPIOS_PIN
#define CONFIG_BMI160_NAME DT_SNPS_DESIGNWARE_SPI_80010100_BOSCH_BMI160_1_LABEL #define DT_BMI160_NAME DT_SNPS_DESIGNWARE_SPI_80010100_BOSCH_BMI160_1_LABEL
#define CONFIG_BMI160_SPI_BUS_FREQ DT_SNPS_DESIGNWARE_SPI_80010100_BOSCH_BMI160_1_SPI_MAX_FREQUENCY #define DT_BMI160_SPI_BUS_FREQ DT_SNPS_DESIGNWARE_SPI_80010100_BOSCH_BMI160_1_SPI_MAX_FREQUENCY

24
boards/arc/em_starterkit/arc_mpu_regions.c
View file

@ -27,18 +27,18 @@ static struct arc_mpu_region mpu_regions[] = {
AUX_MPU_RDP_KW | AUX_MPU_RDP_KR), AUX_MPU_RDP_KW | AUX_MPU_RDP_KR),
#else #else
#if CONFIG_ICCM_SIZE > 0 #if DT_ICCM_SIZE > 0
/* Region ICCM */ /* Region ICCM */
MPU_REGION_ENTRY("ICCM", MPU_REGION_ENTRY("ICCM",
CONFIG_ICCM_BASE_ADDRESS, DT_ICCM_BASE_ADDRESS,
CONFIG_ICCM_SIZE * 1024, DT_ICCM_SIZE * 1024,
REGION_FLASH_ATTR), REGION_FLASH_ATTR),
#endif #endif
#if CONFIG_DCCM_SIZE > 0 #if DT_DCCM_SIZE > 0
/* Region DCCM */ /* Region DCCM */
MPU_REGION_ENTRY("DCCM", MPU_REGION_ENTRY("DCCM",
CONFIG_DCCM_BASE_ADDRESS, DT_DCCM_BASE_ADDRESS,
CONFIG_DCCM_SIZE * 1024, DT_DCCM_SIZE * 1024,
AUX_MPU_RDP_KW | AUX_MPU_RDP_KR), AUX_MPU_RDP_KW | AUX_MPU_RDP_KR),
#endif #endif
#if CONFIG_SRAM_SIZE > 0 #if CONFIG_SRAM_SIZE > 0
@ -58,18 +58,18 @@ static struct arc_mpu_region mpu_regions[] = {
}; };
#else /* CONFIG_USERSPACE */ #else /* CONFIG_USERSPACE */
static struct arc_mpu_region mpu_regions[] = { static struct arc_mpu_region mpu_regions[] = {
#if CONFIG_ICCM_SIZE > 0 #if DT_ICCM_SIZE > 0
/* Region ICCM */ /* Region ICCM */
MPU_REGION_ENTRY("ICCM", MPU_REGION_ENTRY("ICCM",
CONFIG_ICCM_BASE_ADDRESS, DT_ICCM_BASE_ADDRESS,
CONFIG_ICCM_SIZE * 1024, DT_ICCM_SIZE * 1024,
REGION_FLASH_ATTR), REGION_FLASH_ATTR),
#endif #endif
#if CONFIG_DCCM_SIZE > 0 #if DT_DCCM_SIZE > 0
/* Region DCCM */ /* Region DCCM */
MPU_REGION_ENTRY("DCCM", MPU_REGION_ENTRY("DCCM",
CONFIG_DCCM_BASE_ADDRESS, DT_DCCM_BASE_ADDRESS,
CONFIG_DCCM_SIZE * 1024, DT_DCCM_SIZE * 1024,
REGION_RAM_ATTR), REGION_RAM_ATTR),
#endif #endif
#if CONFIG_SRAM_SIZE > 0 #if CONFIG_SRAM_SIZE > 0

24
boards/arc/nsim_em/arc_mpu_regions.c
View file

@ -27,18 +27,18 @@ static struct arc_mpu_region mpu_regions[] = {
AUX_MPU_RDP_KW | AUX_MPU_RDP_KR), AUX_MPU_RDP_KW | AUX_MPU_RDP_KR),
#else #else
#if CONFIG_ICCM_SIZE > 0 #if DT_ICCM_SIZE > 0
/* Region ICCM */ /* Region ICCM */
MPU_REGION_ENTRY("ICCM", MPU_REGION_ENTRY("ICCM",
CONFIG_ICCM_BASE_ADDRESS, DT_ICCM_BASE_ADDRESS,
CONFIG_ICCM_SIZE * 1024, DT_ICCM_SIZE * 1024,
REGION_FLASH_ATTR), REGION_FLASH_ATTR),
#endif #endif
#if CONFIG_DCCM_SIZE > 0 #if DT_DCCM_SIZE > 0
/* Region DCCM */ /* Region DCCM */
MPU_REGION_ENTRY("DCCM", MPU_REGION_ENTRY("DCCM",
CONFIG_DCCM_BASE_ADDRESS, DT_DCCM_BASE_ADDRESS,
CONFIG_DCCM_SIZE * 1024, DT_DCCM_SIZE * 1024,
AUX_MPU_RDP_KW | AUX_MPU_RDP_KR), AUX_MPU_RDP_KW | AUX_MPU_RDP_KR),
#endif #endif
#endif /* ARC_MPU_VER == 3 */ #endif /* ARC_MPU_VER == 3 */
@ -50,18 +50,18 @@ static struct arc_mpu_region mpu_regions[] = {
}; };
#else /* CONFIG_USERSPACE */ #else /* CONFIG_USERSPACE */
static struct arc_mpu_region mpu_regions[] = { static struct arc_mpu_region mpu_regions[] = {
#if CONFIG_ICCM_SIZE > 0 #if DT_ICCM_SIZE > 0
/* Region ICCM */ /* Region ICCM */
MPU_REGION_ENTRY("ICCM", MPU_REGION_ENTRY("ICCM",
CONFIG_ICCM_BASE_ADDRESS, DT_ICCM_BASE_ADDRESS,
CONFIG_ICCM_SIZE * 1024, DT_ICCM_SIZE * 1024,
REGION_FLASH_ATTR), REGION_FLASH_ATTR),
#endif #endif
#if CONFIG_DCCM_SIZE > 0 #if DT_DCCM_SIZE > 0
/* Region DCCM */ /* Region DCCM */
MPU_REGION_ENTRY("DCCM", MPU_REGION_ENTRY("DCCM",
CONFIG_DCCM_BASE_ADDRESS, DT_DCCM_BASE_ADDRESS,
CONFIG_DCCM_SIZE * 1024, DT_DCCM_SIZE * 1024,
REGION_RAM_ATTR), REGION_RAM_ATTR),
#endif #endif
/* Region Peripheral */ /* Region Peripheral */

28
boards/arm/96b_argonkey/dts_fixup.h
View file

@ -9,23 +9,23 @@
* generated data matches the driver definitions. * generated data matches the driver definitions.
*/ */
#define CONFIG_HTS221_NAME DT_ST_STM32_I2C_V1_40005800_ST_HTS221_5F_LABEL #define DT_HTS221_NAME DT_ST_STM32_I2C_V1_40005800_ST_HTS221_5F_LABEL
#define CONFIG_HTS221_I2C_MASTER_DEV_NAME DT_ST_STM32_I2C_V1_40005800_ST_HTS221_5F_BUS_NAME #define DT_HTS221_I2C_MASTER_DEV_NAME DT_ST_STM32_I2C_V1_40005800_ST_HTS221_5F_BUS_NAME
#define CONFIG_LPS22HB_DEV_NAME DT_ST_STM32_I2C_V1_40005800_ST_LPS22HB_PRESS_5D_LABEL #define DT_LPS22HB_DEV_NAME DT_ST_STM32_I2C_V1_40005800_ST_LPS22HB_PRESS_5D_LABEL
#define CONFIG_LPS22HB_I2C_ADDR DT_ST_STM32_I2C_V1_40005800_ST_LPS22HB_PRESS_5D_BASE_ADDRESS #define DT_LPS22HB_I2C_ADDR DT_ST_STM32_I2C_V1_40005800_ST_LPS22HB_PRESS_5D_BASE_ADDRESS
#define CONFIG_LPS22HB_I2C_MASTER_DEV_NAME DT_ST_STM32_I2C_V1_40005800_ST_LPS22HB_PRESS_5D_BUS_NAME #define DT_LPS22HB_I2C_MASTER_DEV_NAME DT_ST_STM32_I2C_V1_40005800_ST_LPS22HB_PRESS_5D_BUS_NAME
#define CONFIG_VL53L0X_NAME DT_ST_STM32_I2C_V1_40005800_ST_VL53L0X_29_LABEL #define DT_VL53L0X_NAME DT_ST_STM32_I2C_V1_40005800_ST_VL53L0X_29_LABEL
#define CONFIG_VL53L0X_I2C_ADDR DT_ST_STM32_I2C_V1_40005800_ST_VL53L0X_29_BASE_ADDRESS #define DT_VL53L0X_I2C_ADDR DT_ST_STM32_I2C_V1_40005800_ST_VL53L0X_29_BASE_ADDRESS
#define CONFIG_VL53L0X_I2C_MASTER_DEV_NAME DT_ST_STM32_I2C_V1_40005800_ST_VL53L0X_29_BUS_NAME #define DT_VL53L0X_I2C_MASTER_DEV_NAME DT_ST_STM32_I2C_V1_40005800_ST_VL53L0X_29_BUS_NAME
#define CONFIG_LSM6DSL_DEV_NAME DT_ST_STM32_SPI_40003800_ST_LSM6DSL_SPI_1_LABEL #define DT_LSM6DSL_DEV_NAME DT_ST_STM32_SPI_40003800_ST_LSM6DSL_SPI_1_LABEL
#define CONFIG_LSM6DSL_SPI_SELECT_SLAVE DT_ST_STM32_SPI_40003800_ST_LSM6DSL_SPI_1_BASE_ADDRESS #define DT_LSM6DSL_SPI_SELECT_SLAVE DT_ST_STM32_SPI_40003800_ST_LSM6DSL_SPI_1_BASE_ADDRESS
#define CONFIG_LSM6DSL_SPI_MASTER_DEV_NAME DT_ST_STM32_SPI_40003800_ST_LSM6DSL_SPI_1_BUS_NAME #define DT_LSM6DSL_SPI_MASTER_DEV_NAME DT_ST_STM32_SPI_40003800_ST_LSM6DSL_SPI_1_BUS_NAME
#define CONFIG_LSM6DSL_SPI_BUS_FREQ DT_ST_STM32_SPI_40003800_ST_LSM6DSL_SPI_1_SPI_MAX_FREQUENCY #define DT_LSM6DSL_SPI_BUS_FREQ DT_ST_STM32_SPI_40003800_ST_LSM6DSL_SPI_1_SPI_MAX_FREQUENCY
#define CONFIG_LSM6DSL_GPIO_DEV_NAME DT_ST_STM32_SPI_40003800_ST_LSM6DSL_SPI_1_IRQ_GPIOS_CONTROLLER #define DT_LSM6DSL_GPIO_DEV_NAME DT_ST_STM32_SPI_40003800_ST_LSM6DSL_SPI_1_IRQ_GPIOS_CONTROLLER
#define CONFIG_LSM6DSL_GPIO_PIN_NUM DT_ST_STM32_SPI_40003800_ST_LSM6DSL_SPI_1_IRQ_GPIOS_PIN #define DT_LSM6DSL_GPIO_PIN_NUM DT_ST_STM32_SPI_40003800_ST_LSM6DSL_SPI_1_IRQ_GPIOS_PIN
#define CONFIG_LP3943_DEV_NAME DT_ST_STM32_I2C_V1_40005C00_TI_LP3943_60_LABEL #define CONFIG_LP3943_DEV_NAME DT_ST_STM32_I2C_V1_40005C00_TI_LP3943_60_LABEL
#define CONFIG_LP3943_I2C_ADDRESS DT_ST_STM32_I2C_V1_40005C00_TI_LP3943_60_BASE_ADDRESS #define CONFIG_LP3943_I2C_ADDRESS DT_ST_STM32_I2C_V1_40005C00_TI_LP3943_60_BASE_ADDRESS

30
boards/arm/adafruit_feather_m0_basic_proto/pinmux.c
View file

@ -9,54 +9,54 @@
static int board_pinmux_init(struct device *dev) static int board_pinmux_init(struct device *dev)
{ {
struct device *muxa = device_get_binding(CONFIG_PINMUX_SAM0_A_LABEL); struct device *muxa = device_get_binding(DT_PINMUX_SAM0_A_LABEL);
#if CONFIG_SPI_SAM0_SERCOM4_BASE_ADDRESS #if DT_SPI_SAM0_SERCOM4_BASE_ADDRESS
struct device *muxb = device_get_binding(CONFIG_PINMUX_SAM0_B_LABEL); struct device *muxb = device_get_binding(DT_PINMUX_SAM0_B_LABEL);
#endif #endif
ARG_UNUSED(dev); ARG_UNUSED(dev);
#if CONFIG_UART_SAM0_SERCOM0_BASE_ADDRESS #if DT_UART_SAM0_SERCOM0_BASE_ADDRESS
/* SERCOM0 on RX=PA11/pad 3, TX=PA10/pad 2 */ /* SERCOM0 on RX=PA11/pad 3, TX=PA10/pad 2 */
pinmux_pin_set(muxa, 11, PINMUX_FUNC_C); pinmux_pin_set(muxa, 11, PINMUX_FUNC_C);
pinmux_pin_set(muxa, 10, PINMUX_FUNC_C); pinmux_pin_set(muxa, 10, PINMUX_FUNC_C);
#endif #endif
#if CONFIG_UART_SAM0_SERCOM1_BASE_ADDRESS #if DT_UART_SAM0_SERCOM1_BASE_ADDRESS
#error Pin mapping is not configured #error Pin mapping is not configured
#endif #endif
#if CONFIG_UART_SAM0_SERCOM2_BASE_ADDRESS #if DT_UART_SAM0_SERCOM2_BASE_ADDRESS
#error Pin mapping is not configured #error Pin mapping is not configured
#endif #endif
#if CONFIG_UART_SAM0_SERCOM3_BASE_ADDRESS #if DT_UART_SAM0_SERCOM3_BASE_ADDRESS
#error Pin mapping is not configured #error Pin mapping is not configured
#endif #endif
#if CONFIG_UART_SAM0_SERCOM4_BASE_ADDRESS #if DT_UART_SAM0_SERCOM4_BASE_ADDRESS
#error Pin mapping is not configured #error Pin mapping is not configured
#endif #endif
#if CONFIG_UART_SAM0_SERCOM5_BASE_ADDRESS #if DT_UART_SAM0_SERCOM5_BASE_ADDRESS
#error Pin mapping is not configured #error Pin mapping is not configured
#endif #endif
#if CONFIG_SPI_SAM0_SERCOM4_BASE_ADDRESS #if DT_SPI_SAM0_SERCOM4_BASE_ADDRESS
/* SPI SERCOM4 on MISO=PA12/pad 0, MOSI=PB10/pad 2, SCK=PB11/pad 3 */ /* SPI SERCOM4 on MISO=PA12/pad 0, MOSI=PB10/pad 2, SCK=PB11/pad 3 */
pinmux_pin_set(muxa, 12, PINMUX_FUNC_D); pinmux_pin_set(muxa, 12, PINMUX_FUNC_D);
pinmux_pin_set(muxb, 10, PINMUX_FUNC_D); pinmux_pin_set(muxb, 10, PINMUX_FUNC_D);
pinmux_pin_set(muxb, 11, PINMUX_FUNC_D); pinmux_pin_set(muxb, 11, PINMUX_FUNC_D);
#endif #endif
#if CONFIG_SPI_SAM0_SERCOM0_BASE_ADDRESS #if DT_SPI_SAM0_SERCOM0_BASE_ADDRESS
#error Pin mapping is not configured #error Pin mapping is not configured
#endif #endif
#if CONFIG_SPI_SAM0_SERCOM1_BASE_ADDRESS #if DT_SPI_SAM0_SERCOM1_BASE_ADDRESS
#error Pin mapping is not configured #error Pin mapping is not configured
#endif #endif
#if CONFIG_SPI_SAM0_SERCOM2_BASE_ADDRESS #if DT_SPI_SAM0_SERCOM2_BASE_ADDRESS
#error Pin mapping is not configured #error Pin mapping is not configured
#endif #endif
#if CONFIG_SPI_SAM0_SERCOM3_BASE_ADDRESS #if DT_SPI_SAM0_SERCOM3_BASE_ADDRESS
#error Pin mapping is not configured #error Pin mapping is not configured
#endif #endif
#if CONFIG_SPI_SAM0_SERCOM5_BASE_ADDRESS #if DT_SPI_SAM0_SERCOM5_BASE_ADDRESS
#error Pin mapping is not configured #error Pin mapping is not configured
#endif #endif

26
boards/arm/adafruit_trinket_m0/pinmux.c
View file

@ -9,58 +9,58 @@
static int board_pinmux_init(struct device *dev) static int board_pinmux_init(struct device *dev)
{ {
struct device *muxa = device_get_binding(CONFIG_PINMUX_SAM0_A_LABEL); struct device *muxa = device_get_binding(DT_PINMUX_SAM0_A_LABEL);
ARG_UNUSED(dev); ARG_UNUSED(dev);
#if CONFIG_UART_SAM0_SERCOM0_BASE_ADDRESS #if DT_UART_SAM0_SERCOM0_BASE_ADDRESS
/* SERCOM0 on RX=PA7/pad 3, TX=PA6/pad 2 */ /* SERCOM0 on RX=PA7/pad 3, TX=PA6/pad 2 */
pinmux_pin_set(muxa, 7, PINMUX_FUNC_D); pinmux_pin_set(muxa, 7, PINMUX_FUNC_D);
pinmux_pin_set(muxa, 6, PINMUX_FUNC_D); pinmux_pin_set(muxa, 6, PINMUX_FUNC_D);
#endif #endif
#if CONFIG_UART_SAM0_SERCOM2_BASE_ADDRESS #if DT_UART_SAM0_SERCOM2_BASE_ADDRESS
/* SERCOM2 on RX=PA9/pad 1, TX=PA8/pad 0 */ /* SERCOM2 on RX=PA9/pad 1, TX=PA8/pad 0 */
pinmux_pin_set(muxa, 9, PINMUX_FUNC_D); pinmux_pin_set(muxa, 9, PINMUX_FUNC_D);
pinmux_pin_set(muxa, 8, PINMUX_FUNC_D); pinmux_pin_set(muxa, 8, PINMUX_FUNC_D);
#endif #endif
#if CONFIG_UART_SAM0_SERCOM1_BASE_ADDRESS #if DT_UART_SAM0_SERCOM1_BASE_ADDRESS
#error Pin mapping is not configured #error Pin mapping is not configured
#endif #endif
#if CONFIG_UART_SAM0_SERCOM3_BASE_ADDRESS #if DT_UART_SAM0_SERCOM3_BASE_ADDRESS
#error Pin mapping is not configured #error Pin mapping is not configured
#endif #endif
#if CONFIG_UART_SAM0_SERCOM4_BASE_ADDRESS #if DT_UART_SAM0_SERCOM4_BASE_ADDRESS
#error Pin mapping is not configured #error Pin mapping is not configured
#endif #endif
#if CONFIG_UART_SAM0_SERCOM5_BASE_ADDRESS #if DT_UART_SAM0_SERCOM5_BASE_ADDRESS
#error Pin mapping is not configured #error Pin mapping is not configured
#endif #endif
#if CONFIG_SPI_SAM0_SERCOM0_BASE_ADDRESS #if DT_SPI_SAM0_SERCOM0_BASE_ADDRESS
/* SPI SERCOM0 on MISO=PA9/pad 1, MOSI=PA6/pad 2, SCK=PA7/pad 3 */ /* SPI SERCOM0 on MISO=PA9/pad 1, MOSI=PA6/pad 2, SCK=PA7/pad 3 */
pinmux_pin_set(muxa, 9, PINMUX_FUNC_D); pinmux_pin_set(muxa, 9, PINMUX_FUNC_D);
pinmux_pin_set(muxa, 6, PINMUX_FUNC_D); pinmux_pin_set(muxa, 6, PINMUX_FUNC_D);
pinmux_pin_set(muxa, 7, PINMUX_FUNC_D); pinmux_pin_set(muxa, 7, PINMUX_FUNC_D);
#endif #endif
#if CONFIG_SPI_SAM0_SERCOM1_BASE_ADDRESS #if DT_SPI_SAM0_SERCOM1_BASE_ADDRESS
/* SPI SERCOM1 on MOSI=PA0/pad 0, SCK=PA1/pad 1 */ /* SPI SERCOM1 on MOSI=PA0/pad 0, SCK=PA1/pad 1 */
pinmux_pin_set(muxa, 0, PINMUX_FUNC_D); pinmux_pin_set(muxa, 0, PINMUX_FUNC_D);
pinmux_pin_set(muxa, 1, PINMUX_FUNC_D); pinmux_pin_set(muxa, 1, PINMUX_FUNC_D);
#endif #endif
#if CONFIG_SPI_SAM0_SERCOM2_BASE_ADDRESS #if DT_SPI_SAM0_SERCOM2_BASE_ADDRESS
#error Pin mapping is not configured #error Pin mapping is not configured
#endif #endif
#if CONFIG_SPI_SAM0_SERCOM3_BASE_ADDRESS #if DT_SPI_SAM0_SERCOM3_BASE_ADDRESS
#error Pin mapping is not configured #error Pin mapping is not configured
#endif #endif
#if CONFIG_SPI_SAM0_SERCOM4_BASE_ADDRESS #if DT_SPI_SAM0_SERCOM4_BASE_ADDRESS
#error Pin mapping is not configured #error Pin mapping is not configured
#endif #endif
#if CONFIG_SPI_SAM0_SERCOM5_BASE_ADDRESS #if DT_SPI_SAM0_SERCOM5_BASE_ADDRESS
#error Pin mapping is not configured #error Pin mapping is not configured
#endif #endif

28
boards/arm/arduino_zero/pinmux.c
View file

@ -9,56 +9,56 @@
static int board_pinmux_init(struct device *dev) static int board_pinmux_init(struct device *dev)
{ {
struct device *muxa = device_get_binding(CONFIG_PINMUX_SAM0_A_LABEL); struct device *muxa = device_get_binding(DT_PINMUX_SAM0_A_LABEL);
struct device *muxb = device_get_binding(CONFIG_PINMUX_SAM0_B_LABEL); struct device *muxb = device_get_binding(DT_PINMUX_SAM0_B_LABEL);
ARG_UNUSED(dev); ARG_UNUSED(dev);
#if CONFIG_UART_SAM0_SERCOM0_BASE_ADDRESS #if DT_UART_SAM0_SERCOM0_BASE_ADDRESS
/* SERCOM0 on RX=PA11, TX=PA10 */ /* SERCOM0 on RX=PA11, TX=PA10 */
pinmux_pin_set(muxa, 11, PINMUX_FUNC_C); pinmux_pin_set(muxa, 11, PINMUX_FUNC_C);
pinmux_pin_set(muxa, 10, PINMUX_FUNC_C); pinmux_pin_set(muxa, 10, PINMUX_FUNC_C);
#endif #endif
#if CONFIG_UART_SAM0_SERCOM5_BASE_ADDRESS #if DT_UART_SAM0_SERCOM5_BASE_ADDRESS
/* SERCOM5 on RX=PB23, TX=PB22 */ /* SERCOM5 on RX=PB23, TX=PB22 */
pinmux_pin_set(muxb, 23, PINMUX_FUNC_D); pinmux_pin_set(muxb, 23, PINMUX_FUNC_D);
pinmux_pin_set(muxb, 22, PINMUX_FUNC_D); pinmux_pin_set(muxb, 22, PINMUX_FUNC_D);
#endif #endif
#if CONFIG_UART_SAM0_SERCOM1_BASE_ADDRESS #if DT_UART_SAM0_SERCOM1_BASE_ADDRESS
#error Pin mapping is not configured #error Pin mapping is not configured
#endif #endif
#if CONFIG_UART_SAM0_SERCOM2_BASE_ADDRESS #if DT_UART_SAM0_SERCOM2_BASE_ADDRESS
#error Pin mapping is not configured #error Pin mapping is not configured
#endif #endif
#if CONFIG_UART_SAM0_SERCOM3_BASE_ADDRESS #if DT_UART_SAM0_SERCOM3_BASE_ADDRESS
#error Pin mapping is not configured #error Pin mapping is not configured
#endif #endif
#if CONFIG_UART_SAM0_SERCOM4_BASE_ADDRESS #if DT_UART_SAM0_SERCOM4_BASE_ADDRESS
#error Pin mapping is not configured #error Pin mapping is not configured
#endif #endif
#if CONFIG_SPI_SAM0_SERCOM4_BASE_ADDRESS #if DT_SPI_SAM0_SERCOM4_BASE_ADDRESS
/* SPI SERCOM4 on MISO=PA12/pad 0, MOSI=PB10/pad 2, SCK=PB11/pad 3 */ /* SPI SERCOM4 on MISO=PA12/pad 0, MOSI=PB10/pad 2, SCK=PB11/pad 3 */
pinmux_pin_set(muxa, 12, PINMUX_FUNC_D); pinmux_pin_set(muxa, 12, PINMUX_FUNC_D);
pinmux_pin_set(muxb, 10, PINMUX_FUNC_D); pinmux_pin_set(muxb, 10, PINMUX_FUNC_D);
pinmux_pin_set(muxb, 11, PINMUX_FUNC_D); pinmux_pin_set(muxb, 11, PINMUX_FUNC_D);
#endif #endif
#if CONFIG_SPI_SAM0_SERCOM0_BASE_ADDRESS #if DT_SPI_SAM0_SERCOM0_BASE_ADDRESS
#error Pin mapping is not configured #error Pin mapping is not configured
#endif #endif
#if CONFIG_SPI_SAM0_SERCOM1_BASE_ADDRESS #if DT_SPI_SAM0_SERCOM1_BASE_ADDRESS
#error Pin mapping is not configured #error Pin mapping is not configured
#endif #endif
#if CONFIG_SPI_SAM0_SERCOM2_BASE_ADDRESS #if DT_SPI_SAM0_SERCOM2_BASE_ADDRESS
#error Pin mapping is not configured #error Pin mapping is not configured
#endif #endif
#if CONFIG_SPI_SAM0_SERCOM3_BASE_ADDRESS #if DT_SPI_SAM0_SERCOM3_BASE_ADDRESS
#error Pin mapping is not configured #error Pin mapping is not configured
#endif #endif
#if CONFIG_SPI_SAM0_SERCOM5_BASE_ADDRESS #if DT_SPI_SAM0_SERCOM5_BASE_ADDRESS
#error Pin mapping is not configured #error Pin mapping is not configured
#endif #endif

28
boards/arm/atsamd20_xpro/pinmux.c
View file

@ -9,52 +9,52 @@
static int board_pinmux_init(struct device *dev) static int board_pinmux_init(struct device *dev)
{ {
struct device *muxa = device_get_binding(CONFIG_PINMUX_SAM0_A_LABEL); struct device *muxa = device_get_binding(DT_PINMUX_SAM0_A_LABEL);
struct device *muxb = device_get_binding(CONFIG_PINMUX_SAM0_B_LABEL); struct device *muxb = device_get_binding(DT_PINMUX_SAM0_B_LABEL);
ARG_UNUSED(dev); ARG_UNUSED(dev);
#if CONFIG_UART_SAM0_SERCOM0_BASE_ADDRESS #if DT_UART_SAM0_SERCOM0_BASE_ADDRESS
#error Pin mapping is not configured #error Pin mapping is not configured
#endif #endif
#if CONFIG_UART_SAM0_SERCOM1_BASE_ADDRESS #if DT_UART_SAM0_SERCOM1_BASE_ADDRESS
#error Pin mapping is not configured #error Pin mapping is not configured
#endif #endif
#if CONFIG_UART_SAM0_SERCOM2_BASE_ADDRESS #if DT_UART_SAM0_SERCOM2_BASE_ADDRESS
#error Pin mapping is not configured #error Pin mapping is not configured
#endif #endif
#if CONFIG_UART_SAM0_SERCOM3_BASE_ADDRESS #if DT_UART_SAM0_SERCOM3_BASE_ADDRESS
/* SERCOM3 on RX=PA25, TX=PA24 */ /* SERCOM3 on RX=PA25, TX=PA24 */
pinmux_pin_set(muxa, 24, PINMUX_FUNC_C); pinmux_pin_set(muxa, 24, PINMUX_FUNC_C);
pinmux_pin_set(muxa, 25, PINMUX_FUNC_C); pinmux_pin_set(muxa, 25, PINMUX_FUNC_C);
#endif #endif
#if CONFIG_UART_SAM0_SERCOM4_BASE_ADDRESS #if DT_UART_SAM0_SERCOM4_BASE_ADDRESS
pinmux_pin_set(muxb, 8, PINMUX_FUNC_D); pinmux_pin_set(muxb, 8, PINMUX_FUNC_D);
pinmux_pin_set(muxb, 9, PINMUX_FUNC_D); pinmux_pin_set(muxb, 9, PINMUX_FUNC_D);
#endif #endif
#if CONFIG_UART_SAM0_SERCOM5_BASE_ADDRESS #if DT_UART_SAM0_SERCOM5_BASE_ADDRESS
#error Pin mapping is not configured #error Pin mapping is not configured
#endif #endif
#if CONFIG_SPI_SAM0_SERCOM0_BASE_ADDRESS #if DT_SPI_SAM0_SERCOM0_BASE_ADDRESS
/* SPI SERCOM0 on MISO=PA04, MOSI=PA06, SCK=PA07 */ /* SPI SERCOM0 on MISO=PA04, MOSI=PA06, SCK=PA07 */
pinmux_pin_set(muxa, 4, PINMUX_FUNC_D); pinmux_pin_set(muxa, 4, PINMUX_FUNC_D);
pinmux_pin_set(muxa, 6, PINMUX_FUNC_D); pinmux_pin_set(muxa, 6, PINMUX_FUNC_D);
pinmux_pin_set(muxa, 7, PINMUX_FUNC_D); pinmux_pin_set(muxa, 7, PINMUX_FUNC_D);
#endif #endif
#if CONFIG_SPI_SAM0_SERCOM1_BASE_ADDRESS #if DT_SPI_SAM0_SERCOM1_BASE_ADDRESS
#error Pin mapping is not configured #error Pin mapping is not configured
#endif #endif
#if CONFIG_SPI_SAM0_SERCOM2_BASE_ADDRESS #if DT_SPI_SAM0_SERCOM2_BASE_ADDRESS
#error Pin mapping is not configured #error Pin mapping is not configured
#endif #endif
#if CONFIG_SPI_SAM0_SERCOM3_BASE_ADDRESS #if DT_SPI_SAM0_SERCOM3_BASE_ADDRESS
#error Pin mapping is not configured #error Pin mapping is not configured
#endif #endif
#if CONFIG_SPI_SAM0_SERCOM4_BASE_ADDRESS #if DT_SPI_SAM0_SERCOM4_BASE_ADDRESS
#error Pin mapping is not configured #error Pin mapping is not configured
#endif #endif
#if CONFIG_SPI_SAM0_SERCOM5_BASE_ADDRESS #if DT_SPI_SAM0_SERCOM5_BASE_ADDRESS
#error Pin mapping is not configured #error Pin mapping is not configured
#endif #endif

28
boards/arm/atsamd21_xpro/pinmux.c
View file

@ -9,52 +9,52 @@
static int board_pinmux_init(struct device *dev) static int board_pinmux_init(struct device *dev)
{ {
struct device *muxa = device_get_binding(CONFIG_PINMUX_SAM0_A_LABEL); struct device *muxa = device_get_binding(DT_PINMUX_SAM0_A_LABEL);
struct device *muxb = device_get_binding(CONFIG_PINMUX_SAM0_B_LABEL); struct device *muxb = device_get_binding(DT_PINMUX_SAM0_B_LABEL);
ARG_UNUSED(dev); ARG_UNUSED(dev);
#if CONFIG_UART_SAM0_SERCOM0_BASE_ADDRESS #if DT_UART_SAM0_SERCOM0_BASE_ADDRESS
/* SERCOM0 on RX=PA11, TX=PA10 */ /* SERCOM0 on RX=PA11, TX=PA10 */
pinmux_pin_set(muxa, 11, PINMUX_FUNC_C); pinmux_pin_set(muxa, 11, PINMUX_FUNC_C);
pinmux_pin_set(muxa, 10, PINMUX_FUNC_C); pinmux_pin_set(muxa, 10, PINMUX_FUNC_C);
#endif #endif
#if CONFIG_UART_SAM0_SERCOM1_BASE_ADDRESS #if DT_UART_SAM0_SERCOM1_BASE_ADDRESS
/* SERCOM3 ON RX=PA19, TX=PA16 */ /* SERCOM3 ON RX=PA19, TX=PA16 */
pinmux_pin_set(muxa, 19, PINMUX_FUNC_C); pinmux_pin_set(muxa, 19, PINMUX_FUNC_C);
pinmux_pin_set(muxa, 16, PINMUX_FUNC_C); pinmux_pin_set(muxa, 16, PINMUX_FUNC_C);
#endif #endif
#if CONFIG_UART_SAM0_SERCOM2_BASE_ADDRESS #if DT_UART_SAM0_SERCOM2_BASE_ADDRESS
#error Pin mapping is not configured #error Pin mapping is not configured
#endif #endif
#if CONFIG_UART_SAM0_SERCOM3_BASE_ADDRESS #if DT_UART_SAM0_SERCOM3_BASE_ADDRESS
/* SERCOM3 ON RX=PA23, TX=PA22 */ /* SERCOM3 ON RX=PA23, TX=PA22 */
pinmux_pin_set(muxa, 23, PINMUX_FUNC_C); pinmux_pin_set(muxa, 23, PINMUX_FUNC_C);
pinmux_pin_set(muxa, 22, PINMUX_FUNC_C); pinmux_pin_set(muxa, 22, PINMUX_FUNC_C);
#endif #endif
#if CONFIG_UART_SAM0_SERCOM4_BASE_ADDRESS #if DT_UART_SAM0_SERCOM4_BASE_ADDRESS
#error Pin mapping is not configured #error Pin mapping is not configured
#endif #endif
#if CONFIG_UART_SAM0_SERCOM5_BASE_ADDRESS #if DT_UART_SAM0_SERCOM5_BASE_ADDRESS
#error Pin mapping is not configured #error Pin mapping is not configured
#endif #endif
#if CONFIG_SPI_SAM0_SERCOM0_BASE_ADDRESS #if DT_SPI_SAM0_SERCOM0_BASE_ADDRESS
#error Pin mapping is not configured #error Pin mapping is not configured
#endif #endif
#if CONFIG_SPI_SAM0_SERCOM1_BASE_ADDRESS #if DT_SPI_SAM0_SERCOM1_BASE_ADDRESS
#error Pin mapping is not configured #error Pin mapping is not configured
#endif #endif
#if CONFIG_SPI_SAM0_SERCOM2_BASE_ADDRESS #if DT_SPI_SAM0_SERCOM2_BASE_ADDRESS
#error Pin mapping is not configured #error Pin mapping is not configured
#endif #endif
#if CONFIG_SPI_SAM0_SERCOM3_BASE_ADDRESS #if DT_SPI_SAM0_SERCOM3_BASE_ADDRESS
#error Pin mapping is not configured #error Pin mapping is not configured
#endif #endif
#if CONFIG_SPI_SAM0_SERCOM4_BASE_ADDRESS #if DT_SPI_SAM0_SERCOM4_BASE_ADDRESS
#error Pin mapping is not configured #error Pin mapping is not configured
#endif #endif
#if CONFIG_SPI_SAM0_SERCOM5_BASE_ADDRESS #if DT_SPI_SAM0_SERCOM5_BASE_ADDRESS
/* SPI SERCOM5 on MISO=PB16/pad 0, MOSI=PB22/pad 2, SCK=PB23/pad 3 */ /* SPI SERCOM5 on MISO=PB16/pad 0, MOSI=PB22/pad 2, SCK=PB23/pad 3 */
pinmux_pin_set(muxb, 16, PINMUX_FUNC_C); pinmux_pin_set(muxb, 16, PINMUX_FUNC_C);
pinmux_pin_set(muxb, 22, PINMUX_FUNC_D); pinmux_pin_set(muxb, 22, PINMUX_FUNC_D);

10
boards/arm/bbc_microbit/dts_fixup.h
View file

@ -4,8 +4,8 @@
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
#define CONFIG_FXOS8700_NAME DT_NORDIC_NRF_I2C_40003000_NXP_FXOS8700_1D_LABEL #define DT_FXOS8700_NAME DT_NORDIC_NRF_I2C_40003000_NXP_FXOS8700_1D_LABEL
#define CONFIG_FXOS8700_I2C_NAME DT_NORDIC_NRF_I2C_40003000_NXP_FXOS8700_1D_BUS_NAME #define DT_FXOS8700_I2C_NAME DT_NORDIC_NRF_I2C_40003000_NXP_FXOS8700_1D_BUS_NAME
#define CONFIG_FXOS8700_I2C_ADDRESS DT_NORDIC_NRF_I2C_40003000_NXP_FXOS8700_1D_BASE_ADDRESS #define DT_FXOS8700_I2C_ADDRESS DT_NORDIC_NRF_I2C_40003000_NXP_FXOS8700_1D_BASE_ADDRESS
#define CONFIG_FXOS8700_GPIO_NAME DT_NORDIC_NRF_I2C_40003000_NXP_FXOS8700_1D_INT2_GPIOS_CONTROLLER #define DT_FXOS8700_GPIO_NAME DT_NORDIC_NRF_I2C_40003000_NXP_FXOS8700_1D_INT2_GPIOS_CONTROLLER
#define CONFIG_FXOS8700_GPIO_PIN DT_NORDIC_NRF_I2C_40003000_NXP_FXOS8700_1D_INT2_GPIOS_PIN #define DT_FXOS8700_GPIO_PIN DT_NORDIC_NRF_I2C_40003000_NXP_FXOS8700_1D_INT2_GPIOS_PIN

32
boards/arm/disco_l475_iot1/dts_fixup.h
View file

@ -4,27 +4,27 @@
* generated data matches the driver definitions. * generated data matches the driver definitions.
*/ */
#define CONFIG_HTS221_NAME DT_ST_STM32_I2C_V2_40005800_ST_HTS221_5F_LABEL #define DT_HTS221_NAME DT_ST_STM32_I2C_V2_40005800_ST_HTS221_5F_LABEL
#define CONFIG_HTS221_I2C_MASTER_DEV_NAME DT_ST_STM32_I2C_V2_40005800_ST_HTS221_5F_BUS_NAME #define DT_HTS221_I2C_MASTER_DEV_NAME DT_ST_STM32_I2C_V2_40005800_ST_HTS221_5F_BUS_NAME
#define CONFIG_LIS3MDL_NAME DT_ST_STM32_I2C_V2_40005800_ST_LIS3MDL_MAGN_1E_LABEL #define DT_LIS3MDL_NAME DT_ST_STM32_I2C_V2_40005800_ST_LIS3MDL_MAGN_1E_LABEL
#define CONFIG_LIS3MDL_I2C_ADDR DT_ST_STM32_I2C_V2_40005800_ST_LIS3MDL_MAGN_1E_BASE_ADDRESS #define DT_LIS3MDL_I2C_ADDR DT_ST_STM32_I2C_V2_40005800_ST_LIS3MDL_MAGN_1E_BASE_ADDRESS
#define CONFIG_LIS3MDL_I2C_MASTER_DEV_NAME DT_ST_STM32_I2C_V2_40005800_ST_LIS3MDL_MAGN_1E_BUS_NAME #define DT_LIS3MDL_I2C_MASTER_DEV_NAME DT_ST_STM32_I2C_V2_40005800_ST_LIS3MDL_MAGN_1E_BUS_NAME
#define CONFIG_LSM6DSL_DEV_NAME DT_ST_STM32_I2C_V2_40005800_ST_LSM6DSL_6A_LABEL #define DT_LSM6DSL_DEV_NAME DT_ST_STM32_I2C_V2_40005800_ST_LSM6DSL_6A_LABEL
#define CONFIG_LSM6DSL_I2C_ADDR DT_ST_STM32_I2C_V2_40005800_ST_LSM6DSL_6A_BASE_ADDRESS #define DT_LSM6DSL_I2C_ADDR DT_ST_STM32_I2C_V2_40005800_ST_LSM6DSL_6A_BASE_ADDRESS
#define CONFIG_LSM6DSL_I2C_MASTER_DEV_NAME DT_ST_STM32_I2C_V2_40005800_ST_LSM6DSL_6A_BUS_NAME #define DT_LSM6DSL_I2C_MASTER_DEV_NAME DT_ST_STM32_I2C_V2_40005800_ST_LSM6DSL_6A_BUS_NAME
#define CONFIG_LPS22HB_DEV_NAME DT_ST_STM32_I2C_V2_40005800_ST_LPS22HB_PRESS_5D_LABEL #define DT_LPS22HB_DEV_NAME DT_ST_STM32_I2C_V2_40005800_ST_LPS22HB_PRESS_5D_LABEL
#define CONFIG_LPS22HB_I2C_ADDR DT_ST_STM32_I2C_V2_40005800_ST_LPS22HB_PRESS_5D_BASE_ADDRESS #define DT_LPS22HB_I2C_ADDR DT_ST_STM32_I2C_V2_40005800_ST_LPS22HB_PRESS_5D_BASE_ADDRESS
#define CONFIG_LPS22HB_I2C_MASTER_DEV_NAME DT_ST_STM32_I2C_V2_40005800_ST_LPS22HB_PRESS_5D_BUS_NAME #define DT_LPS22HB_I2C_MASTER_DEV_NAME DT_ST_STM32_I2C_V2_40005800_ST_LPS22HB_PRESS_5D_BUS_NAME
#define CONFIG_BT_SPI_DEV_NAME DT_ST_STM32_SPI_FIFO_40003C00_ST_SPBTLE_RF_0_BUS_NAME #define CONFIG_BT_SPI_DEV_NAME DT_ST_STM32_SPI_FIFO_40003C00_ST_SPBTLE_RF_0_BUS_NAME
#define CONFIG_BT_SPI_MAX_CLK_FREQ DT_ST_STM32_SPI_FIFO_40003C00_ST_SPBTLE_RF_0_SPI_MAX_FREQUENCY #define CONFIG_BT_SPI_MAX_CLK_FREQ DT_ST_STM32_SPI_FIFO_40003C00_ST_SPBTLE_RF_0_SPI_MAX_FREQUENCY
#define CONFIG_VL53L0X_NAME DT_ST_STM32_I2C_V2_40005800_ST_VL53L0X_29_LABEL #define DT_VL53L0X_NAME DT_ST_STM32_I2C_V2_40005800_ST_VL53L0X_29_LABEL
#define CONFIG_VL53L0X_I2C_ADDR DT_ST_STM32_I2C_V2_40005800_ST_VL53L0X_29_BASE_ADDRESS #define DT_VL53L0X_I2C_ADDR DT_ST_STM32_I2C_V2_40005800_ST_VL53L0X_29_BASE_ADDRESS
#define CONFIG_VL53L0X_I2C_MASTER_DEV_NAME DT_ST_STM32_I2C_V2_40005800_ST_VL53L0X_29_BUS_NAME #define DT_VL53L0X_I2C_MASTER_DEV_NAME DT_ST_STM32_I2C_V2_40005800_ST_VL53L0X_29_BUS_NAME
#define CONFIG_BT_SPI_IRQ_DEV_NAME BT_IRQ_GPIOS_CONTROLLER #define CONFIG_BT_SPI_IRQ_DEV_NAME BT_IRQ_GPIOS_CONTROLLER
#define CONFIG_BT_SPI_IRQ_PIN BT_IRQ_GPIOS_PIN #define CONFIG_BT_SPI_IRQ_PIN BT_IRQ_GPIOS_PIN
@ -33,5 +33,5 @@
#define CONFIG_BT_SPI_RESET_DEV_NAME BT_RESET_GPIOS_CONTROLLER #define CONFIG_BT_SPI_RESET_DEV_NAME BT_RESET_GPIOS_CONTROLLER
#define CONFIG_BT_SPI_RESET_PIN BT_RESET_GPIOS_PIN #define CONFIG_BT_SPI_RESET_PIN BT_RESET_GPIOS_PIN
#define ESWIFI0_CS_GPIOS_CONTROLLER DT_ST_STM32_SPI_FIFO_40003C00_CS_GPIOS_CONTROLLER_1 #define DT_ESWIFI0_CS_GPIOS_CONTROLLER DT_ST_STM32_SPI_FIFO_40003C00_CS_GPIOS_CONTROLLER_1
#define ESWIFI0_CS_GPIOS_PIN DT_ST_STM32_SPI_FIFO_40003C00_CS_GPIOS_PIN_1 #define DT_ESWIFI0_CS_GPIOS_PIN DT_ST_STM32_SPI_FIFO_40003C00_CS_GPIOS_PIN_1

2
boards/arm/efm32hg_slstk3400a/board.h
View file

@ -10,7 +10,7 @@
#include <soc.h> #include <soc.h>
/* This pin is used to enable the serial port using the board controller */ /* This pin is used to enable the serial port using the board controller */
#define BC_ENABLE_GPIO_NAME CONFIG_GPIO_GECKO_PORTA_NAME #define BC_ENABLE_GPIO_NAME DT_GPIO_GECKO_PORTA_NAME
#define BC_ENABLE_GPIO_PIN 9 #define BC_ENABLE_GPIO_PIN 9
#endif /* __INC_BOARD_H */ #endif /* __INC_BOARD_H */

2
boards/arm/efm32wg_stk3800/board.h
View file

@ -10,7 +10,7 @@
#include <soc.h> #include <soc.h>
/* This pin is used to enable the serial port using the board controller */ /* This pin is used to enable the serial port using the board controller */
#define BC_ENABLE_GPIO_NAME CONFIG_GPIO_GECKO_PORTF_NAME #define BC_ENABLE_GPIO_NAME DT_GPIO_GECKO_PORTF_NAME
#define BC_ENABLE_GPIO_PIN 7 #define BC_ENABLE_GPIO_PIN 7
#endif /* __INC_BOARD_H */ #endif /* __INC_BOARD_H */

2
boards/arm/efr32_slwstk6061a/board.h
View file

@ -10,7 +10,7 @@
#include <soc.h> #include <soc.h>
/* This pin is used to enable the serial port using the board controller */ /* This pin is used to enable the serial port using the board controller */
#define BC_ENABLE_GPIO_NAME CONFIG_GPIO_GECKO_PORTA_NAME #define BC_ENABLE_GPIO_NAME DT_GPIO_GECKO_PORTA_NAME
#define BC_ENABLE_GPIO_PIN 5 #define BC_ENABLE_GPIO_PIN 5
#endif /* __INC_BOARD_H */ #endif /* __INC_BOARD_H */

10
boards/arm/frdm_k64f/dts_fixup.h
View file

@ -1,8 +1,8 @@
#define CONFIG_FXOS8700_NAME DT_NXP_KINETIS_I2C_40066000_NXP_FXOS8700_1D_LABEL #define DT_FXOS8700_NAME DT_NXP_KINETIS_I2C_40066000_NXP_FXOS8700_1D_LABEL
#define CONFIG_FXOS8700_I2C_NAME DT_NXP_KINETIS_I2C_40066000_NXP_FXOS8700_1D_BUS_NAME #define DT_FXOS8700_I2C_NAME DT_NXP_KINETIS_I2C_40066000_NXP_FXOS8700_1D_BUS_NAME
#define CONFIG_FXOS8700_I2C_ADDRESS DT_NXP_KINETIS_I2C_40066000_NXP_FXOS8700_1D_BASE_ADDRESS #define DT_FXOS8700_I2C_ADDRESS DT_NXP_KINETIS_I2C_40066000_NXP_FXOS8700_1D_BASE_ADDRESS
#define CONFIG_FXOS8700_GPIO_NAME DT_NXP_KINETIS_I2C_40066000_NXP_FXOS8700_1D_INT2_GPIOS_CONTROLLER #define DT_FXOS8700_GPIO_NAME DT_NXP_KINETIS_I2C_40066000_NXP_FXOS8700_1D_INT2_GPIOS_CONTROLLER
#define CONFIG_FXOS8700_GPIO_PIN DT_NXP_KINETIS_I2C_40066000_NXP_FXOS8700_1D_INT2_GPIOS_PIN #define DT_FXOS8700_GPIO_PIN DT_NXP_KINETIS_I2C_40066000_NXP_FXOS8700_1D_INT2_GPIOS_PIN
#define CONFIG_IEEE802154_MCR20A_SPI_DRV_NAME DT_NXP_KINETIS_DSPI_4002C000_NXP_MCR20A_0_BUS_NAME #define CONFIG_IEEE802154_MCR20A_SPI_DRV_NAME DT_NXP_KINETIS_DSPI_4002C000_NXP_MCR20A_0_BUS_NAME
#define CONFIG_IEEE802154_MCR20A_SPI_SLAVE DT_NXP_KINETIS_DSPI_4002C000_NXP_MCR20A_0_BASE_ADDRESS #define CONFIG_IEEE802154_MCR20A_SPI_SLAVE DT_NXP_KINETIS_DSPI_4002C000_NXP_MCR20A_0_BASE_ADDRESS

10
boards/arm/frdm_kl25z/dts_fixup.h
View file

@ -4,8 +4,8 @@
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
#define CONFIG_FXOS8700_NAME DT_NXP_KINETIS_I2C_40066000_NXP_FXOS8700_1D_LABEL #define DT_FXOS8700_NAME DT_NXP_KINETIS_I2C_40066000_NXP_FXOS8700_1D_LABEL
#define CONFIG_FXOS8700_I2C_NAME DT_NXP_KINETIS_I2C_40066000_NXP_FXOS8700_1D_BUS_NAME #define DT_FXOS8700_I2C_NAME DT_NXP_KINETIS_I2C_40066000_NXP_FXOS8700_1D_BUS_NAME
#define CONFIG_FXOS8700_I2C_ADDRESS DT_NXP_KINETIS_I2C_40066000_NXP_FXOS8700_1D_BASE_ADDRESS #define DT_FXOS8700_I2C_ADDRESS DT_NXP_KINETIS_I2C_40066000_NXP_FXOS8700_1D_BASE_ADDRESS
#define CONFIG_FXOS8700_GPIO_NAME DT_NXP_KINETIS_I2C_40066000_NXP_FXOS8700_1D_INT2_GPIOS_CONTROLLER #define DT_FXOS8700_GPIO_NAME DT_NXP_KINETIS_I2C_40066000_NXP_FXOS8700_1D_INT2_GPIOS_CONTROLLER
#define CONFIG_FXOS8700_GPIO_PIN DT_NXP_KINETIS_I2C_40066000_NXP_FXOS8700_1D_INT2_GPIOS_PIN #define DT_FXOS8700_GPIO_PIN DT_NXP_KINETIS_I2C_40066000_NXP_FXOS8700_1D_INT2_GPIOS_PIN

10
boards/arm/frdm_kw41z/dts_fixup.h
View file

@ -1,5 +1,5 @@
#define CONFIG_FXOS8700_NAME DT_NXP_KINETIS_I2C_40067000_NXP_FXOS8700_1F_LABEL #define DT_FXOS8700_NAME DT_NXP_KINETIS_I2C_40067000_NXP_FXOS8700_1F_LABEL
#define CONFIG_FXOS8700_I2C_NAME DT_NXP_KINETIS_I2C_40067000_NXP_FXOS8700_1F_BUS_NAME #define DT_FXOS8700_I2C_NAME DT_NXP_KINETIS_I2C_40067000_NXP_FXOS8700_1F_BUS_NAME
#define CONFIG_FXOS8700_I2C_ADDRESS DT_NXP_KINETIS_I2C_40067000_NXP_FXOS8700_1F_BASE_ADDRESS #define DT_FXOS8700_I2C_ADDRESS DT_NXP_KINETIS_I2C_40067000_NXP_FXOS8700_1F_BASE_ADDRESS
#define CONFIG_FXOS8700_GPIO_NAME DT_NXP_KINETIS_I2C_40067000_NXP_FXOS8700_1F_INT1_GPIOS_CONTROLLER #define DT_FXOS8700_GPIO_NAME DT_NXP_KINETIS_I2C_40067000_NXP_FXOS8700_1F_INT1_GPIOS_CONTROLLER
#define CONFIG_FXOS8700_GPIO_PIN DT_NXP_KINETIS_I2C_40067000_NXP_FXOS8700_1F_INT1_GPIOS_PIN #define DT_FXOS8700_GPIO_PIN DT_NXP_KINETIS_I2C_40067000_NXP_FXOS8700_1F_INT1_GPIOS_PIN

26
boards/arm/hexiwear_k64/dts_fixup.h
View file

@ -1,15 +1,15 @@
#define CONFIG_FXOS8700_NAME DT_NXP_KINETIS_I2C_40067000_NXP_FXOS8700_1E_LABEL #define DT_FXOS8700_NAME DT_NXP_KINETIS_I2C_40067000_NXP_FXOS8700_1E_LABEL
#define CONFIG_FXOS8700_I2C_NAME DT_NXP_KINETIS_I2C_40067000_NXP_FXOS8700_1E_BUS_NAME #define DT_FXOS8700_I2C_NAME DT_NXP_KINETIS_I2C_40067000_NXP_FXOS8700_1E_BUS_NAME
#define CONFIG_FXOS8700_I2C_ADDRESS DT_NXP_KINETIS_I2C_40067000_NXP_FXOS8700_1E_BASE_ADDRESS #define DT_FXOS8700_I2C_ADDRESS DT_NXP_KINETIS_I2C_40067000_NXP_FXOS8700_1E_BASE_ADDRESS
#define CONFIG_FXOS8700_GPIO_NAME DT_NXP_KINETIS_I2C_40067000_NXP_FXOS8700_1E_INT2_GPIOS_CONTROLLER #define DT_FXOS8700_GPIO_NAME DT_NXP_KINETIS_I2C_40067000_NXP_FXOS8700_1E_INT2_GPIOS_CONTROLLER
#define CONFIG_FXOS8700_GPIO_PIN DT_NXP_KINETIS_I2C_40067000_NXP_FXOS8700_1E_INT2_GPIOS_PIN #define DT_FXOS8700_GPIO_PIN DT_NXP_KINETIS_I2C_40067000_NXP_FXOS8700_1E_INT2_GPIOS_PIN
#define CONFIG_FXAS21002_NAME DT_NXP_KINETIS_I2C_40067000_NXP_FXAS21002_20_LABEL #define DT_FXAS21002_NAME DT_NXP_KINETIS_I2C_40067000_NXP_FXAS21002_20_LABEL
#define CONFIG_FXAS21002_I2C_NAME DT_NXP_KINETIS_I2C_40067000_NXP_FXAS21002_20_BUS_NAME #define DT_FXAS21002_I2C_NAME DT_NXP_KINETIS_I2C_40067000_NXP_FXAS21002_20_BUS_NAME
#define CONFIG_FXAS21002_I2C_ADDRESS DT_NXP_KINETIS_I2C_40067000_NXP_FXAS21002_20_BASE_ADDRESS #define DT_FXAS21002_I2C_ADDRESS DT_NXP_KINETIS_I2C_40067000_NXP_FXAS21002_20_BASE_ADDRESS
#define CONFIG_FXAS21002_GPIO_NAME DT_NXP_KINETIS_I2C_40067000_NXP_FXAS21002_20_INT2_GPIOS_CONTROLLER #define DT_FXAS21002_GPIO_NAME DT_NXP_KINETIS_I2C_40067000_NXP_FXAS21002_20_INT2_GPIOS_CONTROLLER
#define CONFIG_FXAS21002_GPIO_PIN DT_NXP_KINETIS_I2C_40067000_NXP_FXAS21002_20_INT2_GPIOS_PIN #define DT_FXAS21002_GPIO_PIN DT_NXP_KINETIS_I2C_40067000_NXP_FXAS21002_20_INT2_GPIOS_PIN
#define CONFIG_MAX30101_NAME DT_NXP_KINETIS_I2C_40066000_MAX_MAX30101_57_LABEL #define DT_MAX30101_NAME DT_NXP_KINETIS_I2C_40066000_MAX_MAX30101_57_LABEL
#define CONFIG_MAX30101_I2C_NAME DT_NXP_KINETIS_I2C_40066000_MAX_MAX30101_57_BUS_NAME #define DT_MAX30101_I2C_NAME DT_NXP_KINETIS_I2C_40066000_MAX_MAX30101_57_BUS_NAME
#define CONFIG_MAX30101_I2C_ADDRESS DT_NXP_KINETIS_I2C_40066000_MAX_MAX30101_57_BASE_ADDRESS #define DT_MAX30101_I2C_ADDRESS DT_NXP_KINETIS_I2C_40066000_MAX_MAX30101_57_BASE_ADDRESS

108
boards/arm/mps2_an385/dts_fixup.h
View file

@ -1,81 +1,81 @@
/* SoC level DTS fixup file */ /* SoC level DTS fixup file */
#define CONFIG_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS #define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
/* CMSDK APB Timers */ /* CMSDK APB Timers */
#define CMSDK_APB_TIMER0 DT_ARM_CMSDK_TIMER_40000000_BASE_ADDRESS #define DT_CMSDK_APB_TIMER0 DT_ARM_CMSDK_TIMER_40000000_BASE_ADDRESS
#define CMSDK_APB_TIMER_0_IRQ DT_ARM_CMSDK_TIMER_40000000_IRQ_0 #define DT_CMSDK_APB_TIMER_0_IRQ DT_ARM_CMSDK_TIMER_40000000_IRQ_0
#define CMSDK_APB_TIMER1 DT_ARM_CMSDK_TIMER_40001000_BASE_ADDRESS #define DT_CMSDK_APB_TIMER1 DT_ARM_CMSDK_TIMER_40001000_BASE_ADDRESS
#define CMSDK_APB_TIMER_1_IRQ IRQ_TIMER1 DT_ARM_CMSDK_TIMER_40001000_IRQ_0 #define DT_CMSDK_APB_TIMER_1_IRQ IRQ_TIMER1 DT_ARM_CMSDK_TIMER_40001000_IRQ_0
/* CMSDK APB Dual Timer */ /* CMSDK APB Dual Timer */
#define CMSDK_APB_DTIMER DT_ARM_CMSDK_DTIMER_40002000_BASE_ADDRESS #define DT_CMSDK_APB_DTIMER DT_ARM_CMSDK_DTIMER_40002000_BASE_ADDRESS
#define CMSDK_APB_DUALTIMER_IRQ DT_ARM_CMSDK_DTIMER_40002000_IRQ_0 #define DT_CMSDK_APB_DUALTIMER_IRQ DT_ARM_CMSDK_DTIMER_40002000_IRQ_0
/* CMSDK APB Universal Asynchronous Receiver-Transmitter (UART) */ /* CMSDK APB Universal Asynchronous Receiver-Transmitter (UART) */
#define CMSDK_APB_UART0 DT_ARM_CMSDK_UART_40004000_BASE_ADDRESS #define DT_CMSDK_APB_UART0 DT_ARM_CMSDK_UART_40004000_BASE_ADDRESS
#define CMSDK_APB_UART_0_IRQ_TX DT_ARM_CMSDK_UART_40004000_IRQ_0 #define DT_CMSDK_APB_UART_0_IRQ_TX DT_ARM_CMSDK_UART_40004000_IRQ_0
#define CMSDK_APB_UART_0_IRQ_RX DT_ARM_CMSDK_UART_40004000_IRQ_1 #define DT_CMSDK_APB_UART_0_IRQ_RX DT_ARM_CMSDK_UART_40004000_IRQ_1
#define CONFIG_UART_CMSDK_APB_PORT0_IRQ_PRI DT_ARM_CMSDK_UART_40004000_IRQ_0_PRIORITY #define DT_UART_CMSDK_APB_PORT0_IRQ_PRI DT_ARM_CMSDK_UART_40004000_IRQ_0_PRIORITY
#define CONFIG_UART_CMSDK_APB_PORT0_BAUD_RATE DT_ARM_CMSDK_UART_40004000_CURRENT_SPEED #define DT_UART_CMSDK_APB_PORT0_BAUD_RATE DT_ARM_CMSDK_UART_40004000_CURRENT_SPEED
#define CONFIG_UART_CMSDK_APB_PORT0_NAME DT_ARM_CMSDK_UART_40004000_LABEL #define DT_UART_CMSDK_APB_PORT0_NAME DT_ARM_CMSDK_UART_40004000_LABEL
#define CMSDK_APB_UART1 DT_ARM_CMSDK_UART_40005000_BASE_ADDRESS #define DT_CMSDK_APB_UART1 DT_ARM_CMSDK_UART_40005000_BASE_ADDRESS
#define CMSDK_APB_UART_1_IRQ_TX DT_ARM_CMSDK_UART_40005000_IRQ_0 #define DT_CMSDK_APB_UART_1_IRQ_TX DT_ARM_CMSDK_UART_40005000_IRQ_0
#define CMSDK_APB_UART_1_IRQ_RX DT_ARM_CMSDK_UART_40005000_IRQ_1 #define DT_CMSDK_APB_UART_1_IRQ_RX DT_ARM_CMSDK_UART_40005000_IRQ_1
#define CONFIG_UART_CMSDK_APB_PORT1_IRQ_PRI DT_ARM_CMSDK_UART_40005000_IRQ_0_PRIORITY #define DT_UART_CMSDK_APB_PORT1_IRQ_PRI DT_ARM_CMSDK_UART_40005000_IRQ_0_PRIORITY
#define CONFIG_UART_CMSDK_APB_PORT1_BAUD_RATE DT_ARM_CMSDK_UART_40005000_CURRENT_SPEED #define DT_UART_CMSDK_APB_PORT1_BAUD_RATE DT_ARM_CMSDK_UART_40005000_CURRENT_SPEED
#define CONFIG_UART_CMSDK_APB_PORT1_NAME DT_ARM_CMSDK_UART_40005000_LABEL #define DT_UART_CMSDK_APB_PORT1_NAME DT_ARM_CMSDK_UART_40005000_LABEL
#define CMSDK_APB_UART2 DT_ARM_CMSDK_UART_40006000_BASE_ADDRESS #define DT_CMSDK_APB_UART2 DT_ARM_CMSDK_UART_40006000_BASE_ADDRESS
#define CMSDK_APB_UART_2_IRQ_TX DT_ARM_CMSDK_UART_40006000_IRQ_0 #define DT_CMSDK_APB_UART_2_IRQ_TX DT_ARM_CMSDK_UART_40006000_IRQ_0
#define CMSDK_APB_UART_2_IRQ_RX DT_ARM_CMSDK_UART_40006000_IRQ_1 #define DT_CMSDK_APB_UART_2_IRQ_RX DT_ARM_CMSDK_UART_40006000_IRQ_1
#define CONFIG_UART_CMSDK_APB_PORT2_IRQ_PRI DT_ARM_CMSDK_UART_40006000_IRQ_0_PRIORITY #define DT_UART_CMSDK_APB_PORT2_IRQ_PRI DT_ARM_CMSDK_UART_40006000_IRQ_0_PRIORITY
#define CONFIG_UART_CMSDK_APB_PORT2_BAUD_RATE DT_ARM_CMSDK_UART_40006000_CURRENT_SPEED #define DT_UART_CMSDK_APB_PORT2_BAUD_RATE DT_ARM_CMSDK_UART_40006000_CURRENT_SPEED
#define CONFIG_UART_CMSDK_APB_PORT2_NAME DT_ARM_CMSDK_UART_40006000_LABEL #define DT_UART_CMSDK_APB_PORT2_NAME DT_ARM_CMSDK_UART_40006000_LABEL
#define CMSDK_APB_UART3 DT_ARM_CMSDK_UART_40007000_BASE_ADDRESS #define DT_CMSDK_APB_UART3 DT_ARM_CMSDK_UART_40007000_BASE_ADDRESS
#define CMSDK_APB_UART_3_IRQ_TX DT_ARM_CMSDK_UART_40007000_IRQ_0 #define DT_CMSDK_APB_UART_3_IRQ_TX DT_ARM_CMSDK_UART_40007000_IRQ_0
#define CMSDK_APB_UART_3_IRQ_RX DT_ARM_CMSDK_UART_40007000_IRQ_1 #define DT_CMSDK_APB_UART_3_IRQ_RX DT_ARM_CMSDK_UART_40007000_IRQ_1
#define CONFIG_UART_CMSDK_APB_PORT3_IRQ_PRI DT_ARM_CMSDK_UART_40007000_IRQ_0_PRIORITY #define DT_UART_CMSDK_APB_PORT3_IRQ_PRI DT_ARM_CMSDK_UART_40007000_IRQ_0_PRIORITY
#define CONFIG_UART_CMSDK_APB_PORT3_BAUD_RATE DT_ARM_CMSDK_UART_40007000_CURRENT_SPEED #define DT_UART_CMSDK_APB_PORT3_BAUD_RATE DT_ARM_CMSDK_UART_40007000_CURRENT_SPEED
#define CONFIG_UART_CMSDK_APB_PORT3_NAME DT_ARM_CMSDK_UART_40007000_LABEL #define DT_UART_CMSDK_APB_PORT3_NAME DT_ARM_CMSDK_UART_40007000_LABEL
#define CMSDK_APB_UART4 DT_ARM_CMSDK_UART_40009000_BASE_ADDRESS #define DT_CMSDK_APB_UART4 DT_ARM_CMSDK_UART_40009000_BASE_ADDRESS
#define CMSDK_APB_UART_4_IRQ_TX DT_ARM_CMSDK_UART_40009000_IRQ_0 #define DT_CMSDK_APB_UART_4_IRQ_TX DT_ARM_CMSDK_UART_40009000_IRQ_0
#define CMSDK_APB_UART_4_IRQ_RX DT_ARM_CMSDK_UART_40009000_IRQ_1 #define DT_CMSDK_APB_UART_4_IRQ_RX DT_ARM_CMSDK_UART_40009000_IRQ_1
#define CONFIG_UART_CMSDK_APB_PORT4_IRQ_PRI DT_ARM_CMSDK_UART_40009000_IRQ_0_PRIORITY #define DT_UART_CMSDK_APB_PORT4_IRQ_PRI DT_ARM_CMSDK_UART_40009000_IRQ_0_PRIORITY
#define CONFIG_UART_CMSDK_APB_PORT4_BAUD_RATE DT_ARM_CMSDK_UART_40009000_CURRENT_SPEED #define DT_UART_CMSDK_APB_PORT4_BAUD_RATE DT_ARM_CMSDK_UART_40009000_CURRENT_SPEED
#define CONFIG_UART_CMSDK_APB_PORT4_NAME DT_ARM_CMSDK_UART_40009000_LABEL #define DT_UART_CMSDK_APB_PORT4_NAME DT_ARM_CMSDK_UART_40009000_LABEL
/* CMSDK APB Watchdog */ /* CMSDK APB Watchdog */
#define CMSDK_APB_WDOG DT_ARM_CMSDK_WATCHDOG_40008000_BASE_ADDRESS #define DT_CMSDK_APB_WDOG DT_ARM_CMSDK_WATCHDOG_40008000_BASE_ADDRESS
/* CMSDK AHB General Purpose Input/Output (GPIO) */ /* CMSDK AHB General Purpose Input/Output (GPIO) */
#define CMSDK_AHB_GPIO0 DT_ARM_CMSDK_GPIO_40010000_BASE_ADDRESS #define DT_CMSDK_AHB_GPIO0 DT_ARM_CMSDK_GPIO_40010000_BASE_ADDRESS
#define IRQ_PORT0_ALL DT_ARM_CMSDK_GPIO_40010000_IRQ_0 #define DT_IRQ_PORT0_ALL DT_ARM_CMSDK_GPIO_40010000_IRQ_0
#define CMSDK_AHB_GPIO1 DT_ARM_CMSDK_GPIO_40011000_BASE_ADDRESS #define DT_CMSDK_AHB_GPIO1 DT_ARM_CMSDK_GPIO_40011000_BASE_ADDRESS
#define IRQ_PORT1_ALL DT_ARM_CMSDK_GPIO_40011000_IRQ_0 #define DT_IRQ_PORT1_ALL DT_ARM_CMSDK_GPIO_40011000_IRQ_0
#define CMSDK_AHB_GPIO2 DT_ARM_CMSDK_GPIO_40012000_BASE_ADDRESS #define DT_CMSDK_AHB_GPIO2 DT_ARM_CMSDK_GPIO_40012000_BASE_ADDRESS
#define IRQ_PORT2_ALL DT_ARM_CMSDK_GPIO_40012000_IRQ_0 #define DT_IRQ_PORT2_ALL DT_ARM_CMSDK_GPIO_40012000_IRQ_0
#define CMSDK_AHB_GPIO3 DT_ARM_CMSDK_GPIO_40013000_BASE_ADDRESS #define DT_CMSDK_AHB_GPIO3 DT_ARM_CMSDK_GPIO_40013000_BASE_ADDRESS
#define IRQ_PORT3_ALL DT_ARM_CMSDK_GPIO_40013000_IRQ_0 #define DT_IRQ_PORT3_ALL DT_ARM_CMSDK_GPIO_40013000_IRQ_0
/* I2C SBCon */ /* I2C SBCon */
#define I2C_SBCON_0_BASE_ADDR DT_ARM_VERSATILE_I2C_40022000_BASE_ADDRESS #define DT_I2C_SBCON_0_BASE_ADDR DT_ARM_VERSATILE_I2C_40022000_BASE_ADDRESS
#define I2C_SBCON_0_NAME DT_ARM_VERSATILE_I2C_40022000_LABEL #define DT_I2C_SBCON_0_NAME DT_ARM_VERSATILE_I2C_40022000_LABEL
#define I2C_SBCON_1_BASE_ADDR DT_ARM_VERSATILE_I2C_40023000_BASE_ADDRESS #define DT_I2C_SBCON_1_BASE_ADDR DT_ARM_VERSATILE_I2C_40023000_BASE_ADDRESS
#define I2C_SBCON_1_NAME DT_ARM_VERSATILE_I2C_40023000_LABEL #define DT_I2C_SBCON_1_NAME DT_ARM_VERSATILE_I2C_40023000_LABEL
#define I2C_SBCON_2_BASE_ADDR DT_ARM_VERSATILE_I2C_40029000_BASE_ADDRESS #define DT_I2C_SBCON_2_BASE_ADDR DT_ARM_VERSATILE_I2C_40029000_BASE_ADDRESS
#define I2C_SBCON_2_NAME DT_ARM_VERSATILE_I2C_40029000_LABEL #define DT_I2C_SBCON_2_NAME DT_ARM_VERSATILE_I2C_40029000_LABEL
#define I2C_SBCON_3_BASE_ADDR DT_ARM_VERSATILE_I2C_4002A000_BASE_ADDRESS #define DT_I2C_SBCON_3_BASE_ADDR DT_ARM_VERSATILE_I2C_4002A000_BASE_ADDRESS
#define I2C_SBCON_3_NAME DT_ARM_VERSATILE_I2C_4002A000_LABEL #define DT_I2C_SBCON_3_NAME DT_ARM_VERSATILE_I2C_4002A000_LABEL
/* End of SoC Level DTS fixup file */ /* End of SoC Level DTS fixup file */

8
boards/arm/mps2_an385/pinmux.c
View file

@ -32,13 +32,13 @@
*/ */
#define CMSDK_AHB_GPIO0_DEV \ #define CMSDK_AHB_GPIO0_DEV \
((volatile struct gpio_cmsdk_ahb *)CMSDK_AHB_GPIO0) ((volatile struct gpio_cmsdk_ahb *)DT_CMSDK_AHB_GPIO0)
#define CMSDK_AHB_GPIO1_DEV \ #define CMSDK_AHB_GPIO1_DEV \
((volatile struct gpio_cmsdk_ahb *)CMSDK_AHB_GPIO1) ((volatile struct gpio_cmsdk_ahb *)DT_CMSDK_AHB_GPIO1)
#define CMSDK_AHB_GPIO2_DEV \ #define CMSDK_AHB_GPIO2_DEV \
((volatile struct gpio_cmsdk_ahb *)CMSDK_AHB_GPIO2) ((volatile struct gpio_cmsdk_ahb *)DT_CMSDK_AHB_GPIO2)
#define CMSDK_AHB_GPIO3_DEV \ #define CMSDK_AHB_GPIO3_DEV \
((volatile struct gpio_cmsdk_ahb *)CMSDK_AHB_GPIO3) ((volatile struct gpio_cmsdk_ahb *)DT_CMSDK_AHB_GPIO3)
/* /*
* This is the mapping from the ARM MPS2 AN385 Board pins to GPIO * This is the mapping from the ARM MPS2 AN385 Board pins to GPIO

2
boards/arm/nrf52_pca20020/board.c
View file

@ -49,7 +49,7 @@ static int pwr_ctrl_init(struct device *dev)
#endif #endif
static const struct pwr_ctrl_cfg vdd_pwr_ctrl_cfg = { static const struct pwr_ctrl_cfg vdd_pwr_ctrl_cfg = {
.port = CONFIG_GPIO_P0_DEV_NAME, .port = DT_GPIO_P0_DEV_NAME,
.pin = VDD_PWR_CTRL_GPIO_PIN, .pin = VDD_PWR_CTRL_GPIO_PIN,
}; };

18
boards/arm/nrf52_pca20020/dts_fixup.h
View file

@ -2,14 +2,14 @@
#define CONFIG_GPIO_SX1509B_I2C_ADDR DT_NORDIC_NRF_I2C_40003000_SEMTECH_SX1509B_3E_BASE_ADDRESS #define CONFIG_GPIO_SX1509B_I2C_ADDR DT_NORDIC_NRF_I2C_40003000_SEMTECH_SX1509B_3E_BASE_ADDRESS
#define CONFIG_GPIO_SX1509B_I2C_MASTER_DEV_NAME DT_NORDIC_NRF_I2C_40003000_SEMTECH_SX1509B_3E_BUS_NAME #define CONFIG_GPIO_SX1509B_I2C_MASTER_DEV_NAME DT_NORDIC_NRF_I2C_40003000_SEMTECH_SX1509B_3E_BUS_NAME
#define CONFIG_HTS221_NAME DT_NORDIC_NRF_I2C_40003000_ST_HTS221_5F_LABEL #define DT_HTS221_NAME DT_NORDIC_NRF_I2C_40003000_ST_HTS221_5F_LABEL
#define CONFIG_HTS221_I2C_MASTER_DEV_NAME DT_NORDIC_NRF_I2C_40003000_ST_HTS221_5F_BUS_NAME #define DT_HTS221_I2C_MASTER_DEV_NAME DT_NORDIC_NRF_I2C_40003000_ST_HTS221_5F_BUS_NAME
#define CONFIG_HTS221_I2C_ADDR DT_NORDIC_NRF_I2C_40003000_ST_HTS221_5F_BASE_ADDRESS #define DT_HTS221_I2C_ADDR DT_NORDIC_NRF_I2C_40003000_ST_HTS221_5F_BASE_ADDRESS
#define CONFIG_CCS811_NAME DT_NORDIC_NRF_I2C_40003000_AMS_CCS811_5A_LABEL #define DT_CCS811_NAME DT_NORDIC_NRF_I2C_40003000_AMS_CCS811_5A_LABEL
#define CONFIG_CCS811_I2C_MASTER_DEV_NAME DT_NORDIC_NRF_I2C_40003000_AMS_CCS811_5A_BUS_NAME #define DT_CCS811_I2C_MASTER_DEV_NAME DT_NORDIC_NRF_I2C_40003000_AMS_CCS811_5A_BUS_NAME
#define CONFIG_CCS811_I2C_ADDR DT_NORDIC_NRF_I2C_40003000_AMS_CCS811_5A_BASE_ADDRESS #define DT_CCS811_I2C_ADDR DT_NORDIC_NRF_I2C_40003000_AMS_CCS811_5A_BASE_ADDRESS
#define CONFIG_LPS22HB_DEV_NAME DT_NORDIC_NRF_I2C_40003000_ST_LPS22HB_PRESS_5C_LABEL #define DT_LPS22HB_DEV_NAME DT_NORDIC_NRF_I2C_40003000_ST_LPS22HB_PRESS_5C_LABEL
#define CONFIG_LPS22HB_I2C_MASTER_DEV_NAME DT_NORDIC_NRF_I2C_40003000_ST_LPS22HB_PRESS_5C_BUS_NAME #define DT_LPS22HB_I2C_MASTER_DEV_NAME DT_NORDIC_NRF_I2C_40003000_ST_LPS22HB_PRESS_5C_BUS_NAME
#define CONFIG_LPS22HB_I2C_ADDR DT_NORDIC_NRF_I2C_40003000_ST_LPS22HB_PRESS_5C_BASE_ADDRESS #define DT_LPS22HB_I2C_ADDR DT_NORDIC_NRF_I2C_40003000_ST_LPS22HB_PRESS_5C_BASE_ADDRESS

6
boards/arm/olimexino_stm32/dts_fixup.h
View file

@ -3,6 +3,6 @@
* are modified to handle the generated information, or the mapping of * are modified to handle the generated information, or the mapping of
* generated data matches the driver definitions. * generated data matches the driver definitions.
*/ */
#define CONFIG_USB_DC_STM32_DISCONN_GPIO_PORT_NAME DT_ST_STM32_USB_40005C00_DISCONNECT_GPIOS_CONTROLLER #define DT_USB_DC_STM32_DISCONN_GPIO_PORT_NAME DT_ST_STM32_USB_40005C00_DISCONNECT_GPIOS_CONTROLLER
#define CONFIG_USB_DC_STM32_DISCONN_PIN DT_ST_STM32_USB_40005C00_DISCONNECT_GPIOS_PIN #define DT_USB_DC_STM32_DISCONN_PIN DT_ST_STM32_USB_40005C00_DISCONNECT_GPIOS_PIN
#define CONFIG_USB_DC_STM32_DISCONN_PIN_LEVEL DT_ST_STM32_USB_40005C00_DISCONNECT_GPIOS_FLAGS #define DT_USB_DC_STM32_DISCONN_PIN_LEVEL DT_ST_STM32_USB_40005C00_DISCONNECT_GPIOS_FLAGS

58
boards/arm/reel_board/dts_fixup.h
View file

@ -1,33 +1,33 @@
#define CONFIG_FXOS8700_NAME DT_NORDIC_NRF_I2C_40003000_NXP_FXOS8700_1D_LABEL #define DT_FXOS8700_NAME DT_NORDIC_NRF_I2C_40003000_NXP_FXOS8700_1D_LABEL
#define CONFIG_FXOS8700_I2C_NAME DT_NORDIC_NRF_I2C_40003000_NXP_FXOS8700_1D_BUS_NAME #define DT_FXOS8700_I2C_NAME DT_NORDIC_NRF_I2C_40003000_NXP_FXOS8700_1D_BUS_NAME
#define CONFIG_FXOS8700_I2C_ADDRESS DT_NORDIC_NRF_I2C_40003000_NXP_FXOS8700_1D_BASE_ADDRESS #define DT_FXOS8700_I2C_ADDRESS DT_NORDIC_NRF_I2C_40003000_NXP_FXOS8700_1D_BASE_ADDRESS
#define CONFIG_FXOS8700_GPIO_NAME DT_NORDIC_NRF_I2C_40003000_NXP_FXOS8700_1D_INT1_GPIOS_CONTROLLER #define DT_FXOS8700_GPIO_NAME DT_NORDIC_NRF_I2C_40003000_NXP_FXOS8700_1D_INT1_GPIOS_CONTROLLER
#define CONFIG_FXOS8700_GPIO_PIN DT_NORDIC_NRF_I2C_40003000_NXP_FXOS8700_1D_INT1_GPIOS_PIN #define DT_FXOS8700_GPIO_PIN DT_NORDIC_NRF_I2C_40003000_NXP_FXOS8700_1D_INT1_GPIOS_PIN
#define CONFIG_HDC1008_NAME DT_NORDIC_NRF_I2C_40003000_TI_HDC1008_43_LABEL #define DT_HDC1008_NAME DT_NORDIC_NRF_I2C_40003000_TI_HDC1008_43_LABEL
#define CONFIG_HDC1008_I2C_MASTER_DEV_NAME DT_NORDIC_NRF_I2C_40003000_TI_HDC1008_43_BUS_NAME #define DT_HDC1008_I2C_MASTER_DEV_NAME DT_NORDIC_NRF_I2C_40003000_TI_HDC1008_43_BUS_NAME
#define CONFIG_HDC1008_I2C_ADDR DT_NORDIC_NRF_I2C_40003000_TI_HDC1008_43_BASE_ADDRESS #define DT_HDC1008_I2C_ADDR DT_NORDIC_NRF_I2C_40003000_TI_HDC1008_43_BASE_ADDRESS
#define CONFIG_HDC1008_GPIO_DEV_NAME DT_NORDIC_NRF_I2C_40003000_TI_HDC1008_43_DRDY_GPIOS_CONTROLLER #define DT_HDC1008_GPIO_DEV_NAME DT_NORDIC_NRF_I2C_40003000_TI_HDC1008_43_DRDY_GPIOS_CONTROLLER
#define CONFIG_HDC1008_GPIO_PIN_NUM DT_NORDIC_NRF_I2C_40003000_TI_HDC1008_43_DRDY_GPIOS_PIN #define DT_HDC1008_GPIO_PIN_NUM DT_NORDIC_NRF_I2C_40003000_TI_HDC1008_43_DRDY_GPIOS_PIN
#define CONFIG_HDC1008_GPIO_FLAGS DT_NORDIC_NRF_I2C_40003000_TI_HDC1008_43_DRDY_GPIOS_FLAGS #define DT_HDC1008_GPIO_FLAGS DT_NORDIC_NRF_I2C_40003000_TI_HDC1008_43_DRDY_GPIOS_FLAGS
#define CONFIG_APDS9960_DRV_NAME DT_NORDIC_NRF_I2C_40003000_AVAGO_APDS9960_29_LABEL #define DT_APDS9960_DRV_NAME DT_NORDIC_NRF_I2C_40003000_AVAGO_APDS9960_29_LABEL
#define CONFIG_APDS9960_I2C_DEV_NAME DT_NORDIC_NRF_I2C_40003000_AVAGO_APDS9960_29_BUS_NAME #define DT_APDS9960_I2C_DEV_NAME DT_NORDIC_NRF_I2C_40003000_AVAGO_APDS9960_29_BUS_NAME
#define CONFIG_APDS9960_GPIO_DEV_NAME DT_NORDIC_NRF_I2C_40003000_AVAGO_APDS9960_29_INT_GPIOS_CONTROLLER #define DT_APDS9960_GPIO_DEV_NAME DT_NORDIC_NRF_I2C_40003000_AVAGO_APDS9960_29_INT_GPIOS_CONTROLLER
#define CONFIG_APDS9960_GPIO_PIN_NUM DT_NORDIC_NRF_I2C_40003000_AVAGO_APDS9960_29_INT_GPIOS_PIN #define DT_APDS9960_GPIO_PIN_NUM DT_NORDIC_NRF_I2C_40003000_AVAGO_APDS9960_29_INT_GPIOS_PIN
#define CONFIG_SSD1673_DEV_NAME DT_NORDIC_NRF_SPI_4002B000_SOLOMON_SSD1673FB_SPI_0_LABEL #define DT_SSD1673_DEV_NAME DT_NORDIC_NRF_SPI_4002B000_SOLOMON_SSD1673FB_SPI_0_LABEL
#define CONFIG_SSD1673_SPI_FREQ DT_NORDIC_NRF_SPI_4002B000_SOLOMON_SSD1673FB_SPI_0_SPI_MAX_FREQUENCY #define DT_SSD1673_SPI_FREQ DT_NORDIC_NRF_SPI_4002B000_SOLOMON_SSD1673FB_SPI_0_SPI_MAX_FREQUENCY
#define CONFIG_SSD1673_SPI_DEV_NAME DT_NORDIC_NRF_SPI_4002B000_SOLOMON_SSD1673FB_SPI_0_BUS_NAME #define DT_SSD1673_SPI_DEV_NAME DT_NORDIC_NRF_SPI_4002B000_SOLOMON_SSD1673FB_SPI_0_BUS_NAME
#define CONFIG_SSD1673_SPI_SLAVE_NUMBER DT_NORDIC_NRF_SPI_4002B000_SOLOMON_SSD1673FB_SPI_0_BASE_ADDRESS #define DT_SSD1673_SPI_SLAVE_NUMBER DT_NORDIC_NRF_SPI_4002B000_SOLOMON_SSD1673FB_SPI_0_BASE_ADDRESS
#define CONFIG_SSD1673_SPI_GPIO_CS y #define DT_SSD1673_SPI_GPIO_CS y
#define CONFIG_SSD1673_SPI_GPIO_CS_DRV_NAME DT_NORDIC_NRF_SPI_4002B000_CS_GPIOS_CONTROLLER #define DT_SSD1673_SPI_GPIO_CS_DRV_NAME DT_NORDIC_NRF_SPI_4002B000_CS_GPIOS_CONTROLLER
#define CONFIG_SSD1673_SPI_GPIO_CS_PIN DT_NORDIC_NRF_SPI_4002B000_CS_GPIOS_PIN #define DT_SSD1673_SPI_GPIO_CS_PIN DT_NORDIC_NRF_SPI_4002B000_CS_GPIOS_PIN
#define CONFIG_SSD1673_RESET_GPIO_PORT_NAME DT_NORDIC_NRF_SPI_4002B000_SOLOMON_SSD1673FB_SPI_0_RESET_GPIOS_CONTROLLER #define DT_SSD1673_RESET_GPIO_PORT_NAME DT_NORDIC_NRF_SPI_4002B000_SOLOMON_SSD1673FB_SPI_0_RESET_GPIOS_CONTROLLER
#define CONFIG_SSD1673_RESET_PIN DT_NORDIC_NRF_SPI_4002B000_SOLOMON_SSD1673FB_SPI_0_RESET_GPIOS_PIN #define DT_SSD1673_RESET_PIN DT_NORDIC_NRF_SPI_4002B000_SOLOMON_SSD1673FB_SPI_0_RESET_GPIOS_PIN
#define CONFIG_SSD1673_DC_GPIO_PORT_NAME DT_NORDIC_NRF_SPI_4002B000_SOLOMON_SSD1673FB_SPI_0_DC_GPIOS_CONTROLLER #define DT_SSD1673_DC_GPIO_PORT_NAME DT_NORDIC_NRF_SPI_4002B000_SOLOMON_SSD1673FB_SPI_0_DC_GPIOS_CONTROLLER
#define CONFIG_SSD1673_DC_PIN DT_NORDIC_NRF_SPI_4002B000_SOLOMON_SSD1673FB_SPI_0_DC_GPIOS_PIN #define DT_SSD1673_DC_PIN DT_NORDIC_NRF_SPI_4002B000_SOLOMON_SSD1673FB_SPI_0_DC_GPIOS_PIN
#define CONFIG_SSD1673_BUSY_GPIO_PORT_NAME DT_NORDIC_NRF_SPI_4002B000_SOLOMON_SSD1673FB_SPI_0_BUSY_GPIOS_CONTROLLER #define DT_SSD1673_BUSY_GPIO_PORT_NAME DT_NORDIC_NRF_SPI_4002B000_SOLOMON_SSD1673FB_SPI_0_BUSY_GPIOS_CONTROLLER
#define CONFIG_SSD1673_BUSY_PIN DT_NORDIC_NRF_SPI_4002B000_SOLOMON_SSD1673FB_SPI_0_BUSY_GPIOS_PIN #define DT_SSD1673_BUSY_PIN DT_NORDIC_NRF_SPI_4002B000_SOLOMON_SSD1673FB_SPI_0_BUSY_GPIOS_PIN
#define CONFIG_SSD1673_ORIENTATION_FLIPPED DT_NORDIC_NRF_SPI_4002B000_SOLOMON_SSD1673FB_SPI_0_ORIENTATION_FLIPPED #define DT_SSD1673_ORIENTATION_FLIPPED DT_NORDIC_NRF_SPI_4002B000_SOLOMON_SSD1673FB_SPI_0_ORIENTATION_FLIPPED

12
boards/arm/stm32f3_disco/dts_fixup.h
View file

@ -4,10 +4,10 @@
* generated data matches the driver definitions. * generated data matches the driver definitions.
*/ */
#define CONFIG_LSM303DLHC_ACCEL_NAME DT_ST_STM32_I2C_V2_40005400_ST_LSM303DLHC_ACCEL_19_LABEL #define DT_LSM303DLHC_ACCEL_NAME DT_ST_STM32_I2C_V2_40005400_ST_LSM303DLHC_ACCEL_19_LABEL
#define CONFIG_LSM303DLHC_ACCEL_I2C_ADDR DT_ST_STM32_I2C_V2_40005400_ST_LSM303DLHC_ACCEL_19_BASE_ADDRESS #define DT_LSM303DLHC_ACCEL_I2C_ADDR DT_ST_STM32_I2C_V2_40005400_ST_LSM303DLHC_ACCEL_19_BASE_ADDRESS
#define CONFIG_LSM303DLHC_ACCEL_I2C_MASTER_DEV DT_ST_STM32_I2C_V2_40005400_ST_LSM303DLHC_ACCEL_19_BUS_NAME #define DT_LSM303DLHC_ACCEL_I2C_MASTER_DEV DT_ST_STM32_I2C_V2_40005400_ST_LSM303DLHC_ACCEL_19_BUS_NAME
#define CONFIG_LSM303DLHC_MAGN_NAME DT_ST_STM32_I2C_V2_40005400_ST_LSM303DLHC_MAGN_1E_LABEL #define DT_LSM303DLHC_MAGN_NAME DT_ST_STM32_I2C_V2_40005400_ST_LSM303DLHC_MAGN_1E_LABEL
#define CONFIG_LSM303DLHC_MAGN_I2C_ADDR DT_ST_STM32_I2C_V2_40005400_ST_LSM303DLHC_MAGN_1E_BASE_ADDRESS #define DT_LSM303DLHC_MAGN_I2C_ADDR DT_ST_STM32_I2C_V2_40005400_ST_LSM303DLHC_MAGN_1E_BASE_ADDRESS
#define CONFIG_LSM303DLHC_MAGN_I2C_MASTER_DEV DT_ST_STM32_I2C_V2_40005400_ST_LSM303DLHC_MAGN_1E_BUS_NAME #define DT_LSM303DLHC_MAGN_I2C_MASTER_DEV DT_ST_STM32_I2C_V2_40005400_ST_LSM303DLHC_MAGN_1E_BUS_NAME

4
boards/arm/v2m_beetle/pinmux.c
View file

@ -33,9 +33,9 @@
*/ */
#define CMSDK_AHB_GPIO0_DEV \ #define CMSDK_AHB_GPIO0_DEV \
((volatile struct gpio_cmsdk_ahb *)CMSDK_AHB_GPIO0) ((volatile struct gpio_cmsdk_ahb *)DT_CMSDK_AHB_GPIO0)
#define CMSDK_AHB_GPIO1_DEV \ #define CMSDK_AHB_GPIO1_DEV \
((volatile struct gpio_cmsdk_ahb *)CMSDK_AHB_GPIO1) ((volatile struct gpio_cmsdk_ahb *)DT_CMSDK_AHB_GPIO1)
/* /*
* This is the mapping from the ARM V2M Beetle Board pins to GPIO * This is the mapping from the ARM V2M Beetle Board pins to GPIO

20
boards/arm/warp7_m4/dts_fixup.h
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@ -1,11 +1,11 @@
#define CONFIG_FXOS8700_NAME DT_FSL_IMX7D_I2C_30A50000_NXP_FXOS8700_1E_LABEL #define DT_FXOS8700_NAME DT_FSL_IMX7D_I2C_30A50000_NXP_FXOS8700_1E_LABEL
#define CONFIG_FXOS8700_I2C_NAME DT_FSL_IMX7D_I2C_30A50000_NXP_FXOS8700_1E_BUS_NAME #define DT_FXOS8700_I2C_NAME DT_FSL_IMX7D_I2C_30A50000_NXP_FXOS8700_1E_BUS_NAME
#define CONFIG_FXOS8700_I2C_ADDRESS DT_FSL_IMX7D_I2C_30A50000_NXP_FXOS8700_1E_BASE_ADDRESS #define DT_FXOS8700_I2C_ADDRESS DT_FSL_IMX7D_I2C_30A50000_NXP_FXOS8700_1E_BASE_ADDRESS
#define CONFIG_FXOS8700_GPIO_NAME DT_FSL_IMX7D_I2C_30A50000_NXP_FXOS8700_1E_INT1_GPIOS_CONTROLLER #define DT_FXOS8700_GPIO_NAME DT_FSL_IMX7D_I2C_30A50000_NXP_FXOS8700_1E_INT1_GPIOS_CONTROLLER
#define CONFIG_FXOS8700_GPIO_PIN DT_FSL_IMX7D_I2C_30A50000_NXP_FXOS8700_1E_INT1_GPIOS_PIN #define DT_FXOS8700_GPIO_PIN DT_FSL_IMX7D_I2C_30A50000_NXP_FXOS8700_1E_INT1_GPIOS_PIN
#define CONFIG_FXAS21002_NAME DT_FSL_IMX7D_I2C_30A50000_NXP_FXAS21002_20_LABEL #define DT_FXAS21002_NAME DT_FSL_IMX7D_I2C_30A50000_NXP_FXAS21002_20_LABEL
#define CONFIG_FXAS21002_I2C_NAME DT_FSL_IMX7D_I2C_30A50000_NXP_FXAS21002_20_BUS_NAME #define DT_FXAS21002_I2C_NAME DT_FSL_IMX7D_I2C_30A50000_NXP_FXAS21002_20_BUS_NAME
#define CONFIG_FXAS21002_I2C_ADDRESS DT_FSL_IMX7D_I2C_30A50000_NXP_FXAS21002_20_BASE_ADDRESS #define DT_FXAS21002_I2C_ADDRESS DT_FSL_IMX7D_I2C_30A50000_NXP_FXAS21002_20_BASE_ADDRESS
#define CONFIG_FXAS21002_GPIO_NAME DT_FSL_IMX7D_I2C_30A50000_NXP_FXAS21002_20_INT1_GPIOS_CONTROLLER #define DT_FXAS21002_GPIO_NAME DT_FSL_IMX7D_I2C_30A50000_NXP_FXAS21002_20_INT1_GPIOS_CONTROLLER
#define CONFIG_FXAS21002_GPIO_PIN DT_FSL_IMX7D_I2C_30A50000_NXP_FXAS21002_20_INT1_GPIOS_PIN #define DT_FXAS21002_GPIO_PIN DT_FSL_IMX7D_I2C_30A50000_NXP_FXAS21002_20_INT1_GPIOS_PIN

22
boards/shields/x_nucleo_iks01a1/dts_fixup.h
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@ -5,17 +5,17 @@
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
#define CONFIG_HTS221_NAME ARDUINO_I2C_ST_HTS221_5F_LABEL #define DT_HTS221_NAME ARDUINO_I2C_ST_HTS221_5F_LABEL
#define CONFIG_HTS221_I2C_MASTER_DEV_NAME ARDUINO_I2C_ST_HTS221_5F_BUS_NAME #define DT_HTS221_I2C_MASTER_DEV_NAME ARDUINO_I2C_ST_HTS221_5F_BUS_NAME
#define CONFIG_LIS3MDL_NAME ARDUINO_I2C_ST_LIS3MDL_MAGN_1E_LABEL #define DT_LIS3MDL_NAME ARDUINO_I2C_ST_LIS3MDL_MAGN_1E_LABEL
#define CONFIG_LIS3MDL_I2C_ADDR ARDUINO_I2C_ST_LIS3MDL_MAGN_1E_BASE_ADDRESS #define DT_LIS3MDL_I2C_ADDR ARDUINO_I2C_ST_LIS3MDL_MAGN_1E_BASE_ADDRESS
#define CONFIG_LIS3MDL_I2C_MASTER_DEV_NAME ARDUINO_I2C_ST_LIS3MDL_MAGN_1E_BUS_NAME #define DT_LIS3MDL_I2C_MASTER_DEV_NAME ARDUINO_I2C_ST_LIS3MDL_MAGN_1E_BUS_NAME
#define CONFIG_LPS25HB_DEV_NAME ARDUINO_I2C_ST_LPS25HB_PRESS_5D_LABEL #define DT_LPS25HB_DEV_NAME ARDUINO_I2C_ST_LPS25HB_PRESS_5D_LABEL
#define CONFIG_LPS25HB_I2C_ADDR ARDUINO_I2C_ST_LPS25HB_PRESS_5D_BASE_ADDRESS #define DT_LPS25HB_I2C_ADDR ARDUINO_I2C_ST_LPS25HB_PRESS_5D_BASE_ADDRESS
#define CONFIG_LPS25HB_I2C_MASTER_DEV_NAME ARDUINO_I2C_ST_LPS25HB_PRESS_5D_BUS_NAME #define DT_LPS25HB_I2C_MASTER_DEV_NAME ARDUINO_I2C_ST_LPS25HB_PRESS_5D_BUS_NAME
#define CONFIG_LSM6DS0_DEV_NAME ARDUINO_I2C_ST_LSM6DS0_6B_LABEL #define DT_LSM6DS0_DEV_NAME ARDUINO_I2C_ST_LSM6DS0_6B_LABEL
#define CONFIG_LSM6DS0_I2C_ADDR ARDUINO_I2C_ST_LSM6DS0_6B_BASE_ADDRESS #define DT_LSM6DS0_I2C_ADDR ARDUINO_I2C_ST_LSM6DS0_6B_BASE_ADDRESS
#define CONFIG_LSM6DS0_I2C_MASTER_DEV_NAME ARDUINO_I2C_ST_LSM6DS0_6B_BUS_NAME #define DT_LSM6DS0_I2C_MASTER_DEV_NAME ARDUINO_I2C_ST_LSM6DS0_6B_BUS_NAME

16
boards/shields/x_nucleo_iks01a2/dts_fixup.h
View file

@ -5,13 +5,13 @@
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
#define CONFIG_HTS221_NAME ARDUINO_I2C_ST_HTS221_5F_LABEL #define DT_HTS221_NAME ARDUINO_I2C_ST_HTS221_5F_LABEL
#define CONFIG_HTS221_I2C_MASTER_DEV_NAME ARDUINO_I2C_ST_HTS221_5F_BUS_NAME #define DT_HTS221_I2C_MASTER_DEV_NAME ARDUINO_I2C_ST_HTS221_5F_BUS_NAME
#define CONFIG_LPS22HB_DEV_NAME ARDUINO_I2C_ST_LPS22HB_PRESS_5D_LABEL #define DT_LPS22HB_DEV_NAME ARDUINO_I2C_ST_LPS22HB_PRESS_5D_LABEL
#define CONFIG_LPS22HB_I2C_ADDR ARDUINO_I2C_ST_LPS22HB_PRESS_5D_BASE_ADDRESS #define DT_LPS22HB_I2C_ADDR ARDUINO_I2C_ST_LPS22HB_PRESS_5D_BASE_ADDRESS
#define CONFIG_LPS22HB_I2C_MASTER_DEV_NAME ARDUINO_I2C_ST_LPS22HB_PRESS_5D_BUS_NAME #define DT_LPS22HB_I2C_MASTER_DEV_NAME ARDUINO_I2C_ST_LPS22HB_PRESS_5D_BUS_NAME
#define CONFIG_LSM6DSL_DEV_NAME ARDUINO_I2C_ST_LSM6DSL_6B_LABEL #define DT_LSM6DSL_DEV_NAME ARDUINO_I2C_ST_LSM6DSL_6B_LABEL
#define CONFIG_LSM6DSL_I2C_ADDR ARDUINO_I2C_ST_LSM6DSL_6B_BASE_ADDRESS #define DT_LSM6DSL_I2C_ADDR ARDUINO_I2C_ST_LSM6DSL_6B_BASE_ADDRESS
#define CONFIG_LSM6DSL_I2C_MASTER_DEV_NAME ARDUINO_I2C_ST_LSM6DSL_6B_BUS_NAME #define DT_LSM6DSL_I2C_MASTER_DEV_NAME ARDUINO_I2C_ST_LSM6DSL_6B_BUS_NAME

8
boards/x86/qemu_x86/dts_fixup.h
View file

@ -1,8 +1,8 @@
/* Board level DTS fixup file */ /* Board level DTS fixup file */
#define CONFIG_ETH_E1000_BASE_ADDRESS DT_INTEL_E1000_FEBC0000_BASE_ADDRESS #define DT_ETH_E1000_BASE_ADDRESS DT_INTEL_E1000_FEBC0000_BASE_ADDRESS
#define CONFIG_ETH_E1000_IRQ DT_INTEL_E1000_FEBC0000_IRQ_0 #define DT_ETH_E1000_IRQ DT_INTEL_E1000_FEBC0000_IRQ_0
#define CONFIG_ETH_E1000_IRQ_PRIORITY DT_INTEL_E1000_FEBC0000_IRQ_0_PRIORITY #define DT_ETH_E1000_IRQ_PRIORITY DT_INTEL_E1000_FEBC0000_IRQ_0_PRIORITY
#define CONFIG_ETH_E1000_IRQ_FLAGS DT_INTEL_E1000_FEBC0000_IRQ_0_SENSE #define DT_ETH_E1000_IRQ_FLAGS DT_INTEL_E1000_FEBC0000_IRQ_0_SENSE
/* End of Board Level DTS fixup file */ /* End of Board Level DTS fixup file */

80
boards/x86/up_squared/dts_fixup.h
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@ -6,76 +6,76 @@
/* Board level DTS fixup file */ /* Board level DTS fixup file */
#define CONFIG_UART_NS16550_PORT_0_BASE_ADDR DT_NS16550_91524000_BASE_ADDRESS #define DT_UART_NS16550_PORT_0_BASE_ADDR DT_NS16550_91524000_BASE_ADDRESS
#define CONFIG_UART_NS16550_PORT_0_BAUD_RATE DT_NS16550_91524000_CURRENT_SPEED #define CONFIG_UART_NS16550_PORT_0_BAUD_RATE DT_NS16550_91524000_CURRENT_SPEED
#define CONFIG_UART_NS16550_PORT_0_NAME DT_NS16550_91524000_LABEL #define CONFIG_UART_NS16550_PORT_0_NAME DT_NS16550_91524000_LABEL
#define CONFIG_UART_NS16550_PORT_0_IRQ DT_NS16550_91524000_IRQ_0 #define DT_UART_NS16550_PORT_0_IRQ DT_NS16550_91524000_IRQ_0
#define CONFIG_UART_NS16550_PORT_0_IRQ_PRI DT_NS16550_91524000_IRQ_0_PRIORITY #define CONFIG_UART_NS16550_PORT_0_IRQ_PRI DT_NS16550_91524000_IRQ_0_PRIORITY
#define CONFIG_UART_NS16550_PORT_0_IRQ_FLAGS DT_NS16550_91524000_IRQ_0_SENSE #define DT_UART_NS16550_PORT_0_IRQ_FLAGS DT_NS16550_91524000_IRQ_0_SENSE
#define CONFIG_UART_NS16550_PORT_0_CLK_FREQ DT_NS16550_91524000_CLOCK_FREQUENCY #define DT_UART_NS16550_PORT_0_CLK_FREQ DT_NS16550_91524000_CLOCK_FREQUENCY
#define CONFIG_UART_NS16550_PORT_1_BASE_ADDR DT_NS16550_91522000_BASE_ADDRESS #define DT_UART_NS16550_PORT_1_BASE_ADDR DT_NS16550_91522000_BASE_ADDRESS
#define CONFIG_UART_NS16550_PORT_1_BAUD_RATE DT_NS16550_91522000_CURRENT_SPEED #define CONFIG_UART_NS16550_PORT_1_BAUD_RATE DT_NS16550_91522000_CURRENT_SPEED
#define CONFIG_UART_NS16550_PORT_1_NAME DT_NS16550_91522000_LABEL #define CONFIG_UART_NS16550_PORT_1_NAME DT_NS16550_91522000_LABEL
#define CONFIG_UART_NS16550_PORT_1_IRQ DT_NS16550_91522000_IRQ_0 #define DT_UART_NS16550_PORT_1_IRQ DT_NS16550_91522000_IRQ_0
#define CONFIG_UART_NS16550_PORT_1_IRQ_PRI DT_NS16550_91522000_IRQ_0_PRIORITY #define CONFIG_UART_NS16550_PORT_1_IRQ_PRI DT_NS16550_91522000_IRQ_0_PRIORITY
#define CONFIG_UART_NS16550_PORT_1_IRQ_FLAGS DT_NS16550_91522000_IRQ_0_SENSE #define DT_UART_NS16550_PORT_1_IRQ_FLAGS DT_NS16550_91522000_IRQ_0_SENSE
#define CONFIG_UART_NS16550_PORT_1_CLK_FREQ DT_NS16550_91522000_CLOCK_FREQUENCY #define DT_UART_NS16550_PORT_1_CLK_FREQ DT_NS16550_91522000_CLOCK_FREQUENCY
#define CONFIG_I2C_0_NAME DT_SNPS_DESIGNWARE_I2C_91534000_LABEL #define CONFIG_I2C_0_NAME DT_SNPS_DESIGNWARE_I2C_91534000_LABEL
#define CONFIG_I2C_0_BASE_ADDR DT_SNPS_DESIGNWARE_I2C_91534000_BASE_ADDRESS #define DT_I2C_0_BASE_ADDR DT_SNPS_DESIGNWARE_I2C_91534000_BASE_ADDRESS
#define CONFIG_I2C_0_IRQ DT_SNPS_DESIGNWARE_I2C_91534000_IRQ_0 #define DT_I2C_0_IRQ DT_SNPS_DESIGNWARE_I2C_91534000_IRQ_0
#define CONFIG_I2C_0_IRQ_PRI DT_SNPS_DESIGNWARE_I2C_91534000_IRQ_0_PRIORITY #define CONFIG_I2C_0_IRQ_PRI DT_SNPS_DESIGNWARE_I2C_91534000_IRQ_0_PRIORITY
#define CONFIG_I2C_0_IRQ_FLAGS DT_SNPS_DESIGNWARE_I2C_91534000_IRQ_0_SENSE #define DT_I2C_0_IRQ_FLAGS DT_SNPS_DESIGNWARE_I2C_91534000_IRQ_0_SENSE
#define CONFIG_I2C_0_BITRATE DT_SNPS_DESIGNWARE_I2C_91534000_CLOCK_FREQUENCY #define DT_I2C_0_BITRATE DT_SNPS_DESIGNWARE_I2C_91534000_CLOCK_FREQUENCY
#define CONFIG_I2C_1_NAME DT_SNPS_DESIGNWARE_I2C_91532000_LABEL #define CONFIG_I2C_1_NAME DT_SNPS_DESIGNWARE_I2C_91532000_LABEL
#define CONFIG_I2C_1_BASE_ADDR DT_SNPS_DESIGNWARE_I2C_91532000_BASE_ADDRESS #define DT_I2C_1_BASE_ADDR DT_SNPS_DESIGNWARE_I2C_91532000_BASE_ADDRESS
#define CONFIG_I2C_1_IRQ DT_SNPS_DESIGNWARE_I2C_91532000_IRQ_0 #define DT_I2C_1_IRQ DT_SNPS_DESIGNWARE_I2C_91532000_IRQ_0
#define CONFIG_I2C_1_IRQ_PRI DT_SNPS_DESIGNWARE_I2C_91532000_IRQ_0_PRIORITY #define CONFIG_I2C_1_IRQ_PRI DT_SNPS_DESIGNWARE_I2C_91532000_IRQ_0_PRIORITY
#define CONFIG_I2C_1_IRQ_FLAGS DT_SNPS_DESIGNWARE_I2C_91532000_IRQ_0_SENSE #define DT_I2C_1_IRQ_FLAGS DT_SNPS_DESIGNWARE_I2C_91532000_IRQ_0_SENSE
#define CONFIG_I2C_1_BITRATE DT_SNPS_DESIGNWARE_I2C_91532000_CLOCK_FREQUENCY #define DT_I2C_1_BITRATE DT_SNPS_DESIGNWARE_I2C_91532000_CLOCK_FREQUENCY
#define CONFIG_I2C_2_NAME DT_SNPS_DESIGNWARE_I2C_91530000_LABEL #define CONFIG_I2C_2_NAME DT_SNPS_DESIGNWARE_I2C_91530000_LABEL
#define CONFIG_I2C_2_BASE_ADDR DT_SNPS_DESIGNWARE_I2C_91530000_BASE_ADDRESS #define DT_I2C_2_BASE_ADDR DT_SNPS_DESIGNWARE_I2C_91530000_BASE_ADDRESS
#define CONFIG_I2C_2_IRQ DT_SNPS_DESIGNWARE_I2C_91530000_IRQ_0 #define DT_I2C_2_IRQ DT_SNPS_DESIGNWARE_I2C_91530000_IRQ_0
#define CONFIG_I2C_2_IRQ_PRI DT_SNPS_DESIGNWARE_I2C_91530000_IRQ_0_PRIORITY #define CONFIG_I2C_2_IRQ_PRI DT_SNPS_DESIGNWARE_I2C_91530000_IRQ_0_PRIORITY
#define CONFIG_I2C_2_IRQ_FLAGS DT_SNPS_DESIGNWARE_I2C_91530000_IRQ_0_SENSE #define DT_I2C_2_IRQ_FLAGS DT_SNPS_DESIGNWARE_I2C_91530000_IRQ_0_SENSE
#define CONFIG_I2C_2_BITRATE DT_SNPS_DESIGNWARE_I2C_91530000_CLOCK_FREQUENCY #define DT_I2C_2_BITRATE DT_SNPS_DESIGNWARE_I2C_91530000_CLOCK_FREQUENCY
#define CONFIG_I2C_3_NAME DT_SNPS_DESIGNWARE_I2C_9152E000_LABEL #define CONFIG_I2C_3_NAME DT_SNPS_DESIGNWARE_I2C_9152E000_LABEL
#define CONFIG_I2C_3_BASE_ADDR DT_SNPS_DESIGNWARE_I2C_9152E000_BASE_ADDRESS #define DT_I2C_3_BASE_ADDR DT_SNPS_DESIGNWARE_I2C_9152E000_BASE_ADDRESS
#define CONFIG_I2C_3_IRQ DT_SNPS_DESIGNWARE_I2C_9152E000_IRQ_0 #define DT_I2C_3_IRQ DT_SNPS_DESIGNWARE_I2C_9152E000_IRQ_0
#define CONFIG_I2C_3_IRQ_PRI DT_SNPS_DESIGNWARE_I2C_9152E000_IRQ_0_PRIORITY #define CONFIG_I2C_3_IRQ_PRI DT_SNPS_DESIGNWARE_I2C_9152E000_IRQ_0_PRIORITY
#define CONFIG_I2C_3_IRQ_FLAGS DT_SNPS_DESIGNWARE_I2C_9152E000_IRQ_0_SENSE #define DT_I2C_3_IRQ_FLAGS DT_SNPS_DESIGNWARE_I2C_9152E000_IRQ_0_SENSE
#define CONFIG_I2C_3_BITRATE DT_SNPS_DESIGNWARE_I2C_9152E000_CLOCK_FREQUENCY #define DT_I2C_3_BITRATE DT_SNPS_DESIGNWARE_I2C_9152E000_CLOCK_FREQUENCY
#define CONFIG_I2C_4_NAME DT_SNPS_DESIGNWARE_I2C_9152C000_LABEL #define CONFIG_I2C_4_NAME DT_SNPS_DESIGNWARE_I2C_9152C000_LABEL
#define CONFIG_I2C_4_BASE_ADDR DT_SNPS_DESIGNWARE_I2C_9152C000_BASE_ADDRESS #define DT_I2C_4_BASE_ADDR DT_SNPS_DESIGNWARE_I2C_9152C000_BASE_ADDRESS
#define CONFIG_I2C_4_IRQ DT_SNPS_DESIGNWARE_I2C_9152C000_IRQ_0 #define DT_I2C_4_IRQ DT_SNPS_DESIGNWARE_I2C_9152C000_IRQ_0
#define CONFIG_I2C_4_IRQ_PRI DT_SNPS_DESIGNWARE_I2C_9152C000_IRQ_0_PRIORITY #define CONFIG_I2C_4_IRQ_PRI DT_SNPS_DESIGNWARE_I2C_9152C000_IRQ_0_PRIORITY
#define CONFIG_I2C_4_IRQ_FLAGS DT_SNPS_DESIGNWARE_I2C_9152C000_IRQ_0_SENSE #define DT_I2C_4_IRQ_FLAGS DT_SNPS_DESIGNWARE_I2C_9152C000_IRQ_0_SENSE
#define CONFIG_I2C_4_BITRATE DT_SNPS_DESIGNWARE_I2C_9152C000_CLOCK_FREQUENCY #define DT_I2C_4_BITRATE DT_SNPS_DESIGNWARE_I2C_9152C000_CLOCK_FREQUENCY
#define CONFIG_I2C_5_NAME DT_SNPS_DESIGNWARE_I2C_9152A000_LABEL #define CONFIG_I2C_5_NAME DT_SNPS_DESIGNWARE_I2C_9152A000_LABEL
#define CONFIG_I2C_5_BASE_ADDR DT_SNPS_DESIGNWARE_I2C_9152A000_BASE_ADDRESS #define DT_I2C_5_BASE_ADDR DT_SNPS_DESIGNWARE_I2C_9152A000_BASE_ADDRESS
#define CONFIG_I2C_5_IRQ DT_SNPS_DESIGNWARE_I2C_9152A000_IRQ_0 #define DT_I2C_5_IRQ DT_SNPS_DESIGNWARE_I2C_9152A000_IRQ_0
#define CONFIG_I2C_5_IRQ_PRI DT_SNPS_DESIGNWARE_I2C_9152A000_IRQ_0_PRIORITY #define CONFIG_I2C_5_IRQ_PRI DT_SNPS_DESIGNWARE_I2C_9152A000_IRQ_0_PRIORITY
#define CONFIG_I2C_5_IRQ_FLAGS DT_SNPS_DESIGNWARE_I2C_9152A000_IRQ_0_SENSE #define DT_I2C_5_IRQ_FLAGS DT_SNPS_DESIGNWARE_I2C_9152A000_IRQ_0_SENSE
#define CONFIG_I2C_5_BITRATE DT_SNPS_DESIGNWARE_I2C_9152A000_CLOCK_FREQUENCY #define DT_I2C_5_BITRATE DT_SNPS_DESIGNWARE_I2C_9152A000_CLOCK_FREQUENCY
#define CONFIG_I2C_6_NAME DT_SNPS_DESIGNWARE_I2C_91528000_LABEL #define CONFIG_I2C_6_NAME DT_SNPS_DESIGNWARE_I2C_91528000_LABEL
#define CONFIG_I2C_6_BASE_ADDR DT_SNPS_DESIGNWARE_I2C_91528000_BASE_ADDRESS #define DT_I2C_6_BASE_ADDR DT_SNPS_DESIGNWARE_I2C_91528000_BASE_ADDRESS
#define CONFIG_I2C_6_IRQ DT_SNPS_DESIGNWARE_I2C_91528000_IRQ_0 #define DT_I2C_6_IRQ DT_SNPS_DESIGNWARE_I2C_91528000_IRQ_0
#define CONFIG_I2C_6_IRQ_PRI DT_SNPS_DESIGNWARE_I2C_91528000_IRQ_0_PRIORITY #define CONFIG_I2C_6_IRQ_PRI DT_SNPS_DESIGNWARE_I2C_91528000_IRQ_0_PRIORITY
#define CONFIG_I2C_6_IRQ_FLAGS DT_SNPS_DESIGNWARE_I2C_91528000_IRQ_0_SENSE #define DT_I2C_6_IRQ_FLAGS DT_SNPS_DESIGNWARE_I2C_91528000_IRQ_0_SENSE
#define CONFIG_I2C_6_BITRATE DT_SNPS_DESIGNWARE_I2C_91528000_CLOCK_FREQUENCY #define DT_I2C_6_BITRATE DT_SNPS_DESIGNWARE_I2C_91528000_CLOCK_FREQUENCY
#define CONFIG_I2C_7_NAME DT_SNPS_DESIGNWARE_I2C_91526000_LABEL #define CONFIG_I2C_7_NAME DT_SNPS_DESIGNWARE_I2C_91526000_LABEL
#define CONFIG_I2C_7_BASE_ADDR DT_SNPS_DESIGNWARE_I2C_91526000_BASE_ADDRESS #define DT_I2C_7_BASE_ADDR DT_SNPS_DESIGNWARE_I2C_91526000_BASE_ADDRESS
#define CONFIG_I2C_7_IRQ DT_SNPS_DESIGNWARE_I2C_91526000_IRQ_0 #define DT_I2C_7_IRQ DT_SNPS_DESIGNWARE_I2C_91526000_IRQ_0
#define CONFIG_I2C_7_IRQ_PRI DT_SNPS_DESIGNWARE_I2C_91526000_IRQ_0_PRIORITY #define CONFIG_I2C_7_IRQ_PRI DT_SNPS_DESIGNWARE_I2C_91526000_IRQ_0_PRIORITY
#define CONFIG_I2C_7_IRQ_FLAGS DT_SNPS_DESIGNWARE_I2C_91526000_IRQ_0_SENSE #define DT_I2C_7_IRQ_FLAGS DT_SNPS_DESIGNWARE_I2C_91526000_IRQ_0_SENSE
#define CONFIG_I2C_7_BITRATE DT_SNPS_DESIGNWARE_I2C_91526000_CLOCK_FREQUENCY #define DT_I2C_7_BITRATE DT_SNPS_DESIGNWARE_I2C_91526000_CLOCK_FREQUENCY
/* End of Board Level DTS fixup file */ /* End of Board Level DTS fixup file */

6
boards/xtensa/intel_s1000_crb/dts_fixup.h
View file

@ -6,13 +6,13 @@
/* Board level DTS fixup file */ /* Board level DTS fixup file */
#define CONFIG_CODEC_I2C_BUS_NAME \ #define DT_CODEC_I2C_BUS_NAME \
SNPS_DESIGNWARE_I2C_80400_TI_TLV320DAC_18_BUS_NAME SNPS_DESIGNWARE_I2C_80400_TI_TLV320DAC_18_BUS_NAME
#define CONFIG_CODEC_I2C_BUS_ADDR \ #define DT_CODEC_I2C_BUS_ADDR \
SNPS_DESIGNWARE_I2C_80400_TI_TLV320DAC_18_BASE_ADDRESS SNPS_DESIGNWARE_I2C_80400_TI_TLV320DAC_18_BASE_ADDRESS
#define CONFIG_CODEC_NAME \ #define DT_CODEC_NAME \
SNPS_DESIGNWARE_I2C_80400_TI_TLV320DAC_18_LABEL SNPS_DESIGNWARE_I2C_80400_TI_TLV320DAC_18_LABEL
/* End of Board Level DTS fixup file */ /* End of Board Level DTS fixup file */

10
drivers/adc/adc_dw.c
View file

@ -480,7 +480,7 @@ static const struct adc_driver_api api_funcs = {
}; };
const static struct adc_config adc_config_dev = { const static struct adc_config adc_config_dev = {
.reg_base = CONFIG_ADC_0_BASE_ADDRESS, .reg_base = DT_ADC_0_BASE_ADDRESS,
.reg_irq_mask = SCSS_REGISTER_BASE + INT_SS_ADC_IRQ_MASK, .reg_irq_mask = SCSS_REGISTER_BASE + INT_SS_ADC_IRQ_MASK,
.reg_err_mask = SCSS_REGISTER_BASE + INT_SS_ADC_ERR_MASK, .reg_err_mask = SCSS_REGISTER_BASE + INT_SS_ADC_ERR_MASK,
#ifdef CONFIG_ADC_DW_SERIAL #ifdef CONFIG_ADC_DW_SERIAL
@ -507,11 +507,11 @@ DEVICE_AND_API_INIT(adc_dw, CONFIG_ADC_0_NAME, &adc_dw_init,
static void adc_config_irq(void) static void adc_config_irq(void)
{ {
IRQ_CONNECT(CONFIG_ADC_0_IRQ, CONFIG_ADC_0_IRQ_PRI, adc_dw_rx_isr, IRQ_CONNECT(DT_ADC_0_IRQ, CONFIG_ADC_0_IRQ_PRI, adc_dw_rx_isr,
DEVICE_GET(adc_dw), 0); DEVICE_GET(adc_dw), 0);
irq_enable(CONFIG_ADC_0_IRQ); irq_enable(DT_ADC_0_IRQ);
IRQ_CONNECT(CONFIG_ADC_IRQ_ERR, CONFIG_ADC_0_IRQ_PRI, IRQ_CONNECT(DT_ADC_IRQ_ERR, CONFIG_ADC_0_IRQ_PRI,
adc_dw_err_isr, DEVICE_GET(adc_dw), 0); adc_dw_err_isr, DEVICE_GET(adc_dw), 0);
irq_enable(CONFIG_ADC_IRQ_ERR); irq_enable(DT_ADC_IRQ_ERR);
} }

8
drivers/adc/adc_intel_quark_d2000.c
View file

@ -481,7 +481,7 @@ static const struct adc_driver_api adc_quark_d2000_driver_api = {
static void adc_quark_d2000_config_func_0(struct device *dev); static void adc_quark_d2000_config_func_0(struct device *dev);
static const struct adc_quark_d2000_config adc_quark_d2000_config_0 = { static const struct adc_quark_d2000_config adc_quark_d2000_config_0 = {
.reg_base = (adc_reg_t *)CONFIG_ADC_0_BASE_ADDRESS, .reg_base = (adc_reg_t *)DT_ADC_0_BASE_ADDRESS,
.config_func = adc_quark_d2000_config_func_0, .config_func = adc_quark_d2000_config_func_0,
}; };
@ -493,11 +493,11 @@ DEVICE_AND_API_INIT(adc_quark_d2000_0, CONFIG_ADC_0_NAME,
static void adc_quark_d2000_config_func_0(struct device *dev) static void adc_quark_d2000_config_func_0(struct device *dev)
{ {
IRQ_CONNECT(CONFIG_ADC_0_IRQ, CONFIG_ADC_0_IRQ_PRI, IRQ_CONNECT(DT_ADC_0_IRQ, CONFIG_ADC_0_IRQ_PRI,
adc_quark_d2000_isr, adc_quark_d2000_isr,
DEVICE_GET(adc_quark_d2000_0), DEVICE_GET(adc_quark_d2000_0),
CONFIG_ADC_0_IRQ_FLAGS); DT_ADC_0_IRQ_FLAGS);
irq_enable(CONFIG_ADC_0_IRQ); irq_enable(DT_ADC_0_IRQ);
} }
#endif /* CONFIG_ADC_0 */ #endif /* CONFIG_ADC_0 */

12
drivers/adc/adc_mcux_adc16.c
View file

@ -223,7 +223,7 @@ static const struct adc_driver_api mcux_adc16_driver_api = {
static void mcux_adc16_config_func_0(struct device *dev); static void mcux_adc16_config_func_0(struct device *dev);
static const struct mcux_adc16_config mcux_adc16_config_0 = { static const struct mcux_adc16_config mcux_adc16_config_0 = {
.base = (ADC_Type *)CONFIG_ADC_0_BASE_ADDRESS, .base = (ADC_Type *)DT_ADC_0_BASE_ADDRESS,
.irq_config_func = mcux_adc16_config_func_0, .irq_config_func = mcux_adc16_config_func_0,
}; };
@ -240,10 +240,10 @@ DEVICE_AND_API_INIT(mcux_adc16_0, CONFIG_ADC_0_NAME, &mcux_adc16_init,
static void mcux_adc16_config_func_0(struct device *dev) static void mcux_adc16_config_func_0(struct device *dev)
{ {
IRQ_CONNECT(CONFIG_ADC_0_IRQ, CONFIG_ADC_0_IRQ_PRI, IRQ_CONNECT(DT_ADC_0_IRQ, CONFIG_ADC_0_IRQ_PRI,
mcux_adc16_isr, DEVICE_GET(mcux_adc16_0), 0); mcux_adc16_isr, DEVICE_GET(mcux_adc16_0), 0);
irq_enable(CONFIG_ADC_0_IRQ); irq_enable(DT_ADC_0_IRQ);
} }
#endif /* CONFIG_ADC_0 */ #endif /* CONFIG_ADC_0 */
@ -251,7 +251,7 @@ static void mcux_adc16_config_func_0(struct device *dev)
static void mcux_adc16_config_func_1(struct device *dev); static void mcux_adc16_config_func_1(struct device *dev);
static const struct mcux_adc16_config mcux_adc16_config_1 = { static const struct mcux_adc16_config mcux_adc16_config_1 = {
.base = (ADC_Type *)CONFIG_ADC_1_BASE_ADDRESS, .base = (ADC_Type *)DT_ADC_1_BASE_ADDRESS,
.irq_config_func = mcux_adc16_config_func_1, .irq_config_func = mcux_adc16_config_func_1,
}; };
@ -268,9 +268,9 @@ DEVICE_AND_API_INIT(mcux_adc16_1, CONFIG_ADC_1_NAME, &mcux_adc16_init,
static void mcux_adc16_config_func_1(struct device *dev) static void mcux_adc16_config_func_1(struct device *dev)
{ {
IRQ_CONNECT(CONFIG_ADC_1_IRQ, CONFIG_ADC_1_IRQ_PRI, IRQ_CONNECT(DT_ADC_1_IRQ, CONFIG_ADC_1_IRQ_PRI,
mcux_adc16_isr, DEVICE_GET(mcux_adc16_1), 0); mcux_adc16_isr, DEVICE_GET(mcux_adc16_1), 0);
irq_enable(CONFIG_ADC_1_IRQ); irq_enable(DT_ADC_1_IRQ);
} }
#endif /* CONFIG_ADC_1 */ #endif /* CONFIG_ADC_1 */

2
drivers/adc/adc_nrfx_adc.c
View file

@ -253,7 +253,7 @@ static int init_adc(struct device *dev)
return -EBUSY; return -EBUSY;
} }
IRQ_CONNECT(CONFIG_ADC_0_IRQ, CONFIG_ADC_0_IRQ_PRI, IRQ_CONNECT(DT_ADC_0_IRQ, CONFIG_ADC_0_IRQ_PRI,
nrfx_isr, nrfx_adc_irq_handler, 0); nrfx_isr, nrfx_adc_irq_handler, 0);
adc_context_unlock_unconditionally(&m_data.ctx); adc_context_unlock_unconditionally(&m_data.ctx);

4
drivers/adc/adc_nrfx_saadc.c
View file

@ -366,9 +366,9 @@ static int init_saadc(struct device *dev)
{ {
nrf_saadc_event_clear(NRF_SAADC_EVENT_END); nrf_saadc_event_clear(NRF_SAADC_EVENT_END);
nrf_saadc_int_enable(NRF_SAADC_INT_END); nrf_saadc_int_enable(NRF_SAADC_INT_END);
NRFX_IRQ_ENABLE(CONFIG_ADC_0_IRQ); NRFX_IRQ_ENABLE(DT_ADC_0_IRQ);
IRQ_CONNECT(CONFIG_ADC_0_IRQ, CONFIG_ADC_0_IRQ_PRI, IRQ_CONNECT(DT_ADC_0_IRQ, CONFIG_ADC_0_IRQ_PRI,
saadc_irq_handler, DEVICE_GET(adc_0), 0); saadc_irq_handler, DEVICE_GET(adc_0), 0);
adc_context_unlock_unconditionally(&m_data.ctx); adc_context_unlock_unconditionally(&m_data.ctx);

16
drivers/adc/adc_sam_afec.c
View file

@ -345,9 +345,9 @@ static void adc_sam_isr(void *arg)
static void adc0_sam_cfg_func(struct device *dev); static void adc0_sam_cfg_func(struct device *dev);
static const struct adc_sam_cfg adc0_sam_cfg = { static const struct adc_sam_cfg adc0_sam_cfg = {
.regs = (Afec *)CONFIG_ADC_0_BASE_ADDRESS, .regs = (Afec *)DT_ADC_0_BASE_ADDRESS,
.cfg_func = adc0_sam_cfg_func, .cfg_func = adc0_sam_cfg_func,
.periph_id = CONFIG_ADC_0_PERIPHERAL_ID, .periph_id = DT_ADC_0_PERIPHERAL_ID,
.afec_trg_pin = PIN_AFE0_ADTRG, .afec_trg_pin = PIN_AFE0_ADTRG,
}; };
@ -363,9 +363,9 @@ DEVICE_AND_API_INIT(adc0_sam, CONFIG_ADC_0_NAME, adc_sam_init,
static void adc0_sam_cfg_func(struct device *dev) static void adc0_sam_cfg_func(struct device *dev)
{ {
IRQ_CONNECT(CONFIG_ADC_0_IRQ, CONFIG_ADC_0_IRQ_PRI, adc_sam_isr, IRQ_CONNECT(DT_ADC_0_IRQ, CONFIG_ADC_0_IRQ_PRI, adc_sam_isr,
DEVICE_GET(adc0_sam), 0); DEVICE_GET(adc0_sam), 0);
irq_enable(CONFIG_ADC_0_IRQ); irq_enable(DT_ADC_0_IRQ);
} }
#endif /* CONFIG_ADC_0 */ #endif /* CONFIG_ADC_0 */
@ -374,9 +374,9 @@ static void adc0_sam_cfg_func(struct device *dev)
static void adc1_sam_cfg_func(struct device *dev); static void adc1_sam_cfg_func(struct device *dev);
static const struct adc_sam_cfg adc1_sam_cfg = { static const struct adc_sam_cfg adc1_sam_cfg = {
.regs = (Afec *)CONFIG_ADC_1_BASE_ADDRESS, .regs = (Afec *)DT_ADC_1_BASE_ADDRESS,
.cfg_func = adc1_sam_cfg_func, .cfg_func = adc1_sam_cfg_func,
.periph_id = CONFIG_ADC_1_PERIPHERAL_ID, .periph_id = DT_ADC_1_PERIPHERAL_ID,
.afec_trg_pin = PIN_AFE1_ADTRG, .afec_trg_pin = PIN_AFE1_ADTRG,
}; };
@ -392,9 +392,9 @@ DEVICE_AND_API_INIT(adc1_sam, CONFIG_ADC_1_NAME, adc_sam_init,
static void adc1_sam_cfg_func(struct device *dev) static void adc1_sam_cfg_func(struct device *dev)
{ {
IRQ_CONNECT(CONFIG_ADC_1_IRQ, CONFIG_ADC_1_IRQ_PRI, adc_sam_isr, IRQ_CONNECT(DT_ADC_1_IRQ, CONFIG_ADC_1_IRQ_PRI, adc_sam_isr,
DEVICE_GET(adc1_sam), 0); DEVICE_GET(adc1_sam), 0);
irq_enable(CONFIG_ADC_1_IRQ); irq_enable(DT_ADC_1_IRQ);
} }
#endif /* CONFIG_ADC_1 */ #endif /* CONFIG_ADC_1 */

6
drivers/audio/tlv320dac310x.c
View file

@ -33,8 +33,8 @@ struct codec_driver_data {
static struct codec_driver_config codec_device_config = { static struct codec_driver_config codec_device_config = {
.i2c_device = NULL, .i2c_device = NULL,
.i2c_dev_name = CONFIG_CODEC_I2C_BUS_NAME, .i2c_dev_name = DT_CODEC_I2C_BUS_NAME,
.i2c_address = CONFIG_CODEC_I2C_BUS_ADDR, .i2c_address = DT_CODEC_I2C_BUS_ADDR,
}; };
static struct codec_driver_data codec_device_data; static struct codec_driver_data codec_device_data;
@ -509,6 +509,6 @@ static const struct audio_codec_api codec_driver_api = {
.apply_properties = codec_apply_properties, .apply_properties = codec_apply_properties,
}; };
DEVICE_AND_API_INIT(tlv320dac310x, CONFIG_CODEC_NAME, codec_initialize, DEVICE_AND_API_INIT(tlv320dac310x, DT_CODEC_NAME, codec_initialize,
&codec_device_data, &codec_device_config, POST_KERNEL, &codec_device_data, &codec_device_config, POST_KERNEL,
CONFIG_AUDIO_CODEC_INIT_PRIORITY, &codec_driver_api); CONFIG_AUDIO_CODEC_INIT_PRIORITY, &codec_driver_api);

32
drivers/can/stm32_can.c
View file

@ -846,21 +846,21 @@ static const struct can_driver_api can_api_funcs = {
static void config_can_1_irq(CAN_TypeDef *can); static void config_can_1_irq(CAN_TypeDef *can);
static const struct can_stm32_config can_stm32_cfg_1 = { static const struct can_stm32_config can_stm32_cfg_1 = {
.can = (CAN_TypeDef *)CONFIG_CAN_1_BASE_ADDRESS, .can = (CAN_TypeDef *)DT_CAN_1_BASE_ADDRESS,
.bus_speed = CONFIG_CAN_1_BUS_SPEED, .bus_speed = DT_CAN_1_BUS_SPEED,
.swj = CONFIG_CAN_1_SJW, .swj = DT_CAN_1_SJW,
.prop_bs1 = CONFIG_CAN_1_PROP_SEG_PHASE_SEG1, .prop_bs1 = DT_CAN_1_PROP_SEG_PHASE_SEG1,
.bs2 = CONFIG_CAN_1_PHASE_SEG2, .bs2 = DT_CAN_1_PHASE_SEG2,
.pclken = { .pclken = {
.enr = CONFIG_CAN_1_CLOCK_BITS, .enr = DT_CAN_1_CLOCK_BITS,
.bus = CONFIG_CAN_1_CLOCK_BUS, .bus = DT_CAN_1_CLOCK_BUS,
}, },
.config_irq = config_can_1_irq .config_irq = config_can_1_irq
}; };
static struct can_stm32_data can_stm32_dev_data_1; static struct can_stm32_data can_stm32_dev_data_1;
DEVICE_AND_API_INIT(can_stm32_1, CONFIG_CAN_1_NAME, &can_stm32_init, DEVICE_AND_API_INIT(can_stm32_1, DT_CAN_1_NAME, &can_stm32_init,
&can_stm32_dev_data_1, &can_stm32_cfg_1, &can_stm32_dev_data_1, &can_stm32_cfg_1,
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
&can_api_funcs); &can_api_funcs);
@ -869,21 +869,21 @@ static void config_can_1_irq(CAN_TypeDef *can)
{ {
LOG_DBG("Enable CAN1 IRQ"); LOG_DBG("Enable CAN1 IRQ");
#ifdef CONFIG_SOC_SERIES_STM32F0X #ifdef CONFIG_SOC_SERIES_STM32F0X
IRQ_CONNECT(CONFIG_CAN_1_IRQ, CONFIG_CAN_1_IRQ_PRIORITY, can_stm32_isr, IRQ_CONNECT(DT_CAN_1_IRQ, DT_CAN_1_IRQ_PRIORITY, can_stm32_isr,
DEVICE_GET(can_stm32_1), 0); DEVICE_GET(can_stm32_1), 0);
irq_enable(CONFIG_CAN_1_IRQ); irq_enable(DT_CAN_1_IRQ);
#else #else
IRQ_CONNECT(CONFIG_CAN_1_IRQ_RX0, CONFIG_CAN_1_IRQ_PRIORITY, IRQ_CONNECT(DT_CAN_1_IRQ_RX0, DT_CAN_1_IRQ_PRIORITY,
can_stm32_rx_isr, DEVICE_GET(can_stm32_1), 0); can_stm32_rx_isr, DEVICE_GET(can_stm32_1), 0);
irq_enable(CONFIG_CAN_1_IRQ_RX0); irq_enable(DT_CAN_1_IRQ_RX0);
IRQ_CONNECT(CONFIG_CAN_1_IRQ_TX, CONFIG_CAN_1_IRQ_PRIORITY, IRQ_CONNECT(DT_CAN_1_IRQ_TX, DT_CAN_1_IRQ_PRIORITY,
can_stm32_tx_isr, DEVICE_GET(can_stm32_1), 0); can_stm32_tx_isr, DEVICE_GET(can_stm32_1), 0);
irq_enable(CONFIG_CAN_1_IRQ_TX); irq_enable(DT_CAN_1_IRQ_TX);
IRQ_CONNECT(CONFIG_CAN_1_IRQ_SCE, CONFIG_CAN_1_IRQ_PRIORITY, IRQ_CONNECT(DT_CAN_1_IRQ_SCE, DT_CAN_1_IRQ_PRIORITY,
can_stm32_tx_isr, DEVICE_GET(can_stm32_1), 0); can_stm32_tx_isr, DEVICE_GET(can_stm32_1), 0);
irq_enable(CONFIG_CAN_1_IRQ_SCE); irq_enable(DT_CAN_1_IRQ_SCE);
#endif #endif
can->IER |= CAN_IT_TME | CAN_IT_ERR | CAN_IT_FMP0 | CAN_IT_FMP1; can->IER |= CAN_IT_TME | CAN_IT_ERR | CAN_IT_FMP0 | CAN_IT_FMP1;
} }

2
drivers/clock_control/clock_control_mcux_ccm.c
View file

@ -75,7 +75,7 @@ static const struct clock_control_driver_api mcux_ccm_driver_api = {
.get_rate = mcux_ccm_get_subsys_rate, .get_rate = mcux_ccm_get_subsys_rate,
}; };
DEVICE_AND_API_INIT(mcux_ccm, CONFIG_MCUX_CCM_NAME, DEVICE_AND_API_INIT(mcux_ccm, DT_MCUX_CCM_NAME,
&mcux_ccm_init, &mcux_ccm_init,
NULL, NULL, NULL, NULL,
PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,

2
drivers/clock_control/clock_control_mcux_sim.c
View file

@ -54,7 +54,7 @@ static const struct clock_control_driver_api mcux_sim_driver_api = {
.get_rate = mcux_sim_get_subsys_rate, .get_rate = mcux_sim_get_subsys_rate,
}; };
DEVICE_AND_API_INIT(mcux_sim, CONFIG_SIM_NAME, DEVICE_AND_API_INIT(mcux_sim, DT_SIM_NAME,
&mcux_sim_init, &mcux_sim_init,
NULL, NULL, NULL, NULL,
PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,

8
drivers/counter/counter_dtmr_cmsdk_apb.c
View file

@ -102,13 +102,13 @@ static int counter_dtmr_cmsdk_apb_init(struct device *dev)
/* COUNTER 0 */ /* COUNTER 0 */
#ifdef CONFIG_COUNTER_DTMR_CMSDK_APB_0 #ifdef CONFIG_COUNTER_DTMR_CMSDK_APB_0
static const struct counter_dtmr_cmsdk_apb_cfg counter_dtmr_cmsdk_apb_cfg_0 = { static const struct counter_dtmr_cmsdk_apb_cfg counter_dtmr_cmsdk_apb_cfg_0 = {
.dtimer = ((volatile struct dualtimer_cmsdk_apb *)CMSDK_APB_DTIMER), .dtimer = ((volatile struct dualtimer_cmsdk_apb *)DT_CMSDK_APB_DTIMER),
.dtimer_cc_as = {.bus = CMSDK_APB, .state = SOC_ACTIVE, .dtimer_cc_as = {.bus = CMSDK_APB, .state = SOC_ACTIVE,
.device = CMSDK_APB_DTIMER,}, .device = DT_CMSDK_APB_DTIMER,},
.dtimer_cc_ss = {.bus = CMSDK_APB, .state = SOC_SLEEP, .dtimer_cc_ss = {.bus = CMSDK_APB, .state = SOC_SLEEP,
.device = CMSDK_APB_DTIMER,}, .device = DT_CMSDK_APB_DTIMER,},
.dtimer_cc_dss = {.bus = CMSDK_APB, .state = SOC_DEEPSLEEP, .dtimer_cc_dss = {.bus = CMSDK_APB, .state = SOC_DEEPSLEEP,
.device = CMSDK_APB_DTIMER,}, .device = DT_CMSDK_APB_DTIMER,},
}; };
DEVICE_AND_API_INIT(counter_dtmr_cmsdk_apb_0, DEVICE_AND_API_INIT(counter_dtmr_cmsdk_apb_0,

16
drivers/counter/counter_tmr_cmsdk_apb.c
View file

@ -102,13 +102,13 @@ static int counter_tmr_cmsdk_apb_init(struct device *dev)
/* COUNTER 0 */ /* COUNTER 0 */
#ifdef CONFIG_COUNTER_TMR_CMSDK_APB_0 #ifdef CONFIG_COUNTER_TMR_CMSDK_APB_0
static const struct counter_tmr_cmsdk_apb_cfg counter_tmr_cmsdk_apb_cfg_0 = { static const struct counter_tmr_cmsdk_apb_cfg counter_tmr_cmsdk_apb_cfg_0 = {
.timer = ((volatile struct timer_cmsdk_apb *)CMSDK_APB_TIMER0), .timer = ((volatile struct timer_cmsdk_apb *)DT_CMSDK_APB_TIMER0),
.timer_cc_as = {.bus = CMSDK_APB, .state = SOC_ACTIVE, .timer_cc_as = {.bus = CMSDK_APB, .state = SOC_ACTIVE,
.device = CMSDK_APB_TIMER0,}, .device = DT_CMSDK_APB_TIMER0,},
.timer_cc_ss = {.bus = CMSDK_APB, .state = SOC_SLEEP, .timer_cc_ss = {.bus = CMSDK_APB, .state = SOC_SLEEP,
.device = CMSDK_APB_TIMER0,}, .device = DT_CMSDK_APB_TIMER0,},
.timer_cc_dss = {.bus = CMSDK_APB, .state = SOC_DEEPSLEEP, .timer_cc_dss = {.bus = CMSDK_APB, .state = SOC_DEEPSLEEP,
.device = CMSDK_APB_TIMER0,}, .device = DT_CMSDK_APB_TIMER0,},
}; };
DEVICE_AND_API_INIT(counter_tmr_cmsdk_apb_0, DEVICE_AND_API_INIT(counter_tmr_cmsdk_apb_0,
@ -122,13 +122,13 @@ DEVICE_AND_API_INIT(counter_tmr_cmsdk_apb_0,
/* COUNTER 1 */ /* COUNTER 1 */
#ifdef CONFIG_COUNTER_TMR_CMSDK_APB_1 #ifdef CONFIG_COUNTER_TMR_CMSDK_APB_1
static const struct counter_tmr_cmsdk_apb_cfg counter_tmr_cmsdk_apb_cfg_1 = { static const struct counter_tmr_cmsdk_apb_cfg counter_tmr_cmsdk_apb_cfg_1 = {
.timer = ((volatile struct timer_cmsdk_apb *)CMSDK_APB_TIMER1), .timer = ((volatile struct timer_cmsdk_apb *)DT_CMSDK_APB_TIMER1),
.timer_cc_as = {.bus = CMSDK_APB, .state = SOC_ACTIVE, .timer_cc_as = {.bus = CMSDK_APB, .state = SOC_ACTIVE,
.device = CMSDK_APB_TIMER1,}, .device = DT_CMSDK_APB_TIMER1,},
.timer_cc_ss = {.bus = CMSDK_APB, .state = SOC_SLEEP, .timer_cc_ss = {.bus = CMSDK_APB, .state = SOC_SLEEP,
.device = CMSDK_APB_TIMER1,}, .device = DT_CMSDK_APB_TIMER1,},
.timer_cc_dss = {.bus = CMSDK_APB, .state = SOC_DEEPSLEEP, .timer_cc_dss = {.bus = CMSDK_APB, .state = SOC_DEEPSLEEP,
.device = CMSDK_APB_TIMER1,}, .device = DT_CMSDK_APB_TIMER1,},
}; };
DEVICE_AND_API_INIT(counter_tmr_cmsdk_apb_1, DEVICE_AND_API_INIT(counter_tmr_cmsdk_apb_1,

12
drivers/counter/timer_dtmr_cmsdk_apb.c
View file

@ -172,14 +172,14 @@ static int timer_dtmr_cmsdk_apb_init(struct device *dev)
static void dtimer_cmsdk_apb_config_0(struct device *dev); static void dtimer_cmsdk_apb_config_0(struct device *dev);
static const struct timer_dtmr_cmsdk_apb_cfg timer_dtmr_cmsdk_apb_cfg_0 = { static const struct timer_dtmr_cmsdk_apb_cfg timer_dtmr_cmsdk_apb_cfg_0 = {
.dtimer = ((volatile struct dualtimer_cmsdk_apb *)CMSDK_APB_DTIMER), .dtimer = ((volatile struct dualtimer_cmsdk_apb *)DT_CMSDK_APB_DTIMER),
.dtimer_config_func = dtimer_cmsdk_apb_config_0, .dtimer_config_func = dtimer_cmsdk_apb_config_0,
.dtimer_cc_as = {.bus = CMSDK_APB, .state = SOC_ACTIVE, .dtimer_cc_as = {.bus = CMSDK_APB, .state = SOC_ACTIVE,
.device = CMSDK_APB_DTIMER,}, .device = DT_CMSDK_APB_DTIMER,},
.dtimer_cc_ss = {.bus = CMSDK_APB, .state = SOC_SLEEP, .dtimer_cc_ss = {.bus = CMSDK_APB, .state = SOC_SLEEP,
.device = CMSDK_APB_DTIMER,}, .device = DT_CMSDK_APB_DTIMER,},
.dtimer_cc_dss = {.bus = CMSDK_APB, .state = SOC_DEEPSLEEP, .dtimer_cc_dss = {.bus = CMSDK_APB, .state = SOC_DEEPSLEEP,
.device = CMSDK_APB_DTIMER,}, .device = DT_CMSDK_APB_DTIMER,},
}; };
static struct timer_dtmr_cmsdk_apb_dev_data timer_dtmr_cmsdk_apb_dev_data_0 = { static struct timer_dtmr_cmsdk_apb_dev_data timer_dtmr_cmsdk_apb_dev_data_0 = {
@ -197,10 +197,10 @@ DEVICE_AND_API_INIT(timer_dtmr_cmsdk_apb_0,
static void dtimer_cmsdk_apb_config_0(struct device *dev) static void dtimer_cmsdk_apb_config_0(struct device *dev)
{ {
IRQ_CONNECT(CMSDK_APB_DUALTIMER_IRQ, IRQ_CONNECT(DT_CMSDK_APB_DUALTIMER_IRQ,
CONFIG_TIMER_DTMR_CMSDK_APB_0_IRQ_PRI, CONFIG_TIMER_DTMR_CMSDK_APB_0_IRQ_PRI,
timer_dtmr_cmsdk_apb_isr, timer_dtmr_cmsdk_apb_isr,
DEVICE_GET(timer_dtmr_cmsdk_apb_0), 0); DEVICE_GET(timer_dtmr_cmsdk_apb_0), 0);
irq_enable(CMSDK_APB_DUALTIMER_IRQ); irq_enable(DT_CMSDK_APB_DUALTIMER_IRQ);
} }
#endif /* CONFIG_TIMER_DTMR_CMSDK_APB_0 */ #endif /* CONFIG_TIMER_DTMR_CMSDK_APB_0 */

24
drivers/counter/timer_tmr_cmsdk_apb.c
View file

@ -173,14 +173,14 @@ static int timer_tmr_cmsdk_apb_init(struct device *dev)
static void timer_cmsdk_apb_config_0(struct device *dev); static void timer_cmsdk_apb_config_0(struct device *dev);
static const struct timer_tmr_cmsdk_apb_cfg timer_tmr_cmsdk_apb_cfg_0 = { static const struct timer_tmr_cmsdk_apb_cfg timer_tmr_cmsdk_apb_cfg_0 = {
.timer = ((volatile struct timer_cmsdk_apb *)CMSDK_APB_TIMER0), .timer = ((volatile struct timer_cmsdk_apb *)DT_CMSDK_APB_TIMER0),
.timer_config_func = timer_cmsdk_apb_config_0, .timer_config_func = timer_cmsdk_apb_config_0,
.timer_cc_as = {.bus = CMSDK_APB, .state = SOC_ACTIVE, .timer_cc_as = {.bus = CMSDK_APB, .state = SOC_ACTIVE,
.device = CMSDK_APB_TIMER0,}, .device = DT_CMSDK_APB_TIMER0,},
.timer_cc_ss = {.bus = CMSDK_APB, .state = SOC_SLEEP, .timer_cc_ss = {.bus = CMSDK_APB, .state = SOC_SLEEP,
.device = CMSDK_APB_TIMER0,}, .device = DT_CMSDK_APB_TIMER0,},
.timer_cc_dss = {.bus = CMSDK_APB, .state = SOC_DEEPSLEEP, .timer_cc_dss = {.bus = CMSDK_APB, .state = SOC_DEEPSLEEP,
.device = CMSDK_APB_TIMER0,}, .device = DT_CMSDK_APB_TIMER0,},
}; };
static struct timer_tmr_cmsdk_apb_dev_data timer_tmr_cmsdk_apb_dev_data_0 = { static struct timer_tmr_cmsdk_apb_dev_data timer_tmr_cmsdk_apb_dev_data_0 = {
@ -197,10 +197,10 @@ DEVICE_AND_API_INIT(timer_tmr_cmsdk_apb_0,
static void timer_cmsdk_apb_config_0(struct device *dev) static void timer_cmsdk_apb_config_0(struct device *dev)
{ {
IRQ_CONNECT(CMSDK_APB_TIMER_0_IRQ, CONFIG_TIMER_TMR_CMSDK_APB_0_IRQ_PRI, IRQ_CONNECT(DT_CMSDK_APB_TIMER_0_IRQ, CONFIG_TIMER_TMR_CMSDK_APB_0_IRQ_PRI,
timer_tmr_cmsdk_apb_isr, timer_tmr_cmsdk_apb_isr,
DEVICE_GET(timer_tmr_cmsdk_apb_0), 0); DEVICE_GET(timer_tmr_cmsdk_apb_0), 0);
irq_enable(CMSDK_APB_TIMER_0_IRQ); irq_enable(DT_CMSDK_APB_TIMER_0_IRQ);
} }
#endif /* CONFIG_TIMER_TMR_CMSDK_APB_0 */ #endif /* CONFIG_TIMER_TMR_CMSDK_APB_0 */
@ -209,14 +209,14 @@ static void timer_cmsdk_apb_config_0(struct device *dev)
static void timer_cmsdk_apb_config_1(struct device *dev); static void timer_cmsdk_apb_config_1(struct device *dev);
static const struct timer_tmr_cmsdk_apb_cfg timer_tmr_cmsdk_apb_cfg_1 = { static const struct timer_tmr_cmsdk_apb_cfg timer_tmr_cmsdk_apb_cfg_1 = {
.timer = ((volatile struct timer_cmsdk_apb *)CMSDK_APB_TIMER1), .timer = ((volatile struct timer_cmsdk_apb *)DT_CMSDK_APB_TIMER1),
.timer_config_func = timer_cmsdk_apb_config_1, .timer_config_func = timer_cmsdk_apb_config_1,
.timer_cc_as = {.bus = CMSDK_APB, .state = SOC_ACTIVE, .timer_cc_as = {.bus = CMSDK_APB, .state = SOC_ACTIVE,
.device = CMSDK_APB_TIMER1,}, .device = DT_CMSDK_APB_TIMER1,},
.timer_cc_ss = {.bus = CMSDK_APB, .state = SOC_SLEEP, .timer_cc_ss = {.bus = CMSDK_APB, .state = SOC_SLEEP,
.device = CMSDK_APB_TIMER1,}, .device = DT_CMSDK_APB_TIMER1,},
.timer_cc_dss = {.bus = CMSDK_APB, .state = SOC_DEEPSLEEP, .timer_cc_dss = {.bus = CMSDK_APB, .state = SOC_DEEPSLEEP,
.device = CMSDK_APB_TIMER1,}, .device = DT_CMSDK_APB_TIMER1,},
}; };
static struct timer_tmr_cmsdk_apb_dev_data timer_tmr_cmsdk_apb_dev_data_1 = { static struct timer_tmr_cmsdk_apb_dev_data timer_tmr_cmsdk_apb_dev_data_1 = {
@ -233,9 +233,9 @@ DEVICE_AND_API_INIT(timer_tmr_cmsdk_apb_1,
static void timer_cmsdk_apb_config_1(struct device *dev) static void timer_cmsdk_apb_config_1(struct device *dev)
{ {
IRQ_CONNECT(CMSDK_APB_TIMER_1_IRQ, CONFIG_TIMER_TMR_CMSDK_APB_1_IRQ_PRI, IRQ_CONNECT(DT_CMSDK_APB_TIMER_1_IRQ, CONFIG_TIMER_TMR_CMSDK_APB_1_IRQ_PRI,
timer_tmr_cmsdk_apb_isr, timer_tmr_cmsdk_apb_isr,
DEVICE_GET(timer_tmr_cmsdk_apb_0), 0); DEVICE_GET(timer_tmr_cmsdk_apb_0), 0);
irq_enable(CMSDK_APB_TIMER_1_IRQ); irq_enable(DT_CMSDK_APB_TIMER_1_IRQ);
} }
#endif /* CONFIG_TIMER_TMR_CMSDK_APB_1 */ #endif /* CONFIG_TIMER_TMR_CMSDK_APB_1 */

26
drivers/display/display_ili9340.c
View file

@ -41,15 +41,15 @@ static int ili9340_init(struct device *dev)
LOG_DBG("Initializing display driver"); LOG_DBG("Initializing display driver");
data->spi_dev = device_get_binding(CONFIG_ILI9340_SPI_DEV_NAME); data->spi_dev = device_get_binding(DT_ILI9340_SPI_DEV_NAME);
if (data->spi_dev == NULL) { if (data->spi_dev == NULL) {
LOG_ERR("Could not get SPI device for ILI9340"); LOG_ERR("Could not get SPI device for ILI9340");
return -EPERM; return -EPERM;
} }
data->spi_config.frequency = CONFIG_ILI9340_SPI_FREQ; data->spi_config.frequency = DT_ILI9340_SPI_FREQ;
data->spi_config.operation = SPI_OP_MODE_MASTER | SPI_WORD_SET(8); data->spi_config.operation = SPI_OP_MODE_MASTER | SPI_WORD_SET(8);
data->spi_config.slave = CONFIG_ILI9340_SPI_SLAVE_NUMBER; data->spi_config.slave = DT_ILI9340_SPI_SLAVE_NUMBER;
#ifdef CONFIG_ILI9340_GPIO_CS #ifdef CONFIG_ILI9340_GPIO_CS
data->cs_ctrl.gpio_dev = data->cs_ctrl.gpio_dev =
@ -62,31 +62,31 @@ static int ili9340_init(struct device *dev)
#endif #endif
data->reset_gpio = data->reset_gpio =
device_get_binding(CONFIG_ILI9340_RESET_GPIO_PORT_NAME); device_get_binding(DT_ILI9340_RESET_GPIO_PORT_NAME);
if (data->reset_gpio == NULL) { if (data->reset_gpio == NULL) {
LOG_ERR("Could not get GPIO port for ILI9340 reset"); LOG_ERR("Could not get GPIO port for ILI9340 reset");
return -EPERM; return -EPERM;
} }
gpio_pin_configure(data->reset_gpio, CONFIG_ILI9340_RESET_PIN, gpio_pin_configure(data->reset_gpio, DT_ILI9340_RESET_PIN,
GPIO_DIR_OUT); GPIO_DIR_OUT);
data->command_data_gpio = data->command_data_gpio =
device_get_binding(CONFIG_ILI9340_CMD_DATA_GPIO_PORT_NAME); device_get_binding(DT_ILI9340_CMD_DATA_GPIO_PORT_NAME);
if (data->command_data_gpio == NULL) { if (data->command_data_gpio == NULL) {
LOG_ERR("Could not get GPIO port for ILI9340 command/data"); LOG_ERR("Could not get GPIO port for ILI9340 command/data");
return -EPERM; return -EPERM;
} }
gpio_pin_configure(data->command_data_gpio, CONFIG_ILI9340_CMD_DATA_PIN, gpio_pin_configure(data->command_data_gpio, DT_ILI9340_CMD_DATA_PIN,
GPIO_DIR_OUT); GPIO_DIR_OUT);
LOG_DBG("Resetting display driver"); LOG_DBG("Resetting display driver");
gpio_pin_write(data->reset_gpio, CONFIG_ILI9340_RESET_PIN, 1); gpio_pin_write(data->reset_gpio, DT_ILI9340_RESET_PIN, 1);
k_sleep(1); k_sleep(1);
gpio_pin_write(data->reset_gpio, CONFIG_ILI9340_RESET_PIN, 0); gpio_pin_write(data->reset_gpio, DT_ILI9340_RESET_PIN, 0);
k_sleep(1); k_sleep(1);
gpio_pin_write(data->reset_gpio, CONFIG_ILI9340_RESET_PIN, 1); gpio_pin_write(data->reset_gpio, DT_ILI9340_RESET_PIN, 1);
k_sleep(5); k_sleep(5);
LOG_DBG("Initializing LCD"); LOG_DBG("Initializing LCD");
@ -242,7 +242,7 @@ void ili9340_transmit(struct ili9340_data *data, u8_t cmd, void *tx_data,
struct spi_buf tx_buf = { .buf = &cmd, .len = 1 }; struct spi_buf tx_buf = { .buf = &cmd, .len = 1 };
struct spi_buf_set tx_bufs = { .buffers = &tx_buf, .count = 1 }; struct spi_buf_set tx_bufs = { .buffers = &tx_buf, .count = 1 };
gpio_pin_write(data->command_data_gpio, CONFIG_ILI9340_CMD_DATA_PIN, gpio_pin_write(data->command_data_gpio, DT_ILI9340_CMD_DATA_PIN,
ILI9340_CMD_DATA_PIN_COMMAND); ILI9340_CMD_DATA_PIN_COMMAND);
spi_write(data->spi_dev, &data->spi_config, &tx_bufs); spi_write(data->spi_dev, &data->spi_config, &tx_bufs);
@ -250,7 +250,7 @@ void ili9340_transmit(struct ili9340_data *data, u8_t cmd, void *tx_data,
tx_buf.buf = tx_data; tx_buf.buf = tx_data;
tx_buf.len = tx_len; tx_buf.len = tx_len;
gpio_pin_write(data->command_data_gpio, gpio_pin_write(data->command_data_gpio,
CONFIG_ILI9340_CMD_DATA_PIN, DT_ILI9340_CMD_DATA_PIN,
ILI9340_CMD_DATA_PIN_DATA); ILI9340_CMD_DATA_PIN_DATA);
spi_write(data->spi_dev, &data->spi_config, &tx_bufs); spi_write(data->spi_dev, &data->spi_config, &tx_bufs);
} }
@ -271,6 +271,6 @@ static const struct display_driver_api ili9340_api = {
static struct ili9340_data ili9340_data; static struct ili9340_data ili9340_data;
DEVICE_AND_API_INIT(ili9340, CONFIG_ILI9340_DEV_NAME, &ili9340_init, DEVICE_AND_API_INIT(ili9340, DT_ILI9340_DEV_NAME, &ili9340_init,
&ili9340_data, NULL, APPLICATION, &ili9340_data, NULL, APPLICATION,
CONFIG_APPLICATION_INIT_PRIORITY, &ili9340_api); CONFIG_APPLICATION_INIT_PRIORITY, &ili9340_api);

26
drivers/display/mb_display.c
View file

@ -26,51 +26,51 @@
/* Onboard LED Row 1 */ /* Onboard LED Row 1 */
#define LED_ROW1_GPIO_PIN 13 #define LED_ROW1_GPIO_PIN 13
#define LED_ROW1_GPIO_PORT CONFIG_GPIO_P0_DEV_NAME #define LED_ROW1_GPIO_PORT DT_GPIO_P0_DEV_NAME
/* Onboard LED Row 2 */ /* Onboard LED Row 2 */
#define LED_ROW2_GPIO_PIN 14 #define LED_ROW2_GPIO_PIN 14
#define LED_ROW2_GPIO_PORT CONFIG_GPIO_P0_DEV_NAME #define LED_ROW2_GPIO_PORT DT_GPIO_P0_DEV_NAME
/* Onboard LED Row 3 */ /* Onboard LED Row 3 */
#define LED_ROW3_GPIO_PIN 15 #define LED_ROW3_GPIO_PIN 15
#define LED_ROW3_GPIO_PORT CONFIG_GPIO_P0_DEV_NAME #define LED_ROW3_GPIO_PORT DT_GPIO_P0_DEV_NAME
/* Onboard LED Column 1 */ /* Onboard LED Column 1 */
#define LED_COL1_GPIO_PIN 4 #define LED_COL1_GPIO_PIN 4
#define LED_COL1_GPIO_PORT CONFIG_GPIO_P0_DEV_NAME #define LED_COL1_GPIO_PORT DT_GPIO_P0_DEV_NAME
/* Onboard LED Column 2 */ /* Onboard LED Column 2 */
#define LED_COL2_GPIO_PIN 5 #define LED_COL2_GPIO_PIN 5
#define LED_COL2_GPIO_PORT CONFIG_GPIO_P0_DEV_NAME #define LED_COL2_GPIO_PORT DT_GPIO_P0_DEV_NAME
/* Onboard LED Column 3 */ /* Onboard LED Column 3 */
#define LED_COL3_GPIO_PIN 6 #define LED_COL3_GPIO_PIN 6
#define LED_COL3_GPIO_PORT CONFIG_GPIO_P0_DEV_NAME #define LED_COL3_GPIO_PORT DT_GPIO_P0_DEV_NAME
/* Onboard LED Column 4 */ /* Onboard LED Column 4 */
#define LED_COL4_GPIO_PIN 7 #define LED_COL4_GPIO_PIN 7
#define LED_COL4_GPIO_PORT CONFIG_GPIO_P0_DEV_NAME #define LED_COL4_GPIO_PORT DT_GPIO_P0_DEV_NAME
/* Onboard LED Column 5 */ /* Onboard LED Column 5 */
#define LED_COL5_GPIO_PIN 8 #define LED_COL5_GPIO_PIN 8
#define LED_COL5_GPIO_PORT CONFIG_GPIO_P0_DEV_NAME #define LED_COL5_GPIO_PORT DT_GPIO_P0_DEV_NAME
/* Onboard LED Column 6 */ /* Onboard LED Column 6 */
#define LED_COL6_GPIO_PIN 9 #define LED_COL6_GPIO_PIN 9
#define LED_COL6_GPIO_PORT CONFIG_GPIO_P0_DEV_NAME #define LED_COL6_GPIO_PORT DT_GPIO_P0_DEV_NAME
/* Onboard LED Column 7 */ /* Onboard LED Column 7 */
#define LED_COL7_GPIO_PIN 10 #define LED_COL7_GPIO_PIN 10
#define LED_COL7_GPIO_PORT CONFIG_GPIO_P0_DEV_NAME #define LED_COL7_GPIO_PORT DT_GPIO_P0_DEV_NAME
/* Onboard LED Column 8 */ /* Onboard LED Column 8 */
#define LED_COL8_GPIO_PIN 11 #define LED_COL8_GPIO_PIN 11
#define LED_COL8_GPIO_PORT CONFIG_GPIO_P0_DEV_NAME #define LED_COL8_GPIO_PORT DT_GPIO_P0_DEV_NAME
/* Onboard LED Column 9 */ /* Onboard LED Column 9 */
#define LED_COL9_GPIO_PIN 12 #define LED_COL9_GPIO_PIN 12
#define LED_COL9_GPIO_PORT CONFIG_GPIO_P0_DEV_NAME #define LED_COL9_GPIO_PORT DT_GPIO_P0_DEV_NAME
#define DISPLAY_ROWS 3 #define DISPLAY_ROWS 3
@ -434,7 +434,7 @@ static int mb_display_init(struct device *dev)
{ {
ARG_UNUSED(dev); ARG_UNUSED(dev);
display.dev = device_get_binding(CONFIG_GPIO_P0_DEV_NAME); display.dev = device_get_binding(DT_GPIO_P0_DEV_NAME);
__ASSERT(dev, "No GPIO device found"); __ASSERT(dev, "No GPIO device found");

56
drivers/display/ssd1306.c
View file

@ -17,19 +17,19 @@ LOG_MODULE_REGISTER(ssd1306);
#include "ssd1306_regs.h" #include "ssd1306_regs.h"
#include <display/cfb.h> #include <display/cfb.h>
#if CONFIG_SSD1306_PANEL_SEGMENT_REMAP == 1 #if DT_SSD1306_PANEL_SEGMENT_REMAP == 1
#define SSD1306_PANEL_SEGMENT_REMAP true #define SSD1306_PANEL_SEGMENT_REMAP true
#else #else
#define SSD1306_PANEL_SEGMENT_REMAP false #define SSD1306_PANEL_SEGMENT_REMAP false
#endif #endif
#if CONFIG_SSD1306_PANEL_COM_INVDIR == 1 #if DT_SSD1306_PANEL_COM_INVDIR == 1
#define SSD1306_PANEL_COM_INVDIR true #define SSD1306_PANEL_COM_INVDIR true
#else #else
#define SSD1306_PANEL_COM_INVDIR false #define SSD1306_PANEL_COM_INVDIR false
#endif #endif
#define SSD1306_PANEL_NUMOF_PAGES (SSD1306_PANEL_HEIGHT / 8) #define SSD1306_PANEL_NUMOF_PAGES (DT_SSD1306_PANEL_HEIGHT / 8)
#define SSD1306_CLOCK_DIV_RATIO 0x0 #define SSD1306_CLOCK_DIV_RATIO 0x0
#define SSD1306_CLOCK_FREQUENCY 0x8 #define SSD1306_CLOCK_FREQUENCY 0x8
#define SSD1306_PANEL_MUX_RATIO 63 #define SSD1306_PANEL_MUX_RATIO 63
@ -55,21 +55,21 @@ struct ssd1306_data {
static inline int ssd1306_reg_read(struct ssd1306_data *driver, static inline int ssd1306_reg_read(struct ssd1306_data *driver,
u8_t reg, u8_t * const val) u8_t reg, u8_t * const val)
{ {
return i2c_reg_read_byte(driver->i2c, CONFIG_SSD1306_I2C_ADDR, return i2c_reg_read_byte(driver->i2c, DT_SSD1306_I2C_ADDR,
reg, val); reg, val);
} }
static inline int ssd1306_reg_write(struct ssd1306_data *driver, static inline int ssd1306_reg_write(struct ssd1306_data *driver,
u8_t reg, u8_t val) u8_t reg, u8_t val)
{ {
return i2c_reg_write_byte(driver->i2c, CONFIG_SSD1306_I2C_ADDR, return i2c_reg_write_byte(driver->i2c, DT_SSD1306_I2C_ADDR,
reg, val); reg, val);
} }
static inline int ssd1306_reg_update(struct ssd1306_data *driver, u8_t reg, static inline int ssd1306_reg_update(struct ssd1306_data *driver, u8_t reg,
u8_t mask, u8_t val) u8_t mask, u8_t val)
{ {
return i2c_reg_update_byte(driver->i2c, CONFIG_SSD1306_I2C_ADDR, return i2c_reg_update_byte(driver->i2c, DT_SSD1306_I2C_ADDR,
reg, mask, val); reg, mask, val);
} }
@ -88,7 +88,7 @@ static inline int ssd1306_set_panel_orientation(struct device *dev)
}; };
return i2c_write(driver->i2c, cmd_buf, sizeof(cmd_buf), return i2c_write(driver->i2c, cmd_buf, sizeof(cmd_buf),
CONFIG_SSD1306_I2C_ADDR); DT_SSD1306_I2C_ADDR);
} }
static inline int ssd1306_set_timing_setting(struct device *dev) static inline int ssd1306_set_timing_setting(struct device *dev)
@ -102,7 +102,7 @@ static inline int ssd1306_set_timing_setting(struct device *dev)
SSD1306_CONTROL_BYTE_CMD, SSD1306_CONTROL_BYTE_CMD,
SSD1306_SET_CHARGE_PERIOD, SSD1306_SET_CHARGE_PERIOD,
SSD1306_CONTROL_BYTE_CMD, SSD1306_CONTROL_BYTE_CMD,
SSD1306_PANEL_PRECHARGE_PERIOD, DT_SSD1306_PANEL_PRECHARGE_PERIOD,
SSD1306_CONTROL_BYTE_CMD, SSD1306_CONTROL_BYTE_CMD,
SSD1306_SET_VCOM_DESELECT_LEVEL, SSD1306_SET_VCOM_DESELECT_LEVEL,
SSD1306_CONTROL_LAST_BYTE_CMD, SSD1306_CONTROL_LAST_BYTE_CMD,
@ -110,7 +110,7 @@ static inline int ssd1306_set_timing_setting(struct device *dev)
}; };
return i2c_write(driver->i2c, cmd_buf, sizeof(cmd_buf), return i2c_write(driver->i2c, cmd_buf, sizeof(cmd_buf),
CONFIG_SSD1306_I2C_ADDR); DT_SSD1306_I2C_ADDR);
} }
static inline int ssd1306_set_hardware_config(struct device *dev) static inline int ssd1306_set_hardware_config(struct device *dev)
@ -122,7 +122,7 @@ static inline int ssd1306_set_hardware_config(struct device *dev)
SSD1306_CONTROL_BYTE_CMD, SSD1306_CONTROL_BYTE_CMD,
SSD1306_SET_DISPLAY_OFFSET, SSD1306_SET_DISPLAY_OFFSET,
SSD1306_CONTROL_BYTE_CMD, SSD1306_CONTROL_BYTE_CMD,
SSD1306_PANEL_DISPLAY_OFFSET, DT_SSD1306_PANEL_DISPLAY_OFFSET,
SSD1306_CONTROL_BYTE_CMD, SSD1306_CONTROL_BYTE_CMD,
SSD1306_SET_PADS_HW_CONFIG, SSD1306_SET_PADS_HW_CONFIG,
SSD1306_CONTROL_BYTE_CMD, SSD1306_CONTROL_BYTE_CMD,
@ -134,7 +134,7 @@ static inline int ssd1306_set_hardware_config(struct device *dev)
}; };
return i2c_write(driver->i2c, cmd_buf, sizeof(cmd_buf), return i2c_write(driver->i2c, cmd_buf, sizeof(cmd_buf),
CONFIG_SSD1306_I2C_ADDR); DT_SSD1306_I2C_ADDR);
} }
static inline int ssd1306_set_charge_pump(const struct device *dev) static inline int ssd1306_set_charge_pump(const struct device *dev)
@ -158,7 +158,7 @@ static inline int ssd1306_set_charge_pump(const struct device *dev)
}; };
return i2c_write(driver->i2c, cmd_buf, sizeof(cmd_buf), return i2c_write(driver->i2c, cmd_buf, sizeof(cmd_buf),
CONFIG_SSD1306_I2C_ADDR); DT_SSD1306_I2C_ADDR);
} }
int ssd1306_resume(const struct device *dev) int ssd1306_resume(const struct device *dev)
@ -190,11 +190,11 @@ int ssd1306_write_page(struct device *dev, u8_t page, void * const data,
#endif #endif
SSD1306_CONTROL_BYTE_CMD, SSD1306_CONTROL_BYTE_CMD,
SSD1306_SET_LOWER_COL_ADDRESS | SSD1306_SET_LOWER_COL_ADDRESS |
(SSD1306_PANEL_FIRST_SEG & (DT_SSD1306_PANEL_FIRST_SEG &
SSD1306_SET_LOWER_COL_ADDRESS_MASK), SSD1306_SET_LOWER_COL_ADDRESS_MASK),
SSD1306_CONTROL_BYTE_CMD, SSD1306_CONTROL_BYTE_CMD,
SSD1306_SET_HIGHER_COL_ADDRESS | SSD1306_SET_HIGHER_COL_ADDRESS |
((SSD1306_PANEL_FIRST_SEG >> 4) & ((DT_SSD1306_PANEL_FIRST_SEG >> 4) &
SSD1306_SET_LOWER_COL_ADDRESS_MASK), SSD1306_SET_LOWER_COL_ADDRESS_MASK),
SSD1306_CONTROL_LAST_BYTE_CMD, SSD1306_CONTROL_LAST_BYTE_CMD,
SSD1306_SET_PAGE_START_ADDRESS | page SSD1306_SET_PAGE_START_ADDRESS | page
@ -209,11 +209,11 @@ int ssd1306_write_page(struct device *dev, u8_t page, void * const data,
} }
if (i2c_write(driver->i2c, cmd_buf, sizeof(cmd_buf), if (i2c_write(driver->i2c, cmd_buf, sizeof(cmd_buf),
CONFIG_SSD1306_I2C_ADDR)) { DT_SSD1306_I2C_ADDR)) {
return -1; return -1;
} }
return i2c_burst_write(driver->i2c, CONFIG_SSD1306_I2C_ADDR, return i2c_burst_write(driver->i2c, DT_SSD1306_I2C_ADDR,
SSD1306_CONTROL_LAST_BYTE_DATA, SSD1306_CONTROL_LAST_BYTE_DATA,
data, length); data, length);
} }
@ -265,25 +265,25 @@ int ssd1306_write(const struct device *dev, const u16_t x, const u16_t y,
}; };
if (i2c_write(driver->i2c, cmd_buf, sizeof(cmd_buf), if (i2c_write(driver->i2c, cmd_buf, sizeof(cmd_buf),
CONFIG_SSD1306_I2C_ADDR)) { DT_SSD1306_I2C_ADDR)) {
LOG_ERR("Failed to write command"); LOG_ERR("Failed to write command");
return -1; return -1;
} }
return i2c_burst_write(driver->i2c, CONFIG_SSD1306_I2C_ADDR, return i2c_burst_write(driver->i2c, DT_SSD1306_I2C_ADDR,
SSD1306_CONTROL_LAST_BYTE_DATA, SSD1306_CONTROL_LAST_BYTE_DATA,
(u8_t *)buf, desc->buf_size); (u8_t *)buf, desc->buf_size);
#elif defined(CONFIG_SSD1306_SH1106_COMPATIBLE) #elif defined(CONFIG_SSD1306_SH1106_COMPATIBLE)
if (len != SSD1306_PANEL_NUMOF_PAGES * SSD1306_PANEL_WIDTH) { if (len != SSD1306_PANEL_NUMOF_PAGES * DT_SSD1306_PANEL_WIDTH) {
return -1; return -1;
} }
for (size_t pidx = 0; pidx < SSD1306_PANEL_NUMOF_PAGES; pidx++) { for (size_t pidx = 0; pidx < SSD1306_PANEL_NUMOF_PAGES; pidx++) {
if (ssd1306_write_page(dev, pidx, buf, SSD1306_PANEL_WIDTH)) { if (ssd1306_write_page(dev, pidx, buf, DT_SSD1306_PANEL_WIDTH)) {
return -1; return -1;
} }
buf = (u8_t *)buf + SSD1306_PANEL_WIDTH; buf = (u8_t *)buf + DT_SSD1306_PANEL_WIDTH;
} }
#endif #endif
@ -323,15 +323,15 @@ int ssd1306_set_contrast(const struct device *dev, const u8_t contrast)
}; };
return i2c_write(driver->i2c, cmd_buf, sizeof(cmd_buf), return i2c_write(driver->i2c, cmd_buf, sizeof(cmd_buf),
CONFIG_SSD1306_I2C_ADDR); DT_SSD1306_I2C_ADDR);
} }
static void ssd1306_get_capabilities(const struct device *dev, static void ssd1306_get_capabilities(const struct device *dev,
struct display_capabilities *caps) struct display_capabilities *caps)
{ {
memset(caps, 0, sizeof(struct display_capabilities)); memset(caps, 0, sizeof(struct display_capabilities));
caps->x_resolution = SSD1306_PANEL_WIDTH; caps->x_resolution = DT_SSD1306_PANEL_WIDTH;
caps->y_resolution = SSD1306_PANEL_HEIGHT; caps->y_resolution = DT_SSD1306_PANEL_HEIGHT;
caps->supported_pixel_formats = PIXEL_FORMAT_MONO10; caps->supported_pixel_formats = PIXEL_FORMAT_MONO10;
caps->current_pixel_format = PIXEL_FORMAT_MONO10; caps->current_pixel_format = PIXEL_FORMAT_MONO10;
caps->screen_info = SCREEN_INFO_MONO_VTILED; caps->screen_info = SCREEN_INFO_MONO_VTILED;
@ -378,7 +378,7 @@ static int ssd1306_init_device(struct device *dev)
} }
if (i2c_write(driver->i2c, cmd_buf, sizeof(cmd_buf), if (i2c_write(driver->i2c, cmd_buf, sizeof(cmd_buf),
CONFIG_SSD1306_I2C_ADDR)) { DT_SSD1306_I2C_ADDR)) {
return -EIO; return -EIO;
} }
@ -397,10 +397,10 @@ static int ssd1306_init(struct device *dev)
LOG_DBG(""); LOG_DBG("");
driver->i2c = device_get_binding(CONFIG_SSD1306_I2C_MASTER_DEV_NAME); driver->i2c = device_get_binding(DT_SSD1306_I2C_MASTER_DEV_NAME);
if (driver->i2c == NULL) { if (driver->i2c == NULL) {
LOG_ERR("Failed to get pointer to %s device!", LOG_ERR("Failed to get pointer to %s device!",
CONFIG_SSD1306_I2C_MASTER_DEV_NAME); DT_SSD1306_I2C_MASTER_DEV_NAME);
return -EINVAL; return -EINVAL;
} }
@ -426,7 +426,7 @@ static struct display_driver_api ssd1306_driver_api = {
.set_pixel_format = ssd1306_set_pixel_format, .set_pixel_format = ssd1306_set_pixel_format,
}; };
DEVICE_AND_API_INIT(ssd1306, CONFIG_SSD1306_DEV_NAME, ssd1306_init, DEVICE_AND_API_INIT(ssd1306, DT_SSD1306_DEV_NAME, ssd1306_init,
&ssd1306_driver, NULL, &ssd1306_driver, NULL,
POST_KERNEL, CONFIG_APPLICATION_INIT_PRIORITY, POST_KERNEL, CONFIG_APPLICATION_INIT_PRIORITY,
&ssd1306_driver_api); &ssd1306_driver_api);

46
drivers/display/ssd1673.c
View file

@ -36,7 +36,7 @@ struct ssd1673_data {
struct device *busy; struct device *busy;
struct device *spi_dev; struct device *spi_dev;
struct spi_config spi_config; struct spi_config spi_config;
#if defined(CONFIG_SSD1673_SPI_GPIO_CS) #if defined(DT_SSD1673_SPI_GPIO_CS)
struct spi_cs_control cs_ctrl; struct spi_cs_control cs_ctrl;
#endif #endif
u8_t contrast; u8_t contrast;
@ -69,7 +69,7 @@ static inline int ssd1673_write_cmd(struct ssd1673_data *driver,
struct spi_buf buf = {.buf = &cmd, .len = sizeof(cmd)}; struct spi_buf buf = {.buf = &cmd, .len = sizeof(cmd)};
struct spi_buf_set buf_set = {.buffers = &buf, .count = 1}; struct spi_buf_set buf_set = {.buffers = &buf, .count = 1};
gpio_pin_write(driver->dc, CONFIG_SSD1673_DC_PIN, 0); gpio_pin_write(driver->dc, DT_SSD1673_DC_PIN, 0);
if (spi_write(driver->spi_dev, &driver->spi_config, &buf_set)) { if (spi_write(driver->spi_dev, &driver->spi_config, &buf_set)) {
return -1; return -1;
} }
@ -77,7 +77,7 @@ static inline int ssd1673_write_cmd(struct ssd1673_data *driver,
if (data != NULL) { if (data != NULL) {
buf.buf = data; buf.buf = data;
buf.len = len; buf.len = len;
gpio_pin_write(driver->dc, CONFIG_SSD1673_DC_PIN, 1); gpio_pin_write(driver->dc, DT_SSD1673_DC_PIN, 1);
if (spi_write(driver->spi_dev, &driver->spi_config, &buf_set)) { if (spi_write(driver->spi_dev, &driver->spi_config, &buf_set)) {
return -1; return -1;
} }
@ -90,10 +90,10 @@ static inline void ssd1673_busy_wait(struct ssd1673_data *driver)
{ {
u32_t val = 0; u32_t val = 0;
gpio_pin_read(driver->busy, CONFIG_SSD1673_BUSY_PIN, &val); gpio_pin_read(driver->busy, DT_SSD1673_BUSY_PIN, &val);
while (val) { while (val) {
k_busy_wait(SSD1673_BUSY_DELAY); k_busy_wait(SSD1673_BUSY_DELAY);
gpio_pin_read(driver->busy, CONFIG_SSD1673_BUSY_PIN, &val); gpio_pin_read(driver->busy, DT_SSD1673_BUSY_PIN, &val);
} }
} }
@ -136,7 +136,7 @@ static inline int ssd1673_set_ram_ptr(struct ssd1673_data *driver,
static inline void ssd1673_set_orientation(struct ssd1673_data *driver) static inline void ssd1673_set_orientation(struct ssd1673_data *driver)
{ {
#if CONFIG_SSD1673_ORIENTATION_FLIPPED == 1 #if DT_SSD1673_ORIENTATION_FLIPPED == 1
driver->scan_mode = SSD1673_DATA_ENTRY_XIYDY; driver->scan_mode = SSD1673_DATA_ENTRY_XIYDY;
#else #else
driver->scan_mode = SSD1673_DATA_ENTRY_XDYIY; driver->scan_mode = SSD1673_DATA_ENTRY_XDYIY;
@ -298,12 +298,12 @@ static int ssd1673_write(const struct device *dev, const u16_t x,
return -1; return -1;
} }
gpio_pin_write(driver->dc, CONFIG_SSD1673_DC_PIN, 0); gpio_pin_write(driver->dc, DT_SSD1673_DC_PIN, 0);
if (spi_write(driver->spi_dev, &driver->spi_config, &buf_set)) { if (spi_write(driver->spi_dev, &driver->spi_config, &buf_set)) {
return -1; return -1;
} }
gpio_pin_write(driver->dc, CONFIG_SSD1673_DC_PIN, 1); gpio_pin_write(driver->dc, DT_SSD1673_DC_PIN, 1);
/* clear unusable page */ /* clear unusable page */
if (driver->scan_mode == SSD1673_DATA_ENTRY_XDYIY) { if (driver->scan_mode == SSD1673_DATA_ENTRY_XDYIY) {
sbuf.buf = dummy_page; sbuf.buf = dummy_page;
@ -397,9 +397,9 @@ static int ssd1673_controller_init(struct device *dev)
LOG_DBG(""); LOG_DBG("");
gpio_pin_write(driver->reset, CONFIG_SSD1673_RESET_PIN, 0); gpio_pin_write(driver->reset, DT_SSD1673_RESET_PIN, 0);
k_sleep(SSD1673_RESET_DELAY); k_sleep(SSD1673_RESET_DELAY);
gpio_pin_write(driver->reset, CONFIG_SSD1673_RESET_PIN, 1); gpio_pin_write(driver->reset, DT_SSD1673_RESET_PIN, 1);
k_sleep(SSD1673_RESET_DELAY); k_sleep(SSD1673_RESET_DELAY);
ssd1673_busy_wait(driver); ssd1673_busy_wait(driver);
@ -454,53 +454,53 @@ static int ssd1673_init(struct device *dev)
LOG_DBG(""); LOG_DBG("");
driver->spi_dev = device_get_binding(CONFIG_SSD1673_SPI_DEV_NAME); driver->spi_dev = device_get_binding(DT_SSD1673_SPI_DEV_NAME);
if (driver->spi_dev == NULL) { if (driver->spi_dev == NULL) {
LOG_ERR("Could not get SPI device for SSD1673"); LOG_ERR("Could not get SPI device for SSD1673");
return -EIO; return -EIO;
} }
driver->spi_config.frequency = CONFIG_SSD1673_SPI_FREQ; driver->spi_config.frequency = DT_SSD1673_SPI_FREQ;
driver->spi_config.operation = SPI_OP_MODE_MASTER | SPI_WORD_SET(8); driver->spi_config.operation = SPI_OP_MODE_MASTER | SPI_WORD_SET(8);
driver->spi_config.slave = CONFIG_SSD1673_SPI_SLAVE_NUMBER; driver->spi_config.slave = DT_SSD1673_SPI_SLAVE_NUMBER;
driver->spi_config.cs = NULL; driver->spi_config.cs = NULL;
driver->reset = device_get_binding(CONFIG_SSD1673_RESET_GPIO_PORT_NAME); driver->reset = device_get_binding(DT_SSD1673_RESET_GPIO_PORT_NAME);
if (driver->reset == NULL) { if (driver->reset == NULL) {
LOG_ERR("Could not get GPIO port for SSD1673 reset"); LOG_ERR("Could not get GPIO port for SSD1673 reset");
return -EIO; return -EIO;
} }
gpio_pin_configure(driver->reset, CONFIG_SSD1673_RESET_PIN, gpio_pin_configure(driver->reset, DT_SSD1673_RESET_PIN,
GPIO_DIR_OUT); GPIO_DIR_OUT);
driver->dc = device_get_binding(CONFIG_SSD1673_DC_GPIO_PORT_NAME); driver->dc = device_get_binding(DT_SSD1673_DC_GPIO_PORT_NAME);
if (driver->dc == NULL) { if (driver->dc == NULL) {
LOG_ERR("Could not get GPIO port for SSD1673 DC signal"); LOG_ERR("Could not get GPIO port for SSD1673 DC signal");
return -EIO; return -EIO;
} }
gpio_pin_configure(driver->dc, CONFIG_SSD1673_DC_PIN, gpio_pin_configure(driver->dc, DT_SSD1673_DC_PIN,
GPIO_DIR_OUT); GPIO_DIR_OUT);
driver->busy = device_get_binding(CONFIG_SSD1673_BUSY_GPIO_PORT_NAME); driver->busy = device_get_binding(DT_SSD1673_BUSY_GPIO_PORT_NAME);
if (driver->busy == NULL) { if (driver->busy == NULL) {
LOG_ERR("Could not get GPIO port for SSD1673 busy signal"); LOG_ERR("Could not get GPIO port for SSD1673 busy signal");
return -EIO; return -EIO;
} }
gpio_pin_configure(driver->busy, CONFIG_SSD1673_BUSY_PIN, gpio_pin_configure(driver->busy, DT_SSD1673_BUSY_PIN,
GPIO_DIR_IN); GPIO_DIR_IN);
#if defined(CONFIG_SSD1673_SPI_GPIO_CS) #if defined(DT_SSD1673_SPI_GPIO_CS)
driver->cs_ctrl.gpio_dev = device_get_binding( driver->cs_ctrl.gpio_dev = device_get_binding(
CONFIG_SSD1673_SPI_GPIO_CS_DRV_NAME); DT_SSD1673_SPI_GPIO_CS_DRV_NAME);
if (!driver->cs_ctrl.gpio_dev) { if (!driver->cs_ctrl.gpio_dev) {
LOG_ERR("Unable to get SPI GPIO CS device"); LOG_ERR("Unable to get SPI GPIO CS device");
return -EIO; return -EIO;
} }
driver->cs_ctrl.gpio_pin = CONFIG_SSD1673_SPI_GPIO_CS_PIN; driver->cs_ctrl.gpio_pin = DT_SSD1673_SPI_GPIO_CS_PIN;
driver->cs_ctrl.delay = 0; driver->cs_ctrl.delay = 0;
driver->spi_config.cs = &driver->cs_ctrl; driver->spi_config.cs = &driver->cs_ctrl;
#endif #endif
@ -526,7 +526,7 @@ static struct display_driver_api ssd1673_driver_api = {
}; };
DEVICE_AND_API_INIT(ssd1673, CONFIG_SSD1673_DEV_NAME, ssd1673_init, DEVICE_AND_API_INIT(ssd1673, DT_SSD1673_DEV_NAME, ssd1673_init,
&ssd1673_driver, NULL, &ssd1673_driver, NULL,
POST_KERNEL, CONFIG_APPLICATION_INIT_PRIORITY, POST_KERNEL, CONFIG_APPLICATION_INIT_PRIORITY,
&ssd1673_driver_api); &ssd1673_driver_api);

6
drivers/ethernet/eth_e1000.c
View file

@ -212,11 +212,11 @@ static void e1000_init(struct net_if *iface)
net_if_set_link_addr(iface, dev->mac, sizeof(dev->mac), net_if_set_link_addr(iface, dev->mac, sizeof(dev->mac),
NET_LINK_ETHERNET); NET_LINK_ETHERNET);
IRQ_CONNECT(CONFIG_ETH_E1000_IRQ, CONFIG_ETH_E1000_IRQ_PRIORITY, IRQ_CONNECT(DT_ETH_E1000_IRQ, DT_ETH_E1000_IRQ_PRIORITY,
e1000_isr, DEVICE_GET(eth_e1000), e1000_isr, DEVICE_GET(eth_e1000),
CONFIG_ETH_E1000_IRQ_FLAGS); DT_ETH_E1000_IRQ_FLAGS);
irq_enable(CONFIG_ETH_E1000_IRQ); irq_enable(DT_ETH_E1000_IRQ);
iow32(dev, CTRL, CTRL_SLU); /* Set link up */ iow32(dev, CTRL, CTRL_SLU); /* Set link up */

24
drivers/ethernet/eth_mcux.c
View file

@ -968,35 +968,35 @@ static struct eth_context eth_0_context = {
0x04, 0x04,
0x9f, 0x9f,
#if defined(CONFIG_ETH_MCUX_0_MANUAL_MAC) #if defined(CONFIG_ETH_MCUX_0_MANUAL_MAC)
CONFIG_ETH_MCUX_0_MAC3, DT_ETH_MCUX_0_MAC3,
CONFIG_ETH_MCUX_0_MAC4, DT_ETH_MCUX_0_MAC4,
CONFIG_ETH_MCUX_0_MAC5 DT_ETH_MCUX_0_MAC5
#endif #endif
} }
}; };
ETH_NET_DEVICE_INIT(eth_mcux_0, CONFIG_ETH_MCUX_0_NAME, eth_0_init, ETH_NET_DEVICE_INIT(eth_mcux_0, DT_ETH_MCUX_0_NAME, eth_0_init,
&eth_0_context, NULL, CONFIG_ETH_INIT_PRIORITY, &eth_0_context, NULL, CONFIG_ETH_INIT_PRIORITY,
&api_funcs, 1500); &api_funcs, 1500);
static void eth_0_config_func(void) static void eth_0_config_func(void)
{ {
IRQ_CONNECT(CONFIG_IRQ_ETH_RX, CONFIG_ETH_MCUX_0_IRQ_PRI, IRQ_CONNECT(DT_IRQ_ETH_RX, DT_ETH_MCUX_0_IRQ_PRI,
eth_mcux_rx_isr, DEVICE_GET(eth_mcux_0), 0); eth_mcux_rx_isr, DEVICE_GET(eth_mcux_0), 0);
irq_enable(CONFIG_IRQ_ETH_RX); irq_enable(DT_IRQ_ETH_RX);
IRQ_CONNECT(CONFIG_IRQ_ETH_TX, CONFIG_ETH_MCUX_0_IRQ_PRI, IRQ_CONNECT(DT_IRQ_ETH_TX, DT_ETH_MCUX_0_IRQ_PRI,
eth_mcux_tx_isr, DEVICE_GET(eth_mcux_0), 0); eth_mcux_tx_isr, DEVICE_GET(eth_mcux_0), 0);
irq_enable(CONFIG_IRQ_ETH_TX); irq_enable(DT_IRQ_ETH_TX);
IRQ_CONNECT(CONFIG_IRQ_ETH_ERR_MISC, CONFIG_ETH_MCUX_0_IRQ_PRI, IRQ_CONNECT(DT_IRQ_ETH_ERR_MISC, DT_ETH_MCUX_0_IRQ_PRI,
eth_mcux_error_isr, DEVICE_GET(eth_mcux_0), 0); eth_mcux_error_isr, DEVICE_GET(eth_mcux_0), 0);
irq_enable(CONFIG_IRQ_ETH_ERR_MISC); irq_enable(DT_IRQ_ETH_ERR_MISC);
#if defined(CONFIG_PTP_CLOCK_MCUX) #if defined(CONFIG_PTP_CLOCK_MCUX)
IRQ_CONNECT(CONFIG_IRQ_ETH_IEEE1588_TMR, CONFIG_ETH_MCUX_0_IRQ_PRI, IRQ_CONNECT(DT_IRQ_ETH_IEEE1588_TMR, DT_ETH_MCUX_0_IRQ_PRI,
eth_mcux_ptp_isr, DEVICE_GET(eth_mcux_0), 0); eth_mcux_ptp_isr, DEVICE_GET(eth_mcux_0), 0);
irq_enable(CONFIG_IRQ_ETH_IEEE1588_TMR); irq_enable(DT_IRQ_ETH_IEEE1588_TMR);
#endif #endif
} }

2
drivers/flash/flash_gecko.c
View file

@ -189,6 +189,6 @@ static const struct flash_driver_api flash_gecko_driver_api = {
static struct flash_gecko_data flash_gecko_0_data; static struct flash_gecko_data flash_gecko_0_data;
DEVICE_AND_API_INIT(flash_gecko_0, FLASH_DEV_NAME, DEVICE_AND_API_INIT(flash_gecko_0, DT_FLASH_DEV_NAME,
flash_gecko_init, &flash_gecko_0_data, NULL, POST_KERNEL, flash_gecko_init, &flash_gecko_0_data, NULL, POST_KERNEL,
CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &flash_gecko_driver_api); CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &flash_gecko_driver_api);

2
drivers/flash/flash_sam0.c
View file

@ -376,6 +376,6 @@ static const struct flash_driver_api flash_sam0_api = {
static struct flash_sam0_data flash_sam0_data_0; static struct flash_sam0_data flash_sam0_data_0;
DEVICE_AND_API_INIT(flash_sam0, FLASH_DEV_NAME, DEVICE_AND_API_INIT(flash_sam0, DT_FLASH_DEV_NAME,
flash_sam0_init, &flash_sam0_data_0, NULL, POST_KERNEL, flash_sam0_init, &flash_sam0_data_0, NULL, POST_KERNEL,
CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &flash_sam0_api); CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &flash_sam0_api);

8
drivers/flash/flash_shell.c
View file

@ -36,7 +36,7 @@ static int cmd_erase(const struct shell *shell, size_t argc, char *argv[])
int result; int result;
u32_t size; u32_t size;
flash_dev = device_get_binding(FLASH_DEV_NAME); flash_dev = device_get_binding(DT_FLASH_DEV_NAME);
if (!flash_dev) { if (!flash_dev) {
error(shell, "Flash driver was not found!"); error(shell, "Flash driver was not found!");
return -ENODEV; return -ENODEV;
@ -76,7 +76,7 @@ static int cmd_write(const struct shell *shell, size_t argc, char *argv[])
u32_t w_addr; u32_t w_addr;
int j = 0; int j = 0;
flash_dev = device_get_binding(FLASH_DEV_NAME); flash_dev = device_get_binding(DT_FLASH_DEV_NAME);
if (!flash_dev) { if (!flash_dev) {
error(shell, "Flash driver was not found!"); error(shell, "Flash driver was not found!");
return -ENODEV; return -ENODEV;
@ -128,7 +128,7 @@ static int cmd_read(const struct shell *shell, size_t argc, char *argv[])
u32_t addr; u32_t addr;
int cnt; int cnt;
flash_dev = device_get_binding(FLASH_DEV_NAME); flash_dev = device_get_binding(DT_FLASH_DEV_NAME);
if (!flash_dev) { if (!flash_dev) {
error(shell, "Flash driver was not found!"); error(shell, "Flash driver was not found!");
return -ENODEV; return -ENODEV;
@ -168,7 +168,7 @@ static int cmd_test(const struct shell *shell, size_t argc, char *argv[])
u32_t addr; u32_t addr;
u32_t size; u32_t size;
flash_dev = device_get_binding(FLASH_DEV_NAME); flash_dev = device_get_binding(DT_FLASH_DEV_NAME);
if (!flash_dev) { if (!flash_dev) {
error(shell, "Flash driver was not found!"); error(shell, "Flash driver was not found!");
return -ENODEV; return -ENODEV;

8
drivers/flash/flash_stm32.c
View file

@ -204,13 +204,13 @@ static int flash_stm32_write_protection(struct device *dev, bool enable)
static struct flash_stm32_priv flash_data = { static struct flash_stm32_priv flash_data = {
#if defined(CONFIG_SOC_SERIES_STM32F0X) #if defined(CONFIG_SOC_SERIES_STM32F0X)
.regs = (struct stm32f0x_flash *) FLASH_DEV_BASE_ADDRESS, .regs = (struct stm32f0x_flash *) DT_FLASH_DEV_BASE_ADDRESS,
.pclken = { .bus = STM32_CLOCK_BUS_AHB1, .pclken = { .bus = STM32_CLOCK_BUS_AHB1,
.enr = LL_AHB1_GRP1_PERIPH_FLASH }, .enr = LL_AHB1_GRP1_PERIPH_FLASH },
#elif defined(CONFIG_SOC_SERIES_STM32F4X) #elif defined(CONFIG_SOC_SERIES_STM32F4X)
.regs = (struct stm32f4x_flash *) FLASH_DEV_BASE_ADDRESS, .regs = (struct stm32f4x_flash *) DT_FLASH_DEV_BASE_ADDRESS,
#elif defined(CONFIG_SOC_SERIES_STM32L4X) #elif defined(CONFIG_SOC_SERIES_STM32L4X)
.regs = (struct stm32l4x_flash *) FLASH_DEV_BASE_ADDRESS, .regs = (struct stm32l4x_flash *) DT_FLASH_DEV_BASE_ADDRESS,
.pclken = { .bus = STM32_CLOCK_BUS_AHB1, .pclken = { .bus = STM32_CLOCK_BUS_AHB1,
.enr = LL_AHB1_GRP1_PERIPH_FLASH }, .enr = LL_AHB1_GRP1_PERIPH_FLASH },
#endif #endif
@ -260,6 +260,6 @@ static int stm32_flash_init(struct device *dev)
return flash_stm32_write_protection(dev, false); return flash_stm32_write_protection(dev, false);
} }
DEVICE_AND_API_INIT(stm32_flash, FLASH_DEV_NAME, DEVICE_AND_API_INIT(stm32_flash, DT_FLASH_DEV_NAME,
stm32_flash_init, &flash_data, NULL, POST_KERNEL, stm32_flash_init, &flash_data, NULL, POST_KERNEL,
CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &flash_stm32_api); CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &flash_stm32_api);

4
drivers/flash/flash_stm32f3x.c
View file

@ -133,7 +133,7 @@ static const struct flash_driver_api flash_stm32_api = {
}; };
static const struct flash_stm32_dev_config flash_device_config = { static const struct flash_stm32_dev_config flash_device_config = {
.base = (u32_t *)FLASH_DEV_BASE_ADDRESS, .base = (u32_t *)DT_FLASH_DEV_BASE_ADDRESS,
.pclken = { .bus = STM32_CLOCK_BUS_APB1, .pclken = { .bus = STM32_CLOCK_BUS_APB1,
.enr = LL_AHB1_GRP1_PERIPH_FLASH}, .enr = LL_AHB1_GRP1_PERIPH_FLASH},
}; };
@ -142,7 +142,7 @@ static struct flash_stm32_dev_data flash_device_data = {
}; };
DEVICE_AND_API_INIT(flash_stm32, FLASH_DEV_NAME, DEVICE_AND_API_INIT(flash_stm32, DT_FLASH_DEV_NAME,
flash_stm32_init, flash_stm32_init,
&flash_device_data, &flash_device_data,
&flash_device_config, &flash_device_config,

2
drivers/flash/soc_flash_mcux.c
View file

@ -151,7 +151,7 @@ static int flash_mcux_init(struct device *dev)
return (rc == kStatus_Success) ? 0 : -EIO; return (rc == kStatus_Success) ? 0 : -EIO;
} }
DEVICE_AND_API_INIT(flash_mcux, FLASH_DEV_NAME, DEVICE_AND_API_INIT(flash_mcux, DT_FLASH_DEV_NAME,
flash_mcux_init, &flash_data, NULL, POST_KERNEL, flash_mcux_init, &flash_data, NULL, POST_KERNEL,
CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &flash_mcux_api); CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &flash_mcux_api);

2
drivers/flash/soc_flash_nrf.c
View file

@ -239,7 +239,7 @@ static int nrf_flash_init(struct device *dev)
return 0; return 0;
} }
DEVICE_INIT(nrf_flash, FLASH_DEV_NAME, nrf_flash_init, DEVICE_INIT(nrf_flash, DT_FLASH_DEV_NAME, nrf_flash_init,
NULL, NULL, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE); NULL, NULL, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE);
#if defined(CONFIG_SOC_FLASH_NRF_RADIO_SYNC) #if defined(CONFIG_SOC_FLASH_NRF_RADIO_SYNC)

48
drivers/gpio/gpio_cc32xx.c
View file

@ -200,8 +200,8 @@ static const struct gpio_driver_api api_funcs = {
#ifdef CONFIG_GPIO_CC32XX_A0 #ifdef CONFIG_GPIO_CC32XX_A0
static const struct gpio_cc32xx_config gpio_cc32xx_a0_config = { static const struct gpio_cc32xx_config gpio_cc32xx_a0_config = {
.port_base = CONFIG_GPIO_CC32XX_A0_BASE_ADDRESS, .port_base = DT_GPIO_CC32XX_A0_BASE_ADDRESS,
.irq_num = CONFIG_GPIO_CC32XX_A0_IRQ+16, .irq_num = DT_GPIO_CC32XX_A0_IRQ+16,
}; };
static struct device DEVICE_NAME_GET(gpio_cc32xx_a0); static struct device DEVICE_NAME_GET(gpio_cc32xx_a0);
@ -211,16 +211,16 @@ static int gpio_cc32xx_a0_init(struct device *dev)
{ {
ARG_UNUSED(dev); ARG_UNUSED(dev);
IRQ_CONNECT(CONFIG_GPIO_CC32XX_A0_IRQ, CONFIG_GPIO_CC32XX_A0_IRQ_PRI, IRQ_CONNECT(DT_GPIO_CC32XX_A0_IRQ, DT_GPIO_CC32XX_A0_IRQ_PRI,
gpio_cc32xx_port_isr, DEVICE_GET(gpio_cc32xx_a0), 0); gpio_cc32xx_port_isr, DEVICE_GET(gpio_cc32xx_a0), 0);
MAP_IntPendClear(CONFIG_GPIO_CC32XX_A0_IRQ+16); MAP_IntPendClear(DT_GPIO_CC32XX_A0_IRQ+16);
irq_enable(CONFIG_GPIO_CC32XX_A0_IRQ); irq_enable(DT_GPIO_CC32XX_A0_IRQ);
return 0; return 0;
} }
DEVICE_AND_API_INIT(gpio_cc32xx_a0, CONFIG_GPIO_CC32XX_A0_NAME, DEVICE_AND_API_INIT(gpio_cc32xx_a0, DT_GPIO_CC32XX_A0_NAME,
&gpio_cc32xx_a0_init, &gpio_cc32xx_a0_data, &gpio_cc32xx_a0_init, &gpio_cc32xx_a0_data,
&gpio_cc32xx_a0_config, &gpio_cc32xx_a0_config,
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
@ -230,8 +230,8 @@ DEVICE_AND_API_INIT(gpio_cc32xx_a0, CONFIG_GPIO_CC32XX_A0_NAME,
#ifdef CONFIG_GPIO_CC32XX_A1 #ifdef CONFIG_GPIO_CC32XX_A1
static const struct gpio_cc32xx_config gpio_cc32xx_a1_config = { static const struct gpio_cc32xx_config gpio_cc32xx_a1_config = {
.port_base = CONFIG_GPIO_CC32XX_A1_BASE_ADDRESS, .port_base = DT_GPIO_CC32XX_A1_BASE_ADDRESS,
.irq_num = CONFIG_GPIO_CC32XX_A1_IRQ+16, .irq_num = DT_GPIO_CC32XX_A1_IRQ+16,
}; };
static struct device DEVICE_NAME_GET(gpio_cc32xx_a1); static struct device DEVICE_NAME_GET(gpio_cc32xx_a1);
@ -241,16 +241,16 @@ static int gpio_cc32xx_a1_init(struct device *dev)
{ {
ARG_UNUSED(dev); ARG_UNUSED(dev);
IRQ_CONNECT(CONFIG_GPIO_CC32XX_A1_IRQ, CONFIG_GPIO_CC32XX_A1_IRQ_PRI, IRQ_CONNECT(DT_GPIO_CC32XX_A1_IRQ, DT_GPIO_CC32XX_A1_IRQ_PRI,
gpio_cc32xx_port_isr, DEVICE_GET(gpio_cc32xx_a1), 0); gpio_cc32xx_port_isr, DEVICE_GET(gpio_cc32xx_a1), 0);
MAP_IntPendClear(CONFIG_GPIO_CC32XX_A1_IRQ+16); MAP_IntPendClear(DT_GPIO_CC32XX_A1_IRQ+16);
irq_enable(CONFIG_GPIO_CC32XX_A1_IRQ); irq_enable(DT_GPIO_CC32XX_A1_IRQ);
return 0; return 0;
} }
DEVICE_AND_API_INIT(gpio_cc32xx_a1, CONFIG_GPIO_CC32XX_A1_NAME, DEVICE_AND_API_INIT(gpio_cc32xx_a1, DT_GPIO_CC32XX_A1_NAME,
&gpio_cc32xx_a1_init, &gpio_cc32xx_a1_data, &gpio_cc32xx_a1_init, &gpio_cc32xx_a1_data,
&gpio_cc32xx_a1_config, &gpio_cc32xx_a1_config,
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
@ -260,8 +260,8 @@ DEVICE_AND_API_INIT(gpio_cc32xx_a1, CONFIG_GPIO_CC32XX_A1_NAME,
#ifdef CONFIG_GPIO_CC32XX_A2 #ifdef CONFIG_GPIO_CC32XX_A2
static const struct gpio_cc32xx_config gpio_cc32xx_a2_config = { static const struct gpio_cc32xx_config gpio_cc32xx_a2_config = {
.port_base = CONFIG_GPIO_CC32XX_A2_BASE_ADDRESS, .port_base = DT_GPIO_CC32XX_A2_BASE_ADDRESS,
.irq_num = CONFIG_GPIO_CC32XX_A2_IRQ+16, .irq_num = DT_GPIO_CC32XX_A2_IRQ+16,
}; };
static struct device DEVICE_NAME_GET(gpio_cc32xx_a2); static struct device DEVICE_NAME_GET(gpio_cc32xx_a2);
@ -271,16 +271,16 @@ static int gpio_cc32xx_a2_init(struct device *dev)
{ {
ARG_UNUSED(dev); ARG_UNUSED(dev);
IRQ_CONNECT(CONFIG_GPIO_CC32XX_A2_IRQ, CONFIG_GPIO_CC32XX_A2_IRQ_PRI, IRQ_CONNECT(DT_GPIO_CC32XX_A2_IRQ, DT_GPIO_CC32XX_A2_IRQ_PRI,
gpio_cc32xx_port_isr, DEVICE_GET(gpio_cc32xx_a2), 0); gpio_cc32xx_port_isr, DEVICE_GET(gpio_cc32xx_a2), 0);
MAP_IntPendClear(CONFIG_GPIO_CC32XX_A2_IRQ+16); MAP_IntPendClear(DT_GPIO_CC32XX_A2_IRQ+16);
irq_enable(CONFIG_GPIO_CC32XX_A2_IRQ); irq_enable(DT_GPIO_CC32XX_A2_IRQ);
return 0; return 0;
} }
DEVICE_AND_API_INIT(gpio_cc32xx_a2, CONFIG_GPIO_CC32XX_A2_NAME, DEVICE_AND_API_INIT(gpio_cc32xx_a2, DT_GPIO_CC32XX_A2_NAME,
&gpio_cc32xx_a2_init, &gpio_cc32xx_a2_data, &gpio_cc32xx_a2_init, &gpio_cc32xx_a2_data,
&gpio_cc32xx_a2_config, &gpio_cc32xx_a2_config,
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
@ -290,8 +290,8 @@ DEVICE_AND_API_INIT(gpio_cc32xx_a2, CONFIG_GPIO_CC32XX_A2_NAME,
#ifdef CONFIG_GPIO_CC32XX_A3 #ifdef CONFIG_GPIO_CC32XX_A3
static const struct gpio_cc32xx_config gpio_cc32xx_a3_config = { static const struct gpio_cc32xx_config gpio_cc32xx_a3_config = {
.port_base = CONFIG_GPIO_CC32XX_A3_BASE_ADDRESS, .port_base = DT_GPIO_CC32XX_A3_BASE_ADDRESS,
.irq_num = CONFIG_GPIO_CC32XX_A3_IRQ+16, .irq_num = DT_GPIO_CC32XX_A3_IRQ+16,
}; };
static struct device DEVICE_NAME_GET(gpio_cc32xx_a3); static struct device DEVICE_NAME_GET(gpio_cc32xx_a3);
@ -301,16 +301,16 @@ static int gpio_cc32xx_a3_init(struct device *dev)
{ {
ARG_UNUSED(dev); ARG_UNUSED(dev);
IRQ_CONNECT(CONFIG_GPIO_CC32XX_A3_IRQ, CONFIG_GPIO_CC32XX_A3_IRQ_PRI, IRQ_CONNECT(DT_GPIO_CC32XX_A3_IRQ, DT_GPIO_CC32XX_A3_IRQ_PRI,
gpio_cc32xx_port_isr, DEVICE_GET(gpio_cc32xx_a3), 0); gpio_cc32xx_port_isr, DEVICE_GET(gpio_cc32xx_a3), 0);
MAP_IntPendClear(CONFIG_GPIO_CC32XX_A3_IRQ+16); MAP_IntPendClear(DT_GPIO_CC32XX_A3_IRQ+16);
irq_enable(CONFIG_GPIO_CC32XX_A3_IRQ); irq_enable(DT_GPIO_CC32XX_A3_IRQ);
return 0; return 0;
} }
DEVICE_AND_API_INIT(gpio_cc32xx_a3, CONFIG_GPIO_CC32XX_A3_NAME, DEVICE_AND_API_INIT(gpio_cc32xx_a3, DT_GPIO_CC32XX_A3_NAME,
&gpio_cc32xx_a3_init, &gpio_cc32xx_a3_data, &gpio_cc32xx_a3_init, &gpio_cc32xx_a3_data,
&gpio_cc32xx_a3_config, &gpio_cc32xx_a3_config,
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,

48
drivers/gpio/gpio_cmsdk_ahb.c
View file

@ -307,14 +307,14 @@ static int gpio_cmsdk_ahb_init(struct device *dev)
static void gpio_cmsdk_ahb_config_0(struct device *dev); static void gpio_cmsdk_ahb_config_0(struct device *dev);
static const struct gpio_cmsdk_ahb_cfg gpio_cmsdk_ahb_0_cfg = { static const struct gpio_cmsdk_ahb_cfg gpio_cmsdk_ahb_0_cfg = {
.port = ((volatile struct gpio_cmsdk_ahb *)CMSDK_AHB_GPIO0), .port = ((volatile struct gpio_cmsdk_ahb *)DT_CMSDK_AHB_GPIO0),
.gpio_config_func = gpio_cmsdk_ahb_config_0, .gpio_config_func = gpio_cmsdk_ahb_config_0,
.gpio_cc_as = {.bus = CMSDK_AHB, .state = SOC_ACTIVE, .gpio_cc_as = {.bus = CMSDK_AHB, .state = SOC_ACTIVE,
.device = CMSDK_AHB_GPIO0,}, .device = DT_CMSDK_AHB_GPIO0,},
.gpio_cc_ss = {.bus = CMSDK_AHB, .state = SOC_SLEEP, .gpio_cc_ss = {.bus = CMSDK_AHB, .state = SOC_SLEEP,
.device = CMSDK_AHB_GPIO0,}, .device = DT_CMSDK_AHB_GPIO0,},
.gpio_cc_dss = {.bus = CMSDK_AHB, .state = SOC_DEEPSLEEP, .gpio_cc_dss = {.bus = CMSDK_AHB, .state = SOC_DEEPSLEEP,
.device = CMSDK_AHB_GPIO0,}, .device = DT_CMSDK_AHB_GPIO0,},
}; };
static struct gpio_cmsdk_ahb_dev_data gpio_cmsdk_ahb_0_data; static struct gpio_cmsdk_ahb_dev_data gpio_cmsdk_ahb_0_data;
@ -328,10 +328,10 @@ DEVICE_AND_API_INIT(gpio_cmsdk_ahb_0,
static void gpio_cmsdk_ahb_config_0(struct device *dev) static void gpio_cmsdk_ahb_config_0(struct device *dev)
{ {
IRQ_CONNECT(IRQ_PORT0_ALL, CONFIG_GPIO_CMSDK_AHB_PORT0_IRQ_PRI, IRQ_CONNECT(DT_IRQ_PORT0_ALL, CONFIG_GPIO_CMSDK_AHB_PORT0_IRQ_PRI,
gpio_cmsdk_ahb_isr, gpio_cmsdk_ahb_isr,
DEVICE_GET(gpio_cmsdk_ahb_0), 0); DEVICE_GET(gpio_cmsdk_ahb_0), 0);
irq_enable(IRQ_PORT0_ALL); irq_enable(DT_IRQ_PORT0_ALL);
} }
#endif /* CONFIG_GPIO_CMSDK_AHB_PORT0 */ #endif /* CONFIG_GPIO_CMSDK_AHB_PORT0 */
@ -340,14 +340,14 @@ static void gpio_cmsdk_ahb_config_0(struct device *dev)
static void gpio_cmsdk_ahb_config_1(struct device *dev); static void gpio_cmsdk_ahb_config_1(struct device *dev);
static const struct gpio_cmsdk_ahb_cfg gpio_cmsdk_ahb_1_cfg = { static const struct gpio_cmsdk_ahb_cfg gpio_cmsdk_ahb_1_cfg = {
.port = ((volatile struct gpio_cmsdk_ahb *)CMSDK_AHB_GPIO1), .port = ((volatile struct gpio_cmsdk_ahb *)DT_CMSDK_AHB_GPIO1),
.gpio_config_func = gpio_cmsdk_ahb_config_1, .gpio_config_func = gpio_cmsdk_ahb_config_1,
.gpio_cc_as = {.bus = CMSDK_AHB, .state = SOC_ACTIVE, .gpio_cc_as = {.bus = CMSDK_AHB, .state = SOC_ACTIVE,
.device = CMSDK_AHB_GPIO1,}, .device = DT_CMSDK_AHB_GPIO1,},
.gpio_cc_ss = {.bus = CMSDK_AHB, .state = SOC_SLEEP, .gpio_cc_ss = {.bus = CMSDK_AHB, .state = SOC_SLEEP,
.device = CMSDK_AHB_GPIO1,}, .device = DT_CMSDK_AHB_GPIO1,},
.gpio_cc_dss = {.bus = CMSDK_AHB, .state = SOC_DEEPSLEEP, .gpio_cc_dss = {.bus = CMSDK_AHB, .state = SOC_DEEPSLEEP,
.device = CMSDK_AHB_GPIO1,}, .device = DT_CMSDK_AHB_GPIO1,},
}; };
static struct gpio_cmsdk_ahb_dev_data gpio_cmsdk_ahb_1_data; static struct gpio_cmsdk_ahb_dev_data gpio_cmsdk_ahb_1_data;
@ -361,10 +361,10 @@ DEVICE_AND_API_INIT(gpio_cmsdk_ahb_1,
static void gpio_cmsdk_ahb_config_1(struct device *dev) static void gpio_cmsdk_ahb_config_1(struct device *dev)
{ {
IRQ_CONNECT(IRQ_PORT1_ALL, CONFIG_GPIO_CMSDK_AHB_PORT1_IRQ_PRI, IRQ_CONNECT(DT_IRQ_PORT1_ALL, CONFIG_GPIO_CMSDK_AHB_PORT1_IRQ_PRI,
gpio_cmsdk_ahb_isr, gpio_cmsdk_ahb_isr,
DEVICE_GET(gpio_cmsdk_ahb_1), 0); DEVICE_GET(gpio_cmsdk_ahb_1), 0);
irq_enable(IRQ_PORT1_ALL); irq_enable(DT_IRQ_PORT1_ALL);
} }
#endif /* CONFIG_GPIO_CMSDK_AHB_PORT1 */ #endif /* CONFIG_GPIO_CMSDK_AHB_PORT1 */
@ -373,14 +373,14 @@ static void gpio_cmsdk_ahb_config_1(struct device *dev)
static void gpio_cmsdk_ahb_config_2(struct device *dev); static void gpio_cmsdk_ahb_config_2(struct device *dev);
static const struct gpio_cmsdk_ahb_cfg gpio_cmsdk_ahb_2_cfg = { static const struct gpio_cmsdk_ahb_cfg gpio_cmsdk_ahb_2_cfg = {
.port = ((volatile struct gpio_cmsdk_ahb *)CMSDK_AHB_GPIO2), .port = ((volatile struct gpio_cmsdk_ahb *)DT_CMSDK_AHB_GPIO2),
.gpio_config_func = gpio_cmsdk_ahb_config_2, .gpio_config_func = gpio_cmsdk_ahb_config_2,
.gpio_cc_as = {.bus = CMSDK_AHB, .state = SOC_ACTIVE, .gpio_cc_as = {.bus = CMSDK_AHB, .state = SOC_ACTIVE,
.device = CMSDK_AHB_GPIO2,}, .device = DT_CMSDK_AHB_GPIO2,},
.gpio_cc_ss = {.bus = CMSDK_AHB, .state = SOC_SLEEP, .gpio_cc_ss = {.bus = CMSDK_AHB, .state = SOC_SLEEP,
.device = CMSDK_AHB_GPIO2,}, .device = DT_CMSDK_AHB_GPIO2,},
.gpio_cc_dss = {.bus = CMSDK_AHB, .state = SOC_DEEPSLEEP, .gpio_cc_dss = {.bus = CMSDK_AHB, .state = SOC_DEEPSLEEP,
.device = CMSDK_AHB_GPIO2,}, .device = DT_CMSDK_AHB_GPIO2,},
}; };
static struct gpio_cmsdk_ahb_dev_data gpio_cmsdk_ahb_2_data; static struct gpio_cmsdk_ahb_dev_data gpio_cmsdk_ahb_2_data;
@ -394,10 +394,10 @@ DEVICE_AND_API_INIT(gpio_cmsdk_ahb_2,
static void gpio_cmsdk_ahb_config_2(struct device *dev) static void gpio_cmsdk_ahb_config_2(struct device *dev)
{ {
IRQ_CONNECT(IRQ_PORT2_ALL, CONFIG_GPIO_CMSDK_AHB_PORT2_IRQ_PRI, IRQ_CONNECT(DT_IRQ_PORT2_ALL, CONFIG_GPIO_CMSDK_AHB_PORT2_IRQ_PRI,
gpio_cmsdk_ahb_isr, gpio_cmsdk_ahb_isr,
DEVICE_GET(gpio_cmsdk_ahb_2), 0); DEVICE_GET(gpio_cmsdk_ahb_2), 0);
irq_enable(IRQ_PORT2_ALL); irq_enable(DT_IRQ_PORT2_ALL);
} }
#endif /* CONFIG_GPIO_CMSDK_AHB_PORT2 */ #endif /* CONFIG_GPIO_CMSDK_AHB_PORT2 */
@ -406,14 +406,14 @@ static void gpio_cmsdk_ahb_config_2(struct device *dev)
static void gpio_cmsdk_ahb_config_3(struct device *dev); static void gpio_cmsdk_ahb_config_3(struct device *dev);
static const struct gpio_cmsdk_ahb_cfg gpio_cmsdk_ahb_3_cfg = { static const struct gpio_cmsdk_ahb_cfg gpio_cmsdk_ahb_3_cfg = {
.port = ((volatile struct gpio_cmsdk_ahb *)CMSDK_AHB_GPIO3), .port = ((volatile struct gpio_cmsdk_ahb *)DT_CMSDK_AHB_GPIO3),
.gpio_config_func = gpio_cmsdk_ahb_config_3, .gpio_config_func = gpio_cmsdk_ahb_config_3,
.gpio_cc_as = {.bus = CMSDK_AHB, .state = SOC_ACTIVE, .gpio_cc_as = {.bus = CMSDK_AHB, .state = SOC_ACTIVE,
.device = CMSDK_AHB_GPIO3,}, .device = DT_CMSDK_AHB_GPIO3,},
.gpio_cc_ss = {.bus = CMSDK_AHB, .state = SOC_SLEEP, .gpio_cc_ss = {.bus = CMSDK_AHB, .state = SOC_SLEEP,
.device = CMSDK_AHB_GPIO3,}, .device = DT_CMSDK_AHB_GPIO3,},
.gpio_cc_dss = {.bus = CMSDK_AHB, .state = SOC_DEEPSLEEP, .gpio_cc_dss = {.bus = CMSDK_AHB, .state = SOC_DEEPSLEEP,
.device = CMSDK_AHB_GPIO3,}, .device = DT_CMSDK_AHB_GPIO3,},
}; };
static struct gpio_cmsdk_ahb_dev_data gpio_cmsdk_ahb_3_data; static struct gpio_cmsdk_ahb_dev_data gpio_cmsdk_ahb_3_data;
@ -427,9 +427,9 @@ DEVICE_AND_API_INIT(gpio_cmsdk_ahb_3,
static void gpio_cmsdk_ahb_config_3(struct device *dev) static void gpio_cmsdk_ahb_config_3(struct device *dev)
{ {
IRQ_CONNECT(IRQ_PORT3_ALL, CONFIG_GPIO_CMSDK_AHB_PORT3_IRQ_PRI, IRQ_CONNECT(DT_IRQ_PORT3_ALL, CONFIG_GPIO_CMSDK_AHB_PORT3_IRQ_PRI,
gpio_cmsdk_ahb_isr, gpio_cmsdk_ahb_isr,
DEVICE_GET(gpio_cmsdk_ahb_3), 0); DEVICE_GET(gpio_cmsdk_ahb_3), 0);
irq_enable(IRQ_PORT3_ALL); irq_enable(DT_IRQ_PORT3_ALL);
} }
#endif /* CONFIG_GPIO_CMSDK_AHB_PORT3 */ #endif /* CONFIG_GPIO_CMSDK_AHB_PORT3 */

42
drivers/gpio/gpio_dw.c
View file

@ -499,9 +499,9 @@ static void gpio_config_0_irq(struct device *port);
static const struct gpio_dw_config gpio_config_0 = { static const struct gpio_dw_config gpio_config_0 = {
#ifdef CONFIG_GPIO_DW_0_IRQ_DIRECT #ifdef CONFIG_GPIO_DW_0_IRQ_DIRECT
.irq_num = GPIO_DW_0_IRQ, .irq_num = DT_GPIO_DW_0_IRQ,
#endif #endif
.bits = GPIO_DW_0_BITS, .bits = DT_GPIO_DW_0_BITS,
.config_func = gpio_config_0_irq, .config_func = gpio_config_0_irq,
#ifdef CONFIG_GPIO_DW_0_IRQ_SHARED #ifdef CONFIG_GPIO_DW_0_IRQ_SHARED
.shared_irq_dev_name = CONFIG_GPIO_DW_0_IRQ_SHARED_NAME, .shared_irq_dev_name = CONFIG_GPIO_DW_0_IRQ_SHARED_NAME,
@ -512,7 +512,7 @@ static const struct gpio_dw_config gpio_config_0 = {
}; };
static struct gpio_dw_runtime gpio_0_runtime = { static struct gpio_dw_runtime gpio_0_runtime = {
.base_addr = GPIO_DW_0_BASE_ADDR, .base_addr = DT_GPIO_DW_0_BASE_ADDR,
#if CONFIG_PCI #if CONFIG_PCI
.pci_dev.class_type = GPIO_DW_PCI_CLASS, .pci_dev.class_type = GPIO_DW_PCI_CLASS,
.pci_dev.bus = GPIO_DW_0_PCI_BUS, .pci_dev.bus = GPIO_DW_0_PCI_BUS,
@ -539,12 +539,12 @@ DEVICE_AND_API_INIT(gpio_dw_0, CONFIG_GPIO_DW_0_NAME, gpio_dw_initialize,
static void gpio_config_0_irq(struct device *port) static void gpio_config_0_irq(struct device *port)
{ {
#if (GPIO_DW_0_IRQ > 0) #if (DT_GPIO_DW_0_IRQ > 0)
const struct gpio_dw_config *config = port->config->config_info; const struct gpio_dw_config *config = port->config->config_info;
#ifdef CONFIG_GPIO_DW_0_IRQ_DIRECT #ifdef CONFIG_GPIO_DW_0_IRQ_DIRECT
IRQ_CONNECT(GPIO_DW_0_IRQ, CONFIG_GPIO_DW_0_IRQ_PRI, gpio_dw_isr, IRQ_CONNECT(DT_GPIO_DW_0_IRQ, CONFIG_GPIO_DW_0_IRQ_PRI, gpio_dw_isr,
DEVICE_GET(gpio_dw_0), GPIO_DW_0_IRQ_FLAGS); DEVICE_GET(gpio_dw_0), DT_GPIO_DW_0_IRQ_FLAGS);
irq_enable(config->irq_num); irq_enable(config->irq_num);
#elif defined(CONFIG_GPIO_DW_0_IRQ_SHARED) #elif defined(CONFIG_GPIO_DW_0_IRQ_SHARED)
struct device *shared_irq_dev; struct device *shared_irq_dev;
@ -567,9 +567,9 @@ static void gpio_config_1_irq(struct device *port);
static const struct gpio_dw_config gpio_dw_config_1 = { static const struct gpio_dw_config gpio_dw_config_1 = {
#ifdef CONFIG_GPIO_DW_1_IRQ_DIRECT #ifdef CONFIG_GPIO_DW_1_IRQ_DIRECT
.irq_num = GPIO_DW_1_IRQ, .irq_num = DT_GPIO_DW_1_IRQ,
#endif #endif
.bits = GPIO_DW_1_BITS, .bits = DT_GPIO_DW_1_BITS,
.config_func = gpio_config_1_irq, .config_func = gpio_config_1_irq,
#ifdef CONFIG_GPIO_DW_1_IRQ_SHARED #ifdef CONFIG_GPIO_DW_1_IRQ_SHARED
@ -581,7 +581,7 @@ static const struct gpio_dw_config gpio_dw_config_1 = {
}; };
static struct gpio_dw_runtime gpio_1_runtime = { static struct gpio_dw_runtime gpio_1_runtime = {
.base_addr = GPIO_DW_1_BASE_ADDR, .base_addr = DT_GPIO_DW_1_BASE_ADDR,
#if CONFIG_PCI #if CONFIG_PCI
.pci_dev.class_type = GPIO_DW_PCI_CLASS, .pci_dev.class_type = GPIO_DW_PCI_CLASS,
.pci_dev.bus = GPIO_DW_1_PCI_BUS, .pci_dev.bus = GPIO_DW_1_PCI_BUS,
@ -607,11 +607,11 @@ DEVICE_AND_API_INIT(gpio_dw_1, CONFIG_GPIO_DW_1_NAME, gpio_dw_initialize,
static void gpio_config_1_irq(struct device *port) static void gpio_config_1_irq(struct device *port)
{ {
#if (GPIO_DW_1_IRQ > 0) #if (DT_GPIO_DW_1_IRQ > 0)
const struct gpio_dw_config *config = port->config->config_info; const struct gpio_dw_config *config = port->config->config_info;
#ifdef CONFIG_GPIO_DW_1_IRQ_DIRECT #ifdef CONFIG_GPIO_DW_1_IRQ_DIRECT
IRQ_CONNECT(GPIO_DW_1_IRQ, CONFIG_GPIO_DW_1_IRQ_PRI, gpio_dw_isr, IRQ_CONNECT(DT_GPIO_DW_1_IRQ, CONFIG_GPIO_DW_1_IRQ_PRI, gpio_dw_isr,
DEVICE_GET(gpio_dw_1), GPIO_DW_1_IRQ_FLAGS); DEVICE_GET(gpio_dw_1), GPIO_DW_1_IRQ_FLAGS);
irq_enable(config->irq_num); irq_enable(config->irq_num);
#elif defined(CONFIG_GPIO_DW_1_IRQ_SHARED) #elif defined(CONFIG_GPIO_DW_1_IRQ_SHARED)
@ -634,9 +634,9 @@ static void gpio_config_2_irq(struct device *port);
static const struct gpio_dw_config gpio_dw_config_2 = { static const struct gpio_dw_config gpio_dw_config_2 = {
#ifdef CONFIG_GPIO_DW_2_IRQ_DIRECT #ifdef CONFIG_GPIO_DW_2_IRQ_DIRECT
.irq_num = GPIO_DW_2_IRQ, .irq_num = DT_GPIO_DW_2_IRQ,
#endif #endif
.bits = GPIO_DW_2_BITS, .bits = DT_GPIO_DW_2_BITS,
.config_func = gpio_config_2_irq, .config_func = gpio_config_2_irq,
#ifdef CONFIG_GPIO_DW_2_IRQ_SHARED #ifdef CONFIG_GPIO_DW_2_IRQ_SHARED
@ -648,7 +648,7 @@ static const struct gpio_dw_config gpio_dw_config_2 = {
}; };
static struct gpio_dw_runtime gpio_2_runtime = { static struct gpio_dw_runtime gpio_2_runtime = {
.base_addr = GPIO_DW_2_BASE_ADDR, .base_addr = DT_GPIO_DW_2_BASE_ADDR,
#if CONFIG_PCI #if CONFIG_PCI
.pci_dev.class_type = GPIO_DW_PCI_CLASS, .pci_dev.class_type = GPIO_DW_PCI_CLASS,
.pci_dev.bus = GPIO_DW_2_PCI_BUS, .pci_dev.bus = GPIO_DW_2_PCI_BUS,
@ -674,11 +674,11 @@ DEVICE_AND_API_INIT(gpio_dw_2, CONFIG_GPIO_DW_2_NAME, gpio_dw_initialize,
static void gpio_config_2_irq(struct device *port) static void gpio_config_2_irq(struct device *port)
{ {
#if (GPIO_DW_2_IRQ > 0) #if (DT_GPIO_DW_2_IRQ > 0)
const struct gpio_dw_config *config = port->config->config_info; const struct gpio_dw_config *config = port->config->config_info;
#ifdef CONFIG_GPIO_DW_2_IRQ_DIRECT #ifdef CONFIG_GPIO_DW_2_IRQ_DIRECT
IRQ_CONNECT(GPIO_DW_2_IRQ, CONFIG_GPIO_DW_2_IRQ_PRI, gpio_dw_isr, IRQ_CONNECT(DT_GPIO_DW_2_IRQ, CONFIG_GPIO_DW_2_IRQ_PRI, gpio_dw_isr,
DEVICE_GET(gpio_dw_2), GPIO_DW_2_IRQ_FLAGS); DEVICE_GET(gpio_dw_2), GPIO_DW_2_IRQ_FLAGS);
irq_enable(config->irq_num); irq_enable(config->irq_num);
#elif defined(CONFIG_GPIO_DW_2_IRQ_SHARED) #elif defined(CONFIG_GPIO_DW_2_IRQ_SHARED)
@ -701,9 +701,9 @@ static void gpio_config_3_irq(struct device *port);
static const struct gpio_dw_config gpio_dw_config_3 = { static const struct gpio_dw_config gpio_dw_config_3 = {
#ifdef CONFIG_GPIO_DW_3_IRQ_DIRECT #ifdef CONFIG_GPIO_DW_3_IRQ_DIRECT
.irq_num = GPIO_DW_3_IRQ, .irq_num = DT_GPIO_DW_3_IRQ,
#endif #endif
.bits = GPIO_DW_3_BITS, .bits = DT_GPIO_DW_3_BITS,
.config_func = gpio_config_3_irq, .config_func = gpio_config_3_irq,
#ifdef CONFIG_GPIO_DW_3_IRQ_SHARED #ifdef CONFIG_GPIO_DW_3_IRQ_SHARED
@ -715,7 +715,7 @@ static const struct gpio_dw_config gpio_dw_config_3 = {
}; };
static struct gpio_dw_runtime gpio_3_runtime = { static struct gpio_dw_runtime gpio_3_runtime = {
.base_addr = GPIO_DW_3_BASE_ADDR, .base_addr = DT_GPIO_DW_3_BASE_ADDR,
#if CONFIG_PCI #if CONFIG_PCI
.pci_dev.class_type = GPIO_DW_PCI_CLASS, .pci_dev.class_type = GPIO_DW_PCI_CLASS,
.pci_dev.bus = GPIO_DW_3_PCI_BUS, .pci_dev.bus = GPIO_DW_3_PCI_BUS,
@ -741,11 +741,11 @@ DEVICE_AND_API_INIT(gpio_dw_3, CONFIG_GPIO_DW_3_NAME, gpio_dw_initialize,
static void gpio_config_3_irq(struct device *port) static void gpio_config_3_irq(struct device *port)
{ {
#if (GPIO_DW_3_IRQ > 0) #if (DT_GPIO_DW_3_IRQ > 0)
const struct gpio_dw_config *config = port->config->config_info; const struct gpio_dw_config *config = port->config->config_info;
#ifdef CONFIG_GPIO_DW_3_IRQ_DIRECT #ifdef CONFIG_GPIO_DW_3_IRQ_DIRECT
IRQ_CONNECT(GPIO_DW_3_IRQ, CONFIG_GPIO_DW_3_IRQ_PRI, gpio_dw_isr, IRQ_CONNECT(DT_GPIO_DW_3_IRQ, CONFIG_GPIO_DW_3_IRQ_PRI, gpio_dw_isr,
DEVICE_GET(gpio_dw_3), GPIO_DW_3_IRQ_FLAGS); DEVICE_GET(gpio_dw_3), GPIO_DW_3_IRQ_FLAGS);
irq_enable(config->irq_num); irq_enable(config->irq_num);
#elif defined(CONFIG_GPIO_DW_3_IRQ_SHARED) #elif defined(CONFIG_GPIO_DW_3_IRQ_SHARED)

18
drivers/gpio/gpio_gecko.c
View file

@ -285,7 +285,7 @@ static const struct gpio_gecko_common_config gpio_gecko_common_config = {
static struct gpio_gecko_common_data gpio_gecko_common_data; static struct gpio_gecko_common_data gpio_gecko_common_data;
DEVICE_AND_API_INIT(gpio_gecko_common, CONFIG_GPIO_GECKO_COMMON_NAME, DEVICE_AND_API_INIT(gpio_gecko_common, DT_GPIO_GECKO_COMMON_NAME,
gpio_gecko_common_init, gpio_gecko_common_init,
&gpio_gecko_common_data, &gpio_gecko_common_config, &gpio_gecko_common_data, &gpio_gecko_common_config,
POST_KERNEL, CONFIG_GPIO_GECKO_COMMON_INIT_PRIORITY, POST_KERNEL, CONFIG_GPIO_GECKO_COMMON_INIT_PRIORITY,
@ -294,10 +294,10 @@ DEVICE_AND_API_INIT(gpio_gecko_common, CONFIG_GPIO_GECKO_COMMON_NAME,
static int gpio_gecko_common_init(struct device *dev) static int gpio_gecko_common_init(struct device *dev)
{ {
gpio_gecko_common_data.count = 0; gpio_gecko_common_data.count = 0;
IRQ_CONNECT(GPIO_EVEN_IRQn, CONFIG_GPIO_GECKO_COMMON_EVEN_PRI, IRQ_CONNECT(GPIO_EVEN_IRQn, DT_GPIO_GECKO_COMMON_EVEN_PRI,
gpio_gecko_common_isr, DEVICE_GET(gpio_gecko_common), 0); gpio_gecko_common_isr, DEVICE_GET(gpio_gecko_common), 0);
IRQ_CONNECT(GPIO_ODD_IRQn, CONFIG_GPIO_GECKO_COMMON_ODD_PRI, IRQ_CONNECT(GPIO_ODD_IRQn, DT_GPIO_GECKO_COMMON_ODD_PRI,
gpio_gecko_common_isr, DEVICE_GET(gpio_gecko_common), 0); gpio_gecko_common_isr, DEVICE_GET(gpio_gecko_common), 0);
irq_enable(GPIO_EVEN_IRQn); irq_enable(GPIO_EVEN_IRQn);
@ -318,7 +318,7 @@ static const struct gpio_gecko_config gpio_gecko_porta_config = {
static struct gpio_gecko_data gpio_gecko_porta_data; static struct gpio_gecko_data gpio_gecko_porta_data;
DEVICE_AND_API_INIT(gpio_gecko_porta, CONFIG_GPIO_GECKO_PORTA_NAME, DEVICE_AND_API_INIT(gpio_gecko_porta, DT_GPIO_GECKO_PORTA_NAME,
gpio_gecko_porta_init, gpio_gecko_porta_init,
&gpio_gecko_porta_data, &gpio_gecko_porta_config, &gpio_gecko_porta_data, &gpio_gecko_porta_config,
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
@ -341,7 +341,7 @@ static const struct gpio_gecko_config gpio_gecko_portb_config = {
static struct gpio_gecko_data gpio_gecko_portb_data; static struct gpio_gecko_data gpio_gecko_portb_data;
DEVICE_AND_API_INIT(gpio_gecko_portb, CONFIG_GPIO_GECKO_PORTB_NAME, DEVICE_AND_API_INIT(gpio_gecko_portb, DT_GPIO_GECKO_PORTB_NAME,
gpio_gecko_portb_init, gpio_gecko_portb_init,
&gpio_gecko_portb_data, &gpio_gecko_portb_config, &gpio_gecko_portb_data, &gpio_gecko_portb_config,
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
@ -364,7 +364,7 @@ static const struct gpio_gecko_config gpio_gecko_portc_config = {
static struct gpio_gecko_data gpio_gecko_portc_data; static struct gpio_gecko_data gpio_gecko_portc_data;
DEVICE_AND_API_INIT(gpio_gecko_portc, CONFIG_GPIO_GECKO_PORTC_NAME, DEVICE_AND_API_INIT(gpio_gecko_portc, DT_GPIO_GECKO_PORTC_NAME,
gpio_gecko_portc_init, gpio_gecko_portc_init,
&gpio_gecko_portc_data, &gpio_gecko_portc_config, &gpio_gecko_portc_data, &gpio_gecko_portc_config,
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
@ -387,7 +387,7 @@ static const struct gpio_gecko_config gpio_gecko_portd_config = {
static struct gpio_gecko_data gpio_gecko_portd_data; static struct gpio_gecko_data gpio_gecko_portd_data;
DEVICE_AND_API_INIT(gpio_gecko_portd, CONFIG_GPIO_GECKO_PORTD_NAME, DEVICE_AND_API_INIT(gpio_gecko_portd, DT_GPIO_GECKO_PORTD_NAME,
gpio_gecko_portd_init, gpio_gecko_portd_init,
&gpio_gecko_portd_data, &gpio_gecko_portd_config, &gpio_gecko_portd_data, &gpio_gecko_portd_config,
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
@ -410,7 +410,7 @@ static const struct gpio_gecko_config gpio_gecko_porte_config = {
static struct gpio_gecko_data gpio_gecko_porte_data; static struct gpio_gecko_data gpio_gecko_porte_data;
DEVICE_AND_API_INIT(gpio_gecko_porte, CONFIG_GPIO_GECKO_PORTE_NAME, DEVICE_AND_API_INIT(gpio_gecko_porte, DT_GPIO_GECKO_PORTE_NAME,
gpio_gecko_porte_init, gpio_gecko_porte_init,
&gpio_gecko_porte_data, &gpio_gecko_porte_config, &gpio_gecko_porte_data, &gpio_gecko_porte_config,
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
@ -433,7 +433,7 @@ static const struct gpio_gecko_config gpio_gecko_portf_config = {
static struct gpio_gecko_data gpio_gecko_portf_data; static struct gpio_gecko_data gpio_gecko_portf_data;
DEVICE_AND_API_INIT(gpio_gecko_portf, CONFIG_GPIO_GECKO_PORTF_NAME, DEVICE_AND_API_INIT(gpio_gecko_portf, DT_GPIO_GECKO_PORTF_NAME,
gpio_gecko_portf_init, gpio_gecko_portf_init,
&gpio_gecko_portf_data, &gpio_gecko_portf_config, &gpio_gecko_portf_data, &gpio_gecko_portf_config,
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,

112
drivers/gpio/gpio_imx.c
View file

@ -183,12 +183,12 @@ static const struct gpio_driver_api imx_gpio_driver_api = {
static int imx_gpio_1_init(struct device *dev); static int imx_gpio_1_init(struct device *dev);
static const struct imx_gpio_config imx_gpio_1_config = { static const struct imx_gpio_config imx_gpio_1_config = {
.base = (GPIO_Type *)CONFIG_GPIO_IMX_PORT_1_BASE_ADDRESS, .base = (GPIO_Type *)DT_GPIO_IMX_PORT_1_BASE_ADDRESS,
}; };
static struct imx_gpio_data imx_gpio_1_data; static struct imx_gpio_data imx_gpio_1_data;
DEVICE_AND_API_INIT(imx_gpio_1, CONFIG_GPIO_IMX_PORT_1_NAME, DEVICE_AND_API_INIT(imx_gpio_1, DT_GPIO_IMX_PORT_1_NAME,
imx_gpio_1_init, imx_gpio_1_init,
&imx_gpio_1_data, &imx_gpio_1_config, &imx_gpio_1_data, &imx_gpio_1_config,
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
@ -196,17 +196,17 @@ DEVICE_AND_API_INIT(imx_gpio_1, CONFIG_GPIO_IMX_PORT_1_NAME,
static int imx_gpio_1_init(struct device *dev) static int imx_gpio_1_init(struct device *dev)
{ {
IRQ_CONNECT(CONFIG_GPIO_IMX_PORT_1_IRQ_0, IRQ_CONNECT(DT_GPIO_IMX_PORT_1_IRQ_0,
CONFIG_GPIO_IMX_PORT_1_IRQ_0_PRI, DT_GPIO_IMX_PORT_1_IRQ_0_PRI,
imx_gpio_port_isr, DEVICE_GET(imx_gpio_1), 0); imx_gpio_port_isr, DEVICE_GET(imx_gpio_1), 0);
irq_enable(CONFIG_GPIO_IMX_PORT_1_IRQ_0); irq_enable(DT_GPIO_IMX_PORT_1_IRQ_0);
IRQ_CONNECT(CONFIG_GPIO_IMX_PORT_1_IRQ_1, IRQ_CONNECT(DT_GPIO_IMX_PORT_1_IRQ_1,
CONFIG_GPIO_IMX_PORT_1_IRQ_1_PRI, DT_GPIO_IMX_PORT_1_IRQ_1_PRI,
imx_gpio_port_isr, DEVICE_GET(imx_gpio_1), 0); imx_gpio_port_isr, DEVICE_GET(imx_gpio_1), 0);
irq_enable(CONFIG_GPIO_IMX_PORT_1_IRQ_1); irq_enable(DT_GPIO_IMX_PORT_1_IRQ_1);
return 0; return 0;
} }
@ -216,12 +216,12 @@ static int imx_gpio_1_init(struct device *dev)
static int imx_gpio_2_init(struct device *dev); static int imx_gpio_2_init(struct device *dev);
static const struct imx_gpio_config imx_gpio_2_config = { static const struct imx_gpio_config imx_gpio_2_config = {
.base = (GPIO_Type *)CONFIG_GPIO_IMX_PORT_2_BASE_ADDRESS, .base = (GPIO_Type *)DT_GPIO_IMX_PORT_2_BASE_ADDRESS,
}; };
static struct imx_gpio_data imx_gpio_2_data; static struct imx_gpio_data imx_gpio_2_data;
DEVICE_AND_API_INIT(imx_gpio_2, CONFIG_GPIO_IMX_PORT_2_NAME, DEVICE_AND_API_INIT(imx_gpio_2, DT_GPIO_IMX_PORT_2_NAME,
imx_gpio_2_init, imx_gpio_2_init,
&imx_gpio_2_data, &imx_gpio_2_config, &imx_gpio_2_data, &imx_gpio_2_config,
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
@ -229,17 +229,17 @@ DEVICE_AND_API_INIT(imx_gpio_2, CONFIG_GPIO_IMX_PORT_2_NAME,
static int imx_gpio_2_init(struct device *dev) static int imx_gpio_2_init(struct device *dev)
{ {
IRQ_CONNECT(CONFIG_GPIO_IMX_PORT_2_IRQ_0, IRQ_CONNECT(DT_GPIO_IMX_PORT_2_IRQ_0,
CONFIG_GPIO_IMX_PORT_2_IRQ_0_PRI, DT_GPIO_IMX_PORT_2_IRQ_0_PRI,
imx_gpio_port_isr, DEVICE_GET(imx_gpio_2), 0); imx_gpio_port_isr, DEVICE_GET(imx_gpio_2), 0);
irq_enable(CONFIG_GPIO_IMX_PORT_2_IRQ_0); irq_enable(DT_GPIO_IMX_PORT_2_IRQ_0);
IRQ_CONNECT(CONFIG_GPIO_IMX_PORT_2_IRQ_1, IRQ_CONNECT(DT_GPIO_IMX_PORT_2_IRQ_1,
CONFIG_GPIO_IMX_PORT_2_IRQ_1_PRI, DT_GPIO_IMX_PORT_2_IRQ_1_PRI,
imx_gpio_port_isr, DEVICE_GET(imx_gpio_2), 0); imx_gpio_port_isr, DEVICE_GET(imx_gpio_2), 0);
irq_enable(CONFIG_GPIO_IMX_PORT_2_IRQ_1); irq_enable(DT_GPIO_IMX_PORT_2_IRQ_1);
return 0; return 0;
} }
@ -249,12 +249,12 @@ static int imx_gpio_2_init(struct device *dev)
static int imx_gpio_3_init(struct device *dev); static int imx_gpio_3_init(struct device *dev);
static const struct imx_gpio_config imx_gpio_3_config = { static const struct imx_gpio_config imx_gpio_3_config = {
.base = (GPIO_Type *)CONFIG_GPIO_IMX_PORT_3_BASE_ADDRESS, .base = (GPIO_Type *)DT_GPIO_IMX_PORT_3_BASE_ADDRESS,
}; };
static struct imx_gpio_data imx_gpio_3_data; static struct imx_gpio_data imx_gpio_3_data;
DEVICE_AND_API_INIT(imx_gpio_3, CONFIG_GPIO_IMX_PORT_3_NAME, DEVICE_AND_API_INIT(imx_gpio_3, DT_GPIO_IMX_PORT_3_NAME,
imx_gpio_3_init, imx_gpio_3_init,
&imx_gpio_3_data, &imx_gpio_3_config, &imx_gpio_3_data, &imx_gpio_3_config,
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
@ -262,17 +262,17 @@ DEVICE_AND_API_INIT(imx_gpio_3, CONFIG_GPIO_IMX_PORT_3_NAME,
static int imx_gpio_3_init(struct device *dev) static int imx_gpio_3_init(struct device *dev)
{ {
IRQ_CONNECT(CONFIG_GPIO_IMX_PORT_3_IRQ_0, IRQ_CONNECT(DT_GPIO_IMX_PORT_3_IRQ_0,
CONFIG_GPIO_IMX_PORT_3_IRQ_0_PRI, DT_GPIO_IMX_PORT_3_IRQ_0_PRI,
imx_gpio_port_isr, DEVICE_GET(imx_gpio_3), 0); imx_gpio_port_isr, DEVICE_GET(imx_gpio_3), 0);
irq_enable(CONFIG_GPIO_IMX_PORT_3_IRQ_0); irq_enable(DT_GPIO_IMX_PORT_3_IRQ_0);
IRQ_CONNECT(CONFIG_GPIO_IMX_PORT_3_IRQ_1, IRQ_CONNECT(DT_GPIO_IMX_PORT_3_IRQ_1,
CONFIG_GPIO_IMX_PORT_3_IRQ_1_PRI, DT_GPIO_IMX_PORT_3_IRQ_1_PRI,
imx_gpio_port_isr, DEVICE_GET(imx_gpio_3), 0); imx_gpio_port_isr, DEVICE_GET(imx_gpio_3), 0);
irq_enable(CONFIG_GPIO_IMX_PORT_3_IRQ_1); irq_enable(DT_GPIO_IMX_PORT_3_IRQ_1);
return 0; return 0;
} }
@ -282,12 +282,12 @@ static int imx_gpio_3_init(struct device *dev)
static int imx_gpio_4_init(struct device *dev); static int imx_gpio_4_init(struct device *dev);
static const struct imx_gpio_config imx_gpio_4_config = { static const struct imx_gpio_config imx_gpio_4_config = {
.base = (GPIO_Type *)CONFIG_GPIO_IMX_PORT_4_BASE_ADDRESS, .base = (GPIO_Type *)DT_GPIO_IMX_PORT_4_BASE_ADDRESS,
}; };
static struct imx_gpio_data imx_gpio_4_data; static struct imx_gpio_data imx_gpio_4_data;
DEVICE_AND_API_INIT(imx_gpio_4, CONFIG_GPIO_IMX_PORT_4_NAME, DEVICE_AND_API_INIT(imx_gpio_4, DT_GPIO_IMX_PORT_4_NAME,
imx_gpio_4_init, imx_gpio_4_init,
&imx_gpio_4_data, &imx_gpio_4_config, &imx_gpio_4_data, &imx_gpio_4_config,
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
@ -295,17 +295,17 @@ DEVICE_AND_API_INIT(imx_gpio_4, CONFIG_GPIO_IMX_PORT_4_NAME,
static int imx_gpio_4_init(struct device *dev) static int imx_gpio_4_init(struct device *dev)
{ {
IRQ_CONNECT(CONFIG_GPIO_IMX_PORT_4_IRQ_0, IRQ_CONNECT(DT_GPIO_IMX_PORT_4_IRQ_0,
CONFIG_GPIO_IMX_PORT_4_IRQ_0_PRI, DT_GPIO_IMX_PORT_4_IRQ_0_PRI,
imx_gpio_port_isr, DEVICE_GET(imx_gpio_4), 0); imx_gpio_port_isr, DEVICE_GET(imx_gpio_4), 0);
irq_enable(CONFIG_GPIO_IMX_PORT_4_IRQ_0); irq_enable(DT_GPIO_IMX_PORT_4_IRQ_0);
IRQ_CONNECT(CONFIG_GPIO_IMX_PORT_4_IRQ_1, IRQ_CONNECT(DT_GPIO_IMX_PORT_4_IRQ_1,
CONFIG_GPIO_IMX_PORT_4_IRQ_1_PRI, DT_GPIO_IMX_PORT_4_IRQ_1_PRI,
imx_gpio_port_isr, DEVICE_GET(imx_gpio_4), 0); imx_gpio_port_isr, DEVICE_GET(imx_gpio_4), 0);
irq_enable(CONFIG_GPIO_IMX_PORT_4_IRQ_1); irq_enable(DT_GPIO_IMX_PORT_4_IRQ_1);
return 0; return 0;
} }
@ -315,12 +315,12 @@ static int imx_gpio_4_init(struct device *dev)
static int imx_gpio_5_init(struct device *dev); static int imx_gpio_5_init(struct device *dev);
static const struct imx_gpio_config imx_gpio_5_config = { static const struct imx_gpio_config imx_gpio_5_config = {
.base = (GPIO_Type *)CONFIG_GPIO_IMX_PORT_5_BASE_ADDRESS, .base = (GPIO_Type *)DT_GPIO_IMX_PORT_5_BASE_ADDRESS,
}; };
static struct imx_gpio_data imx_gpio_5_data; static struct imx_gpio_data imx_gpio_5_data;
DEVICE_AND_API_INIT(imx_gpio_5, CONFIG_GPIO_IMX_PORT_5_NAME, DEVICE_AND_API_INIT(imx_gpio_5, DT_GPIO_IMX_PORT_5_NAME,
imx_gpio_5_init, imx_gpio_5_init,
&imx_gpio_5_data, &imx_gpio_5_config, &imx_gpio_5_data, &imx_gpio_5_config,
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
@ -328,17 +328,17 @@ DEVICE_AND_API_INIT(imx_gpio_5, CONFIG_GPIO_IMX_PORT_5_NAME,
static int imx_gpio_5_init(struct device *dev) static int imx_gpio_5_init(struct device *dev)
{ {
IRQ_CONNECT(CONFIG_GPIO_IMX_PORT_5_IRQ_0, IRQ_CONNECT(DT_GPIO_IMX_PORT_5_IRQ_0,
CONFIG_GPIO_IMX_PORT_5_IRQ_0_PRI, DT_GPIO_IMX_PORT_5_IRQ_0_PRI,
imx_gpio_port_isr, DEVICE_GET(imx_gpio_5), 0); imx_gpio_port_isr, DEVICE_GET(imx_gpio_5), 0);
irq_enable(CONFIG_GPIO_IMX_PORT_5_IRQ_0); irq_enable(DT_GPIO_IMX_PORT_5_IRQ_0);
IRQ_CONNECT(CONFIG_GPIO_IMX_PORT_5_IRQ_1, IRQ_CONNECT(DT_GPIO_IMX_PORT_5_IRQ_1,
CONFIG_GPIO_IMX_PORT_5_IRQ_1_PRI, DT_GPIO_IMX_PORT_5_IRQ_1_PRI,
imx_gpio_port_isr, DEVICE_GET(imx_gpio_5), 0); imx_gpio_port_isr, DEVICE_GET(imx_gpio_5), 0);
irq_enable(CONFIG_GPIO_IMX_PORT_5_IRQ_1); irq_enable(DT_GPIO_IMX_PORT_5_IRQ_1);
return 0; return 0;
} }
@ -348,12 +348,12 @@ static int imx_gpio_5_init(struct device *dev)
static int imx_gpio_6_init(struct device *dev); static int imx_gpio_6_init(struct device *dev);
static const struct imx_gpio_config imx_gpio_6_config = { static const struct imx_gpio_config imx_gpio_6_config = {
.base = (GPIO_Type *)CONFIG_GPIO_IMX_PORT_6_BASE_ADDRESS, .base = (GPIO_Type *)DT_GPIO_IMX_PORT_6_BASE_ADDRESS,
}; };
static struct imx_gpio_data imx_gpio_6_data; static struct imx_gpio_data imx_gpio_6_data;
DEVICE_AND_API_INIT(imx_gpio_6, CONFIG_GPIO_IMX_PORT_6_NAME, DEVICE_AND_API_INIT(imx_gpio_6, DT_GPIO_IMX_PORT_6_NAME,
imx_gpio_6_init, imx_gpio_6_init,
&imx_gpio_6_data, &imx_gpio_6_config, &imx_gpio_6_data, &imx_gpio_6_config,
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
@ -361,17 +361,17 @@ DEVICE_AND_API_INIT(imx_gpio_6, CONFIG_GPIO_IMX_PORT_6_NAME,
static int imx_gpio_6_init(struct device *dev) static int imx_gpio_6_init(struct device *dev)
{ {
IRQ_CONNECT(CONFIG_GPIO_IMX_PORT_6_IRQ_0, IRQ_CONNECT(DT_GPIO_IMX_PORT_6_IRQ_0,
CONFIG_GPIO_IMX_PORT_6_IRQ_0_PRI, DT_GPIO_IMX_PORT_6_IRQ_0_PRI,
imx_gpio_port_isr, DEVICE_GET(imx_gpio_6), 0); imx_gpio_port_isr, DEVICE_GET(imx_gpio_6), 0);
irq_enable(CONFIG_GPIO_IMX_PORT_6_IRQ_0); irq_enable(DT_GPIO_IMX_PORT_6_IRQ_0);
IRQ_CONNECT(CONFIG_GPIO_IMX_PORT_6_IRQ_1, IRQ_CONNECT(DT_GPIO_IMX_PORT_6_IRQ_1,
CONFIG_GPIO_IMX_PORT_6_IRQ_1_PRI, DT_GPIO_IMX_PORT_6_IRQ_1_PRI,
imx_gpio_port_isr, DEVICE_GET(imx_gpio_6), 0); imx_gpio_port_isr, DEVICE_GET(imx_gpio_6), 0);
irq_enable(CONFIG_GPIO_IMX_PORT_6_IRQ_1); irq_enable(DT_GPIO_IMX_PORT_6_IRQ_1);
return 0; return 0;
} }
@ -381,12 +381,12 @@ static int imx_gpio_6_init(struct device *dev)
static int imx_gpio_7_init(struct device *dev); static int imx_gpio_7_init(struct device *dev);
static const struct imx_gpio_config imx_gpio_7_config = { static const struct imx_gpio_config imx_gpio_7_config = {
.base = (GPIO_Type *)CONFIG_GPIO_IMX_PORT_7_BASE_ADDRESS, .base = (GPIO_Type *)DT_GPIO_IMX_PORT_7_BASE_ADDRESS,
}; };
static struct imx_gpio_data imx_gpio_7_data; static struct imx_gpio_data imx_gpio_7_data;
DEVICE_AND_API_INIT(imx_gpio_7, CONFIG_GPIO_IMX_PORT_7_NAME, DEVICE_AND_API_INIT(imx_gpio_7, DT_GPIO_IMX_PORT_7_NAME,
imx_gpio_7_init, imx_gpio_7_init,
&imx_gpio_7_data, &imx_gpio_7_config, &imx_gpio_7_data, &imx_gpio_7_config,
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
@ -394,17 +394,17 @@ DEVICE_AND_API_INIT(imx_gpio_7, CONFIG_GPIO_IMX_PORT_7_NAME,
static int imx_gpio_7_init(struct device *dev) static int imx_gpio_7_init(struct device *dev)
{ {
IRQ_CONNECT(CONFIG_GPIO_IMX_PORT_7_IRQ_0, IRQ_CONNECT(DT_GPIO_IMX_PORT_7_IRQ_0,
CONFIG_GPIO_IMX_PORT_7_IRQ_0_PRI, DT_GPIO_IMX_PORT_7_IRQ_0_PRI,
imx_gpio_port_isr, DEVICE_GET(imx_gpio_7), 0); imx_gpio_port_isr, DEVICE_GET(imx_gpio_7), 0);
irq_enable(CONFIG_GPIO_IMX_PORT_7_IRQ_0); irq_enable(DT_GPIO_IMX_PORT_7_IRQ_0);
IRQ_CONNECT(CONFIG_GPIO_IMX_PORT_7_IRQ_1, IRQ_CONNECT(DT_GPIO_IMX_PORT_7_IRQ_1,
CONFIG_GPIO_IMX_PORT_7_IRQ_1_PRI, DT_GPIO_IMX_PORT_7_IRQ_1_PRI,
imx_gpio_port_isr, DEVICE_GET(imx_gpio_7), 0); imx_gpio_port_isr, DEVICE_GET(imx_gpio_7), 0);
irq_enable(CONFIG_GPIO_IMX_PORT_7_IRQ_1); irq_enable(DT_GPIO_IMX_PORT_7_IRQ_1);
return 0; return 0;
} }

16
drivers/gpio/gpio_intel_apl.c
View file

@ -430,22 +430,22 @@ static const struct gpio_intel_apl_config gpio_intel_apl_cfg = {
.islands = { .islands = {
{ {
/* North island */ /* North island */
.reg_base = CONFIG_APL_GPIO_BASE_ADDRESS_0, .reg_base = DT_APL_GPIO_BASE_ADDRESS_0,
.num_pins = 78, .num_pins = 78,
}, },
{ {
/* Northwest island */ /* Northwest island */
.reg_base = CONFIG_APL_GPIO_BASE_ADDRESS_1, .reg_base = DT_APL_GPIO_BASE_ADDRESS_1,
.num_pins = 77, .num_pins = 77,
}, },
{ {
/* West island */ /* West island */
.reg_base = CONFIG_APL_GPIO_BASE_ADDRESS_2, .reg_base = DT_APL_GPIO_BASE_ADDRESS_2,
.num_pins = 47, .num_pins = 47,
}, },
{ {
/* Southwest island */ /* Southwest island */
.reg_base = CONFIG_APL_GPIO_BASE_ADDRESS_3, .reg_base = DT_APL_GPIO_BASE_ADDRESS_3,
.num_pins = 43, .num_pins = 43,
}, },
}, },
@ -453,7 +453,7 @@ static const struct gpio_intel_apl_config gpio_intel_apl_cfg = {
static struct gpio_intel_apl_data gpio_intel_apl_data; static struct gpio_intel_apl_data gpio_intel_apl_data;
DEVICE_AND_API_INIT(gpio_intel_apl, CONFIG_APL_GPIO_LABEL, DEVICE_AND_API_INIT(gpio_intel_apl, DT_APL_GPIO_LABEL,
gpio_intel_apl_init, gpio_intel_apl_init,
&gpio_intel_apl_data, &gpio_intel_apl_cfg, &gpio_intel_apl_data, &gpio_intel_apl_cfg,
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
@ -461,9 +461,9 @@ DEVICE_AND_API_INIT(gpio_intel_apl, CONFIG_APL_GPIO_LABEL,
static void gpio_intel_apl_irq_config(struct device *dev) static void gpio_intel_apl_irq_config(struct device *dev)
{ {
IRQ_CONNECT(CONFIG_APL_GPIO_IRQ, CONFIG_APL_GPIO_IRQ_PRIORITY, IRQ_CONNECT(DT_APL_GPIO_IRQ, DT_APL_GPIO_IRQ_PRIORITY,
gpio_intel_apl_isr, DEVICE_GET(gpio_intel_apl), gpio_intel_apl_isr, DEVICE_GET(gpio_intel_apl),
CONFIG_APL_GPIO_IRQ_SENSE); DT_APL_GPIO_IRQ_SENSE);
irq_enable(CONFIG_APL_GPIO_IRQ); irq_enable(DT_APL_GPIO_IRQ);
} }

24
drivers/gpio/gpio_mcux_igpio.c
View file

@ -174,12 +174,12 @@ static const struct gpio_driver_api mcux_igpio_driver_api = {
static int mcux_igpio_1_init(struct device *dev); static int mcux_igpio_1_init(struct device *dev);
static const struct mcux_igpio_config mcux_igpio_1_config = { static const struct mcux_igpio_config mcux_igpio_1_config = {
.base = (GPIO_Type *)CONFIG_MCUX_IGPIO_1_BASE_ADDRESS, .base = (GPIO_Type *)DT_MCUX_IGPIO_1_BASE_ADDRESS,
}; };
static struct mcux_igpio_data mcux_igpio_1_data; static struct mcux_igpio_data mcux_igpio_1_data;
DEVICE_AND_API_INIT(mcux_igpio_1, CONFIG_MCUX_IGPIO_1_NAME, DEVICE_AND_API_INIT(mcux_igpio_1, DT_MCUX_IGPIO_1_NAME,
mcux_igpio_1_init, mcux_igpio_1_init,
&mcux_igpio_1_data, &mcux_igpio_1_config, &mcux_igpio_1_data, &mcux_igpio_1_config,
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
@ -187,15 +187,15 @@ DEVICE_AND_API_INIT(mcux_igpio_1, CONFIG_MCUX_IGPIO_1_NAME,
static int mcux_igpio_1_init(struct device *dev) static int mcux_igpio_1_init(struct device *dev)
{ {
IRQ_CONNECT(CONFIG_MCUX_IGPIO_1_IRQ_0, CONFIG_MCUX_IGPIO_1_IRQ_0_PRI, IRQ_CONNECT(DT_MCUX_IGPIO_1_IRQ_0, DT_MCUX_IGPIO_1_IRQ_0_PRI,
mcux_igpio_port_isr, DEVICE_GET(mcux_igpio_1), 0); mcux_igpio_port_isr, DEVICE_GET(mcux_igpio_1), 0);
irq_enable(CONFIG_MCUX_IGPIO_1_IRQ_0); irq_enable(DT_MCUX_IGPIO_1_IRQ_0);
IRQ_CONNECT(CONFIG_MCUX_IGPIO_1_IRQ_1, CONFIG_MCUX_IGPIO_1_IRQ_1_PRI, IRQ_CONNECT(DT_MCUX_IGPIO_1_IRQ_1, DT_MCUX_IGPIO_1_IRQ_1_PRI,
mcux_igpio_port_isr, DEVICE_GET(mcux_igpio_1), 0); mcux_igpio_port_isr, DEVICE_GET(mcux_igpio_1), 0);
irq_enable(CONFIG_MCUX_IGPIO_1_IRQ_1); irq_enable(DT_MCUX_IGPIO_1_IRQ_1);
return 0; return 0;
} }
@ -298,12 +298,12 @@ static int mcux_igpio_4_init(struct device *dev)
static int mcux_igpio_5_init(struct device *dev); static int mcux_igpio_5_init(struct device *dev);
static const struct mcux_igpio_config mcux_igpio_5_config = { static const struct mcux_igpio_config mcux_igpio_5_config = {
.base = (GPIO_Type *)CONFIG_MCUX_IGPIO_5_BASE_ADDRESS, .base = (GPIO_Type *)DT_MCUX_IGPIO_5_BASE_ADDRESS,
}; };
static struct mcux_igpio_data mcux_igpio_5_data; static struct mcux_igpio_data mcux_igpio_5_data;
DEVICE_AND_API_INIT(mcux_igpio_5, CONFIG_MCUX_IGPIO_5_NAME, DEVICE_AND_API_INIT(mcux_igpio_5, DT_MCUX_IGPIO_5_NAME,
mcux_igpio_5_init, mcux_igpio_5_init,
&mcux_igpio_5_data, &mcux_igpio_5_config, &mcux_igpio_5_data, &mcux_igpio_5_config,
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
@ -311,15 +311,15 @@ DEVICE_AND_API_INIT(mcux_igpio_5, CONFIG_MCUX_IGPIO_5_NAME,
static int mcux_igpio_5_init(struct device *dev) static int mcux_igpio_5_init(struct device *dev)
{ {
IRQ_CONNECT(CONFIG_MCUX_IGPIO_5_IRQ_0, CONFIG_MCUX_IGPIO_5_IRQ_0_PRI, IRQ_CONNECT(DT_MCUX_IGPIO_5_IRQ_0, DT_MCUX_IGPIO_5_IRQ_0_PRI,
mcux_igpio_port_isr, DEVICE_GET(mcux_igpio_5), 0); mcux_igpio_port_isr, DEVICE_GET(mcux_igpio_5), 0);
irq_enable(CONFIG_MCUX_IGPIO_5_IRQ_0); irq_enable(DT_MCUX_IGPIO_5_IRQ_0);
IRQ_CONNECT(CONFIG_MCUX_IGPIO_5_IRQ_1, CONFIG_MCUX_IGPIO_5_IRQ_1_PRI, IRQ_CONNECT(DT_MCUX_IGPIO_5_IRQ_1, DT_MCUX_IGPIO_5_IRQ_1_PRI,
mcux_igpio_port_isr, DEVICE_GET(mcux_igpio_5), 0); mcux_igpio_port_isr, DEVICE_GET(mcux_igpio_5), 0);
irq_enable(CONFIG_MCUX_IGPIO_5_IRQ_1); irq_enable(DT_MCUX_IGPIO_5_IRQ_1);
return 0; return 0;
} }

6
drivers/gpio/gpio_nrfx.c
View file

@ -419,10 +419,10 @@ static int gpio_nrfx_init(struct device *port)
if (!gpio_initialized) { if (!gpio_initialized) {
gpio_initialized = true; gpio_initialized = true;
IRQ_CONNECT(CONFIG_GPIOTE_IRQ, CONFIG_GPIOTE_IRQ_PRI, IRQ_CONNECT(DT_GPIOTE_IRQ, DT_GPIOTE_IRQ_PRI,
gpiote_event_handler, NULL, 0); gpiote_event_handler, NULL, 0);
irq_enable(CONFIG_GPIOTE_IRQ); irq_enable(DT_GPIOTE_IRQ);
nrf_gpiote_int_enable(NRF_GPIOTE_INT_PORT_MASK); nrf_gpiote_int_enable(NRF_GPIOTE_INT_PORT_MASK);
} }
@ -442,7 +442,7 @@ static int gpio_nrfx_init(struct device *port)
static struct gpio_nrfx_data gpio_nrfx_p##id##_data; \ static struct gpio_nrfx_data gpio_nrfx_p##id##_data; \
\ \
DEVICE_AND_API_INIT(gpio_nrfx_p##id, \ DEVICE_AND_API_INIT(gpio_nrfx_p##id, \
CONFIG_GPIO_P##id##_DEV_NAME, \ DT_GPIO_P##id##_DEV_NAME, \
gpio_nrfx_init, \ gpio_nrfx_init, \
&gpio_nrfx_p##id##_data, \ &gpio_nrfx_p##id##_data, \
&gpio_nrfx_p##id##_cfg, \ &gpio_nrfx_p##id##_cfg, \

18
drivers/gpio/gpio_qmsi.c
View file

@ -117,7 +117,7 @@ static int gpio_qmsi_device_ctrl(struct device *port, u32_t ctrl_command,
} }
#endif #endif
DEVICE_DEFINE(gpio_0, CONFIG_GPIO_QMSI_0_NAME, &gpio_qmsi_init, DEVICE_DEFINE(gpio_0, DT_GPIO_QMSI_0_NAME, &gpio_qmsi_init,
gpio_qmsi_device_ctrl, &gpio_0_runtime, &gpio_0_config, gpio_qmsi_device_ctrl, &gpio_0_runtime, &gpio_0_config,
POST_KERNEL, CONFIG_GPIO_QMSI_INIT_PRIORITY, NULL); POST_KERNEL, CONFIG_GPIO_QMSI_INIT_PRIORITY, NULL);
@ -154,7 +154,7 @@ static int gpio_aon_device_ctrl(struct device *port, u32_t ctrl_command,
} }
#endif #endif
DEVICE_DEFINE(gpio_aon, CONFIG_GPIO_QMSI_1_NAME, &gpio_qmsi_init, DEVICE_DEFINE(gpio_aon, DT_GPIO_QMSI_1_NAME, &gpio_qmsi_init,
gpio_aon_device_ctrl, &gpio_aon_runtime, &gpio_aon_config, gpio_aon_device_ctrl, &gpio_aon_runtime, &gpio_aon_config,
POST_KERNEL, CONFIG_GPIO_QMSI_INIT_PRIORITY, NULL); POST_KERNEL, CONFIG_GPIO_QMSI_INIT_PRIORITY, NULL);
@ -378,18 +378,18 @@ static int gpio_qmsi_init(struct device *port)
CLK_PERIPH_GPIO_INTERRUPT | CLK_PERIPH_GPIO_INTERRUPT |
CLK_PERIPH_GPIO_DB | CLK_PERIPH_GPIO_DB |
CLK_PERIPH_CLK); CLK_PERIPH_CLK);
IRQ_CONNECT(CONFIG_GPIO_QMSI_0_IRQ, IRQ_CONNECT(DT_GPIO_QMSI_0_IRQ,
CONFIG_GPIO_QMSI_0_IRQ_PRI, qm_gpio_0_isr, 0, CONFIG_GPIO_QMSI_0_IRQ_PRI, qm_gpio_0_isr, 0,
CONFIG_GPIO_QMSI_0_IRQ_FLAGS); DT_GPIO_QMSI_0_IRQ_FLAGS);
irq_enable(CONFIG_GPIO_QMSI_0_IRQ); irq_enable(DT_GPIO_QMSI_0_IRQ);
QM_IR_UNMASK_INTERRUPTS(QM_INTERRUPT_ROUTER->gpio_0_int_mask); QM_IR_UNMASK_INTERRUPTS(QM_INTERRUPT_ROUTER->gpio_0_int_mask);
break; break;
#ifdef CONFIG_GPIO_QMSI_1 #ifdef CONFIG_GPIO_QMSI_1
case QM_AON_GPIO_0: case QM_AON_GPIO_0:
IRQ_CONNECT(CONFIG_GPIO_QMSI_1_IRQ, IRQ_CONNECT(DT_GPIO_QMSI_1_IRQ,
CONFIG_GPIO_QMSI_1_IRQ_PRI, qm_aon_gpio_0_isr, DT_GPIO_QMSI_1_IRQ_PRI, qm_aon_gpio_0_isr,
0, CONFIG_GPIO_QMSI_1_IRQ_FLAGS); 0, DT_GPIO_QMSI_1_IRQ_FLAGS);
irq_enable(CONFIG_GPIO_QMSI_1_IRQ); irq_enable(DT_GPIO_QMSI_1_IRQ);
QM_IR_UNMASK_INTERRUPTS( QM_IR_UNMASK_INTERRUPTS(
QM_INTERRUPT_ROUTER->aon_gpio_0_int_mask); QM_INTERRUPT_ROUTER->aon_gpio_0_int_mask);
break; break;

12
drivers/gpio/gpio_qmsi_ss.c
View file

@ -112,7 +112,7 @@ static const struct ss_gpio_qmsi_config ss_gpio_0_config = {
static struct ss_gpio_qmsi_runtime ss_gpio_0_runtime; static struct ss_gpio_qmsi_runtime ss_gpio_0_runtime;
DEVICE_DEFINE(ss_gpio_0, CONFIG_GPIO_QMSI_SS_0_NAME, &ss_gpio_qmsi_init, DEVICE_DEFINE(ss_gpio_0, DT_GPIO_QMSI_SS_0_NAME, &ss_gpio_qmsi_init,
ss_gpio_qmsi_device_ctrl, &ss_gpio_0_runtime, &ss_gpio_0_config, ss_gpio_qmsi_device_ctrl, &ss_gpio_0_runtime, &ss_gpio_0_config,
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, NULL); POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, NULL);
@ -126,7 +126,7 @@ static const struct ss_gpio_qmsi_config ss_gpio_1_config = {
static struct ss_gpio_qmsi_runtime gpio_1_runtime; static struct ss_gpio_qmsi_runtime gpio_1_runtime;
DEVICE_DEFINE(ss_gpio_1, CONFIG_GPIO_QMSI_SS_1_NAME, &ss_gpio_qmsi_init, DEVICE_DEFINE(ss_gpio_1, DT_GPIO_QMSI_SS_1_NAME, &ss_gpio_qmsi_init,
ss_gpio_qmsi_device_ctrl, &gpio_1_runtime, &ss_gpio_1_config, ss_gpio_qmsi_device_ctrl, &gpio_1_runtime, &ss_gpio_1_config,
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, NULL); POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, NULL);
@ -374,8 +374,8 @@ static int ss_gpio_qmsi_init(struct device *port)
switch (gpio_config->gpio) { switch (gpio_config->gpio) {
#ifdef CONFIG_GPIO_QMSI_SS_0 #ifdef CONFIG_GPIO_QMSI_SS_0
case QM_SS_GPIO_0: case QM_SS_GPIO_0:
IRQ_CONNECT(CONFIG_GPIO_QMSI_SS_0_IRQ, IRQ_CONNECT(DT_GPIO_QMSI_SS_0_IRQ,
CONFIG_GPIO_QMSI_SS_0_IRQ_PRI, ss_gpio_isr, DT_GPIO_QMSI_SS_0_IRQ_PRI, ss_gpio_isr,
DEVICE_GET(ss_gpio_0), 0); DEVICE_GET(ss_gpio_0), 0);
irq_enable(IRQ_GPIO0_INTR); irq_enable(IRQ_GPIO0_INTR);
@ -388,8 +388,8 @@ static int ss_gpio_qmsi_init(struct device *port)
#endif /* CONFIG_GPIO_QMSI_SS_0 */ #endif /* CONFIG_GPIO_QMSI_SS_0 */
#ifdef CONFIG_GPIO_QMSI_SS_1 #ifdef CONFIG_GPIO_QMSI_SS_1
case QM_SS_GPIO_1: case QM_SS_GPIO_1:
IRQ_CONNECT(CONFIG_GPIO_QMSI_SS_1_IRQ, IRQ_CONNECT(DT_GPIO_QMSI_SS_1_IRQ,
CONFIG_GPIO_QMSI_SS_1_IRQ_PRI, ss_gpio_isr, DT_GPIO_QMSI_SS_1_IRQ_PRI, ss_gpio_isr,
DEVICE_GET(ss_gpio_1), 0); DEVICE_GET(ss_gpio_1), 0);
irq_enable(IRQ_GPIO1_INTR); irq_enable(IRQ_GPIO1_INTR);

70
drivers/gpio/gpio_sam.c
View file

@ -275,126 +275,126 @@ int gpio_sam_init(struct device *dev)
} }
/* PORT A */ /* PORT A */
#ifdef CONFIG_GPIO_SAM_PORTA_BASE_ADDRESS #ifdef DT_GPIO_SAM_PORTA_BASE_ADDRESS
static void port_a_sam_config_func(struct device *dev); static void port_a_sam_config_func(struct device *dev);
static const struct gpio_sam_config port_a_sam_config = { static const struct gpio_sam_config port_a_sam_config = {
.regs = (Pio *)CONFIG_GPIO_SAM_PORTA_BASE_ADDRESS, .regs = (Pio *)DT_GPIO_SAM_PORTA_BASE_ADDRESS,
.periph_id = CONFIG_GPIO_SAM_PORTA_PERIPHERAL_ID, .periph_id = DT_GPIO_SAM_PORTA_PERIPHERAL_ID,
.config_func = port_a_sam_config_func, .config_func = port_a_sam_config_func,
}; };
static struct gpio_sam_runtime port_a_sam_runtime; static struct gpio_sam_runtime port_a_sam_runtime;
DEVICE_AND_API_INIT(port_a_sam, CONFIG_GPIO_SAM_PORTA_LABEL, gpio_sam_init, DEVICE_AND_API_INIT(port_a_sam, DT_GPIO_SAM_PORTA_LABEL, gpio_sam_init,
&port_a_sam_runtime, &port_a_sam_config, POST_KERNEL, &port_a_sam_runtime, &port_a_sam_config, POST_KERNEL,
CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &gpio_sam_api); CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &gpio_sam_api);
static void port_a_sam_config_func(struct device *dev) static void port_a_sam_config_func(struct device *dev)
{ {
IRQ_CONNECT(CONFIG_GPIO_SAM_PORTA_IRQ, CONFIG_GPIO_SAM_PORTA_IRQ_PRIO, IRQ_CONNECT(DT_GPIO_SAM_PORTA_IRQ, DT_GPIO_SAM_PORTA_IRQ_PRIO,
gpio_sam_isr, DEVICE_GET(port_a_sam), 0); gpio_sam_isr, DEVICE_GET(port_a_sam), 0);
irq_enable(CONFIG_GPIO_SAM_PORTA_IRQ); irq_enable(DT_GPIO_SAM_PORTA_IRQ);
} }
#endif /* CONFIG_GPIO_SAM_PORTA_BASE_ADDRESS */ #endif /* DT_GPIO_SAM_PORTA_BASE_ADDRESS */
/* PORT B */ /* PORT B */
#ifdef CONFIG_GPIO_SAM_PORTB_BASE_ADDRESS #ifdef DT_GPIO_SAM_PORTB_BASE_ADDRESS
static void port_b_sam_config_func(struct device *dev); static void port_b_sam_config_func(struct device *dev);
static const struct gpio_sam_config port_b_sam_config = { static const struct gpio_sam_config port_b_sam_config = {
.regs = (Pio *)CONFIG_GPIO_SAM_PORTB_BASE_ADDRESS, .regs = (Pio *)DT_GPIO_SAM_PORTB_BASE_ADDRESS,
.periph_id = CONFIG_GPIO_SAM_PORTB_PERIPHERAL_ID, .periph_id = DT_GPIO_SAM_PORTB_PERIPHERAL_ID,
.config_func = port_b_sam_config_func, .config_func = port_b_sam_config_func,
}; };
static struct gpio_sam_runtime port_b_sam_runtime; static struct gpio_sam_runtime port_b_sam_runtime;
DEVICE_AND_API_INIT(port_b_sam, CONFIG_GPIO_SAM_PORTB_LABEL, gpio_sam_init, DEVICE_AND_API_INIT(port_b_sam, DT_GPIO_SAM_PORTB_LABEL, gpio_sam_init,
&port_b_sam_runtime, &port_b_sam_config, POST_KERNEL, &port_b_sam_runtime, &port_b_sam_config, POST_KERNEL,
CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &gpio_sam_api); CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &gpio_sam_api);
static void port_b_sam_config_func(struct device *dev) static void port_b_sam_config_func(struct device *dev)
{ {
IRQ_CONNECT(CONFIG_GPIO_SAM_PORTB_IRQ, CONFIG_GPIO_SAM_PORTB_IRQ_PRIO, IRQ_CONNECT(DT_GPIO_SAM_PORTB_IRQ, DT_GPIO_SAM_PORTB_IRQ_PRIO,
gpio_sam_isr, DEVICE_GET(port_b_sam), 0); gpio_sam_isr, DEVICE_GET(port_b_sam), 0);
irq_enable(CONFIG_GPIO_SAM_PORTB_IRQ); irq_enable(DT_GPIO_SAM_PORTB_IRQ);
} }
#endif /* CONFIG_GPIO_SAM_PORTB_BASE_ADDRESS */ #endif /* DT_GPIO_SAM_PORTB_BASE_ADDRESS */
/* PORT C */ /* PORT C */
#ifdef CONFIG_GPIO_SAM_PORTC_BASE_ADDRESS #ifdef DT_GPIO_SAM_PORTC_BASE_ADDRESS
static void port_c_sam_config_func(struct device *dev); static void port_c_sam_config_func(struct device *dev);
static const struct gpio_sam_config port_c_sam_config = { static const struct gpio_sam_config port_c_sam_config = {
.regs = (Pio *)CONFIG_GPIO_SAM_PORTC_BASE_ADDRESS, .regs = (Pio *)DT_GPIO_SAM_PORTC_BASE_ADDRESS,
.periph_id = CONFIG_GPIO_SAM_PORTC_PERIPHERAL_ID, .periph_id = DT_GPIO_SAM_PORTC_PERIPHERAL_ID,
.config_func = port_c_sam_config_func, .config_func = port_c_sam_config_func,
}; };
static struct gpio_sam_runtime port_c_sam_runtime; static struct gpio_sam_runtime port_c_sam_runtime;
DEVICE_AND_API_INIT(port_c_sam, CONFIG_GPIO_SAM_PORTC_LABEL, gpio_sam_init, DEVICE_AND_API_INIT(port_c_sam, DT_GPIO_SAM_PORTC_LABEL, gpio_sam_init,
&port_c_sam_runtime, &port_c_sam_config, POST_KERNEL, &port_c_sam_runtime, &port_c_sam_config, POST_KERNEL,
CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &gpio_sam_api); CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &gpio_sam_api);
static void port_c_sam_config_func(struct device *dev) static void port_c_sam_config_func(struct device *dev)
{ {
IRQ_CONNECT(CONFIG_GPIO_SAM_PORTC_IRQ, CONFIG_GPIO_SAM_PORTC_IRQ_PRIO, IRQ_CONNECT(DT_GPIO_SAM_PORTC_IRQ, DT_GPIO_SAM_PORTC_IRQ_PRIO,
gpio_sam_isr, DEVICE_GET(port_c_sam), 0); gpio_sam_isr, DEVICE_GET(port_c_sam), 0);
irq_enable(CONFIG_GPIO_SAM_PORTC_IRQ); irq_enable(DT_GPIO_SAM_PORTC_IRQ);
} }
#endif /* CONFIG_GPIO_SAM_PORTC_BASE_ADDRESS */ #endif /* DT_GPIO_SAM_PORTC_BASE_ADDRESS */
/* PORT D */ /* PORT D */
#ifdef CONFIG_GPIO_SAM_PORTD_BASE_ADDRESS #ifdef DT_GPIO_SAM_PORTD_BASE_ADDRESS
static void port_d_sam_config_func(struct device *dev); static void port_d_sam_config_func(struct device *dev);
static const struct gpio_sam_config port_d_sam_config = { static const struct gpio_sam_config port_d_sam_config = {
.regs = (Pio *)CONFIG_GPIO_SAM_PORTD_BASE_ADDRESS, .regs = (Pio *)DT_GPIO_SAM_PORTD_BASE_ADDRESS,
.periph_id = CONFIG_GPIO_SAM_PORTD_PERIPHERAL_ID, .periph_id = DT_GPIO_SAM_PORTD_PERIPHERAL_ID,
.config_func = port_d_sam_config_func, .config_func = port_d_sam_config_func,
}; };
static struct gpio_sam_runtime port_d_sam_runtime; static struct gpio_sam_runtime port_d_sam_runtime;
DEVICE_AND_API_INIT(port_d_sam, CONFIG_GPIO_SAM_PORTD_LABEL, gpio_sam_init, DEVICE_AND_API_INIT(port_d_sam, DT_GPIO_SAM_PORTD_LABEL, gpio_sam_init,
&port_d_sam_runtime, &port_d_sam_config, POST_KERNEL, &port_d_sam_runtime, &port_d_sam_config, POST_KERNEL,
CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &gpio_sam_api); CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &gpio_sam_api);
static void port_d_sam_config_func(struct device *dev) static void port_d_sam_config_func(struct device *dev)
{ {
IRQ_CONNECT(CONFIG_GPIO_SAM_PORTD_IRQ, CONFIG_GPIO_SAM_PORTD_IRQ_PRIO, IRQ_CONNECT(DT_GPIO_SAM_PORTD_IRQ, DT_GPIO_SAM_PORTD_IRQ_PRIO,
gpio_sam_isr, DEVICE_GET(port_d_sam), 0); gpio_sam_isr, DEVICE_GET(port_d_sam), 0);
irq_enable(CONFIG_GPIO_SAM_PORTD_IRQ); irq_enable(DT_GPIO_SAM_PORTD_IRQ);
} }
#endif /* CONFIG_GPIO_SAM_PORTD_BASE_ADDRESS */ #endif /* DT_GPIO_SAM_PORTD_BASE_ADDRESS */
/* PORT E */ /* PORT E */
#ifdef CONFIG_GPIO_SAM_PORTE_BASE_ADDRESS #ifdef DT_GPIO_SAM_PORTE_BASE_ADDRESS
static void port_e_sam_config_func(struct device *dev); static void port_e_sam_config_func(struct device *dev);
static const struct gpio_sam_config port_e_sam_config = { static const struct gpio_sam_config port_e_sam_config = {
.regs = (Pio *)CONFIG_GPIO_SAM_PORTE_BASE_ADDRESS, .regs = (Pio *)DT_GPIO_SAM_PORTE_BASE_ADDRESS,
.periph_id = CONFIG_GPIO_SAM_PORTE_PERIPHERAL_ID, .periph_id = DT_GPIO_SAM_PORTE_PERIPHERAL_ID,
.config_func = port_e_sam_config_func, .config_func = port_e_sam_config_func,
}; };
static struct gpio_sam_runtime port_e_sam_runtime; static struct gpio_sam_runtime port_e_sam_runtime;
DEVICE_AND_API_INIT(port_e_sam, CONFIG_GPIO_SAM_PORTE_LABEL, gpio_sam_init, DEVICE_AND_API_INIT(port_e_sam, DT_GPIO_SAM_PORTE_LABEL, gpio_sam_init,
&port_e_sam_runtime, &port_e_sam_config, POST_KERNEL, &port_e_sam_runtime, &port_e_sam_config, POST_KERNEL,
CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &gpio_sam_api); CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &gpio_sam_api);
static void port_e_sam_config_func(struct device *dev) static void port_e_sam_config_func(struct device *dev)
{ {
IRQ_CONNECT(CONFIG_GPIO_SAM_PORTE_IRQ, CONFIG_GPIO_SAM_PORTE_IRQ_PRIO, IRQ_CONNECT(DT_GPIO_SAM_PORTE_IRQ, DT_GPIO_SAM_PORTE_IRQ_PRIO,
gpio_sam_isr, DEVICE_GET(port_e_sam), 0); gpio_sam_isr, DEVICE_GET(port_e_sam), 0);
irq_enable(CONFIG_GPIO_SAM_PORTE_IRQ); irq_enable(DT_GPIO_SAM_PORTE_IRQ);
} }
#endif /* CONFIG_GPIO_SAM_PORTE_BASE_ADDRESS */ #endif /* DT_GPIO_SAM_PORTE_BASE_ADDRESS */

12
drivers/gpio/gpio_sam0.c
View file

@ -122,25 +122,25 @@ static const struct gpio_driver_api gpio_sam0_api = {
static int gpio_sam0_init(struct device *dev) { return 0; } static int gpio_sam0_init(struct device *dev) { return 0; }
/* Port A */ /* Port A */
#ifdef CONFIG_GPIO_SAM0_PORTA_BASE_ADDRESS #ifdef DT_GPIO_SAM0_PORTA_BASE_ADDRESS
static const struct gpio_sam0_config gpio_sam0_config_0 = { static const struct gpio_sam0_config gpio_sam0_config_0 = {
.regs = (PortGroup *)CONFIG_GPIO_SAM0_PORTA_BASE_ADDRESS, .regs = (PortGroup *)DT_GPIO_SAM0_PORTA_BASE_ADDRESS,
}; };
DEVICE_AND_API_INIT(gpio_sam0_0, CONFIG_GPIO_SAM0_PORTA_LABEL, gpio_sam0_init, DEVICE_AND_API_INIT(gpio_sam0_0, DT_GPIO_SAM0_PORTA_LABEL, gpio_sam0_init,
NULL, &gpio_sam0_config_0, POST_KERNEL, NULL, &gpio_sam0_config_0, POST_KERNEL,
CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &gpio_sam0_api); CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &gpio_sam0_api);
#endif #endif
/* Port B */ /* Port B */
#ifdef CONFIG_GPIO_SAM0_PORTB_BASE_ADDRESS #ifdef DT_GPIO_SAM0_PORTB_BASE_ADDRESS
static const struct gpio_sam0_config gpio_sam0_config_1 = { static const struct gpio_sam0_config gpio_sam0_config_1 = {
.regs = (PortGroup *)CONFIG_GPIO_SAM0_PORTB_BASE_ADDRESS, .regs = (PortGroup *)DT_GPIO_SAM0_PORTB_BASE_ADDRESS,
}; };
DEVICE_AND_API_INIT(gpio_sam0_1, CONFIG_GPIO_SAM0_PORTB_LABEL, gpio_sam0_init, DEVICE_AND_API_INIT(gpio_sam0_1, DT_GPIO_SAM0_PORTB_LABEL, gpio_sam0_init,
NULL, &gpio_sam0_config_1, POST_KERNEL, NULL, &gpio_sam0_config_1, POST_KERNEL,
CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &gpio_sam0_api); CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &gpio_sam0_api);
#endif #endif

132
drivers/gpio/gpio_sifive.c
View file

@ -357,8 +357,8 @@ static int gpio_sifive_init(struct device *dev)
static void gpio_sifive_cfg_0(void); static void gpio_sifive_cfg_0(void);
static const struct gpio_sifive_config gpio_sifive_config0 = { static const struct gpio_sifive_config gpio_sifive_config0 = {
.gpio_base_addr = CONFIG_SIFIVE_GPIO_0_BASE_ADDR, .gpio_base_addr = DT_SIFIVE_GPIO_0_BASE_ADDR,
.gpio_irq_base = RISCV_MAX_GENERIC_IRQ + CONFIG_SIFIVE_GPIO_0_IRQ_0, .gpio_irq_base = RISCV_MAX_GENERIC_IRQ + DT_SIFIVE_GPIO_0_IRQ_0,
.gpio_cfg_func = gpio_sifive_cfg_0, .gpio_cfg_func = gpio_sifive_cfg_0,
}; };
@ -372,225 +372,225 @@ DEVICE_AND_API_INIT(gpio_sifive_0, CONFIG_GPIO_SIFIVE_GPIO_NAME,
static void gpio_sifive_cfg_0(void) static void gpio_sifive_cfg_0(void)
{ {
#ifdef CONFIG_SIFIVE_GPIO_0_IRQ_0 #ifdef DT_SIFIVE_GPIO_0_IRQ_0
IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + CONFIG_SIFIVE_GPIO_0_IRQ_0, IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + DT_SIFIVE_GPIO_0_IRQ_0,
CONFIG_GPIO_SIFIVE_0_PRIORITY, CONFIG_GPIO_SIFIVE_0_PRIORITY,
gpio_sifive_irq_handler, gpio_sifive_irq_handler,
DEVICE_GET(gpio_sifive_0), DEVICE_GET(gpio_sifive_0),
0); 0);
#endif #endif
#ifdef CONFIG_SIFIVE_GPIO_0_IRQ_1 #ifdef DT_SIFIVE_GPIO_0_IRQ_1
IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + CONFIG_SIFIVE_GPIO_0_IRQ_1, IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + DT_SIFIVE_GPIO_0_IRQ_1,
CONFIG_GPIO_SIFIVE_1_PRIORITY, CONFIG_GPIO_SIFIVE_1_PRIORITY,
gpio_sifive_irq_handler, gpio_sifive_irq_handler,
DEVICE_GET(gpio_sifive_0), DEVICE_GET(gpio_sifive_0),
0); 0);
#endif #endif
#ifdef CONFIG_SIFIVE_GPIO_0_IRQ_2 #ifdef DT_SIFIVE_GPIO_0_IRQ_2
IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + CONFIG_SIFIVE_GPIO_0_IRQ_2, IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + DT_SIFIVE_GPIO_0_IRQ_2,
CONFIG_GPIO_SIFIVE_2_PRIORITY, CONFIG_GPIO_SIFIVE_2_PRIORITY,
gpio_sifive_irq_handler, gpio_sifive_irq_handler,
DEVICE_GET(gpio_sifive_0), DEVICE_GET(gpio_sifive_0),
0); 0);
#endif #endif
#ifdef CONFIG_SIFIVE_GPIO_0_IRQ_3 #ifdef DT_SIFIVE_GPIO_0_IRQ_3
IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + CONFIG_SIFIVE_GPIO_0_IRQ_3, IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + DT_SIFIVE_GPIO_0_IRQ_3,
CONFIG_GPIO_SIFIVE_3_PRIORITY, CONFIG_GPIO_SIFIVE_3_PRIORITY,
gpio_sifive_irq_handler, gpio_sifive_irq_handler,
DEVICE_GET(gpio_sifive_0), DEVICE_GET(gpio_sifive_0),
0); 0);
#endif #endif
#ifdef CONFIG_SIFIVE_GPIO_0_IRQ_4 #ifdef DT_SIFIVE_GPIO_0_IRQ_4
IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + CONFIG_SIFIVE_GPIO_0_IRQ_4, IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + DT_SIFIVE_GPIO_0_IRQ_4,
CONFIG_GPIO_SIFIVE_4_PRIORITY, CONFIG_GPIO_SIFIVE_4_PRIORITY,
gpio_sifive_irq_handler, gpio_sifive_irq_handler,
DEVICE_GET(gpio_sifive_0), DEVICE_GET(gpio_sifive_0),
0); 0);
#endif #endif
#ifdef CONFIG_SIFIVE_GPIO_0_IRQ_5 #ifdef DT_SIFIVE_GPIO_0_IRQ_5
IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + CONFIG_SIFIVE_GPIO_0_IRQ_5, IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + DT_SIFIVE_GPIO_0_IRQ_5,
CONFIG_GPIO_SIFIVE_5_PRIORITY, CONFIG_GPIO_SIFIVE_5_PRIORITY,
gpio_sifive_irq_handler, gpio_sifive_irq_handler,
DEVICE_GET(gpio_sifive_0), DEVICE_GET(gpio_sifive_0),
0); 0);
#endif #endif
#ifdef CONFIG_SIFIVE_GPIO_0_IRQ_6 #ifdef DT_SIFIVE_GPIO_0_IRQ_6
IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + CONFIG_SIFIVE_GPIO_0_IRQ_6, IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + DT_SIFIVE_GPIO_0_IRQ_6,
CONFIG_GPIO_SIFIVE_6_PRIORITY, CONFIG_GPIO_SIFIVE_6_PRIORITY,
gpio_sifive_irq_handler, gpio_sifive_irq_handler,
DEVICE_GET(gpio_sifive_0), DEVICE_GET(gpio_sifive_0),
0); 0);
#endif #endif
#ifdef CONFIG_SIFIVE_GPIO_0_IRQ_7 #ifdef DT_SIFIVE_GPIO_0_IRQ_7
IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + CONFIG_SIFIVE_GPIO_0_IRQ_7, IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + DT_SIFIVE_GPIO_0_IRQ_7,
CONFIG_GPIO_SIFIVE_7_PRIORITY, CONFIG_GPIO_SIFIVE_7_PRIORITY,
gpio_sifive_irq_handler, gpio_sifive_irq_handler,
DEVICE_GET(gpio_sifive_0), DEVICE_GET(gpio_sifive_0),
0); 0);
#endif #endif
#ifdef CONFIG_SIFIVE_GPIO_0_IRQ_8 #ifdef DT_SIFIVE_GPIO_0_IRQ_8
IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + CONFIG_SIFIVE_GPIO_0_IRQ_8, IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + DT_SIFIVE_GPIO_0_IRQ_8,
CONFIG_GPIO_SIFIVE_8_PRIORITY, CONFIG_GPIO_SIFIVE_8_PRIORITY,
gpio_sifive_irq_handler, gpio_sifive_irq_handler,
DEVICE_GET(gpio_sifive_0), DEVICE_GET(gpio_sifive_0),
0); 0);
#endif #endif
#ifdef CONFIG_SIFIVE_GPIO_0_IRQ_9 #ifdef DT_SIFIVE_GPIO_0_IRQ_9
IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + CONFIG_SIFIVE_GPIO_0_IRQ_9, IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + DT_SIFIVE_GPIO_0_IRQ_9,
CONFIG_GPIO_SIFIVE_9_PRIORITY, CONFIG_GPIO_SIFIVE_9_PRIORITY,
gpio_sifive_irq_handler, gpio_sifive_irq_handler,
DEVICE_GET(gpio_sifive_0), DEVICE_GET(gpio_sifive_0),
0); 0);
#endif #endif
#ifdef CONFIG_SIFIVE_GPIO_0_IRQ_10 #ifdef DT_SIFIVE_GPIO_0_IRQ_10
IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + CONFIG_SIFIVE_GPIO_0_IRQ_10, IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + DT_SIFIVE_GPIO_0_IRQ_10,
CONFIG_GPIO_SIFIVE_10_PRIORITY, CONFIG_GPIO_SIFIVE_10_PRIORITY,
gpio_sifive_irq_handler, gpio_sifive_irq_handler,
DEVICE_GET(gpio_sifive_0), DEVICE_GET(gpio_sifive_0),
0); 0);
#endif #endif
#ifdef CONFIG_SIFIVE_GPIO_0_IRQ_11 #ifdef DT_SIFIVE_GPIO_0_IRQ_11
IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + CONFIG_SIFIVE_GPIO_0_IRQ_11, IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + DT_SIFIVE_GPIO_0_IRQ_11,
CONFIG_GPIO_SIFIVE_11_PRIORITY, CONFIG_GPIO_SIFIVE_11_PRIORITY,
gpio_sifive_irq_handler, gpio_sifive_irq_handler,
DEVICE_GET(gpio_sifive_0), DEVICE_GET(gpio_sifive_0),
0); 0);
#endif #endif
#ifdef CONFIG_SIFIVE_GPIO_0_IRQ_12 #ifdef DT_SIFIVE_GPIO_0_IRQ_12
IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + CONFIG_SIFIVE_GPIO_0_IRQ_12, IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + DT_SIFIVE_GPIO_0_IRQ_12,
CONFIG_GPIO_SIFIVE_12_PRIORITY, CONFIG_GPIO_SIFIVE_12_PRIORITY,
gpio_sifive_irq_handler, gpio_sifive_irq_handler,
DEVICE_GET(gpio_sifive_0), DEVICE_GET(gpio_sifive_0),
0); 0);
#endif #endif
#ifdef CONFIG_SIFIVE_GPIO_0_IRQ_13 #ifdef DT_SIFIVE_GPIO_0_IRQ_13
IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + CONFIG_SIFIVE_GPIO_0_IRQ_13, IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + DT_SIFIVE_GPIO_0_IRQ_13,
CONFIG_GPIO_SIFIVE_13_PRIORITY, CONFIG_GPIO_SIFIVE_13_PRIORITY,
gpio_sifive_irq_handler, gpio_sifive_irq_handler,
DEVICE_GET(gpio_sifive_0), DEVICE_GET(gpio_sifive_0),
0); 0);
#endif #endif
#ifdef CONFIG_SIFIVE_GPIO_0_IRQ_14 #ifdef DT_SIFIVE_GPIO_0_IRQ_14
IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + CONFIG_SIFIVE_GPIO_0_IRQ_14, IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + DT_SIFIVE_GPIO_0_IRQ_14,
CONFIG_GPIO_SIFIVE_14_PRIORITY, CONFIG_GPIO_SIFIVE_14_PRIORITY,
gpio_sifive_irq_handler, gpio_sifive_irq_handler,
DEVICE_GET(gpio_sifive_0), DEVICE_GET(gpio_sifive_0),
0); 0);
#endif #endif
#ifdef CONFIG_SIFIVE_GPIO_0_IRQ_15 #ifdef DT_SIFIVE_GPIO_0_IRQ_15
IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + CONFIG_SIFIVE_GPIO_0_IRQ_15, IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + DT_SIFIVE_GPIO_0_IRQ_15,
CONFIG_GPIO_SIFIVE_15_PRIORITY, CONFIG_GPIO_SIFIVE_15_PRIORITY,
gpio_sifive_irq_handler, gpio_sifive_irq_handler,
DEVICE_GET(gpio_sifive_0), DEVICE_GET(gpio_sifive_0),
0); 0);
#endif #endif
#ifdef CONFIG_SIFIVE_GPIO_0_IRQ_16 #ifdef DT_SIFIVE_GPIO_0_IRQ_16
IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + CONFIG_SIFIVE_GPIO_0_IRQ_16, IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + DT_SIFIVE_GPIO_0_IRQ_16,
CONFIG_GPIO_SIFIVE_16_PRIORITY, CONFIG_GPIO_SIFIVE_16_PRIORITY,
gpio_sifive_irq_handler, gpio_sifive_irq_handler,
DEVICE_GET(gpio_sifive_0), DEVICE_GET(gpio_sifive_0),
0); 0);
#endif #endif
#ifdef CONFIG_SIFIVE_GPIO_0_IRQ_17 #ifdef DT_SIFIVE_GPIO_0_IRQ_17
IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + CONFIG_SIFIVE_GPIO_0_IRQ_17, IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + DT_SIFIVE_GPIO_0_IRQ_17,
CONFIG_GPIO_SIFIVE_17_PRIORITY, CONFIG_GPIO_SIFIVE_17_PRIORITY,
gpio_sifive_irq_handler, gpio_sifive_irq_handler,
DEVICE_GET(gpio_sifive_0), DEVICE_GET(gpio_sifive_0),
0); 0);
#endif #endif
#ifdef CONFIG_SIFIVE_GPIO_0_IRQ_18 #ifdef DT_SIFIVE_GPIO_0_IRQ_18
IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + CONFIG_SIFIVE_GPIO_0_IRQ_18, IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + DT_SIFIVE_GPIO_0_IRQ_18,
CONFIG_GPIO_SIFIVE_18_PRIORITY, CONFIG_GPIO_SIFIVE_18_PRIORITY,
gpio_sifive_irq_handler, gpio_sifive_irq_handler,
DEVICE_GET(gpio_sifive_0), DEVICE_GET(gpio_sifive_0),
0); 0);
#endif #endif
#ifdef CONFIG_SIFIVE_GPIO_0_IRQ_19 #ifdef DT_SIFIVE_GPIO_0_IRQ_19
IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + CONFIG_SIFIVE_GPIO_0_IRQ_19, IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + DT_SIFIVE_GPIO_0_IRQ_19,
CONFIG_GPIO_SIFIVE_19_PRIORITY, CONFIG_GPIO_SIFIVE_19_PRIORITY,
gpio_sifive_irq_handler, gpio_sifive_irq_handler,
DEVICE_GET(gpio_sifive_0), DEVICE_GET(gpio_sifive_0),
0); 0);
#endif #endif
#ifdef CONFIG_SIFIVE_GPIO_0_IRQ_20 #ifdef DT_SIFIVE_GPIO_0_IRQ_20
IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + CONFIG_SIFIVE_GPIO_0_IRQ_20, IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + DT_SIFIVE_GPIO_0_IRQ_20,
CONFIG_GPIO_SIFIVE_20_PRIORITY, CONFIG_GPIO_SIFIVE_20_PRIORITY,
gpio_sifive_irq_handler, gpio_sifive_irq_handler,
DEVICE_GET(gpio_sifive_0), DEVICE_GET(gpio_sifive_0),
0); 0);
#endif #endif
#ifdef CONFIG_SIFIVE_GPIO_0_IRQ_21 #ifdef DT_SIFIVE_GPIO_0_IRQ_21
IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + CONFIG_SIFIVE_GPIO_0_IRQ_21, IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + DT_SIFIVE_GPIO_0_IRQ_21,
CONFIG_GPIO_SIFIVE_21_PRIORITY, CONFIG_GPIO_SIFIVE_21_PRIORITY,
gpio_sifive_irq_handler, gpio_sifive_irq_handler,
DEVICE_GET(gpio_sifive_0), DEVICE_GET(gpio_sifive_0),
0); 0);
#endif #endif
#ifdef CONFIG_SIFIVE_GPIO_0_IRQ_22 #ifdef DT_SIFIVE_GPIO_0_IRQ_22
IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + CONFIG_SIFIVE_GPIO_0_IRQ_22, IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + DT_SIFIVE_GPIO_0_IRQ_22,
CONFIG_GPIO_SIFIVE_22_PRIORITY, CONFIG_GPIO_SIFIVE_22_PRIORITY,
gpio_sifive_irq_handler, gpio_sifive_irq_handler,
DEVICE_GET(gpio_sifive_0), DEVICE_GET(gpio_sifive_0),
0); 0);
#endif #endif
#ifdef CONFIG_SIFIVE_GPIO_0_IRQ_23 #ifdef DT_SIFIVE_GPIO_0_IRQ_23
IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + CONFIG_SIFIVE_GPIO_0_IRQ_23, IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + DT_SIFIVE_GPIO_0_IRQ_23,
CONFIG_GPIO_SIFIVE_23_PRIORITY, CONFIG_GPIO_SIFIVE_23_PRIORITY,
gpio_sifive_irq_handler, gpio_sifive_irq_handler,
DEVICE_GET(gpio_sifive_0), DEVICE_GET(gpio_sifive_0),
0); 0);
#endif #endif
#ifdef CONFIG_SIFIVE_GPIO_0_IRQ_24 #ifdef DT_SIFIVE_GPIO_0_IRQ_24
IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + CONFIG_SIFIVE_GPIO_0_IRQ_24, IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + DT_SIFIVE_GPIO_0_IRQ_24,
CONFIG_GPIO_SIFIVE_24_PRIORITY, CONFIG_GPIO_SIFIVE_24_PRIORITY,
gpio_sifive_irq_handler, gpio_sifive_irq_handler,
DEVICE_GET(gpio_sifive_0), DEVICE_GET(gpio_sifive_0),
0); 0);
#endif #endif
#ifdef CONFIG_SIFIVE_GPIO_0_IRQ_25 #ifdef DT_SIFIVE_GPIO_0_IRQ_25
IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + CONFIG_SIFIVE_GPIO_0_IRQ_25, IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + DT_SIFIVE_GPIO_0_IRQ_25,
CONFIG_GPIO_SIFIVE_25_PRIORITY, CONFIG_GPIO_SIFIVE_25_PRIORITY,
gpio_sifive_irq_handler, gpio_sifive_irq_handler,
DEVICE_GET(gpio_sifive_0), DEVICE_GET(gpio_sifive_0),
0); 0);
#endif #endif
#ifdef CONFIG_SIFIVE_GPIO_0_IRQ_26 #ifdef DT_SIFIVE_GPIO_0_IRQ_26
IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + CONFIG_SIFIVE_GPIO_0_IRQ_26, IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + DT_SIFIVE_GPIO_0_IRQ_26,
CONFIG_GPIO_SIFIVE_26_PRIORITY, CONFIG_GPIO_SIFIVE_26_PRIORITY,
gpio_sifive_irq_handler, gpio_sifive_irq_handler,
DEVICE_GET(gpio_sifive_0), DEVICE_GET(gpio_sifive_0),
0); 0);
#endif #endif
#ifdef CONFIG_SIFIVE_GPIO_0_IRQ_27 #ifdef DT_SIFIVE_GPIO_0_IRQ_27
IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + CONFIG_SIFIVE_GPIO_0_IRQ_27, IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + DT_SIFIVE_GPIO_0_IRQ_27,
CONFIG_GPIO_SIFIVE_27_PRIORITY, CONFIG_GPIO_SIFIVE_27_PRIORITY,
gpio_sifive_irq_handler, gpio_sifive_irq_handler,
DEVICE_GET(gpio_sifive_0), DEVICE_GET(gpio_sifive_0),
0); 0);
#endif #endif
#ifdef CONFIG_SIFIVE_GPIO_0_IRQ_28 #ifdef DT_SIFIVE_GPIO_0_IRQ_28
IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + CONFIG_SIFIVE_GPIO_0_IRQ_28, IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + DT_SIFIVE_GPIO_0_IRQ_28,
CONFIG_GPIO_SIFIVE_28_PRIORITY, CONFIG_GPIO_SIFIVE_28_PRIORITY,
gpio_sifive_irq_handler, gpio_sifive_irq_handler,
DEVICE_GET(gpio_sifive_0), DEVICE_GET(gpio_sifive_0),
0); 0);
#endif #endif
#ifdef CONFIG_SIFIVE_GPIO_0_IRQ_29 #ifdef DT_SIFIVE_GPIO_0_IRQ_29
IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + CONFIG_SIFIVE_GPIO_0_IRQ_29, IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + DT_SIFIVE_GPIO_0_IRQ_29,
CONFIG_GPIO_SIFIVE_29_PRIORITY, CONFIG_GPIO_SIFIVE_29_PRIORITY,
gpio_sifive_irq_handler, gpio_sifive_irq_handler,
DEVICE_GET(gpio_sifive_0), DEVICE_GET(gpio_sifive_0),
0); 0);
#endif #endif
#ifdef CONFIG_SIFIVE_GPIO_0_IRQ_30 #ifdef DT_SIFIVE_GPIO_0_IRQ_30
IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + CONFIG_SIFIVE_GPIO_0_IRQ_30, IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + DT_SIFIVE_GPIO_0_IRQ_30,
CONFIG_GPIO_SIFIVE_30_PRIORITY, CONFIG_GPIO_SIFIVE_30_PRIORITY,
gpio_sifive_irq_handler, gpio_sifive_irq_handler,
DEVICE_GET(gpio_sifive_0), DEVICE_GET(gpio_sifive_0),
0); 0);
#endif #endif
#ifdef CONFIG_SIFIVE_GPIO_0_IRQ_31 #ifdef DT_SIFIVE_GPIO_0_IRQ_31
IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + CONFIG_SIFIVE_GPIO_0_IRQ_31, IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + DT_SIFIVE_GPIO_0_IRQ_31,
CONFIG_GPIO_SIFIVE_31_PRIORITY, CONFIG_GPIO_SIFIVE_31_PRIORITY,
gpio_sifive_irq_handler, gpio_sifive_irq_handler,
DEVICE_GET(gpio_sifive_0), DEVICE_GET(gpio_sifive_0),

8
drivers/gpio/gpio_stm32.c
View file

@ -212,12 +212,12 @@ DEVICE_AND_API_INIT(gpio_stm32_## __suffix, \
#define GPIO_DEVICE_INIT_STM32(__suffix, __SUFFIX) \ #define GPIO_DEVICE_INIT_STM32(__suffix, __SUFFIX) \
GPIO_DEVICE_INIT(CONFIG_GPIO_STM32_GPIO##__SUFFIX##_LABEL, \ GPIO_DEVICE_INIT(DT_GPIO_STM32_GPIO##__SUFFIX##_LABEL, \
__suffix, \ __suffix, \
CONFIG_GPIO_STM32_GPIO##__SUFFIX##_BASE_ADDRESS, \ DT_GPIO_STM32_GPIO##__SUFFIX##_BASE_ADDRESS, \
STM32_PORT##__SUFFIX, \ STM32_PORT##__SUFFIX, \
CONFIG_GPIO_STM32_GPIO##__SUFFIX##_CLOCK_BITS, \ DT_GPIO_STM32_GPIO##__SUFFIX##_CLOCK_BITS, \
CONFIG_GPIO_STM32_GPIO##__SUFFIX##_CLOCK_BUS) DT_GPIO_STM32_GPIO##__SUFFIX##_CLOCK_BUS)
#ifdef CONFIG_GPIO_STM32_PORTA #ifdef CONFIG_GPIO_STM32_PORTA
GPIO_DEVICE_INIT_STM32(a, A); GPIO_DEVICE_INIT_STM32(a, A);

12
drivers/i2c/i2c_cc32xx.c
View file

@ -372,22 +372,22 @@ static const struct i2c_driver_api i2c_cc32xx_driver_api = {
static const struct i2c_cc32xx_config i2c_cc32xx_config = { static const struct i2c_cc32xx_config i2c_cc32xx_config = {
.base = CONFIG_I2C_0_BASE_ADDRESS, .base = DT_I2C_0_BASE_ADDRESS,
.bitrate = CONFIG_I2C_0_BITRATE, .bitrate = DT_I2C_0_BITRATE,
.irq_no = CONFIG_I2C_0_IRQ, .irq_no = DT_I2C_0_IRQ,
}; };
static struct i2c_cc32xx_data i2c_cc32xx_data; static struct i2c_cc32xx_data i2c_cc32xx_data;
DEVICE_AND_API_INIT(i2c_cc32xx, CONFIG_I2C_0_LABEL, &i2c_cc32xx_init, DEVICE_AND_API_INIT(i2c_cc32xx, DT_I2C_0_LABEL, &i2c_cc32xx_init,
&i2c_cc32xx_data, &i2c_cc32xx_config, &i2c_cc32xx_data, &i2c_cc32xx_config,
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
&i2c_cc32xx_driver_api); &i2c_cc32xx_driver_api);
static void configure_i2c_irq(const struct i2c_cc32xx_config *config) static void configure_i2c_irq(const struct i2c_cc32xx_config *config)
{ {
IRQ_CONNECT(CONFIG_I2C_0_IRQ, IRQ_CONNECT(DT_I2C_0_IRQ,
CONFIG_I2C_0_IRQ_PRIORITY, DT_I2C_0_IRQ_PRIORITY,
i2c_cc32xx_isr, DEVICE_GET(i2c_cc32xx), 0); i2c_cc32xx_isr, DEVICE_GET(i2c_cc32xx), 0);
irq_enable(config->irq_no); irq_enable(config->irq_no);

80
drivers/i2c/i2c_dw.c
View file

@ -706,11 +706,11 @@ static const struct i2c_dw_rom_config i2c_config_dw_0 = {
#ifdef CONFIG_GPIO_DW_0_IRQ_SHARED #ifdef CONFIG_GPIO_DW_0_IRQ_SHARED
.shared_irq_dev_name = CONFIG_I2C_DW_0_IRQ_SHARED_NAME, .shared_irq_dev_name = CONFIG_I2C_DW_0_IRQ_SHARED_NAME,
#endif #endif
.bitrate = CONFIG_I2C_0_BITRATE, .bitrate = DT_I2C_0_BITRATE,
}; };
static struct i2c_dw_dev_config i2c_0_runtime = { static struct i2c_dw_dev_config i2c_0_runtime = {
.base_address = CONFIG_I2C_0_BASE_ADDR, .base_address = DT_I2C_0_BASE_ADDR,
#if CONFIG_PCI #if CONFIG_PCI
.pci_dev.class_type = I2C_DW_0_PCI_CLASS, .pci_dev.class_type = I2C_DW_0_PCI_CLASS,
.pci_dev.bus = I2C_DW_0_PCI_BUS, .pci_dev.bus = I2C_DW_0_PCI_BUS,
@ -730,9 +730,9 @@ DEVICE_AND_API_INIT(i2c_0, CONFIG_I2C_0_NAME, &i2c_dw_initialize,
static void i2c_config_0(struct device *port) static void i2c_config_0(struct device *port)
{ {
#if defined(CONFIG_I2C_DW_0_IRQ_DIRECT) #if defined(CONFIG_I2C_DW_0_IRQ_DIRECT)
IRQ_CONNECT(CONFIG_I2C_0_IRQ, CONFIG_I2C_0_IRQ_PRI, IRQ_CONNECT(DT_I2C_0_IRQ, CONFIG_I2C_0_IRQ_PRI,
i2c_dw_isr, DEVICE_GET(i2c_0), CONFIG_I2C_0_IRQ_FLAGS); i2c_dw_isr, DEVICE_GET(i2c_0), DT_I2C_0_IRQ_FLAGS);
irq_enable(CONFIG_I2C_0_IRQ); irq_enable(DT_I2C_0_IRQ);
#elif defined(CONFIG_I2C_DW_0_IRQ_SHARED) #elif defined(CONFIG_I2C_DW_0_IRQ_SHARED)
const struct i2c_dw_rom_config * const config = const struct i2c_dw_rom_config * const config =
port->config->config_info; port->config->config_info;
@ -754,11 +754,11 @@ static void i2c_config_1(struct device *port);
static const struct i2c_dw_rom_config i2c_config_dw_1 = { static const struct i2c_dw_rom_config i2c_config_dw_1 = {
.config_func = i2c_config_1, .config_func = i2c_config_1,
.bitrate = CONFIG_I2C_1_BITRATE, .bitrate = DT_I2C_1_BITRATE,
}; };
static struct i2c_dw_dev_config i2c_1_runtime = { static struct i2c_dw_dev_config i2c_1_runtime = {
.base_address = CONFIG_I2C_1_BASE_ADDR, .base_address = DT_I2C_1_BASE_ADDR,
#if CONFIG_PCI #if CONFIG_PCI
.pci_dev.class_type = I2C_DW_1_PCI_CLASS, .pci_dev.class_type = I2C_DW_1_PCI_CLASS,
.pci_dev.bus = I2C_DW_1_PCI_BUS, .pci_dev.bus = I2C_DW_1_PCI_BUS,
@ -777,9 +777,9 @@ DEVICE_AND_API_INIT(i2c_1, CONFIG_I2C_1_NAME, &i2c_dw_initialize,
static void i2c_config_1(struct device *port) static void i2c_config_1(struct device *port)
{ {
IRQ_CONNECT(CONFIG_I2C_1_IRQ, CONFIG_I2C_1_IRQ_PRI, IRQ_CONNECT(DT_I2C_1_IRQ, CONFIG_I2C_1_IRQ_PRI,
i2c_dw_isr, DEVICE_GET(i2c_1), CONFIG_I2C_1_IRQ_FLAGS); i2c_dw_isr, DEVICE_GET(i2c_1), DT_I2C_1_IRQ_FLAGS);
irq_enable(CONFIG_I2C_1_IRQ); irq_enable(DT_I2C_1_IRQ);
} }
#endif /* CONFIG_I2C_1 */ #endif /* CONFIG_I2C_1 */
@ -792,11 +792,11 @@ static void i2c_config_2(struct device *port);
static const struct i2c_dw_rom_config i2c_config_dw_2 = { static const struct i2c_dw_rom_config i2c_config_dw_2 = {
.config_func = i2c_config_2, .config_func = i2c_config_2,
.bitrate = CONFIG_I2C_2_BITRATE, .bitrate = DT_I2C_2_BITRATE,
}; };
static struct i2c_dw_dev_config I2C_2_runtime = { static struct i2c_dw_dev_config I2C_2_runtime = {
.base_address = CONFIG_I2C_2_BASE_ADDR, .base_address = DT_I2C_2_BASE_ADDR,
#if CONFIG_PCI #if CONFIG_PCI
.pci_dev.class_type = I2C_DW_2_PCI_CLASS, .pci_dev.class_type = I2C_DW_2_PCI_CLASS,
.pci_dev.bus = I2C_DW_2_PCI_BUS, .pci_dev.bus = I2C_DW_2_PCI_BUS,
@ -815,9 +815,9 @@ DEVICE_AND_API_INIT(I2C_2, CONFIG_I2C_2_NAME, &i2c_dw_initialize,
static void i2c_config_2(struct device *port) static void i2c_config_2(struct device *port)
{ {
IRQ_CONNECT(CONFIG_I2C_2_IRQ, CONFIG_I2C_2_IRQ_PRI, IRQ_CONNECT(DT_I2C_2_IRQ, CONFIG_I2C_2_IRQ_PRI,
i2c_dw_isr, DEVICE_GET(I2C_2), CONFIG_I2C_2_IRQ_FLAGS); i2c_dw_isr, DEVICE_GET(I2C_2), DT_I2C_2_IRQ_FLAGS);
irq_enable(CONFIG_I2C_2_IRQ); irq_enable(DT_I2C_2_IRQ);
} }
#endif /* CONFIG_I2C_2 */ #endif /* CONFIG_I2C_2 */
@ -830,11 +830,11 @@ static void i2c_config_3(struct device *port);
static const struct i2c_dw_rom_config i2c_config_dw_3 = { static const struct i2c_dw_rom_config i2c_config_dw_3 = {
.config_func = i2c_config_3, .config_func = i2c_config_3,
.bitrate = CONFIG_I2C_3_BITRATE, .bitrate = DT_I2C_3_BITRATE,
}; };
static struct i2c_dw_dev_config I2C_3_runtime = { static struct i2c_dw_dev_config I2C_3_runtime = {
.base_address = CONFIG_I2C_3_BASE_ADDR, .base_address = DT_I2C_3_BASE_ADDR,
#if CONFIG_PCI #if CONFIG_PCI
.pci_dev.class_type = I2C_DW_3_PCI_CLASS, .pci_dev.class_type = I2C_DW_3_PCI_CLASS,
.pci_dev.bus = I2C_DW_3_PCI_BUS, .pci_dev.bus = I2C_DW_3_PCI_BUS,
@ -853,9 +853,9 @@ DEVICE_AND_API_INIT(I2C_3, CONFIG_I2C_3_NAME, &i2c_dw_initialize,
static void i2c_config_3(struct device *port) static void i2c_config_3(struct device *port)
{ {
IRQ_CONNECT(CONFIG_I2C_3_IRQ, CONFIG_I2C_3_IRQ_PRI, IRQ_CONNECT(DT_I2C_3_IRQ, CONFIG_I2C_3_IRQ_PRI,
i2c_dw_isr, DEVICE_GET(I2C_3), CONFIG_I2C_3_IRQ_FLAGS); i2c_dw_isr, DEVICE_GET(I2C_3), DT_I2C_3_IRQ_FLAGS);
irq_enable(CONFIG_I2C_3_IRQ); irq_enable(DT_I2C_3_IRQ);
} }
#endif /* CONFIG_I2C_3 */ #endif /* CONFIG_I2C_3 */
@ -868,11 +868,11 @@ static void i2c_config_4(struct device *port);
static const struct i2c_dw_rom_config i2c_config_dw_4 = { static const struct i2c_dw_rom_config i2c_config_dw_4 = {
.config_func = i2c_config_4, .config_func = i2c_config_4,
.bitrate = CONFIG_I2C_4_BITRATE, .bitrate = DT_I2C_4_BITRATE,
}; };
static struct i2c_dw_dev_config I2C_4_runtime = { static struct i2c_dw_dev_config I2C_4_runtime = {
.base_address = CONFIG_I2C_4_BASE_ADDR, .base_address = DT_I2C_4_BASE_ADDR,
#if CONFIG_PCI #if CONFIG_PCI
.pci_dev.class_type = I2C_DW_4_PCI_CLASS, .pci_dev.class_type = I2C_DW_4_PCI_CLASS,
.pci_dev.bus = I2C_DW_4_PCI_BUS, .pci_dev.bus = I2C_DW_4_PCI_BUS,
@ -891,9 +891,9 @@ DEVICE_AND_API_INIT(I2C_4, CONFIG_I2C_4_NAME, &i2c_dw_initialize,
static void i2c_config_4(struct device *port) static void i2c_config_4(struct device *port)
{ {
IRQ_CONNECT(CONFIG_I2C_4_IRQ, CONFIG_I2C_4_IRQ_PRI, IRQ_CONNECT(DT_I2C_4_IRQ, CONFIG_I2C_4_IRQ_PRI,
i2c_dw_isr, DEVICE_GET(I2C_4), CONFIG_I2C_4_IRQ_FLAGS); i2c_dw_isr, DEVICE_GET(I2C_4), DT_I2C_4_IRQ_FLAGS);
irq_enable(CONFIG_I2C_4_IRQ); irq_enable(DT_I2C_4_IRQ);
} }
#endif /* CONFIG_I2C_4 */ #endif /* CONFIG_I2C_4 */
@ -906,11 +906,11 @@ static void i2c_config_5(struct device *port);
static const struct i2c_dw_rom_config i2c_config_dw_5 = { static const struct i2c_dw_rom_config i2c_config_dw_5 = {
.config_func = i2c_config_5, .config_func = i2c_config_5,
.bitrate = CONFIG_I2C_5_BITRATE, .bitrate = DT_I2C_5_BITRATE,
}; };
static struct i2c_dw_dev_config I2C_5_runtime = { static struct i2c_dw_dev_config I2C_5_runtime = {
.base_address = CONFIG_I2C_5_BASE_ADDR, .base_address = DT_I2C_5_BASE_ADDR,
#if CONFIG_PCI #if CONFIG_PCI
.pci_dev.class_type = I2C_DW_5_PCI_CLASS, .pci_dev.class_type = I2C_DW_5_PCI_CLASS,
.pci_dev.bus = I2C_DW_5_PCI_BUS, .pci_dev.bus = I2C_DW_5_PCI_BUS,
@ -929,9 +929,9 @@ DEVICE_AND_API_INIT(I2C_5, CONFIG_I2C_5_NAME, &i2c_dw_initialize,
static void i2c_config_5(struct device *port) static void i2c_config_5(struct device *port)
{ {
IRQ_CONNECT(CONFIG_I2C_5_IRQ, CONFIG_I2C_5_IRQ_PRI, IRQ_CONNECT(DT_I2C_5_IRQ, CONFIG_I2C_5_IRQ_PRI,
i2c_dw_isr, DEVICE_GET(I2C_5), CONFIG_I2C_5_IRQ_FLAGS); i2c_dw_isr, DEVICE_GET(I2C_5), DT_I2C_5_IRQ_FLAGS);
irq_enable(CONFIG_I2C_5_IRQ); irq_enable(DT_I2C_5_IRQ);
} }
#endif /* CONFIG_I2C_5 */ #endif /* CONFIG_I2C_5 */
@ -944,11 +944,11 @@ static void i2c_config_6(struct device *port);
static const struct i2c_dw_rom_config i2c_config_dw_6 = { static const struct i2c_dw_rom_config i2c_config_dw_6 = {
.config_func = i2c_config_6, .config_func = i2c_config_6,
.bitrate = CONFIG_I2C_6_BITRATE, .bitrate = DT_I2C_6_BITRATE,
}; };
static struct i2c_dw_dev_config I2C_6_runtime = { static struct i2c_dw_dev_config I2C_6_runtime = {
.base_address = CONFIG_I2C_6_BASE_ADDR, .base_address = DT_I2C_6_BASE_ADDR,
#if CONFIG_PCI #if CONFIG_PCI
.pci_dev.class_type = I2C_DW_6_PCI_CLASS, .pci_dev.class_type = I2C_DW_6_PCI_CLASS,
.pci_dev.bus = I2C_DW_6_PCI_BUS, .pci_dev.bus = I2C_DW_6_PCI_BUS,
@ -967,9 +967,9 @@ DEVICE_AND_API_INIT(I2C_6, CONFIG_I2C_6_NAME, &i2c_dw_initialize,
static void i2c_config_6(struct device *port) static void i2c_config_6(struct device *port)
{ {
IRQ_CONNECT(CONFIG_I2C_6_IRQ, CONFIG_I2C_6_IRQ_PRI, IRQ_CONNECT(DT_I2C_6_IRQ, CONFIG_I2C_6_IRQ_PRI,
i2c_dw_isr, DEVICE_GET(I2C_6), CONFIG_I2C_6_IRQ_FLAGS); i2c_dw_isr, DEVICE_GET(I2C_6), DT_I2C_6_IRQ_FLAGS);
irq_enable(CONFIG_I2C_6_IRQ); irq_enable(DT_I2C_6_IRQ);
} }
#endif /* CONFIG_I2C_6 */ #endif /* CONFIG_I2C_6 */
@ -982,11 +982,11 @@ static void i2c_config_7(struct device *port);
static const struct i2c_dw_rom_config i2c_config_dw_7 = { static const struct i2c_dw_rom_config i2c_config_dw_7 = {
.config_func = i2c_config_7, .config_func = i2c_config_7,
.bitrate = CONFIG_I2C_7_BITRATE, .bitrate = DT_I2C_7_BITRATE,
}; };
static struct i2c_dw_dev_config I2C_7_runtime = { static struct i2c_dw_dev_config I2C_7_runtime = {
.base_address = CONFIG_I2C_7_BASE_ADDR, .base_address = DT_I2C_7_BASE_ADDR,
#if CONFIG_PCI #if CONFIG_PCI
.pci_dev.class_type = I2C_DW_7_PCI_CLASS, .pci_dev.class_type = I2C_DW_7_PCI_CLASS,
.pci_dev.bus = I2C_DW_7_PCI_BUS, .pci_dev.bus = I2C_DW_7_PCI_BUS,
@ -1005,9 +1005,9 @@ DEVICE_AND_API_INIT(I2C_7, CONFIG_I2C_7_NAME, &i2c_dw_initialize,
static void i2c_config_7(struct device *port) static void i2c_config_7(struct device *port)
{ {
IRQ_CONNECT(CONFIG_I2C_7_IRQ, CONFIG_I2C_7_IRQ_PRI, IRQ_CONNECT(DT_I2C_7_IRQ, CONFIG_I2C_7_IRQ_PRI,
i2c_dw_isr, DEVICE_GET(I2C_7), CONFIG_I2C_7_IRQ_FLAGS); i2c_dw_isr, DEVICE_GET(I2C_7), DT_I2C_7_IRQ_FLAGS);
irq_enable(CONFIG_I2C_7_IRQ); irq_enable(DT_I2C_7_IRQ);
} }
#endif /* CONFIG_I2C_7 */ #endif /* CONFIG_I2C_7 */

16
drivers/i2c/i2c_gecko.c
View file

@ -180,18 +180,18 @@ static const struct i2c_driver_api i2c_gecko_driver_api = {
#ifdef CONFIG_I2C_0 #ifdef CONFIG_I2C_0
static struct i2c_gecko_config i2c_gecko_config_0 = { static struct i2c_gecko_config i2c_gecko_config_0 = {
.base = (I2C_TypeDef *)CONFIG_I2C_GECKO_0_BASE_ADDRESS, .base = (I2C_TypeDef *)DT_I2C_GECKO_0_BASE_ADDRESS,
.clock = cmuClock_I2C0, .clock = cmuClock_I2C0,
.i2cInit = I2C_INIT_DEFAULT, .i2cInit = I2C_INIT_DEFAULT,
.pin_sda = PIN_I2C0_SDA, .pin_sda = PIN_I2C0_SDA,
.pin_scl = PIN_I2C0_SCL, .pin_scl = PIN_I2C0_SCL,
.loc = CONFIG_I2C_GECKO_0_LOCATION, .loc = DT_I2C_GECKO_0_LOCATION,
.bitrate = CONFIG_I2C_GECKO_0_CLOCK_FREQUENCY, .bitrate = DT_I2C_GECKO_0_CLOCK_FREQUENCY,
}; };
static struct i2c_gecko_data i2c_gecko_data_0; static struct i2c_gecko_data i2c_gecko_data_0;
DEVICE_AND_API_INIT(i2c_gecko_0, CONFIG_I2C_GECKO_0_LABEL, &i2c_gecko_init, DEVICE_AND_API_INIT(i2c_gecko_0, DT_I2C_GECKO_0_LABEL, &i2c_gecko_init,
&i2c_gecko_data_0, &i2c_gecko_config_0, &i2c_gecko_data_0, &i2c_gecko_config_0,
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
&i2c_gecko_driver_api); &i2c_gecko_driver_api);
@ -199,18 +199,18 @@ DEVICE_AND_API_INIT(i2c_gecko_0, CONFIG_I2C_GECKO_0_LABEL, &i2c_gecko_init,
#ifdef CONFIG_I2C_1 #ifdef CONFIG_I2C_1
static struct i2c_gecko_config i2c_gecko_config_1 = { static struct i2c_gecko_config i2c_gecko_config_1 = {
.base = (I2C_TypeDef *)CONFIG_I2C_GECKO_1_BASE_ADDRESS, .base = (I2C_TypeDef *)DT_I2C_GECKO_1_BASE_ADDRESS,
.clock = cmuClock_I2C1, .clock = cmuClock_I2C1,
.i2cInit = I2C_INIT_DEFAULT, .i2cInit = I2C_INIT_DEFAULT,
.pin_sda = PIN_I2C1_SDA, .pin_sda = PIN_I2C1_SDA,
.pin_scl = PIN_I2C1_SCL, .pin_scl = PIN_I2C1_SCL,
.loc = CONFIG_I2C_GECKO_1_LOCATION, .loc = DT_I2C_GECKO_1_LOCATION,
.bitrate = CONFIG_I2C_GECKO_1_CLOCK_FREQUENCY, .bitrate = DT_I2C_GECKO_1_CLOCK_FREQUENCY,
}; };
static struct i2c_gecko_data i2c_gecko_data_1; static struct i2c_gecko_data i2c_gecko_data_1;
DEVICE_AND_API_INIT(i2c_gecko_1, CONFIG_I2C_GECKO_1_LABEL, &i2c_gecko_init, DEVICE_AND_API_INIT(i2c_gecko_1, DT_I2C_GECKO_1_LABEL, &i2c_gecko_init,
&i2c_gecko_data_1, &i2c_gecko_config_1, &i2c_gecko_data_1, &i2c_gecko_config_1,
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
&i2c_gecko_driver_api); &i2c_gecko_driver_api);

78
drivers/i2c/i2c_ll_stm32.c
View file

@ -181,19 +181,19 @@ static int i2c_stm32_init(struct device *dev)
switch ((u32_t)cfg->i2c) { switch ((u32_t)cfg->i2c) {
#ifdef CONFIG_I2C_1 #ifdef CONFIG_I2C_1
case CONFIG_I2C_1_BASE_ADDRESS: case DT_I2C_1_BASE_ADDRESS:
LL_RCC_SetI2CClockSource(LL_RCC_I2C1_CLKSOURCE_SYSCLK); LL_RCC_SetI2CClockSource(LL_RCC_I2C1_CLKSOURCE_SYSCLK);
break; break;
#endif /* CONFIG_I2C_1 */ #endif /* CONFIG_I2C_1 */
#if defined(CONFIG_SOC_SERIES_STM32F3X) && defined(CONFIG_I2C_2) #if defined(CONFIG_SOC_SERIES_STM32F3X) && defined(CONFIG_I2C_2)
case CONFIG_I2C_2_BASE_ADDRESS: case DT_I2C_2_BASE_ADDRESS:
LL_RCC_SetI2CClockSource(LL_RCC_I2C2_CLKSOURCE_SYSCLK); LL_RCC_SetI2CClockSource(LL_RCC_I2C2_CLKSOURCE_SYSCLK);
break; break;
#endif /* CONFIG_SOC_SERIES_STM32F3X && CONFIG_I2C_2 */ #endif /* CONFIG_SOC_SERIES_STM32F3X && CONFIG_I2C_2 */
#ifdef CONFIG_I2C_3 #ifdef CONFIG_I2C_3
case CONFIG_I2C_3_BASE_ADDRESS: case DT_I2C_3_BASE_ADDRESS:
LL_RCC_SetI2CClockSource(LL_RCC_I2C3_CLKSOURCE_SYSCLK); LL_RCC_SetI2CClockSource(LL_RCC_I2C3_CLKSOURCE_SYSCLK);
break; break;
#endif /* CONFIG_I2C_3 */ #endif /* CONFIG_I2C_3 */
@ -218,15 +218,15 @@ static void i2c_stm32_irq_config_func_1(struct device *port);
#endif #endif
static const struct i2c_stm32_config i2c_stm32_cfg_1 = { static const struct i2c_stm32_config i2c_stm32_cfg_1 = {
.i2c = (I2C_TypeDef *)CONFIG_I2C_1_BASE_ADDRESS, .i2c = (I2C_TypeDef *)DT_I2C_1_BASE_ADDRESS,
.pclken = { .pclken = {
.enr = CONFIG_I2C_1_CLOCK_BITS, .enr = DT_I2C_1_CLOCK_BITS,
.bus = CONFIG_I2C_1_CLOCK_BUS, .bus = DT_I2C_1_CLOCK_BUS,
}, },
#ifdef CONFIG_I2C_STM32_INTERRUPT #ifdef CONFIG_I2C_STM32_INTERRUPT
.irq_config_func = i2c_stm32_irq_config_func_1, .irq_config_func = i2c_stm32_irq_config_func_1,
#endif #endif
.bitrate = CONFIG_I2C_1_BITRATE, .bitrate = DT_I2C_1_BITRATE,
}; };
static struct i2c_stm32_data i2c_stm32_dev_data_1; static struct i2c_stm32_data i2c_stm32_dev_data_1;
@ -240,17 +240,17 @@ DEVICE_AND_API_INIT(i2c_stm32_1, CONFIG_I2C_1_NAME, &i2c_stm32_init,
static void i2c_stm32_irq_config_func_1(struct device *dev) static void i2c_stm32_irq_config_func_1(struct device *dev)
{ {
#ifdef CONFIG_I2C_STM32_COMBINED_INTERRUPT #ifdef CONFIG_I2C_STM32_COMBINED_INTERRUPT
IRQ_CONNECT(CONFIG_I2C_1_COMBINED_IRQ, CONFIG_I2C_1_COMBINED_IRQ_PRI, IRQ_CONNECT(DT_I2C_1_COMBINED_IRQ, DT_I2C_1_COMBINED_IRQ_PRI,
stm32_i2c_combined_isr, DEVICE_GET(i2c_stm32_1), 0); stm32_i2c_combined_isr, DEVICE_GET(i2c_stm32_1), 0);
irq_enable(CONFIG_I2C_1_COMBINED_IRQ); irq_enable(DT_I2C_1_COMBINED_IRQ);
#else #else
IRQ_CONNECT(CONFIG_I2C_1_EVENT_IRQ, CONFIG_I2C_1_EVENT_IRQ_PRI, IRQ_CONNECT(DT_I2C_1_EVENT_IRQ, DT_I2C_1_EVENT_IRQ_PRI,
stm32_i2c_event_isr, DEVICE_GET(i2c_stm32_1), 0); stm32_i2c_event_isr, DEVICE_GET(i2c_stm32_1), 0);
irq_enable(CONFIG_I2C_1_EVENT_IRQ); irq_enable(DT_I2C_1_EVENT_IRQ);
IRQ_CONNECT(CONFIG_I2C_1_ERROR_IRQ, CONFIG_I2C_1_ERROR_IRQ_PRI, IRQ_CONNECT(DT_I2C_1_ERROR_IRQ, DT_I2C_1_ERROR_IRQ_PRI,
stm32_i2c_error_isr, DEVICE_GET(i2c_stm32_1), 0); stm32_i2c_error_isr, DEVICE_GET(i2c_stm32_1), 0);
irq_enable(CONFIG_I2C_1_ERROR_IRQ); irq_enable(DT_I2C_1_ERROR_IRQ);
#endif #endif
} }
#endif #endif
@ -264,15 +264,15 @@ static void i2c_stm32_irq_config_func_2(struct device *port);
#endif #endif
static const struct i2c_stm32_config i2c_stm32_cfg_2 = { static const struct i2c_stm32_config i2c_stm32_cfg_2 = {
.i2c = (I2C_TypeDef *)CONFIG_I2C_2_BASE_ADDRESS, .i2c = (I2C_TypeDef *)DT_I2C_2_BASE_ADDRESS,
.pclken = { .pclken = {
.enr = CONFIG_I2C_2_CLOCK_BITS, .enr = DT_I2C_2_CLOCK_BITS,
.bus = CONFIG_I2C_2_CLOCK_BUS, .bus = DT_I2C_2_CLOCK_BUS,
}, },
#ifdef CONFIG_I2C_STM32_INTERRUPT #ifdef CONFIG_I2C_STM32_INTERRUPT
.irq_config_func = i2c_stm32_irq_config_func_2, .irq_config_func = i2c_stm32_irq_config_func_2,
#endif #endif
.bitrate = CONFIG_I2C_2_BITRATE, .bitrate = DT_I2C_2_BITRATE,
}; };
static struct i2c_stm32_data i2c_stm32_dev_data_2; static struct i2c_stm32_data i2c_stm32_dev_data_2;
@ -286,17 +286,17 @@ DEVICE_AND_API_INIT(i2c_stm32_2, CONFIG_I2C_2_NAME, &i2c_stm32_init,
static void i2c_stm32_irq_config_func_2(struct device *dev) static void i2c_stm32_irq_config_func_2(struct device *dev)
{ {
#ifdef CONFIG_I2C_STM32_COMBINED_INTERRUPT #ifdef CONFIG_I2C_STM32_COMBINED_INTERRUPT
IRQ_CONNECT(CONFIG_I2C_2_COMBINED_IRQ, CONFIG_I2C_2_COMBINED_IRQ_PRI, IRQ_CONNECT(DT_I2C_2_COMBINED_IRQ, DT_I2C_2_COMBINED_IRQ_PRI,
stm32_i2c_combined_isr, DEVICE_GET(i2c_stm32_2), 0); stm32_i2c_combined_isr, DEVICE_GET(i2c_stm32_2), 0);
irq_enable(CONFIG_I2C_2_COMBINED_IRQ); irq_enable(DT_I2C_2_COMBINED_IRQ);
#else #else
IRQ_CONNECT(CONFIG_I2C_2_EVENT_IRQ, CONFIG_I2C_2_EVENT_IRQ_PRI, IRQ_CONNECT(DT_I2C_2_EVENT_IRQ, DT_I2C_2_EVENT_IRQ_PRI,
stm32_i2c_event_isr, DEVICE_GET(i2c_stm32_2), 0); stm32_i2c_event_isr, DEVICE_GET(i2c_stm32_2), 0);
irq_enable(CONFIG_I2C_2_EVENT_IRQ); irq_enable(DT_I2C_2_EVENT_IRQ);
IRQ_CONNECT(CONFIG_I2C_2_ERROR_IRQ, CONFIG_I2C_2_ERROR_IRQ_PRI, IRQ_CONNECT(DT_I2C_2_ERROR_IRQ, DT_I2C_2_ERROR_IRQ_PRI,
stm32_i2c_error_isr, DEVICE_GET(i2c_stm32_2), 0); stm32_i2c_error_isr, DEVICE_GET(i2c_stm32_2), 0);
irq_enable(CONFIG_I2C_2_ERROR_IRQ); irq_enable(DT_I2C_2_ERROR_IRQ);
#endif #endif
} }
#endif #endif
@ -314,15 +314,15 @@ static void i2c_stm32_irq_config_func_3(struct device *port);
#endif #endif
static const struct i2c_stm32_config i2c_stm32_cfg_3 = { static const struct i2c_stm32_config i2c_stm32_cfg_3 = {
.i2c = (I2C_TypeDef *)CONFIG_I2C_3_BASE_ADDRESS, .i2c = (I2C_TypeDef *)DT_I2C_3_BASE_ADDRESS,
.pclken = { .pclken = {
.enr = CONFIG_I2C_3_CLOCK_BITS, .enr = DT_I2C_3_CLOCK_BITS,
.bus = CONFIG_I2C_3_CLOCK_BUS, .bus = DT_I2C_3_CLOCK_BUS,
}, },
#ifdef CONFIG_I2C_STM32_INTERRUPT #ifdef CONFIG_I2C_STM32_INTERRUPT
.irq_config_func = i2c_stm32_irq_config_func_3, .irq_config_func = i2c_stm32_irq_config_func_3,
#endif #endif
.bitrate = CONFIG_I2C_3_BITRATE, .bitrate = DT_I2C_3_BITRATE,
}; };
static struct i2c_stm32_data i2c_stm32_dev_data_3; static struct i2c_stm32_data i2c_stm32_dev_data_3;
@ -335,13 +335,13 @@ DEVICE_AND_API_INIT(i2c_stm32_3, CONFIG_I2C_3_NAME, &i2c_stm32_init,
#ifdef CONFIG_I2C_STM32_INTERRUPT #ifdef CONFIG_I2C_STM32_INTERRUPT
static void i2c_stm32_irq_config_func_3(struct device *dev) static void i2c_stm32_irq_config_func_3(struct device *dev)
{ {
IRQ_CONNECT(CONFIG_I2C_3_EVENT_IRQ, CONFIG_I2C_3_EVENT_IRQ_PRI, IRQ_CONNECT(DT_I2C_3_EVENT_IRQ, DT_I2C_3_EVENT_IRQ_PRI,
stm32_i2c_event_isr, DEVICE_GET(i2c_stm32_3), 0); stm32_i2c_event_isr, DEVICE_GET(i2c_stm32_3), 0);
irq_enable(CONFIG_I2C_3_EVENT_IRQ); irq_enable(DT_I2C_3_EVENT_IRQ);
IRQ_CONNECT(CONFIG_I2C_3_ERROR_IRQ, CONFIG_I2C_3_ERROR_IRQ_PRI, IRQ_CONNECT(DT_I2C_3_ERROR_IRQ, DT_I2C_3_ERROR_IRQ_PRI,
stm32_i2c_error_isr, DEVICE_GET(i2c_stm32_3), 0); stm32_i2c_error_isr, DEVICE_GET(i2c_stm32_3), 0);
irq_enable(CONFIG_I2C_3_ERROR_IRQ); irq_enable(DT_I2C_3_ERROR_IRQ);
} }
#endif #endif
@ -358,15 +358,15 @@ static void i2c_stm32_irq_config_func_4(struct device *port);
#endif #endif
static const struct i2c_stm32_config i2c_stm32_cfg_4 = { static const struct i2c_stm32_config i2c_stm32_cfg_4 = {
.i2c = (I2C_TypeDef *)CONFIG_I2C_4_BASE_ADDRESS, .i2c = (I2C_TypeDef *)DT_I2C_4_BASE_ADDRESS,
.pclken = { .pclken = {
.enr = CONFIG_I2C_4_CLOCK_BITS, .enr = DT_I2C_4_CLOCK_BITS,
.bus = CONFIG_I2C_4_CLOCK_BUS, .bus = DT_I2C_4_CLOCK_BUS,
}, },
#ifdef CONFIG_I2C_STM32_INTERRUPT #ifdef CONFIG_I2C_STM32_INTERRUPT
.irq_config_func = i2c_stm32_irq_config_func_4, .irq_config_func = i2c_stm32_irq_config_func_4,
#endif #endif
.bitrate = CONFIG_I2C_4_BITRATE, .bitrate = DT_I2C_4_BITRATE,
}; };
static struct i2c_stm32_data i2c_stm32_dev_data_4; static struct i2c_stm32_data i2c_stm32_dev_data_4;
@ -379,13 +379,13 @@ DEVICE_AND_API_INIT(i2c_stm32_4, CONFIG_I2C_4_NAME, &i2c_stm32_init,
#ifdef CONFIG_I2C_STM32_INTERRUPT #ifdef CONFIG_I2C_STM32_INTERRUPT
static void i2c_stm32_irq_config_func_4(struct device *dev) static void i2c_stm32_irq_config_func_4(struct device *dev)
{ {
IRQ_CONNECT(CONFIG_I2C_4_EVENT_IRQ, CONFIG_I2C_4_EVENT_IRQ_PRI, IRQ_CONNECT(DT_I2C_4_EVENT_IRQ, DT_I2C_4_EVENT_IRQ_PRI,
stm32_i2c_event_isr, DEVICE_GET(i2c_stm32_4), 0); stm32_i2c_event_isr, DEVICE_GET(i2c_stm32_4), 0);
irq_enable(CONFIG_I2C_4_EVENT_IRQ); irq_enable(DT_I2C_4_EVENT_IRQ);
IRQ_CONNECT(CONFIG_I2C_4_ERROR_IRQ, CONFIG_I2C_4_ERROR_IRQ_PRI, IRQ_CONNECT(DT_I2C_4_ERROR_IRQ, DT_I2C_4_ERROR_IRQ_PRI,
stm32_i2c_error_isr, DEVICE_GET(i2c_stm32_4), 0); stm32_i2c_error_isr, DEVICE_GET(i2c_stm32_4), 0);
irq_enable(CONFIG_I2C_4_ERROR_IRQ); irq_enable(DT_I2C_4_ERROR_IRQ);
} }
#endif #endif

16
drivers/i2c/i2c_mcux.c
View file

@ -195,10 +195,10 @@ static const struct i2c_driver_api i2c_mcux_driver_api = {
static void i2c_mcux_config_func_0(struct device *dev); static void i2c_mcux_config_func_0(struct device *dev);
static const struct i2c_mcux_config i2c_mcux_config_0 = { static const struct i2c_mcux_config i2c_mcux_config_0 = {
.base = (I2C_Type *)CONFIG_I2C_MCUX_0_BASE_ADDRESS, .base = (I2C_Type *)DT_I2C_MCUX_0_BASE_ADDRESS,
.clock_source = I2C0_CLK_SRC, .clock_source = I2C0_CLK_SRC,
.irq_config_func = i2c_mcux_config_func_0, .irq_config_func = i2c_mcux_config_func_0,
.bitrate = CONFIG_I2C_MCUX_0_BITRATE, .bitrate = DT_I2C_MCUX_0_BITRATE,
}; };
static struct i2c_mcux_data i2c_mcux_data_0; static struct i2c_mcux_data i2c_mcux_data_0;
@ -212,10 +212,10 @@ static void i2c_mcux_config_func_0(struct device *dev)
{ {
ARG_UNUSED(dev); ARG_UNUSED(dev);
IRQ_CONNECT(CONFIG_I2C_MCUX_0_IRQ, CONFIG_I2C_MCUX_0_IRQ_PRI, IRQ_CONNECT(DT_I2C_MCUX_0_IRQ, DT_I2C_MCUX_0_IRQ_PRI,
i2c_mcux_isr, DEVICE_GET(i2c_mcux_0), 0); i2c_mcux_isr, DEVICE_GET(i2c_mcux_0), 0);
irq_enable(CONFIG_I2C_MCUX_0_IRQ); irq_enable(DT_I2C_MCUX_0_IRQ);
} }
#endif /* CONFIG_I2C_0 */ #endif /* CONFIG_I2C_0 */
@ -223,10 +223,10 @@ static void i2c_mcux_config_func_0(struct device *dev)
static void i2c_mcux_config_func_1(struct device *dev); static void i2c_mcux_config_func_1(struct device *dev);
static const struct i2c_mcux_config i2c_mcux_config_1 = { static const struct i2c_mcux_config i2c_mcux_config_1 = {
.base = (I2C_Type *)CONFIG_I2C_MCUX_1_BASE_ADDRESS, .base = (I2C_Type *)DT_I2C_MCUX_1_BASE_ADDRESS,
.clock_source = I2C1_CLK_SRC, .clock_source = I2C1_CLK_SRC,
.irq_config_func = i2c_mcux_config_func_1, .irq_config_func = i2c_mcux_config_func_1,
.bitrate = CONFIG_I2C_MCUX_1_BITRATE, .bitrate = DT_I2C_MCUX_1_BITRATE,
}; };
static struct i2c_mcux_data i2c_mcux_data_1; static struct i2c_mcux_data i2c_mcux_data_1;
@ -238,9 +238,9 @@ DEVICE_AND_API_INIT(i2c_mcux_1, CONFIG_I2C_1_NAME, &i2c_mcux_init,
static void i2c_mcux_config_func_1(struct device *dev) static void i2c_mcux_config_func_1(struct device *dev)
{ {
IRQ_CONNECT(CONFIG_I2C_MCUX_1_IRQ, CONFIG_I2C_MCUX_1_IRQ_PRI, IRQ_CONNECT(DT_I2C_MCUX_1_IRQ, DT_I2C_MCUX_1_IRQ_PRI,
i2c_mcux_isr, DEVICE_GET(i2c_mcux_1), 0); i2c_mcux_isr, DEVICE_GET(i2c_mcux_1), 0);
irq_enable(CONFIG_I2C_MCUX_1_IRQ); irq_enable(DT_I2C_MCUX_1_IRQ);
} }
#endif /* CONFIG_I2C_1 */ #endif /* CONFIG_I2C_1 */

6
drivers/i2c/i2c_nrfx_twi.c
View file

@ -139,12 +139,12 @@ static int init_twi(struct device *dev, const nrfx_twi_config_t *config)
#define I2C_NRFX_TWI_DEVICE(idx) \ #define I2C_NRFX_TWI_DEVICE(idx) \
static int twi_##idx##_init(struct device *dev) \ static int twi_##idx##_init(struct device *dev) \
{ \ { \
IRQ_CONNECT(CONFIG_I2C_##idx##_IRQ, \ IRQ_CONNECT(DT_I2C_##idx##_IRQ, \
CONFIG_I2C_##idx##_IRQ_PRI, \ CONFIG_I2C_##idx##_IRQ_PRI, \
nrfx_isr, nrfx_twi_##idx##_irq_handler, 0); \ nrfx_isr, nrfx_twi_##idx##_irq_handler, 0); \
const nrfx_twi_config_t config = { \ const nrfx_twi_config_t config = { \
.scl = CONFIG_I2C_##idx##_SCL_PIN, \ .scl = DT_I2C_##idx##_SCL_PIN, \
.sda = CONFIG_I2C_##idx##_SDA_PIN, \ .sda = DT_I2C_##idx##_SDA_PIN, \
.frequency = NRF_TWI_FREQ_100K, \ .frequency = NRF_TWI_FREQ_100K, \
}; \ }; \
return init_twi(dev, &config); \ return init_twi(dev, &config); \

6
drivers/i2c/i2c_nrfx_twim.c
View file

@ -140,12 +140,12 @@ static int init_twim(struct device *dev, const nrfx_twim_config_t *config)
#define I2C_NRFX_TWIM_DEVICE(idx) \ #define I2C_NRFX_TWIM_DEVICE(idx) \
static int twim_##idx##_init(struct device *dev) \ static int twim_##idx##_init(struct device *dev) \
{ \ { \
IRQ_CONNECT(CONFIG_I2C_##idx##_IRQ, \ IRQ_CONNECT(DT_I2C_##idx##_IRQ, \
CONFIG_I2C_##idx##_IRQ_PRI, \ CONFIG_I2C_##idx##_IRQ_PRI, \
nrfx_isr, nrfx_twim_##idx##_irq_handler, 0);\ nrfx_isr, nrfx_twim_##idx##_irq_handler, 0);\
const nrfx_twim_config_t config = { \ const nrfx_twim_config_t config = { \
.scl = CONFIG_I2C_##idx##_SCL_PIN, \ .scl = DT_I2C_##idx##_SCL_PIN, \
.sda = CONFIG_I2C_##idx##_SDA_PIN, \ .sda = DT_I2C_##idx##_SDA_PIN, \
.frequency = NRF_TWIM_FREQ_100K, \ .frequency = NRF_TWIM_FREQ_100K, \
}; \ }; \
return init_twim(dev, &config); \ return init_twim(dev, &config); \

16
drivers/i2c/i2c_qmsi.c
View file

@ -117,7 +117,7 @@ static struct i2c_qmsi_driver_data driver_data_0;
static const struct i2c_qmsi_config_info config_info_0 = { static const struct i2c_qmsi_config_info config_info_0 = {
.instance = QM_I2C_0, .instance = QM_I2C_0,
.bitrate = CONFIG_I2C_0_BITRATE, .bitrate = DT_I2C_0_BITRATE,
.clock_gate = CLK_PERIPH_I2C_M0_REGISTER | CLK_PERIPH_CLK, .clock_gate = CLK_PERIPH_I2C_M0_REGISTER | CLK_PERIPH_CLK,
}; };
@ -133,7 +133,7 @@ static struct i2c_qmsi_driver_data driver_data_1;
static const struct i2c_qmsi_config_info config_info_1 = { static const struct i2c_qmsi_config_info config_info_1 = {
.instance = QM_I2C_1, .instance = QM_I2C_1,
.bitrate = CONFIG_I2C_1_BITRATE, .bitrate = DT_I2C_1_BITRATE,
.clock_gate = CLK_PERIPH_I2C_M1_REGISTER | CLK_PERIPH_CLK, .clock_gate = CLK_PERIPH_I2C_M1_REGISTER | CLK_PERIPH_CLK,
}; };
@ -273,20 +273,20 @@ static int i2c_qmsi_init(struct device *dev)
/* Register interrupt handler, unmask IRQ and route it /* Register interrupt handler, unmask IRQ and route it
* to Lakemont core. * to Lakemont core.
*/ */
IRQ_CONNECT(CONFIG_I2C_0_IRQ, IRQ_CONNECT(DT_I2C_0_IRQ,
CONFIG_I2C_0_IRQ_PRI, qm_i2c_0_irq_isr, NULL, CONFIG_I2C_0_IRQ_PRI, qm_i2c_0_irq_isr, NULL,
CONFIG_I2C_0_IRQ_FLAGS); DT_I2C_0_IRQ_FLAGS);
irq_enable(CONFIG_I2C_0_IRQ); irq_enable(DT_I2C_0_IRQ);
QM_IR_UNMASK_INTERRUPTS( QM_IR_UNMASK_INTERRUPTS(
QM_INTERRUPT_ROUTER->i2c_master_0_int_mask); QM_INTERRUPT_ROUTER->i2c_master_0_int_mask);
break; break;
#ifdef CONFIG_I2C_1 #ifdef CONFIG_I2C_1
case QM_I2C_1: case QM_I2C_1:
IRQ_CONNECT(CONFIG_I2C_1_IRQ, IRQ_CONNECT(DT_I2C_1_IRQ,
CONFIG_I2C_1_IRQ_PRI, qm_i2c_1_irq_isr, NULL, CONFIG_I2C_1_IRQ_PRI, qm_i2c_1_irq_isr, NULL,
CONFIG_I2C_1_IRQ_FLAGS); DT_I2C_1_IRQ_FLAGS);
irq_enable(CONFIG_I2C_1_IRQ); irq_enable(DT_I2C_1_IRQ);
QM_IR_UNMASK_INTERRUPTS( QM_IR_UNMASK_INTERRUPTS(
QM_INTERRUPT_ROUTER->i2c_master_1_int_mask); QM_INTERRUPT_ROUTER->i2c_master_1_int_mask);
break; break;

40
drivers/i2c/i2c_qmsi_ss.c
View file

@ -117,11 +117,11 @@ static void i2c_qmsi_ss_config_irq_0(void);
static const struct i2c_qmsi_ss_config_info config_info_0 = { static const struct i2c_qmsi_ss_config_info config_info_0 = {
.instance = QM_SS_I2C_0, .instance = QM_SS_I2C_0,
.bitrate = CONFIG_I2C_SS_0_BITRATE, .bitrate = DT_I2C_SS_0_BITRATE,
.irq_cfg = i2c_qmsi_ss_config_irq_0, .irq_cfg = i2c_qmsi_ss_config_irq_0,
}; };
DEVICE_DEFINE(i2c_ss_0, CONFIG_I2C_SS_0_NAME, i2c_qmsi_ss_init, DEVICE_DEFINE(i2c_ss_0, DT_I2C_SS_0_NAME, i2c_qmsi_ss_init,
ss_i2c_device_ctrl, &driver_data_0, &config_info_0, POST_KERNEL, ss_i2c_device_ctrl, &driver_data_0, &config_info_0, POST_KERNEL,
CONFIG_KERNEL_INIT_PRIORITY_DEVICE, NULL); CONFIG_KERNEL_INIT_PRIORITY_DEVICE, NULL);
@ -150,19 +150,19 @@ static void i2c_qmsi_ss_config_irq_0(void)
sys_write32(mask, SCSS_REGISTER_BASE + I2C_SS_0_STOP_MASK); sys_write32(mask, SCSS_REGISTER_BASE + I2C_SS_0_STOP_MASK);
/* Connect the IRQs to ISR */ /* Connect the IRQs to ISR */
IRQ_CONNECT(CONFIG_I2C_SS_0_ERR_IRQ, CONFIG_I2C_SS_0_ERR_IRQ_PRI, IRQ_CONNECT(DT_I2C_SS_0_ERR_IRQ, DT_I2C_SS_0_ERR_IRQ_PRI,
qm_ss_i2c_0_error_isr, DEVICE_GET(i2c_ss_0), 0); qm_ss_i2c_0_error_isr, DEVICE_GET(i2c_ss_0), 0);
IRQ_CONNECT(CONFIG_I2C_SS_0_RX_IRQ, CONFIG_I2C_SS_0_RX_IRQ_PRI, IRQ_CONNECT(DT_I2C_SS_0_RX_IRQ, DT_I2C_SS_0_RX_IRQ_PRI,
qm_ss_i2c_0_rx_avail_isr, DEVICE_GET(i2c_ss_0), 0); qm_ss_i2c_0_rx_avail_isr, DEVICE_GET(i2c_ss_0), 0);
IRQ_CONNECT(CONFIG_I2C_SS_0_TX_IRQ, CONFIG_I2C_SS_0_TX_IRQ_PRI, IRQ_CONNECT(DT_I2C_SS_0_TX_IRQ, DT_I2C_SS_0_TX_IRQ_PRI,
qm_ss_i2c_0_tx_req_isr, DEVICE_GET(i2c_ss_0), 0); qm_ss_i2c_0_tx_req_isr, DEVICE_GET(i2c_ss_0), 0);
IRQ_CONNECT(CONFIG_I2C_SS_0_STOP_IRQ, CONFIG_I2C_SS_0_STOP_IRQ_PRI, IRQ_CONNECT(DT_I2C_SS_0_STOP_IRQ, DT_I2C_SS_0_STOP_IRQ_PRI,
qm_ss_i2c_0_stop_det_isr, DEVICE_GET(i2c_ss_0), 0); qm_ss_i2c_0_stop_det_isr, DEVICE_GET(i2c_ss_0), 0);
irq_enable(CONFIG_I2C_SS_0_ERR_IRQ); irq_enable(DT_I2C_SS_0_ERR_IRQ);
irq_enable(CONFIG_I2C_SS_0_RX_IRQ); irq_enable(DT_I2C_SS_0_RX_IRQ);
irq_enable(CONFIG_I2C_SS_0_TX_IRQ); irq_enable(DT_I2C_SS_0_TX_IRQ);
irq_enable(CONFIG_I2C_SS_0_STOP_IRQ); irq_enable(DT_I2C_SS_0_STOP_IRQ);
} }
#endif /* CONFIG_I2C_SS_0 */ #endif /* CONFIG_I2C_SS_0 */
@ -174,11 +174,11 @@ static void i2c_qmsi_ss_config_irq_1(void);
static const struct i2c_qmsi_ss_config_info config_info_1 = { static const struct i2c_qmsi_ss_config_info config_info_1 = {
.instance = QM_SS_I2C_1, .instance = QM_SS_I2C_1,
.bitrate = CONFIG_I2C_SS_1_BITRATE, .bitrate = DT_I2C_SS_1_BITRATE,
.irq_cfg = i2c_qmsi_ss_config_irq_1, .irq_cfg = i2c_qmsi_ss_config_irq_1,
}; };
DEVICE_DEFINE(i2c_ss_1, CONFIG_I2C_SS_1_NAME, i2c_qmsi_ss_init, DEVICE_DEFINE(i2c_ss_1, DT_I2C_SS_1_NAME, i2c_qmsi_ss_init,
ss_i2c_device_ctrl, &driver_data_1, &config_info_1, POST_KERNEL, ss_i2c_device_ctrl, &driver_data_1, &config_info_1, POST_KERNEL,
CONFIG_KERNEL_INIT_PRIORITY_DEVICE, NULL); CONFIG_KERNEL_INIT_PRIORITY_DEVICE, NULL);
@ -207,19 +207,19 @@ static void i2c_qmsi_ss_config_irq_1(void)
sys_write32(mask, SCSS_REGISTER_BASE + I2C_SS_1_STOP_MASK); sys_write32(mask, SCSS_REGISTER_BASE + I2C_SS_1_STOP_MASK);
/* Connect the IRQs to ISR */ /* Connect the IRQs to ISR */
IRQ_CONNECT(CONFIG_I2C_SS_1_ERR_IRQ, CONFIG_I2C_SS_1_ERR_IRQ_PRI, IRQ_CONNECT(DT_I2C_SS_1_ERR_IRQ, DT_I2C_SS_1_ERR_IRQ_PRI,
qm_ss_i2c_1_error_isr, DEVICE_GET(i2c_ss_1), 0); qm_ss_i2c_1_error_isr, DEVICE_GET(i2c_ss_1), 0);
IRQ_CONNECT(CONFIG_I2C_SS_1_RX_IRQ, CONFIG_I2C_SS_1_RX_IRQ_PRI, IRQ_CONNECT(DT_I2C_SS_1_RX_IRQ, DT_I2C_SS_1_RX_IRQ_PRI,
qm_ss_i2c_1_rx_avail_isr, DEVICE_GET(i2c_ss_1), 0); qm_ss_i2c_1_rx_avail_isr, DEVICE_GET(i2c_ss_1), 0);
IRQ_CONNECT(CONFIG_I2C_SS_1_TX_IRQ, CONFIG_I2C_SS_1_TX_IRQ_PRI, IRQ_CONNECT(DT_I2C_SS_1_TX_IRQ, DT_I2C_SS_1_TX_IRQ_PRI,
qm_ss_i2c_1_tx_req_isr, DEVICE_GET(i2c_ss_1), 0); qm_ss_i2c_1_tx_req_isr, DEVICE_GET(i2c_ss_1), 0);
IRQ_CONNECT(CONFIG_I2C_SS_1_STOP_IRQ, CONFIG_I2C_SS_1_STOP_IRQ_PRI, IRQ_CONNECT(DT_I2C_SS_1_STOP_IRQ, DT_I2C_SS_1_STOP_IRQ_PRI,
qm_ss_i2c_1_stop_det_isr, DEVICE_GET(i2c_ss_1), 0); qm_ss_i2c_1_stop_det_isr, DEVICE_GET(i2c_ss_1), 0);
irq_enable(CONFIG_I2C_SS_1_ERR_IRQ); irq_enable(DT_I2C_SS_1_ERR_IRQ);
irq_enable(CONFIG_I2C_SS_1_RX_IRQ); irq_enable(DT_I2C_SS_1_RX_IRQ);
irq_enable(CONFIG_I2C_SS_1_TX_IRQ); irq_enable(DT_I2C_SS_1_TX_IRQ);
irq_enable(CONFIG_I2C_SS_1_STOP_IRQ); irq_enable(DT_I2C_SS_1_STOP_IRQ);
} }
#endif /* CONFIG_I2C_SS_1 */ #endif /* CONFIG_I2C_SS_1 */

20
drivers/i2c/i2c_sam_twi.c
View file

@ -343,20 +343,20 @@ static struct device DEVICE_NAME_GET(i2c0_sam);
static void i2c0_sam_irq_config(void) static void i2c0_sam_irq_config(void)
{ {
IRQ_CONNECT(CONFIG_I2C_0_IRQ, CONFIG_I2C_0_IRQ_PRI, i2c_sam_twi_isr, IRQ_CONNECT(DT_I2C_0_IRQ, CONFIG_I2C_0_IRQ_PRI, i2c_sam_twi_isr,
DEVICE_GET(i2c0_sam), 0); DEVICE_GET(i2c0_sam), 0);
} }
static const struct soc_gpio_pin pins_twi0[] = PINS_TWI0; static const struct soc_gpio_pin pins_twi0[] = PINS_TWI0;
static const struct i2c_sam_twi_dev_cfg i2c0_sam_config = { static const struct i2c_sam_twi_dev_cfg i2c0_sam_config = {
.regs = (Twi *)CONFIG_I2C_0_BASE_ADDRESS, .regs = (Twi *)DT_I2C_0_BASE_ADDRESS,
.irq_config = i2c0_sam_irq_config, .irq_config = i2c0_sam_irq_config,
.periph_id = CONFIG_I2C_0_PERIPHERAL_ID, .periph_id = DT_I2C_0_PERIPHERAL_ID,
.irq_id = CONFIG_I2C_0_IRQ, .irq_id = DT_I2C_0_IRQ,
.pin_list = pins_twi0, .pin_list = pins_twi0,
.pin_list_size = ARRAY_SIZE(pins_twi0), .pin_list_size = ARRAY_SIZE(pins_twi0),
.bitrate = CONFIG_I2C_0_BITRATE, .bitrate = DT_I2C_0_BITRATE,
}; };
static struct i2c_sam_twi_dev_data i2c0_sam_data; static struct i2c_sam_twi_dev_data i2c0_sam_data;
@ -373,20 +373,20 @@ static struct device DEVICE_NAME_GET(i2c1_sam);
static void i2c1_sam_irq_config(void) static void i2c1_sam_irq_config(void)
{ {
IRQ_CONNECT(CONFIG_I2C_1_IRQ, CONFIG_I2C_1_IRQ_PRI, i2c_sam_twi_isr, IRQ_CONNECT(DT_I2C_1_IRQ, CONFIG_I2C_1_IRQ_PRI, i2c_sam_twi_isr,
DEVICE_GET(i2c1_sam), 0); DEVICE_GET(i2c1_sam), 0);
} }
static const struct soc_gpio_pin pins_twi1[] = PINS_TWI1; static const struct soc_gpio_pin pins_twi1[] = PINS_TWI1;
static const struct i2c_sam_twi_dev_cfg i2c1_sam_config = { static const struct i2c_sam_twi_dev_cfg i2c1_sam_config = {
.regs = (Twi *)CONFIG_I2C_1_BASE_ADDRESS, .regs = (Twi *)DT_I2C_1_BASE_ADDRESS,
.irq_config = i2c1_sam_irq_config, .irq_config = i2c1_sam_irq_config,
.periph_id = CONFIG_I2C_1_PERIPHERAL_ID, .periph_id = DT_I2C_1_PERIPHERAL_ID,
.irq_id = CONFIG_I2C_1_IRQ, .irq_id = DT_I2C_1_IRQ,
.pin_list = pins_twi1, .pin_list = pins_twi1,
.pin_list_size = ARRAY_SIZE(pins_twi1), .pin_list_size = ARRAY_SIZE(pins_twi1),
.bitrate = CONFIG_I2C_1_BITRATE, .bitrate = DT_I2C_1_BITRATE,
}; };
static struct i2c_sam_twi_dev_data i2c1_sam_data; static struct i2c_sam_twi_dev_data i2c1_sam_data;

30
drivers/i2c/i2c_sam_twihs.c
View file

@ -330,20 +330,20 @@ static struct device DEVICE_NAME_GET(i2c0_sam);
static void i2c0_sam_irq_config(void) static void i2c0_sam_irq_config(void)
{ {
IRQ_CONNECT(CONFIG_I2C_0_IRQ, CONFIG_I2C_0_IRQ_PRI, i2c_sam_twihs_isr, IRQ_CONNECT(DT_I2C_0_IRQ, CONFIG_I2C_0_IRQ_PRI, i2c_sam_twihs_isr,
DEVICE_GET(i2c0_sam), 0); DEVICE_GET(i2c0_sam), 0);
} }
static const struct soc_gpio_pin pins_twihs0[] = PINS_TWIHS0; static const struct soc_gpio_pin pins_twihs0[] = PINS_TWIHS0;
static const struct i2c_sam_twihs_dev_cfg i2c0_sam_config = { static const struct i2c_sam_twihs_dev_cfg i2c0_sam_config = {
.regs = (Twihs *)CONFIG_I2C_0_BASE_ADDRESS, .regs = (Twihs *)DT_I2C_0_BASE_ADDRESS,
.irq_config = i2c0_sam_irq_config, .irq_config = i2c0_sam_irq_config,
.periph_id = CONFIG_I2C_0_PERIPHERAL_ID, .periph_id = DT_I2C_0_PERIPHERAL_ID,
.irq_id = CONFIG_I2C_0_IRQ, .irq_id = DT_I2C_0_IRQ,
.pin_list = pins_twihs0, .pin_list = pins_twihs0,
.pin_list_size = ARRAY_SIZE(pins_twihs0), .pin_list_size = ARRAY_SIZE(pins_twihs0),
.bitrate = CONFIG_I2C_0_BITRATE, .bitrate = DT_I2C_0_BITRATE,
}; };
static struct i2c_sam_twihs_dev_data i2c0_sam_data; static struct i2c_sam_twihs_dev_data i2c0_sam_data;
@ -360,20 +360,20 @@ static struct device DEVICE_NAME_GET(i2c1_sam);
static void i2c1_sam_irq_config(void) static void i2c1_sam_irq_config(void)
{ {
IRQ_CONNECT(CONFIG_I2C_1_IRQ, CONFIG_I2C_1_IRQ_PRI, i2c_sam_twihs_isr, IRQ_CONNECT(DT_I2C_1_IRQ, CONFIG_I2C_1_IRQ_PRI, i2c_sam_twihs_isr,
DEVICE_GET(i2c1_sam), 0); DEVICE_GET(i2c1_sam), 0);
} }
static const struct soc_gpio_pin pins_twihs1[] = PINS_TWIHS1; static const struct soc_gpio_pin pins_twihs1[] = PINS_TWIHS1;
static const struct i2c_sam_twihs_dev_cfg i2c1_sam_config = { static const struct i2c_sam_twihs_dev_cfg i2c1_sam_config = {
.regs = (Twihs *)CONFIG_I2C_1_BASE_ADDRESS, .regs = (Twihs *)DT_I2C_1_BASE_ADDRESS,
.irq_config = i2c1_sam_irq_config, .irq_config = i2c1_sam_irq_config,
.periph_id = CONFIG_I2C_1_PERIPHERAL_ID, .periph_id = DT_I2C_1_PERIPHERAL_ID,
.irq_id = CONFIG_I2C_1_IRQ, .irq_id = DT_I2C_1_IRQ,
.pin_list = pins_twihs1, .pin_list = pins_twihs1,
.pin_list_size = ARRAY_SIZE(pins_twihs1), .pin_list_size = ARRAY_SIZE(pins_twihs1),
.bitrate = CONFIG_I2C_1_BITRATE, .bitrate = DT_I2C_1_BITRATE,
}; };
static struct i2c_sam_twihs_dev_data i2c1_sam_data; static struct i2c_sam_twihs_dev_data i2c1_sam_data;
@ -390,20 +390,20 @@ static struct device DEVICE_NAME_GET(i2c2_sam);
static void i2c2_sam_irq_config(void) static void i2c2_sam_irq_config(void)
{ {
IRQ_CONNECT(CONFIG_I2C_2_IRQ, CONFIG_I2C_2_IRQ_PRI, i2c_sam_twihs_isr, IRQ_CONNECT(DT_I2C_2_IRQ, CONFIG_I2C_2_IRQ_PRI, i2c_sam_twihs_isr,
DEVICE_GET(i2c2_sam), 0); DEVICE_GET(i2c2_sam), 0);
} }
static const struct soc_gpio_pin pins_twihs2[] = PINS_TWIHS2; static const struct soc_gpio_pin pins_twihs2[] = PINS_TWIHS2;
static const struct i2c_sam_twihs_dev_cfg i2c2_sam_config = { static const struct i2c_sam_twihs_dev_cfg i2c2_sam_config = {
.regs = (Twihs *)CONFIG_I2C_2_BASE_ADDRESS, .regs = (Twihs *)DT_I2C_2_BASE_ADDRESS,
.irq_config = i2c2_sam_irq_config, .irq_config = i2c2_sam_irq_config,
.periph_id = CONFIG_I2C_2_PERIPHERAL_ID, .periph_id = DT_I2C_2_PERIPHERAL_ID,
.irq_id = CONFIG_I2C_2_IRQ, .irq_id = DT_I2C_2_IRQ,
.pin_list = pins_twihs2, .pin_list = pins_twihs2,
.pin_list_size = ARRAY_SIZE(pins_twihs2), .pin_list_size = ARRAY_SIZE(pins_twihs2),
.bitrate = CONFIG_I2C_2_BITRATE, .bitrate = DT_I2C_2_BITRATE,
}; };
static struct i2c_sam_twihs_dev_data i2c2_sam_data; static struct i2c_sam_twihs_dev_data i2c2_sam_data;

2
drivers/i2c/i2c_sbcon.c
View file

@ -113,7 +113,7 @@ static int i2c_sbcon_init(struct device *dev)
static struct i2c_sbcon_context i2c_sbcon_dev_data_##_num; \ static struct i2c_sbcon_context i2c_sbcon_dev_data_##_num; \
\ \
static const struct i2c_sbcon_config i2c_sbcon_dev_cfg_##_num = { \ static const struct i2c_sbcon_config i2c_sbcon_dev_cfg_##_num = { \
.sbcon = (void *)I2C_SBCON_##_num##_BASE_ADDR, \ .sbcon = (void *)DT_I2C_SBCON_##_num##_BASE_ADDR, \
}; \ }; \
\ \
DEVICE_INIT(i2c_sbcon_##_num, CONFIG_I2C_SBCON_##_num##_NAME, \ DEVICE_INIT(i2c_sbcon_##_num, CONFIG_I2C_SBCON_##_num##_NAME, \

60
drivers/i2s/i2s_ll_stm32.c
View file

@ -803,10 +803,10 @@ static struct device DEVICE_NAME_GET(i2s_stm32_1);
static void i2s_stm32_irq_config_func_1(struct device *dev); static void i2s_stm32_irq_config_func_1(struct device *dev);
static const struct i2s_stm32_cfg i2s_stm32_config_1 = { static const struct i2s_stm32_cfg i2s_stm32_config_1 = {
.i2s = (SPI_TypeDef *) CONFIG_I2S_1_BASE_ADDRESS, .i2s = (SPI_TypeDef *) DT_I2S_1_BASE_ADDRESS,
.pclken = { .pclken = {
.enr = CONFIG_I2S_1_CLOCK_BITS, .enr = DT_I2S_1_CLOCK_BITS,
.bus = CONFIG_I2S_1_CLOCK_BUS, .bus = DT_I2S_1_CLOCK_BUS,
}, },
.i2s_clk_sel = CLK_SEL_2, .i2s_clk_sel = CLK_SEL_2,
.irq_config = i2s_stm32_irq_config_func_1, .irq_config = i2s_stm32_irq_config_func_1,
@ -854,15 +854,15 @@ static struct i2s_stm32_data i2s_stm32_data_1 = {
.mem_block_queue.len = ARRAY_SIZE(tx_1_ring_buf), .mem_block_queue.len = ARRAY_SIZE(tx_1_ring_buf),
}, },
}; };
DEVICE_AND_API_INIT(i2s_stm32_1, CONFIG_I2S_1_NAME, &i2s_stm32_initialize, DEVICE_AND_API_INIT(i2s_stm32_1, DT_I2S_1_NAME, &i2s_stm32_initialize,
&i2s_stm32_data_1, &i2s_stm32_config_1, POST_KERNEL, &i2s_stm32_data_1, &i2s_stm32_config_1, POST_KERNEL,
CONFIG_I2S_INIT_PRIORITY, &i2s_stm32_driver_api); CONFIG_I2S_INIT_PRIORITY, &i2s_stm32_driver_api);
static void i2s_stm32_irq_config_func_1(struct device *dev) static void i2s_stm32_irq_config_func_1(struct device *dev)
{ {
IRQ_CONNECT(CONFIG_I2S_1_IRQ, CONFIG_I2S_1_IRQ_PRI, i2s_stm32_isr, IRQ_CONNECT(DT_I2S_1_IRQ, DT_I2S_1_IRQ_PRI, i2s_stm32_isr,
DEVICE_GET(i2s_stm32_1), 0); DEVICE_GET(i2s_stm32_1), 0);
irq_enable(CONFIG_I2S_1_IRQ); irq_enable(DT_I2S_1_IRQ);
} }
#endif /* CONFIG_I2S_1 */ #endif /* CONFIG_I2S_1 */
@ -873,10 +873,10 @@ static struct device DEVICE_NAME_GET(i2s_stm32_2);
static void i2s_stm32_irq_config_func_2(struct device *dev); static void i2s_stm32_irq_config_func_2(struct device *dev);
static const struct i2s_stm32_cfg i2s_stm32_config_2 = { static const struct i2s_stm32_cfg i2s_stm32_config_2 = {
.i2s = (SPI_TypeDef *) CONFIG_I2S_2_BASE_ADDRESS, .i2s = (SPI_TypeDef *) DT_I2S_2_BASE_ADDRESS,
.pclken = { .pclken = {
.enr = CONFIG_I2S_2_CLOCK_BITS, .enr = DT_I2S_2_CLOCK_BITS,
.bus = CONFIG_I2S_2_CLOCK_BUS, .bus = DT_I2S_2_CLOCK_BUS,
}, },
.i2s_clk_sel = CLK_SEL_1, .i2s_clk_sel = CLK_SEL_1,
.irq_config = i2s_stm32_irq_config_func_2, .irq_config = i2s_stm32_irq_config_func_2,
@ -924,15 +924,15 @@ static struct i2s_stm32_data i2s_stm32_data_2 = {
.mem_block_queue.len = ARRAY_SIZE(tx_2_ring_buf), .mem_block_queue.len = ARRAY_SIZE(tx_2_ring_buf),
}, },
}; };
DEVICE_AND_API_INIT(i2s_stm32_2, CONFIG_I2S_2_NAME, &i2s_stm32_initialize, DEVICE_AND_API_INIT(i2s_stm32_2, DT_I2S_2_NAME, &i2s_stm32_initialize,
&i2s_stm32_data_2, &i2s_stm32_config_2, POST_KERNEL, &i2s_stm32_data_2, &i2s_stm32_config_2, POST_KERNEL,
CONFIG_I2S_INIT_PRIORITY, &i2s_stm32_driver_api); CONFIG_I2S_INIT_PRIORITY, &i2s_stm32_driver_api);
static void i2s_stm32_irq_config_func_2(struct device *dev) static void i2s_stm32_irq_config_func_2(struct device *dev)
{ {
IRQ_CONNECT(CONFIG_I2S_2_IRQ, CONFIG_I2S_2_IRQ_PRI, i2s_stm32_isr, IRQ_CONNECT(DT_I2S_2_IRQ, DT_I2S_2_IRQ_PRI, i2s_stm32_isr,
DEVICE_GET(i2s_stm32_2), 0); DEVICE_GET(i2s_stm32_2), 0);
irq_enable(CONFIG_I2S_2_IRQ); irq_enable(DT_I2S_2_IRQ);
} }
#endif /* CONFIG_I2S_2 */ #endif /* CONFIG_I2S_2 */
@ -943,10 +943,10 @@ static struct device DEVICE_NAME_GET(i2s_stm32_3);
static void i2s_stm32_irq_config_func_3(struct device *dev); static void i2s_stm32_irq_config_func_3(struct device *dev);
static const struct i2s_stm32_cfg i2s_stm32_config_3 = { static const struct i2s_stm32_cfg i2s_stm32_config_3 = {
.i2s = (SPI_TypeDef *) CONFIG_I2S_3_BASE_ADDRESS, .i2s = (SPI_TypeDef *) DT_I2S_3_BASE_ADDRESS,
.pclken = { .pclken = {
.enr = CONFIG_I2S_3_CLOCK_BITS, .enr = DT_I2S_3_CLOCK_BITS,
.bus = CONFIG_I2S_3_CLOCK_BUS, .bus = DT_I2S_3_CLOCK_BUS,
}, },
.i2s_clk_sel = CLK_SEL_1, .i2s_clk_sel = CLK_SEL_1,
.irq_config = i2s_stm32_irq_config_func_3, .irq_config = i2s_stm32_irq_config_func_3,
@ -994,15 +994,15 @@ static struct i2s_stm32_data i2s_stm32_data_3 = {
.mem_block_queue.len = ARRAY_SIZE(tx_3_ring_buf), .mem_block_queue.len = ARRAY_SIZE(tx_3_ring_buf),
}, },
}; };
DEVICE_AND_API_INIT(i2s_stm32_3, CONFIG_I2S_3_NAME, &i2s_stm32_initialize, DEVICE_AND_API_INIT(i2s_stm32_3, DT_I2S_3_NAME, &i2s_stm32_initialize,
&i2s_stm32_data_3, &i2s_stm32_config_3, POST_KERNEL, &i2s_stm32_data_3, &i2s_stm32_config_3, POST_KERNEL,
CONFIG_I2S_INIT_PRIORITY, &i2s_stm32_driver_api); CONFIG_I2S_INIT_PRIORITY, &i2s_stm32_driver_api);
static void i2s_stm32_irq_config_func_3(struct device *dev) static void i2s_stm32_irq_config_func_3(struct device *dev)
{ {
IRQ_CONNECT(CONFIG_I2S_3_IRQ, CONFIG_I2S_3_IRQ_PRI, i2s_stm32_isr, IRQ_CONNECT(DT_I2S_3_IRQ, DT_I2S_3_IRQ_PRI, i2s_stm32_isr,
DEVICE_GET(i2s_stm32_3), 0); DEVICE_GET(i2s_stm32_3), 0);
irq_enable(CONFIG_I2S_3_IRQ); irq_enable(DT_I2S_3_IRQ);
} }
#endif /* CONFIG_I2S_3 */ #endif /* CONFIG_I2S_3 */
@ -1013,10 +1013,10 @@ static struct device DEVICE_NAME_GET(i2s_stm32_4);
static void i2s_stm32_irq_config_func_4(struct device *dev); static void i2s_stm32_irq_config_func_4(struct device *dev);
static const struct i2s_stm32_cfg i2s_stm32_config_4 = { static const struct i2s_stm32_cfg i2s_stm32_config_4 = {
.i2s = (SPI_TypeDef *) CONFIG_I2S_4_BASE_ADDRESS, .i2s = (SPI_TypeDef *) DT_I2S_4_BASE_ADDRESS,
.pclken = { .pclken = {
.enr = CONFIG_I2S_4_CLOCK_BITS, .enr = DT_I2S_4_CLOCK_BITS,
.bus = CONFIG_I2S_4_CLOCK_BUS, .bus = DT_I2S_4_CLOCK_BUS,
}, },
.i2s_clk_sel = CLK_SEL_2, .i2s_clk_sel = CLK_SEL_2,
.irq_config = i2s_stm32_irq_config_func_4, .irq_config = i2s_stm32_irq_config_func_4,
@ -1064,15 +1064,15 @@ static struct i2s_stm32_data i2s_stm32_data_4 = {
.mem_block_queue.len = ARRAY_SIZE(tx_4_ring_buf), .mem_block_queue.len = ARRAY_SIZE(tx_4_ring_buf),
}, },
}; };
DEVICE_AND_API_INIT(i2s_stm32_4, CONFIG_I2S_4_NAME, &i2s_stm32_initialize, DEVICE_AND_API_INIT(i2s_stm32_4, DT_I2S_4_NAME, &i2s_stm32_initialize,
&i2s_stm32_data_4, &i2s_stm32_config_4, POST_KERNEL, &i2s_stm32_data_4, &i2s_stm32_config_4, POST_KERNEL,
CONFIG_I2S_INIT_PRIORITY, &i2s_stm32_driver_api); CONFIG_I2S_INIT_PRIORITY, &i2s_stm32_driver_api);
static void i2s_stm32_irq_config_func_4(struct device *dev) static void i2s_stm32_irq_config_func_4(struct device *dev)
{ {
IRQ_CONNECT(CONFIG_I2S_4_IRQ, CONFIG_I2S_4_IRQ_PRI, i2s_stm32_isr, IRQ_CONNECT(DT_I2S_4_IRQ, DT_I2S_4_IRQ_PRI, i2s_stm32_isr,
DEVICE_GET(i2s_stm32_4), 0); DEVICE_GET(i2s_stm32_4), 0);
irq_enable(CONFIG_I2S_4_IRQ); irq_enable(DT_I2S_4_IRQ);
} }
#endif /* CONFIG_I2S_4 */ #endif /* CONFIG_I2S_4 */
@ -1083,10 +1083,10 @@ static struct device DEVICE_NAME_GET(i2s_stm32_5);
static void i2s_stm32_irq_config_func_5(struct device *dev); static void i2s_stm32_irq_config_func_5(struct device *dev);
static const struct i2s_stm32_cfg i2s_stm32_config_5 = { static const struct i2s_stm32_cfg i2s_stm32_config_5 = {
.i2s = (SPI_TypeDef *) CONFIG_I2S_5_BASE_ADDRESS, .i2s = (SPI_TypeDef *) DT_I2S_5_BASE_ADDRESS,
.pclken = { .pclken = {
.enr = CONFIG_I2S_5_CLOCK_BITS, .enr = DT_I2S_5_CLOCK_BITS,
.bus = CONFIG_I2S_5_CLOCK_BUS, .bus = DT_I2S_5_CLOCK_BUS,
}, },
.i2s_clk_sel = CLK_SEL_2, .i2s_clk_sel = CLK_SEL_2,
.irq_config = i2s_stm32_irq_config_func_5, .irq_config = i2s_stm32_irq_config_func_5,
@ -1134,15 +1134,15 @@ static struct i2s_stm32_data i2s_stm32_data_5 = {
.mem_block_queue.len = ARRAY_SIZE(tx_5_ring_buf), .mem_block_queue.len = ARRAY_SIZE(tx_5_ring_buf),
}, },
}; };
DEVICE_AND_API_INIT(i2s_stm32_5, CONFIG_I2S_5_NAME, &i2s_stm32_initialize, DEVICE_AND_API_INIT(i2s_stm32_5, DT_I2S_5_NAME, &i2s_stm32_initialize,
&i2s_stm32_data_5, &i2s_stm32_config_5, POST_KERNEL, &i2s_stm32_data_5, &i2s_stm32_config_5, POST_KERNEL,
CONFIG_I2S_INIT_PRIORITY, &i2s_stm32_driver_api); CONFIG_I2S_INIT_PRIORITY, &i2s_stm32_driver_api);
static void i2s_stm32_irq_config_func_5(struct device *dev) static void i2s_stm32_irq_config_func_5(struct device *dev)
{ {
IRQ_CONNECT(CONFIG_I2S_5_IRQ, CONFIG_I2S_5_IRQ_PRI, i2s_stm32_isr, IRQ_CONNECT(DT_I2S_5_IRQ, DT_I2S_5_IRQ_PRI, i2s_stm32_isr,
DEVICE_GET(i2s_stm32_5), 0); DEVICE_GET(i2s_stm32_5), 0);
irq_enable(CONFIG_I2S_5_IRQ); irq_enable(DT_I2S_5_IRQ);
} }
#endif /* CONFIG_I2S_5 */ #endif /* CONFIG_I2S_5 */

32
drivers/interrupt_controller/cavs_ictl.c
View file

@ -89,13 +89,13 @@ static int cavs_ictl_0_initialize(struct device *port)
static void cavs_config_0_irq(struct device *port); static void cavs_config_0_irq(struct device *port);
static const struct cavs_ictl_config cavs_config_0 = { static const struct cavs_ictl_config cavs_config_0 = {
.irq_num = CAVS_ICTL_0_IRQ, .irq_num = DT_CAVS_ICTL_0_IRQ,
.isr_table_offset = CONFIG_CAVS_ISR_TBL_OFFSET, .isr_table_offset = CONFIG_CAVS_ISR_TBL_OFFSET,
.config_func = cavs_config_0_irq, .config_func = cavs_config_0_irq,
}; };
static struct cavs_ictl_runtime cavs_0_runtime = { static struct cavs_ictl_runtime cavs_0_runtime = {
.base_addr = CAVS_ICTL_BASE_ADDR, .base_addr = DT_CAVS_ICTL_BASE_ADDR,
}; };
DEVICE_AND_API_INIT(cavs_ictl_0, CONFIG_CAVS_ICTL_0_NAME, DEVICE_AND_API_INIT(cavs_ictl_0, CONFIG_CAVS_ICTL_0_NAME,
@ -104,8 +104,8 @@ DEVICE_AND_API_INIT(cavs_ictl_0, CONFIG_CAVS_ICTL_0_NAME,
static void cavs_config_0_irq(struct device *port) static void cavs_config_0_irq(struct device *port)
{ {
IRQ_CONNECT(CAVS_ICTL_0_IRQ, CONFIG_CAVS_ICTL_0_IRQ_PRI, cavs_ictl_isr, IRQ_CONNECT(DT_CAVS_ICTL_0_IRQ, DT_CAVS_ICTL_0_IRQ_PRI, cavs_ictl_isr,
DEVICE_GET(cavs_ictl_0), CAVS_ICTL_0_IRQ_FLAGS); DEVICE_GET(cavs_ictl_0), DT_CAVS_ICTL_0_IRQ_FLAGS);
} }
static int cavs_ictl_1_initialize(struct device *port) static int cavs_ictl_1_initialize(struct device *port)
@ -116,14 +116,14 @@ static int cavs_ictl_1_initialize(struct device *port)
static void cavs_config_1_irq(struct device *port); static void cavs_config_1_irq(struct device *port);
static const struct cavs_ictl_config cavs_config_1 = { static const struct cavs_ictl_config cavs_config_1 = {
.irq_num = CAVS_ICTL_1_IRQ, .irq_num = DT_CAVS_ICTL_1_IRQ,
.isr_table_offset = CONFIG_CAVS_ISR_TBL_OFFSET + .isr_table_offset = CONFIG_CAVS_ISR_TBL_OFFSET +
CONFIG_MAX_IRQ_PER_AGGREGATOR, CONFIG_MAX_IRQ_PER_AGGREGATOR,
.config_func = cavs_config_1_irq, .config_func = cavs_config_1_irq,
}; };
static struct cavs_ictl_runtime cavs_1_runtime = { static struct cavs_ictl_runtime cavs_1_runtime = {
.base_addr = CAVS_ICTL_BASE_ADDR + sizeof(struct cavs_registers), .base_addr = DT_CAVS_ICTL_BASE_ADDR + sizeof(struct cavs_registers),
}; };
DEVICE_AND_API_INIT(cavs_ictl_1, CONFIG_CAVS_ICTL_1_NAME, DEVICE_AND_API_INIT(cavs_ictl_1, CONFIG_CAVS_ICTL_1_NAME,
@ -132,8 +132,8 @@ DEVICE_AND_API_INIT(cavs_ictl_1, CONFIG_CAVS_ICTL_1_NAME,
static void cavs_config_1_irq(struct device *port) static void cavs_config_1_irq(struct device *port)
{ {
IRQ_CONNECT(CAVS_ICTL_1_IRQ, CONFIG_CAVS_ICTL_1_IRQ_PRI, cavs_ictl_isr, IRQ_CONNECT(DT_CAVS_ICTL_1_IRQ, DT_CAVS_ICTL_1_IRQ_PRI, cavs_ictl_isr,
DEVICE_GET(cavs_ictl_1), CAVS_ICTL_1_IRQ_FLAGS); DEVICE_GET(cavs_ictl_1), DT_CAVS_ICTL_1_IRQ_FLAGS);
} }
static int cavs_ictl_2_initialize(struct device *port) static int cavs_ictl_2_initialize(struct device *port)
@ -144,14 +144,14 @@ static int cavs_ictl_2_initialize(struct device *port)
static void cavs_config_2_irq(struct device *port); static void cavs_config_2_irq(struct device *port);
static const struct cavs_ictl_config cavs_config_2 = { static const struct cavs_ictl_config cavs_config_2 = {
.irq_num = CAVS_ICTL_2_IRQ, .irq_num = DT_CAVS_ICTL_2_IRQ,
.isr_table_offset = CONFIG_CAVS_ISR_TBL_OFFSET + .isr_table_offset = CONFIG_CAVS_ISR_TBL_OFFSET +
CONFIG_MAX_IRQ_PER_AGGREGATOR * 2, CONFIG_MAX_IRQ_PER_AGGREGATOR * 2,
.config_func = cavs_config_2_irq, .config_func = cavs_config_2_irq,
}; };
static struct cavs_ictl_runtime cavs_2_runtime = { static struct cavs_ictl_runtime cavs_2_runtime = {
.base_addr = CAVS_ICTL_BASE_ADDR + sizeof(struct cavs_registers) * 2, .base_addr = DT_CAVS_ICTL_BASE_ADDR + sizeof(struct cavs_registers) * 2,
}; };
DEVICE_AND_API_INIT(cavs_ictl_2, CONFIG_CAVS_ICTL_2_NAME, DEVICE_AND_API_INIT(cavs_ictl_2, CONFIG_CAVS_ICTL_2_NAME,
@ -160,8 +160,8 @@ DEVICE_AND_API_INIT(cavs_ictl_2, CONFIG_CAVS_ICTL_2_NAME,
static void cavs_config_2_irq(struct device *port) static void cavs_config_2_irq(struct device *port)
{ {
IRQ_CONNECT(CAVS_ICTL_2_IRQ, CONFIG_CAVS_ICTL_2_IRQ_PRI, cavs_ictl_isr, IRQ_CONNECT(DT_CAVS_ICTL_2_IRQ, DT_CAVS_ICTL_2_IRQ_PRI, cavs_ictl_isr,
DEVICE_GET(cavs_ictl_2), CAVS_ICTL_2_IRQ_FLAGS); DEVICE_GET(cavs_ictl_2), DT_CAVS_ICTL_2_IRQ_FLAGS);
} }
static int cavs_ictl_3_initialize(struct device *port) static int cavs_ictl_3_initialize(struct device *port)
@ -172,14 +172,14 @@ static int cavs_ictl_3_initialize(struct device *port)
static void cavs_config_3_irq(struct device *port); static void cavs_config_3_irq(struct device *port);
static const struct cavs_ictl_config cavs_config_3 = { static const struct cavs_ictl_config cavs_config_3 = {
.irq_num = CAVS_ICTL_3_IRQ, .irq_num = DT_CAVS_ICTL_3_IRQ,
.isr_table_offset = CONFIG_CAVS_ISR_TBL_OFFSET + .isr_table_offset = CONFIG_CAVS_ISR_TBL_OFFSET +
CONFIG_MAX_IRQ_PER_AGGREGATOR*3, CONFIG_MAX_IRQ_PER_AGGREGATOR*3,
.config_func = cavs_config_3_irq, .config_func = cavs_config_3_irq,
}; };
static struct cavs_ictl_runtime cavs_3_runtime = { static struct cavs_ictl_runtime cavs_3_runtime = {
.base_addr = CAVS_ICTL_BASE_ADDR + sizeof(struct cavs_registers) * 3, .base_addr = DT_CAVS_ICTL_BASE_ADDR + sizeof(struct cavs_registers) * 3,
}; };
DEVICE_AND_API_INIT(cavs_ictl_3, CONFIG_CAVS_ICTL_3_NAME, DEVICE_AND_API_INIT(cavs_ictl_3, CONFIG_CAVS_ICTL_3_NAME,
@ -188,6 +188,6 @@ DEVICE_AND_API_INIT(cavs_ictl_3, CONFIG_CAVS_ICTL_3_NAME,
static void cavs_config_3_irq(struct device *port) static void cavs_config_3_irq(struct device *port)
{ {
IRQ_CONNECT(CAVS_ICTL_3_IRQ, CONFIG_CAVS_ICTL_3_IRQ_PRI, cavs_ictl_isr, IRQ_CONNECT(DT_CAVS_ICTL_3_IRQ, DT_CAVS_ICTL_3_IRQ_PRI, cavs_ictl_isr,
DEVICE_GET(cavs_ictl_3), CAVS_ICTL_3_IRQ_FLAGS); DEVICE_GET(cavs_ictl_3), DT_CAVS_ICTL_3_IRQ_FLAGS);
} }

8
drivers/interrupt_controller/dw_ictl.c
View file

@ -116,14 +116,14 @@ static inline unsigned int dw_ictl_intr_get_state(struct device *dev)
static void dw_ictl_config_irq(struct device *port); static void dw_ictl_config_irq(struct device *port);
static const struct dw_ictl_config dw_config = { static const struct dw_ictl_config dw_config = {
.irq_num = DW_ICTL_IRQ, .irq_num = DT_DW_ICTL_IRQ,
.numirqs = DW_ICTL_NUM_IRQS, .numirqs = DW_ICTL_NUM_IRQS,
.isr_table_offset = CONFIG_DW_ISR_TBL_OFFSET, .isr_table_offset = CONFIG_DW_ISR_TBL_OFFSET,
.config_func = dw_ictl_config_irq, .config_func = dw_ictl_config_irq,
}; };
static struct dw_ictl_runtime dw_runtime = { static struct dw_ictl_runtime dw_runtime = {
.base_addr = DW_ICTL_BASE_ADDR, .base_addr = DT_DW_ICTL_BASE_ADDR,
}; };
static const struct irq_next_level_api dw_ictl_apis = { static const struct irq_next_level_api dw_ictl_apis = {
@ -138,6 +138,6 @@ DEVICE_AND_API_INIT(dw_ictl, CONFIG_DW_ICTL_NAME, dw_ictl_initialize,
static void dw_ictl_config_irq(struct device *port) static void dw_ictl_config_irq(struct device *port)
{ {
IRQ_CONNECT(DW_ICTL_IRQ, CONFIG_DW_ICTL_IRQ_PRI, dw_ictl_isr, IRQ_CONNECT(DT_DW_ICTL_IRQ, DT_DW_ICTL_IRQ_PRI, dw_ictl_isr,
DEVICE_GET(dw_ictl), DW_ICTL_IRQ_FLAGS); DEVICE_GET(dw_ictl), DT_DW_ICTL_IRQ_FLAGS);
} }

8
drivers/interrupt_controller/ioapic_intr.c
View file

@ -328,8 +328,8 @@ static u32_t __IoApicGet(s32_t offset)
key = irq_lock(); key = irq_lock();
*((volatile u32_t *) *((volatile u32_t *)
(CONFIG_IOAPIC_BASE_ADDRESS + IOAPIC_IND)) = (char)offset; (DT_IOAPIC_BASE_ADDRESS + IOAPIC_IND)) = (char)offset;
value = *((volatile u32_t *)(CONFIG_IOAPIC_BASE_ADDRESS + IOAPIC_DATA)); value = *((volatile u32_t *)(DT_IOAPIC_BASE_ADDRESS + IOAPIC_DATA));
irq_unlock(key); irq_unlock(key);
@ -354,8 +354,8 @@ static void __IoApicSet(s32_t offset, u32_t value)
key = irq_lock(); key = irq_lock();
*(volatile u32_t *)(CONFIG_IOAPIC_BASE_ADDRESS + IOAPIC_IND) = (char)offset; *(volatile u32_t *)(DT_IOAPIC_BASE_ADDRESS + IOAPIC_IND) = (char)offset;
*((volatile u32_t *)(CONFIG_IOAPIC_BASE_ADDRESS + IOAPIC_DATA)) = value; *((volatile u32_t *)(DT_IOAPIC_BASE_ADDRESS + IOAPIC_DATA)) = value;
irq_unlock(key); irq_unlock(key);
} }

10
drivers/ipm/ipm_mcux.c
View file

@ -154,13 +154,13 @@ static const struct ipm_driver_api mcux_mailbox_driver_api = {
static void mcux_mailbox_config_func_0(struct device *dev); static void mcux_mailbox_config_func_0(struct device *dev);
static const struct mcux_mailbox_config mcux_mailbox_0_config = { static const struct mcux_mailbox_config mcux_mailbox_0_config = {
.base = (MAILBOX_Type *)CONFIG_MAILBOX_MCUX_MAILBOX_0_BASE_ADDRESS, .base = (MAILBOX_Type *)DT_MAILBOX_MCUX_MAILBOX_0_BASE_ADDRESS,
.irq_config_func = mcux_mailbox_config_func_0, .irq_config_func = mcux_mailbox_config_func_0,
}; };
static struct mcux_mailbox_data mcux_mailbox_0_data; static struct mcux_mailbox_data mcux_mailbox_0_data;
DEVICE_AND_API_INIT(mailbox_0, CONFIG_MAILBOX_MCUX_MAILBOX_0_NAME, DEVICE_AND_API_INIT(mailbox_0, DT_MAILBOX_MCUX_MAILBOX_0_NAME,
&mcux_mailbox_init, &mcux_mailbox_init,
&mcux_mailbox_0_data, &mcux_mailbox_0_config, &mcux_mailbox_0_data, &mcux_mailbox_0_config,
PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
@ -169,9 +169,9 @@ DEVICE_AND_API_INIT(mailbox_0, CONFIG_MAILBOX_MCUX_MAILBOX_0_NAME,
static void mcux_mailbox_config_func_0(struct device *dev) static void mcux_mailbox_config_func_0(struct device *dev)
{ {
IRQ_CONNECT(CONFIG_MAILBOX_MCUX_MAILBOX_0_IRQ, IRQ_CONNECT(DT_MAILBOX_MCUX_MAILBOX_0_IRQ,
CONFIG_MAILBOX_MCUX_MAILBOX_0_IRQ_PRI, DT_MAILBOX_MCUX_MAILBOX_0_IRQ_PRI,
mcux_mailbox_isr, DEVICE_GET(mailbox_0), 0); mcux_mailbox_isr, DEVICE_GET(mailbox_0), 0);
irq_enable(CONFIG_MAILBOX_MCUX_MAILBOX_0_IRQ); irq_enable(DT_MAILBOX_MCUX_MAILBOX_0_IRQ);
} }

32
drivers/modem/wncm14a2a.c
View file

@ -54,7 +54,7 @@ enum mdm_control_pins {
MDM_KEEP_AWAKE, MDM_KEEP_AWAKE,
MDM_RESET, MDM_RESET,
SHLD_3V3_1V8_SIG_TRANS_ENA, SHLD_3V3_1V8_SIG_TRANS_ENA,
#ifdef CONFIG_WNCM14A2A_GPIO_MDM_SEND_OK_PIN #ifdef DT_WNCM14A2A_GPIO_MDM_SEND_OK_PIN
MDM_SEND_OK, MDM_SEND_OK,
#endif #endif
MAX_MDM_CONTROL_PINS, MAX_MDM_CONTROL_PINS,
@ -62,33 +62,33 @@ enum mdm_control_pins {
static const struct mdm_control_pinconfig pinconfig[] = { static const struct mdm_control_pinconfig pinconfig[] = {
/* MDM_BOOT_MODE_SEL */ /* MDM_BOOT_MODE_SEL */
PINCONFIG(CONFIG_WNCM14A2A_GPIO_MDM_BOOT_MODE_SEL_NAME, PINCONFIG(DT_WNCM14A2A_GPIO_MDM_BOOT_MODE_SEL_NAME,
CONFIG_WNCM14A2A_GPIO_MDM_BOOT_MODE_SEL_PIN), DT_WNCM14A2A_GPIO_MDM_BOOT_MODE_SEL_PIN),
/* MDM_POWER */ /* MDM_POWER */
PINCONFIG(CONFIG_WNCM14A2A_GPIO_MDM_POWER_NAME, PINCONFIG(DT_WNCM14A2A_GPIO_MDM_POWER_NAME,
CONFIG_WNCM14A2A_GPIO_MDM_POWER_PIN), DT_WNCM14A2A_GPIO_MDM_POWER_PIN),
/* MDM_KEEP_AWAKE */ /* MDM_KEEP_AWAKE */
PINCONFIG(CONFIG_WNCM14A2A_GPIO_MDM_KEEP_AWAKE_NAME, PINCONFIG(DT_WNCM14A2A_GPIO_MDM_KEEP_AWAKE_NAME,
CONFIG_WNCM14A2A_GPIO_MDM_KEEP_AWAKE_PIN), DT_WNCM14A2A_GPIO_MDM_KEEP_AWAKE_PIN),
/* MDM_RESET */ /* MDM_RESET */
PINCONFIG(CONFIG_WNCM14A2A_GPIO_MDM_RESET_NAME, PINCONFIG(DT_WNCM14A2A_GPIO_MDM_RESET_NAME,
CONFIG_WNCM14A2A_GPIO_MDM_RESET_PIN), DT_WNCM14A2A_GPIO_MDM_RESET_PIN),
/* SHLD_3V3_1V8_SIG_TRANS_ENA */ /* SHLD_3V3_1V8_SIG_TRANS_ENA */
PINCONFIG(CONFIG_WNCM14A2A_GPIO_MDM_SHLD_TRANS_ENA_NAME, PINCONFIG(DT_WNCM14A2A_GPIO_MDM_SHLD_TRANS_ENA_NAME,
CONFIG_WNCM14A2A_GPIO_MDM_SHLD_TRANS_ENA_PIN), DT_WNCM14A2A_GPIO_MDM_SHLD_TRANS_ENA_PIN),
#ifdef CONFIG_WNCM14A2A_GPIO_MDM_SEND_OK_PIN #ifdef DT_WNCM14A2A_GPIO_MDM_SEND_OK_PIN
/* MDM_SEND_OK */ /* MDM_SEND_OK */
PINCONFIG(CONFIG_WNCM14A2A_GPIO_MDM_SEND_OK_NAME, PINCONFIG(DT_WNCM14A2A_GPIO_MDM_SEND_OK_NAME,
CONFIG_WNCM14A2A_GPIO_MDM_SEND_OK_PIN), DT_WNCM14A2A_GPIO_MDM_SEND_OK_PIN),
#endif #endif
}; };
#define MDM_UART_DEV_NAME CONFIG_WNCM14A2A_UART_DRV_NAME #define MDM_UART_DEV_NAME DT_WNCM14A2A_UART_DRV_NAME
#define MDM_BOOT_MODE_SPECIAL 0 #define MDM_BOOT_MODE_SPECIAL 0
#define MDM_BOOT_MODE_NORMAL 1 #define MDM_BOOT_MODE_NORMAL 1
@ -1256,7 +1256,7 @@ static int modem_pin_init(void)
LOG_DBG("MDM_KEEP_AWAKE_PIN -> ENABLED"); LOG_DBG("MDM_KEEP_AWAKE_PIN -> ENABLED");
gpio_pin_write(ictx.gpio_port_dev[MDM_KEEP_AWAKE], gpio_pin_write(ictx.gpio_port_dev[MDM_KEEP_AWAKE],
pinconfig[MDM_KEEP_AWAKE].pin, MDM_KEEP_AWAKE_ENABLED); pinconfig[MDM_KEEP_AWAKE].pin, MDM_KEEP_AWAKE_ENABLED);
#ifdef CONFIG_WNCM14A2A_GPIO_MDM_SEND_OK_PIN #ifdef DT_WNCM14A2A_GPIO_MDM_SEND_OK_PIN
LOG_DBG("MDM_SEND_OK_PIN -> ENABLED"); LOG_DBG("MDM_SEND_OK_PIN -> ENABLED");
gpio_pin_write(ictx.gpio_port_dev[MDM_SEND_OK], gpio_pin_write(ictx.gpio_port_dev[MDM_SEND_OK],
pinconfig[MDM_SEND_OK].pin, MDM_SEND_OK_ENABLED); pinconfig[MDM_SEND_OK].pin, MDM_SEND_OK_ENABLED);

4
drivers/neural_net/intel_gna.c
View file

@ -141,8 +141,8 @@ static int intel_gna_setup_page_table(void *physical, size_t size,
LOG_DBG("physical %p size %u virtual %p", physical, size, virtual); LOG_DBG("physical %p size %u virtual %p", physical, size, virtual);
if (((phys_addr + size - L2_SRAM_BASE) > L2_SRAM_SIZE) || if (((phys_addr + size - DT_L2_SRAM_BASE) > DT_L2_SRAM_SIZE) ||
(phys_addr < L2_SRAM_BASE)) { (phys_addr < DT_L2_SRAM_BASE)) {
LOG_ERR("model at %p of size %u exceeds L2 SRAM space", LOG_ERR("model at %p of size %u exceeds L2 SRAM space",
physical, size); physical, size);
return -EINVAL; return -EINVAL;

2
drivers/neural_net/intel_gna.h
View file

@ -63,7 +63,7 @@ extern "C" {
#define GNA_LAYER_DESC_ALIGN (128) #define GNA_LAYER_DESC_ALIGN (128)
#define GNA_ADDRESSABLE_MEM_SIZE L2_SRAM_SIZE #define GNA_ADDRESSABLE_MEM_SIZE DT_L2_SRAM_SIZE
#define GNA_NUM_PG_TABLE_INDEX_BITS 10 #define GNA_NUM_PG_TABLE_INDEX_BITS 10
#define GNA_NUM_PG_TABLE_ENTRIES BIT(GNA_NUM_PG_TABLE_INDEX_BITS) #define GNA_NUM_PG_TABLE_ENTRIES BIT(GNA_NUM_PG_TABLE_INDEX_BITS)
#define GNA_PG_SIZE_IN_BITSHIFT 12 #define GNA_PG_SIZE_IN_BITSHIFT 12

4
drivers/pinmux/dev/pinmux_dev_arm_beetle.c
View file

@ -17,9 +17,9 @@
#define PINS_PER_PORT 16 #define PINS_PER_PORT 16
#define CMSDK_AHB_GPIO0_DEV \ #define CMSDK_AHB_GPIO0_DEV \
((volatile struct gpio_cmsdk_ahb *)CMSDK_AHB_GPIO0) ((volatile struct gpio_cmsdk_ahb *)DT_CMSDK_AHB_GPIO0)
#define CMSDK_AHB_GPIO1_DEV \ #define CMSDK_AHB_GPIO1_DEV \
((volatile struct gpio_cmsdk_ahb *)CMSDK_AHB_GPIO1) ((volatile struct gpio_cmsdk_ahb *)DT_CMSDK_AHB_GPIO1)
static volatile struct gpio_cmsdk_ahb *_get_port(u32_t pin) static volatile struct gpio_cmsdk_ahb *_get_port(u32_t pin)
{ {

12
drivers/pinmux/pinmux_sam0.c
View file

@ -69,23 +69,23 @@ const struct pinmux_driver_api pinmux_sam0_api = {
.input = pinmux_sam0_input, .input = pinmux_sam0_input,
}; };
#if CONFIG_PINMUX_SAM0_A_BASE_ADDRESS #if DT_PINMUX_SAM0_A_BASE_ADDRESS
static const struct pinmux_sam0_config pinmux_sam0_config_0 = { static const struct pinmux_sam0_config pinmux_sam0_config_0 = {
.regs = (PortGroup *)CONFIG_PINMUX_SAM0_A_BASE_ADDRESS, .regs = (PortGroup *)DT_PINMUX_SAM0_A_BASE_ADDRESS,
}; };
DEVICE_AND_API_INIT(pinmux_sam0_0, CONFIG_PINMUX_SAM0_A_LABEL, DEVICE_AND_API_INIT(pinmux_sam0_0, DT_PINMUX_SAM0_A_LABEL,
pinmux_sam0_init, NULL, &pinmux_sam0_config_0, pinmux_sam0_init, NULL, &pinmux_sam0_config_0,
PRE_KERNEL_1, CONFIG_PINMUX_INIT_PRIORITY, PRE_KERNEL_1, CONFIG_PINMUX_INIT_PRIORITY,
&pinmux_sam0_api); &pinmux_sam0_api);
#endif #endif
#if CONFIG_PINMUX_SAM0_B_BASE_ADDRESS #if DT_PINMUX_SAM0_B_BASE_ADDRESS
static const struct pinmux_sam0_config pinmux_sam0_config_1 = { static const struct pinmux_sam0_config pinmux_sam0_config_1 = {
.regs = (PortGroup *)CONFIG_PINMUX_SAM0_B_BASE_ADDRESS, .regs = (PortGroup *)DT_PINMUX_SAM0_B_BASE_ADDRESS,
}; };
DEVICE_AND_API_INIT(pinmux_sam0_1, CONFIG_PINMUX_SAM0_B_LABEL, DEVICE_AND_API_INIT(pinmux_sam0_1, DT_PINMUX_SAM0_B_LABEL,
pinmux_sam0_init, NULL, &pinmux_sam0_config_1, pinmux_sam0_init, NULL, &pinmux_sam0_config_1,
PRE_KERNEL_1, CONFIG_PINMUX_INIT_PRIORITY, PRE_KERNEL_1, CONFIG_PINMUX_INIT_PRIORITY,
&pinmux_sam0_api); &pinmux_sam0_api);

8
drivers/pwm/pwm_mcux_ftm.c
View file

@ -162,7 +162,7 @@ DEVICE_AND_API_INIT(mcux_ftm_0, CONFIG_FTM_0_NAME, &mcux_ftm_init,
#ifdef CONFIG_PWM_1 #ifdef CONFIG_PWM_1
static const struct mcux_ftm_config mcux_ftm_config_1 = { static const struct mcux_ftm_config mcux_ftm_config_1 = {
.base = (FTM_Type *)CONFIG_FTM_1_BASE_ADDRESS, .base = (FTM_Type *)DT_FTM_1_BASE_ADDRESS,
.clock_source = kCLOCK_McgFixedFreqClk, .clock_source = kCLOCK_McgFixedFreqClk,
.ftm_clock_source = kFTM_FixedClock, .ftm_clock_source = kFTM_FixedClock,
.prescale = kFTM_Prescale_Divide_16, .prescale = kFTM_Prescale_Divide_16,
@ -172,7 +172,7 @@ static const struct mcux_ftm_config mcux_ftm_config_1 = {
static struct mcux_ftm_data mcux_ftm_data_1; static struct mcux_ftm_data mcux_ftm_data_1;
DEVICE_AND_API_INIT(mcux_ftm_1, CONFIG_FTM_1_NAME, &mcux_ftm_init, DEVICE_AND_API_INIT(mcux_ftm_1, DT_FTM_1_NAME, &mcux_ftm_init,
&mcux_ftm_data_1, &mcux_ftm_config_1, &mcux_ftm_data_1, &mcux_ftm_config_1,
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
&mcux_ftm_driver_api); &mcux_ftm_driver_api);
@ -198,7 +198,7 @@ DEVICE_AND_API_INIT(mcux_ftm_2, CONFIG_FTM_2_NAME, &mcux_ftm_init,
#ifdef CONFIG_PWM_3 #ifdef CONFIG_PWM_3
static const struct mcux_ftm_config mcux_ftm_config_3 = { static const struct mcux_ftm_config mcux_ftm_config_3 = {
.base = (FTM_Type *)CONFIG_FTM_3_BASE_ADDRESS, .base = (FTM_Type *)DT_FTM_3_BASE_ADDRESS,
.clock_source = kCLOCK_McgFixedFreqClk, .clock_source = kCLOCK_McgFixedFreqClk,
.ftm_clock_source = kFTM_FixedClock, .ftm_clock_source = kFTM_FixedClock,
.prescale = kFTM_Prescale_Divide_16, .prescale = kFTM_Prescale_Divide_16,
@ -208,7 +208,7 @@ static const struct mcux_ftm_config mcux_ftm_config_3 = {
static struct mcux_ftm_data mcux_ftm_data_3; static struct mcux_ftm_data mcux_ftm_data_3;
DEVICE_AND_API_INIT(mcux_ftm_3, CONFIG_FTM_3_NAME, &mcux_ftm_init, DEVICE_AND_API_INIT(mcux_ftm_3, DT_FTM_3_NAME, &mcux_ftm_init,
&mcux_ftm_data_3, &mcux_ftm_config_3, &mcux_ftm_data_3, &mcux_ftm_config_3,
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
&mcux_ftm_driver_api); &mcux_ftm_driver_api);

50
drivers/pwm/pwm_stm32.c
View file

@ -215,7 +215,7 @@ static int pwm_stm32_init(struct device *dev)
}; \ }; \
\ \
DEVICE_AND_API_INIT(pwm_stm32_ ## n, \ DEVICE_AND_API_INIT(pwm_stm32_ ## n, \
CONFIG_PWM_STM32_ ## n ## _DEV_NAME, \ DT_PWM_STM32_ ## n ## _DEV_NAME, \
pwm_stm32_init, \ pwm_stm32_init, \
&pwm_stm32_dev_data_ ## n, \ &pwm_stm32_dev_data_ ## n, \
&pwm_stm32_dev_cfg_ ## n, \ &pwm_stm32_dev_cfg_ ## n, \
@ -225,115 +225,115 @@ static int pwm_stm32_init(struct device *dev)
#ifdef CONFIG_PWM_STM32_1 #ifdef CONFIG_PWM_STM32_1
/* 16-bit advanced-control timer */ /* 16-bit advanced-control timer */
#ifdef CONFIG_SOC_SERIES_STM32F0X #ifdef CONFIG_SOC_SERIES_STM32F0X
PWM_DEVICE_INIT_STM32(1, APB1, GRP2, CONFIG_PWM_STM32_1_PRESCALER) PWM_DEVICE_INIT_STM32(1, APB1, GRP2, DT_PWM_STM32_1_PRESCALER)
#else #else
PWM_DEVICE_INIT_STM32(1, APB2, GRP1, CONFIG_PWM_STM32_1_PRESCALER) PWM_DEVICE_INIT_STM32(1, APB2, GRP1, DT_PWM_STM32_1_PRESCALER)
#endif /*CONFIG_SOC_SERIES_STM32F0X */ #endif /*CONFIG_SOC_SERIES_STM32F0X */
#endif /* CONFIG_PWM_STM32_1 */ #endif /* CONFIG_PWM_STM32_1 */
#ifdef CONFIG_PWM_STM32_2 #ifdef CONFIG_PWM_STM32_2
/* 32-bit general-purpose timer */ /* 32-bit general-purpose timer */
PWM_DEVICE_INIT_STM32(2, APB1, GRP1, CONFIG_PWM_STM32_2_PRESCALER) PWM_DEVICE_INIT_STM32(2, APB1, GRP1, DT_PWM_STM32_2_PRESCALER)
#endif /* CONFIG_PWM_STM32_2 */ #endif /* CONFIG_PWM_STM32_2 */
#ifdef CONFIG_PWM_STM32_3 #ifdef CONFIG_PWM_STM32_3
/* 16-bit general-purpose timer */ /* 16-bit general-purpose timer */
PWM_DEVICE_INIT_STM32(3, APB1, GRP1, CONFIG_PWM_STM32_3_PRESCALER) PWM_DEVICE_INIT_STM32(3, APB1, GRP1, DT_PWM_STM32_3_PRESCALER)
#endif /* CONFIG_PWM_STM32_3 */ #endif /* CONFIG_PWM_STM32_3 */
#ifdef CONFIG_PWM_STM32_4 #ifdef CONFIG_PWM_STM32_4
/* 16-bit general-purpose timer */ /* 16-bit general-purpose timer */
PWM_DEVICE_INIT_STM32(4, APB1, GRP1, CONFIG_PWM_STM32_4_PRESCALER) PWM_DEVICE_INIT_STM32(4, APB1, GRP1, DT_PWM_STM32_4_PRESCALER)
#endif /* CONFIG_PWM_STM32_4 */ #endif /* CONFIG_PWM_STM32_4 */
#ifdef CONFIG_PWM_STM32_5 #ifdef CONFIG_PWM_STM32_5
/* 32-bit general-purpose timer */ /* 32-bit general-purpose timer */
PWM_DEVICE_INIT_STM32(5, APB1, GRP1, CONFIG_PWM_STM32_5_PRESCALER) PWM_DEVICE_INIT_STM32(5, APB1, GRP1, DT_PWM_STM32_5_PRESCALER)
#endif /* CONFIG_PWM_STM32_5 */ #endif /* CONFIG_PWM_STM32_5 */
#ifdef CONFIG_PWM_STM32_6 #ifdef CONFIG_PWM_STM32_6
/* 16-bit basic timer */ /* 16-bit basic timer */
PWM_DEVICE_INIT_STM32(6, APB1, GRP1, CONFIG_PWM_STM32_6_PRESCALER) PWM_DEVICE_INIT_STM32(6, APB1, GRP1, DT_PWM_STM32_6_PRESCALER)
#endif /* CONFIG_PWM_STM32_6 */ #endif /* CONFIG_PWM_STM32_6 */
#ifdef CONFIG_PWM_STM32_7 #ifdef CONFIG_PWM_STM32_7
/* 16-bit basic timer */ /* 16-bit basic timer */
PWM_DEVICE_INIT_STM32(7, APB1, GRP1, CONFIG_PWM_STM32_7_PRESCALER) PWM_DEVICE_INIT_STM32(7, APB1, GRP1, DT_PWM_STM32_7_PRESCALER)
#endif /* CONFIG_PWM_STM32_7 */ #endif /* CONFIG_PWM_STM32_7 */
#ifdef CONFIG_PWM_STM32_8 #ifdef CONFIG_PWM_STM32_8
/* 16-bit advanced-control timer */ /* 16-bit advanced-control timer */
PWM_DEVICE_INIT_STM32(8, APB2, GRP1, CONFIG_PWM_STM32_8_PRESCALER) PWM_DEVICE_INIT_STM32(8, APB2, GRP1, DT_PWM_STM32_8_PRESCALER)
#endif /* CONFIG_PWM_STM32_8 */ #endif /* CONFIG_PWM_STM32_8 */
#ifdef CONFIG_PWM_STM32_9 #ifdef CONFIG_PWM_STM32_9
/* 16-bit general-purpose timer */ /* 16-bit general-purpose timer */
PWM_DEVICE_INIT_STM32(9, APB2, GRP1, CONFIG_PWM_STM32_9_PRESCALER) PWM_DEVICE_INIT_STM32(9, APB2, GRP1, DT_PWM_STM32_9_PRESCALER)
#endif /* CONFIG_PWM_STM32_9 */ #endif /* CONFIG_PWM_STM32_9 */
#ifdef CONFIG_PWM_STM32_10 #ifdef CONFIG_PWM_STM32_10
/* 16-bit general-purpose timer */ /* 16-bit general-purpose timer */
PWM_DEVICE_INIT_STM32(10, APB2, GRP1, CONFIG_PWM_STM32_10_PRESCALER) PWM_DEVICE_INIT_STM32(10, APB2, GRP1, DT_PWM_STM32_10_PRESCALER)
#endif /* CONFIG_PWM_STM32_10 */ #endif /* CONFIG_PWM_STM32_10 */
#ifdef CONFIG_PWM_STM32_11 #ifdef CONFIG_PWM_STM32_11
/* 16-bit general-purpose timer */ /* 16-bit general-purpose timer */
PWM_DEVICE_INIT_STM32(11, APB2, GRP1, CONFIG_PWM_STM32_11_PRESCALER) PWM_DEVICE_INIT_STM32(11, APB2, GRP1, DT_PWM_STM32_11_PRESCALER)
#endif /* CONFIG_PWM_STM32_11 */ #endif /* CONFIG_PWM_STM32_11 */
#ifdef CONFIG_PWM_STM32_12 #ifdef CONFIG_PWM_STM32_12
/* 16-bit general-purpose timer */ /* 16-bit general-purpose timer */
PWM_DEVICE_INIT_STM32(12, APB1, GRP1, CONFIG_PWM_STM32_12_PRESCALER) PWM_DEVICE_INIT_STM32(12, APB1, GRP1, DT_PWM_STM32_12_PRESCALER)
#endif /* CONFIG_PWM_STM32_12 */ #endif /* CONFIG_PWM_STM32_12 */
#ifdef CONFIG_PWM_STM32_13 #ifdef CONFIG_PWM_STM32_13
/* 16-bit general-purpose timer */ /* 16-bit general-purpose timer */
PWM_DEVICE_INIT_STM32(13, APB1, GRP1, CONFIG_PWM_STM32_13_PRESCALER) PWM_DEVICE_INIT_STM32(13, APB1, GRP1, DT_PWM_STM32_13_PRESCALER)
#endif /* CONFIG_PWM_STM32_13 */ #endif /* CONFIG_PWM_STM32_13 */
#ifdef CONFIG_PWM_STM32_14 #ifdef CONFIG_PWM_STM32_14
/* 16-bit general-purpose timer */ /* 16-bit general-purpose timer */
PWM_DEVICE_INIT_STM32(14, APB1, GRP1, CONFIG_PWM_STM32_14_PRESCALER) PWM_DEVICE_INIT_STM32(14, APB1, GRP1, DT_PWM_STM32_14_PRESCALER)
#endif /* CONFIG_PWM_STM32_14 */ #endif /* CONFIG_PWM_STM32_14 */
#ifdef CONFIG_PWM_STM32_15 #ifdef CONFIG_PWM_STM32_15
/* 16-bit general-purpose timer */ /* 16-bit general-purpose timer */
#ifdef CONFIG_SOC_SERIES_STM32F0X #ifdef CONFIG_SOC_SERIES_STM32F0X
PWM_DEVICE_INIT_STM32(15, APB1, GRP2, CONFIG_PWM_STM32_15_PRESCALER) PWM_DEVICE_INIT_STM32(15, APB1, GRP2, DT_PWM_STM32_15_PRESCALER)
#else #else
PWM_DEVICE_INIT_STM32(15, APB2, GRP1, CONFIG_PWM_STM32_15_PRESCALER) PWM_DEVICE_INIT_STM32(15, APB2, GRP1, DT_PWM_STM32_15_PRESCALER)
#endif /* CONFIG_SOC_SERIES_STM32F0X */ #endif /* CONFIG_SOC_SERIES_STM32F0X */
#endif /* CONFIG_PWM_STM32_15 */ #endif /* CONFIG_PWM_STM32_15 */
#ifdef CONFIG_PWM_STM32_16 #ifdef CONFIG_PWM_STM32_16
/* 16-bit general-purpose timer */ /* 16-bit general-purpose timer */
#ifdef CONFIG_SOC_SERIES_STM32F0X #ifdef CONFIG_SOC_SERIES_STM32F0X
PWM_DEVICE_INIT_STM32(16, APB1, GRP2, CONFIG_PWM_STM32_16_PRESCALER) PWM_DEVICE_INIT_STM32(16, APB1, GRP2, DT_PWM_STM32_16_PRESCALER)
#else #else
PWM_DEVICE_INIT_STM32(16, APB2, GRP1, CONFIG_PWM_STM32_16_PRESCALER) PWM_DEVICE_INIT_STM32(16, APB2, GRP1, DT_PWM_STM32_16_PRESCALER)
#endif /* CONFIG_SOC_SERIES_STM32F0X */ #endif /* CONFIG_SOC_SERIES_STM32F0X */
#endif /* CONFIG_PWM_STM32_16 */ #endif /* CONFIG_PWM_STM32_16 */
#ifdef CONFIG_PWM_STM32_17 #ifdef CONFIG_PWM_STM32_17
/* 16-bit general-purpose timer */ /* 16-bit general-purpose timer */
#ifdef CONFIG_SOC_SERIES_STM32F0X #ifdef CONFIG_SOC_SERIES_STM32F0X
PWM_DEVICE_INIT_STM32(17, APB1, GRP2, CONFIG_PWM_STM32_17_PRESCALER) PWM_DEVICE_INIT_STM32(17, APB1, GRP2, DT_PWM_STM32_17_PRESCALER)
#else #else
PWM_DEVICE_INIT_STM32(17, APB2, GRP1, CONFIG_PWM_STM32_17_PRESCALER) PWM_DEVICE_INIT_STM32(17, APB2, GRP1, DT_PWM_STM32_17_PRESCALER)
#endif /* CONFIG_SOC_SERIES_STM32F0X */ #endif /* CONFIG_SOC_SERIES_STM32F0X */
#endif /* CONFIG_PWM_STM32_17 */ #endif /* CONFIG_PWM_STM32_17 */
#ifdef CONFIG_PWM_STM32_18 #ifdef CONFIG_PWM_STM32_18
/* 16-bit advanced timer */ /* 16-bit advanced timer */
PWM_DEVICE_INIT_STM32(18, APB1, GRP1, CONFIG_PWM_STM32_18_PRESCALER) PWM_DEVICE_INIT_STM32(18, APB1, GRP1, DT_PWM_STM32_18_PRESCALER)
#endif /* CONFIG_PWM_STM32_18 */ #endif /* CONFIG_PWM_STM32_18 */
#ifdef CONFIG_PWM_STM32_19 #ifdef CONFIG_PWM_STM32_19
/* 16-bit general-purpose timer */ /* 16-bit general-purpose timer */
PWM_DEVICE_INIT_STM32(19, APB2, GRP1, CONFIG_PWM_STM32_19_PRESCALER) PWM_DEVICE_INIT_STM32(19, APB2, GRP1, DT_PWM_STM32_19_PRESCALER)
#endif /* CONFIG_PWM_STM32_19 */ #endif /* CONFIG_PWM_STM32_19 */
#ifdef CONFIG_PWM_STM32_20 #ifdef CONFIG_PWM_STM32_20
/* 16-bit advanced timer */ /* 16-bit advanced timer */
PWM_DEVICE_INIT_STM32(20, APB2, GRP1, CONFIG_PWM_STM32_20_PRESCALER) PWM_DEVICE_INIT_STM32(20, APB2, GRP1, DT_PWM_STM32_20_PRESCALER)
#endif /* CONFIG_PWM_STM32_20 */ #endif /* CONFIG_PWM_STM32_20 */

4
drivers/rtc/rtc_ll_stm32.c
View file

@ -302,7 +302,7 @@ DEVICE_AND_API_INIT(rtc_stm32, CONFIG_RTC_0_NAME, &rtc_stm32_init,
static void rtc_stm32_irq_config(struct device *dev) static void rtc_stm32_irq_config(struct device *dev)
{ {
IRQ_CONNECT(CONFIG_RTC_0_IRQ, CONFIG_RTC_0_IRQ_PRI, IRQ_CONNECT(DT_RTC_0_IRQ, CONFIG_RTC_0_IRQ_PRI,
rtc_stm32_isr, DEVICE_GET(rtc_stm32), 0); rtc_stm32_isr, DEVICE_GET(rtc_stm32), 0);
irq_enable(CONFIG_RTC_0_IRQ); irq_enable(DT_RTC_0_IRQ);
} }

8
drivers/rtc/rtc_mcux.c
View file

@ -190,18 +190,18 @@ static struct mcux_rtc_data rtc_mcux_data_0;
static void rtc_mcux_irq_config_0(struct device *dev); static void rtc_mcux_irq_config_0(struct device *dev);
static struct mcux_rtc_config rtc_mcux_config_0 = { static struct mcux_rtc_config rtc_mcux_config_0 = {
.base = (RTC_Type *)CONFIG_RTC_MCUX_0_BASE_ADDRESS, .base = (RTC_Type *)DT_RTC_MCUX_0_BASE_ADDRESS,
.irq_config_func = rtc_mcux_irq_config_0, .irq_config_func = rtc_mcux_irq_config_0,
}; };
DEVICE_DEFINE(rtc, CONFIG_RTC_MCUX_0_NAME, DEVICE_DEFINE(rtc, DT_RTC_MCUX_0_NAME,
&mcux_rtc_init, NULL, &rtc_mcux_data_0, &rtc_mcux_config_0, &mcux_rtc_init, NULL, &rtc_mcux_data_0, &rtc_mcux_config_0,
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
&mcux_rtc_driver_api); &mcux_rtc_driver_api);
static void rtc_mcux_irq_config_0(struct device *dev) static void rtc_mcux_irq_config_0(struct device *dev)
{ {
IRQ_CONNECT(CONFIG_RTC_MCUX_0_IRQ, CONFIG_RTC_MCUX_0_IRQ_PRI, IRQ_CONNECT(DT_RTC_MCUX_0_IRQ, DT_RTC_MCUX_0_IRQ_PRI,
mcux_rtc_isr, DEVICE_GET(rtc), 0); mcux_rtc_isr, DEVICE_GET(rtc), 0);
irq_enable(CONFIG_RTC_MCUX_0_IRQ); irq_enable(DT_RTC_MCUX_0_IRQ);
} }

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