From 20202902f2a8210497736dd872c539abf9a9a424 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andrzej=20G=C5=82=C4=85bek?= Date: Tue, 13 Nov 2018 15:15:23 +0100 Subject: [PATCH] dts_fixups: Use DT_ prefix in all defined labels not related to Kconfig MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit These changes were obtained by running a script created by Ulf Magnusson for the following specification: 1. Read the contents of all dts_fixup.h files in Zephyr 2. Check the left-hand side of the #define macros (i.e. the X in #define X Y) 3. Check if that name is also the name of a Kconfig option 3.a If it is, then do nothing 3.b If it is not, then replace CONFIG_ with DT_ or add DT_ if it has neither of these two prefixes 4. Replace the use of the changed #define in the code itself (.c, .h, .ld) Additionally, some tweaks had to be added to this script to catch some of the macros used in the code in a parameterized form, e.g.: - CONFIG_GPIO_STM32_GPIO##__SUFFIX##_BASE_ADDRESS - CONFIG_UART_##idx##_TX_PIN - I2C_SBCON_##_num##_BASE_ADDR and to prevent adding DT_ prefix to the following symbols: - FLASH_START - FLASH_SIZE - SRAM_START - SRAM_SIZE - _ROM_ADDR - _ROM_SIZE - _RAM_ADDR - _RAM_SIZE which are surprisingly also defined in some dts_fixup.h files. Finally, some manual corrections had to be done as well: - name##_IRQ -> DT_##name##_IRQ in uart_stm32.c Signed-off-by: Andrzej Głąbek --- arch/arm/core/irq_manage.c | 4 +- boards/arc/arduino_101_sss/dts_fixup.h | 12 +- boards/arc/em_starterkit/arc_mpu_regions.c | 24 +- boards/arc/nsim_em/arc_mpu_regions.c | 24 +- boards/arm/96b_argonkey/dts_fixup.h | 28 +- .../adafruit_feather_m0_basic_proto/pinmux.c | 30 +- boards/arm/adafruit_trinket_m0/pinmux.c | 26 +- boards/arm/arduino_zero/pinmux.c | 28 +- boards/arm/atsamd20_xpro/pinmux.c | 28 +- boards/arm/atsamd21_xpro/pinmux.c | 28 +- boards/arm/bbc_microbit/dts_fixup.h | 10 +- boards/arm/disco_l475_iot1/dts_fixup.h | 32 +- boards/arm/efm32hg_slstk3400a/board.h | 2 +- boards/arm/efm32wg_stk3800/board.h | 2 +- boards/arm/efr32_slwstk6061a/board.h | 2 +- boards/arm/frdm_k64f/dts_fixup.h | 10 +- boards/arm/frdm_kl25z/dts_fixup.h | 10 +- boards/arm/frdm_kw41z/dts_fixup.h | 10 +- boards/arm/hexiwear_k64/dts_fixup.h | 26 +- boards/arm/mps2_an385/dts_fixup.h | 108 ++-- boards/arm/mps2_an385/pinmux.c | 8 +- boards/arm/nrf52_pca20020/board.c | 2 +- boards/arm/nrf52_pca20020/dts_fixup.h | 18 +- boards/arm/olimexino_stm32/dts_fixup.h | 6 +- boards/arm/reel_board/dts_fixup.h | 58 +-- boards/arm/stm32f3_disco/dts_fixup.h | 12 +- boards/arm/v2m_beetle/pinmux.c | 4 +- boards/arm/warp7_m4/dts_fixup.h | 20 +- boards/shields/x_nucleo_iks01a1/dts_fixup.h | 22 +- boards/shields/x_nucleo_iks01a2/dts_fixup.h | 16 +- boards/x86/qemu_x86/dts_fixup.h | 8 +- boards/x86/up_squared/dts_fixup.h | 80 +-- boards/xtensa/intel_s1000_crb/dts_fixup.h | 6 +- drivers/adc/adc_dw.c | 10 +- drivers/adc/adc_intel_quark_d2000.c | 8 +- drivers/adc/adc_mcux_adc16.c | 12 +- drivers/adc/adc_nrfx_adc.c | 2 +- drivers/adc/adc_nrfx_saadc.c | 4 +- drivers/adc/adc_sam_afec.c | 16 +- drivers/audio/tlv320dac310x.c | 6 +- drivers/can/stm32_can.c | 32 +- .../clock_control/clock_control_mcux_ccm.c | 2 +- .../clock_control/clock_control_mcux_sim.c | 2 +- drivers/counter/counter_dtmr_cmsdk_apb.c | 8 +- drivers/counter/counter_tmr_cmsdk_apb.c | 16 +- drivers/counter/timer_dtmr_cmsdk_apb.c | 12 +- drivers/counter/timer_tmr_cmsdk_apb.c | 24 +- drivers/display/display_ili9340.c | 26 +- drivers/display/mb_display.c | 26 +- drivers/display/ssd1306.c | 56 +-- drivers/display/ssd1673.c | 46 +- drivers/ethernet/eth_e1000.c | 6 +- drivers/ethernet/eth_mcux.c | 24 +- drivers/flash/flash_gecko.c | 2 +- drivers/flash/flash_sam0.c | 2 +- drivers/flash/flash_shell.c | 8 +- drivers/flash/flash_stm32.c | 8 +- drivers/flash/flash_stm32f3x.c | 4 +- drivers/flash/soc_flash_mcux.c | 2 +- drivers/flash/soc_flash_nrf.c | 2 +- drivers/gpio/gpio_cc32xx.c | 48 +- drivers/gpio/gpio_cmsdk_ahb.c | 48 +- drivers/gpio/gpio_dw.c | 42 +- drivers/gpio/gpio_gecko.c | 18 +- drivers/gpio/gpio_imx.c | 112 ++--- drivers/gpio/gpio_intel_apl.c | 16 +- drivers/gpio/gpio_mcux_igpio.c | 24 +- drivers/gpio/gpio_nrfx.c | 6 +- drivers/gpio/gpio_qmsi.c | 18 +- drivers/gpio/gpio_qmsi_ss.c | 12 +- drivers/gpio/gpio_sam.c | 70 +-- drivers/gpio/gpio_sam0.c | 12 +- drivers/gpio/gpio_sifive.c | 132 ++--- drivers/gpio/gpio_stm32.c | 8 +- drivers/i2c/i2c_cc32xx.c | 12 +- drivers/i2c/i2c_dw.c | 80 +-- drivers/i2c/i2c_gecko.c | 16 +- drivers/i2c/i2c_ll_stm32.c | 78 +-- drivers/i2c/i2c_mcux.c | 16 +- drivers/i2c/i2c_nrfx_twi.c | 6 +- drivers/i2c/i2c_nrfx_twim.c | 6 +- drivers/i2c/i2c_qmsi.c | 16 +- drivers/i2c/i2c_qmsi_ss.c | 40 +- drivers/i2c/i2c_sam_twi.c | 20 +- drivers/i2c/i2c_sam_twihs.c | 30 +- drivers/i2c/i2c_sbcon.c | 2 +- drivers/i2s/i2s_ll_stm32.c | 60 +-- drivers/interrupt_controller/cavs_ictl.c | 32 +- drivers/interrupt_controller/dw_ictl.c | 8 +- drivers/interrupt_controller/ioapic_intr.c | 8 +- drivers/ipm/ipm_mcux.c | 10 +- drivers/modem/wncm14a2a.c | 32 +- drivers/neural_net/intel_gna.c | 4 +- drivers/neural_net/intel_gna.h | 2 +- drivers/pinmux/dev/pinmux_dev_arm_beetle.c | 4 +- drivers/pinmux/pinmux_sam0.c | 12 +- drivers/pwm/pwm_mcux_ftm.c | 8 +- drivers/pwm/pwm_stm32.c | 50 +- drivers/rtc/rtc_ll_stm32.c | 4 +- drivers/rtc/rtc_mcux.c | 8 +- drivers/rtc/rtc_qmsi.c | 6 +- drivers/sensor/adt7420/adt7420.c | 10 +- drivers/sensor/adxl372/adxl372.c | 16 +- drivers/sensor/apds9960/apds9960.c | 20 +- drivers/sensor/apds9960/apds9960_trigger.c | 6 +- drivers/sensor/bmi160/bmi160.c | 14 +- drivers/sensor/ccs811/ccs811.c | 22 +- drivers/sensor/fxas21002/fxas21002.c | 10 +- drivers/sensor/fxos8700/fxos8700.c | 10 +- drivers/sensor/hdc1008/hdc1008.c | 30 +- drivers/sensor/hts221/hts221.c | 6 +- drivers/sensor/lis3mdl/lis3mdl.c | 14 +- drivers/sensor/lis3mdl/lis3mdl.h | 4 +- drivers/sensor/lis3mdl/lis3mdl_trigger.c | 2 +- drivers/sensor/lps22hb/lps22hb.c | 6 +- drivers/sensor/lps25hb/lps25hb.c | 6 +- .../lsm303dlhc_accel/lsm303dlhc_accel.c | 6 +- .../sensor/lsm303dlhc_magn/lsm303dlhc_magn.c | 6 +- drivers/sensor/lsm6ds0/lsm6ds0.c | 6 +- drivers/sensor/lsm6dsl/lsm6dsl.c | 6 +- drivers/sensor/lsm6dsl/lsm6dsl_i2c.c | 2 +- drivers/sensor/lsm6dsl/lsm6dsl_spi.c | 4 +- drivers/sensor/lsm6dsl/lsm6dsl_trigger.c | 18 +- drivers/sensor/max30101/max30101.c | 4 +- drivers/sensor/ms5837/ms5837.c | 6 +- drivers/sensor/qdec_nrfx/qdec_nrfx.c | 30 +- drivers/sensor/vl53l0x/vl53l0x.c | 8 +- drivers/serial/leuart_gecko.c | 14 +- drivers/serial/uart_cc32xx.c | 2 +- drivers/serial/uart_cmsdk_apb.c | 142 +++--- drivers/serial/uart_gecko.c | 120 ++--- drivers/serial/uart_imx.c | 98 ++-- drivers/serial/uart_mcux.c | 120 ++--- drivers/serial/uart_mcux_lpsci.c | 6 +- drivers/serial/uart_mcux_lpuart.c | 46 +- drivers/serial/uart_miv.c | 8 +- drivers/serial/uart_msp432p4xx.c | 6 +- drivers/serial/uart_nrfx_uart.c | 38 +- drivers/serial/uart_nrfx_uarte.c | 26 +- drivers/serial/uart_ns16550.c | 34 +- drivers/serial/uart_psoc6.c | 52 +- drivers/serial/uart_qmsi.c | 24 +- drivers/serial/uart_sam.c | 70 +-- drivers/serial/uart_sam0.c | 28 +- drivers/serial/uart_sifive.c | 22 +- drivers/serial/uart_stellaris.c | 6 +- drivers/serial/uart_stm32.c | 16 +- drivers/serial/usart_mcux_lpc.c | 6 +- drivers/serial/usart_sam.c | 48 +- drivers/spi/spi_dw.c | 80 +-- drivers/spi/spi_dw.h | 4 +- drivers/spi/spi_intel.c | 16 +- drivers/spi/spi_ll_stm32.c | 18 +- drivers/spi/spi_mcux_dspi.c | 30 +- drivers/spi/spi_nrfx_spi.c | 6 +- drivers/spi/spi_nrfx_spim.c | 6 +- drivers/spi/spi_nrfx_spis.c | 8 +- drivers/spi/spi_sam.c | 8 +- drivers/spi/spi_sam0.c | 20 +- drivers/usb/device/usb_dc_kinetis.c | 6 +- drivers/usb/device/usb_dc_nrfx.c | 16 +- drivers/usb/device/usb_dc_sam.c | 54 +- drivers/usb/device/usb_dc_sam0.c | 12 +- drivers/usb/device/usb_dc_stm32.c | 82 +-- drivers/watchdog/wdog_cmsdk_apb.c | 2 +- drivers/watchdog/wdt_mcux_wdog.c | 10 +- drivers/watchdog/wdt_nrfx.c | 4 +- drivers/watchdog/wdt_qmsi.c | 4 +- drivers/watchdog/wdt_sam.c | 8 +- drivers/watchdog/wdt_sam0.c | 8 +- drivers/wifi/eswifi/eswifi_bus_spi.c | 4 +- .../port/zephyr/src/zephyr_img_mgmt.c | 2 +- include/arch/arm/cortex_m/cmsis.h | 6 +- include/arch/arm/cortex_m/exc.h | 2 +- include/arch/x86/linker.ld | 6 +- lib/libc/newlib/libc-hooks.c | 4 +- .../boards/arm/nrf52840_pca10056/board.h | 16 +- samples/basic/blink_led/src/main.c | 4 +- samples/basic/fade_led/src/main.c | 4 +- samples/bluetooth/mesh_demo/src/microbit.c | 2 +- samples/boards/96b_argonkey/src/main.c | 16 +- .../environmental_sensing/sensor/dts_fixup.h | 10 +- .../reel_board/mesh_badge/src/periphs.c | 8 +- .../reel_board/mesh_badge/src/reel_board.c | 4 +- .../boards/up_squared/gpio_counter/src/main.c | 2 +- samples/display/cfb/dts_fixup.h | 22 +- samples/display/ili9340/dts_fixup.h | 16 +- samples/drivers/flash_shell/src/main.c | 10 +- samples/drivers/gpio/src/main.c | 4 +- samples/drivers/i2c_fujitsu_fram/src/main.c | 2 +- samples/drivers/led_apa102c/src/main.c | 2 +- samples/drivers/soc_flash_nrf/src/main.c | 2 +- samples/mpu/mpu_test/src/main.c | 4 +- samples/net/lwm2m_client/dts_fixup.h | 26 +- samples/sensor/adt7420/dts_fixup.h | 8 +- samples/sensor/adt7420/src/main.c | 2 +- samples/sensor/adxl372/dts_fixup.h | 22 +- samples/sensor/adxl372/src/main.c | 4 +- samples/sensor/apds9960/src/main.c | 2 +- samples/sensor/bmi160/src/bmi160.c | 2 +- samples/sensor/ccs811/dts_fixup.h | 8 +- samples/sensor/fxas21002/src/main.c | 2 +- samples/sensor/fxos8700/src/main.c | 2 +- samples/sensor/lsm303dlhc/src/main.c | 8 +- samples/sensor/max30101/src/main.c | 2 +- samples/sensor/ms5837/dts_fixup.h | 12 +- samples/sensor/ms5837/src/main.c | 2 +- samples/sensor/vl53l0x/src/main.c | 2 +- samples/shields/x_nucleo_iks01a1/src/main.c | 8 +- samples/subsys/nvs/src/main.c | 2 +- soc/arc/quark_se_c1000_ss/dts_fixup.h | 128 ++--- soc/arc/quark_se_c1000_ss/linker.ld | 4 +- soc/arc/quark_se_c1000_ss/soc.h | 32 +- soc/arc/snps_emsk/dts_fixup.h | 86 ++-- soc/arc/snps_emsk/linker.ld | 12 +- soc/arc/snps_emsk/soc.h | 52 +- soc/arc/snps_emsk/soc_config.c | 8 +- soc/arc/snps_nsim/dts_fixup.h | 8 +- soc/arc/snps_nsim/linker.ld | 12 +- soc/arm/arm/beetle/dts_fixup.h | 52 +- soc/arm/atmel_sam/sam3x/dts_fixup.h | 50 +- soc/arm/atmel_sam/sam4s/dts_fixup.h | 80 +-- soc/arm/atmel_sam/same70/dts_fixup.h | 190 +++---- soc/arm/atmel_sam0/samd20/dts_fixup.h | 162 +++--- soc/arm/atmel_sam0/samd21/dts_fixup.h | 170 +++---- soc/arm/cypress/psoc6/dts_fixup.h | 48 +- soc/arm/nordic_nrf/nrf51/dts_fixup.h | 98 ++-- soc/arm/nordic_nrf/nrf52/dts_fixup.h | 214 ++++---- soc/arm/nxp_imx/mcimx6x_m4/dts_fixup.h | 158 +++--- soc/arm/nxp_imx/mcimx7_m4/dts_fixup.h | 170 +++---- soc/arm/nxp_imx/rt/dts_fixup.h | 58 +-- soc/arm/nxp_kinetis/k6x/dts_fixup.h | 208 ++++---- soc/arm/nxp_kinetis/kl2x/dts_fixup.h | 38 +- soc/arm/nxp_kinetis/kwx/dts_fixup.h | 196 ++++---- soc/arm/nxp_lpc/lpc54xxx/dts_fixup.h | 20 +- soc/arm/silabs_exx32/efm32hg/dts_fixup.h | 64 +-- soc/arm/silabs_exx32/efm32hg/soc_pinmap.h | 20 +- soc/arm/silabs_exx32/efm32wg/dts_fixup.h | 118 ++--- soc/arm/silabs_exx32/efm32wg/soc_pinmap.h | 14 +- soc/arm/silabs_exx32/efr32fg1p/dts_fixup.h | 64 +-- soc/arm/silabs_exx32/efr32fg1p/soc_pinmap.h | 14 +- soc/arm/silabs_exx32/efr32mg12p/dts_fixup.h | 142 +++--- soc/arm/silabs_exx32/efr32mg12p/soc_pinmap.h | 8 +- soc/arm/st_stm32/stm32f0/dts_fixup.h | 228 ++++----- soc/arm/st_stm32/stm32f1/dts_fixup.h | 256 +++++----- soc/arm/st_stm32/stm32f2/dts_fixup.h | 242 ++++----- soc/arm/st_stm32/stm32f3/dts_fixup.h | 292 +++++------ soc/arm/st_stm32/stm32f4/dts_fixup.h | 474 +++++++++--------- soc/arm/st_stm32/stm32f7/dts_fixup.h | 454 ++++++++--------- soc/arm/st_stm32/stm32l0/dts_fixup.h | 194 +++---- soc/arm/st_stm32/stm32l4/dts_fixup.h | 406 +++++++-------- soc/arm/ti_lm3s6965/dts_fixup.h | 2 +- soc/arm/ti_lm3s6965/soc.h | 2 +- soc/arm/ti_simplelink/cc2650/dts_fixup.h | 4 +- soc/arm/ti_simplelink/cc32xx/dts_fixup.h | 46 +- soc/arm/ti_simplelink/cc32xx/soc.h | 2 +- soc/arm/ti_simplelink/msp432p4xx/dts_fixup.h | 8 +- soc/nios2/nios2-qemu/soc.h | 6 +- soc/nios2/nios2f-zephyr/soc.h | 6 +- soc/riscv32/pulpino/dts_fixup.h | 6 +- soc/riscv32/pulpino/soc.h | 2 +- soc/riscv32/riscv-privilege/miv/dts_fixup.h | 8 +- .../sifive-freedom/dts_fixup.h | 90 ++-- .../riscv-privilege/sifive-freedom/soc.h | 2 +- soc/x86/apollo_lake/dts_fixup.h | 34 +- soc/x86/apollo_lake/linker.ld | 10 +- soc/x86/apollo_lake/soc.c | 40 +- soc/x86/atom/dts_fixup.h | 26 +- soc/x86/atom/linker.ld | 10 +- soc/x86/atom/soc.c | 2 +- soc/x86/ia32/dts_fixup.h | 26 +- soc/x86/ia32/linker.ld | 10 +- soc/x86/ia32/soc.c | 4 +- soc/x86/intel_quark/quark_d2000/dts_fixup.h | 56 +-- soc/x86/intel_quark/quark_d2000/linker.ld | 12 +- soc/x86/intel_quark/quark_d2000/soc.h | 2 +- soc/x86/intel_quark/quark_se/dts_fixup.h | 74 +-- soc/x86/intel_quark/quark_se/eoi.c | 2 +- soc/x86/intel_quark/quark_se/linker.ld | 14 +- soc/x86/intel_quark/quark_se/soc.c | 2 +- soc/x86/intel_quark/quark_se/soc.h | 2 +- soc/x86/intel_quark/quark_x1000/dts_fixup.h | 46 +- soc/x86/intel_quark/quark_x1000/linker.ld | 10 +- soc/x86/intel_quark/quark_x1000/soc.h | 8 +- soc/xtensa/intel_s1000/dts_fixup.h | 54 +- soc/xtensa/intel_s1000/linker.ld | 2 +- soc/xtensa/intel_s1000/memory.h | 24 +- soc/xtensa/intel_s1000/soc.c | 16 +- soc/xtensa/intel_s1000/soc.h | 12 +- subsys/debug/tracing/sysview_config.c | 4 +- subsys/dfu/boot/mcuboot.c | 2 +- subsys/fs/shell.c | 2 +- subsys/net/lib/openthread/platform/flash.c | 2 +- subsys/storage/flash_map/flash_map.c | 4 +- subsys/usb/class/usb_dfu.c | 2 +- tests/boards/intel_s1000_crb/src/gpio_test.c | 2 +- tests/drivers/aio/api/src/test_callback.c | 4 +- tests/drivers/build_all/dts_fixup.h | 170 +++---- .../gpio/gpio_basic_api/src/test_gpio.h | 18 +- tests/drivers/i2c/i2c_api/src/test_i2c.c | 2 +- .../pinmux/pinmux_basic_api/src/pinmux_gpio.c | 10 +- tests/subsys/dfu/img_util/src/main.c | 2 +- tests/subsys/dfu/mcuboot/src/main.c | 6 +- tests/subsys/storage/flash_map/src/main.c | 2 +- 304 files changed, 5118 insertions(+), 5118 deletions(-) diff --git a/arch/arm/core/irq_manage.c b/arch/arm/core/irq_manage.c index b39a3c36a9c..a4712ef2438 100644 --- a/arch/arm/core/irq_manage.c +++ b/arch/arm/core/irq_manage.c @@ -108,10 +108,10 @@ void _irq_priority_set(unsigned int irq, unsigned int prio, u32_t flags) * affecting performance (can still be useful on systems with a * reduced set of priorities, like Cortex-M0/M0+). */ - __ASSERT(prio <= ((1 << CONFIG_NUM_IRQ_PRIO_BITS) - 1), + __ASSERT(prio <= ((1 << DT_NUM_IRQ_PRIO_BITS) - 1), "invalid priority %d! values must be less than %d\n", prio - _IRQ_PRIO_OFFSET, - (1 << CONFIG_NUM_IRQ_PRIO_BITS) - (_IRQ_PRIO_OFFSET)); + (1 << DT_NUM_IRQ_PRIO_BITS) - (_IRQ_PRIO_OFFSET)); NVIC_SetPriority((IRQn_Type)irq, prio); } diff --git a/boards/arc/arduino_101_sss/dts_fixup.h b/boards/arc/arduino_101_sss/dts_fixup.h index 5592c9301be..8f8a69ee090 100644 --- a/boards/arc/arduino_101_sss/dts_fixup.h +++ b/boards/arc/arduino_101_sss/dts_fixup.h @@ -4,10 +4,10 @@ * SPDX-License-Identifier: Apache-2.0 */ -#define CONFIG_BMI160_SLAVE DT_SNPS_DESIGNWARE_SPI_80010100_BOSCH_BMI160_1_BASE_ADDRESS -#define CONFIG_BMI160_SPI_PORT_NAME DT_SNPS_DESIGNWARE_SPI_80010100_BOSCH_BMI160_1_BUS_NAME -#define CONFIG_BMI160_GPIO_DEV_NAME DT_SNPS_DESIGNWARE_SPI_80010100_BOSCH_BMI160_1_INT_GPIOS_CONTROLLER -#define CONFIG_BMI160_GPIO_PIN_NUM DT_SNPS_DESIGNWARE_SPI_80010100_BOSCH_BMI160_1_INT_GPIOS_PIN -#define CONFIG_BMI160_NAME DT_SNPS_DESIGNWARE_SPI_80010100_BOSCH_BMI160_1_LABEL -#define CONFIG_BMI160_SPI_BUS_FREQ DT_SNPS_DESIGNWARE_SPI_80010100_BOSCH_BMI160_1_SPI_MAX_FREQUENCY +#define DT_BMI160_SLAVE DT_SNPS_DESIGNWARE_SPI_80010100_BOSCH_BMI160_1_BASE_ADDRESS +#define DT_BMI160_SPI_PORT_NAME DT_SNPS_DESIGNWARE_SPI_80010100_BOSCH_BMI160_1_BUS_NAME +#define DT_BMI160_GPIO_DEV_NAME DT_SNPS_DESIGNWARE_SPI_80010100_BOSCH_BMI160_1_INT_GPIOS_CONTROLLER +#define DT_BMI160_GPIO_PIN_NUM DT_SNPS_DESIGNWARE_SPI_80010100_BOSCH_BMI160_1_INT_GPIOS_PIN +#define DT_BMI160_NAME DT_SNPS_DESIGNWARE_SPI_80010100_BOSCH_BMI160_1_LABEL +#define DT_BMI160_SPI_BUS_FREQ DT_SNPS_DESIGNWARE_SPI_80010100_BOSCH_BMI160_1_SPI_MAX_FREQUENCY diff --git a/boards/arc/em_starterkit/arc_mpu_regions.c b/boards/arc/em_starterkit/arc_mpu_regions.c index e357c78e39c..1aaae2b351a 100644 --- a/boards/arc/em_starterkit/arc_mpu_regions.c +++ b/boards/arc/em_starterkit/arc_mpu_regions.c @@ -27,18 +27,18 @@ static struct arc_mpu_region mpu_regions[] = { AUX_MPU_RDP_KW | AUX_MPU_RDP_KR), #else -#if CONFIG_ICCM_SIZE > 0 +#if DT_ICCM_SIZE > 0 /* Region ICCM */ MPU_REGION_ENTRY("ICCM", - CONFIG_ICCM_BASE_ADDRESS, - CONFIG_ICCM_SIZE * 1024, + DT_ICCM_BASE_ADDRESS, + DT_ICCM_SIZE * 1024, REGION_FLASH_ATTR), #endif -#if CONFIG_DCCM_SIZE > 0 +#if DT_DCCM_SIZE > 0 /* Region DCCM */ MPU_REGION_ENTRY("DCCM", - CONFIG_DCCM_BASE_ADDRESS, - CONFIG_DCCM_SIZE * 1024, + DT_DCCM_BASE_ADDRESS, + DT_DCCM_SIZE * 1024, AUX_MPU_RDP_KW | AUX_MPU_RDP_KR), #endif #if CONFIG_SRAM_SIZE > 0 @@ -58,18 +58,18 @@ static struct arc_mpu_region mpu_regions[] = { }; #else /* CONFIG_USERSPACE */ static struct arc_mpu_region mpu_regions[] = { -#if CONFIG_ICCM_SIZE > 0 +#if DT_ICCM_SIZE > 0 /* Region ICCM */ MPU_REGION_ENTRY("ICCM", - CONFIG_ICCM_BASE_ADDRESS, - CONFIG_ICCM_SIZE * 1024, + DT_ICCM_BASE_ADDRESS, + DT_ICCM_SIZE * 1024, REGION_FLASH_ATTR), #endif -#if CONFIG_DCCM_SIZE > 0 +#if DT_DCCM_SIZE > 0 /* Region DCCM */ MPU_REGION_ENTRY("DCCM", - CONFIG_DCCM_BASE_ADDRESS, - CONFIG_DCCM_SIZE * 1024, + DT_DCCM_BASE_ADDRESS, + DT_DCCM_SIZE * 1024, REGION_RAM_ATTR), #endif #if CONFIG_SRAM_SIZE > 0 diff --git a/boards/arc/nsim_em/arc_mpu_regions.c b/boards/arc/nsim_em/arc_mpu_regions.c index 57ddea98228..cdfca1d219e 100644 --- a/boards/arc/nsim_em/arc_mpu_regions.c +++ b/boards/arc/nsim_em/arc_mpu_regions.c @@ -27,18 +27,18 @@ static struct arc_mpu_region mpu_regions[] = { AUX_MPU_RDP_KW | AUX_MPU_RDP_KR), #else -#if CONFIG_ICCM_SIZE > 0 +#if DT_ICCM_SIZE > 0 /* Region ICCM */ MPU_REGION_ENTRY("ICCM", - CONFIG_ICCM_BASE_ADDRESS, - CONFIG_ICCM_SIZE * 1024, + DT_ICCM_BASE_ADDRESS, + DT_ICCM_SIZE * 1024, REGION_FLASH_ATTR), #endif -#if CONFIG_DCCM_SIZE > 0 +#if DT_DCCM_SIZE > 0 /* Region DCCM */ MPU_REGION_ENTRY("DCCM", - CONFIG_DCCM_BASE_ADDRESS, - CONFIG_DCCM_SIZE * 1024, + DT_DCCM_BASE_ADDRESS, + DT_DCCM_SIZE * 1024, AUX_MPU_RDP_KW | AUX_MPU_RDP_KR), #endif #endif /* ARC_MPU_VER == 3 */ @@ -50,18 +50,18 @@ static struct arc_mpu_region mpu_regions[] = { }; #else /* CONFIG_USERSPACE */ static struct arc_mpu_region mpu_regions[] = { -#if CONFIG_ICCM_SIZE > 0 +#if DT_ICCM_SIZE > 0 /* Region ICCM */ MPU_REGION_ENTRY("ICCM", - CONFIG_ICCM_BASE_ADDRESS, - CONFIG_ICCM_SIZE * 1024, + DT_ICCM_BASE_ADDRESS, + DT_ICCM_SIZE * 1024, REGION_FLASH_ATTR), #endif -#if CONFIG_DCCM_SIZE > 0 +#if DT_DCCM_SIZE > 0 /* Region DCCM */ MPU_REGION_ENTRY("DCCM", - CONFIG_DCCM_BASE_ADDRESS, - CONFIG_DCCM_SIZE * 1024, + DT_DCCM_BASE_ADDRESS, + DT_DCCM_SIZE * 1024, REGION_RAM_ATTR), #endif /* Region Peripheral */ diff --git a/boards/arm/96b_argonkey/dts_fixup.h b/boards/arm/96b_argonkey/dts_fixup.h index c2006c2ad37..895b53527b9 100644 --- a/boards/arm/96b_argonkey/dts_fixup.h +++ b/boards/arm/96b_argonkey/dts_fixup.h @@ -9,23 +9,23 @@ * generated data matches the driver definitions. */ -#define CONFIG_HTS221_NAME DT_ST_STM32_I2C_V1_40005800_ST_HTS221_5F_LABEL -#define CONFIG_HTS221_I2C_MASTER_DEV_NAME DT_ST_STM32_I2C_V1_40005800_ST_HTS221_5F_BUS_NAME +#define DT_HTS221_NAME DT_ST_STM32_I2C_V1_40005800_ST_HTS221_5F_LABEL +#define DT_HTS221_I2C_MASTER_DEV_NAME DT_ST_STM32_I2C_V1_40005800_ST_HTS221_5F_BUS_NAME -#define CONFIG_LPS22HB_DEV_NAME DT_ST_STM32_I2C_V1_40005800_ST_LPS22HB_PRESS_5D_LABEL -#define CONFIG_LPS22HB_I2C_ADDR DT_ST_STM32_I2C_V1_40005800_ST_LPS22HB_PRESS_5D_BASE_ADDRESS -#define CONFIG_LPS22HB_I2C_MASTER_DEV_NAME DT_ST_STM32_I2C_V1_40005800_ST_LPS22HB_PRESS_5D_BUS_NAME +#define DT_LPS22HB_DEV_NAME DT_ST_STM32_I2C_V1_40005800_ST_LPS22HB_PRESS_5D_LABEL +#define DT_LPS22HB_I2C_ADDR DT_ST_STM32_I2C_V1_40005800_ST_LPS22HB_PRESS_5D_BASE_ADDRESS +#define DT_LPS22HB_I2C_MASTER_DEV_NAME DT_ST_STM32_I2C_V1_40005800_ST_LPS22HB_PRESS_5D_BUS_NAME -#define CONFIG_VL53L0X_NAME DT_ST_STM32_I2C_V1_40005800_ST_VL53L0X_29_LABEL -#define CONFIG_VL53L0X_I2C_ADDR DT_ST_STM32_I2C_V1_40005800_ST_VL53L0X_29_BASE_ADDRESS -#define CONFIG_VL53L0X_I2C_MASTER_DEV_NAME DT_ST_STM32_I2C_V1_40005800_ST_VL53L0X_29_BUS_NAME +#define DT_VL53L0X_NAME DT_ST_STM32_I2C_V1_40005800_ST_VL53L0X_29_LABEL +#define DT_VL53L0X_I2C_ADDR DT_ST_STM32_I2C_V1_40005800_ST_VL53L0X_29_BASE_ADDRESS +#define DT_VL53L0X_I2C_MASTER_DEV_NAME DT_ST_STM32_I2C_V1_40005800_ST_VL53L0X_29_BUS_NAME -#define CONFIG_LSM6DSL_DEV_NAME DT_ST_STM32_SPI_40003800_ST_LSM6DSL_SPI_1_LABEL -#define CONFIG_LSM6DSL_SPI_SELECT_SLAVE DT_ST_STM32_SPI_40003800_ST_LSM6DSL_SPI_1_BASE_ADDRESS -#define CONFIG_LSM6DSL_SPI_MASTER_DEV_NAME DT_ST_STM32_SPI_40003800_ST_LSM6DSL_SPI_1_BUS_NAME -#define CONFIG_LSM6DSL_SPI_BUS_FREQ DT_ST_STM32_SPI_40003800_ST_LSM6DSL_SPI_1_SPI_MAX_FREQUENCY -#define CONFIG_LSM6DSL_GPIO_DEV_NAME DT_ST_STM32_SPI_40003800_ST_LSM6DSL_SPI_1_IRQ_GPIOS_CONTROLLER -#define CONFIG_LSM6DSL_GPIO_PIN_NUM DT_ST_STM32_SPI_40003800_ST_LSM6DSL_SPI_1_IRQ_GPIOS_PIN +#define DT_LSM6DSL_DEV_NAME DT_ST_STM32_SPI_40003800_ST_LSM6DSL_SPI_1_LABEL +#define DT_LSM6DSL_SPI_SELECT_SLAVE DT_ST_STM32_SPI_40003800_ST_LSM6DSL_SPI_1_BASE_ADDRESS +#define DT_LSM6DSL_SPI_MASTER_DEV_NAME DT_ST_STM32_SPI_40003800_ST_LSM6DSL_SPI_1_BUS_NAME +#define DT_LSM6DSL_SPI_BUS_FREQ DT_ST_STM32_SPI_40003800_ST_LSM6DSL_SPI_1_SPI_MAX_FREQUENCY +#define DT_LSM6DSL_GPIO_DEV_NAME DT_ST_STM32_SPI_40003800_ST_LSM6DSL_SPI_1_IRQ_GPIOS_CONTROLLER +#define DT_LSM6DSL_GPIO_PIN_NUM DT_ST_STM32_SPI_40003800_ST_LSM6DSL_SPI_1_IRQ_GPIOS_PIN #define CONFIG_LP3943_DEV_NAME DT_ST_STM32_I2C_V1_40005C00_TI_LP3943_60_LABEL #define CONFIG_LP3943_I2C_ADDRESS DT_ST_STM32_I2C_V1_40005C00_TI_LP3943_60_BASE_ADDRESS diff --git a/boards/arm/adafruit_feather_m0_basic_proto/pinmux.c b/boards/arm/adafruit_feather_m0_basic_proto/pinmux.c index 4adc145d722..5137e74a7c8 100644 --- a/boards/arm/adafruit_feather_m0_basic_proto/pinmux.c +++ b/boards/arm/adafruit_feather_m0_basic_proto/pinmux.c @@ -9,54 +9,54 @@ static int board_pinmux_init(struct device *dev) { - struct device *muxa = device_get_binding(CONFIG_PINMUX_SAM0_A_LABEL); -#if CONFIG_SPI_SAM0_SERCOM4_BASE_ADDRESS - struct device *muxb = device_get_binding(CONFIG_PINMUX_SAM0_B_LABEL); + struct device *muxa = device_get_binding(DT_PINMUX_SAM0_A_LABEL); +#if DT_SPI_SAM0_SERCOM4_BASE_ADDRESS + struct device *muxb = device_get_binding(DT_PINMUX_SAM0_B_LABEL); #endif ARG_UNUSED(dev); -#if CONFIG_UART_SAM0_SERCOM0_BASE_ADDRESS +#if DT_UART_SAM0_SERCOM0_BASE_ADDRESS /* SERCOM0 on RX=PA11/pad 3, TX=PA10/pad 2 */ pinmux_pin_set(muxa, 11, PINMUX_FUNC_C); pinmux_pin_set(muxa, 10, PINMUX_FUNC_C); #endif -#if CONFIG_UART_SAM0_SERCOM1_BASE_ADDRESS +#if DT_UART_SAM0_SERCOM1_BASE_ADDRESS #error Pin mapping is not configured #endif -#if CONFIG_UART_SAM0_SERCOM2_BASE_ADDRESS +#if DT_UART_SAM0_SERCOM2_BASE_ADDRESS #error Pin mapping is not configured #endif -#if CONFIG_UART_SAM0_SERCOM3_BASE_ADDRESS +#if DT_UART_SAM0_SERCOM3_BASE_ADDRESS #error Pin mapping is not configured #endif -#if CONFIG_UART_SAM0_SERCOM4_BASE_ADDRESS +#if DT_UART_SAM0_SERCOM4_BASE_ADDRESS #error Pin mapping is not configured #endif -#if CONFIG_UART_SAM0_SERCOM5_BASE_ADDRESS +#if DT_UART_SAM0_SERCOM5_BASE_ADDRESS #error Pin mapping is not configured #endif -#if CONFIG_SPI_SAM0_SERCOM4_BASE_ADDRESS +#if DT_SPI_SAM0_SERCOM4_BASE_ADDRESS /* SPI SERCOM4 on MISO=PA12/pad 0, MOSI=PB10/pad 2, SCK=PB11/pad 3 */ pinmux_pin_set(muxa, 12, PINMUX_FUNC_D); pinmux_pin_set(muxb, 10, PINMUX_FUNC_D); pinmux_pin_set(muxb, 11, PINMUX_FUNC_D); #endif -#if CONFIG_SPI_SAM0_SERCOM0_BASE_ADDRESS +#if DT_SPI_SAM0_SERCOM0_BASE_ADDRESS #error Pin mapping is not configured #endif -#if CONFIG_SPI_SAM0_SERCOM1_BASE_ADDRESS +#if DT_SPI_SAM0_SERCOM1_BASE_ADDRESS #error Pin mapping is not configured #endif -#if CONFIG_SPI_SAM0_SERCOM2_BASE_ADDRESS +#if DT_SPI_SAM0_SERCOM2_BASE_ADDRESS #error Pin mapping is not configured #endif -#if CONFIG_SPI_SAM0_SERCOM3_BASE_ADDRESS +#if DT_SPI_SAM0_SERCOM3_BASE_ADDRESS #error Pin mapping is not configured #endif -#if CONFIG_SPI_SAM0_SERCOM5_BASE_ADDRESS +#if DT_SPI_SAM0_SERCOM5_BASE_ADDRESS #error Pin mapping is not configured #endif diff --git a/boards/arm/adafruit_trinket_m0/pinmux.c b/boards/arm/adafruit_trinket_m0/pinmux.c index 477f3bacc7e..0c516a2f92b 100644 --- a/boards/arm/adafruit_trinket_m0/pinmux.c +++ b/boards/arm/adafruit_trinket_m0/pinmux.c @@ -9,58 +9,58 @@ static int board_pinmux_init(struct device *dev) { - struct device *muxa = device_get_binding(CONFIG_PINMUX_SAM0_A_LABEL); + struct device *muxa = device_get_binding(DT_PINMUX_SAM0_A_LABEL); ARG_UNUSED(dev); -#if CONFIG_UART_SAM0_SERCOM0_BASE_ADDRESS +#if DT_UART_SAM0_SERCOM0_BASE_ADDRESS /* SERCOM0 on RX=PA7/pad 3, TX=PA6/pad 2 */ pinmux_pin_set(muxa, 7, PINMUX_FUNC_D); pinmux_pin_set(muxa, 6, PINMUX_FUNC_D); #endif -#if CONFIG_UART_SAM0_SERCOM2_BASE_ADDRESS +#if DT_UART_SAM0_SERCOM2_BASE_ADDRESS /* SERCOM2 on RX=PA9/pad 1, TX=PA8/pad 0 */ pinmux_pin_set(muxa, 9, PINMUX_FUNC_D); pinmux_pin_set(muxa, 8, PINMUX_FUNC_D); #endif -#if CONFIG_UART_SAM0_SERCOM1_BASE_ADDRESS +#if DT_UART_SAM0_SERCOM1_BASE_ADDRESS #error Pin mapping is not configured #endif -#if CONFIG_UART_SAM0_SERCOM3_BASE_ADDRESS +#if DT_UART_SAM0_SERCOM3_BASE_ADDRESS #error Pin mapping is not configured #endif -#if CONFIG_UART_SAM0_SERCOM4_BASE_ADDRESS +#if DT_UART_SAM0_SERCOM4_BASE_ADDRESS #error Pin mapping is not configured #endif -#if CONFIG_UART_SAM0_SERCOM5_BASE_ADDRESS +#if DT_UART_SAM0_SERCOM5_BASE_ADDRESS #error Pin mapping is not configured #endif -#if CONFIG_SPI_SAM0_SERCOM0_BASE_ADDRESS +#if DT_SPI_SAM0_SERCOM0_BASE_ADDRESS /* SPI SERCOM0 on MISO=PA9/pad 1, MOSI=PA6/pad 2, SCK=PA7/pad 3 */ pinmux_pin_set(muxa, 9, PINMUX_FUNC_D); pinmux_pin_set(muxa, 6, PINMUX_FUNC_D); pinmux_pin_set(muxa, 7, PINMUX_FUNC_D); #endif -#if CONFIG_SPI_SAM0_SERCOM1_BASE_ADDRESS +#if DT_SPI_SAM0_SERCOM1_BASE_ADDRESS /* SPI SERCOM1 on MOSI=PA0/pad 0, SCK=PA1/pad 1 */ pinmux_pin_set(muxa, 0, PINMUX_FUNC_D); pinmux_pin_set(muxa, 1, PINMUX_FUNC_D); #endif -#if CONFIG_SPI_SAM0_SERCOM2_BASE_ADDRESS +#if DT_SPI_SAM0_SERCOM2_BASE_ADDRESS #error Pin mapping is not configured #endif -#if CONFIG_SPI_SAM0_SERCOM3_BASE_ADDRESS +#if DT_SPI_SAM0_SERCOM3_BASE_ADDRESS #error Pin mapping is not configured #endif -#if CONFIG_SPI_SAM0_SERCOM4_BASE_ADDRESS +#if DT_SPI_SAM0_SERCOM4_BASE_ADDRESS #error Pin mapping is not configured #endif -#if CONFIG_SPI_SAM0_SERCOM5_BASE_ADDRESS +#if DT_SPI_SAM0_SERCOM5_BASE_ADDRESS #error Pin mapping is not configured #endif diff --git a/boards/arm/arduino_zero/pinmux.c b/boards/arm/arduino_zero/pinmux.c index 214cabd7f9c..ea19e0c9896 100644 --- a/boards/arm/arduino_zero/pinmux.c +++ b/boards/arm/arduino_zero/pinmux.c @@ -9,56 +9,56 @@ static int board_pinmux_init(struct device *dev) { - struct device *muxa = device_get_binding(CONFIG_PINMUX_SAM0_A_LABEL); - struct device *muxb = device_get_binding(CONFIG_PINMUX_SAM0_B_LABEL); + struct device *muxa = device_get_binding(DT_PINMUX_SAM0_A_LABEL); + struct device *muxb = device_get_binding(DT_PINMUX_SAM0_B_LABEL); ARG_UNUSED(dev); -#if CONFIG_UART_SAM0_SERCOM0_BASE_ADDRESS +#if DT_UART_SAM0_SERCOM0_BASE_ADDRESS /* SERCOM0 on RX=PA11, TX=PA10 */ pinmux_pin_set(muxa, 11, PINMUX_FUNC_C); pinmux_pin_set(muxa, 10, PINMUX_FUNC_C); #endif -#if CONFIG_UART_SAM0_SERCOM5_BASE_ADDRESS +#if DT_UART_SAM0_SERCOM5_BASE_ADDRESS /* SERCOM5 on RX=PB23, TX=PB22 */ pinmux_pin_set(muxb, 23, PINMUX_FUNC_D); pinmux_pin_set(muxb, 22, PINMUX_FUNC_D); #endif -#if CONFIG_UART_SAM0_SERCOM1_BASE_ADDRESS +#if DT_UART_SAM0_SERCOM1_BASE_ADDRESS #error Pin mapping is not configured #endif -#if CONFIG_UART_SAM0_SERCOM2_BASE_ADDRESS +#if DT_UART_SAM0_SERCOM2_BASE_ADDRESS #error Pin mapping is not configured #endif -#if CONFIG_UART_SAM0_SERCOM3_BASE_ADDRESS +#if DT_UART_SAM0_SERCOM3_BASE_ADDRESS #error Pin mapping is not configured #endif -#if CONFIG_UART_SAM0_SERCOM4_BASE_ADDRESS +#if DT_UART_SAM0_SERCOM4_BASE_ADDRESS #error Pin mapping is not configured #endif -#if CONFIG_SPI_SAM0_SERCOM4_BASE_ADDRESS +#if DT_SPI_SAM0_SERCOM4_BASE_ADDRESS /* SPI SERCOM4 on MISO=PA12/pad 0, MOSI=PB10/pad 2, SCK=PB11/pad 3 */ pinmux_pin_set(muxa, 12, PINMUX_FUNC_D); pinmux_pin_set(muxb, 10, PINMUX_FUNC_D); pinmux_pin_set(muxb, 11, PINMUX_FUNC_D); #endif -#if CONFIG_SPI_SAM0_SERCOM0_BASE_ADDRESS +#if DT_SPI_SAM0_SERCOM0_BASE_ADDRESS #error Pin mapping is not configured #endif -#if CONFIG_SPI_SAM0_SERCOM1_BASE_ADDRESS +#if DT_SPI_SAM0_SERCOM1_BASE_ADDRESS #error Pin mapping is not configured #endif -#if CONFIG_SPI_SAM0_SERCOM2_BASE_ADDRESS +#if DT_SPI_SAM0_SERCOM2_BASE_ADDRESS #error Pin mapping is not configured #endif -#if CONFIG_SPI_SAM0_SERCOM3_BASE_ADDRESS +#if DT_SPI_SAM0_SERCOM3_BASE_ADDRESS #error Pin mapping is not configured #endif -#if CONFIG_SPI_SAM0_SERCOM5_BASE_ADDRESS +#if DT_SPI_SAM0_SERCOM5_BASE_ADDRESS #error Pin mapping is not configured #endif diff --git a/boards/arm/atsamd20_xpro/pinmux.c b/boards/arm/atsamd20_xpro/pinmux.c index 86eef9c5f06..29a005d3d88 100644 --- a/boards/arm/atsamd20_xpro/pinmux.c +++ b/boards/arm/atsamd20_xpro/pinmux.c @@ -9,52 +9,52 @@ static int board_pinmux_init(struct device *dev) { - struct device *muxa = device_get_binding(CONFIG_PINMUX_SAM0_A_LABEL); - struct device *muxb = device_get_binding(CONFIG_PINMUX_SAM0_B_LABEL); + struct device *muxa = device_get_binding(DT_PINMUX_SAM0_A_LABEL); + struct device *muxb = device_get_binding(DT_PINMUX_SAM0_B_LABEL); ARG_UNUSED(dev); -#if CONFIG_UART_SAM0_SERCOM0_BASE_ADDRESS +#if DT_UART_SAM0_SERCOM0_BASE_ADDRESS #error Pin mapping is not configured #endif -#if CONFIG_UART_SAM0_SERCOM1_BASE_ADDRESS +#if DT_UART_SAM0_SERCOM1_BASE_ADDRESS #error Pin mapping is not configured #endif -#if CONFIG_UART_SAM0_SERCOM2_BASE_ADDRESS +#if DT_UART_SAM0_SERCOM2_BASE_ADDRESS #error Pin mapping is not configured #endif -#if CONFIG_UART_SAM0_SERCOM3_BASE_ADDRESS +#if DT_UART_SAM0_SERCOM3_BASE_ADDRESS /* SERCOM3 on RX=PA25, TX=PA24 */ pinmux_pin_set(muxa, 24, PINMUX_FUNC_C); pinmux_pin_set(muxa, 25, PINMUX_FUNC_C); #endif -#if CONFIG_UART_SAM0_SERCOM4_BASE_ADDRESS +#if DT_UART_SAM0_SERCOM4_BASE_ADDRESS pinmux_pin_set(muxb, 8, PINMUX_FUNC_D); pinmux_pin_set(muxb, 9, PINMUX_FUNC_D); #endif -#if CONFIG_UART_SAM0_SERCOM5_BASE_ADDRESS +#if DT_UART_SAM0_SERCOM5_BASE_ADDRESS #error Pin mapping is not configured #endif -#if CONFIG_SPI_SAM0_SERCOM0_BASE_ADDRESS +#if DT_SPI_SAM0_SERCOM0_BASE_ADDRESS /* SPI SERCOM0 on MISO=PA04, MOSI=PA06, SCK=PA07 */ pinmux_pin_set(muxa, 4, PINMUX_FUNC_D); pinmux_pin_set(muxa, 6, PINMUX_FUNC_D); pinmux_pin_set(muxa, 7, PINMUX_FUNC_D); #endif -#if CONFIG_SPI_SAM0_SERCOM1_BASE_ADDRESS +#if DT_SPI_SAM0_SERCOM1_BASE_ADDRESS #error Pin mapping is not configured #endif -#if CONFIG_SPI_SAM0_SERCOM2_BASE_ADDRESS +#if DT_SPI_SAM0_SERCOM2_BASE_ADDRESS #error Pin mapping is not configured #endif -#if CONFIG_SPI_SAM0_SERCOM3_BASE_ADDRESS +#if DT_SPI_SAM0_SERCOM3_BASE_ADDRESS #error Pin mapping is not configured #endif -#if CONFIG_SPI_SAM0_SERCOM4_BASE_ADDRESS +#if DT_SPI_SAM0_SERCOM4_BASE_ADDRESS #error Pin mapping is not configured #endif -#if CONFIG_SPI_SAM0_SERCOM5_BASE_ADDRESS +#if DT_SPI_SAM0_SERCOM5_BASE_ADDRESS #error Pin mapping is not configured #endif diff --git a/boards/arm/atsamd21_xpro/pinmux.c b/boards/arm/atsamd21_xpro/pinmux.c index 5ea40330ba1..cd77551a260 100644 --- a/boards/arm/atsamd21_xpro/pinmux.c +++ b/boards/arm/atsamd21_xpro/pinmux.c @@ -9,52 +9,52 @@ static int board_pinmux_init(struct device *dev) { - struct device *muxa = device_get_binding(CONFIG_PINMUX_SAM0_A_LABEL); - struct device *muxb = device_get_binding(CONFIG_PINMUX_SAM0_B_LABEL); + struct device *muxa = device_get_binding(DT_PINMUX_SAM0_A_LABEL); + struct device *muxb = device_get_binding(DT_PINMUX_SAM0_B_LABEL); ARG_UNUSED(dev); -#if CONFIG_UART_SAM0_SERCOM0_BASE_ADDRESS +#if DT_UART_SAM0_SERCOM0_BASE_ADDRESS /* SERCOM0 on RX=PA11, TX=PA10 */ pinmux_pin_set(muxa, 11, PINMUX_FUNC_C); pinmux_pin_set(muxa, 10, PINMUX_FUNC_C); #endif -#if CONFIG_UART_SAM0_SERCOM1_BASE_ADDRESS +#if DT_UART_SAM0_SERCOM1_BASE_ADDRESS /* SERCOM3 ON RX=PA19, TX=PA16 */ pinmux_pin_set(muxa, 19, PINMUX_FUNC_C); pinmux_pin_set(muxa, 16, PINMUX_FUNC_C); #endif -#if CONFIG_UART_SAM0_SERCOM2_BASE_ADDRESS +#if DT_UART_SAM0_SERCOM2_BASE_ADDRESS #error Pin mapping is not configured #endif -#if CONFIG_UART_SAM0_SERCOM3_BASE_ADDRESS +#if DT_UART_SAM0_SERCOM3_BASE_ADDRESS /* SERCOM3 ON RX=PA23, TX=PA22 */ pinmux_pin_set(muxa, 23, PINMUX_FUNC_C); pinmux_pin_set(muxa, 22, PINMUX_FUNC_C); #endif -#if CONFIG_UART_SAM0_SERCOM4_BASE_ADDRESS +#if DT_UART_SAM0_SERCOM4_BASE_ADDRESS #error Pin mapping is not configured #endif -#if CONFIG_UART_SAM0_SERCOM5_BASE_ADDRESS +#if DT_UART_SAM0_SERCOM5_BASE_ADDRESS #error Pin mapping is not configured #endif -#if CONFIG_SPI_SAM0_SERCOM0_BASE_ADDRESS +#if DT_SPI_SAM0_SERCOM0_BASE_ADDRESS #error Pin mapping is not configured #endif -#if CONFIG_SPI_SAM0_SERCOM1_BASE_ADDRESS +#if DT_SPI_SAM0_SERCOM1_BASE_ADDRESS #error Pin mapping is not configured #endif -#if CONFIG_SPI_SAM0_SERCOM2_BASE_ADDRESS +#if DT_SPI_SAM0_SERCOM2_BASE_ADDRESS #error Pin mapping is not configured #endif -#if CONFIG_SPI_SAM0_SERCOM3_BASE_ADDRESS +#if DT_SPI_SAM0_SERCOM3_BASE_ADDRESS #error Pin mapping is not configured #endif -#if CONFIG_SPI_SAM0_SERCOM4_BASE_ADDRESS +#if DT_SPI_SAM0_SERCOM4_BASE_ADDRESS #error Pin mapping is not configured #endif -#if CONFIG_SPI_SAM0_SERCOM5_BASE_ADDRESS +#if DT_SPI_SAM0_SERCOM5_BASE_ADDRESS /* SPI SERCOM5 on MISO=PB16/pad 0, MOSI=PB22/pad 2, SCK=PB23/pad 3 */ pinmux_pin_set(muxb, 16, PINMUX_FUNC_C); pinmux_pin_set(muxb, 22, PINMUX_FUNC_D); diff --git a/boards/arm/bbc_microbit/dts_fixup.h b/boards/arm/bbc_microbit/dts_fixup.h index aa18574defb..986731c844b 100644 --- a/boards/arm/bbc_microbit/dts_fixup.h +++ b/boards/arm/bbc_microbit/dts_fixup.h @@ -4,8 +4,8 @@ * SPDX-License-Identifier: Apache-2.0 */ -#define CONFIG_FXOS8700_NAME DT_NORDIC_NRF_I2C_40003000_NXP_FXOS8700_1D_LABEL -#define CONFIG_FXOS8700_I2C_NAME DT_NORDIC_NRF_I2C_40003000_NXP_FXOS8700_1D_BUS_NAME -#define CONFIG_FXOS8700_I2C_ADDRESS DT_NORDIC_NRF_I2C_40003000_NXP_FXOS8700_1D_BASE_ADDRESS -#define CONFIG_FXOS8700_GPIO_NAME DT_NORDIC_NRF_I2C_40003000_NXP_FXOS8700_1D_INT2_GPIOS_CONTROLLER -#define CONFIG_FXOS8700_GPIO_PIN DT_NORDIC_NRF_I2C_40003000_NXP_FXOS8700_1D_INT2_GPIOS_PIN +#define DT_FXOS8700_NAME DT_NORDIC_NRF_I2C_40003000_NXP_FXOS8700_1D_LABEL +#define DT_FXOS8700_I2C_NAME DT_NORDIC_NRF_I2C_40003000_NXP_FXOS8700_1D_BUS_NAME +#define DT_FXOS8700_I2C_ADDRESS DT_NORDIC_NRF_I2C_40003000_NXP_FXOS8700_1D_BASE_ADDRESS +#define DT_FXOS8700_GPIO_NAME DT_NORDIC_NRF_I2C_40003000_NXP_FXOS8700_1D_INT2_GPIOS_CONTROLLER +#define DT_FXOS8700_GPIO_PIN DT_NORDIC_NRF_I2C_40003000_NXP_FXOS8700_1D_INT2_GPIOS_PIN diff --git a/boards/arm/disco_l475_iot1/dts_fixup.h b/boards/arm/disco_l475_iot1/dts_fixup.h index efadd935b31..18b319322eb 100644 --- a/boards/arm/disco_l475_iot1/dts_fixup.h +++ b/boards/arm/disco_l475_iot1/dts_fixup.h @@ -4,27 +4,27 @@ * generated data matches the driver definitions. */ -#define CONFIG_HTS221_NAME DT_ST_STM32_I2C_V2_40005800_ST_HTS221_5F_LABEL -#define CONFIG_HTS221_I2C_MASTER_DEV_NAME DT_ST_STM32_I2C_V2_40005800_ST_HTS221_5F_BUS_NAME +#define DT_HTS221_NAME DT_ST_STM32_I2C_V2_40005800_ST_HTS221_5F_LABEL +#define DT_HTS221_I2C_MASTER_DEV_NAME DT_ST_STM32_I2C_V2_40005800_ST_HTS221_5F_BUS_NAME -#define CONFIG_LIS3MDL_NAME DT_ST_STM32_I2C_V2_40005800_ST_LIS3MDL_MAGN_1E_LABEL -#define CONFIG_LIS3MDL_I2C_ADDR DT_ST_STM32_I2C_V2_40005800_ST_LIS3MDL_MAGN_1E_BASE_ADDRESS -#define CONFIG_LIS3MDL_I2C_MASTER_DEV_NAME DT_ST_STM32_I2C_V2_40005800_ST_LIS3MDL_MAGN_1E_BUS_NAME +#define DT_LIS3MDL_NAME DT_ST_STM32_I2C_V2_40005800_ST_LIS3MDL_MAGN_1E_LABEL +#define DT_LIS3MDL_I2C_ADDR DT_ST_STM32_I2C_V2_40005800_ST_LIS3MDL_MAGN_1E_BASE_ADDRESS +#define DT_LIS3MDL_I2C_MASTER_DEV_NAME DT_ST_STM32_I2C_V2_40005800_ST_LIS3MDL_MAGN_1E_BUS_NAME -#define CONFIG_LSM6DSL_DEV_NAME DT_ST_STM32_I2C_V2_40005800_ST_LSM6DSL_6A_LABEL -#define CONFIG_LSM6DSL_I2C_ADDR DT_ST_STM32_I2C_V2_40005800_ST_LSM6DSL_6A_BASE_ADDRESS -#define CONFIG_LSM6DSL_I2C_MASTER_DEV_NAME DT_ST_STM32_I2C_V2_40005800_ST_LSM6DSL_6A_BUS_NAME +#define DT_LSM6DSL_DEV_NAME DT_ST_STM32_I2C_V2_40005800_ST_LSM6DSL_6A_LABEL +#define DT_LSM6DSL_I2C_ADDR DT_ST_STM32_I2C_V2_40005800_ST_LSM6DSL_6A_BASE_ADDRESS +#define DT_LSM6DSL_I2C_MASTER_DEV_NAME DT_ST_STM32_I2C_V2_40005800_ST_LSM6DSL_6A_BUS_NAME -#define CONFIG_LPS22HB_DEV_NAME DT_ST_STM32_I2C_V2_40005800_ST_LPS22HB_PRESS_5D_LABEL -#define CONFIG_LPS22HB_I2C_ADDR DT_ST_STM32_I2C_V2_40005800_ST_LPS22HB_PRESS_5D_BASE_ADDRESS -#define CONFIG_LPS22HB_I2C_MASTER_DEV_NAME DT_ST_STM32_I2C_V2_40005800_ST_LPS22HB_PRESS_5D_BUS_NAME +#define DT_LPS22HB_DEV_NAME DT_ST_STM32_I2C_V2_40005800_ST_LPS22HB_PRESS_5D_LABEL +#define DT_LPS22HB_I2C_ADDR DT_ST_STM32_I2C_V2_40005800_ST_LPS22HB_PRESS_5D_BASE_ADDRESS +#define DT_LPS22HB_I2C_MASTER_DEV_NAME DT_ST_STM32_I2C_V2_40005800_ST_LPS22HB_PRESS_5D_BUS_NAME #define CONFIG_BT_SPI_DEV_NAME DT_ST_STM32_SPI_FIFO_40003C00_ST_SPBTLE_RF_0_BUS_NAME #define CONFIG_BT_SPI_MAX_CLK_FREQ DT_ST_STM32_SPI_FIFO_40003C00_ST_SPBTLE_RF_0_SPI_MAX_FREQUENCY -#define CONFIG_VL53L0X_NAME DT_ST_STM32_I2C_V2_40005800_ST_VL53L0X_29_LABEL -#define CONFIG_VL53L0X_I2C_ADDR DT_ST_STM32_I2C_V2_40005800_ST_VL53L0X_29_BASE_ADDRESS -#define CONFIG_VL53L0X_I2C_MASTER_DEV_NAME DT_ST_STM32_I2C_V2_40005800_ST_VL53L0X_29_BUS_NAME +#define DT_VL53L0X_NAME DT_ST_STM32_I2C_V2_40005800_ST_VL53L0X_29_LABEL +#define DT_VL53L0X_I2C_ADDR DT_ST_STM32_I2C_V2_40005800_ST_VL53L0X_29_BASE_ADDRESS +#define DT_VL53L0X_I2C_MASTER_DEV_NAME DT_ST_STM32_I2C_V2_40005800_ST_VL53L0X_29_BUS_NAME #define CONFIG_BT_SPI_IRQ_DEV_NAME BT_IRQ_GPIOS_CONTROLLER #define CONFIG_BT_SPI_IRQ_PIN BT_IRQ_GPIOS_PIN @@ -33,5 +33,5 @@ #define CONFIG_BT_SPI_RESET_DEV_NAME BT_RESET_GPIOS_CONTROLLER #define CONFIG_BT_SPI_RESET_PIN BT_RESET_GPIOS_PIN -#define ESWIFI0_CS_GPIOS_CONTROLLER DT_ST_STM32_SPI_FIFO_40003C00_CS_GPIOS_CONTROLLER_1 -#define ESWIFI0_CS_GPIOS_PIN DT_ST_STM32_SPI_FIFO_40003C00_CS_GPIOS_PIN_1 +#define DT_ESWIFI0_CS_GPIOS_CONTROLLER DT_ST_STM32_SPI_FIFO_40003C00_CS_GPIOS_CONTROLLER_1 +#define DT_ESWIFI0_CS_GPIOS_PIN DT_ST_STM32_SPI_FIFO_40003C00_CS_GPIOS_PIN_1 diff --git a/boards/arm/efm32hg_slstk3400a/board.h b/boards/arm/efm32hg_slstk3400a/board.h index 1104f68a1d9..f416e6918d3 100644 --- a/boards/arm/efm32hg_slstk3400a/board.h +++ b/boards/arm/efm32hg_slstk3400a/board.h @@ -10,7 +10,7 @@ #include /* This pin is used to enable the serial port using the board controller */ -#define BC_ENABLE_GPIO_NAME CONFIG_GPIO_GECKO_PORTA_NAME +#define BC_ENABLE_GPIO_NAME DT_GPIO_GECKO_PORTA_NAME #define BC_ENABLE_GPIO_PIN 9 #endif /* __INC_BOARD_H */ diff --git a/boards/arm/efm32wg_stk3800/board.h b/boards/arm/efm32wg_stk3800/board.h index d69eaba7564..ebe6fa17869 100644 --- a/boards/arm/efm32wg_stk3800/board.h +++ b/boards/arm/efm32wg_stk3800/board.h @@ -10,7 +10,7 @@ #include /* This pin is used to enable the serial port using the board controller */ -#define BC_ENABLE_GPIO_NAME CONFIG_GPIO_GECKO_PORTF_NAME +#define BC_ENABLE_GPIO_NAME DT_GPIO_GECKO_PORTF_NAME #define BC_ENABLE_GPIO_PIN 7 #endif /* __INC_BOARD_H */ diff --git a/boards/arm/efr32_slwstk6061a/board.h b/boards/arm/efr32_slwstk6061a/board.h index 077c5f24c0b..b2701c0be1b 100644 --- a/boards/arm/efr32_slwstk6061a/board.h +++ b/boards/arm/efr32_slwstk6061a/board.h @@ -10,7 +10,7 @@ #include /* This pin is used to enable the serial port using the board controller */ -#define BC_ENABLE_GPIO_NAME CONFIG_GPIO_GECKO_PORTA_NAME +#define BC_ENABLE_GPIO_NAME DT_GPIO_GECKO_PORTA_NAME #define BC_ENABLE_GPIO_PIN 5 #endif /* __INC_BOARD_H */ diff --git a/boards/arm/frdm_k64f/dts_fixup.h b/boards/arm/frdm_k64f/dts_fixup.h index 2e83e718a97..f70cd43efe6 100644 --- a/boards/arm/frdm_k64f/dts_fixup.h +++ b/boards/arm/frdm_k64f/dts_fixup.h @@ -1,8 +1,8 @@ -#define CONFIG_FXOS8700_NAME DT_NXP_KINETIS_I2C_40066000_NXP_FXOS8700_1D_LABEL -#define CONFIG_FXOS8700_I2C_NAME DT_NXP_KINETIS_I2C_40066000_NXP_FXOS8700_1D_BUS_NAME -#define CONFIG_FXOS8700_I2C_ADDRESS DT_NXP_KINETIS_I2C_40066000_NXP_FXOS8700_1D_BASE_ADDRESS -#define CONFIG_FXOS8700_GPIO_NAME DT_NXP_KINETIS_I2C_40066000_NXP_FXOS8700_1D_INT2_GPIOS_CONTROLLER -#define CONFIG_FXOS8700_GPIO_PIN DT_NXP_KINETIS_I2C_40066000_NXP_FXOS8700_1D_INT2_GPIOS_PIN +#define DT_FXOS8700_NAME DT_NXP_KINETIS_I2C_40066000_NXP_FXOS8700_1D_LABEL +#define DT_FXOS8700_I2C_NAME DT_NXP_KINETIS_I2C_40066000_NXP_FXOS8700_1D_BUS_NAME +#define DT_FXOS8700_I2C_ADDRESS DT_NXP_KINETIS_I2C_40066000_NXP_FXOS8700_1D_BASE_ADDRESS +#define DT_FXOS8700_GPIO_NAME DT_NXP_KINETIS_I2C_40066000_NXP_FXOS8700_1D_INT2_GPIOS_CONTROLLER +#define DT_FXOS8700_GPIO_PIN DT_NXP_KINETIS_I2C_40066000_NXP_FXOS8700_1D_INT2_GPIOS_PIN #define CONFIG_IEEE802154_MCR20A_SPI_DRV_NAME DT_NXP_KINETIS_DSPI_4002C000_NXP_MCR20A_0_BUS_NAME #define CONFIG_IEEE802154_MCR20A_SPI_SLAVE DT_NXP_KINETIS_DSPI_4002C000_NXP_MCR20A_0_BASE_ADDRESS diff --git a/boards/arm/frdm_kl25z/dts_fixup.h b/boards/arm/frdm_kl25z/dts_fixup.h index 3b36763de5f..ec2e64c54b9 100644 --- a/boards/arm/frdm_kl25z/dts_fixup.h +++ b/boards/arm/frdm_kl25z/dts_fixup.h @@ -4,8 +4,8 @@ * SPDX-License-Identifier: Apache-2.0 */ -#define CONFIG_FXOS8700_NAME DT_NXP_KINETIS_I2C_40066000_NXP_FXOS8700_1D_LABEL -#define CONFIG_FXOS8700_I2C_NAME DT_NXP_KINETIS_I2C_40066000_NXP_FXOS8700_1D_BUS_NAME -#define CONFIG_FXOS8700_I2C_ADDRESS DT_NXP_KINETIS_I2C_40066000_NXP_FXOS8700_1D_BASE_ADDRESS -#define CONFIG_FXOS8700_GPIO_NAME DT_NXP_KINETIS_I2C_40066000_NXP_FXOS8700_1D_INT2_GPIOS_CONTROLLER -#define CONFIG_FXOS8700_GPIO_PIN DT_NXP_KINETIS_I2C_40066000_NXP_FXOS8700_1D_INT2_GPIOS_PIN +#define DT_FXOS8700_NAME DT_NXP_KINETIS_I2C_40066000_NXP_FXOS8700_1D_LABEL +#define DT_FXOS8700_I2C_NAME DT_NXP_KINETIS_I2C_40066000_NXP_FXOS8700_1D_BUS_NAME +#define DT_FXOS8700_I2C_ADDRESS DT_NXP_KINETIS_I2C_40066000_NXP_FXOS8700_1D_BASE_ADDRESS +#define DT_FXOS8700_GPIO_NAME DT_NXP_KINETIS_I2C_40066000_NXP_FXOS8700_1D_INT2_GPIOS_CONTROLLER +#define DT_FXOS8700_GPIO_PIN DT_NXP_KINETIS_I2C_40066000_NXP_FXOS8700_1D_INT2_GPIOS_PIN diff --git a/boards/arm/frdm_kw41z/dts_fixup.h b/boards/arm/frdm_kw41z/dts_fixup.h index 200adf0f4fe..adc41ae0d3d 100644 --- a/boards/arm/frdm_kw41z/dts_fixup.h +++ b/boards/arm/frdm_kw41z/dts_fixup.h @@ -1,5 +1,5 @@ -#define CONFIG_FXOS8700_NAME DT_NXP_KINETIS_I2C_40067000_NXP_FXOS8700_1F_LABEL -#define CONFIG_FXOS8700_I2C_NAME DT_NXP_KINETIS_I2C_40067000_NXP_FXOS8700_1F_BUS_NAME -#define CONFIG_FXOS8700_I2C_ADDRESS DT_NXP_KINETIS_I2C_40067000_NXP_FXOS8700_1F_BASE_ADDRESS -#define CONFIG_FXOS8700_GPIO_NAME DT_NXP_KINETIS_I2C_40067000_NXP_FXOS8700_1F_INT1_GPIOS_CONTROLLER -#define CONFIG_FXOS8700_GPIO_PIN DT_NXP_KINETIS_I2C_40067000_NXP_FXOS8700_1F_INT1_GPIOS_PIN +#define DT_FXOS8700_NAME DT_NXP_KINETIS_I2C_40067000_NXP_FXOS8700_1F_LABEL +#define DT_FXOS8700_I2C_NAME DT_NXP_KINETIS_I2C_40067000_NXP_FXOS8700_1F_BUS_NAME +#define DT_FXOS8700_I2C_ADDRESS DT_NXP_KINETIS_I2C_40067000_NXP_FXOS8700_1F_BASE_ADDRESS +#define DT_FXOS8700_GPIO_NAME DT_NXP_KINETIS_I2C_40067000_NXP_FXOS8700_1F_INT1_GPIOS_CONTROLLER +#define DT_FXOS8700_GPIO_PIN DT_NXP_KINETIS_I2C_40067000_NXP_FXOS8700_1F_INT1_GPIOS_PIN diff --git a/boards/arm/hexiwear_k64/dts_fixup.h b/boards/arm/hexiwear_k64/dts_fixup.h index ede17c14c32..7adc724ffb1 100644 --- a/boards/arm/hexiwear_k64/dts_fixup.h +++ b/boards/arm/hexiwear_k64/dts_fixup.h @@ -1,15 +1,15 @@ -#define CONFIG_FXOS8700_NAME DT_NXP_KINETIS_I2C_40067000_NXP_FXOS8700_1E_LABEL -#define CONFIG_FXOS8700_I2C_NAME DT_NXP_KINETIS_I2C_40067000_NXP_FXOS8700_1E_BUS_NAME -#define CONFIG_FXOS8700_I2C_ADDRESS DT_NXP_KINETIS_I2C_40067000_NXP_FXOS8700_1E_BASE_ADDRESS -#define CONFIG_FXOS8700_GPIO_NAME DT_NXP_KINETIS_I2C_40067000_NXP_FXOS8700_1E_INT2_GPIOS_CONTROLLER -#define CONFIG_FXOS8700_GPIO_PIN DT_NXP_KINETIS_I2C_40067000_NXP_FXOS8700_1E_INT2_GPIOS_PIN +#define DT_FXOS8700_NAME DT_NXP_KINETIS_I2C_40067000_NXP_FXOS8700_1E_LABEL +#define DT_FXOS8700_I2C_NAME DT_NXP_KINETIS_I2C_40067000_NXP_FXOS8700_1E_BUS_NAME +#define DT_FXOS8700_I2C_ADDRESS DT_NXP_KINETIS_I2C_40067000_NXP_FXOS8700_1E_BASE_ADDRESS +#define DT_FXOS8700_GPIO_NAME DT_NXP_KINETIS_I2C_40067000_NXP_FXOS8700_1E_INT2_GPIOS_CONTROLLER +#define DT_FXOS8700_GPIO_PIN DT_NXP_KINETIS_I2C_40067000_NXP_FXOS8700_1E_INT2_GPIOS_PIN -#define CONFIG_FXAS21002_NAME DT_NXP_KINETIS_I2C_40067000_NXP_FXAS21002_20_LABEL -#define CONFIG_FXAS21002_I2C_NAME DT_NXP_KINETIS_I2C_40067000_NXP_FXAS21002_20_BUS_NAME -#define CONFIG_FXAS21002_I2C_ADDRESS DT_NXP_KINETIS_I2C_40067000_NXP_FXAS21002_20_BASE_ADDRESS -#define CONFIG_FXAS21002_GPIO_NAME DT_NXP_KINETIS_I2C_40067000_NXP_FXAS21002_20_INT2_GPIOS_CONTROLLER -#define CONFIG_FXAS21002_GPIO_PIN DT_NXP_KINETIS_I2C_40067000_NXP_FXAS21002_20_INT2_GPIOS_PIN +#define DT_FXAS21002_NAME DT_NXP_KINETIS_I2C_40067000_NXP_FXAS21002_20_LABEL +#define DT_FXAS21002_I2C_NAME DT_NXP_KINETIS_I2C_40067000_NXP_FXAS21002_20_BUS_NAME +#define DT_FXAS21002_I2C_ADDRESS DT_NXP_KINETIS_I2C_40067000_NXP_FXAS21002_20_BASE_ADDRESS +#define DT_FXAS21002_GPIO_NAME DT_NXP_KINETIS_I2C_40067000_NXP_FXAS21002_20_INT2_GPIOS_CONTROLLER +#define DT_FXAS21002_GPIO_PIN DT_NXP_KINETIS_I2C_40067000_NXP_FXAS21002_20_INT2_GPIOS_PIN -#define CONFIG_MAX30101_NAME DT_NXP_KINETIS_I2C_40066000_MAX_MAX30101_57_LABEL -#define CONFIG_MAX30101_I2C_NAME DT_NXP_KINETIS_I2C_40066000_MAX_MAX30101_57_BUS_NAME -#define CONFIG_MAX30101_I2C_ADDRESS DT_NXP_KINETIS_I2C_40066000_MAX_MAX30101_57_BASE_ADDRESS +#define DT_MAX30101_NAME DT_NXP_KINETIS_I2C_40066000_MAX_MAX30101_57_LABEL +#define DT_MAX30101_I2C_NAME DT_NXP_KINETIS_I2C_40066000_MAX_MAX30101_57_BUS_NAME +#define DT_MAX30101_I2C_ADDRESS DT_NXP_KINETIS_I2C_40066000_MAX_MAX30101_57_BASE_ADDRESS diff --git a/boards/arm/mps2_an385/dts_fixup.h b/boards/arm/mps2_an385/dts_fixup.h index d37dd435539..17d6e9309ed 100644 --- a/boards/arm/mps2_an385/dts_fixup.h +++ b/boards/arm/mps2_an385/dts_fixup.h @@ -1,81 +1,81 @@ /* SoC level DTS fixup file */ -#define CONFIG_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS +#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS /* CMSDK APB Timers */ -#define CMSDK_APB_TIMER0 DT_ARM_CMSDK_TIMER_40000000_BASE_ADDRESS -#define CMSDK_APB_TIMER_0_IRQ DT_ARM_CMSDK_TIMER_40000000_IRQ_0 +#define DT_CMSDK_APB_TIMER0 DT_ARM_CMSDK_TIMER_40000000_BASE_ADDRESS +#define DT_CMSDK_APB_TIMER_0_IRQ DT_ARM_CMSDK_TIMER_40000000_IRQ_0 -#define CMSDK_APB_TIMER1 DT_ARM_CMSDK_TIMER_40001000_BASE_ADDRESS -#define CMSDK_APB_TIMER_1_IRQ IRQ_TIMER1 DT_ARM_CMSDK_TIMER_40001000_IRQ_0 +#define DT_CMSDK_APB_TIMER1 DT_ARM_CMSDK_TIMER_40001000_BASE_ADDRESS +#define DT_CMSDK_APB_TIMER_1_IRQ IRQ_TIMER1 DT_ARM_CMSDK_TIMER_40001000_IRQ_0 /* CMSDK APB Dual Timer */ -#define CMSDK_APB_DTIMER DT_ARM_CMSDK_DTIMER_40002000_BASE_ADDRESS -#define CMSDK_APB_DUALTIMER_IRQ DT_ARM_CMSDK_DTIMER_40002000_IRQ_0 +#define DT_CMSDK_APB_DTIMER DT_ARM_CMSDK_DTIMER_40002000_BASE_ADDRESS +#define DT_CMSDK_APB_DUALTIMER_IRQ DT_ARM_CMSDK_DTIMER_40002000_IRQ_0 /* CMSDK APB Universal Asynchronous Receiver-Transmitter (UART) */ -#define CMSDK_APB_UART0 DT_ARM_CMSDK_UART_40004000_BASE_ADDRESS -#define CMSDK_APB_UART_0_IRQ_TX DT_ARM_CMSDK_UART_40004000_IRQ_0 -#define CMSDK_APB_UART_0_IRQ_RX DT_ARM_CMSDK_UART_40004000_IRQ_1 -#define CONFIG_UART_CMSDK_APB_PORT0_IRQ_PRI DT_ARM_CMSDK_UART_40004000_IRQ_0_PRIORITY -#define CONFIG_UART_CMSDK_APB_PORT0_BAUD_RATE DT_ARM_CMSDK_UART_40004000_CURRENT_SPEED -#define CONFIG_UART_CMSDK_APB_PORT0_NAME DT_ARM_CMSDK_UART_40004000_LABEL +#define DT_CMSDK_APB_UART0 DT_ARM_CMSDK_UART_40004000_BASE_ADDRESS +#define DT_CMSDK_APB_UART_0_IRQ_TX DT_ARM_CMSDK_UART_40004000_IRQ_0 +#define DT_CMSDK_APB_UART_0_IRQ_RX DT_ARM_CMSDK_UART_40004000_IRQ_1 +#define DT_UART_CMSDK_APB_PORT0_IRQ_PRI DT_ARM_CMSDK_UART_40004000_IRQ_0_PRIORITY +#define DT_UART_CMSDK_APB_PORT0_BAUD_RATE DT_ARM_CMSDK_UART_40004000_CURRENT_SPEED +#define DT_UART_CMSDK_APB_PORT0_NAME DT_ARM_CMSDK_UART_40004000_LABEL -#define CMSDK_APB_UART1 DT_ARM_CMSDK_UART_40005000_BASE_ADDRESS -#define CMSDK_APB_UART_1_IRQ_TX DT_ARM_CMSDK_UART_40005000_IRQ_0 -#define CMSDK_APB_UART_1_IRQ_RX DT_ARM_CMSDK_UART_40005000_IRQ_1 -#define CONFIG_UART_CMSDK_APB_PORT1_IRQ_PRI DT_ARM_CMSDK_UART_40005000_IRQ_0_PRIORITY -#define CONFIG_UART_CMSDK_APB_PORT1_BAUD_RATE DT_ARM_CMSDK_UART_40005000_CURRENT_SPEED -#define CONFIG_UART_CMSDK_APB_PORT1_NAME DT_ARM_CMSDK_UART_40005000_LABEL +#define DT_CMSDK_APB_UART1 DT_ARM_CMSDK_UART_40005000_BASE_ADDRESS +#define DT_CMSDK_APB_UART_1_IRQ_TX DT_ARM_CMSDK_UART_40005000_IRQ_0 +#define DT_CMSDK_APB_UART_1_IRQ_RX DT_ARM_CMSDK_UART_40005000_IRQ_1 +#define DT_UART_CMSDK_APB_PORT1_IRQ_PRI DT_ARM_CMSDK_UART_40005000_IRQ_0_PRIORITY +#define DT_UART_CMSDK_APB_PORT1_BAUD_RATE DT_ARM_CMSDK_UART_40005000_CURRENT_SPEED +#define DT_UART_CMSDK_APB_PORT1_NAME DT_ARM_CMSDK_UART_40005000_LABEL -#define CMSDK_APB_UART2 DT_ARM_CMSDK_UART_40006000_BASE_ADDRESS -#define CMSDK_APB_UART_2_IRQ_TX DT_ARM_CMSDK_UART_40006000_IRQ_0 -#define CMSDK_APB_UART_2_IRQ_RX DT_ARM_CMSDK_UART_40006000_IRQ_1 -#define CONFIG_UART_CMSDK_APB_PORT2_IRQ_PRI DT_ARM_CMSDK_UART_40006000_IRQ_0_PRIORITY -#define CONFIG_UART_CMSDK_APB_PORT2_BAUD_RATE DT_ARM_CMSDK_UART_40006000_CURRENT_SPEED -#define CONFIG_UART_CMSDK_APB_PORT2_NAME DT_ARM_CMSDK_UART_40006000_LABEL +#define DT_CMSDK_APB_UART2 DT_ARM_CMSDK_UART_40006000_BASE_ADDRESS +#define DT_CMSDK_APB_UART_2_IRQ_TX DT_ARM_CMSDK_UART_40006000_IRQ_0 +#define DT_CMSDK_APB_UART_2_IRQ_RX DT_ARM_CMSDK_UART_40006000_IRQ_1 +#define DT_UART_CMSDK_APB_PORT2_IRQ_PRI DT_ARM_CMSDK_UART_40006000_IRQ_0_PRIORITY +#define DT_UART_CMSDK_APB_PORT2_BAUD_RATE DT_ARM_CMSDK_UART_40006000_CURRENT_SPEED +#define DT_UART_CMSDK_APB_PORT2_NAME DT_ARM_CMSDK_UART_40006000_LABEL -#define CMSDK_APB_UART3 DT_ARM_CMSDK_UART_40007000_BASE_ADDRESS -#define CMSDK_APB_UART_3_IRQ_TX DT_ARM_CMSDK_UART_40007000_IRQ_0 -#define CMSDK_APB_UART_3_IRQ_RX DT_ARM_CMSDK_UART_40007000_IRQ_1 -#define CONFIG_UART_CMSDK_APB_PORT3_IRQ_PRI DT_ARM_CMSDK_UART_40007000_IRQ_0_PRIORITY -#define CONFIG_UART_CMSDK_APB_PORT3_BAUD_RATE DT_ARM_CMSDK_UART_40007000_CURRENT_SPEED -#define CONFIG_UART_CMSDK_APB_PORT3_NAME DT_ARM_CMSDK_UART_40007000_LABEL +#define DT_CMSDK_APB_UART3 DT_ARM_CMSDK_UART_40007000_BASE_ADDRESS +#define DT_CMSDK_APB_UART_3_IRQ_TX DT_ARM_CMSDK_UART_40007000_IRQ_0 +#define DT_CMSDK_APB_UART_3_IRQ_RX DT_ARM_CMSDK_UART_40007000_IRQ_1 +#define DT_UART_CMSDK_APB_PORT3_IRQ_PRI DT_ARM_CMSDK_UART_40007000_IRQ_0_PRIORITY +#define DT_UART_CMSDK_APB_PORT3_BAUD_RATE DT_ARM_CMSDK_UART_40007000_CURRENT_SPEED +#define DT_UART_CMSDK_APB_PORT3_NAME DT_ARM_CMSDK_UART_40007000_LABEL -#define CMSDK_APB_UART4 DT_ARM_CMSDK_UART_40009000_BASE_ADDRESS -#define CMSDK_APB_UART_4_IRQ_TX DT_ARM_CMSDK_UART_40009000_IRQ_0 -#define CMSDK_APB_UART_4_IRQ_RX DT_ARM_CMSDK_UART_40009000_IRQ_1 -#define CONFIG_UART_CMSDK_APB_PORT4_IRQ_PRI DT_ARM_CMSDK_UART_40009000_IRQ_0_PRIORITY -#define CONFIG_UART_CMSDK_APB_PORT4_BAUD_RATE DT_ARM_CMSDK_UART_40009000_CURRENT_SPEED -#define CONFIG_UART_CMSDK_APB_PORT4_NAME DT_ARM_CMSDK_UART_40009000_LABEL +#define DT_CMSDK_APB_UART4 DT_ARM_CMSDK_UART_40009000_BASE_ADDRESS +#define DT_CMSDK_APB_UART_4_IRQ_TX DT_ARM_CMSDK_UART_40009000_IRQ_0 +#define DT_CMSDK_APB_UART_4_IRQ_RX DT_ARM_CMSDK_UART_40009000_IRQ_1 +#define DT_UART_CMSDK_APB_PORT4_IRQ_PRI DT_ARM_CMSDK_UART_40009000_IRQ_0_PRIORITY +#define DT_UART_CMSDK_APB_PORT4_BAUD_RATE DT_ARM_CMSDK_UART_40009000_CURRENT_SPEED +#define DT_UART_CMSDK_APB_PORT4_NAME DT_ARM_CMSDK_UART_40009000_LABEL /* CMSDK APB Watchdog */ -#define CMSDK_APB_WDOG DT_ARM_CMSDK_WATCHDOG_40008000_BASE_ADDRESS +#define DT_CMSDK_APB_WDOG DT_ARM_CMSDK_WATCHDOG_40008000_BASE_ADDRESS /* CMSDK AHB General Purpose Input/Output (GPIO) */ -#define CMSDK_AHB_GPIO0 DT_ARM_CMSDK_GPIO_40010000_BASE_ADDRESS -#define IRQ_PORT0_ALL DT_ARM_CMSDK_GPIO_40010000_IRQ_0 +#define DT_CMSDK_AHB_GPIO0 DT_ARM_CMSDK_GPIO_40010000_BASE_ADDRESS +#define DT_IRQ_PORT0_ALL DT_ARM_CMSDK_GPIO_40010000_IRQ_0 -#define CMSDK_AHB_GPIO1 DT_ARM_CMSDK_GPIO_40011000_BASE_ADDRESS -#define IRQ_PORT1_ALL DT_ARM_CMSDK_GPIO_40011000_IRQ_0 +#define DT_CMSDK_AHB_GPIO1 DT_ARM_CMSDK_GPIO_40011000_BASE_ADDRESS +#define DT_IRQ_PORT1_ALL DT_ARM_CMSDK_GPIO_40011000_IRQ_0 -#define CMSDK_AHB_GPIO2 DT_ARM_CMSDK_GPIO_40012000_BASE_ADDRESS -#define IRQ_PORT2_ALL DT_ARM_CMSDK_GPIO_40012000_IRQ_0 +#define DT_CMSDK_AHB_GPIO2 DT_ARM_CMSDK_GPIO_40012000_BASE_ADDRESS +#define DT_IRQ_PORT2_ALL DT_ARM_CMSDK_GPIO_40012000_IRQ_0 -#define CMSDK_AHB_GPIO3 DT_ARM_CMSDK_GPIO_40013000_BASE_ADDRESS -#define IRQ_PORT3_ALL DT_ARM_CMSDK_GPIO_40013000_IRQ_0 +#define DT_CMSDK_AHB_GPIO3 DT_ARM_CMSDK_GPIO_40013000_BASE_ADDRESS +#define DT_IRQ_PORT3_ALL DT_ARM_CMSDK_GPIO_40013000_IRQ_0 /* I2C SBCon */ -#define I2C_SBCON_0_BASE_ADDR DT_ARM_VERSATILE_I2C_40022000_BASE_ADDRESS -#define I2C_SBCON_0_NAME DT_ARM_VERSATILE_I2C_40022000_LABEL +#define DT_I2C_SBCON_0_BASE_ADDR DT_ARM_VERSATILE_I2C_40022000_BASE_ADDRESS +#define DT_I2C_SBCON_0_NAME DT_ARM_VERSATILE_I2C_40022000_LABEL -#define I2C_SBCON_1_BASE_ADDR DT_ARM_VERSATILE_I2C_40023000_BASE_ADDRESS -#define I2C_SBCON_1_NAME DT_ARM_VERSATILE_I2C_40023000_LABEL +#define DT_I2C_SBCON_1_BASE_ADDR DT_ARM_VERSATILE_I2C_40023000_BASE_ADDRESS +#define DT_I2C_SBCON_1_NAME DT_ARM_VERSATILE_I2C_40023000_LABEL -#define I2C_SBCON_2_BASE_ADDR DT_ARM_VERSATILE_I2C_40029000_BASE_ADDRESS -#define I2C_SBCON_2_NAME DT_ARM_VERSATILE_I2C_40029000_LABEL +#define DT_I2C_SBCON_2_BASE_ADDR DT_ARM_VERSATILE_I2C_40029000_BASE_ADDRESS +#define DT_I2C_SBCON_2_NAME DT_ARM_VERSATILE_I2C_40029000_LABEL -#define I2C_SBCON_3_BASE_ADDR DT_ARM_VERSATILE_I2C_4002A000_BASE_ADDRESS -#define I2C_SBCON_3_NAME DT_ARM_VERSATILE_I2C_4002A000_LABEL +#define DT_I2C_SBCON_3_BASE_ADDR DT_ARM_VERSATILE_I2C_4002A000_BASE_ADDRESS +#define DT_I2C_SBCON_3_NAME DT_ARM_VERSATILE_I2C_4002A000_LABEL /* End of SoC Level DTS fixup file */ diff --git a/boards/arm/mps2_an385/pinmux.c b/boards/arm/mps2_an385/pinmux.c index 251958cf7f8..0d1ce3cf5e8 100644 --- a/boards/arm/mps2_an385/pinmux.c +++ b/boards/arm/mps2_an385/pinmux.c @@ -32,13 +32,13 @@ */ #define CMSDK_AHB_GPIO0_DEV \ - ((volatile struct gpio_cmsdk_ahb *)CMSDK_AHB_GPIO0) + ((volatile struct gpio_cmsdk_ahb *)DT_CMSDK_AHB_GPIO0) #define CMSDK_AHB_GPIO1_DEV \ - ((volatile struct gpio_cmsdk_ahb *)CMSDK_AHB_GPIO1) + ((volatile struct gpio_cmsdk_ahb *)DT_CMSDK_AHB_GPIO1) #define CMSDK_AHB_GPIO2_DEV \ - ((volatile struct gpio_cmsdk_ahb *)CMSDK_AHB_GPIO2) + ((volatile struct gpio_cmsdk_ahb *)DT_CMSDK_AHB_GPIO2) #define CMSDK_AHB_GPIO3_DEV \ - ((volatile struct gpio_cmsdk_ahb *)CMSDK_AHB_GPIO3) + ((volatile struct gpio_cmsdk_ahb *)DT_CMSDK_AHB_GPIO3) /* * This is the mapping from the ARM MPS2 AN385 Board pins to GPIO diff --git a/boards/arm/nrf52_pca20020/board.c b/boards/arm/nrf52_pca20020/board.c index 953a8f744c6..4194c333205 100644 --- a/boards/arm/nrf52_pca20020/board.c +++ b/boards/arm/nrf52_pca20020/board.c @@ -49,7 +49,7 @@ static int pwr_ctrl_init(struct device *dev) #endif static const struct pwr_ctrl_cfg vdd_pwr_ctrl_cfg = { - .port = CONFIG_GPIO_P0_DEV_NAME, + .port = DT_GPIO_P0_DEV_NAME, .pin = VDD_PWR_CTRL_GPIO_PIN, }; diff --git a/boards/arm/nrf52_pca20020/dts_fixup.h b/boards/arm/nrf52_pca20020/dts_fixup.h index d0606696b73..1d5c3c97843 100644 --- a/boards/arm/nrf52_pca20020/dts_fixup.h +++ b/boards/arm/nrf52_pca20020/dts_fixup.h @@ -2,14 +2,14 @@ #define CONFIG_GPIO_SX1509B_I2C_ADDR DT_NORDIC_NRF_I2C_40003000_SEMTECH_SX1509B_3E_BASE_ADDRESS #define CONFIG_GPIO_SX1509B_I2C_MASTER_DEV_NAME DT_NORDIC_NRF_I2C_40003000_SEMTECH_SX1509B_3E_BUS_NAME -#define CONFIG_HTS221_NAME DT_NORDIC_NRF_I2C_40003000_ST_HTS221_5F_LABEL -#define CONFIG_HTS221_I2C_MASTER_DEV_NAME DT_NORDIC_NRF_I2C_40003000_ST_HTS221_5F_BUS_NAME -#define CONFIG_HTS221_I2C_ADDR DT_NORDIC_NRF_I2C_40003000_ST_HTS221_5F_BASE_ADDRESS +#define DT_HTS221_NAME DT_NORDIC_NRF_I2C_40003000_ST_HTS221_5F_LABEL +#define DT_HTS221_I2C_MASTER_DEV_NAME DT_NORDIC_NRF_I2C_40003000_ST_HTS221_5F_BUS_NAME +#define DT_HTS221_I2C_ADDR DT_NORDIC_NRF_I2C_40003000_ST_HTS221_5F_BASE_ADDRESS -#define CONFIG_CCS811_NAME DT_NORDIC_NRF_I2C_40003000_AMS_CCS811_5A_LABEL -#define CONFIG_CCS811_I2C_MASTER_DEV_NAME DT_NORDIC_NRF_I2C_40003000_AMS_CCS811_5A_BUS_NAME -#define CONFIG_CCS811_I2C_ADDR DT_NORDIC_NRF_I2C_40003000_AMS_CCS811_5A_BASE_ADDRESS +#define DT_CCS811_NAME DT_NORDIC_NRF_I2C_40003000_AMS_CCS811_5A_LABEL +#define DT_CCS811_I2C_MASTER_DEV_NAME DT_NORDIC_NRF_I2C_40003000_AMS_CCS811_5A_BUS_NAME +#define DT_CCS811_I2C_ADDR DT_NORDIC_NRF_I2C_40003000_AMS_CCS811_5A_BASE_ADDRESS -#define CONFIG_LPS22HB_DEV_NAME DT_NORDIC_NRF_I2C_40003000_ST_LPS22HB_PRESS_5C_LABEL -#define CONFIG_LPS22HB_I2C_MASTER_DEV_NAME DT_NORDIC_NRF_I2C_40003000_ST_LPS22HB_PRESS_5C_BUS_NAME -#define CONFIG_LPS22HB_I2C_ADDR DT_NORDIC_NRF_I2C_40003000_ST_LPS22HB_PRESS_5C_BASE_ADDRESS +#define DT_LPS22HB_DEV_NAME DT_NORDIC_NRF_I2C_40003000_ST_LPS22HB_PRESS_5C_LABEL +#define DT_LPS22HB_I2C_MASTER_DEV_NAME DT_NORDIC_NRF_I2C_40003000_ST_LPS22HB_PRESS_5C_BUS_NAME +#define DT_LPS22HB_I2C_ADDR DT_NORDIC_NRF_I2C_40003000_ST_LPS22HB_PRESS_5C_BASE_ADDRESS diff --git a/boards/arm/olimexino_stm32/dts_fixup.h b/boards/arm/olimexino_stm32/dts_fixup.h index 711073e2d15..d84ffb497e9 100644 --- a/boards/arm/olimexino_stm32/dts_fixup.h +++ b/boards/arm/olimexino_stm32/dts_fixup.h @@ -3,6 +3,6 @@ * are modified to handle the generated information, or the mapping of * generated data matches the driver definitions. */ -#define CONFIG_USB_DC_STM32_DISCONN_GPIO_PORT_NAME DT_ST_STM32_USB_40005C00_DISCONNECT_GPIOS_CONTROLLER -#define CONFIG_USB_DC_STM32_DISCONN_PIN DT_ST_STM32_USB_40005C00_DISCONNECT_GPIOS_PIN -#define CONFIG_USB_DC_STM32_DISCONN_PIN_LEVEL DT_ST_STM32_USB_40005C00_DISCONNECT_GPIOS_FLAGS +#define DT_USB_DC_STM32_DISCONN_GPIO_PORT_NAME DT_ST_STM32_USB_40005C00_DISCONNECT_GPIOS_CONTROLLER +#define DT_USB_DC_STM32_DISCONN_PIN DT_ST_STM32_USB_40005C00_DISCONNECT_GPIOS_PIN +#define DT_USB_DC_STM32_DISCONN_PIN_LEVEL DT_ST_STM32_USB_40005C00_DISCONNECT_GPIOS_FLAGS diff --git a/boards/arm/reel_board/dts_fixup.h b/boards/arm/reel_board/dts_fixup.h index 11462cd92c4..29f01d3c934 100644 --- a/boards/arm/reel_board/dts_fixup.h +++ b/boards/arm/reel_board/dts_fixup.h @@ -1,33 +1,33 @@ -#define CONFIG_FXOS8700_NAME DT_NORDIC_NRF_I2C_40003000_NXP_FXOS8700_1D_LABEL -#define CONFIG_FXOS8700_I2C_NAME DT_NORDIC_NRF_I2C_40003000_NXP_FXOS8700_1D_BUS_NAME -#define CONFIG_FXOS8700_I2C_ADDRESS DT_NORDIC_NRF_I2C_40003000_NXP_FXOS8700_1D_BASE_ADDRESS -#define CONFIG_FXOS8700_GPIO_NAME DT_NORDIC_NRF_I2C_40003000_NXP_FXOS8700_1D_INT1_GPIOS_CONTROLLER -#define CONFIG_FXOS8700_GPIO_PIN DT_NORDIC_NRF_I2C_40003000_NXP_FXOS8700_1D_INT1_GPIOS_PIN +#define DT_FXOS8700_NAME DT_NORDIC_NRF_I2C_40003000_NXP_FXOS8700_1D_LABEL +#define DT_FXOS8700_I2C_NAME DT_NORDIC_NRF_I2C_40003000_NXP_FXOS8700_1D_BUS_NAME +#define DT_FXOS8700_I2C_ADDRESS DT_NORDIC_NRF_I2C_40003000_NXP_FXOS8700_1D_BASE_ADDRESS +#define DT_FXOS8700_GPIO_NAME DT_NORDIC_NRF_I2C_40003000_NXP_FXOS8700_1D_INT1_GPIOS_CONTROLLER +#define DT_FXOS8700_GPIO_PIN DT_NORDIC_NRF_I2C_40003000_NXP_FXOS8700_1D_INT1_GPIOS_PIN -#define CONFIG_HDC1008_NAME DT_NORDIC_NRF_I2C_40003000_TI_HDC1008_43_LABEL -#define CONFIG_HDC1008_I2C_MASTER_DEV_NAME DT_NORDIC_NRF_I2C_40003000_TI_HDC1008_43_BUS_NAME -#define CONFIG_HDC1008_I2C_ADDR DT_NORDIC_NRF_I2C_40003000_TI_HDC1008_43_BASE_ADDRESS -#define CONFIG_HDC1008_GPIO_DEV_NAME DT_NORDIC_NRF_I2C_40003000_TI_HDC1008_43_DRDY_GPIOS_CONTROLLER -#define CONFIG_HDC1008_GPIO_PIN_NUM DT_NORDIC_NRF_I2C_40003000_TI_HDC1008_43_DRDY_GPIOS_PIN -#define CONFIG_HDC1008_GPIO_FLAGS DT_NORDIC_NRF_I2C_40003000_TI_HDC1008_43_DRDY_GPIOS_FLAGS +#define DT_HDC1008_NAME DT_NORDIC_NRF_I2C_40003000_TI_HDC1008_43_LABEL +#define DT_HDC1008_I2C_MASTER_DEV_NAME DT_NORDIC_NRF_I2C_40003000_TI_HDC1008_43_BUS_NAME +#define DT_HDC1008_I2C_ADDR DT_NORDIC_NRF_I2C_40003000_TI_HDC1008_43_BASE_ADDRESS +#define DT_HDC1008_GPIO_DEV_NAME DT_NORDIC_NRF_I2C_40003000_TI_HDC1008_43_DRDY_GPIOS_CONTROLLER +#define DT_HDC1008_GPIO_PIN_NUM DT_NORDIC_NRF_I2C_40003000_TI_HDC1008_43_DRDY_GPIOS_PIN +#define DT_HDC1008_GPIO_FLAGS DT_NORDIC_NRF_I2C_40003000_TI_HDC1008_43_DRDY_GPIOS_FLAGS -#define CONFIG_APDS9960_DRV_NAME DT_NORDIC_NRF_I2C_40003000_AVAGO_APDS9960_29_LABEL -#define CONFIG_APDS9960_I2C_DEV_NAME DT_NORDIC_NRF_I2C_40003000_AVAGO_APDS9960_29_BUS_NAME -#define CONFIG_APDS9960_GPIO_DEV_NAME DT_NORDIC_NRF_I2C_40003000_AVAGO_APDS9960_29_INT_GPIOS_CONTROLLER -#define CONFIG_APDS9960_GPIO_PIN_NUM DT_NORDIC_NRF_I2C_40003000_AVAGO_APDS9960_29_INT_GPIOS_PIN +#define DT_APDS9960_DRV_NAME DT_NORDIC_NRF_I2C_40003000_AVAGO_APDS9960_29_LABEL +#define DT_APDS9960_I2C_DEV_NAME DT_NORDIC_NRF_I2C_40003000_AVAGO_APDS9960_29_BUS_NAME +#define DT_APDS9960_GPIO_DEV_NAME DT_NORDIC_NRF_I2C_40003000_AVAGO_APDS9960_29_INT_GPIOS_CONTROLLER +#define DT_APDS9960_GPIO_PIN_NUM DT_NORDIC_NRF_I2C_40003000_AVAGO_APDS9960_29_INT_GPIOS_PIN -#define CONFIG_SSD1673_DEV_NAME DT_NORDIC_NRF_SPI_4002B000_SOLOMON_SSD1673FB_SPI_0_LABEL -#define CONFIG_SSD1673_SPI_FREQ DT_NORDIC_NRF_SPI_4002B000_SOLOMON_SSD1673FB_SPI_0_SPI_MAX_FREQUENCY -#define CONFIG_SSD1673_SPI_DEV_NAME DT_NORDIC_NRF_SPI_4002B000_SOLOMON_SSD1673FB_SPI_0_BUS_NAME -#define CONFIG_SSD1673_SPI_SLAVE_NUMBER DT_NORDIC_NRF_SPI_4002B000_SOLOMON_SSD1673FB_SPI_0_BASE_ADDRESS -#define CONFIG_SSD1673_SPI_GPIO_CS y -#define CONFIG_SSD1673_SPI_GPIO_CS_DRV_NAME DT_NORDIC_NRF_SPI_4002B000_CS_GPIOS_CONTROLLER -#define CONFIG_SSD1673_SPI_GPIO_CS_PIN DT_NORDIC_NRF_SPI_4002B000_CS_GPIOS_PIN +#define DT_SSD1673_DEV_NAME DT_NORDIC_NRF_SPI_4002B000_SOLOMON_SSD1673FB_SPI_0_LABEL +#define DT_SSD1673_SPI_FREQ DT_NORDIC_NRF_SPI_4002B000_SOLOMON_SSD1673FB_SPI_0_SPI_MAX_FREQUENCY +#define DT_SSD1673_SPI_DEV_NAME DT_NORDIC_NRF_SPI_4002B000_SOLOMON_SSD1673FB_SPI_0_BUS_NAME +#define DT_SSD1673_SPI_SLAVE_NUMBER DT_NORDIC_NRF_SPI_4002B000_SOLOMON_SSD1673FB_SPI_0_BASE_ADDRESS +#define DT_SSD1673_SPI_GPIO_CS y +#define DT_SSD1673_SPI_GPIO_CS_DRV_NAME DT_NORDIC_NRF_SPI_4002B000_CS_GPIOS_CONTROLLER +#define DT_SSD1673_SPI_GPIO_CS_PIN DT_NORDIC_NRF_SPI_4002B000_CS_GPIOS_PIN -#define CONFIG_SSD1673_RESET_GPIO_PORT_NAME DT_NORDIC_NRF_SPI_4002B000_SOLOMON_SSD1673FB_SPI_0_RESET_GPIOS_CONTROLLER -#define CONFIG_SSD1673_RESET_PIN DT_NORDIC_NRF_SPI_4002B000_SOLOMON_SSD1673FB_SPI_0_RESET_GPIOS_PIN -#define CONFIG_SSD1673_DC_GPIO_PORT_NAME DT_NORDIC_NRF_SPI_4002B000_SOLOMON_SSD1673FB_SPI_0_DC_GPIOS_CONTROLLER -#define CONFIG_SSD1673_DC_PIN DT_NORDIC_NRF_SPI_4002B000_SOLOMON_SSD1673FB_SPI_0_DC_GPIOS_PIN -#define CONFIG_SSD1673_BUSY_GPIO_PORT_NAME DT_NORDIC_NRF_SPI_4002B000_SOLOMON_SSD1673FB_SPI_0_BUSY_GPIOS_CONTROLLER -#define CONFIG_SSD1673_BUSY_PIN DT_NORDIC_NRF_SPI_4002B000_SOLOMON_SSD1673FB_SPI_0_BUSY_GPIOS_PIN -#define CONFIG_SSD1673_ORIENTATION_FLIPPED DT_NORDIC_NRF_SPI_4002B000_SOLOMON_SSD1673FB_SPI_0_ORIENTATION_FLIPPED +#define DT_SSD1673_RESET_GPIO_PORT_NAME DT_NORDIC_NRF_SPI_4002B000_SOLOMON_SSD1673FB_SPI_0_RESET_GPIOS_CONTROLLER +#define DT_SSD1673_RESET_PIN DT_NORDIC_NRF_SPI_4002B000_SOLOMON_SSD1673FB_SPI_0_RESET_GPIOS_PIN +#define DT_SSD1673_DC_GPIO_PORT_NAME DT_NORDIC_NRF_SPI_4002B000_SOLOMON_SSD1673FB_SPI_0_DC_GPIOS_CONTROLLER +#define DT_SSD1673_DC_PIN DT_NORDIC_NRF_SPI_4002B000_SOLOMON_SSD1673FB_SPI_0_DC_GPIOS_PIN +#define DT_SSD1673_BUSY_GPIO_PORT_NAME DT_NORDIC_NRF_SPI_4002B000_SOLOMON_SSD1673FB_SPI_0_BUSY_GPIOS_CONTROLLER +#define DT_SSD1673_BUSY_PIN DT_NORDIC_NRF_SPI_4002B000_SOLOMON_SSD1673FB_SPI_0_BUSY_GPIOS_PIN +#define DT_SSD1673_ORIENTATION_FLIPPED DT_NORDIC_NRF_SPI_4002B000_SOLOMON_SSD1673FB_SPI_0_ORIENTATION_FLIPPED diff --git a/boards/arm/stm32f3_disco/dts_fixup.h b/boards/arm/stm32f3_disco/dts_fixup.h index 6da426e5bec..03b2816d1f0 100644 --- a/boards/arm/stm32f3_disco/dts_fixup.h +++ b/boards/arm/stm32f3_disco/dts_fixup.h @@ -4,10 +4,10 @@ * generated data matches the driver definitions. */ -#define CONFIG_LSM303DLHC_ACCEL_NAME DT_ST_STM32_I2C_V2_40005400_ST_LSM303DLHC_ACCEL_19_LABEL -#define CONFIG_LSM303DLHC_ACCEL_I2C_ADDR DT_ST_STM32_I2C_V2_40005400_ST_LSM303DLHC_ACCEL_19_BASE_ADDRESS -#define CONFIG_LSM303DLHC_ACCEL_I2C_MASTER_DEV DT_ST_STM32_I2C_V2_40005400_ST_LSM303DLHC_ACCEL_19_BUS_NAME +#define DT_LSM303DLHC_ACCEL_NAME DT_ST_STM32_I2C_V2_40005400_ST_LSM303DLHC_ACCEL_19_LABEL +#define DT_LSM303DLHC_ACCEL_I2C_ADDR DT_ST_STM32_I2C_V2_40005400_ST_LSM303DLHC_ACCEL_19_BASE_ADDRESS +#define DT_LSM303DLHC_ACCEL_I2C_MASTER_DEV DT_ST_STM32_I2C_V2_40005400_ST_LSM303DLHC_ACCEL_19_BUS_NAME -#define CONFIG_LSM303DLHC_MAGN_NAME DT_ST_STM32_I2C_V2_40005400_ST_LSM303DLHC_MAGN_1E_LABEL -#define CONFIG_LSM303DLHC_MAGN_I2C_ADDR DT_ST_STM32_I2C_V2_40005400_ST_LSM303DLHC_MAGN_1E_BASE_ADDRESS -#define CONFIG_LSM303DLHC_MAGN_I2C_MASTER_DEV DT_ST_STM32_I2C_V2_40005400_ST_LSM303DLHC_MAGN_1E_BUS_NAME +#define DT_LSM303DLHC_MAGN_NAME DT_ST_STM32_I2C_V2_40005400_ST_LSM303DLHC_MAGN_1E_LABEL +#define DT_LSM303DLHC_MAGN_I2C_ADDR DT_ST_STM32_I2C_V2_40005400_ST_LSM303DLHC_MAGN_1E_BASE_ADDRESS +#define DT_LSM303DLHC_MAGN_I2C_MASTER_DEV DT_ST_STM32_I2C_V2_40005400_ST_LSM303DLHC_MAGN_1E_BUS_NAME diff --git a/boards/arm/v2m_beetle/pinmux.c b/boards/arm/v2m_beetle/pinmux.c index 8f2215a9ff8..90d4bb4e250 100644 --- a/boards/arm/v2m_beetle/pinmux.c +++ b/boards/arm/v2m_beetle/pinmux.c @@ -33,9 +33,9 @@ */ #define CMSDK_AHB_GPIO0_DEV \ - ((volatile struct gpio_cmsdk_ahb *)CMSDK_AHB_GPIO0) + ((volatile struct gpio_cmsdk_ahb *)DT_CMSDK_AHB_GPIO0) #define CMSDK_AHB_GPIO1_DEV \ - ((volatile struct gpio_cmsdk_ahb *)CMSDK_AHB_GPIO1) + ((volatile struct gpio_cmsdk_ahb *)DT_CMSDK_AHB_GPIO1) /* * This is the mapping from the ARM V2M Beetle Board pins to GPIO diff --git a/boards/arm/warp7_m4/dts_fixup.h b/boards/arm/warp7_m4/dts_fixup.h index ffc6e9532bb..3140242615d 100644 --- a/boards/arm/warp7_m4/dts_fixup.h +++ b/boards/arm/warp7_m4/dts_fixup.h @@ -1,11 +1,11 @@ -#define CONFIG_FXOS8700_NAME DT_FSL_IMX7D_I2C_30A50000_NXP_FXOS8700_1E_LABEL -#define CONFIG_FXOS8700_I2C_NAME DT_FSL_IMX7D_I2C_30A50000_NXP_FXOS8700_1E_BUS_NAME -#define CONFIG_FXOS8700_I2C_ADDRESS DT_FSL_IMX7D_I2C_30A50000_NXP_FXOS8700_1E_BASE_ADDRESS -#define CONFIG_FXOS8700_GPIO_NAME DT_FSL_IMX7D_I2C_30A50000_NXP_FXOS8700_1E_INT1_GPIOS_CONTROLLER -#define CONFIG_FXOS8700_GPIO_PIN DT_FSL_IMX7D_I2C_30A50000_NXP_FXOS8700_1E_INT1_GPIOS_PIN +#define DT_FXOS8700_NAME DT_FSL_IMX7D_I2C_30A50000_NXP_FXOS8700_1E_LABEL +#define DT_FXOS8700_I2C_NAME DT_FSL_IMX7D_I2C_30A50000_NXP_FXOS8700_1E_BUS_NAME +#define DT_FXOS8700_I2C_ADDRESS DT_FSL_IMX7D_I2C_30A50000_NXP_FXOS8700_1E_BASE_ADDRESS +#define DT_FXOS8700_GPIO_NAME DT_FSL_IMX7D_I2C_30A50000_NXP_FXOS8700_1E_INT1_GPIOS_CONTROLLER +#define DT_FXOS8700_GPIO_PIN DT_FSL_IMX7D_I2C_30A50000_NXP_FXOS8700_1E_INT1_GPIOS_PIN -#define CONFIG_FXAS21002_NAME DT_FSL_IMX7D_I2C_30A50000_NXP_FXAS21002_20_LABEL -#define CONFIG_FXAS21002_I2C_NAME DT_FSL_IMX7D_I2C_30A50000_NXP_FXAS21002_20_BUS_NAME -#define CONFIG_FXAS21002_I2C_ADDRESS DT_FSL_IMX7D_I2C_30A50000_NXP_FXAS21002_20_BASE_ADDRESS -#define CONFIG_FXAS21002_GPIO_NAME DT_FSL_IMX7D_I2C_30A50000_NXP_FXAS21002_20_INT1_GPIOS_CONTROLLER -#define CONFIG_FXAS21002_GPIO_PIN DT_FSL_IMX7D_I2C_30A50000_NXP_FXAS21002_20_INT1_GPIOS_PIN +#define DT_FXAS21002_NAME DT_FSL_IMX7D_I2C_30A50000_NXP_FXAS21002_20_LABEL +#define DT_FXAS21002_I2C_NAME DT_FSL_IMX7D_I2C_30A50000_NXP_FXAS21002_20_BUS_NAME +#define DT_FXAS21002_I2C_ADDRESS DT_FSL_IMX7D_I2C_30A50000_NXP_FXAS21002_20_BASE_ADDRESS +#define DT_FXAS21002_GPIO_NAME DT_FSL_IMX7D_I2C_30A50000_NXP_FXAS21002_20_INT1_GPIOS_CONTROLLER +#define DT_FXAS21002_GPIO_PIN DT_FSL_IMX7D_I2C_30A50000_NXP_FXAS21002_20_INT1_GPIOS_PIN diff --git a/boards/shields/x_nucleo_iks01a1/dts_fixup.h b/boards/shields/x_nucleo_iks01a1/dts_fixup.h index d9cdad948e3..6b210d20f10 100644 --- a/boards/shields/x_nucleo_iks01a1/dts_fixup.h +++ b/boards/shields/x_nucleo_iks01a1/dts_fixup.h @@ -5,17 +5,17 @@ * SPDX-License-Identifier: Apache-2.0 */ -#define CONFIG_HTS221_NAME ARDUINO_I2C_ST_HTS221_5F_LABEL -#define CONFIG_HTS221_I2C_MASTER_DEV_NAME ARDUINO_I2C_ST_HTS221_5F_BUS_NAME +#define DT_HTS221_NAME ARDUINO_I2C_ST_HTS221_5F_LABEL +#define DT_HTS221_I2C_MASTER_DEV_NAME ARDUINO_I2C_ST_HTS221_5F_BUS_NAME -#define CONFIG_LIS3MDL_NAME ARDUINO_I2C_ST_LIS3MDL_MAGN_1E_LABEL -#define CONFIG_LIS3MDL_I2C_ADDR ARDUINO_I2C_ST_LIS3MDL_MAGN_1E_BASE_ADDRESS -#define CONFIG_LIS3MDL_I2C_MASTER_DEV_NAME ARDUINO_I2C_ST_LIS3MDL_MAGN_1E_BUS_NAME +#define DT_LIS3MDL_NAME ARDUINO_I2C_ST_LIS3MDL_MAGN_1E_LABEL +#define DT_LIS3MDL_I2C_ADDR ARDUINO_I2C_ST_LIS3MDL_MAGN_1E_BASE_ADDRESS +#define DT_LIS3MDL_I2C_MASTER_DEV_NAME ARDUINO_I2C_ST_LIS3MDL_MAGN_1E_BUS_NAME -#define CONFIG_LPS25HB_DEV_NAME ARDUINO_I2C_ST_LPS25HB_PRESS_5D_LABEL -#define CONFIG_LPS25HB_I2C_ADDR ARDUINO_I2C_ST_LPS25HB_PRESS_5D_BASE_ADDRESS -#define CONFIG_LPS25HB_I2C_MASTER_DEV_NAME ARDUINO_I2C_ST_LPS25HB_PRESS_5D_BUS_NAME +#define DT_LPS25HB_DEV_NAME ARDUINO_I2C_ST_LPS25HB_PRESS_5D_LABEL +#define DT_LPS25HB_I2C_ADDR ARDUINO_I2C_ST_LPS25HB_PRESS_5D_BASE_ADDRESS +#define DT_LPS25HB_I2C_MASTER_DEV_NAME ARDUINO_I2C_ST_LPS25HB_PRESS_5D_BUS_NAME -#define CONFIG_LSM6DS0_DEV_NAME ARDUINO_I2C_ST_LSM6DS0_6B_LABEL -#define CONFIG_LSM6DS0_I2C_ADDR ARDUINO_I2C_ST_LSM6DS0_6B_BASE_ADDRESS -#define CONFIG_LSM6DS0_I2C_MASTER_DEV_NAME ARDUINO_I2C_ST_LSM6DS0_6B_BUS_NAME +#define DT_LSM6DS0_DEV_NAME ARDUINO_I2C_ST_LSM6DS0_6B_LABEL +#define DT_LSM6DS0_I2C_ADDR ARDUINO_I2C_ST_LSM6DS0_6B_BASE_ADDRESS +#define DT_LSM6DS0_I2C_MASTER_DEV_NAME ARDUINO_I2C_ST_LSM6DS0_6B_BUS_NAME diff --git a/boards/shields/x_nucleo_iks01a2/dts_fixup.h b/boards/shields/x_nucleo_iks01a2/dts_fixup.h index f5c22523bbf..4b3778903fc 100644 --- a/boards/shields/x_nucleo_iks01a2/dts_fixup.h +++ b/boards/shields/x_nucleo_iks01a2/dts_fixup.h @@ -5,13 +5,13 @@ * SPDX-License-Identifier: Apache-2.0 */ -#define CONFIG_HTS221_NAME ARDUINO_I2C_ST_HTS221_5F_LABEL -#define CONFIG_HTS221_I2C_MASTER_DEV_NAME ARDUINO_I2C_ST_HTS221_5F_BUS_NAME +#define DT_HTS221_NAME ARDUINO_I2C_ST_HTS221_5F_LABEL +#define DT_HTS221_I2C_MASTER_DEV_NAME ARDUINO_I2C_ST_HTS221_5F_BUS_NAME -#define CONFIG_LPS22HB_DEV_NAME ARDUINO_I2C_ST_LPS22HB_PRESS_5D_LABEL -#define CONFIG_LPS22HB_I2C_ADDR ARDUINO_I2C_ST_LPS22HB_PRESS_5D_BASE_ADDRESS -#define CONFIG_LPS22HB_I2C_MASTER_DEV_NAME ARDUINO_I2C_ST_LPS22HB_PRESS_5D_BUS_NAME +#define DT_LPS22HB_DEV_NAME ARDUINO_I2C_ST_LPS22HB_PRESS_5D_LABEL +#define DT_LPS22HB_I2C_ADDR ARDUINO_I2C_ST_LPS22HB_PRESS_5D_BASE_ADDRESS +#define DT_LPS22HB_I2C_MASTER_DEV_NAME ARDUINO_I2C_ST_LPS22HB_PRESS_5D_BUS_NAME -#define CONFIG_LSM6DSL_DEV_NAME ARDUINO_I2C_ST_LSM6DSL_6B_LABEL -#define CONFIG_LSM6DSL_I2C_ADDR ARDUINO_I2C_ST_LSM6DSL_6B_BASE_ADDRESS -#define CONFIG_LSM6DSL_I2C_MASTER_DEV_NAME ARDUINO_I2C_ST_LSM6DSL_6B_BUS_NAME +#define DT_LSM6DSL_DEV_NAME ARDUINO_I2C_ST_LSM6DSL_6B_LABEL +#define DT_LSM6DSL_I2C_ADDR ARDUINO_I2C_ST_LSM6DSL_6B_BASE_ADDRESS +#define DT_LSM6DSL_I2C_MASTER_DEV_NAME ARDUINO_I2C_ST_LSM6DSL_6B_BUS_NAME diff --git a/boards/x86/qemu_x86/dts_fixup.h b/boards/x86/qemu_x86/dts_fixup.h index ee0fc0f8ae7..d20bad3cfbb 100644 --- a/boards/x86/qemu_x86/dts_fixup.h +++ b/boards/x86/qemu_x86/dts_fixup.h @@ -1,8 +1,8 @@ /* Board level DTS fixup file */ -#define CONFIG_ETH_E1000_BASE_ADDRESS DT_INTEL_E1000_FEBC0000_BASE_ADDRESS -#define CONFIG_ETH_E1000_IRQ DT_INTEL_E1000_FEBC0000_IRQ_0 -#define CONFIG_ETH_E1000_IRQ_PRIORITY DT_INTEL_E1000_FEBC0000_IRQ_0_PRIORITY -#define CONFIG_ETH_E1000_IRQ_FLAGS DT_INTEL_E1000_FEBC0000_IRQ_0_SENSE +#define DT_ETH_E1000_BASE_ADDRESS DT_INTEL_E1000_FEBC0000_BASE_ADDRESS +#define DT_ETH_E1000_IRQ DT_INTEL_E1000_FEBC0000_IRQ_0 +#define DT_ETH_E1000_IRQ_PRIORITY DT_INTEL_E1000_FEBC0000_IRQ_0_PRIORITY +#define DT_ETH_E1000_IRQ_FLAGS DT_INTEL_E1000_FEBC0000_IRQ_0_SENSE /* End of Board Level DTS fixup file */ diff --git a/boards/x86/up_squared/dts_fixup.h b/boards/x86/up_squared/dts_fixup.h index 023add141ba..30bb80ca93e 100644 --- a/boards/x86/up_squared/dts_fixup.h +++ b/boards/x86/up_squared/dts_fixup.h @@ -6,76 +6,76 @@ /* Board level DTS fixup file */ -#define CONFIG_UART_NS16550_PORT_0_BASE_ADDR DT_NS16550_91524000_BASE_ADDRESS +#define DT_UART_NS16550_PORT_0_BASE_ADDR DT_NS16550_91524000_BASE_ADDRESS #define CONFIG_UART_NS16550_PORT_0_BAUD_RATE DT_NS16550_91524000_CURRENT_SPEED #define CONFIG_UART_NS16550_PORT_0_NAME DT_NS16550_91524000_LABEL -#define CONFIG_UART_NS16550_PORT_0_IRQ DT_NS16550_91524000_IRQ_0 +#define DT_UART_NS16550_PORT_0_IRQ DT_NS16550_91524000_IRQ_0 #define CONFIG_UART_NS16550_PORT_0_IRQ_PRI DT_NS16550_91524000_IRQ_0_PRIORITY -#define CONFIG_UART_NS16550_PORT_0_IRQ_FLAGS DT_NS16550_91524000_IRQ_0_SENSE -#define CONFIG_UART_NS16550_PORT_0_CLK_FREQ DT_NS16550_91524000_CLOCK_FREQUENCY +#define DT_UART_NS16550_PORT_0_IRQ_FLAGS DT_NS16550_91524000_IRQ_0_SENSE +#define DT_UART_NS16550_PORT_0_CLK_FREQ DT_NS16550_91524000_CLOCK_FREQUENCY -#define CONFIG_UART_NS16550_PORT_1_BASE_ADDR DT_NS16550_91522000_BASE_ADDRESS +#define DT_UART_NS16550_PORT_1_BASE_ADDR DT_NS16550_91522000_BASE_ADDRESS #define CONFIG_UART_NS16550_PORT_1_BAUD_RATE DT_NS16550_91522000_CURRENT_SPEED #define CONFIG_UART_NS16550_PORT_1_NAME DT_NS16550_91522000_LABEL -#define CONFIG_UART_NS16550_PORT_1_IRQ DT_NS16550_91522000_IRQ_0 +#define DT_UART_NS16550_PORT_1_IRQ DT_NS16550_91522000_IRQ_0 #define CONFIG_UART_NS16550_PORT_1_IRQ_PRI DT_NS16550_91522000_IRQ_0_PRIORITY -#define CONFIG_UART_NS16550_PORT_1_IRQ_FLAGS DT_NS16550_91522000_IRQ_0_SENSE -#define CONFIG_UART_NS16550_PORT_1_CLK_FREQ DT_NS16550_91522000_CLOCK_FREQUENCY +#define DT_UART_NS16550_PORT_1_IRQ_FLAGS DT_NS16550_91522000_IRQ_0_SENSE +#define DT_UART_NS16550_PORT_1_CLK_FREQ DT_NS16550_91522000_CLOCK_FREQUENCY #define CONFIG_I2C_0_NAME DT_SNPS_DESIGNWARE_I2C_91534000_LABEL -#define CONFIG_I2C_0_BASE_ADDR DT_SNPS_DESIGNWARE_I2C_91534000_BASE_ADDRESS -#define CONFIG_I2C_0_IRQ DT_SNPS_DESIGNWARE_I2C_91534000_IRQ_0 +#define DT_I2C_0_BASE_ADDR DT_SNPS_DESIGNWARE_I2C_91534000_BASE_ADDRESS +#define DT_I2C_0_IRQ DT_SNPS_DESIGNWARE_I2C_91534000_IRQ_0 #define CONFIG_I2C_0_IRQ_PRI DT_SNPS_DESIGNWARE_I2C_91534000_IRQ_0_PRIORITY -#define CONFIG_I2C_0_IRQ_FLAGS DT_SNPS_DESIGNWARE_I2C_91534000_IRQ_0_SENSE -#define CONFIG_I2C_0_BITRATE DT_SNPS_DESIGNWARE_I2C_91534000_CLOCK_FREQUENCY +#define DT_I2C_0_IRQ_FLAGS DT_SNPS_DESIGNWARE_I2C_91534000_IRQ_0_SENSE +#define DT_I2C_0_BITRATE DT_SNPS_DESIGNWARE_I2C_91534000_CLOCK_FREQUENCY #define CONFIG_I2C_1_NAME DT_SNPS_DESIGNWARE_I2C_91532000_LABEL -#define CONFIG_I2C_1_BASE_ADDR DT_SNPS_DESIGNWARE_I2C_91532000_BASE_ADDRESS -#define CONFIG_I2C_1_IRQ DT_SNPS_DESIGNWARE_I2C_91532000_IRQ_0 +#define DT_I2C_1_BASE_ADDR DT_SNPS_DESIGNWARE_I2C_91532000_BASE_ADDRESS +#define DT_I2C_1_IRQ DT_SNPS_DESIGNWARE_I2C_91532000_IRQ_0 #define CONFIG_I2C_1_IRQ_PRI DT_SNPS_DESIGNWARE_I2C_91532000_IRQ_0_PRIORITY -#define CONFIG_I2C_1_IRQ_FLAGS DT_SNPS_DESIGNWARE_I2C_91532000_IRQ_0_SENSE -#define CONFIG_I2C_1_BITRATE DT_SNPS_DESIGNWARE_I2C_91532000_CLOCK_FREQUENCY +#define DT_I2C_1_IRQ_FLAGS DT_SNPS_DESIGNWARE_I2C_91532000_IRQ_0_SENSE +#define DT_I2C_1_BITRATE DT_SNPS_DESIGNWARE_I2C_91532000_CLOCK_FREQUENCY #define CONFIG_I2C_2_NAME DT_SNPS_DESIGNWARE_I2C_91530000_LABEL -#define CONFIG_I2C_2_BASE_ADDR DT_SNPS_DESIGNWARE_I2C_91530000_BASE_ADDRESS -#define CONFIG_I2C_2_IRQ DT_SNPS_DESIGNWARE_I2C_91530000_IRQ_0 +#define DT_I2C_2_BASE_ADDR DT_SNPS_DESIGNWARE_I2C_91530000_BASE_ADDRESS +#define DT_I2C_2_IRQ DT_SNPS_DESIGNWARE_I2C_91530000_IRQ_0 #define CONFIG_I2C_2_IRQ_PRI DT_SNPS_DESIGNWARE_I2C_91530000_IRQ_0_PRIORITY -#define CONFIG_I2C_2_IRQ_FLAGS DT_SNPS_DESIGNWARE_I2C_91530000_IRQ_0_SENSE -#define CONFIG_I2C_2_BITRATE DT_SNPS_DESIGNWARE_I2C_91530000_CLOCK_FREQUENCY +#define DT_I2C_2_IRQ_FLAGS DT_SNPS_DESIGNWARE_I2C_91530000_IRQ_0_SENSE +#define DT_I2C_2_BITRATE DT_SNPS_DESIGNWARE_I2C_91530000_CLOCK_FREQUENCY #define CONFIG_I2C_3_NAME DT_SNPS_DESIGNWARE_I2C_9152E000_LABEL -#define CONFIG_I2C_3_BASE_ADDR DT_SNPS_DESIGNWARE_I2C_9152E000_BASE_ADDRESS -#define CONFIG_I2C_3_IRQ DT_SNPS_DESIGNWARE_I2C_9152E000_IRQ_0 +#define DT_I2C_3_BASE_ADDR DT_SNPS_DESIGNWARE_I2C_9152E000_BASE_ADDRESS +#define DT_I2C_3_IRQ DT_SNPS_DESIGNWARE_I2C_9152E000_IRQ_0 #define CONFIG_I2C_3_IRQ_PRI DT_SNPS_DESIGNWARE_I2C_9152E000_IRQ_0_PRIORITY -#define CONFIG_I2C_3_IRQ_FLAGS DT_SNPS_DESIGNWARE_I2C_9152E000_IRQ_0_SENSE -#define CONFIG_I2C_3_BITRATE DT_SNPS_DESIGNWARE_I2C_9152E000_CLOCK_FREQUENCY +#define DT_I2C_3_IRQ_FLAGS DT_SNPS_DESIGNWARE_I2C_9152E000_IRQ_0_SENSE +#define DT_I2C_3_BITRATE DT_SNPS_DESIGNWARE_I2C_9152E000_CLOCK_FREQUENCY #define CONFIG_I2C_4_NAME DT_SNPS_DESIGNWARE_I2C_9152C000_LABEL -#define CONFIG_I2C_4_BASE_ADDR DT_SNPS_DESIGNWARE_I2C_9152C000_BASE_ADDRESS -#define CONFIG_I2C_4_IRQ DT_SNPS_DESIGNWARE_I2C_9152C000_IRQ_0 +#define DT_I2C_4_BASE_ADDR DT_SNPS_DESIGNWARE_I2C_9152C000_BASE_ADDRESS +#define DT_I2C_4_IRQ DT_SNPS_DESIGNWARE_I2C_9152C000_IRQ_0 #define CONFIG_I2C_4_IRQ_PRI DT_SNPS_DESIGNWARE_I2C_9152C000_IRQ_0_PRIORITY -#define CONFIG_I2C_4_IRQ_FLAGS DT_SNPS_DESIGNWARE_I2C_9152C000_IRQ_0_SENSE -#define CONFIG_I2C_4_BITRATE DT_SNPS_DESIGNWARE_I2C_9152C000_CLOCK_FREQUENCY +#define DT_I2C_4_IRQ_FLAGS DT_SNPS_DESIGNWARE_I2C_9152C000_IRQ_0_SENSE +#define DT_I2C_4_BITRATE DT_SNPS_DESIGNWARE_I2C_9152C000_CLOCK_FREQUENCY #define CONFIG_I2C_5_NAME DT_SNPS_DESIGNWARE_I2C_9152A000_LABEL -#define CONFIG_I2C_5_BASE_ADDR DT_SNPS_DESIGNWARE_I2C_9152A000_BASE_ADDRESS -#define CONFIG_I2C_5_IRQ DT_SNPS_DESIGNWARE_I2C_9152A000_IRQ_0 +#define DT_I2C_5_BASE_ADDR DT_SNPS_DESIGNWARE_I2C_9152A000_BASE_ADDRESS +#define DT_I2C_5_IRQ DT_SNPS_DESIGNWARE_I2C_9152A000_IRQ_0 #define CONFIG_I2C_5_IRQ_PRI DT_SNPS_DESIGNWARE_I2C_9152A000_IRQ_0_PRIORITY -#define CONFIG_I2C_5_IRQ_FLAGS DT_SNPS_DESIGNWARE_I2C_9152A000_IRQ_0_SENSE -#define CONFIG_I2C_5_BITRATE DT_SNPS_DESIGNWARE_I2C_9152A000_CLOCK_FREQUENCY +#define DT_I2C_5_IRQ_FLAGS DT_SNPS_DESIGNWARE_I2C_9152A000_IRQ_0_SENSE +#define DT_I2C_5_BITRATE DT_SNPS_DESIGNWARE_I2C_9152A000_CLOCK_FREQUENCY #define CONFIG_I2C_6_NAME DT_SNPS_DESIGNWARE_I2C_91528000_LABEL -#define CONFIG_I2C_6_BASE_ADDR DT_SNPS_DESIGNWARE_I2C_91528000_BASE_ADDRESS -#define CONFIG_I2C_6_IRQ DT_SNPS_DESIGNWARE_I2C_91528000_IRQ_0 +#define DT_I2C_6_BASE_ADDR DT_SNPS_DESIGNWARE_I2C_91528000_BASE_ADDRESS +#define DT_I2C_6_IRQ DT_SNPS_DESIGNWARE_I2C_91528000_IRQ_0 #define CONFIG_I2C_6_IRQ_PRI DT_SNPS_DESIGNWARE_I2C_91528000_IRQ_0_PRIORITY -#define CONFIG_I2C_6_IRQ_FLAGS DT_SNPS_DESIGNWARE_I2C_91528000_IRQ_0_SENSE -#define CONFIG_I2C_6_BITRATE DT_SNPS_DESIGNWARE_I2C_91528000_CLOCK_FREQUENCY +#define DT_I2C_6_IRQ_FLAGS DT_SNPS_DESIGNWARE_I2C_91528000_IRQ_0_SENSE +#define DT_I2C_6_BITRATE DT_SNPS_DESIGNWARE_I2C_91528000_CLOCK_FREQUENCY #define CONFIG_I2C_7_NAME DT_SNPS_DESIGNWARE_I2C_91526000_LABEL -#define CONFIG_I2C_7_BASE_ADDR DT_SNPS_DESIGNWARE_I2C_91526000_BASE_ADDRESS -#define CONFIG_I2C_7_IRQ DT_SNPS_DESIGNWARE_I2C_91526000_IRQ_0 +#define DT_I2C_7_BASE_ADDR DT_SNPS_DESIGNWARE_I2C_91526000_BASE_ADDRESS +#define DT_I2C_7_IRQ DT_SNPS_DESIGNWARE_I2C_91526000_IRQ_0 #define CONFIG_I2C_7_IRQ_PRI DT_SNPS_DESIGNWARE_I2C_91526000_IRQ_0_PRIORITY -#define CONFIG_I2C_7_IRQ_FLAGS DT_SNPS_DESIGNWARE_I2C_91526000_IRQ_0_SENSE -#define CONFIG_I2C_7_BITRATE DT_SNPS_DESIGNWARE_I2C_91526000_CLOCK_FREQUENCY +#define DT_I2C_7_IRQ_FLAGS DT_SNPS_DESIGNWARE_I2C_91526000_IRQ_0_SENSE +#define DT_I2C_7_BITRATE DT_SNPS_DESIGNWARE_I2C_91526000_CLOCK_FREQUENCY /* End of Board Level DTS fixup file */ diff --git a/boards/xtensa/intel_s1000_crb/dts_fixup.h b/boards/xtensa/intel_s1000_crb/dts_fixup.h index 8d6f9f5ef99..6bcb744a133 100644 --- a/boards/xtensa/intel_s1000_crb/dts_fixup.h +++ b/boards/xtensa/intel_s1000_crb/dts_fixup.h @@ -6,13 +6,13 @@ /* Board level DTS fixup file */ -#define CONFIG_CODEC_I2C_BUS_NAME \ +#define DT_CODEC_I2C_BUS_NAME \ SNPS_DESIGNWARE_I2C_80400_TI_TLV320DAC_18_BUS_NAME -#define CONFIG_CODEC_I2C_BUS_ADDR \ +#define DT_CODEC_I2C_BUS_ADDR \ SNPS_DESIGNWARE_I2C_80400_TI_TLV320DAC_18_BASE_ADDRESS -#define CONFIG_CODEC_NAME \ +#define DT_CODEC_NAME \ SNPS_DESIGNWARE_I2C_80400_TI_TLV320DAC_18_LABEL /* End of Board Level DTS fixup file */ diff --git a/drivers/adc/adc_dw.c b/drivers/adc/adc_dw.c index 40b1ff3b851..586ce9b40ff 100644 --- a/drivers/adc/adc_dw.c +++ b/drivers/adc/adc_dw.c @@ -480,7 +480,7 @@ static const struct adc_driver_api api_funcs = { }; const static struct adc_config adc_config_dev = { - .reg_base = CONFIG_ADC_0_BASE_ADDRESS, + .reg_base = DT_ADC_0_BASE_ADDRESS, .reg_irq_mask = SCSS_REGISTER_BASE + INT_SS_ADC_IRQ_MASK, .reg_err_mask = SCSS_REGISTER_BASE + INT_SS_ADC_ERR_MASK, #ifdef CONFIG_ADC_DW_SERIAL @@ -507,11 +507,11 @@ DEVICE_AND_API_INIT(adc_dw, CONFIG_ADC_0_NAME, &adc_dw_init, static void adc_config_irq(void) { - IRQ_CONNECT(CONFIG_ADC_0_IRQ, CONFIG_ADC_0_IRQ_PRI, adc_dw_rx_isr, + IRQ_CONNECT(DT_ADC_0_IRQ, CONFIG_ADC_0_IRQ_PRI, adc_dw_rx_isr, DEVICE_GET(adc_dw), 0); - irq_enable(CONFIG_ADC_0_IRQ); + irq_enable(DT_ADC_0_IRQ); - IRQ_CONNECT(CONFIG_ADC_IRQ_ERR, CONFIG_ADC_0_IRQ_PRI, + IRQ_CONNECT(DT_ADC_IRQ_ERR, CONFIG_ADC_0_IRQ_PRI, adc_dw_err_isr, DEVICE_GET(adc_dw), 0); - irq_enable(CONFIG_ADC_IRQ_ERR); + irq_enable(DT_ADC_IRQ_ERR); } diff --git a/drivers/adc/adc_intel_quark_d2000.c b/drivers/adc/adc_intel_quark_d2000.c index 424f44ba96e..dd4da744257 100644 --- a/drivers/adc/adc_intel_quark_d2000.c +++ b/drivers/adc/adc_intel_quark_d2000.c @@ -481,7 +481,7 @@ static const struct adc_driver_api adc_quark_d2000_driver_api = { static void adc_quark_d2000_config_func_0(struct device *dev); static const struct adc_quark_d2000_config adc_quark_d2000_config_0 = { - .reg_base = (adc_reg_t *)CONFIG_ADC_0_BASE_ADDRESS, + .reg_base = (adc_reg_t *)DT_ADC_0_BASE_ADDRESS, .config_func = adc_quark_d2000_config_func_0, }; @@ -493,11 +493,11 @@ DEVICE_AND_API_INIT(adc_quark_d2000_0, CONFIG_ADC_0_NAME, static void adc_quark_d2000_config_func_0(struct device *dev) { - IRQ_CONNECT(CONFIG_ADC_0_IRQ, CONFIG_ADC_0_IRQ_PRI, + IRQ_CONNECT(DT_ADC_0_IRQ, CONFIG_ADC_0_IRQ_PRI, adc_quark_d2000_isr, DEVICE_GET(adc_quark_d2000_0), - CONFIG_ADC_0_IRQ_FLAGS); + DT_ADC_0_IRQ_FLAGS); - irq_enable(CONFIG_ADC_0_IRQ); + irq_enable(DT_ADC_0_IRQ); } #endif /* CONFIG_ADC_0 */ diff --git a/drivers/adc/adc_mcux_adc16.c b/drivers/adc/adc_mcux_adc16.c index 77ec65ad660..c221625a100 100644 --- a/drivers/adc/adc_mcux_adc16.c +++ b/drivers/adc/adc_mcux_adc16.c @@ -223,7 +223,7 @@ static const struct adc_driver_api mcux_adc16_driver_api = { static void mcux_adc16_config_func_0(struct device *dev); static const struct mcux_adc16_config mcux_adc16_config_0 = { - .base = (ADC_Type *)CONFIG_ADC_0_BASE_ADDRESS, + .base = (ADC_Type *)DT_ADC_0_BASE_ADDRESS, .irq_config_func = mcux_adc16_config_func_0, }; @@ -240,10 +240,10 @@ DEVICE_AND_API_INIT(mcux_adc16_0, CONFIG_ADC_0_NAME, &mcux_adc16_init, static void mcux_adc16_config_func_0(struct device *dev) { - IRQ_CONNECT(CONFIG_ADC_0_IRQ, CONFIG_ADC_0_IRQ_PRI, + IRQ_CONNECT(DT_ADC_0_IRQ, CONFIG_ADC_0_IRQ_PRI, mcux_adc16_isr, DEVICE_GET(mcux_adc16_0), 0); - irq_enable(CONFIG_ADC_0_IRQ); + irq_enable(DT_ADC_0_IRQ); } #endif /* CONFIG_ADC_0 */ @@ -251,7 +251,7 @@ static void mcux_adc16_config_func_0(struct device *dev) static void mcux_adc16_config_func_1(struct device *dev); static const struct mcux_adc16_config mcux_adc16_config_1 = { - .base = (ADC_Type *)CONFIG_ADC_1_BASE_ADDRESS, + .base = (ADC_Type *)DT_ADC_1_BASE_ADDRESS, .irq_config_func = mcux_adc16_config_func_1, }; @@ -268,9 +268,9 @@ DEVICE_AND_API_INIT(mcux_adc16_1, CONFIG_ADC_1_NAME, &mcux_adc16_init, static void mcux_adc16_config_func_1(struct device *dev) { - IRQ_CONNECT(CONFIG_ADC_1_IRQ, CONFIG_ADC_1_IRQ_PRI, + IRQ_CONNECT(DT_ADC_1_IRQ, CONFIG_ADC_1_IRQ_PRI, mcux_adc16_isr, DEVICE_GET(mcux_adc16_1), 0); - irq_enable(CONFIG_ADC_1_IRQ); + irq_enable(DT_ADC_1_IRQ); } #endif /* CONFIG_ADC_1 */ diff --git a/drivers/adc/adc_nrfx_adc.c b/drivers/adc/adc_nrfx_adc.c index 4224f42e166..b1fb069c22f 100644 --- a/drivers/adc/adc_nrfx_adc.c +++ b/drivers/adc/adc_nrfx_adc.c @@ -253,7 +253,7 @@ static int init_adc(struct device *dev) return -EBUSY; } - IRQ_CONNECT(CONFIG_ADC_0_IRQ, CONFIG_ADC_0_IRQ_PRI, + IRQ_CONNECT(DT_ADC_0_IRQ, CONFIG_ADC_0_IRQ_PRI, nrfx_isr, nrfx_adc_irq_handler, 0); adc_context_unlock_unconditionally(&m_data.ctx); diff --git a/drivers/adc/adc_nrfx_saadc.c b/drivers/adc/adc_nrfx_saadc.c index 4f8db7b6b3b..d2023fb1d99 100644 --- a/drivers/adc/adc_nrfx_saadc.c +++ b/drivers/adc/adc_nrfx_saadc.c @@ -366,9 +366,9 @@ static int init_saadc(struct device *dev) { nrf_saadc_event_clear(NRF_SAADC_EVENT_END); nrf_saadc_int_enable(NRF_SAADC_INT_END); - NRFX_IRQ_ENABLE(CONFIG_ADC_0_IRQ); + NRFX_IRQ_ENABLE(DT_ADC_0_IRQ); - IRQ_CONNECT(CONFIG_ADC_0_IRQ, CONFIG_ADC_0_IRQ_PRI, + IRQ_CONNECT(DT_ADC_0_IRQ, CONFIG_ADC_0_IRQ_PRI, saadc_irq_handler, DEVICE_GET(adc_0), 0); adc_context_unlock_unconditionally(&m_data.ctx); diff --git a/drivers/adc/adc_sam_afec.c b/drivers/adc/adc_sam_afec.c index 89e81266700..056af0a4cab 100644 --- a/drivers/adc/adc_sam_afec.c +++ b/drivers/adc/adc_sam_afec.c @@ -345,9 +345,9 @@ static void adc_sam_isr(void *arg) static void adc0_sam_cfg_func(struct device *dev); static const struct adc_sam_cfg adc0_sam_cfg = { - .regs = (Afec *)CONFIG_ADC_0_BASE_ADDRESS, + .regs = (Afec *)DT_ADC_0_BASE_ADDRESS, .cfg_func = adc0_sam_cfg_func, - .periph_id = CONFIG_ADC_0_PERIPHERAL_ID, + .periph_id = DT_ADC_0_PERIPHERAL_ID, .afec_trg_pin = PIN_AFE0_ADTRG, }; @@ -363,9 +363,9 @@ DEVICE_AND_API_INIT(adc0_sam, CONFIG_ADC_0_NAME, adc_sam_init, static void adc0_sam_cfg_func(struct device *dev) { - IRQ_CONNECT(CONFIG_ADC_0_IRQ, CONFIG_ADC_0_IRQ_PRI, adc_sam_isr, + IRQ_CONNECT(DT_ADC_0_IRQ, CONFIG_ADC_0_IRQ_PRI, adc_sam_isr, DEVICE_GET(adc0_sam), 0); - irq_enable(CONFIG_ADC_0_IRQ); + irq_enable(DT_ADC_0_IRQ); } #endif /* CONFIG_ADC_0 */ @@ -374,9 +374,9 @@ static void adc0_sam_cfg_func(struct device *dev) static void adc1_sam_cfg_func(struct device *dev); static const struct adc_sam_cfg adc1_sam_cfg = { - .regs = (Afec *)CONFIG_ADC_1_BASE_ADDRESS, + .regs = (Afec *)DT_ADC_1_BASE_ADDRESS, .cfg_func = adc1_sam_cfg_func, - .periph_id = CONFIG_ADC_1_PERIPHERAL_ID, + .periph_id = DT_ADC_1_PERIPHERAL_ID, .afec_trg_pin = PIN_AFE1_ADTRG, }; @@ -392,9 +392,9 @@ DEVICE_AND_API_INIT(adc1_sam, CONFIG_ADC_1_NAME, adc_sam_init, static void adc1_sam_cfg_func(struct device *dev) { - IRQ_CONNECT(CONFIG_ADC_1_IRQ, CONFIG_ADC_1_IRQ_PRI, adc_sam_isr, + IRQ_CONNECT(DT_ADC_1_IRQ, CONFIG_ADC_1_IRQ_PRI, adc_sam_isr, DEVICE_GET(adc1_sam), 0); - irq_enable(CONFIG_ADC_1_IRQ); + irq_enable(DT_ADC_1_IRQ); } #endif /* CONFIG_ADC_1 */ diff --git a/drivers/audio/tlv320dac310x.c b/drivers/audio/tlv320dac310x.c index d14e998c5ce..6dad6428740 100644 --- a/drivers/audio/tlv320dac310x.c +++ b/drivers/audio/tlv320dac310x.c @@ -33,8 +33,8 @@ struct codec_driver_data { static struct codec_driver_config codec_device_config = { .i2c_device = NULL, - .i2c_dev_name = CONFIG_CODEC_I2C_BUS_NAME, - .i2c_address = CONFIG_CODEC_I2C_BUS_ADDR, + .i2c_dev_name = DT_CODEC_I2C_BUS_NAME, + .i2c_address = DT_CODEC_I2C_BUS_ADDR, }; static struct codec_driver_data codec_device_data; @@ -509,6 +509,6 @@ static const struct audio_codec_api codec_driver_api = { .apply_properties = codec_apply_properties, }; -DEVICE_AND_API_INIT(tlv320dac310x, CONFIG_CODEC_NAME, codec_initialize, +DEVICE_AND_API_INIT(tlv320dac310x, DT_CODEC_NAME, codec_initialize, &codec_device_data, &codec_device_config, POST_KERNEL, CONFIG_AUDIO_CODEC_INIT_PRIORITY, &codec_driver_api); diff --git a/drivers/can/stm32_can.c b/drivers/can/stm32_can.c index 630e2f72cf4..d1dae4303ae 100644 --- a/drivers/can/stm32_can.c +++ b/drivers/can/stm32_can.c @@ -846,21 +846,21 @@ static const struct can_driver_api can_api_funcs = { static void config_can_1_irq(CAN_TypeDef *can); static const struct can_stm32_config can_stm32_cfg_1 = { - .can = (CAN_TypeDef *)CONFIG_CAN_1_BASE_ADDRESS, - .bus_speed = CONFIG_CAN_1_BUS_SPEED, - .swj = CONFIG_CAN_1_SJW, - .prop_bs1 = CONFIG_CAN_1_PROP_SEG_PHASE_SEG1, - .bs2 = CONFIG_CAN_1_PHASE_SEG2, + .can = (CAN_TypeDef *)DT_CAN_1_BASE_ADDRESS, + .bus_speed = DT_CAN_1_BUS_SPEED, + .swj = DT_CAN_1_SJW, + .prop_bs1 = DT_CAN_1_PROP_SEG_PHASE_SEG1, + .bs2 = DT_CAN_1_PHASE_SEG2, .pclken = { - .enr = CONFIG_CAN_1_CLOCK_BITS, - .bus = CONFIG_CAN_1_CLOCK_BUS, + .enr = DT_CAN_1_CLOCK_BITS, + .bus = DT_CAN_1_CLOCK_BUS, }, .config_irq = config_can_1_irq }; static struct can_stm32_data can_stm32_dev_data_1; -DEVICE_AND_API_INIT(can_stm32_1, CONFIG_CAN_1_NAME, &can_stm32_init, +DEVICE_AND_API_INIT(can_stm32_1, DT_CAN_1_NAME, &can_stm32_init, &can_stm32_dev_data_1, &can_stm32_cfg_1, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &can_api_funcs); @@ -869,21 +869,21 @@ static void config_can_1_irq(CAN_TypeDef *can) { LOG_DBG("Enable CAN1 IRQ"); #ifdef CONFIG_SOC_SERIES_STM32F0X - IRQ_CONNECT(CONFIG_CAN_1_IRQ, CONFIG_CAN_1_IRQ_PRIORITY, can_stm32_isr, + IRQ_CONNECT(DT_CAN_1_IRQ, DT_CAN_1_IRQ_PRIORITY, can_stm32_isr, DEVICE_GET(can_stm32_1), 0); - irq_enable(CONFIG_CAN_1_IRQ); + irq_enable(DT_CAN_1_IRQ); #else - IRQ_CONNECT(CONFIG_CAN_1_IRQ_RX0, CONFIG_CAN_1_IRQ_PRIORITY, + IRQ_CONNECT(DT_CAN_1_IRQ_RX0, DT_CAN_1_IRQ_PRIORITY, can_stm32_rx_isr, DEVICE_GET(can_stm32_1), 0); - irq_enable(CONFIG_CAN_1_IRQ_RX0); + irq_enable(DT_CAN_1_IRQ_RX0); - IRQ_CONNECT(CONFIG_CAN_1_IRQ_TX, CONFIG_CAN_1_IRQ_PRIORITY, + IRQ_CONNECT(DT_CAN_1_IRQ_TX, DT_CAN_1_IRQ_PRIORITY, can_stm32_tx_isr, DEVICE_GET(can_stm32_1), 0); - irq_enable(CONFIG_CAN_1_IRQ_TX); + irq_enable(DT_CAN_1_IRQ_TX); - IRQ_CONNECT(CONFIG_CAN_1_IRQ_SCE, CONFIG_CAN_1_IRQ_PRIORITY, + IRQ_CONNECT(DT_CAN_1_IRQ_SCE, DT_CAN_1_IRQ_PRIORITY, can_stm32_tx_isr, DEVICE_GET(can_stm32_1), 0); - irq_enable(CONFIG_CAN_1_IRQ_SCE); + irq_enable(DT_CAN_1_IRQ_SCE); #endif can->IER |= CAN_IT_TME | CAN_IT_ERR | CAN_IT_FMP0 | CAN_IT_FMP1; } diff --git a/drivers/clock_control/clock_control_mcux_ccm.c b/drivers/clock_control/clock_control_mcux_ccm.c index 4101b04a5b6..b14e7b55de9 100644 --- a/drivers/clock_control/clock_control_mcux_ccm.c +++ b/drivers/clock_control/clock_control_mcux_ccm.c @@ -75,7 +75,7 @@ static const struct clock_control_driver_api mcux_ccm_driver_api = { .get_rate = mcux_ccm_get_subsys_rate, }; -DEVICE_AND_API_INIT(mcux_ccm, CONFIG_MCUX_CCM_NAME, +DEVICE_AND_API_INIT(mcux_ccm, DT_MCUX_CCM_NAME, &mcux_ccm_init, NULL, NULL, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, diff --git a/drivers/clock_control/clock_control_mcux_sim.c b/drivers/clock_control/clock_control_mcux_sim.c index d467ed2f1cf..17815d98550 100644 --- a/drivers/clock_control/clock_control_mcux_sim.c +++ b/drivers/clock_control/clock_control_mcux_sim.c @@ -54,7 +54,7 @@ static const struct clock_control_driver_api mcux_sim_driver_api = { .get_rate = mcux_sim_get_subsys_rate, }; -DEVICE_AND_API_INIT(mcux_sim, CONFIG_SIM_NAME, +DEVICE_AND_API_INIT(mcux_sim, DT_SIM_NAME, &mcux_sim_init, NULL, NULL, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, diff --git a/drivers/counter/counter_dtmr_cmsdk_apb.c b/drivers/counter/counter_dtmr_cmsdk_apb.c index fe94588d74b..1185c8c9251 100644 --- a/drivers/counter/counter_dtmr_cmsdk_apb.c +++ b/drivers/counter/counter_dtmr_cmsdk_apb.c @@ -102,13 +102,13 @@ static int counter_dtmr_cmsdk_apb_init(struct device *dev) /* COUNTER 0 */ #ifdef CONFIG_COUNTER_DTMR_CMSDK_APB_0 static const struct counter_dtmr_cmsdk_apb_cfg counter_dtmr_cmsdk_apb_cfg_0 = { - .dtimer = ((volatile struct dualtimer_cmsdk_apb *)CMSDK_APB_DTIMER), + .dtimer = ((volatile struct dualtimer_cmsdk_apb *)DT_CMSDK_APB_DTIMER), .dtimer_cc_as = {.bus = CMSDK_APB, .state = SOC_ACTIVE, - .device = CMSDK_APB_DTIMER,}, + .device = DT_CMSDK_APB_DTIMER,}, .dtimer_cc_ss = {.bus = CMSDK_APB, .state = SOC_SLEEP, - .device = CMSDK_APB_DTIMER,}, + .device = DT_CMSDK_APB_DTIMER,}, .dtimer_cc_dss = {.bus = CMSDK_APB, .state = SOC_DEEPSLEEP, - .device = CMSDK_APB_DTIMER,}, + .device = DT_CMSDK_APB_DTIMER,}, }; DEVICE_AND_API_INIT(counter_dtmr_cmsdk_apb_0, diff --git a/drivers/counter/counter_tmr_cmsdk_apb.c b/drivers/counter/counter_tmr_cmsdk_apb.c index a4ae9d0b8ef..02deaca2e95 100644 --- a/drivers/counter/counter_tmr_cmsdk_apb.c +++ b/drivers/counter/counter_tmr_cmsdk_apb.c @@ -102,13 +102,13 @@ static int counter_tmr_cmsdk_apb_init(struct device *dev) /* COUNTER 0 */ #ifdef CONFIG_COUNTER_TMR_CMSDK_APB_0 static const struct counter_tmr_cmsdk_apb_cfg counter_tmr_cmsdk_apb_cfg_0 = { - .timer = ((volatile struct timer_cmsdk_apb *)CMSDK_APB_TIMER0), + .timer = ((volatile struct timer_cmsdk_apb *)DT_CMSDK_APB_TIMER0), .timer_cc_as = {.bus = CMSDK_APB, .state = SOC_ACTIVE, - .device = CMSDK_APB_TIMER0,}, + .device = DT_CMSDK_APB_TIMER0,}, .timer_cc_ss = {.bus = CMSDK_APB, .state = SOC_SLEEP, - .device = CMSDK_APB_TIMER0,}, + .device = DT_CMSDK_APB_TIMER0,}, .timer_cc_dss = {.bus = CMSDK_APB, .state = SOC_DEEPSLEEP, - .device = CMSDK_APB_TIMER0,}, + .device = DT_CMSDK_APB_TIMER0,}, }; DEVICE_AND_API_INIT(counter_tmr_cmsdk_apb_0, @@ -122,13 +122,13 @@ DEVICE_AND_API_INIT(counter_tmr_cmsdk_apb_0, /* COUNTER 1 */ #ifdef CONFIG_COUNTER_TMR_CMSDK_APB_1 static const struct counter_tmr_cmsdk_apb_cfg counter_tmr_cmsdk_apb_cfg_1 = { - .timer = ((volatile struct timer_cmsdk_apb *)CMSDK_APB_TIMER1), + .timer = ((volatile struct timer_cmsdk_apb *)DT_CMSDK_APB_TIMER1), .timer_cc_as = {.bus = CMSDK_APB, .state = SOC_ACTIVE, - .device = CMSDK_APB_TIMER1,}, + .device = DT_CMSDK_APB_TIMER1,}, .timer_cc_ss = {.bus = CMSDK_APB, .state = SOC_SLEEP, - .device = CMSDK_APB_TIMER1,}, + .device = DT_CMSDK_APB_TIMER1,}, .timer_cc_dss = {.bus = CMSDK_APB, .state = SOC_DEEPSLEEP, - .device = CMSDK_APB_TIMER1,}, + .device = DT_CMSDK_APB_TIMER1,}, }; DEVICE_AND_API_INIT(counter_tmr_cmsdk_apb_1, diff --git a/drivers/counter/timer_dtmr_cmsdk_apb.c b/drivers/counter/timer_dtmr_cmsdk_apb.c index d48fb92208f..310de69c40e 100644 --- a/drivers/counter/timer_dtmr_cmsdk_apb.c +++ b/drivers/counter/timer_dtmr_cmsdk_apb.c @@ -172,14 +172,14 @@ static int timer_dtmr_cmsdk_apb_init(struct device *dev) static void dtimer_cmsdk_apb_config_0(struct device *dev); static const struct timer_dtmr_cmsdk_apb_cfg timer_dtmr_cmsdk_apb_cfg_0 = { - .dtimer = ((volatile struct dualtimer_cmsdk_apb *)CMSDK_APB_DTIMER), + .dtimer = ((volatile struct dualtimer_cmsdk_apb *)DT_CMSDK_APB_DTIMER), .dtimer_config_func = dtimer_cmsdk_apb_config_0, .dtimer_cc_as = {.bus = CMSDK_APB, .state = SOC_ACTIVE, - .device = CMSDK_APB_DTIMER,}, + .device = DT_CMSDK_APB_DTIMER,}, .dtimer_cc_ss = {.bus = CMSDK_APB, .state = SOC_SLEEP, - .device = CMSDK_APB_DTIMER,}, + .device = DT_CMSDK_APB_DTIMER,}, .dtimer_cc_dss = {.bus = CMSDK_APB, .state = SOC_DEEPSLEEP, - .device = CMSDK_APB_DTIMER,}, + .device = DT_CMSDK_APB_DTIMER,}, }; static struct timer_dtmr_cmsdk_apb_dev_data timer_dtmr_cmsdk_apb_dev_data_0 = { @@ -197,10 +197,10 @@ DEVICE_AND_API_INIT(timer_dtmr_cmsdk_apb_0, static void dtimer_cmsdk_apb_config_0(struct device *dev) { - IRQ_CONNECT(CMSDK_APB_DUALTIMER_IRQ, + IRQ_CONNECT(DT_CMSDK_APB_DUALTIMER_IRQ, CONFIG_TIMER_DTMR_CMSDK_APB_0_IRQ_PRI, timer_dtmr_cmsdk_apb_isr, DEVICE_GET(timer_dtmr_cmsdk_apb_0), 0); - irq_enable(CMSDK_APB_DUALTIMER_IRQ); + irq_enable(DT_CMSDK_APB_DUALTIMER_IRQ); } #endif /* CONFIG_TIMER_DTMR_CMSDK_APB_0 */ diff --git a/drivers/counter/timer_tmr_cmsdk_apb.c b/drivers/counter/timer_tmr_cmsdk_apb.c index 77e7f45bc21..16cef514877 100644 --- a/drivers/counter/timer_tmr_cmsdk_apb.c +++ b/drivers/counter/timer_tmr_cmsdk_apb.c @@ -173,14 +173,14 @@ static int timer_tmr_cmsdk_apb_init(struct device *dev) static void timer_cmsdk_apb_config_0(struct device *dev); static const struct timer_tmr_cmsdk_apb_cfg timer_tmr_cmsdk_apb_cfg_0 = { - .timer = ((volatile struct timer_cmsdk_apb *)CMSDK_APB_TIMER0), + .timer = ((volatile struct timer_cmsdk_apb *)DT_CMSDK_APB_TIMER0), .timer_config_func = timer_cmsdk_apb_config_0, .timer_cc_as = {.bus = CMSDK_APB, .state = SOC_ACTIVE, - .device = CMSDK_APB_TIMER0,}, + .device = DT_CMSDK_APB_TIMER0,}, .timer_cc_ss = {.bus = CMSDK_APB, .state = SOC_SLEEP, - .device = CMSDK_APB_TIMER0,}, + .device = DT_CMSDK_APB_TIMER0,}, .timer_cc_dss = {.bus = CMSDK_APB, .state = SOC_DEEPSLEEP, - .device = CMSDK_APB_TIMER0,}, + .device = DT_CMSDK_APB_TIMER0,}, }; static struct timer_tmr_cmsdk_apb_dev_data timer_tmr_cmsdk_apb_dev_data_0 = { @@ -197,10 +197,10 @@ DEVICE_AND_API_INIT(timer_tmr_cmsdk_apb_0, static void timer_cmsdk_apb_config_0(struct device *dev) { - IRQ_CONNECT(CMSDK_APB_TIMER_0_IRQ, CONFIG_TIMER_TMR_CMSDK_APB_0_IRQ_PRI, + IRQ_CONNECT(DT_CMSDK_APB_TIMER_0_IRQ, CONFIG_TIMER_TMR_CMSDK_APB_0_IRQ_PRI, timer_tmr_cmsdk_apb_isr, DEVICE_GET(timer_tmr_cmsdk_apb_0), 0); - irq_enable(CMSDK_APB_TIMER_0_IRQ); + irq_enable(DT_CMSDK_APB_TIMER_0_IRQ); } #endif /* CONFIG_TIMER_TMR_CMSDK_APB_0 */ @@ -209,14 +209,14 @@ static void timer_cmsdk_apb_config_0(struct device *dev) static void timer_cmsdk_apb_config_1(struct device *dev); static const struct timer_tmr_cmsdk_apb_cfg timer_tmr_cmsdk_apb_cfg_1 = { - .timer = ((volatile struct timer_cmsdk_apb *)CMSDK_APB_TIMER1), + .timer = ((volatile struct timer_cmsdk_apb *)DT_CMSDK_APB_TIMER1), .timer_config_func = timer_cmsdk_apb_config_1, .timer_cc_as = {.bus = CMSDK_APB, .state = SOC_ACTIVE, - .device = CMSDK_APB_TIMER1,}, + .device = DT_CMSDK_APB_TIMER1,}, .timer_cc_ss = {.bus = CMSDK_APB, .state = SOC_SLEEP, - .device = CMSDK_APB_TIMER1,}, + .device = DT_CMSDK_APB_TIMER1,}, .timer_cc_dss = {.bus = CMSDK_APB, .state = SOC_DEEPSLEEP, - .device = CMSDK_APB_TIMER1,}, + .device = DT_CMSDK_APB_TIMER1,}, }; static struct timer_tmr_cmsdk_apb_dev_data timer_tmr_cmsdk_apb_dev_data_1 = { @@ -233,9 +233,9 @@ DEVICE_AND_API_INIT(timer_tmr_cmsdk_apb_1, static void timer_cmsdk_apb_config_1(struct device *dev) { - IRQ_CONNECT(CMSDK_APB_TIMER_1_IRQ, CONFIG_TIMER_TMR_CMSDK_APB_1_IRQ_PRI, + IRQ_CONNECT(DT_CMSDK_APB_TIMER_1_IRQ, CONFIG_TIMER_TMR_CMSDK_APB_1_IRQ_PRI, timer_tmr_cmsdk_apb_isr, DEVICE_GET(timer_tmr_cmsdk_apb_0), 0); - irq_enable(CMSDK_APB_TIMER_1_IRQ); + irq_enable(DT_CMSDK_APB_TIMER_1_IRQ); } #endif /* CONFIG_TIMER_TMR_CMSDK_APB_1 */ diff --git a/drivers/display/display_ili9340.c b/drivers/display/display_ili9340.c index b2ad7838d33..3ba46e27462 100644 --- a/drivers/display/display_ili9340.c +++ b/drivers/display/display_ili9340.c @@ -41,15 +41,15 @@ static int ili9340_init(struct device *dev) LOG_DBG("Initializing display driver"); - data->spi_dev = device_get_binding(CONFIG_ILI9340_SPI_DEV_NAME); + data->spi_dev = device_get_binding(DT_ILI9340_SPI_DEV_NAME); if (data->spi_dev == NULL) { LOG_ERR("Could not get SPI device for ILI9340"); return -EPERM; } - data->spi_config.frequency = CONFIG_ILI9340_SPI_FREQ; + data->spi_config.frequency = DT_ILI9340_SPI_FREQ; data->spi_config.operation = SPI_OP_MODE_MASTER | SPI_WORD_SET(8); - data->spi_config.slave = CONFIG_ILI9340_SPI_SLAVE_NUMBER; + data->spi_config.slave = DT_ILI9340_SPI_SLAVE_NUMBER; #ifdef CONFIG_ILI9340_GPIO_CS data->cs_ctrl.gpio_dev = @@ -62,31 +62,31 @@ static int ili9340_init(struct device *dev) #endif data->reset_gpio = - device_get_binding(CONFIG_ILI9340_RESET_GPIO_PORT_NAME); + device_get_binding(DT_ILI9340_RESET_GPIO_PORT_NAME); if (data->reset_gpio == NULL) { LOG_ERR("Could not get GPIO port for ILI9340 reset"); return -EPERM; } - gpio_pin_configure(data->reset_gpio, CONFIG_ILI9340_RESET_PIN, + gpio_pin_configure(data->reset_gpio, DT_ILI9340_RESET_PIN, GPIO_DIR_OUT); data->command_data_gpio = - device_get_binding(CONFIG_ILI9340_CMD_DATA_GPIO_PORT_NAME); + device_get_binding(DT_ILI9340_CMD_DATA_GPIO_PORT_NAME); if (data->command_data_gpio == NULL) { LOG_ERR("Could not get GPIO port for ILI9340 command/data"); return -EPERM; } - gpio_pin_configure(data->command_data_gpio, CONFIG_ILI9340_CMD_DATA_PIN, + gpio_pin_configure(data->command_data_gpio, DT_ILI9340_CMD_DATA_PIN, GPIO_DIR_OUT); LOG_DBG("Resetting display driver"); - gpio_pin_write(data->reset_gpio, CONFIG_ILI9340_RESET_PIN, 1); + gpio_pin_write(data->reset_gpio, DT_ILI9340_RESET_PIN, 1); k_sleep(1); - gpio_pin_write(data->reset_gpio, CONFIG_ILI9340_RESET_PIN, 0); + gpio_pin_write(data->reset_gpio, DT_ILI9340_RESET_PIN, 0); k_sleep(1); - gpio_pin_write(data->reset_gpio, CONFIG_ILI9340_RESET_PIN, 1); + gpio_pin_write(data->reset_gpio, DT_ILI9340_RESET_PIN, 1); k_sleep(5); LOG_DBG("Initializing LCD"); @@ -242,7 +242,7 @@ void ili9340_transmit(struct ili9340_data *data, u8_t cmd, void *tx_data, struct spi_buf tx_buf = { .buf = &cmd, .len = 1 }; struct spi_buf_set tx_bufs = { .buffers = &tx_buf, .count = 1 }; - gpio_pin_write(data->command_data_gpio, CONFIG_ILI9340_CMD_DATA_PIN, + gpio_pin_write(data->command_data_gpio, DT_ILI9340_CMD_DATA_PIN, ILI9340_CMD_DATA_PIN_COMMAND); spi_write(data->spi_dev, &data->spi_config, &tx_bufs); @@ -250,7 +250,7 @@ void ili9340_transmit(struct ili9340_data *data, u8_t cmd, void *tx_data, tx_buf.buf = tx_data; tx_buf.len = tx_len; gpio_pin_write(data->command_data_gpio, - CONFIG_ILI9340_CMD_DATA_PIN, + DT_ILI9340_CMD_DATA_PIN, ILI9340_CMD_DATA_PIN_DATA); spi_write(data->spi_dev, &data->spi_config, &tx_bufs); } @@ -271,6 +271,6 @@ static const struct display_driver_api ili9340_api = { static struct ili9340_data ili9340_data; -DEVICE_AND_API_INIT(ili9340, CONFIG_ILI9340_DEV_NAME, &ili9340_init, +DEVICE_AND_API_INIT(ili9340, DT_ILI9340_DEV_NAME, &ili9340_init, &ili9340_data, NULL, APPLICATION, CONFIG_APPLICATION_INIT_PRIORITY, &ili9340_api); diff --git a/drivers/display/mb_display.c b/drivers/display/mb_display.c index 402639dcf2a..d3a655f6b4b 100644 --- a/drivers/display/mb_display.c +++ b/drivers/display/mb_display.c @@ -26,51 +26,51 @@ /* Onboard LED Row 1 */ #define LED_ROW1_GPIO_PIN 13 -#define LED_ROW1_GPIO_PORT CONFIG_GPIO_P0_DEV_NAME +#define LED_ROW1_GPIO_PORT DT_GPIO_P0_DEV_NAME /* Onboard LED Row 2 */ #define LED_ROW2_GPIO_PIN 14 -#define LED_ROW2_GPIO_PORT CONFIG_GPIO_P0_DEV_NAME +#define LED_ROW2_GPIO_PORT DT_GPIO_P0_DEV_NAME /* Onboard LED Row 3 */ #define LED_ROW3_GPIO_PIN 15 -#define LED_ROW3_GPIO_PORT CONFIG_GPIO_P0_DEV_NAME +#define LED_ROW3_GPIO_PORT DT_GPIO_P0_DEV_NAME /* Onboard LED Column 1 */ #define LED_COL1_GPIO_PIN 4 -#define LED_COL1_GPIO_PORT CONFIG_GPIO_P0_DEV_NAME +#define LED_COL1_GPIO_PORT DT_GPIO_P0_DEV_NAME /* Onboard LED Column 2 */ #define LED_COL2_GPIO_PIN 5 -#define LED_COL2_GPIO_PORT CONFIG_GPIO_P0_DEV_NAME +#define LED_COL2_GPIO_PORT DT_GPIO_P0_DEV_NAME /* Onboard LED Column 3 */ #define LED_COL3_GPIO_PIN 6 -#define LED_COL3_GPIO_PORT CONFIG_GPIO_P0_DEV_NAME +#define LED_COL3_GPIO_PORT DT_GPIO_P0_DEV_NAME /* Onboard LED Column 4 */ #define LED_COL4_GPIO_PIN 7 -#define LED_COL4_GPIO_PORT CONFIG_GPIO_P0_DEV_NAME +#define LED_COL4_GPIO_PORT DT_GPIO_P0_DEV_NAME /* Onboard LED Column 5 */ #define LED_COL5_GPIO_PIN 8 -#define LED_COL5_GPIO_PORT CONFIG_GPIO_P0_DEV_NAME +#define LED_COL5_GPIO_PORT DT_GPIO_P0_DEV_NAME /* Onboard LED Column 6 */ #define LED_COL6_GPIO_PIN 9 -#define LED_COL6_GPIO_PORT CONFIG_GPIO_P0_DEV_NAME +#define LED_COL6_GPIO_PORT DT_GPIO_P0_DEV_NAME /* Onboard LED Column 7 */ #define LED_COL7_GPIO_PIN 10 -#define LED_COL7_GPIO_PORT CONFIG_GPIO_P0_DEV_NAME +#define LED_COL7_GPIO_PORT DT_GPIO_P0_DEV_NAME /* Onboard LED Column 8 */ #define LED_COL8_GPIO_PIN 11 -#define LED_COL8_GPIO_PORT CONFIG_GPIO_P0_DEV_NAME +#define LED_COL8_GPIO_PORT DT_GPIO_P0_DEV_NAME /* Onboard LED Column 9 */ #define LED_COL9_GPIO_PIN 12 -#define LED_COL9_GPIO_PORT CONFIG_GPIO_P0_DEV_NAME +#define LED_COL9_GPIO_PORT DT_GPIO_P0_DEV_NAME #define DISPLAY_ROWS 3 @@ -434,7 +434,7 @@ static int mb_display_init(struct device *dev) { ARG_UNUSED(dev); - display.dev = device_get_binding(CONFIG_GPIO_P0_DEV_NAME); + display.dev = device_get_binding(DT_GPIO_P0_DEV_NAME); __ASSERT(dev, "No GPIO device found"); diff --git a/drivers/display/ssd1306.c b/drivers/display/ssd1306.c index 500a5f3c41b..d07890352fb 100644 --- a/drivers/display/ssd1306.c +++ b/drivers/display/ssd1306.c @@ -17,19 +17,19 @@ LOG_MODULE_REGISTER(ssd1306); #include "ssd1306_regs.h" #include -#if CONFIG_SSD1306_PANEL_SEGMENT_REMAP == 1 +#if DT_SSD1306_PANEL_SEGMENT_REMAP == 1 #define SSD1306_PANEL_SEGMENT_REMAP true #else #define SSD1306_PANEL_SEGMENT_REMAP false #endif -#if CONFIG_SSD1306_PANEL_COM_INVDIR == 1 +#if DT_SSD1306_PANEL_COM_INVDIR == 1 #define SSD1306_PANEL_COM_INVDIR true #else #define SSD1306_PANEL_COM_INVDIR false #endif -#define SSD1306_PANEL_NUMOF_PAGES (SSD1306_PANEL_HEIGHT / 8) +#define SSD1306_PANEL_NUMOF_PAGES (DT_SSD1306_PANEL_HEIGHT / 8) #define SSD1306_CLOCK_DIV_RATIO 0x0 #define SSD1306_CLOCK_FREQUENCY 0x8 #define SSD1306_PANEL_MUX_RATIO 63 @@ -55,21 +55,21 @@ struct ssd1306_data { static inline int ssd1306_reg_read(struct ssd1306_data *driver, u8_t reg, u8_t * const val) { - return i2c_reg_read_byte(driver->i2c, CONFIG_SSD1306_I2C_ADDR, + return i2c_reg_read_byte(driver->i2c, DT_SSD1306_I2C_ADDR, reg, val); } static inline int ssd1306_reg_write(struct ssd1306_data *driver, u8_t reg, u8_t val) { - return i2c_reg_write_byte(driver->i2c, CONFIG_SSD1306_I2C_ADDR, + return i2c_reg_write_byte(driver->i2c, DT_SSD1306_I2C_ADDR, reg, val); } static inline int ssd1306_reg_update(struct ssd1306_data *driver, u8_t reg, u8_t mask, u8_t val) { - return i2c_reg_update_byte(driver->i2c, CONFIG_SSD1306_I2C_ADDR, + return i2c_reg_update_byte(driver->i2c, DT_SSD1306_I2C_ADDR, reg, mask, val); } @@ -88,7 +88,7 @@ static inline int ssd1306_set_panel_orientation(struct device *dev) }; return i2c_write(driver->i2c, cmd_buf, sizeof(cmd_buf), - CONFIG_SSD1306_I2C_ADDR); + DT_SSD1306_I2C_ADDR); } static inline int ssd1306_set_timing_setting(struct device *dev) @@ -102,7 +102,7 @@ static inline int ssd1306_set_timing_setting(struct device *dev) SSD1306_CONTROL_BYTE_CMD, SSD1306_SET_CHARGE_PERIOD, SSD1306_CONTROL_BYTE_CMD, - SSD1306_PANEL_PRECHARGE_PERIOD, + DT_SSD1306_PANEL_PRECHARGE_PERIOD, SSD1306_CONTROL_BYTE_CMD, SSD1306_SET_VCOM_DESELECT_LEVEL, SSD1306_CONTROL_LAST_BYTE_CMD, @@ -110,7 +110,7 @@ static inline int ssd1306_set_timing_setting(struct device *dev) }; return i2c_write(driver->i2c, cmd_buf, sizeof(cmd_buf), - CONFIG_SSD1306_I2C_ADDR); + DT_SSD1306_I2C_ADDR); } static inline int ssd1306_set_hardware_config(struct device *dev) @@ -122,7 +122,7 @@ static inline int ssd1306_set_hardware_config(struct device *dev) SSD1306_CONTROL_BYTE_CMD, SSD1306_SET_DISPLAY_OFFSET, SSD1306_CONTROL_BYTE_CMD, - SSD1306_PANEL_DISPLAY_OFFSET, + DT_SSD1306_PANEL_DISPLAY_OFFSET, SSD1306_CONTROL_BYTE_CMD, SSD1306_SET_PADS_HW_CONFIG, SSD1306_CONTROL_BYTE_CMD, @@ -134,7 +134,7 @@ static inline int ssd1306_set_hardware_config(struct device *dev) }; return i2c_write(driver->i2c, cmd_buf, sizeof(cmd_buf), - CONFIG_SSD1306_I2C_ADDR); + DT_SSD1306_I2C_ADDR); } static inline int ssd1306_set_charge_pump(const struct device *dev) @@ -158,7 +158,7 @@ static inline int ssd1306_set_charge_pump(const struct device *dev) }; return i2c_write(driver->i2c, cmd_buf, sizeof(cmd_buf), - CONFIG_SSD1306_I2C_ADDR); + DT_SSD1306_I2C_ADDR); } int ssd1306_resume(const struct device *dev) @@ -190,11 +190,11 @@ int ssd1306_write_page(struct device *dev, u8_t page, void * const data, #endif SSD1306_CONTROL_BYTE_CMD, SSD1306_SET_LOWER_COL_ADDRESS | - (SSD1306_PANEL_FIRST_SEG & + (DT_SSD1306_PANEL_FIRST_SEG & SSD1306_SET_LOWER_COL_ADDRESS_MASK), SSD1306_CONTROL_BYTE_CMD, SSD1306_SET_HIGHER_COL_ADDRESS | - ((SSD1306_PANEL_FIRST_SEG >> 4) & + ((DT_SSD1306_PANEL_FIRST_SEG >> 4) & SSD1306_SET_LOWER_COL_ADDRESS_MASK), SSD1306_CONTROL_LAST_BYTE_CMD, SSD1306_SET_PAGE_START_ADDRESS | page @@ -209,11 +209,11 @@ int ssd1306_write_page(struct device *dev, u8_t page, void * const data, } if (i2c_write(driver->i2c, cmd_buf, sizeof(cmd_buf), - CONFIG_SSD1306_I2C_ADDR)) { + DT_SSD1306_I2C_ADDR)) { return -1; } - return i2c_burst_write(driver->i2c, CONFIG_SSD1306_I2C_ADDR, + return i2c_burst_write(driver->i2c, DT_SSD1306_I2C_ADDR, SSD1306_CONTROL_LAST_BYTE_DATA, data, length); } @@ -265,25 +265,25 @@ int ssd1306_write(const struct device *dev, const u16_t x, const u16_t y, }; if (i2c_write(driver->i2c, cmd_buf, sizeof(cmd_buf), - CONFIG_SSD1306_I2C_ADDR)) { + DT_SSD1306_I2C_ADDR)) { LOG_ERR("Failed to write command"); return -1; } - return i2c_burst_write(driver->i2c, CONFIG_SSD1306_I2C_ADDR, + return i2c_burst_write(driver->i2c, DT_SSD1306_I2C_ADDR, SSD1306_CONTROL_LAST_BYTE_DATA, (u8_t *)buf, desc->buf_size); #elif defined(CONFIG_SSD1306_SH1106_COMPATIBLE) - if (len != SSD1306_PANEL_NUMOF_PAGES * SSD1306_PANEL_WIDTH) { + if (len != SSD1306_PANEL_NUMOF_PAGES * DT_SSD1306_PANEL_WIDTH) { return -1; } for (size_t pidx = 0; pidx < SSD1306_PANEL_NUMOF_PAGES; pidx++) { - if (ssd1306_write_page(dev, pidx, buf, SSD1306_PANEL_WIDTH)) { + if (ssd1306_write_page(dev, pidx, buf, DT_SSD1306_PANEL_WIDTH)) { return -1; } - buf = (u8_t *)buf + SSD1306_PANEL_WIDTH; + buf = (u8_t *)buf + DT_SSD1306_PANEL_WIDTH; } #endif @@ -323,15 +323,15 @@ int ssd1306_set_contrast(const struct device *dev, const u8_t contrast) }; return i2c_write(driver->i2c, cmd_buf, sizeof(cmd_buf), - CONFIG_SSD1306_I2C_ADDR); + DT_SSD1306_I2C_ADDR); } static void ssd1306_get_capabilities(const struct device *dev, struct display_capabilities *caps) { memset(caps, 0, sizeof(struct display_capabilities)); - caps->x_resolution = SSD1306_PANEL_WIDTH; - caps->y_resolution = SSD1306_PANEL_HEIGHT; + caps->x_resolution = DT_SSD1306_PANEL_WIDTH; + caps->y_resolution = DT_SSD1306_PANEL_HEIGHT; caps->supported_pixel_formats = PIXEL_FORMAT_MONO10; caps->current_pixel_format = PIXEL_FORMAT_MONO10; caps->screen_info = SCREEN_INFO_MONO_VTILED; @@ -378,7 +378,7 @@ static int ssd1306_init_device(struct device *dev) } if (i2c_write(driver->i2c, cmd_buf, sizeof(cmd_buf), - CONFIG_SSD1306_I2C_ADDR)) { + DT_SSD1306_I2C_ADDR)) { return -EIO; } @@ -397,10 +397,10 @@ static int ssd1306_init(struct device *dev) LOG_DBG(""); - driver->i2c = device_get_binding(CONFIG_SSD1306_I2C_MASTER_DEV_NAME); + driver->i2c = device_get_binding(DT_SSD1306_I2C_MASTER_DEV_NAME); if (driver->i2c == NULL) { LOG_ERR("Failed to get pointer to %s device!", - CONFIG_SSD1306_I2C_MASTER_DEV_NAME); + DT_SSD1306_I2C_MASTER_DEV_NAME); return -EINVAL; } @@ -426,7 +426,7 @@ static struct display_driver_api ssd1306_driver_api = { .set_pixel_format = ssd1306_set_pixel_format, }; -DEVICE_AND_API_INIT(ssd1306, CONFIG_SSD1306_DEV_NAME, ssd1306_init, +DEVICE_AND_API_INIT(ssd1306, DT_SSD1306_DEV_NAME, ssd1306_init, &ssd1306_driver, NULL, POST_KERNEL, CONFIG_APPLICATION_INIT_PRIORITY, &ssd1306_driver_api); diff --git a/drivers/display/ssd1673.c b/drivers/display/ssd1673.c index d5b80bb6dc2..7f91ac863d2 100644 --- a/drivers/display/ssd1673.c +++ b/drivers/display/ssd1673.c @@ -36,7 +36,7 @@ struct ssd1673_data { struct device *busy; struct device *spi_dev; struct spi_config spi_config; -#if defined(CONFIG_SSD1673_SPI_GPIO_CS) +#if defined(DT_SSD1673_SPI_GPIO_CS) struct spi_cs_control cs_ctrl; #endif u8_t contrast; @@ -69,7 +69,7 @@ static inline int ssd1673_write_cmd(struct ssd1673_data *driver, struct spi_buf buf = {.buf = &cmd, .len = sizeof(cmd)}; struct spi_buf_set buf_set = {.buffers = &buf, .count = 1}; - gpio_pin_write(driver->dc, CONFIG_SSD1673_DC_PIN, 0); + gpio_pin_write(driver->dc, DT_SSD1673_DC_PIN, 0); if (spi_write(driver->spi_dev, &driver->spi_config, &buf_set)) { return -1; } @@ -77,7 +77,7 @@ static inline int ssd1673_write_cmd(struct ssd1673_data *driver, if (data != NULL) { buf.buf = data; buf.len = len; - gpio_pin_write(driver->dc, CONFIG_SSD1673_DC_PIN, 1); + gpio_pin_write(driver->dc, DT_SSD1673_DC_PIN, 1); if (spi_write(driver->spi_dev, &driver->spi_config, &buf_set)) { return -1; } @@ -90,10 +90,10 @@ static inline void ssd1673_busy_wait(struct ssd1673_data *driver) { u32_t val = 0; - gpio_pin_read(driver->busy, CONFIG_SSD1673_BUSY_PIN, &val); + gpio_pin_read(driver->busy, DT_SSD1673_BUSY_PIN, &val); while (val) { k_busy_wait(SSD1673_BUSY_DELAY); - gpio_pin_read(driver->busy, CONFIG_SSD1673_BUSY_PIN, &val); + gpio_pin_read(driver->busy, DT_SSD1673_BUSY_PIN, &val); } } @@ -136,7 +136,7 @@ static inline int ssd1673_set_ram_ptr(struct ssd1673_data *driver, static inline void ssd1673_set_orientation(struct ssd1673_data *driver) { -#if CONFIG_SSD1673_ORIENTATION_FLIPPED == 1 +#if DT_SSD1673_ORIENTATION_FLIPPED == 1 driver->scan_mode = SSD1673_DATA_ENTRY_XIYDY; #else driver->scan_mode = SSD1673_DATA_ENTRY_XDYIY; @@ -298,12 +298,12 @@ static int ssd1673_write(const struct device *dev, const u16_t x, return -1; } - gpio_pin_write(driver->dc, CONFIG_SSD1673_DC_PIN, 0); + gpio_pin_write(driver->dc, DT_SSD1673_DC_PIN, 0); if (spi_write(driver->spi_dev, &driver->spi_config, &buf_set)) { return -1; } - gpio_pin_write(driver->dc, CONFIG_SSD1673_DC_PIN, 1); + gpio_pin_write(driver->dc, DT_SSD1673_DC_PIN, 1); /* clear unusable page */ if (driver->scan_mode == SSD1673_DATA_ENTRY_XDYIY) { sbuf.buf = dummy_page; @@ -397,9 +397,9 @@ static int ssd1673_controller_init(struct device *dev) LOG_DBG(""); - gpio_pin_write(driver->reset, CONFIG_SSD1673_RESET_PIN, 0); + gpio_pin_write(driver->reset, DT_SSD1673_RESET_PIN, 0); k_sleep(SSD1673_RESET_DELAY); - gpio_pin_write(driver->reset, CONFIG_SSD1673_RESET_PIN, 1); + gpio_pin_write(driver->reset, DT_SSD1673_RESET_PIN, 1); k_sleep(SSD1673_RESET_DELAY); ssd1673_busy_wait(driver); @@ -454,53 +454,53 @@ static int ssd1673_init(struct device *dev) LOG_DBG(""); - driver->spi_dev = device_get_binding(CONFIG_SSD1673_SPI_DEV_NAME); + driver->spi_dev = device_get_binding(DT_SSD1673_SPI_DEV_NAME); if (driver->spi_dev == NULL) { LOG_ERR("Could not get SPI device for SSD1673"); return -EIO; } - driver->spi_config.frequency = CONFIG_SSD1673_SPI_FREQ; + driver->spi_config.frequency = DT_SSD1673_SPI_FREQ; driver->spi_config.operation = SPI_OP_MODE_MASTER | SPI_WORD_SET(8); - driver->spi_config.slave = CONFIG_SSD1673_SPI_SLAVE_NUMBER; + driver->spi_config.slave = DT_SSD1673_SPI_SLAVE_NUMBER; driver->spi_config.cs = NULL; - driver->reset = device_get_binding(CONFIG_SSD1673_RESET_GPIO_PORT_NAME); + driver->reset = device_get_binding(DT_SSD1673_RESET_GPIO_PORT_NAME); if (driver->reset == NULL) { LOG_ERR("Could not get GPIO port for SSD1673 reset"); return -EIO; } - gpio_pin_configure(driver->reset, CONFIG_SSD1673_RESET_PIN, + gpio_pin_configure(driver->reset, DT_SSD1673_RESET_PIN, GPIO_DIR_OUT); - driver->dc = device_get_binding(CONFIG_SSD1673_DC_GPIO_PORT_NAME); + driver->dc = device_get_binding(DT_SSD1673_DC_GPIO_PORT_NAME); if (driver->dc == NULL) { LOG_ERR("Could not get GPIO port for SSD1673 DC signal"); return -EIO; } - gpio_pin_configure(driver->dc, CONFIG_SSD1673_DC_PIN, + gpio_pin_configure(driver->dc, DT_SSD1673_DC_PIN, GPIO_DIR_OUT); - driver->busy = device_get_binding(CONFIG_SSD1673_BUSY_GPIO_PORT_NAME); + driver->busy = device_get_binding(DT_SSD1673_BUSY_GPIO_PORT_NAME); if (driver->busy == NULL) { LOG_ERR("Could not get GPIO port for SSD1673 busy signal"); return -EIO; } - gpio_pin_configure(driver->busy, CONFIG_SSD1673_BUSY_PIN, + gpio_pin_configure(driver->busy, DT_SSD1673_BUSY_PIN, GPIO_DIR_IN); -#if defined(CONFIG_SSD1673_SPI_GPIO_CS) +#if defined(DT_SSD1673_SPI_GPIO_CS) driver->cs_ctrl.gpio_dev = device_get_binding( - CONFIG_SSD1673_SPI_GPIO_CS_DRV_NAME); + DT_SSD1673_SPI_GPIO_CS_DRV_NAME); if (!driver->cs_ctrl.gpio_dev) { LOG_ERR("Unable to get SPI GPIO CS device"); return -EIO; } - driver->cs_ctrl.gpio_pin = CONFIG_SSD1673_SPI_GPIO_CS_PIN; + driver->cs_ctrl.gpio_pin = DT_SSD1673_SPI_GPIO_CS_PIN; driver->cs_ctrl.delay = 0; driver->spi_config.cs = &driver->cs_ctrl; #endif @@ -526,7 +526,7 @@ static struct display_driver_api ssd1673_driver_api = { }; -DEVICE_AND_API_INIT(ssd1673, CONFIG_SSD1673_DEV_NAME, ssd1673_init, +DEVICE_AND_API_INIT(ssd1673, DT_SSD1673_DEV_NAME, ssd1673_init, &ssd1673_driver, NULL, POST_KERNEL, CONFIG_APPLICATION_INIT_PRIORITY, &ssd1673_driver_api); diff --git a/drivers/ethernet/eth_e1000.c b/drivers/ethernet/eth_e1000.c index da5b2210ca7..6f99d572616 100644 --- a/drivers/ethernet/eth_e1000.c +++ b/drivers/ethernet/eth_e1000.c @@ -212,11 +212,11 @@ static void e1000_init(struct net_if *iface) net_if_set_link_addr(iface, dev->mac, sizeof(dev->mac), NET_LINK_ETHERNET); - IRQ_CONNECT(CONFIG_ETH_E1000_IRQ, CONFIG_ETH_E1000_IRQ_PRIORITY, + IRQ_CONNECT(DT_ETH_E1000_IRQ, DT_ETH_E1000_IRQ_PRIORITY, e1000_isr, DEVICE_GET(eth_e1000), - CONFIG_ETH_E1000_IRQ_FLAGS); + DT_ETH_E1000_IRQ_FLAGS); - irq_enable(CONFIG_ETH_E1000_IRQ); + irq_enable(DT_ETH_E1000_IRQ); iow32(dev, CTRL, CTRL_SLU); /* Set link up */ diff --git a/drivers/ethernet/eth_mcux.c b/drivers/ethernet/eth_mcux.c index 2e78b716bab..19507792e97 100644 --- a/drivers/ethernet/eth_mcux.c +++ b/drivers/ethernet/eth_mcux.c @@ -968,35 +968,35 @@ static struct eth_context eth_0_context = { 0x04, 0x9f, #if defined(CONFIG_ETH_MCUX_0_MANUAL_MAC) - CONFIG_ETH_MCUX_0_MAC3, - CONFIG_ETH_MCUX_0_MAC4, - CONFIG_ETH_MCUX_0_MAC5 + DT_ETH_MCUX_0_MAC3, + DT_ETH_MCUX_0_MAC4, + DT_ETH_MCUX_0_MAC5 #endif } }; -ETH_NET_DEVICE_INIT(eth_mcux_0, CONFIG_ETH_MCUX_0_NAME, eth_0_init, +ETH_NET_DEVICE_INIT(eth_mcux_0, DT_ETH_MCUX_0_NAME, eth_0_init, ð_0_context, NULL, CONFIG_ETH_INIT_PRIORITY, &api_funcs, 1500); static void eth_0_config_func(void) { - IRQ_CONNECT(CONFIG_IRQ_ETH_RX, CONFIG_ETH_MCUX_0_IRQ_PRI, + IRQ_CONNECT(DT_IRQ_ETH_RX, DT_ETH_MCUX_0_IRQ_PRI, eth_mcux_rx_isr, DEVICE_GET(eth_mcux_0), 0); - irq_enable(CONFIG_IRQ_ETH_RX); + irq_enable(DT_IRQ_ETH_RX); - IRQ_CONNECT(CONFIG_IRQ_ETH_TX, CONFIG_ETH_MCUX_0_IRQ_PRI, + IRQ_CONNECT(DT_IRQ_ETH_TX, DT_ETH_MCUX_0_IRQ_PRI, eth_mcux_tx_isr, DEVICE_GET(eth_mcux_0), 0); - irq_enable(CONFIG_IRQ_ETH_TX); + irq_enable(DT_IRQ_ETH_TX); - IRQ_CONNECT(CONFIG_IRQ_ETH_ERR_MISC, CONFIG_ETH_MCUX_0_IRQ_PRI, + IRQ_CONNECT(DT_IRQ_ETH_ERR_MISC, DT_ETH_MCUX_0_IRQ_PRI, eth_mcux_error_isr, DEVICE_GET(eth_mcux_0), 0); - irq_enable(CONFIG_IRQ_ETH_ERR_MISC); + irq_enable(DT_IRQ_ETH_ERR_MISC); #if defined(CONFIG_PTP_CLOCK_MCUX) - IRQ_CONNECT(CONFIG_IRQ_ETH_IEEE1588_TMR, CONFIG_ETH_MCUX_0_IRQ_PRI, + IRQ_CONNECT(DT_IRQ_ETH_IEEE1588_TMR, DT_ETH_MCUX_0_IRQ_PRI, eth_mcux_ptp_isr, DEVICE_GET(eth_mcux_0), 0); - irq_enable(CONFIG_IRQ_ETH_IEEE1588_TMR); + irq_enable(DT_IRQ_ETH_IEEE1588_TMR); #endif } diff --git a/drivers/flash/flash_gecko.c b/drivers/flash/flash_gecko.c index a6a16e12fd4..b7eb5721611 100644 --- a/drivers/flash/flash_gecko.c +++ b/drivers/flash/flash_gecko.c @@ -189,6 +189,6 @@ static const struct flash_driver_api flash_gecko_driver_api = { static struct flash_gecko_data flash_gecko_0_data; -DEVICE_AND_API_INIT(flash_gecko_0, FLASH_DEV_NAME, +DEVICE_AND_API_INIT(flash_gecko_0, DT_FLASH_DEV_NAME, flash_gecko_init, &flash_gecko_0_data, NULL, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &flash_gecko_driver_api); diff --git a/drivers/flash/flash_sam0.c b/drivers/flash/flash_sam0.c index 36d74026f8b..39b9476a968 100644 --- a/drivers/flash/flash_sam0.c +++ b/drivers/flash/flash_sam0.c @@ -376,6 +376,6 @@ static const struct flash_driver_api flash_sam0_api = { static struct flash_sam0_data flash_sam0_data_0; -DEVICE_AND_API_INIT(flash_sam0, FLASH_DEV_NAME, +DEVICE_AND_API_INIT(flash_sam0, DT_FLASH_DEV_NAME, flash_sam0_init, &flash_sam0_data_0, NULL, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &flash_sam0_api); diff --git a/drivers/flash/flash_shell.c b/drivers/flash/flash_shell.c index ac3d7bee1ce..2eda678f025 100644 --- a/drivers/flash/flash_shell.c +++ b/drivers/flash/flash_shell.c @@ -36,7 +36,7 @@ static int cmd_erase(const struct shell *shell, size_t argc, char *argv[]) int result; u32_t size; - flash_dev = device_get_binding(FLASH_DEV_NAME); + flash_dev = device_get_binding(DT_FLASH_DEV_NAME); if (!flash_dev) { error(shell, "Flash driver was not found!"); return -ENODEV; @@ -76,7 +76,7 @@ static int cmd_write(const struct shell *shell, size_t argc, char *argv[]) u32_t w_addr; int j = 0; - flash_dev = device_get_binding(FLASH_DEV_NAME); + flash_dev = device_get_binding(DT_FLASH_DEV_NAME); if (!flash_dev) { error(shell, "Flash driver was not found!"); return -ENODEV; @@ -128,7 +128,7 @@ static int cmd_read(const struct shell *shell, size_t argc, char *argv[]) u32_t addr; int cnt; - flash_dev = device_get_binding(FLASH_DEV_NAME); + flash_dev = device_get_binding(DT_FLASH_DEV_NAME); if (!flash_dev) { error(shell, "Flash driver was not found!"); return -ENODEV; @@ -168,7 +168,7 @@ static int cmd_test(const struct shell *shell, size_t argc, char *argv[]) u32_t addr; u32_t size; - flash_dev = device_get_binding(FLASH_DEV_NAME); + flash_dev = device_get_binding(DT_FLASH_DEV_NAME); if (!flash_dev) { error(shell, "Flash driver was not found!"); return -ENODEV; diff --git a/drivers/flash/flash_stm32.c b/drivers/flash/flash_stm32.c index 649e3e91a08..b58c0e799e8 100644 --- a/drivers/flash/flash_stm32.c +++ b/drivers/flash/flash_stm32.c @@ -204,13 +204,13 @@ static int flash_stm32_write_protection(struct device *dev, bool enable) static struct flash_stm32_priv flash_data = { #if defined(CONFIG_SOC_SERIES_STM32F0X) - .regs = (struct stm32f0x_flash *) FLASH_DEV_BASE_ADDRESS, + .regs = (struct stm32f0x_flash *) DT_FLASH_DEV_BASE_ADDRESS, .pclken = { .bus = STM32_CLOCK_BUS_AHB1, .enr = LL_AHB1_GRP1_PERIPH_FLASH }, #elif defined(CONFIG_SOC_SERIES_STM32F4X) - .regs = (struct stm32f4x_flash *) FLASH_DEV_BASE_ADDRESS, + .regs = (struct stm32f4x_flash *) DT_FLASH_DEV_BASE_ADDRESS, #elif defined(CONFIG_SOC_SERIES_STM32L4X) - .regs = (struct stm32l4x_flash *) FLASH_DEV_BASE_ADDRESS, + .regs = (struct stm32l4x_flash *) DT_FLASH_DEV_BASE_ADDRESS, .pclken = { .bus = STM32_CLOCK_BUS_AHB1, .enr = LL_AHB1_GRP1_PERIPH_FLASH }, #endif @@ -260,6 +260,6 @@ static int stm32_flash_init(struct device *dev) return flash_stm32_write_protection(dev, false); } -DEVICE_AND_API_INIT(stm32_flash, FLASH_DEV_NAME, +DEVICE_AND_API_INIT(stm32_flash, DT_FLASH_DEV_NAME, stm32_flash_init, &flash_data, NULL, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &flash_stm32_api); diff --git a/drivers/flash/flash_stm32f3x.c b/drivers/flash/flash_stm32f3x.c index 8e0bf1ac213..15a9bbcaea2 100644 --- a/drivers/flash/flash_stm32f3x.c +++ b/drivers/flash/flash_stm32f3x.c @@ -133,7 +133,7 @@ static const struct flash_driver_api flash_stm32_api = { }; static const struct flash_stm32_dev_config flash_device_config = { - .base = (u32_t *)FLASH_DEV_BASE_ADDRESS, + .base = (u32_t *)DT_FLASH_DEV_BASE_ADDRESS, .pclken = { .bus = STM32_CLOCK_BUS_APB1, .enr = LL_AHB1_GRP1_PERIPH_FLASH}, }; @@ -142,7 +142,7 @@ static struct flash_stm32_dev_data flash_device_data = { }; -DEVICE_AND_API_INIT(flash_stm32, FLASH_DEV_NAME, +DEVICE_AND_API_INIT(flash_stm32, DT_FLASH_DEV_NAME, flash_stm32_init, &flash_device_data, &flash_device_config, diff --git a/drivers/flash/soc_flash_mcux.c b/drivers/flash/soc_flash_mcux.c index b1a2bfd6c6b..13c4454a089 100644 --- a/drivers/flash/soc_flash_mcux.c +++ b/drivers/flash/soc_flash_mcux.c @@ -151,7 +151,7 @@ static int flash_mcux_init(struct device *dev) return (rc == kStatus_Success) ? 0 : -EIO; } -DEVICE_AND_API_INIT(flash_mcux, FLASH_DEV_NAME, +DEVICE_AND_API_INIT(flash_mcux, DT_FLASH_DEV_NAME, flash_mcux_init, &flash_data, NULL, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &flash_mcux_api); diff --git a/drivers/flash/soc_flash_nrf.c b/drivers/flash/soc_flash_nrf.c index 0fdd3c516e1..d14da9d2109 100644 --- a/drivers/flash/soc_flash_nrf.c +++ b/drivers/flash/soc_flash_nrf.c @@ -239,7 +239,7 @@ static int nrf_flash_init(struct device *dev) return 0; } -DEVICE_INIT(nrf_flash, FLASH_DEV_NAME, nrf_flash_init, +DEVICE_INIT(nrf_flash, DT_FLASH_DEV_NAME, nrf_flash_init, NULL, NULL, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE); #if defined(CONFIG_SOC_FLASH_NRF_RADIO_SYNC) diff --git a/drivers/gpio/gpio_cc32xx.c b/drivers/gpio/gpio_cc32xx.c index 091163da1d2..9aa37d5ab4e 100644 --- a/drivers/gpio/gpio_cc32xx.c +++ b/drivers/gpio/gpio_cc32xx.c @@ -200,8 +200,8 @@ static const struct gpio_driver_api api_funcs = { #ifdef CONFIG_GPIO_CC32XX_A0 static const struct gpio_cc32xx_config gpio_cc32xx_a0_config = { - .port_base = CONFIG_GPIO_CC32XX_A0_BASE_ADDRESS, - .irq_num = CONFIG_GPIO_CC32XX_A0_IRQ+16, + .port_base = DT_GPIO_CC32XX_A0_BASE_ADDRESS, + .irq_num = DT_GPIO_CC32XX_A0_IRQ+16, }; static struct device DEVICE_NAME_GET(gpio_cc32xx_a0); @@ -211,16 +211,16 @@ static int gpio_cc32xx_a0_init(struct device *dev) { ARG_UNUSED(dev); - IRQ_CONNECT(CONFIG_GPIO_CC32XX_A0_IRQ, CONFIG_GPIO_CC32XX_A0_IRQ_PRI, + IRQ_CONNECT(DT_GPIO_CC32XX_A0_IRQ, DT_GPIO_CC32XX_A0_IRQ_PRI, gpio_cc32xx_port_isr, DEVICE_GET(gpio_cc32xx_a0), 0); - MAP_IntPendClear(CONFIG_GPIO_CC32XX_A0_IRQ+16); - irq_enable(CONFIG_GPIO_CC32XX_A0_IRQ); + MAP_IntPendClear(DT_GPIO_CC32XX_A0_IRQ+16); + irq_enable(DT_GPIO_CC32XX_A0_IRQ); return 0; } -DEVICE_AND_API_INIT(gpio_cc32xx_a0, CONFIG_GPIO_CC32XX_A0_NAME, +DEVICE_AND_API_INIT(gpio_cc32xx_a0, DT_GPIO_CC32XX_A0_NAME, &gpio_cc32xx_a0_init, &gpio_cc32xx_a0_data, &gpio_cc32xx_a0_config, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, @@ -230,8 +230,8 @@ DEVICE_AND_API_INIT(gpio_cc32xx_a0, CONFIG_GPIO_CC32XX_A0_NAME, #ifdef CONFIG_GPIO_CC32XX_A1 static const struct gpio_cc32xx_config gpio_cc32xx_a1_config = { - .port_base = CONFIG_GPIO_CC32XX_A1_BASE_ADDRESS, - .irq_num = CONFIG_GPIO_CC32XX_A1_IRQ+16, + .port_base = DT_GPIO_CC32XX_A1_BASE_ADDRESS, + .irq_num = DT_GPIO_CC32XX_A1_IRQ+16, }; static struct device DEVICE_NAME_GET(gpio_cc32xx_a1); @@ -241,16 +241,16 @@ static int gpio_cc32xx_a1_init(struct device *dev) { ARG_UNUSED(dev); - IRQ_CONNECT(CONFIG_GPIO_CC32XX_A1_IRQ, CONFIG_GPIO_CC32XX_A1_IRQ_PRI, + IRQ_CONNECT(DT_GPIO_CC32XX_A1_IRQ, DT_GPIO_CC32XX_A1_IRQ_PRI, gpio_cc32xx_port_isr, DEVICE_GET(gpio_cc32xx_a1), 0); - MAP_IntPendClear(CONFIG_GPIO_CC32XX_A1_IRQ+16); - irq_enable(CONFIG_GPIO_CC32XX_A1_IRQ); + MAP_IntPendClear(DT_GPIO_CC32XX_A1_IRQ+16); + irq_enable(DT_GPIO_CC32XX_A1_IRQ); return 0; } -DEVICE_AND_API_INIT(gpio_cc32xx_a1, CONFIG_GPIO_CC32XX_A1_NAME, +DEVICE_AND_API_INIT(gpio_cc32xx_a1, DT_GPIO_CC32XX_A1_NAME, &gpio_cc32xx_a1_init, &gpio_cc32xx_a1_data, &gpio_cc32xx_a1_config, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, @@ -260,8 +260,8 @@ DEVICE_AND_API_INIT(gpio_cc32xx_a1, CONFIG_GPIO_CC32XX_A1_NAME, #ifdef CONFIG_GPIO_CC32XX_A2 static const struct gpio_cc32xx_config gpio_cc32xx_a2_config = { - .port_base = CONFIG_GPIO_CC32XX_A2_BASE_ADDRESS, - .irq_num = CONFIG_GPIO_CC32XX_A2_IRQ+16, + .port_base = DT_GPIO_CC32XX_A2_BASE_ADDRESS, + .irq_num = DT_GPIO_CC32XX_A2_IRQ+16, }; static struct device DEVICE_NAME_GET(gpio_cc32xx_a2); @@ -271,16 +271,16 @@ static int gpio_cc32xx_a2_init(struct device *dev) { ARG_UNUSED(dev); - IRQ_CONNECT(CONFIG_GPIO_CC32XX_A2_IRQ, CONFIG_GPIO_CC32XX_A2_IRQ_PRI, + IRQ_CONNECT(DT_GPIO_CC32XX_A2_IRQ, DT_GPIO_CC32XX_A2_IRQ_PRI, gpio_cc32xx_port_isr, DEVICE_GET(gpio_cc32xx_a2), 0); - MAP_IntPendClear(CONFIG_GPIO_CC32XX_A2_IRQ+16); - irq_enable(CONFIG_GPIO_CC32XX_A2_IRQ); + MAP_IntPendClear(DT_GPIO_CC32XX_A2_IRQ+16); + irq_enable(DT_GPIO_CC32XX_A2_IRQ); return 0; } -DEVICE_AND_API_INIT(gpio_cc32xx_a2, CONFIG_GPIO_CC32XX_A2_NAME, +DEVICE_AND_API_INIT(gpio_cc32xx_a2, DT_GPIO_CC32XX_A2_NAME, &gpio_cc32xx_a2_init, &gpio_cc32xx_a2_data, &gpio_cc32xx_a2_config, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, @@ -290,8 +290,8 @@ DEVICE_AND_API_INIT(gpio_cc32xx_a2, CONFIG_GPIO_CC32XX_A2_NAME, #ifdef CONFIG_GPIO_CC32XX_A3 static const struct gpio_cc32xx_config gpio_cc32xx_a3_config = { - .port_base = CONFIG_GPIO_CC32XX_A3_BASE_ADDRESS, - .irq_num = CONFIG_GPIO_CC32XX_A3_IRQ+16, + .port_base = DT_GPIO_CC32XX_A3_BASE_ADDRESS, + .irq_num = DT_GPIO_CC32XX_A3_IRQ+16, }; static struct device DEVICE_NAME_GET(gpio_cc32xx_a3); @@ -301,16 +301,16 @@ static int gpio_cc32xx_a3_init(struct device *dev) { ARG_UNUSED(dev); - IRQ_CONNECT(CONFIG_GPIO_CC32XX_A3_IRQ, CONFIG_GPIO_CC32XX_A3_IRQ_PRI, + IRQ_CONNECT(DT_GPIO_CC32XX_A3_IRQ, DT_GPIO_CC32XX_A3_IRQ_PRI, gpio_cc32xx_port_isr, DEVICE_GET(gpio_cc32xx_a3), 0); - MAP_IntPendClear(CONFIG_GPIO_CC32XX_A3_IRQ+16); - irq_enable(CONFIG_GPIO_CC32XX_A3_IRQ); + MAP_IntPendClear(DT_GPIO_CC32XX_A3_IRQ+16); + irq_enable(DT_GPIO_CC32XX_A3_IRQ); return 0; } -DEVICE_AND_API_INIT(gpio_cc32xx_a3, CONFIG_GPIO_CC32XX_A3_NAME, +DEVICE_AND_API_INIT(gpio_cc32xx_a3, DT_GPIO_CC32XX_A3_NAME, &gpio_cc32xx_a3_init, &gpio_cc32xx_a3_data, &gpio_cc32xx_a3_config, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, diff --git a/drivers/gpio/gpio_cmsdk_ahb.c b/drivers/gpio/gpio_cmsdk_ahb.c index 5ccca28a126..2173079ac93 100644 --- a/drivers/gpio/gpio_cmsdk_ahb.c +++ b/drivers/gpio/gpio_cmsdk_ahb.c @@ -307,14 +307,14 @@ static int gpio_cmsdk_ahb_init(struct device *dev) static void gpio_cmsdk_ahb_config_0(struct device *dev); static const struct gpio_cmsdk_ahb_cfg gpio_cmsdk_ahb_0_cfg = { - .port = ((volatile struct gpio_cmsdk_ahb *)CMSDK_AHB_GPIO0), + .port = ((volatile struct gpio_cmsdk_ahb *)DT_CMSDK_AHB_GPIO0), .gpio_config_func = gpio_cmsdk_ahb_config_0, .gpio_cc_as = {.bus = CMSDK_AHB, .state = SOC_ACTIVE, - .device = CMSDK_AHB_GPIO0,}, + .device = DT_CMSDK_AHB_GPIO0,}, .gpio_cc_ss = {.bus = CMSDK_AHB, .state = SOC_SLEEP, - .device = CMSDK_AHB_GPIO0,}, + .device = DT_CMSDK_AHB_GPIO0,}, .gpio_cc_dss = {.bus = CMSDK_AHB, .state = SOC_DEEPSLEEP, - .device = CMSDK_AHB_GPIO0,}, + .device = DT_CMSDK_AHB_GPIO0,}, }; static struct gpio_cmsdk_ahb_dev_data gpio_cmsdk_ahb_0_data; @@ -328,10 +328,10 @@ DEVICE_AND_API_INIT(gpio_cmsdk_ahb_0, static void gpio_cmsdk_ahb_config_0(struct device *dev) { - IRQ_CONNECT(IRQ_PORT0_ALL, CONFIG_GPIO_CMSDK_AHB_PORT0_IRQ_PRI, + IRQ_CONNECT(DT_IRQ_PORT0_ALL, CONFIG_GPIO_CMSDK_AHB_PORT0_IRQ_PRI, gpio_cmsdk_ahb_isr, DEVICE_GET(gpio_cmsdk_ahb_0), 0); - irq_enable(IRQ_PORT0_ALL); + irq_enable(DT_IRQ_PORT0_ALL); } #endif /* CONFIG_GPIO_CMSDK_AHB_PORT0 */ @@ -340,14 +340,14 @@ static void gpio_cmsdk_ahb_config_0(struct device *dev) static void gpio_cmsdk_ahb_config_1(struct device *dev); static const struct gpio_cmsdk_ahb_cfg gpio_cmsdk_ahb_1_cfg = { - .port = ((volatile struct gpio_cmsdk_ahb *)CMSDK_AHB_GPIO1), + .port = ((volatile struct gpio_cmsdk_ahb *)DT_CMSDK_AHB_GPIO1), .gpio_config_func = gpio_cmsdk_ahb_config_1, .gpio_cc_as = {.bus = CMSDK_AHB, .state = SOC_ACTIVE, - .device = CMSDK_AHB_GPIO1,}, + .device = DT_CMSDK_AHB_GPIO1,}, .gpio_cc_ss = {.bus = CMSDK_AHB, .state = SOC_SLEEP, - .device = CMSDK_AHB_GPIO1,}, + .device = DT_CMSDK_AHB_GPIO1,}, .gpio_cc_dss = {.bus = CMSDK_AHB, .state = SOC_DEEPSLEEP, - .device = CMSDK_AHB_GPIO1,}, + .device = DT_CMSDK_AHB_GPIO1,}, }; static struct gpio_cmsdk_ahb_dev_data gpio_cmsdk_ahb_1_data; @@ -361,10 +361,10 @@ DEVICE_AND_API_INIT(gpio_cmsdk_ahb_1, static void gpio_cmsdk_ahb_config_1(struct device *dev) { - IRQ_CONNECT(IRQ_PORT1_ALL, CONFIG_GPIO_CMSDK_AHB_PORT1_IRQ_PRI, + IRQ_CONNECT(DT_IRQ_PORT1_ALL, CONFIG_GPIO_CMSDK_AHB_PORT1_IRQ_PRI, gpio_cmsdk_ahb_isr, DEVICE_GET(gpio_cmsdk_ahb_1), 0); - irq_enable(IRQ_PORT1_ALL); + irq_enable(DT_IRQ_PORT1_ALL); } #endif /* CONFIG_GPIO_CMSDK_AHB_PORT1 */ @@ -373,14 +373,14 @@ static void gpio_cmsdk_ahb_config_1(struct device *dev) static void gpio_cmsdk_ahb_config_2(struct device *dev); static const struct gpio_cmsdk_ahb_cfg gpio_cmsdk_ahb_2_cfg = { - .port = ((volatile struct gpio_cmsdk_ahb *)CMSDK_AHB_GPIO2), + .port = ((volatile struct gpio_cmsdk_ahb *)DT_CMSDK_AHB_GPIO2), .gpio_config_func = gpio_cmsdk_ahb_config_2, .gpio_cc_as = {.bus = CMSDK_AHB, .state = SOC_ACTIVE, - .device = CMSDK_AHB_GPIO2,}, + .device = DT_CMSDK_AHB_GPIO2,}, .gpio_cc_ss = {.bus = CMSDK_AHB, .state = SOC_SLEEP, - .device = CMSDK_AHB_GPIO2,}, + .device = DT_CMSDK_AHB_GPIO2,}, .gpio_cc_dss = {.bus = CMSDK_AHB, .state = SOC_DEEPSLEEP, - .device = CMSDK_AHB_GPIO2,}, + .device = DT_CMSDK_AHB_GPIO2,}, }; static struct gpio_cmsdk_ahb_dev_data gpio_cmsdk_ahb_2_data; @@ -394,10 +394,10 @@ DEVICE_AND_API_INIT(gpio_cmsdk_ahb_2, static void gpio_cmsdk_ahb_config_2(struct device *dev) { - IRQ_CONNECT(IRQ_PORT2_ALL, CONFIG_GPIO_CMSDK_AHB_PORT2_IRQ_PRI, + IRQ_CONNECT(DT_IRQ_PORT2_ALL, CONFIG_GPIO_CMSDK_AHB_PORT2_IRQ_PRI, gpio_cmsdk_ahb_isr, DEVICE_GET(gpio_cmsdk_ahb_2), 0); - irq_enable(IRQ_PORT2_ALL); + irq_enable(DT_IRQ_PORT2_ALL); } #endif /* CONFIG_GPIO_CMSDK_AHB_PORT2 */ @@ -406,14 +406,14 @@ static void gpio_cmsdk_ahb_config_2(struct device *dev) static void gpio_cmsdk_ahb_config_3(struct device *dev); static const struct gpio_cmsdk_ahb_cfg gpio_cmsdk_ahb_3_cfg = { - .port = ((volatile struct gpio_cmsdk_ahb *)CMSDK_AHB_GPIO3), + .port = ((volatile struct gpio_cmsdk_ahb *)DT_CMSDK_AHB_GPIO3), .gpio_config_func = gpio_cmsdk_ahb_config_3, .gpio_cc_as = {.bus = CMSDK_AHB, .state = SOC_ACTIVE, - .device = CMSDK_AHB_GPIO3,}, + .device = DT_CMSDK_AHB_GPIO3,}, .gpio_cc_ss = {.bus = CMSDK_AHB, .state = SOC_SLEEP, - .device = CMSDK_AHB_GPIO3,}, + .device = DT_CMSDK_AHB_GPIO3,}, .gpio_cc_dss = {.bus = CMSDK_AHB, .state = SOC_DEEPSLEEP, - .device = CMSDK_AHB_GPIO3,}, + .device = DT_CMSDK_AHB_GPIO3,}, }; static struct gpio_cmsdk_ahb_dev_data gpio_cmsdk_ahb_3_data; @@ -427,9 +427,9 @@ DEVICE_AND_API_INIT(gpio_cmsdk_ahb_3, static void gpio_cmsdk_ahb_config_3(struct device *dev) { - IRQ_CONNECT(IRQ_PORT3_ALL, CONFIG_GPIO_CMSDK_AHB_PORT3_IRQ_PRI, + IRQ_CONNECT(DT_IRQ_PORT3_ALL, CONFIG_GPIO_CMSDK_AHB_PORT3_IRQ_PRI, gpio_cmsdk_ahb_isr, DEVICE_GET(gpio_cmsdk_ahb_3), 0); - irq_enable(IRQ_PORT3_ALL); + irq_enable(DT_IRQ_PORT3_ALL); } #endif /* CONFIG_GPIO_CMSDK_AHB_PORT3 */ diff --git a/drivers/gpio/gpio_dw.c b/drivers/gpio/gpio_dw.c index 044f9010f2f..021f8d23a32 100644 --- a/drivers/gpio/gpio_dw.c +++ b/drivers/gpio/gpio_dw.c @@ -499,9 +499,9 @@ static void gpio_config_0_irq(struct device *port); static const struct gpio_dw_config gpio_config_0 = { #ifdef CONFIG_GPIO_DW_0_IRQ_DIRECT - .irq_num = GPIO_DW_0_IRQ, + .irq_num = DT_GPIO_DW_0_IRQ, #endif - .bits = GPIO_DW_0_BITS, + .bits = DT_GPIO_DW_0_BITS, .config_func = gpio_config_0_irq, #ifdef CONFIG_GPIO_DW_0_IRQ_SHARED .shared_irq_dev_name = CONFIG_GPIO_DW_0_IRQ_SHARED_NAME, @@ -512,7 +512,7 @@ static const struct gpio_dw_config gpio_config_0 = { }; static struct gpio_dw_runtime gpio_0_runtime = { - .base_addr = GPIO_DW_0_BASE_ADDR, + .base_addr = DT_GPIO_DW_0_BASE_ADDR, #if CONFIG_PCI .pci_dev.class_type = GPIO_DW_PCI_CLASS, .pci_dev.bus = GPIO_DW_0_PCI_BUS, @@ -539,12 +539,12 @@ DEVICE_AND_API_INIT(gpio_dw_0, CONFIG_GPIO_DW_0_NAME, gpio_dw_initialize, static void gpio_config_0_irq(struct device *port) { -#if (GPIO_DW_0_IRQ > 0) +#if (DT_GPIO_DW_0_IRQ > 0) const struct gpio_dw_config *config = port->config->config_info; #ifdef CONFIG_GPIO_DW_0_IRQ_DIRECT - IRQ_CONNECT(GPIO_DW_0_IRQ, CONFIG_GPIO_DW_0_IRQ_PRI, gpio_dw_isr, - DEVICE_GET(gpio_dw_0), GPIO_DW_0_IRQ_FLAGS); + IRQ_CONNECT(DT_GPIO_DW_0_IRQ, CONFIG_GPIO_DW_0_IRQ_PRI, gpio_dw_isr, + DEVICE_GET(gpio_dw_0), DT_GPIO_DW_0_IRQ_FLAGS); irq_enable(config->irq_num); #elif defined(CONFIG_GPIO_DW_0_IRQ_SHARED) struct device *shared_irq_dev; @@ -567,9 +567,9 @@ static void gpio_config_1_irq(struct device *port); static const struct gpio_dw_config gpio_dw_config_1 = { #ifdef CONFIG_GPIO_DW_1_IRQ_DIRECT - .irq_num = GPIO_DW_1_IRQ, + .irq_num = DT_GPIO_DW_1_IRQ, #endif - .bits = GPIO_DW_1_BITS, + .bits = DT_GPIO_DW_1_BITS, .config_func = gpio_config_1_irq, #ifdef CONFIG_GPIO_DW_1_IRQ_SHARED @@ -581,7 +581,7 @@ static const struct gpio_dw_config gpio_dw_config_1 = { }; static struct gpio_dw_runtime gpio_1_runtime = { - .base_addr = GPIO_DW_1_BASE_ADDR, + .base_addr = DT_GPIO_DW_1_BASE_ADDR, #if CONFIG_PCI .pci_dev.class_type = GPIO_DW_PCI_CLASS, .pci_dev.bus = GPIO_DW_1_PCI_BUS, @@ -607,11 +607,11 @@ DEVICE_AND_API_INIT(gpio_dw_1, CONFIG_GPIO_DW_1_NAME, gpio_dw_initialize, static void gpio_config_1_irq(struct device *port) { -#if (GPIO_DW_1_IRQ > 0) +#if (DT_GPIO_DW_1_IRQ > 0) const struct gpio_dw_config *config = port->config->config_info; #ifdef CONFIG_GPIO_DW_1_IRQ_DIRECT - IRQ_CONNECT(GPIO_DW_1_IRQ, CONFIG_GPIO_DW_1_IRQ_PRI, gpio_dw_isr, + IRQ_CONNECT(DT_GPIO_DW_1_IRQ, CONFIG_GPIO_DW_1_IRQ_PRI, gpio_dw_isr, DEVICE_GET(gpio_dw_1), GPIO_DW_1_IRQ_FLAGS); irq_enable(config->irq_num); #elif defined(CONFIG_GPIO_DW_1_IRQ_SHARED) @@ -634,9 +634,9 @@ static void gpio_config_2_irq(struct device *port); static const struct gpio_dw_config gpio_dw_config_2 = { #ifdef CONFIG_GPIO_DW_2_IRQ_DIRECT - .irq_num = GPIO_DW_2_IRQ, + .irq_num = DT_GPIO_DW_2_IRQ, #endif - .bits = GPIO_DW_2_BITS, + .bits = DT_GPIO_DW_2_BITS, .config_func = gpio_config_2_irq, #ifdef CONFIG_GPIO_DW_2_IRQ_SHARED @@ -648,7 +648,7 @@ static const struct gpio_dw_config gpio_dw_config_2 = { }; static struct gpio_dw_runtime gpio_2_runtime = { - .base_addr = GPIO_DW_2_BASE_ADDR, + .base_addr = DT_GPIO_DW_2_BASE_ADDR, #if CONFIG_PCI .pci_dev.class_type = GPIO_DW_PCI_CLASS, .pci_dev.bus = GPIO_DW_2_PCI_BUS, @@ -674,11 +674,11 @@ DEVICE_AND_API_INIT(gpio_dw_2, CONFIG_GPIO_DW_2_NAME, gpio_dw_initialize, static void gpio_config_2_irq(struct device *port) { -#if (GPIO_DW_2_IRQ > 0) +#if (DT_GPIO_DW_2_IRQ > 0) const struct gpio_dw_config *config = port->config->config_info; #ifdef CONFIG_GPIO_DW_2_IRQ_DIRECT - IRQ_CONNECT(GPIO_DW_2_IRQ, CONFIG_GPIO_DW_2_IRQ_PRI, gpio_dw_isr, + IRQ_CONNECT(DT_GPIO_DW_2_IRQ, CONFIG_GPIO_DW_2_IRQ_PRI, gpio_dw_isr, DEVICE_GET(gpio_dw_2), GPIO_DW_2_IRQ_FLAGS); irq_enable(config->irq_num); #elif defined(CONFIG_GPIO_DW_2_IRQ_SHARED) @@ -701,9 +701,9 @@ static void gpio_config_3_irq(struct device *port); static const struct gpio_dw_config gpio_dw_config_3 = { #ifdef CONFIG_GPIO_DW_3_IRQ_DIRECT - .irq_num = GPIO_DW_3_IRQ, + .irq_num = DT_GPIO_DW_3_IRQ, #endif - .bits = GPIO_DW_3_BITS, + .bits = DT_GPIO_DW_3_BITS, .config_func = gpio_config_3_irq, #ifdef CONFIG_GPIO_DW_3_IRQ_SHARED @@ -715,7 +715,7 @@ static const struct gpio_dw_config gpio_dw_config_3 = { }; static struct gpio_dw_runtime gpio_3_runtime = { - .base_addr = GPIO_DW_3_BASE_ADDR, + .base_addr = DT_GPIO_DW_3_BASE_ADDR, #if CONFIG_PCI .pci_dev.class_type = GPIO_DW_PCI_CLASS, .pci_dev.bus = GPIO_DW_3_PCI_BUS, @@ -741,11 +741,11 @@ DEVICE_AND_API_INIT(gpio_dw_3, CONFIG_GPIO_DW_3_NAME, gpio_dw_initialize, static void gpio_config_3_irq(struct device *port) { -#if (GPIO_DW_3_IRQ > 0) +#if (DT_GPIO_DW_3_IRQ > 0) const struct gpio_dw_config *config = port->config->config_info; #ifdef CONFIG_GPIO_DW_3_IRQ_DIRECT - IRQ_CONNECT(GPIO_DW_3_IRQ, CONFIG_GPIO_DW_3_IRQ_PRI, gpio_dw_isr, + IRQ_CONNECT(DT_GPIO_DW_3_IRQ, CONFIG_GPIO_DW_3_IRQ_PRI, gpio_dw_isr, DEVICE_GET(gpio_dw_3), GPIO_DW_3_IRQ_FLAGS); irq_enable(config->irq_num); #elif defined(CONFIG_GPIO_DW_3_IRQ_SHARED) diff --git a/drivers/gpio/gpio_gecko.c b/drivers/gpio/gpio_gecko.c index d859d22b905..20ee732ac67 100644 --- a/drivers/gpio/gpio_gecko.c +++ b/drivers/gpio/gpio_gecko.c @@ -285,7 +285,7 @@ static const struct gpio_gecko_common_config gpio_gecko_common_config = { static struct gpio_gecko_common_data gpio_gecko_common_data; -DEVICE_AND_API_INIT(gpio_gecko_common, CONFIG_GPIO_GECKO_COMMON_NAME, +DEVICE_AND_API_INIT(gpio_gecko_common, DT_GPIO_GECKO_COMMON_NAME, gpio_gecko_common_init, &gpio_gecko_common_data, &gpio_gecko_common_config, POST_KERNEL, CONFIG_GPIO_GECKO_COMMON_INIT_PRIORITY, @@ -294,10 +294,10 @@ DEVICE_AND_API_INIT(gpio_gecko_common, CONFIG_GPIO_GECKO_COMMON_NAME, static int gpio_gecko_common_init(struct device *dev) { gpio_gecko_common_data.count = 0; - IRQ_CONNECT(GPIO_EVEN_IRQn, CONFIG_GPIO_GECKO_COMMON_EVEN_PRI, + IRQ_CONNECT(GPIO_EVEN_IRQn, DT_GPIO_GECKO_COMMON_EVEN_PRI, gpio_gecko_common_isr, DEVICE_GET(gpio_gecko_common), 0); - IRQ_CONNECT(GPIO_ODD_IRQn, CONFIG_GPIO_GECKO_COMMON_ODD_PRI, + IRQ_CONNECT(GPIO_ODD_IRQn, DT_GPIO_GECKO_COMMON_ODD_PRI, gpio_gecko_common_isr, DEVICE_GET(gpio_gecko_common), 0); irq_enable(GPIO_EVEN_IRQn); @@ -318,7 +318,7 @@ static const struct gpio_gecko_config gpio_gecko_porta_config = { static struct gpio_gecko_data gpio_gecko_porta_data; -DEVICE_AND_API_INIT(gpio_gecko_porta, CONFIG_GPIO_GECKO_PORTA_NAME, +DEVICE_AND_API_INIT(gpio_gecko_porta, DT_GPIO_GECKO_PORTA_NAME, gpio_gecko_porta_init, &gpio_gecko_porta_data, &gpio_gecko_porta_config, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, @@ -341,7 +341,7 @@ static const struct gpio_gecko_config gpio_gecko_portb_config = { static struct gpio_gecko_data gpio_gecko_portb_data; -DEVICE_AND_API_INIT(gpio_gecko_portb, CONFIG_GPIO_GECKO_PORTB_NAME, +DEVICE_AND_API_INIT(gpio_gecko_portb, DT_GPIO_GECKO_PORTB_NAME, gpio_gecko_portb_init, &gpio_gecko_portb_data, &gpio_gecko_portb_config, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, @@ -364,7 +364,7 @@ static const struct gpio_gecko_config gpio_gecko_portc_config = { static struct gpio_gecko_data gpio_gecko_portc_data; -DEVICE_AND_API_INIT(gpio_gecko_portc, CONFIG_GPIO_GECKO_PORTC_NAME, +DEVICE_AND_API_INIT(gpio_gecko_portc, DT_GPIO_GECKO_PORTC_NAME, gpio_gecko_portc_init, &gpio_gecko_portc_data, &gpio_gecko_portc_config, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, @@ -387,7 +387,7 @@ static const struct gpio_gecko_config gpio_gecko_portd_config = { static struct gpio_gecko_data gpio_gecko_portd_data; -DEVICE_AND_API_INIT(gpio_gecko_portd, CONFIG_GPIO_GECKO_PORTD_NAME, +DEVICE_AND_API_INIT(gpio_gecko_portd, DT_GPIO_GECKO_PORTD_NAME, gpio_gecko_portd_init, &gpio_gecko_portd_data, &gpio_gecko_portd_config, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, @@ -410,7 +410,7 @@ static const struct gpio_gecko_config gpio_gecko_porte_config = { static struct gpio_gecko_data gpio_gecko_porte_data; -DEVICE_AND_API_INIT(gpio_gecko_porte, CONFIG_GPIO_GECKO_PORTE_NAME, +DEVICE_AND_API_INIT(gpio_gecko_porte, DT_GPIO_GECKO_PORTE_NAME, gpio_gecko_porte_init, &gpio_gecko_porte_data, &gpio_gecko_porte_config, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, @@ -433,7 +433,7 @@ static const struct gpio_gecko_config gpio_gecko_portf_config = { static struct gpio_gecko_data gpio_gecko_portf_data; -DEVICE_AND_API_INIT(gpio_gecko_portf, CONFIG_GPIO_GECKO_PORTF_NAME, +DEVICE_AND_API_INIT(gpio_gecko_portf, DT_GPIO_GECKO_PORTF_NAME, gpio_gecko_portf_init, &gpio_gecko_portf_data, &gpio_gecko_portf_config, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, diff --git a/drivers/gpio/gpio_imx.c b/drivers/gpio/gpio_imx.c index 3a85b6e99ba..c6e698de91e 100644 --- a/drivers/gpio/gpio_imx.c +++ b/drivers/gpio/gpio_imx.c @@ -183,12 +183,12 @@ static const struct gpio_driver_api imx_gpio_driver_api = { static int imx_gpio_1_init(struct device *dev); static const struct imx_gpio_config imx_gpio_1_config = { - .base = (GPIO_Type *)CONFIG_GPIO_IMX_PORT_1_BASE_ADDRESS, + .base = (GPIO_Type *)DT_GPIO_IMX_PORT_1_BASE_ADDRESS, }; static struct imx_gpio_data imx_gpio_1_data; -DEVICE_AND_API_INIT(imx_gpio_1, CONFIG_GPIO_IMX_PORT_1_NAME, +DEVICE_AND_API_INIT(imx_gpio_1, DT_GPIO_IMX_PORT_1_NAME, imx_gpio_1_init, &imx_gpio_1_data, &imx_gpio_1_config, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, @@ -196,17 +196,17 @@ DEVICE_AND_API_INIT(imx_gpio_1, CONFIG_GPIO_IMX_PORT_1_NAME, static int imx_gpio_1_init(struct device *dev) { - IRQ_CONNECT(CONFIG_GPIO_IMX_PORT_1_IRQ_0, - CONFIG_GPIO_IMX_PORT_1_IRQ_0_PRI, + IRQ_CONNECT(DT_GPIO_IMX_PORT_1_IRQ_0, + DT_GPIO_IMX_PORT_1_IRQ_0_PRI, imx_gpio_port_isr, DEVICE_GET(imx_gpio_1), 0); - irq_enable(CONFIG_GPIO_IMX_PORT_1_IRQ_0); + irq_enable(DT_GPIO_IMX_PORT_1_IRQ_0); - IRQ_CONNECT(CONFIG_GPIO_IMX_PORT_1_IRQ_1, - CONFIG_GPIO_IMX_PORT_1_IRQ_1_PRI, + IRQ_CONNECT(DT_GPIO_IMX_PORT_1_IRQ_1, + DT_GPIO_IMX_PORT_1_IRQ_1_PRI, imx_gpio_port_isr, DEVICE_GET(imx_gpio_1), 0); - irq_enable(CONFIG_GPIO_IMX_PORT_1_IRQ_1); + irq_enable(DT_GPIO_IMX_PORT_1_IRQ_1); return 0; } @@ -216,12 +216,12 @@ static int imx_gpio_1_init(struct device *dev) static int imx_gpio_2_init(struct device *dev); static const struct imx_gpio_config imx_gpio_2_config = { - .base = (GPIO_Type *)CONFIG_GPIO_IMX_PORT_2_BASE_ADDRESS, + .base = (GPIO_Type *)DT_GPIO_IMX_PORT_2_BASE_ADDRESS, }; static struct imx_gpio_data imx_gpio_2_data; -DEVICE_AND_API_INIT(imx_gpio_2, CONFIG_GPIO_IMX_PORT_2_NAME, +DEVICE_AND_API_INIT(imx_gpio_2, DT_GPIO_IMX_PORT_2_NAME, imx_gpio_2_init, &imx_gpio_2_data, &imx_gpio_2_config, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, @@ -229,17 +229,17 @@ DEVICE_AND_API_INIT(imx_gpio_2, CONFIG_GPIO_IMX_PORT_2_NAME, static int imx_gpio_2_init(struct device *dev) { - IRQ_CONNECT(CONFIG_GPIO_IMX_PORT_2_IRQ_0, - CONFIG_GPIO_IMX_PORT_2_IRQ_0_PRI, + IRQ_CONNECT(DT_GPIO_IMX_PORT_2_IRQ_0, + DT_GPIO_IMX_PORT_2_IRQ_0_PRI, imx_gpio_port_isr, DEVICE_GET(imx_gpio_2), 0); - irq_enable(CONFIG_GPIO_IMX_PORT_2_IRQ_0); + irq_enable(DT_GPIO_IMX_PORT_2_IRQ_0); - IRQ_CONNECT(CONFIG_GPIO_IMX_PORT_2_IRQ_1, - CONFIG_GPIO_IMX_PORT_2_IRQ_1_PRI, + IRQ_CONNECT(DT_GPIO_IMX_PORT_2_IRQ_1, + DT_GPIO_IMX_PORT_2_IRQ_1_PRI, imx_gpio_port_isr, DEVICE_GET(imx_gpio_2), 0); - irq_enable(CONFIG_GPIO_IMX_PORT_2_IRQ_1); + irq_enable(DT_GPIO_IMX_PORT_2_IRQ_1); return 0; } @@ -249,12 +249,12 @@ static int imx_gpio_2_init(struct device *dev) static int imx_gpio_3_init(struct device *dev); static const struct imx_gpio_config imx_gpio_3_config = { - .base = (GPIO_Type *)CONFIG_GPIO_IMX_PORT_3_BASE_ADDRESS, + .base = (GPIO_Type *)DT_GPIO_IMX_PORT_3_BASE_ADDRESS, }; static struct imx_gpio_data imx_gpio_3_data; -DEVICE_AND_API_INIT(imx_gpio_3, CONFIG_GPIO_IMX_PORT_3_NAME, +DEVICE_AND_API_INIT(imx_gpio_3, DT_GPIO_IMX_PORT_3_NAME, imx_gpio_3_init, &imx_gpio_3_data, &imx_gpio_3_config, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, @@ -262,17 +262,17 @@ DEVICE_AND_API_INIT(imx_gpio_3, CONFIG_GPIO_IMX_PORT_3_NAME, static int imx_gpio_3_init(struct device *dev) { - IRQ_CONNECT(CONFIG_GPIO_IMX_PORT_3_IRQ_0, - CONFIG_GPIO_IMX_PORT_3_IRQ_0_PRI, + IRQ_CONNECT(DT_GPIO_IMX_PORT_3_IRQ_0, + DT_GPIO_IMX_PORT_3_IRQ_0_PRI, imx_gpio_port_isr, DEVICE_GET(imx_gpio_3), 0); - irq_enable(CONFIG_GPIO_IMX_PORT_3_IRQ_0); + irq_enable(DT_GPIO_IMX_PORT_3_IRQ_0); - IRQ_CONNECT(CONFIG_GPIO_IMX_PORT_3_IRQ_1, - CONFIG_GPIO_IMX_PORT_3_IRQ_1_PRI, + IRQ_CONNECT(DT_GPIO_IMX_PORT_3_IRQ_1, + DT_GPIO_IMX_PORT_3_IRQ_1_PRI, imx_gpio_port_isr, DEVICE_GET(imx_gpio_3), 0); - irq_enable(CONFIG_GPIO_IMX_PORT_3_IRQ_1); + irq_enable(DT_GPIO_IMX_PORT_3_IRQ_1); return 0; } @@ -282,12 +282,12 @@ static int imx_gpio_3_init(struct device *dev) static int imx_gpio_4_init(struct device *dev); static const struct imx_gpio_config imx_gpio_4_config = { - .base = (GPIO_Type *)CONFIG_GPIO_IMX_PORT_4_BASE_ADDRESS, + .base = (GPIO_Type *)DT_GPIO_IMX_PORT_4_BASE_ADDRESS, }; static struct imx_gpio_data imx_gpio_4_data; -DEVICE_AND_API_INIT(imx_gpio_4, CONFIG_GPIO_IMX_PORT_4_NAME, +DEVICE_AND_API_INIT(imx_gpio_4, DT_GPIO_IMX_PORT_4_NAME, imx_gpio_4_init, &imx_gpio_4_data, &imx_gpio_4_config, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, @@ -295,17 +295,17 @@ DEVICE_AND_API_INIT(imx_gpio_4, CONFIG_GPIO_IMX_PORT_4_NAME, static int imx_gpio_4_init(struct device *dev) { - IRQ_CONNECT(CONFIG_GPIO_IMX_PORT_4_IRQ_0, - CONFIG_GPIO_IMX_PORT_4_IRQ_0_PRI, + IRQ_CONNECT(DT_GPIO_IMX_PORT_4_IRQ_0, + DT_GPIO_IMX_PORT_4_IRQ_0_PRI, imx_gpio_port_isr, DEVICE_GET(imx_gpio_4), 0); - irq_enable(CONFIG_GPIO_IMX_PORT_4_IRQ_0); + irq_enable(DT_GPIO_IMX_PORT_4_IRQ_0); - IRQ_CONNECT(CONFIG_GPIO_IMX_PORT_4_IRQ_1, - CONFIG_GPIO_IMX_PORT_4_IRQ_1_PRI, + IRQ_CONNECT(DT_GPIO_IMX_PORT_4_IRQ_1, + DT_GPIO_IMX_PORT_4_IRQ_1_PRI, imx_gpio_port_isr, DEVICE_GET(imx_gpio_4), 0); - irq_enable(CONFIG_GPIO_IMX_PORT_4_IRQ_1); + irq_enable(DT_GPIO_IMX_PORT_4_IRQ_1); return 0; } @@ -315,12 +315,12 @@ static int imx_gpio_4_init(struct device *dev) static int imx_gpio_5_init(struct device *dev); static const struct imx_gpio_config imx_gpio_5_config = { - .base = (GPIO_Type *)CONFIG_GPIO_IMX_PORT_5_BASE_ADDRESS, + .base = (GPIO_Type *)DT_GPIO_IMX_PORT_5_BASE_ADDRESS, }; static struct imx_gpio_data imx_gpio_5_data; -DEVICE_AND_API_INIT(imx_gpio_5, CONFIG_GPIO_IMX_PORT_5_NAME, +DEVICE_AND_API_INIT(imx_gpio_5, DT_GPIO_IMX_PORT_5_NAME, imx_gpio_5_init, &imx_gpio_5_data, &imx_gpio_5_config, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, @@ -328,17 +328,17 @@ DEVICE_AND_API_INIT(imx_gpio_5, CONFIG_GPIO_IMX_PORT_5_NAME, static int imx_gpio_5_init(struct device *dev) { - IRQ_CONNECT(CONFIG_GPIO_IMX_PORT_5_IRQ_0, - CONFIG_GPIO_IMX_PORT_5_IRQ_0_PRI, + IRQ_CONNECT(DT_GPIO_IMX_PORT_5_IRQ_0, + DT_GPIO_IMX_PORT_5_IRQ_0_PRI, imx_gpio_port_isr, DEVICE_GET(imx_gpio_5), 0); - irq_enable(CONFIG_GPIO_IMX_PORT_5_IRQ_0); + irq_enable(DT_GPIO_IMX_PORT_5_IRQ_0); - IRQ_CONNECT(CONFIG_GPIO_IMX_PORT_5_IRQ_1, - CONFIG_GPIO_IMX_PORT_5_IRQ_1_PRI, + IRQ_CONNECT(DT_GPIO_IMX_PORT_5_IRQ_1, + DT_GPIO_IMX_PORT_5_IRQ_1_PRI, imx_gpio_port_isr, DEVICE_GET(imx_gpio_5), 0); - irq_enable(CONFIG_GPIO_IMX_PORT_5_IRQ_1); + irq_enable(DT_GPIO_IMX_PORT_5_IRQ_1); return 0; } @@ -348,12 +348,12 @@ static int imx_gpio_5_init(struct device *dev) static int imx_gpio_6_init(struct device *dev); static const struct imx_gpio_config imx_gpio_6_config = { - .base = (GPIO_Type *)CONFIG_GPIO_IMX_PORT_6_BASE_ADDRESS, + .base = (GPIO_Type *)DT_GPIO_IMX_PORT_6_BASE_ADDRESS, }; static struct imx_gpio_data imx_gpio_6_data; -DEVICE_AND_API_INIT(imx_gpio_6, CONFIG_GPIO_IMX_PORT_6_NAME, +DEVICE_AND_API_INIT(imx_gpio_6, DT_GPIO_IMX_PORT_6_NAME, imx_gpio_6_init, &imx_gpio_6_data, &imx_gpio_6_config, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, @@ -361,17 +361,17 @@ DEVICE_AND_API_INIT(imx_gpio_6, CONFIG_GPIO_IMX_PORT_6_NAME, static int imx_gpio_6_init(struct device *dev) { - IRQ_CONNECT(CONFIG_GPIO_IMX_PORT_6_IRQ_0, - CONFIG_GPIO_IMX_PORT_6_IRQ_0_PRI, + IRQ_CONNECT(DT_GPIO_IMX_PORT_6_IRQ_0, + DT_GPIO_IMX_PORT_6_IRQ_0_PRI, imx_gpio_port_isr, DEVICE_GET(imx_gpio_6), 0); - irq_enable(CONFIG_GPIO_IMX_PORT_6_IRQ_0); + irq_enable(DT_GPIO_IMX_PORT_6_IRQ_0); - IRQ_CONNECT(CONFIG_GPIO_IMX_PORT_6_IRQ_1, - CONFIG_GPIO_IMX_PORT_6_IRQ_1_PRI, + IRQ_CONNECT(DT_GPIO_IMX_PORT_6_IRQ_1, + DT_GPIO_IMX_PORT_6_IRQ_1_PRI, imx_gpio_port_isr, DEVICE_GET(imx_gpio_6), 0); - irq_enable(CONFIG_GPIO_IMX_PORT_6_IRQ_1); + irq_enable(DT_GPIO_IMX_PORT_6_IRQ_1); return 0; } @@ -381,12 +381,12 @@ static int imx_gpio_6_init(struct device *dev) static int imx_gpio_7_init(struct device *dev); static const struct imx_gpio_config imx_gpio_7_config = { - .base = (GPIO_Type *)CONFIG_GPIO_IMX_PORT_7_BASE_ADDRESS, + .base = (GPIO_Type *)DT_GPIO_IMX_PORT_7_BASE_ADDRESS, }; static struct imx_gpio_data imx_gpio_7_data; -DEVICE_AND_API_INIT(imx_gpio_7, CONFIG_GPIO_IMX_PORT_7_NAME, +DEVICE_AND_API_INIT(imx_gpio_7, DT_GPIO_IMX_PORT_7_NAME, imx_gpio_7_init, &imx_gpio_7_data, &imx_gpio_7_config, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, @@ -394,17 +394,17 @@ DEVICE_AND_API_INIT(imx_gpio_7, CONFIG_GPIO_IMX_PORT_7_NAME, static int imx_gpio_7_init(struct device *dev) { - IRQ_CONNECT(CONFIG_GPIO_IMX_PORT_7_IRQ_0, - CONFIG_GPIO_IMX_PORT_7_IRQ_0_PRI, + IRQ_CONNECT(DT_GPIO_IMX_PORT_7_IRQ_0, + DT_GPIO_IMX_PORT_7_IRQ_0_PRI, imx_gpio_port_isr, DEVICE_GET(imx_gpio_7), 0); - irq_enable(CONFIG_GPIO_IMX_PORT_7_IRQ_0); + irq_enable(DT_GPIO_IMX_PORT_7_IRQ_0); - IRQ_CONNECT(CONFIG_GPIO_IMX_PORT_7_IRQ_1, - CONFIG_GPIO_IMX_PORT_7_IRQ_1_PRI, + IRQ_CONNECT(DT_GPIO_IMX_PORT_7_IRQ_1, + DT_GPIO_IMX_PORT_7_IRQ_1_PRI, imx_gpio_port_isr, DEVICE_GET(imx_gpio_7), 0); - irq_enable(CONFIG_GPIO_IMX_PORT_7_IRQ_1); + irq_enable(DT_GPIO_IMX_PORT_7_IRQ_1); return 0; } diff --git a/drivers/gpio/gpio_intel_apl.c b/drivers/gpio/gpio_intel_apl.c index 33a637c3574..9dcbd2007f8 100644 --- a/drivers/gpio/gpio_intel_apl.c +++ b/drivers/gpio/gpio_intel_apl.c @@ -430,22 +430,22 @@ static const struct gpio_intel_apl_config gpio_intel_apl_cfg = { .islands = { { /* North island */ - .reg_base = CONFIG_APL_GPIO_BASE_ADDRESS_0, + .reg_base = DT_APL_GPIO_BASE_ADDRESS_0, .num_pins = 78, }, { /* Northwest island */ - .reg_base = CONFIG_APL_GPIO_BASE_ADDRESS_1, + .reg_base = DT_APL_GPIO_BASE_ADDRESS_1, .num_pins = 77, }, { /* West island */ - .reg_base = CONFIG_APL_GPIO_BASE_ADDRESS_2, + .reg_base = DT_APL_GPIO_BASE_ADDRESS_2, .num_pins = 47, }, { /* Southwest island */ - .reg_base = CONFIG_APL_GPIO_BASE_ADDRESS_3, + .reg_base = DT_APL_GPIO_BASE_ADDRESS_3, .num_pins = 43, }, }, @@ -453,7 +453,7 @@ static const struct gpio_intel_apl_config gpio_intel_apl_cfg = { static struct gpio_intel_apl_data gpio_intel_apl_data; -DEVICE_AND_API_INIT(gpio_intel_apl, CONFIG_APL_GPIO_LABEL, +DEVICE_AND_API_INIT(gpio_intel_apl, DT_APL_GPIO_LABEL, gpio_intel_apl_init, &gpio_intel_apl_data, &gpio_intel_apl_cfg, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, @@ -461,9 +461,9 @@ DEVICE_AND_API_INIT(gpio_intel_apl, CONFIG_APL_GPIO_LABEL, static void gpio_intel_apl_irq_config(struct device *dev) { - IRQ_CONNECT(CONFIG_APL_GPIO_IRQ, CONFIG_APL_GPIO_IRQ_PRIORITY, + IRQ_CONNECT(DT_APL_GPIO_IRQ, DT_APL_GPIO_IRQ_PRIORITY, gpio_intel_apl_isr, DEVICE_GET(gpio_intel_apl), - CONFIG_APL_GPIO_IRQ_SENSE); + DT_APL_GPIO_IRQ_SENSE); - irq_enable(CONFIG_APL_GPIO_IRQ); + irq_enable(DT_APL_GPIO_IRQ); } diff --git a/drivers/gpio/gpio_mcux_igpio.c b/drivers/gpio/gpio_mcux_igpio.c index 87dd90d4f61..4bc37b9a0d5 100644 --- a/drivers/gpio/gpio_mcux_igpio.c +++ b/drivers/gpio/gpio_mcux_igpio.c @@ -174,12 +174,12 @@ static const struct gpio_driver_api mcux_igpio_driver_api = { static int mcux_igpio_1_init(struct device *dev); static const struct mcux_igpio_config mcux_igpio_1_config = { - .base = (GPIO_Type *)CONFIG_MCUX_IGPIO_1_BASE_ADDRESS, + .base = (GPIO_Type *)DT_MCUX_IGPIO_1_BASE_ADDRESS, }; static struct mcux_igpio_data mcux_igpio_1_data; -DEVICE_AND_API_INIT(mcux_igpio_1, CONFIG_MCUX_IGPIO_1_NAME, +DEVICE_AND_API_INIT(mcux_igpio_1, DT_MCUX_IGPIO_1_NAME, mcux_igpio_1_init, &mcux_igpio_1_data, &mcux_igpio_1_config, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, @@ -187,15 +187,15 @@ DEVICE_AND_API_INIT(mcux_igpio_1, CONFIG_MCUX_IGPIO_1_NAME, static int mcux_igpio_1_init(struct device *dev) { - IRQ_CONNECT(CONFIG_MCUX_IGPIO_1_IRQ_0, CONFIG_MCUX_IGPIO_1_IRQ_0_PRI, + IRQ_CONNECT(DT_MCUX_IGPIO_1_IRQ_0, DT_MCUX_IGPIO_1_IRQ_0_PRI, mcux_igpio_port_isr, DEVICE_GET(mcux_igpio_1), 0); - irq_enable(CONFIG_MCUX_IGPIO_1_IRQ_0); + irq_enable(DT_MCUX_IGPIO_1_IRQ_0); - IRQ_CONNECT(CONFIG_MCUX_IGPIO_1_IRQ_1, CONFIG_MCUX_IGPIO_1_IRQ_1_PRI, + IRQ_CONNECT(DT_MCUX_IGPIO_1_IRQ_1, DT_MCUX_IGPIO_1_IRQ_1_PRI, mcux_igpio_port_isr, DEVICE_GET(mcux_igpio_1), 0); - irq_enable(CONFIG_MCUX_IGPIO_1_IRQ_1); + irq_enable(DT_MCUX_IGPIO_1_IRQ_1); return 0; } @@ -298,12 +298,12 @@ static int mcux_igpio_4_init(struct device *dev) static int mcux_igpio_5_init(struct device *dev); static const struct mcux_igpio_config mcux_igpio_5_config = { - .base = (GPIO_Type *)CONFIG_MCUX_IGPIO_5_BASE_ADDRESS, + .base = (GPIO_Type *)DT_MCUX_IGPIO_5_BASE_ADDRESS, }; static struct mcux_igpio_data mcux_igpio_5_data; -DEVICE_AND_API_INIT(mcux_igpio_5, CONFIG_MCUX_IGPIO_5_NAME, +DEVICE_AND_API_INIT(mcux_igpio_5, DT_MCUX_IGPIO_5_NAME, mcux_igpio_5_init, &mcux_igpio_5_data, &mcux_igpio_5_config, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, @@ -311,15 +311,15 @@ DEVICE_AND_API_INIT(mcux_igpio_5, CONFIG_MCUX_IGPIO_5_NAME, static int mcux_igpio_5_init(struct device *dev) { - IRQ_CONNECT(CONFIG_MCUX_IGPIO_5_IRQ_0, CONFIG_MCUX_IGPIO_5_IRQ_0_PRI, + IRQ_CONNECT(DT_MCUX_IGPIO_5_IRQ_0, DT_MCUX_IGPIO_5_IRQ_0_PRI, mcux_igpio_port_isr, DEVICE_GET(mcux_igpio_5), 0); - irq_enable(CONFIG_MCUX_IGPIO_5_IRQ_0); + irq_enable(DT_MCUX_IGPIO_5_IRQ_0); - IRQ_CONNECT(CONFIG_MCUX_IGPIO_5_IRQ_1, CONFIG_MCUX_IGPIO_5_IRQ_1_PRI, + IRQ_CONNECT(DT_MCUX_IGPIO_5_IRQ_1, DT_MCUX_IGPIO_5_IRQ_1_PRI, mcux_igpio_port_isr, DEVICE_GET(mcux_igpio_5), 0); - irq_enable(CONFIG_MCUX_IGPIO_5_IRQ_1); + irq_enable(DT_MCUX_IGPIO_5_IRQ_1); return 0; } diff --git a/drivers/gpio/gpio_nrfx.c b/drivers/gpio/gpio_nrfx.c index 13dee9d7e9f..013bf1a9c2e 100644 --- a/drivers/gpio/gpio_nrfx.c +++ b/drivers/gpio/gpio_nrfx.c @@ -419,10 +419,10 @@ static int gpio_nrfx_init(struct device *port) if (!gpio_initialized) { gpio_initialized = true; - IRQ_CONNECT(CONFIG_GPIOTE_IRQ, CONFIG_GPIOTE_IRQ_PRI, + IRQ_CONNECT(DT_GPIOTE_IRQ, DT_GPIOTE_IRQ_PRI, gpiote_event_handler, NULL, 0); - irq_enable(CONFIG_GPIOTE_IRQ); + irq_enable(DT_GPIOTE_IRQ); nrf_gpiote_int_enable(NRF_GPIOTE_INT_PORT_MASK); } @@ -442,7 +442,7 @@ static int gpio_nrfx_init(struct device *port) static struct gpio_nrfx_data gpio_nrfx_p##id##_data; \ \ DEVICE_AND_API_INIT(gpio_nrfx_p##id, \ - CONFIG_GPIO_P##id##_DEV_NAME, \ + DT_GPIO_P##id##_DEV_NAME, \ gpio_nrfx_init, \ &gpio_nrfx_p##id##_data, \ &gpio_nrfx_p##id##_cfg, \ diff --git a/drivers/gpio/gpio_qmsi.c b/drivers/gpio/gpio_qmsi.c index 757a1b00769..e9cd333113b 100644 --- a/drivers/gpio/gpio_qmsi.c +++ b/drivers/gpio/gpio_qmsi.c @@ -117,7 +117,7 @@ static int gpio_qmsi_device_ctrl(struct device *port, u32_t ctrl_command, } #endif -DEVICE_DEFINE(gpio_0, CONFIG_GPIO_QMSI_0_NAME, &gpio_qmsi_init, +DEVICE_DEFINE(gpio_0, DT_GPIO_QMSI_0_NAME, &gpio_qmsi_init, gpio_qmsi_device_ctrl, &gpio_0_runtime, &gpio_0_config, POST_KERNEL, CONFIG_GPIO_QMSI_INIT_PRIORITY, NULL); @@ -154,7 +154,7 @@ static int gpio_aon_device_ctrl(struct device *port, u32_t ctrl_command, } #endif -DEVICE_DEFINE(gpio_aon, CONFIG_GPIO_QMSI_1_NAME, &gpio_qmsi_init, +DEVICE_DEFINE(gpio_aon, DT_GPIO_QMSI_1_NAME, &gpio_qmsi_init, gpio_aon_device_ctrl, &gpio_aon_runtime, &gpio_aon_config, POST_KERNEL, CONFIG_GPIO_QMSI_INIT_PRIORITY, NULL); @@ -378,18 +378,18 @@ static int gpio_qmsi_init(struct device *port) CLK_PERIPH_GPIO_INTERRUPT | CLK_PERIPH_GPIO_DB | CLK_PERIPH_CLK); - IRQ_CONNECT(CONFIG_GPIO_QMSI_0_IRQ, + IRQ_CONNECT(DT_GPIO_QMSI_0_IRQ, CONFIG_GPIO_QMSI_0_IRQ_PRI, qm_gpio_0_isr, 0, - CONFIG_GPIO_QMSI_0_IRQ_FLAGS); - irq_enable(CONFIG_GPIO_QMSI_0_IRQ); + DT_GPIO_QMSI_0_IRQ_FLAGS); + irq_enable(DT_GPIO_QMSI_0_IRQ); QM_IR_UNMASK_INTERRUPTS(QM_INTERRUPT_ROUTER->gpio_0_int_mask); break; #ifdef CONFIG_GPIO_QMSI_1 case QM_AON_GPIO_0: - IRQ_CONNECT(CONFIG_GPIO_QMSI_1_IRQ, - CONFIG_GPIO_QMSI_1_IRQ_PRI, qm_aon_gpio_0_isr, - 0, CONFIG_GPIO_QMSI_1_IRQ_FLAGS); - irq_enable(CONFIG_GPIO_QMSI_1_IRQ); + IRQ_CONNECT(DT_GPIO_QMSI_1_IRQ, + DT_GPIO_QMSI_1_IRQ_PRI, qm_aon_gpio_0_isr, + 0, DT_GPIO_QMSI_1_IRQ_FLAGS); + irq_enable(DT_GPIO_QMSI_1_IRQ); QM_IR_UNMASK_INTERRUPTS( QM_INTERRUPT_ROUTER->aon_gpio_0_int_mask); break; diff --git a/drivers/gpio/gpio_qmsi_ss.c b/drivers/gpio/gpio_qmsi_ss.c index 22ab5f46e10..d912380ac0b 100644 --- a/drivers/gpio/gpio_qmsi_ss.c +++ b/drivers/gpio/gpio_qmsi_ss.c @@ -112,7 +112,7 @@ static const struct ss_gpio_qmsi_config ss_gpio_0_config = { static struct ss_gpio_qmsi_runtime ss_gpio_0_runtime; -DEVICE_DEFINE(ss_gpio_0, CONFIG_GPIO_QMSI_SS_0_NAME, &ss_gpio_qmsi_init, +DEVICE_DEFINE(ss_gpio_0, DT_GPIO_QMSI_SS_0_NAME, &ss_gpio_qmsi_init, ss_gpio_qmsi_device_ctrl, &ss_gpio_0_runtime, &ss_gpio_0_config, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, NULL); @@ -126,7 +126,7 @@ static const struct ss_gpio_qmsi_config ss_gpio_1_config = { static struct ss_gpio_qmsi_runtime gpio_1_runtime; -DEVICE_DEFINE(ss_gpio_1, CONFIG_GPIO_QMSI_SS_1_NAME, &ss_gpio_qmsi_init, +DEVICE_DEFINE(ss_gpio_1, DT_GPIO_QMSI_SS_1_NAME, &ss_gpio_qmsi_init, ss_gpio_qmsi_device_ctrl, &gpio_1_runtime, &ss_gpio_1_config, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, NULL); @@ -374,8 +374,8 @@ static int ss_gpio_qmsi_init(struct device *port) switch (gpio_config->gpio) { #ifdef CONFIG_GPIO_QMSI_SS_0 case QM_SS_GPIO_0: - IRQ_CONNECT(CONFIG_GPIO_QMSI_SS_0_IRQ, - CONFIG_GPIO_QMSI_SS_0_IRQ_PRI, ss_gpio_isr, + IRQ_CONNECT(DT_GPIO_QMSI_SS_0_IRQ, + DT_GPIO_QMSI_SS_0_IRQ_PRI, ss_gpio_isr, DEVICE_GET(ss_gpio_0), 0); irq_enable(IRQ_GPIO0_INTR); @@ -388,8 +388,8 @@ static int ss_gpio_qmsi_init(struct device *port) #endif /* CONFIG_GPIO_QMSI_SS_0 */ #ifdef CONFIG_GPIO_QMSI_SS_1 case QM_SS_GPIO_1: - IRQ_CONNECT(CONFIG_GPIO_QMSI_SS_1_IRQ, - CONFIG_GPIO_QMSI_SS_1_IRQ_PRI, ss_gpio_isr, + IRQ_CONNECT(DT_GPIO_QMSI_SS_1_IRQ, + DT_GPIO_QMSI_SS_1_IRQ_PRI, ss_gpio_isr, DEVICE_GET(ss_gpio_1), 0); irq_enable(IRQ_GPIO1_INTR); diff --git a/drivers/gpio/gpio_sam.c b/drivers/gpio/gpio_sam.c index b85de4cf2ad..0251aad32cf 100644 --- a/drivers/gpio/gpio_sam.c +++ b/drivers/gpio/gpio_sam.c @@ -275,126 +275,126 @@ int gpio_sam_init(struct device *dev) } /* PORT A */ -#ifdef CONFIG_GPIO_SAM_PORTA_BASE_ADDRESS +#ifdef DT_GPIO_SAM_PORTA_BASE_ADDRESS static void port_a_sam_config_func(struct device *dev); static const struct gpio_sam_config port_a_sam_config = { - .regs = (Pio *)CONFIG_GPIO_SAM_PORTA_BASE_ADDRESS, - .periph_id = CONFIG_GPIO_SAM_PORTA_PERIPHERAL_ID, + .regs = (Pio *)DT_GPIO_SAM_PORTA_BASE_ADDRESS, + .periph_id = DT_GPIO_SAM_PORTA_PERIPHERAL_ID, .config_func = port_a_sam_config_func, }; static struct gpio_sam_runtime port_a_sam_runtime; -DEVICE_AND_API_INIT(port_a_sam, CONFIG_GPIO_SAM_PORTA_LABEL, gpio_sam_init, +DEVICE_AND_API_INIT(port_a_sam, DT_GPIO_SAM_PORTA_LABEL, gpio_sam_init, &port_a_sam_runtime, &port_a_sam_config, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &gpio_sam_api); static void port_a_sam_config_func(struct device *dev) { - IRQ_CONNECT(CONFIG_GPIO_SAM_PORTA_IRQ, CONFIG_GPIO_SAM_PORTA_IRQ_PRIO, + IRQ_CONNECT(DT_GPIO_SAM_PORTA_IRQ, DT_GPIO_SAM_PORTA_IRQ_PRIO, gpio_sam_isr, DEVICE_GET(port_a_sam), 0); - irq_enable(CONFIG_GPIO_SAM_PORTA_IRQ); + irq_enable(DT_GPIO_SAM_PORTA_IRQ); } -#endif /* CONFIG_GPIO_SAM_PORTA_BASE_ADDRESS */ +#endif /* DT_GPIO_SAM_PORTA_BASE_ADDRESS */ /* PORT B */ -#ifdef CONFIG_GPIO_SAM_PORTB_BASE_ADDRESS +#ifdef DT_GPIO_SAM_PORTB_BASE_ADDRESS static void port_b_sam_config_func(struct device *dev); static const struct gpio_sam_config port_b_sam_config = { - .regs = (Pio *)CONFIG_GPIO_SAM_PORTB_BASE_ADDRESS, - .periph_id = CONFIG_GPIO_SAM_PORTB_PERIPHERAL_ID, + .regs = (Pio *)DT_GPIO_SAM_PORTB_BASE_ADDRESS, + .periph_id = DT_GPIO_SAM_PORTB_PERIPHERAL_ID, .config_func = port_b_sam_config_func, }; static struct gpio_sam_runtime port_b_sam_runtime; -DEVICE_AND_API_INIT(port_b_sam, CONFIG_GPIO_SAM_PORTB_LABEL, gpio_sam_init, +DEVICE_AND_API_INIT(port_b_sam, DT_GPIO_SAM_PORTB_LABEL, gpio_sam_init, &port_b_sam_runtime, &port_b_sam_config, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &gpio_sam_api); static void port_b_sam_config_func(struct device *dev) { - IRQ_CONNECT(CONFIG_GPIO_SAM_PORTB_IRQ, CONFIG_GPIO_SAM_PORTB_IRQ_PRIO, + IRQ_CONNECT(DT_GPIO_SAM_PORTB_IRQ, DT_GPIO_SAM_PORTB_IRQ_PRIO, gpio_sam_isr, DEVICE_GET(port_b_sam), 0); - irq_enable(CONFIG_GPIO_SAM_PORTB_IRQ); + irq_enable(DT_GPIO_SAM_PORTB_IRQ); } -#endif /* CONFIG_GPIO_SAM_PORTB_BASE_ADDRESS */ +#endif /* DT_GPIO_SAM_PORTB_BASE_ADDRESS */ /* PORT C */ -#ifdef CONFIG_GPIO_SAM_PORTC_BASE_ADDRESS +#ifdef DT_GPIO_SAM_PORTC_BASE_ADDRESS static void port_c_sam_config_func(struct device *dev); static const struct gpio_sam_config port_c_sam_config = { - .regs = (Pio *)CONFIG_GPIO_SAM_PORTC_BASE_ADDRESS, - .periph_id = CONFIG_GPIO_SAM_PORTC_PERIPHERAL_ID, + .regs = (Pio *)DT_GPIO_SAM_PORTC_BASE_ADDRESS, + .periph_id = DT_GPIO_SAM_PORTC_PERIPHERAL_ID, .config_func = port_c_sam_config_func, }; static struct gpio_sam_runtime port_c_sam_runtime; -DEVICE_AND_API_INIT(port_c_sam, CONFIG_GPIO_SAM_PORTC_LABEL, gpio_sam_init, +DEVICE_AND_API_INIT(port_c_sam, DT_GPIO_SAM_PORTC_LABEL, gpio_sam_init, &port_c_sam_runtime, &port_c_sam_config, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &gpio_sam_api); static void port_c_sam_config_func(struct device *dev) { - IRQ_CONNECT(CONFIG_GPIO_SAM_PORTC_IRQ, CONFIG_GPIO_SAM_PORTC_IRQ_PRIO, + IRQ_CONNECT(DT_GPIO_SAM_PORTC_IRQ, DT_GPIO_SAM_PORTC_IRQ_PRIO, gpio_sam_isr, DEVICE_GET(port_c_sam), 0); - irq_enable(CONFIG_GPIO_SAM_PORTC_IRQ); + irq_enable(DT_GPIO_SAM_PORTC_IRQ); } -#endif /* CONFIG_GPIO_SAM_PORTC_BASE_ADDRESS */ +#endif /* DT_GPIO_SAM_PORTC_BASE_ADDRESS */ /* PORT D */ -#ifdef CONFIG_GPIO_SAM_PORTD_BASE_ADDRESS +#ifdef DT_GPIO_SAM_PORTD_BASE_ADDRESS static void port_d_sam_config_func(struct device *dev); static const struct gpio_sam_config port_d_sam_config = { - .regs = (Pio *)CONFIG_GPIO_SAM_PORTD_BASE_ADDRESS, - .periph_id = CONFIG_GPIO_SAM_PORTD_PERIPHERAL_ID, + .regs = (Pio *)DT_GPIO_SAM_PORTD_BASE_ADDRESS, + .periph_id = DT_GPIO_SAM_PORTD_PERIPHERAL_ID, .config_func = port_d_sam_config_func, }; static struct gpio_sam_runtime port_d_sam_runtime; -DEVICE_AND_API_INIT(port_d_sam, CONFIG_GPIO_SAM_PORTD_LABEL, gpio_sam_init, +DEVICE_AND_API_INIT(port_d_sam, DT_GPIO_SAM_PORTD_LABEL, gpio_sam_init, &port_d_sam_runtime, &port_d_sam_config, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &gpio_sam_api); static void port_d_sam_config_func(struct device *dev) { - IRQ_CONNECT(CONFIG_GPIO_SAM_PORTD_IRQ, CONFIG_GPIO_SAM_PORTD_IRQ_PRIO, + IRQ_CONNECT(DT_GPIO_SAM_PORTD_IRQ, DT_GPIO_SAM_PORTD_IRQ_PRIO, gpio_sam_isr, DEVICE_GET(port_d_sam), 0); - irq_enable(CONFIG_GPIO_SAM_PORTD_IRQ); + irq_enable(DT_GPIO_SAM_PORTD_IRQ); } -#endif /* CONFIG_GPIO_SAM_PORTD_BASE_ADDRESS */ +#endif /* DT_GPIO_SAM_PORTD_BASE_ADDRESS */ /* PORT E */ -#ifdef CONFIG_GPIO_SAM_PORTE_BASE_ADDRESS +#ifdef DT_GPIO_SAM_PORTE_BASE_ADDRESS static void port_e_sam_config_func(struct device *dev); static const struct gpio_sam_config port_e_sam_config = { - .regs = (Pio *)CONFIG_GPIO_SAM_PORTE_BASE_ADDRESS, - .periph_id = CONFIG_GPIO_SAM_PORTE_PERIPHERAL_ID, + .regs = (Pio *)DT_GPIO_SAM_PORTE_BASE_ADDRESS, + .periph_id = DT_GPIO_SAM_PORTE_PERIPHERAL_ID, .config_func = port_e_sam_config_func, }; static struct gpio_sam_runtime port_e_sam_runtime; -DEVICE_AND_API_INIT(port_e_sam, CONFIG_GPIO_SAM_PORTE_LABEL, gpio_sam_init, +DEVICE_AND_API_INIT(port_e_sam, DT_GPIO_SAM_PORTE_LABEL, gpio_sam_init, &port_e_sam_runtime, &port_e_sam_config, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &gpio_sam_api); static void port_e_sam_config_func(struct device *dev) { - IRQ_CONNECT(CONFIG_GPIO_SAM_PORTE_IRQ, CONFIG_GPIO_SAM_PORTE_IRQ_PRIO, + IRQ_CONNECT(DT_GPIO_SAM_PORTE_IRQ, DT_GPIO_SAM_PORTE_IRQ_PRIO, gpio_sam_isr, DEVICE_GET(port_e_sam), 0); - irq_enable(CONFIG_GPIO_SAM_PORTE_IRQ); + irq_enable(DT_GPIO_SAM_PORTE_IRQ); } -#endif /* CONFIG_GPIO_SAM_PORTE_BASE_ADDRESS */ +#endif /* DT_GPIO_SAM_PORTE_BASE_ADDRESS */ diff --git a/drivers/gpio/gpio_sam0.c b/drivers/gpio/gpio_sam0.c index e05f63ac061..24b7c0a4d3a 100644 --- a/drivers/gpio/gpio_sam0.c +++ b/drivers/gpio/gpio_sam0.c @@ -122,25 +122,25 @@ static const struct gpio_driver_api gpio_sam0_api = { static int gpio_sam0_init(struct device *dev) { return 0; } /* Port A */ -#ifdef CONFIG_GPIO_SAM0_PORTA_BASE_ADDRESS +#ifdef DT_GPIO_SAM0_PORTA_BASE_ADDRESS static const struct gpio_sam0_config gpio_sam0_config_0 = { - .regs = (PortGroup *)CONFIG_GPIO_SAM0_PORTA_BASE_ADDRESS, + .regs = (PortGroup *)DT_GPIO_SAM0_PORTA_BASE_ADDRESS, }; -DEVICE_AND_API_INIT(gpio_sam0_0, CONFIG_GPIO_SAM0_PORTA_LABEL, gpio_sam0_init, +DEVICE_AND_API_INIT(gpio_sam0_0, DT_GPIO_SAM0_PORTA_LABEL, gpio_sam0_init, NULL, &gpio_sam0_config_0, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &gpio_sam0_api); #endif /* Port B */ -#ifdef CONFIG_GPIO_SAM0_PORTB_BASE_ADDRESS +#ifdef DT_GPIO_SAM0_PORTB_BASE_ADDRESS static const struct gpio_sam0_config gpio_sam0_config_1 = { - .regs = (PortGroup *)CONFIG_GPIO_SAM0_PORTB_BASE_ADDRESS, + .regs = (PortGroup *)DT_GPIO_SAM0_PORTB_BASE_ADDRESS, }; -DEVICE_AND_API_INIT(gpio_sam0_1, CONFIG_GPIO_SAM0_PORTB_LABEL, gpio_sam0_init, +DEVICE_AND_API_INIT(gpio_sam0_1, DT_GPIO_SAM0_PORTB_LABEL, gpio_sam0_init, NULL, &gpio_sam0_config_1, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &gpio_sam0_api); #endif diff --git a/drivers/gpio/gpio_sifive.c b/drivers/gpio/gpio_sifive.c index a4b033e8e4d..21b103f1d58 100644 --- a/drivers/gpio/gpio_sifive.c +++ b/drivers/gpio/gpio_sifive.c @@ -357,8 +357,8 @@ static int gpio_sifive_init(struct device *dev) static void gpio_sifive_cfg_0(void); static const struct gpio_sifive_config gpio_sifive_config0 = { - .gpio_base_addr = CONFIG_SIFIVE_GPIO_0_BASE_ADDR, - .gpio_irq_base = RISCV_MAX_GENERIC_IRQ + CONFIG_SIFIVE_GPIO_0_IRQ_0, + .gpio_base_addr = DT_SIFIVE_GPIO_0_BASE_ADDR, + .gpio_irq_base = RISCV_MAX_GENERIC_IRQ + DT_SIFIVE_GPIO_0_IRQ_0, .gpio_cfg_func = gpio_sifive_cfg_0, }; @@ -372,225 +372,225 @@ DEVICE_AND_API_INIT(gpio_sifive_0, CONFIG_GPIO_SIFIVE_GPIO_NAME, static void gpio_sifive_cfg_0(void) { -#ifdef CONFIG_SIFIVE_GPIO_0_IRQ_0 - IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + CONFIG_SIFIVE_GPIO_0_IRQ_0, +#ifdef DT_SIFIVE_GPIO_0_IRQ_0 + IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + DT_SIFIVE_GPIO_0_IRQ_0, CONFIG_GPIO_SIFIVE_0_PRIORITY, gpio_sifive_irq_handler, DEVICE_GET(gpio_sifive_0), 0); #endif -#ifdef CONFIG_SIFIVE_GPIO_0_IRQ_1 - IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + CONFIG_SIFIVE_GPIO_0_IRQ_1, +#ifdef DT_SIFIVE_GPIO_0_IRQ_1 + IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + DT_SIFIVE_GPIO_0_IRQ_1, CONFIG_GPIO_SIFIVE_1_PRIORITY, gpio_sifive_irq_handler, DEVICE_GET(gpio_sifive_0), 0); #endif -#ifdef CONFIG_SIFIVE_GPIO_0_IRQ_2 - IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + CONFIG_SIFIVE_GPIO_0_IRQ_2, +#ifdef DT_SIFIVE_GPIO_0_IRQ_2 + IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + DT_SIFIVE_GPIO_0_IRQ_2, CONFIG_GPIO_SIFIVE_2_PRIORITY, gpio_sifive_irq_handler, DEVICE_GET(gpio_sifive_0), 0); #endif -#ifdef CONFIG_SIFIVE_GPIO_0_IRQ_3 - IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + CONFIG_SIFIVE_GPIO_0_IRQ_3, +#ifdef DT_SIFIVE_GPIO_0_IRQ_3 + IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + DT_SIFIVE_GPIO_0_IRQ_3, CONFIG_GPIO_SIFIVE_3_PRIORITY, gpio_sifive_irq_handler, DEVICE_GET(gpio_sifive_0), 0); #endif -#ifdef CONFIG_SIFIVE_GPIO_0_IRQ_4 - IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + CONFIG_SIFIVE_GPIO_0_IRQ_4, +#ifdef DT_SIFIVE_GPIO_0_IRQ_4 + IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + DT_SIFIVE_GPIO_0_IRQ_4, CONFIG_GPIO_SIFIVE_4_PRIORITY, gpio_sifive_irq_handler, DEVICE_GET(gpio_sifive_0), 0); #endif -#ifdef CONFIG_SIFIVE_GPIO_0_IRQ_5 - IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + CONFIG_SIFIVE_GPIO_0_IRQ_5, +#ifdef DT_SIFIVE_GPIO_0_IRQ_5 + IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + DT_SIFIVE_GPIO_0_IRQ_5, CONFIG_GPIO_SIFIVE_5_PRIORITY, gpio_sifive_irq_handler, DEVICE_GET(gpio_sifive_0), 0); #endif -#ifdef CONFIG_SIFIVE_GPIO_0_IRQ_6 - IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + CONFIG_SIFIVE_GPIO_0_IRQ_6, +#ifdef DT_SIFIVE_GPIO_0_IRQ_6 + IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + DT_SIFIVE_GPIO_0_IRQ_6, CONFIG_GPIO_SIFIVE_6_PRIORITY, gpio_sifive_irq_handler, DEVICE_GET(gpio_sifive_0), 0); #endif -#ifdef CONFIG_SIFIVE_GPIO_0_IRQ_7 - IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + CONFIG_SIFIVE_GPIO_0_IRQ_7, +#ifdef DT_SIFIVE_GPIO_0_IRQ_7 + IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + DT_SIFIVE_GPIO_0_IRQ_7, CONFIG_GPIO_SIFIVE_7_PRIORITY, gpio_sifive_irq_handler, DEVICE_GET(gpio_sifive_0), 0); #endif -#ifdef CONFIG_SIFIVE_GPIO_0_IRQ_8 - IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + CONFIG_SIFIVE_GPIO_0_IRQ_8, +#ifdef DT_SIFIVE_GPIO_0_IRQ_8 + IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + DT_SIFIVE_GPIO_0_IRQ_8, CONFIG_GPIO_SIFIVE_8_PRIORITY, gpio_sifive_irq_handler, DEVICE_GET(gpio_sifive_0), 0); #endif -#ifdef CONFIG_SIFIVE_GPIO_0_IRQ_9 - IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + CONFIG_SIFIVE_GPIO_0_IRQ_9, +#ifdef DT_SIFIVE_GPIO_0_IRQ_9 + IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + DT_SIFIVE_GPIO_0_IRQ_9, CONFIG_GPIO_SIFIVE_9_PRIORITY, gpio_sifive_irq_handler, DEVICE_GET(gpio_sifive_0), 0); #endif -#ifdef CONFIG_SIFIVE_GPIO_0_IRQ_10 - IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + CONFIG_SIFIVE_GPIO_0_IRQ_10, +#ifdef DT_SIFIVE_GPIO_0_IRQ_10 + IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + DT_SIFIVE_GPIO_0_IRQ_10, CONFIG_GPIO_SIFIVE_10_PRIORITY, gpio_sifive_irq_handler, DEVICE_GET(gpio_sifive_0), 0); #endif -#ifdef CONFIG_SIFIVE_GPIO_0_IRQ_11 - IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + CONFIG_SIFIVE_GPIO_0_IRQ_11, +#ifdef DT_SIFIVE_GPIO_0_IRQ_11 + IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + DT_SIFIVE_GPIO_0_IRQ_11, CONFIG_GPIO_SIFIVE_11_PRIORITY, gpio_sifive_irq_handler, DEVICE_GET(gpio_sifive_0), 0); #endif -#ifdef CONFIG_SIFIVE_GPIO_0_IRQ_12 - IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + CONFIG_SIFIVE_GPIO_0_IRQ_12, +#ifdef DT_SIFIVE_GPIO_0_IRQ_12 + IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + DT_SIFIVE_GPIO_0_IRQ_12, CONFIG_GPIO_SIFIVE_12_PRIORITY, gpio_sifive_irq_handler, DEVICE_GET(gpio_sifive_0), 0); #endif -#ifdef CONFIG_SIFIVE_GPIO_0_IRQ_13 - IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + CONFIG_SIFIVE_GPIO_0_IRQ_13, +#ifdef DT_SIFIVE_GPIO_0_IRQ_13 + IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + DT_SIFIVE_GPIO_0_IRQ_13, CONFIG_GPIO_SIFIVE_13_PRIORITY, gpio_sifive_irq_handler, DEVICE_GET(gpio_sifive_0), 0); #endif -#ifdef CONFIG_SIFIVE_GPIO_0_IRQ_14 - IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + CONFIG_SIFIVE_GPIO_0_IRQ_14, +#ifdef DT_SIFIVE_GPIO_0_IRQ_14 + IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + DT_SIFIVE_GPIO_0_IRQ_14, CONFIG_GPIO_SIFIVE_14_PRIORITY, gpio_sifive_irq_handler, DEVICE_GET(gpio_sifive_0), 0); #endif -#ifdef CONFIG_SIFIVE_GPIO_0_IRQ_15 - IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + CONFIG_SIFIVE_GPIO_0_IRQ_15, +#ifdef DT_SIFIVE_GPIO_0_IRQ_15 + IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + DT_SIFIVE_GPIO_0_IRQ_15, CONFIG_GPIO_SIFIVE_15_PRIORITY, gpio_sifive_irq_handler, DEVICE_GET(gpio_sifive_0), 0); #endif -#ifdef CONFIG_SIFIVE_GPIO_0_IRQ_16 - IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + CONFIG_SIFIVE_GPIO_0_IRQ_16, +#ifdef DT_SIFIVE_GPIO_0_IRQ_16 + IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + DT_SIFIVE_GPIO_0_IRQ_16, CONFIG_GPIO_SIFIVE_16_PRIORITY, gpio_sifive_irq_handler, DEVICE_GET(gpio_sifive_0), 0); #endif -#ifdef CONFIG_SIFIVE_GPIO_0_IRQ_17 - IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + CONFIG_SIFIVE_GPIO_0_IRQ_17, +#ifdef DT_SIFIVE_GPIO_0_IRQ_17 + IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + DT_SIFIVE_GPIO_0_IRQ_17, CONFIG_GPIO_SIFIVE_17_PRIORITY, gpio_sifive_irq_handler, DEVICE_GET(gpio_sifive_0), 0); #endif -#ifdef CONFIG_SIFIVE_GPIO_0_IRQ_18 - IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + CONFIG_SIFIVE_GPIO_0_IRQ_18, +#ifdef DT_SIFIVE_GPIO_0_IRQ_18 + IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + DT_SIFIVE_GPIO_0_IRQ_18, CONFIG_GPIO_SIFIVE_18_PRIORITY, gpio_sifive_irq_handler, DEVICE_GET(gpio_sifive_0), 0); #endif -#ifdef CONFIG_SIFIVE_GPIO_0_IRQ_19 - IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + CONFIG_SIFIVE_GPIO_0_IRQ_19, +#ifdef DT_SIFIVE_GPIO_0_IRQ_19 + IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + DT_SIFIVE_GPIO_0_IRQ_19, CONFIG_GPIO_SIFIVE_19_PRIORITY, gpio_sifive_irq_handler, DEVICE_GET(gpio_sifive_0), 0); #endif -#ifdef CONFIG_SIFIVE_GPIO_0_IRQ_20 - IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + CONFIG_SIFIVE_GPIO_0_IRQ_20, +#ifdef DT_SIFIVE_GPIO_0_IRQ_20 + IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + DT_SIFIVE_GPIO_0_IRQ_20, CONFIG_GPIO_SIFIVE_20_PRIORITY, gpio_sifive_irq_handler, DEVICE_GET(gpio_sifive_0), 0); #endif -#ifdef CONFIG_SIFIVE_GPIO_0_IRQ_21 - IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + CONFIG_SIFIVE_GPIO_0_IRQ_21, +#ifdef DT_SIFIVE_GPIO_0_IRQ_21 + IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + DT_SIFIVE_GPIO_0_IRQ_21, CONFIG_GPIO_SIFIVE_21_PRIORITY, gpio_sifive_irq_handler, DEVICE_GET(gpio_sifive_0), 0); #endif -#ifdef CONFIG_SIFIVE_GPIO_0_IRQ_22 - IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + CONFIG_SIFIVE_GPIO_0_IRQ_22, +#ifdef DT_SIFIVE_GPIO_0_IRQ_22 + IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + DT_SIFIVE_GPIO_0_IRQ_22, CONFIG_GPIO_SIFIVE_22_PRIORITY, gpio_sifive_irq_handler, DEVICE_GET(gpio_sifive_0), 0); #endif -#ifdef CONFIG_SIFIVE_GPIO_0_IRQ_23 - IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + CONFIG_SIFIVE_GPIO_0_IRQ_23, +#ifdef DT_SIFIVE_GPIO_0_IRQ_23 + IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + DT_SIFIVE_GPIO_0_IRQ_23, CONFIG_GPIO_SIFIVE_23_PRIORITY, gpio_sifive_irq_handler, DEVICE_GET(gpio_sifive_0), 0); #endif -#ifdef CONFIG_SIFIVE_GPIO_0_IRQ_24 - IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + CONFIG_SIFIVE_GPIO_0_IRQ_24, +#ifdef DT_SIFIVE_GPIO_0_IRQ_24 + IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + DT_SIFIVE_GPIO_0_IRQ_24, CONFIG_GPIO_SIFIVE_24_PRIORITY, gpio_sifive_irq_handler, DEVICE_GET(gpio_sifive_0), 0); #endif -#ifdef CONFIG_SIFIVE_GPIO_0_IRQ_25 - IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + CONFIG_SIFIVE_GPIO_0_IRQ_25, +#ifdef DT_SIFIVE_GPIO_0_IRQ_25 + IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + DT_SIFIVE_GPIO_0_IRQ_25, CONFIG_GPIO_SIFIVE_25_PRIORITY, gpio_sifive_irq_handler, DEVICE_GET(gpio_sifive_0), 0); #endif -#ifdef CONFIG_SIFIVE_GPIO_0_IRQ_26 - IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + CONFIG_SIFIVE_GPIO_0_IRQ_26, +#ifdef DT_SIFIVE_GPIO_0_IRQ_26 + IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + DT_SIFIVE_GPIO_0_IRQ_26, CONFIG_GPIO_SIFIVE_26_PRIORITY, gpio_sifive_irq_handler, DEVICE_GET(gpio_sifive_0), 0); #endif -#ifdef CONFIG_SIFIVE_GPIO_0_IRQ_27 - IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + CONFIG_SIFIVE_GPIO_0_IRQ_27, +#ifdef DT_SIFIVE_GPIO_0_IRQ_27 + IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + DT_SIFIVE_GPIO_0_IRQ_27, CONFIG_GPIO_SIFIVE_27_PRIORITY, gpio_sifive_irq_handler, DEVICE_GET(gpio_sifive_0), 0); #endif -#ifdef CONFIG_SIFIVE_GPIO_0_IRQ_28 - IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + CONFIG_SIFIVE_GPIO_0_IRQ_28, +#ifdef DT_SIFIVE_GPIO_0_IRQ_28 + IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + DT_SIFIVE_GPIO_0_IRQ_28, CONFIG_GPIO_SIFIVE_28_PRIORITY, gpio_sifive_irq_handler, DEVICE_GET(gpio_sifive_0), 0); #endif -#ifdef CONFIG_SIFIVE_GPIO_0_IRQ_29 - IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + CONFIG_SIFIVE_GPIO_0_IRQ_29, +#ifdef DT_SIFIVE_GPIO_0_IRQ_29 + IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + DT_SIFIVE_GPIO_0_IRQ_29, CONFIG_GPIO_SIFIVE_29_PRIORITY, gpio_sifive_irq_handler, DEVICE_GET(gpio_sifive_0), 0); #endif -#ifdef CONFIG_SIFIVE_GPIO_0_IRQ_30 - IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + CONFIG_SIFIVE_GPIO_0_IRQ_30, +#ifdef DT_SIFIVE_GPIO_0_IRQ_30 + IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + DT_SIFIVE_GPIO_0_IRQ_30, CONFIG_GPIO_SIFIVE_30_PRIORITY, gpio_sifive_irq_handler, DEVICE_GET(gpio_sifive_0), 0); #endif -#ifdef CONFIG_SIFIVE_GPIO_0_IRQ_31 - IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + CONFIG_SIFIVE_GPIO_0_IRQ_31, +#ifdef DT_SIFIVE_GPIO_0_IRQ_31 + IRQ_CONNECT(RISCV_MAX_GENERIC_IRQ + DT_SIFIVE_GPIO_0_IRQ_31, CONFIG_GPIO_SIFIVE_31_PRIORITY, gpio_sifive_irq_handler, DEVICE_GET(gpio_sifive_0), diff --git a/drivers/gpio/gpio_stm32.c b/drivers/gpio/gpio_stm32.c index f0186dae25e..2d72de12e1d 100644 --- a/drivers/gpio/gpio_stm32.c +++ b/drivers/gpio/gpio_stm32.c @@ -212,12 +212,12 @@ DEVICE_AND_API_INIT(gpio_stm32_## __suffix, \ #define GPIO_DEVICE_INIT_STM32(__suffix, __SUFFIX) \ - GPIO_DEVICE_INIT(CONFIG_GPIO_STM32_GPIO##__SUFFIX##_LABEL, \ + GPIO_DEVICE_INIT(DT_GPIO_STM32_GPIO##__SUFFIX##_LABEL, \ __suffix, \ - CONFIG_GPIO_STM32_GPIO##__SUFFIX##_BASE_ADDRESS, \ + DT_GPIO_STM32_GPIO##__SUFFIX##_BASE_ADDRESS, \ STM32_PORT##__SUFFIX, \ - CONFIG_GPIO_STM32_GPIO##__SUFFIX##_CLOCK_BITS, \ - CONFIG_GPIO_STM32_GPIO##__SUFFIX##_CLOCK_BUS) + DT_GPIO_STM32_GPIO##__SUFFIX##_CLOCK_BITS, \ + DT_GPIO_STM32_GPIO##__SUFFIX##_CLOCK_BUS) #ifdef CONFIG_GPIO_STM32_PORTA GPIO_DEVICE_INIT_STM32(a, A); diff --git a/drivers/i2c/i2c_cc32xx.c b/drivers/i2c/i2c_cc32xx.c index 11f3f07ca73..38656a8c34a 100644 --- a/drivers/i2c/i2c_cc32xx.c +++ b/drivers/i2c/i2c_cc32xx.c @@ -372,22 +372,22 @@ static const struct i2c_driver_api i2c_cc32xx_driver_api = { static const struct i2c_cc32xx_config i2c_cc32xx_config = { - .base = CONFIG_I2C_0_BASE_ADDRESS, - .bitrate = CONFIG_I2C_0_BITRATE, - .irq_no = CONFIG_I2C_0_IRQ, + .base = DT_I2C_0_BASE_ADDRESS, + .bitrate = DT_I2C_0_BITRATE, + .irq_no = DT_I2C_0_IRQ, }; static struct i2c_cc32xx_data i2c_cc32xx_data; -DEVICE_AND_API_INIT(i2c_cc32xx, CONFIG_I2C_0_LABEL, &i2c_cc32xx_init, +DEVICE_AND_API_INIT(i2c_cc32xx, DT_I2C_0_LABEL, &i2c_cc32xx_init, &i2c_cc32xx_data, &i2c_cc32xx_config, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &i2c_cc32xx_driver_api); static void configure_i2c_irq(const struct i2c_cc32xx_config *config) { - IRQ_CONNECT(CONFIG_I2C_0_IRQ, - CONFIG_I2C_0_IRQ_PRIORITY, + IRQ_CONNECT(DT_I2C_0_IRQ, + DT_I2C_0_IRQ_PRIORITY, i2c_cc32xx_isr, DEVICE_GET(i2c_cc32xx), 0); irq_enable(config->irq_no); diff --git a/drivers/i2c/i2c_dw.c b/drivers/i2c/i2c_dw.c index a00cf97758a..e44ec9426dc 100644 --- a/drivers/i2c/i2c_dw.c +++ b/drivers/i2c/i2c_dw.c @@ -706,11 +706,11 @@ static const struct i2c_dw_rom_config i2c_config_dw_0 = { #ifdef CONFIG_GPIO_DW_0_IRQ_SHARED .shared_irq_dev_name = CONFIG_I2C_DW_0_IRQ_SHARED_NAME, #endif - .bitrate = CONFIG_I2C_0_BITRATE, + .bitrate = DT_I2C_0_BITRATE, }; static struct i2c_dw_dev_config i2c_0_runtime = { - .base_address = CONFIG_I2C_0_BASE_ADDR, + .base_address = DT_I2C_0_BASE_ADDR, #if CONFIG_PCI .pci_dev.class_type = I2C_DW_0_PCI_CLASS, .pci_dev.bus = I2C_DW_0_PCI_BUS, @@ -730,9 +730,9 @@ DEVICE_AND_API_INIT(i2c_0, CONFIG_I2C_0_NAME, &i2c_dw_initialize, static void i2c_config_0(struct device *port) { #if defined(CONFIG_I2C_DW_0_IRQ_DIRECT) - IRQ_CONNECT(CONFIG_I2C_0_IRQ, CONFIG_I2C_0_IRQ_PRI, - i2c_dw_isr, DEVICE_GET(i2c_0), CONFIG_I2C_0_IRQ_FLAGS); - irq_enable(CONFIG_I2C_0_IRQ); + IRQ_CONNECT(DT_I2C_0_IRQ, CONFIG_I2C_0_IRQ_PRI, + i2c_dw_isr, DEVICE_GET(i2c_0), DT_I2C_0_IRQ_FLAGS); + irq_enable(DT_I2C_0_IRQ); #elif defined(CONFIG_I2C_DW_0_IRQ_SHARED) const struct i2c_dw_rom_config * const config = port->config->config_info; @@ -754,11 +754,11 @@ static void i2c_config_1(struct device *port); static const struct i2c_dw_rom_config i2c_config_dw_1 = { .config_func = i2c_config_1, - .bitrate = CONFIG_I2C_1_BITRATE, + .bitrate = DT_I2C_1_BITRATE, }; static struct i2c_dw_dev_config i2c_1_runtime = { - .base_address = CONFIG_I2C_1_BASE_ADDR, + .base_address = DT_I2C_1_BASE_ADDR, #if CONFIG_PCI .pci_dev.class_type = I2C_DW_1_PCI_CLASS, .pci_dev.bus = I2C_DW_1_PCI_BUS, @@ -777,9 +777,9 @@ DEVICE_AND_API_INIT(i2c_1, CONFIG_I2C_1_NAME, &i2c_dw_initialize, static void i2c_config_1(struct device *port) { - IRQ_CONNECT(CONFIG_I2C_1_IRQ, CONFIG_I2C_1_IRQ_PRI, - i2c_dw_isr, DEVICE_GET(i2c_1), CONFIG_I2C_1_IRQ_FLAGS); - irq_enable(CONFIG_I2C_1_IRQ); + IRQ_CONNECT(DT_I2C_1_IRQ, CONFIG_I2C_1_IRQ_PRI, + i2c_dw_isr, DEVICE_GET(i2c_1), DT_I2C_1_IRQ_FLAGS); + irq_enable(DT_I2C_1_IRQ); } #endif /* CONFIG_I2C_1 */ @@ -792,11 +792,11 @@ static void i2c_config_2(struct device *port); static const struct i2c_dw_rom_config i2c_config_dw_2 = { .config_func = i2c_config_2, - .bitrate = CONFIG_I2C_2_BITRATE, + .bitrate = DT_I2C_2_BITRATE, }; static struct i2c_dw_dev_config I2C_2_runtime = { - .base_address = CONFIG_I2C_2_BASE_ADDR, + .base_address = DT_I2C_2_BASE_ADDR, #if CONFIG_PCI .pci_dev.class_type = I2C_DW_2_PCI_CLASS, .pci_dev.bus = I2C_DW_2_PCI_BUS, @@ -815,9 +815,9 @@ DEVICE_AND_API_INIT(I2C_2, CONFIG_I2C_2_NAME, &i2c_dw_initialize, static void i2c_config_2(struct device *port) { - IRQ_CONNECT(CONFIG_I2C_2_IRQ, CONFIG_I2C_2_IRQ_PRI, - i2c_dw_isr, DEVICE_GET(I2C_2), CONFIG_I2C_2_IRQ_FLAGS); - irq_enable(CONFIG_I2C_2_IRQ); + IRQ_CONNECT(DT_I2C_2_IRQ, CONFIG_I2C_2_IRQ_PRI, + i2c_dw_isr, DEVICE_GET(I2C_2), DT_I2C_2_IRQ_FLAGS); + irq_enable(DT_I2C_2_IRQ); } #endif /* CONFIG_I2C_2 */ @@ -830,11 +830,11 @@ static void i2c_config_3(struct device *port); static const struct i2c_dw_rom_config i2c_config_dw_3 = { .config_func = i2c_config_3, - .bitrate = CONFIG_I2C_3_BITRATE, + .bitrate = DT_I2C_3_BITRATE, }; static struct i2c_dw_dev_config I2C_3_runtime = { - .base_address = CONFIG_I2C_3_BASE_ADDR, + .base_address = DT_I2C_3_BASE_ADDR, #if CONFIG_PCI .pci_dev.class_type = I2C_DW_3_PCI_CLASS, .pci_dev.bus = I2C_DW_3_PCI_BUS, @@ -853,9 +853,9 @@ DEVICE_AND_API_INIT(I2C_3, CONFIG_I2C_3_NAME, &i2c_dw_initialize, static void i2c_config_3(struct device *port) { - IRQ_CONNECT(CONFIG_I2C_3_IRQ, CONFIG_I2C_3_IRQ_PRI, - i2c_dw_isr, DEVICE_GET(I2C_3), CONFIG_I2C_3_IRQ_FLAGS); - irq_enable(CONFIG_I2C_3_IRQ); + IRQ_CONNECT(DT_I2C_3_IRQ, CONFIG_I2C_3_IRQ_PRI, + i2c_dw_isr, DEVICE_GET(I2C_3), DT_I2C_3_IRQ_FLAGS); + irq_enable(DT_I2C_3_IRQ); } #endif /* CONFIG_I2C_3 */ @@ -868,11 +868,11 @@ static void i2c_config_4(struct device *port); static const struct i2c_dw_rom_config i2c_config_dw_4 = { .config_func = i2c_config_4, - .bitrate = CONFIG_I2C_4_BITRATE, + .bitrate = DT_I2C_4_BITRATE, }; static struct i2c_dw_dev_config I2C_4_runtime = { - .base_address = CONFIG_I2C_4_BASE_ADDR, + .base_address = DT_I2C_4_BASE_ADDR, #if CONFIG_PCI .pci_dev.class_type = I2C_DW_4_PCI_CLASS, .pci_dev.bus = I2C_DW_4_PCI_BUS, @@ -891,9 +891,9 @@ DEVICE_AND_API_INIT(I2C_4, CONFIG_I2C_4_NAME, &i2c_dw_initialize, static void i2c_config_4(struct device *port) { - IRQ_CONNECT(CONFIG_I2C_4_IRQ, CONFIG_I2C_4_IRQ_PRI, - i2c_dw_isr, DEVICE_GET(I2C_4), CONFIG_I2C_4_IRQ_FLAGS); - irq_enable(CONFIG_I2C_4_IRQ); + IRQ_CONNECT(DT_I2C_4_IRQ, CONFIG_I2C_4_IRQ_PRI, + i2c_dw_isr, DEVICE_GET(I2C_4), DT_I2C_4_IRQ_FLAGS); + irq_enable(DT_I2C_4_IRQ); } #endif /* CONFIG_I2C_4 */ @@ -906,11 +906,11 @@ static void i2c_config_5(struct device *port); static const struct i2c_dw_rom_config i2c_config_dw_5 = { .config_func = i2c_config_5, - .bitrate = CONFIG_I2C_5_BITRATE, + .bitrate = DT_I2C_5_BITRATE, }; static struct i2c_dw_dev_config I2C_5_runtime = { - .base_address = CONFIG_I2C_5_BASE_ADDR, + .base_address = DT_I2C_5_BASE_ADDR, #if CONFIG_PCI .pci_dev.class_type = I2C_DW_5_PCI_CLASS, .pci_dev.bus = I2C_DW_5_PCI_BUS, @@ -929,9 +929,9 @@ DEVICE_AND_API_INIT(I2C_5, CONFIG_I2C_5_NAME, &i2c_dw_initialize, static void i2c_config_5(struct device *port) { - IRQ_CONNECT(CONFIG_I2C_5_IRQ, CONFIG_I2C_5_IRQ_PRI, - i2c_dw_isr, DEVICE_GET(I2C_5), CONFIG_I2C_5_IRQ_FLAGS); - irq_enable(CONFIG_I2C_5_IRQ); + IRQ_CONNECT(DT_I2C_5_IRQ, CONFIG_I2C_5_IRQ_PRI, + i2c_dw_isr, DEVICE_GET(I2C_5), DT_I2C_5_IRQ_FLAGS); + irq_enable(DT_I2C_5_IRQ); } #endif /* CONFIG_I2C_5 */ @@ -944,11 +944,11 @@ static void i2c_config_6(struct device *port); static const struct i2c_dw_rom_config i2c_config_dw_6 = { .config_func = i2c_config_6, - .bitrate = CONFIG_I2C_6_BITRATE, + .bitrate = DT_I2C_6_BITRATE, }; static struct i2c_dw_dev_config I2C_6_runtime = { - .base_address = CONFIG_I2C_6_BASE_ADDR, + .base_address = DT_I2C_6_BASE_ADDR, #if CONFIG_PCI .pci_dev.class_type = I2C_DW_6_PCI_CLASS, .pci_dev.bus = I2C_DW_6_PCI_BUS, @@ -967,9 +967,9 @@ DEVICE_AND_API_INIT(I2C_6, CONFIG_I2C_6_NAME, &i2c_dw_initialize, static void i2c_config_6(struct device *port) { - IRQ_CONNECT(CONFIG_I2C_6_IRQ, CONFIG_I2C_6_IRQ_PRI, - i2c_dw_isr, DEVICE_GET(I2C_6), CONFIG_I2C_6_IRQ_FLAGS); - irq_enable(CONFIG_I2C_6_IRQ); + IRQ_CONNECT(DT_I2C_6_IRQ, CONFIG_I2C_6_IRQ_PRI, + i2c_dw_isr, DEVICE_GET(I2C_6), DT_I2C_6_IRQ_FLAGS); + irq_enable(DT_I2C_6_IRQ); } #endif /* CONFIG_I2C_6 */ @@ -982,11 +982,11 @@ static void i2c_config_7(struct device *port); static const struct i2c_dw_rom_config i2c_config_dw_7 = { .config_func = i2c_config_7, - .bitrate = CONFIG_I2C_7_BITRATE, + .bitrate = DT_I2C_7_BITRATE, }; static struct i2c_dw_dev_config I2C_7_runtime = { - .base_address = CONFIG_I2C_7_BASE_ADDR, + .base_address = DT_I2C_7_BASE_ADDR, #if CONFIG_PCI .pci_dev.class_type = I2C_DW_7_PCI_CLASS, .pci_dev.bus = I2C_DW_7_PCI_BUS, @@ -1005,9 +1005,9 @@ DEVICE_AND_API_INIT(I2C_7, CONFIG_I2C_7_NAME, &i2c_dw_initialize, static void i2c_config_7(struct device *port) { - IRQ_CONNECT(CONFIG_I2C_7_IRQ, CONFIG_I2C_7_IRQ_PRI, - i2c_dw_isr, DEVICE_GET(I2C_7), CONFIG_I2C_7_IRQ_FLAGS); - irq_enable(CONFIG_I2C_7_IRQ); + IRQ_CONNECT(DT_I2C_7_IRQ, CONFIG_I2C_7_IRQ_PRI, + i2c_dw_isr, DEVICE_GET(I2C_7), DT_I2C_7_IRQ_FLAGS); + irq_enable(DT_I2C_7_IRQ); } #endif /* CONFIG_I2C_7 */ diff --git a/drivers/i2c/i2c_gecko.c b/drivers/i2c/i2c_gecko.c index 87852f5799f..3f182bb87e1 100644 --- a/drivers/i2c/i2c_gecko.c +++ b/drivers/i2c/i2c_gecko.c @@ -180,18 +180,18 @@ static const struct i2c_driver_api i2c_gecko_driver_api = { #ifdef CONFIG_I2C_0 static struct i2c_gecko_config i2c_gecko_config_0 = { - .base = (I2C_TypeDef *)CONFIG_I2C_GECKO_0_BASE_ADDRESS, + .base = (I2C_TypeDef *)DT_I2C_GECKO_0_BASE_ADDRESS, .clock = cmuClock_I2C0, .i2cInit = I2C_INIT_DEFAULT, .pin_sda = PIN_I2C0_SDA, .pin_scl = PIN_I2C0_SCL, - .loc = CONFIG_I2C_GECKO_0_LOCATION, - .bitrate = CONFIG_I2C_GECKO_0_CLOCK_FREQUENCY, + .loc = DT_I2C_GECKO_0_LOCATION, + .bitrate = DT_I2C_GECKO_0_CLOCK_FREQUENCY, }; static struct i2c_gecko_data i2c_gecko_data_0; -DEVICE_AND_API_INIT(i2c_gecko_0, CONFIG_I2C_GECKO_0_LABEL, &i2c_gecko_init, +DEVICE_AND_API_INIT(i2c_gecko_0, DT_I2C_GECKO_0_LABEL, &i2c_gecko_init, &i2c_gecko_data_0, &i2c_gecko_config_0, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &i2c_gecko_driver_api); @@ -199,18 +199,18 @@ DEVICE_AND_API_INIT(i2c_gecko_0, CONFIG_I2C_GECKO_0_LABEL, &i2c_gecko_init, #ifdef CONFIG_I2C_1 static struct i2c_gecko_config i2c_gecko_config_1 = { - .base = (I2C_TypeDef *)CONFIG_I2C_GECKO_1_BASE_ADDRESS, + .base = (I2C_TypeDef *)DT_I2C_GECKO_1_BASE_ADDRESS, .clock = cmuClock_I2C1, .i2cInit = I2C_INIT_DEFAULT, .pin_sda = PIN_I2C1_SDA, .pin_scl = PIN_I2C1_SCL, - .loc = CONFIG_I2C_GECKO_1_LOCATION, - .bitrate = CONFIG_I2C_GECKO_1_CLOCK_FREQUENCY, + .loc = DT_I2C_GECKO_1_LOCATION, + .bitrate = DT_I2C_GECKO_1_CLOCK_FREQUENCY, }; static struct i2c_gecko_data i2c_gecko_data_1; -DEVICE_AND_API_INIT(i2c_gecko_1, CONFIG_I2C_GECKO_1_LABEL, &i2c_gecko_init, +DEVICE_AND_API_INIT(i2c_gecko_1, DT_I2C_GECKO_1_LABEL, &i2c_gecko_init, &i2c_gecko_data_1, &i2c_gecko_config_1, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &i2c_gecko_driver_api); diff --git a/drivers/i2c/i2c_ll_stm32.c b/drivers/i2c/i2c_ll_stm32.c index 9757d1e0d5c..821260de6b0 100644 --- a/drivers/i2c/i2c_ll_stm32.c +++ b/drivers/i2c/i2c_ll_stm32.c @@ -181,19 +181,19 @@ static int i2c_stm32_init(struct device *dev) switch ((u32_t)cfg->i2c) { #ifdef CONFIG_I2C_1 - case CONFIG_I2C_1_BASE_ADDRESS: + case DT_I2C_1_BASE_ADDRESS: LL_RCC_SetI2CClockSource(LL_RCC_I2C1_CLKSOURCE_SYSCLK); break; #endif /* CONFIG_I2C_1 */ #if defined(CONFIG_SOC_SERIES_STM32F3X) && defined(CONFIG_I2C_2) - case CONFIG_I2C_2_BASE_ADDRESS: + case DT_I2C_2_BASE_ADDRESS: LL_RCC_SetI2CClockSource(LL_RCC_I2C2_CLKSOURCE_SYSCLK); break; #endif /* CONFIG_SOC_SERIES_STM32F3X && CONFIG_I2C_2 */ #ifdef CONFIG_I2C_3 - case CONFIG_I2C_3_BASE_ADDRESS: + case DT_I2C_3_BASE_ADDRESS: LL_RCC_SetI2CClockSource(LL_RCC_I2C3_CLKSOURCE_SYSCLK); break; #endif /* CONFIG_I2C_3 */ @@ -218,15 +218,15 @@ static void i2c_stm32_irq_config_func_1(struct device *port); #endif static const struct i2c_stm32_config i2c_stm32_cfg_1 = { - .i2c = (I2C_TypeDef *)CONFIG_I2C_1_BASE_ADDRESS, + .i2c = (I2C_TypeDef *)DT_I2C_1_BASE_ADDRESS, .pclken = { - .enr = CONFIG_I2C_1_CLOCK_BITS, - .bus = CONFIG_I2C_1_CLOCK_BUS, + .enr = DT_I2C_1_CLOCK_BITS, + .bus = DT_I2C_1_CLOCK_BUS, }, #ifdef CONFIG_I2C_STM32_INTERRUPT .irq_config_func = i2c_stm32_irq_config_func_1, #endif - .bitrate = CONFIG_I2C_1_BITRATE, + .bitrate = DT_I2C_1_BITRATE, }; static struct i2c_stm32_data i2c_stm32_dev_data_1; @@ -240,17 +240,17 @@ DEVICE_AND_API_INIT(i2c_stm32_1, CONFIG_I2C_1_NAME, &i2c_stm32_init, static void i2c_stm32_irq_config_func_1(struct device *dev) { #ifdef CONFIG_I2C_STM32_COMBINED_INTERRUPT - IRQ_CONNECT(CONFIG_I2C_1_COMBINED_IRQ, CONFIG_I2C_1_COMBINED_IRQ_PRI, + IRQ_CONNECT(DT_I2C_1_COMBINED_IRQ, DT_I2C_1_COMBINED_IRQ_PRI, stm32_i2c_combined_isr, DEVICE_GET(i2c_stm32_1), 0); - irq_enable(CONFIG_I2C_1_COMBINED_IRQ); + irq_enable(DT_I2C_1_COMBINED_IRQ); #else - IRQ_CONNECT(CONFIG_I2C_1_EVENT_IRQ, CONFIG_I2C_1_EVENT_IRQ_PRI, + IRQ_CONNECT(DT_I2C_1_EVENT_IRQ, DT_I2C_1_EVENT_IRQ_PRI, stm32_i2c_event_isr, DEVICE_GET(i2c_stm32_1), 0); - irq_enable(CONFIG_I2C_1_EVENT_IRQ); + irq_enable(DT_I2C_1_EVENT_IRQ); - IRQ_CONNECT(CONFIG_I2C_1_ERROR_IRQ, CONFIG_I2C_1_ERROR_IRQ_PRI, + IRQ_CONNECT(DT_I2C_1_ERROR_IRQ, DT_I2C_1_ERROR_IRQ_PRI, stm32_i2c_error_isr, DEVICE_GET(i2c_stm32_1), 0); - irq_enable(CONFIG_I2C_1_ERROR_IRQ); + irq_enable(DT_I2C_1_ERROR_IRQ); #endif } #endif @@ -264,15 +264,15 @@ static void i2c_stm32_irq_config_func_2(struct device *port); #endif static const struct i2c_stm32_config i2c_stm32_cfg_2 = { - .i2c = (I2C_TypeDef *)CONFIG_I2C_2_BASE_ADDRESS, + .i2c = (I2C_TypeDef *)DT_I2C_2_BASE_ADDRESS, .pclken = { - .enr = CONFIG_I2C_2_CLOCK_BITS, - .bus = CONFIG_I2C_2_CLOCK_BUS, + .enr = DT_I2C_2_CLOCK_BITS, + .bus = DT_I2C_2_CLOCK_BUS, }, #ifdef CONFIG_I2C_STM32_INTERRUPT .irq_config_func = i2c_stm32_irq_config_func_2, #endif - .bitrate = CONFIG_I2C_2_BITRATE, + .bitrate = DT_I2C_2_BITRATE, }; static struct i2c_stm32_data i2c_stm32_dev_data_2; @@ -286,17 +286,17 @@ DEVICE_AND_API_INIT(i2c_stm32_2, CONFIG_I2C_2_NAME, &i2c_stm32_init, static void i2c_stm32_irq_config_func_2(struct device *dev) { #ifdef CONFIG_I2C_STM32_COMBINED_INTERRUPT - IRQ_CONNECT(CONFIG_I2C_2_COMBINED_IRQ, CONFIG_I2C_2_COMBINED_IRQ_PRI, + IRQ_CONNECT(DT_I2C_2_COMBINED_IRQ, DT_I2C_2_COMBINED_IRQ_PRI, stm32_i2c_combined_isr, DEVICE_GET(i2c_stm32_2), 0); - irq_enable(CONFIG_I2C_2_COMBINED_IRQ); + irq_enable(DT_I2C_2_COMBINED_IRQ); #else - IRQ_CONNECT(CONFIG_I2C_2_EVENT_IRQ, CONFIG_I2C_2_EVENT_IRQ_PRI, + IRQ_CONNECT(DT_I2C_2_EVENT_IRQ, DT_I2C_2_EVENT_IRQ_PRI, stm32_i2c_event_isr, DEVICE_GET(i2c_stm32_2), 0); - irq_enable(CONFIG_I2C_2_EVENT_IRQ); + irq_enable(DT_I2C_2_EVENT_IRQ); - IRQ_CONNECT(CONFIG_I2C_2_ERROR_IRQ, CONFIG_I2C_2_ERROR_IRQ_PRI, + IRQ_CONNECT(DT_I2C_2_ERROR_IRQ, DT_I2C_2_ERROR_IRQ_PRI, stm32_i2c_error_isr, DEVICE_GET(i2c_stm32_2), 0); - irq_enable(CONFIG_I2C_2_ERROR_IRQ); + irq_enable(DT_I2C_2_ERROR_IRQ); #endif } #endif @@ -314,15 +314,15 @@ static void i2c_stm32_irq_config_func_3(struct device *port); #endif static const struct i2c_stm32_config i2c_stm32_cfg_3 = { - .i2c = (I2C_TypeDef *)CONFIG_I2C_3_BASE_ADDRESS, + .i2c = (I2C_TypeDef *)DT_I2C_3_BASE_ADDRESS, .pclken = { - .enr = CONFIG_I2C_3_CLOCK_BITS, - .bus = CONFIG_I2C_3_CLOCK_BUS, + .enr = DT_I2C_3_CLOCK_BITS, + .bus = DT_I2C_3_CLOCK_BUS, }, #ifdef CONFIG_I2C_STM32_INTERRUPT .irq_config_func = i2c_stm32_irq_config_func_3, #endif - .bitrate = CONFIG_I2C_3_BITRATE, + .bitrate = DT_I2C_3_BITRATE, }; static struct i2c_stm32_data i2c_stm32_dev_data_3; @@ -335,13 +335,13 @@ DEVICE_AND_API_INIT(i2c_stm32_3, CONFIG_I2C_3_NAME, &i2c_stm32_init, #ifdef CONFIG_I2C_STM32_INTERRUPT static void i2c_stm32_irq_config_func_3(struct device *dev) { - IRQ_CONNECT(CONFIG_I2C_3_EVENT_IRQ, CONFIG_I2C_3_EVENT_IRQ_PRI, + IRQ_CONNECT(DT_I2C_3_EVENT_IRQ, DT_I2C_3_EVENT_IRQ_PRI, stm32_i2c_event_isr, DEVICE_GET(i2c_stm32_3), 0); - irq_enable(CONFIG_I2C_3_EVENT_IRQ); + irq_enable(DT_I2C_3_EVENT_IRQ); - IRQ_CONNECT(CONFIG_I2C_3_ERROR_IRQ, CONFIG_I2C_3_ERROR_IRQ_PRI, + IRQ_CONNECT(DT_I2C_3_ERROR_IRQ, DT_I2C_3_ERROR_IRQ_PRI, stm32_i2c_error_isr, DEVICE_GET(i2c_stm32_3), 0); - irq_enable(CONFIG_I2C_3_ERROR_IRQ); + irq_enable(DT_I2C_3_ERROR_IRQ); } #endif @@ -358,15 +358,15 @@ static void i2c_stm32_irq_config_func_4(struct device *port); #endif static const struct i2c_stm32_config i2c_stm32_cfg_4 = { - .i2c = (I2C_TypeDef *)CONFIG_I2C_4_BASE_ADDRESS, + .i2c = (I2C_TypeDef *)DT_I2C_4_BASE_ADDRESS, .pclken = { - .enr = CONFIG_I2C_4_CLOCK_BITS, - .bus = CONFIG_I2C_4_CLOCK_BUS, + .enr = DT_I2C_4_CLOCK_BITS, + .bus = DT_I2C_4_CLOCK_BUS, }, #ifdef CONFIG_I2C_STM32_INTERRUPT .irq_config_func = i2c_stm32_irq_config_func_4, #endif - .bitrate = CONFIG_I2C_4_BITRATE, + .bitrate = DT_I2C_4_BITRATE, }; static struct i2c_stm32_data i2c_stm32_dev_data_4; @@ -379,13 +379,13 @@ DEVICE_AND_API_INIT(i2c_stm32_4, CONFIG_I2C_4_NAME, &i2c_stm32_init, #ifdef CONFIG_I2C_STM32_INTERRUPT static void i2c_stm32_irq_config_func_4(struct device *dev) { - IRQ_CONNECT(CONFIG_I2C_4_EVENT_IRQ, CONFIG_I2C_4_EVENT_IRQ_PRI, + IRQ_CONNECT(DT_I2C_4_EVENT_IRQ, DT_I2C_4_EVENT_IRQ_PRI, stm32_i2c_event_isr, DEVICE_GET(i2c_stm32_4), 0); - irq_enable(CONFIG_I2C_4_EVENT_IRQ); + irq_enable(DT_I2C_4_EVENT_IRQ); - IRQ_CONNECT(CONFIG_I2C_4_ERROR_IRQ, CONFIG_I2C_4_ERROR_IRQ_PRI, + IRQ_CONNECT(DT_I2C_4_ERROR_IRQ, DT_I2C_4_ERROR_IRQ_PRI, stm32_i2c_error_isr, DEVICE_GET(i2c_stm32_4), 0); - irq_enable(CONFIG_I2C_4_ERROR_IRQ); + irq_enable(DT_I2C_4_ERROR_IRQ); } #endif diff --git a/drivers/i2c/i2c_mcux.c b/drivers/i2c/i2c_mcux.c index efc6c04e166..766ebc33d4f 100644 --- a/drivers/i2c/i2c_mcux.c +++ b/drivers/i2c/i2c_mcux.c @@ -195,10 +195,10 @@ static const struct i2c_driver_api i2c_mcux_driver_api = { static void i2c_mcux_config_func_0(struct device *dev); static const struct i2c_mcux_config i2c_mcux_config_0 = { - .base = (I2C_Type *)CONFIG_I2C_MCUX_0_BASE_ADDRESS, + .base = (I2C_Type *)DT_I2C_MCUX_0_BASE_ADDRESS, .clock_source = I2C0_CLK_SRC, .irq_config_func = i2c_mcux_config_func_0, - .bitrate = CONFIG_I2C_MCUX_0_BITRATE, + .bitrate = DT_I2C_MCUX_0_BITRATE, }; static struct i2c_mcux_data i2c_mcux_data_0; @@ -212,10 +212,10 @@ static void i2c_mcux_config_func_0(struct device *dev) { ARG_UNUSED(dev); - IRQ_CONNECT(CONFIG_I2C_MCUX_0_IRQ, CONFIG_I2C_MCUX_0_IRQ_PRI, + IRQ_CONNECT(DT_I2C_MCUX_0_IRQ, DT_I2C_MCUX_0_IRQ_PRI, i2c_mcux_isr, DEVICE_GET(i2c_mcux_0), 0); - irq_enable(CONFIG_I2C_MCUX_0_IRQ); + irq_enable(DT_I2C_MCUX_0_IRQ); } #endif /* CONFIG_I2C_0 */ @@ -223,10 +223,10 @@ static void i2c_mcux_config_func_0(struct device *dev) static void i2c_mcux_config_func_1(struct device *dev); static const struct i2c_mcux_config i2c_mcux_config_1 = { - .base = (I2C_Type *)CONFIG_I2C_MCUX_1_BASE_ADDRESS, + .base = (I2C_Type *)DT_I2C_MCUX_1_BASE_ADDRESS, .clock_source = I2C1_CLK_SRC, .irq_config_func = i2c_mcux_config_func_1, - .bitrate = CONFIG_I2C_MCUX_1_BITRATE, + .bitrate = DT_I2C_MCUX_1_BITRATE, }; static struct i2c_mcux_data i2c_mcux_data_1; @@ -238,9 +238,9 @@ DEVICE_AND_API_INIT(i2c_mcux_1, CONFIG_I2C_1_NAME, &i2c_mcux_init, static void i2c_mcux_config_func_1(struct device *dev) { - IRQ_CONNECT(CONFIG_I2C_MCUX_1_IRQ, CONFIG_I2C_MCUX_1_IRQ_PRI, + IRQ_CONNECT(DT_I2C_MCUX_1_IRQ, DT_I2C_MCUX_1_IRQ_PRI, i2c_mcux_isr, DEVICE_GET(i2c_mcux_1), 0); - irq_enable(CONFIG_I2C_MCUX_1_IRQ); + irq_enable(DT_I2C_MCUX_1_IRQ); } #endif /* CONFIG_I2C_1 */ diff --git a/drivers/i2c/i2c_nrfx_twi.c b/drivers/i2c/i2c_nrfx_twi.c index d144330311f..9059e2672ca 100644 --- a/drivers/i2c/i2c_nrfx_twi.c +++ b/drivers/i2c/i2c_nrfx_twi.c @@ -139,12 +139,12 @@ static int init_twi(struct device *dev, const nrfx_twi_config_t *config) #define I2C_NRFX_TWI_DEVICE(idx) \ static int twi_##idx##_init(struct device *dev) \ { \ - IRQ_CONNECT(CONFIG_I2C_##idx##_IRQ, \ + IRQ_CONNECT(DT_I2C_##idx##_IRQ, \ CONFIG_I2C_##idx##_IRQ_PRI, \ nrfx_isr, nrfx_twi_##idx##_irq_handler, 0); \ const nrfx_twi_config_t config = { \ - .scl = CONFIG_I2C_##idx##_SCL_PIN, \ - .sda = CONFIG_I2C_##idx##_SDA_PIN, \ + .scl = DT_I2C_##idx##_SCL_PIN, \ + .sda = DT_I2C_##idx##_SDA_PIN, \ .frequency = NRF_TWI_FREQ_100K, \ }; \ return init_twi(dev, &config); \ diff --git a/drivers/i2c/i2c_nrfx_twim.c b/drivers/i2c/i2c_nrfx_twim.c index 32f65766ecc..66be5f2d5f2 100644 --- a/drivers/i2c/i2c_nrfx_twim.c +++ b/drivers/i2c/i2c_nrfx_twim.c @@ -140,12 +140,12 @@ static int init_twim(struct device *dev, const nrfx_twim_config_t *config) #define I2C_NRFX_TWIM_DEVICE(idx) \ static int twim_##idx##_init(struct device *dev) \ { \ - IRQ_CONNECT(CONFIG_I2C_##idx##_IRQ, \ + IRQ_CONNECT(DT_I2C_##idx##_IRQ, \ CONFIG_I2C_##idx##_IRQ_PRI, \ nrfx_isr, nrfx_twim_##idx##_irq_handler, 0);\ const nrfx_twim_config_t config = { \ - .scl = CONFIG_I2C_##idx##_SCL_PIN, \ - .sda = CONFIG_I2C_##idx##_SDA_PIN, \ + .scl = DT_I2C_##idx##_SCL_PIN, \ + .sda = DT_I2C_##idx##_SDA_PIN, \ .frequency = NRF_TWIM_FREQ_100K, \ }; \ return init_twim(dev, &config); \ diff --git a/drivers/i2c/i2c_qmsi.c b/drivers/i2c/i2c_qmsi.c index e4f9858b704..792b0ddf7b7 100644 --- a/drivers/i2c/i2c_qmsi.c +++ b/drivers/i2c/i2c_qmsi.c @@ -117,7 +117,7 @@ static struct i2c_qmsi_driver_data driver_data_0; static const struct i2c_qmsi_config_info config_info_0 = { .instance = QM_I2C_0, - .bitrate = CONFIG_I2C_0_BITRATE, + .bitrate = DT_I2C_0_BITRATE, .clock_gate = CLK_PERIPH_I2C_M0_REGISTER | CLK_PERIPH_CLK, }; @@ -133,7 +133,7 @@ static struct i2c_qmsi_driver_data driver_data_1; static const struct i2c_qmsi_config_info config_info_1 = { .instance = QM_I2C_1, - .bitrate = CONFIG_I2C_1_BITRATE, + .bitrate = DT_I2C_1_BITRATE, .clock_gate = CLK_PERIPH_I2C_M1_REGISTER | CLK_PERIPH_CLK, }; @@ -273,20 +273,20 @@ static int i2c_qmsi_init(struct device *dev) /* Register interrupt handler, unmask IRQ and route it * to Lakemont core. */ - IRQ_CONNECT(CONFIG_I2C_0_IRQ, + IRQ_CONNECT(DT_I2C_0_IRQ, CONFIG_I2C_0_IRQ_PRI, qm_i2c_0_irq_isr, NULL, - CONFIG_I2C_0_IRQ_FLAGS); - irq_enable(CONFIG_I2C_0_IRQ); + DT_I2C_0_IRQ_FLAGS); + irq_enable(DT_I2C_0_IRQ); QM_IR_UNMASK_INTERRUPTS( QM_INTERRUPT_ROUTER->i2c_master_0_int_mask); break; #ifdef CONFIG_I2C_1 case QM_I2C_1: - IRQ_CONNECT(CONFIG_I2C_1_IRQ, + IRQ_CONNECT(DT_I2C_1_IRQ, CONFIG_I2C_1_IRQ_PRI, qm_i2c_1_irq_isr, NULL, - CONFIG_I2C_1_IRQ_FLAGS); - irq_enable(CONFIG_I2C_1_IRQ); + DT_I2C_1_IRQ_FLAGS); + irq_enable(DT_I2C_1_IRQ); QM_IR_UNMASK_INTERRUPTS( QM_INTERRUPT_ROUTER->i2c_master_1_int_mask); break; diff --git a/drivers/i2c/i2c_qmsi_ss.c b/drivers/i2c/i2c_qmsi_ss.c index 73ad1465486..1dfa10131c8 100644 --- a/drivers/i2c/i2c_qmsi_ss.c +++ b/drivers/i2c/i2c_qmsi_ss.c @@ -117,11 +117,11 @@ static void i2c_qmsi_ss_config_irq_0(void); static const struct i2c_qmsi_ss_config_info config_info_0 = { .instance = QM_SS_I2C_0, - .bitrate = CONFIG_I2C_SS_0_BITRATE, + .bitrate = DT_I2C_SS_0_BITRATE, .irq_cfg = i2c_qmsi_ss_config_irq_0, }; -DEVICE_DEFINE(i2c_ss_0, CONFIG_I2C_SS_0_NAME, i2c_qmsi_ss_init, +DEVICE_DEFINE(i2c_ss_0, DT_I2C_SS_0_NAME, i2c_qmsi_ss_init, ss_i2c_device_ctrl, &driver_data_0, &config_info_0, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, NULL); @@ -150,19 +150,19 @@ static void i2c_qmsi_ss_config_irq_0(void) sys_write32(mask, SCSS_REGISTER_BASE + I2C_SS_0_STOP_MASK); /* Connect the IRQs to ISR */ - IRQ_CONNECT(CONFIG_I2C_SS_0_ERR_IRQ, CONFIG_I2C_SS_0_ERR_IRQ_PRI, + IRQ_CONNECT(DT_I2C_SS_0_ERR_IRQ, DT_I2C_SS_0_ERR_IRQ_PRI, qm_ss_i2c_0_error_isr, DEVICE_GET(i2c_ss_0), 0); - IRQ_CONNECT(CONFIG_I2C_SS_0_RX_IRQ, CONFIG_I2C_SS_0_RX_IRQ_PRI, + IRQ_CONNECT(DT_I2C_SS_0_RX_IRQ, DT_I2C_SS_0_RX_IRQ_PRI, qm_ss_i2c_0_rx_avail_isr, DEVICE_GET(i2c_ss_0), 0); - IRQ_CONNECT(CONFIG_I2C_SS_0_TX_IRQ, CONFIG_I2C_SS_0_TX_IRQ_PRI, + IRQ_CONNECT(DT_I2C_SS_0_TX_IRQ, DT_I2C_SS_0_TX_IRQ_PRI, qm_ss_i2c_0_tx_req_isr, DEVICE_GET(i2c_ss_0), 0); - IRQ_CONNECT(CONFIG_I2C_SS_0_STOP_IRQ, CONFIG_I2C_SS_0_STOP_IRQ_PRI, + IRQ_CONNECT(DT_I2C_SS_0_STOP_IRQ, DT_I2C_SS_0_STOP_IRQ_PRI, qm_ss_i2c_0_stop_det_isr, DEVICE_GET(i2c_ss_0), 0); - irq_enable(CONFIG_I2C_SS_0_ERR_IRQ); - irq_enable(CONFIG_I2C_SS_0_RX_IRQ); - irq_enable(CONFIG_I2C_SS_0_TX_IRQ); - irq_enable(CONFIG_I2C_SS_0_STOP_IRQ); + irq_enable(DT_I2C_SS_0_ERR_IRQ); + irq_enable(DT_I2C_SS_0_RX_IRQ); + irq_enable(DT_I2C_SS_0_TX_IRQ); + irq_enable(DT_I2C_SS_0_STOP_IRQ); } #endif /* CONFIG_I2C_SS_0 */ @@ -174,11 +174,11 @@ static void i2c_qmsi_ss_config_irq_1(void); static const struct i2c_qmsi_ss_config_info config_info_1 = { .instance = QM_SS_I2C_1, - .bitrate = CONFIG_I2C_SS_1_BITRATE, + .bitrate = DT_I2C_SS_1_BITRATE, .irq_cfg = i2c_qmsi_ss_config_irq_1, }; -DEVICE_DEFINE(i2c_ss_1, CONFIG_I2C_SS_1_NAME, i2c_qmsi_ss_init, +DEVICE_DEFINE(i2c_ss_1, DT_I2C_SS_1_NAME, i2c_qmsi_ss_init, ss_i2c_device_ctrl, &driver_data_1, &config_info_1, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, NULL); @@ -207,19 +207,19 @@ static void i2c_qmsi_ss_config_irq_1(void) sys_write32(mask, SCSS_REGISTER_BASE + I2C_SS_1_STOP_MASK); /* Connect the IRQs to ISR */ - IRQ_CONNECT(CONFIG_I2C_SS_1_ERR_IRQ, CONFIG_I2C_SS_1_ERR_IRQ_PRI, + IRQ_CONNECT(DT_I2C_SS_1_ERR_IRQ, DT_I2C_SS_1_ERR_IRQ_PRI, qm_ss_i2c_1_error_isr, DEVICE_GET(i2c_ss_1), 0); - IRQ_CONNECT(CONFIG_I2C_SS_1_RX_IRQ, CONFIG_I2C_SS_1_RX_IRQ_PRI, + IRQ_CONNECT(DT_I2C_SS_1_RX_IRQ, DT_I2C_SS_1_RX_IRQ_PRI, qm_ss_i2c_1_rx_avail_isr, DEVICE_GET(i2c_ss_1), 0); - IRQ_CONNECT(CONFIG_I2C_SS_1_TX_IRQ, CONFIG_I2C_SS_1_TX_IRQ_PRI, + IRQ_CONNECT(DT_I2C_SS_1_TX_IRQ, DT_I2C_SS_1_TX_IRQ_PRI, qm_ss_i2c_1_tx_req_isr, DEVICE_GET(i2c_ss_1), 0); - IRQ_CONNECT(CONFIG_I2C_SS_1_STOP_IRQ, CONFIG_I2C_SS_1_STOP_IRQ_PRI, + IRQ_CONNECT(DT_I2C_SS_1_STOP_IRQ, DT_I2C_SS_1_STOP_IRQ_PRI, qm_ss_i2c_1_stop_det_isr, DEVICE_GET(i2c_ss_1), 0); - irq_enable(CONFIG_I2C_SS_1_ERR_IRQ); - irq_enable(CONFIG_I2C_SS_1_RX_IRQ); - irq_enable(CONFIG_I2C_SS_1_TX_IRQ); - irq_enable(CONFIG_I2C_SS_1_STOP_IRQ); + irq_enable(DT_I2C_SS_1_ERR_IRQ); + irq_enable(DT_I2C_SS_1_RX_IRQ); + irq_enable(DT_I2C_SS_1_TX_IRQ); + irq_enable(DT_I2C_SS_1_STOP_IRQ); } #endif /* CONFIG_I2C_SS_1 */ diff --git a/drivers/i2c/i2c_sam_twi.c b/drivers/i2c/i2c_sam_twi.c index 34ccf11ead9..7b5ca58f8f6 100644 --- a/drivers/i2c/i2c_sam_twi.c +++ b/drivers/i2c/i2c_sam_twi.c @@ -343,20 +343,20 @@ static struct device DEVICE_NAME_GET(i2c0_sam); static void i2c0_sam_irq_config(void) { - IRQ_CONNECT(CONFIG_I2C_0_IRQ, CONFIG_I2C_0_IRQ_PRI, i2c_sam_twi_isr, + IRQ_CONNECT(DT_I2C_0_IRQ, CONFIG_I2C_0_IRQ_PRI, i2c_sam_twi_isr, DEVICE_GET(i2c0_sam), 0); } static const struct soc_gpio_pin pins_twi0[] = PINS_TWI0; static const struct i2c_sam_twi_dev_cfg i2c0_sam_config = { - .regs = (Twi *)CONFIG_I2C_0_BASE_ADDRESS, + .regs = (Twi *)DT_I2C_0_BASE_ADDRESS, .irq_config = i2c0_sam_irq_config, - .periph_id = CONFIG_I2C_0_PERIPHERAL_ID, - .irq_id = CONFIG_I2C_0_IRQ, + .periph_id = DT_I2C_0_PERIPHERAL_ID, + .irq_id = DT_I2C_0_IRQ, .pin_list = pins_twi0, .pin_list_size = ARRAY_SIZE(pins_twi0), - .bitrate = CONFIG_I2C_0_BITRATE, + .bitrate = DT_I2C_0_BITRATE, }; static struct i2c_sam_twi_dev_data i2c0_sam_data; @@ -373,20 +373,20 @@ static struct device DEVICE_NAME_GET(i2c1_sam); static void i2c1_sam_irq_config(void) { - IRQ_CONNECT(CONFIG_I2C_1_IRQ, CONFIG_I2C_1_IRQ_PRI, i2c_sam_twi_isr, + IRQ_CONNECT(DT_I2C_1_IRQ, CONFIG_I2C_1_IRQ_PRI, i2c_sam_twi_isr, DEVICE_GET(i2c1_sam), 0); } static const struct soc_gpio_pin pins_twi1[] = PINS_TWI1; static const struct i2c_sam_twi_dev_cfg i2c1_sam_config = { - .regs = (Twi *)CONFIG_I2C_1_BASE_ADDRESS, + .regs = (Twi *)DT_I2C_1_BASE_ADDRESS, .irq_config = i2c1_sam_irq_config, - .periph_id = CONFIG_I2C_1_PERIPHERAL_ID, - .irq_id = CONFIG_I2C_1_IRQ, + .periph_id = DT_I2C_1_PERIPHERAL_ID, + .irq_id = DT_I2C_1_IRQ, .pin_list = pins_twi1, .pin_list_size = ARRAY_SIZE(pins_twi1), - .bitrate = CONFIG_I2C_1_BITRATE, + .bitrate = DT_I2C_1_BITRATE, }; static struct i2c_sam_twi_dev_data i2c1_sam_data; diff --git a/drivers/i2c/i2c_sam_twihs.c b/drivers/i2c/i2c_sam_twihs.c index 9b20ecf7166..478503cd8e2 100644 --- a/drivers/i2c/i2c_sam_twihs.c +++ b/drivers/i2c/i2c_sam_twihs.c @@ -330,20 +330,20 @@ static struct device DEVICE_NAME_GET(i2c0_sam); static void i2c0_sam_irq_config(void) { - IRQ_CONNECT(CONFIG_I2C_0_IRQ, CONFIG_I2C_0_IRQ_PRI, i2c_sam_twihs_isr, + IRQ_CONNECT(DT_I2C_0_IRQ, CONFIG_I2C_0_IRQ_PRI, i2c_sam_twihs_isr, DEVICE_GET(i2c0_sam), 0); } static const struct soc_gpio_pin pins_twihs0[] = PINS_TWIHS0; static const struct i2c_sam_twihs_dev_cfg i2c0_sam_config = { - .regs = (Twihs *)CONFIG_I2C_0_BASE_ADDRESS, + .regs = (Twihs *)DT_I2C_0_BASE_ADDRESS, .irq_config = i2c0_sam_irq_config, - .periph_id = CONFIG_I2C_0_PERIPHERAL_ID, - .irq_id = CONFIG_I2C_0_IRQ, + .periph_id = DT_I2C_0_PERIPHERAL_ID, + .irq_id = DT_I2C_0_IRQ, .pin_list = pins_twihs0, .pin_list_size = ARRAY_SIZE(pins_twihs0), - .bitrate = CONFIG_I2C_0_BITRATE, + .bitrate = DT_I2C_0_BITRATE, }; static struct i2c_sam_twihs_dev_data i2c0_sam_data; @@ -360,20 +360,20 @@ static struct device DEVICE_NAME_GET(i2c1_sam); static void i2c1_sam_irq_config(void) { - IRQ_CONNECT(CONFIG_I2C_1_IRQ, CONFIG_I2C_1_IRQ_PRI, i2c_sam_twihs_isr, + IRQ_CONNECT(DT_I2C_1_IRQ, CONFIG_I2C_1_IRQ_PRI, i2c_sam_twihs_isr, DEVICE_GET(i2c1_sam), 0); } static const struct soc_gpio_pin pins_twihs1[] = PINS_TWIHS1; static const struct i2c_sam_twihs_dev_cfg i2c1_sam_config = { - .regs = (Twihs *)CONFIG_I2C_1_BASE_ADDRESS, + .regs = (Twihs *)DT_I2C_1_BASE_ADDRESS, .irq_config = i2c1_sam_irq_config, - .periph_id = CONFIG_I2C_1_PERIPHERAL_ID, - .irq_id = CONFIG_I2C_1_IRQ, + .periph_id = DT_I2C_1_PERIPHERAL_ID, + .irq_id = DT_I2C_1_IRQ, .pin_list = pins_twihs1, .pin_list_size = ARRAY_SIZE(pins_twihs1), - .bitrate = CONFIG_I2C_1_BITRATE, + .bitrate = DT_I2C_1_BITRATE, }; static struct i2c_sam_twihs_dev_data i2c1_sam_data; @@ -390,20 +390,20 @@ static struct device DEVICE_NAME_GET(i2c2_sam); static void i2c2_sam_irq_config(void) { - IRQ_CONNECT(CONFIG_I2C_2_IRQ, CONFIG_I2C_2_IRQ_PRI, i2c_sam_twihs_isr, + IRQ_CONNECT(DT_I2C_2_IRQ, CONFIG_I2C_2_IRQ_PRI, i2c_sam_twihs_isr, DEVICE_GET(i2c2_sam), 0); } static const struct soc_gpio_pin pins_twihs2[] = PINS_TWIHS2; static const struct i2c_sam_twihs_dev_cfg i2c2_sam_config = { - .regs = (Twihs *)CONFIG_I2C_2_BASE_ADDRESS, + .regs = (Twihs *)DT_I2C_2_BASE_ADDRESS, .irq_config = i2c2_sam_irq_config, - .periph_id = CONFIG_I2C_2_PERIPHERAL_ID, - .irq_id = CONFIG_I2C_2_IRQ, + .periph_id = DT_I2C_2_PERIPHERAL_ID, + .irq_id = DT_I2C_2_IRQ, .pin_list = pins_twihs2, .pin_list_size = ARRAY_SIZE(pins_twihs2), - .bitrate = CONFIG_I2C_2_BITRATE, + .bitrate = DT_I2C_2_BITRATE, }; static struct i2c_sam_twihs_dev_data i2c2_sam_data; diff --git a/drivers/i2c/i2c_sbcon.c b/drivers/i2c/i2c_sbcon.c index 02511c99622..e8325ebfbf3 100644 --- a/drivers/i2c/i2c_sbcon.c +++ b/drivers/i2c/i2c_sbcon.c @@ -113,7 +113,7 @@ static int i2c_sbcon_init(struct device *dev) static struct i2c_sbcon_context i2c_sbcon_dev_data_##_num; \ \ static const struct i2c_sbcon_config i2c_sbcon_dev_cfg_##_num = { \ - .sbcon = (void *)I2C_SBCON_##_num##_BASE_ADDR, \ + .sbcon = (void *)DT_I2C_SBCON_##_num##_BASE_ADDR, \ }; \ \ DEVICE_INIT(i2c_sbcon_##_num, CONFIG_I2C_SBCON_##_num##_NAME, \ diff --git a/drivers/i2s/i2s_ll_stm32.c b/drivers/i2s/i2s_ll_stm32.c index aa5a0c85140..7bea88abf9c 100644 --- a/drivers/i2s/i2s_ll_stm32.c +++ b/drivers/i2s/i2s_ll_stm32.c @@ -803,10 +803,10 @@ static struct device DEVICE_NAME_GET(i2s_stm32_1); static void i2s_stm32_irq_config_func_1(struct device *dev); static const struct i2s_stm32_cfg i2s_stm32_config_1 = { - .i2s = (SPI_TypeDef *) CONFIG_I2S_1_BASE_ADDRESS, + .i2s = (SPI_TypeDef *) DT_I2S_1_BASE_ADDRESS, .pclken = { - .enr = CONFIG_I2S_1_CLOCK_BITS, - .bus = CONFIG_I2S_1_CLOCK_BUS, + .enr = DT_I2S_1_CLOCK_BITS, + .bus = DT_I2S_1_CLOCK_BUS, }, .i2s_clk_sel = CLK_SEL_2, .irq_config = i2s_stm32_irq_config_func_1, @@ -854,15 +854,15 @@ static struct i2s_stm32_data i2s_stm32_data_1 = { .mem_block_queue.len = ARRAY_SIZE(tx_1_ring_buf), }, }; -DEVICE_AND_API_INIT(i2s_stm32_1, CONFIG_I2S_1_NAME, &i2s_stm32_initialize, +DEVICE_AND_API_INIT(i2s_stm32_1, DT_I2S_1_NAME, &i2s_stm32_initialize, &i2s_stm32_data_1, &i2s_stm32_config_1, POST_KERNEL, CONFIG_I2S_INIT_PRIORITY, &i2s_stm32_driver_api); static void i2s_stm32_irq_config_func_1(struct device *dev) { - IRQ_CONNECT(CONFIG_I2S_1_IRQ, CONFIG_I2S_1_IRQ_PRI, i2s_stm32_isr, + IRQ_CONNECT(DT_I2S_1_IRQ, DT_I2S_1_IRQ_PRI, i2s_stm32_isr, DEVICE_GET(i2s_stm32_1), 0); - irq_enable(CONFIG_I2S_1_IRQ); + irq_enable(DT_I2S_1_IRQ); } #endif /* CONFIG_I2S_1 */ @@ -873,10 +873,10 @@ static struct device DEVICE_NAME_GET(i2s_stm32_2); static void i2s_stm32_irq_config_func_2(struct device *dev); static const struct i2s_stm32_cfg i2s_stm32_config_2 = { - .i2s = (SPI_TypeDef *) CONFIG_I2S_2_BASE_ADDRESS, + .i2s = (SPI_TypeDef *) DT_I2S_2_BASE_ADDRESS, .pclken = { - .enr = CONFIG_I2S_2_CLOCK_BITS, - .bus = CONFIG_I2S_2_CLOCK_BUS, + .enr = DT_I2S_2_CLOCK_BITS, + .bus = DT_I2S_2_CLOCK_BUS, }, .i2s_clk_sel = CLK_SEL_1, .irq_config = i2s_stm32_irq_config_func_2, @@ -924,15 +924,15 @@ static struct i2s_stm32_data i2s_stm32_data_2 = { .mem_block_queue.len = ARRAY_SIZE(tx_2_ring_buf), }, }; -DEVICE_AND_API_INIT(i2s_stm32_2, CONFIG_I2S_2_NAME, &i2s_stm32_initialize, +DEVICE_AND_API_INIT(i2s_stm32_2, DT_I2S_2_NAME, &i2s_stm32_initialize, &i2s_stm32_data_2, &i2s_stm32_config_2, POST_KERNEL, CONFIG_I2S_INIT_PRIORITY, &i2s_stm32_driver_api); static void i2s_stm32_irq_config_func_2(struct device *dev) { - IRQ_CONNECT(CONFIG_I2S_2_IRQ, CONFIG_I2S_2_IRQ_PRI, i2s_stm32_isr, + IRQ_CONNECT(DT_I2S_2_IRQ, DT_I2S_2_IRQ_PRI, i2s_stm32_isr, DEVICE_GET(i2s_stm32_2), 0); - irq_enable(CONFIG_I2S_2_IRQ); + irq_enable(DT_I2S_2_IRQ); } #endif /* CONFIG_I2S_2 */ @@ -943,10 +943,10 @@ static struct device DEVICE_NAME_GET(i2s_stm32_3); static void i2s_stm32_irq_config_func_3(struct device *dev); static const struct i2s_stm32_cfg i2s_stm32_config_3 = { - .i2s = (SPI_TypeDef *) CONFIG_I2S_3_BASE_ADDRESS, + .i2s = (SPI_TypeDef *) DT_I2S_3_BASE_ADDRESS, .pclken = { - .enr = CONFIG_I2S_3_CLOCK_BITS, - .bus = CONFIG_I2S_3_CLOCK_BUS, + .enr = DT_I2S_3_CLOCK_BITS, + .bus = DT_I2S_3_CLOCK_BUS, }, .i2s_clk_sel = CLK_SEL_1, .irq_config = i2s_stm32_irq_config_func_3, @@ -994,15 +994,15 @@ static struct i2s_stm32_data i2s_stm32_data_3 = { .mem_block_queue.len = ARRAY_SIZE(tx_3_ring_buf), }, }; -DEVICE_AND_API_INIT(i2s_stm32_3, CONFIG_I2S_3_NAME, &i2s_stm32_initialize, +DEVICE_AND_API_INIT(i2s_stm32_3, DT_I2S_3_NAME, &i2s_stm32_initialize, &i2s_stm32_data_3, &i2s_stm32_config_3, POST_KERNEL, CONFIG_I2S_INIT_PRIORITY, &i2s_stm32_driver_api); static void i2s_stm32_irq_config_func_3(struct device *dev) { - IRQ_CONNECT(CONFIG_I2S_3_IRQ, CONFIG_I2S_3_IRQ_PRI, i2s_stm32_isr, + IRQ_CONNECT(DT_I2S_3_IRQ, DT_I2S_3_IRQ_PRI, i2s_stm32_isr, DEVICE_GET(i2s_stm32_3), 0); - irq_enable(CONFIG_I2S_3_IRQ); + irq_enable(DT_I2S_3_IRQ); } #endif /* CONFIG_I2S_3 */ @@ -1013,10 +1013,10 @@ static struct device DEVICE_NAME_GET(i2s_stm32_4); static void i2s_stm32_irq_config_func_4(struct device *dev); static const struct i2s_stm32_cfg i2s_stm32_config_4 = { - .i2s = (SPI_TypeDef *) CONFIG_I2S_4_BASE_ADDRESS, + .i2s = (SPI_TypeDef *) DT_I2S_4_BASE_ADDRESS, .pclken = { - .enr = CONFIG_I2S_4_CLOCK_BITS, - .bus = CONFIG_I2S_4_CLOCK_BUS, + .enr = DT_I2S_4_CLOCK_BITS, + .bus = DT_I2S_4_CLOCK_BUS, }, .i2s_clk_sel = CLK_SEL_2, .irq_config = i2s_stm32_irq_config_func_4, @@ -1064,15 +1064,15 @@ static struct i2s_stm32_data i2s_stm32_data_4 = { .mem_block_queue.len = ARRAY_SIZE(tx_4_ring_buf), }, }; -DEVICE_AND_API_INIT(i2s_stm32_4, CONFIG_I2S_4_NAME, &i2s_stm32_initialize, +DEVICE_AND_API_INIT(i2s_stm32_4, DT_I2S_4_NAME, &i2s_stm32_initialize, &i2s_stm32_data_4, &i2s_stm32_config_4, POST_KERNEL, CONFIG_I2S_INIT_PRIORITY, &i2s_stm32_driver_api); static void i2s_stm32_irq_config_func_4(struct device *dev) { - IRQ_CONNECT(CONFIG_I2S_4_IRQ, CONFIG_I2S_4_IRQ_PRI, i2s_stm32_isr, + IRQ_CONNECT(DT_I2S_4_IRQ, DT_I2S_4_IRQ_PRI, i2s_stm32_isr, DEVICE_GET(i2s_stm32_4), 0); - irq_enable(CONFIG_I2S_4_IRQ); + irq_enable(DT_I2S_4_IRQ); } #endif /* CONFIG_I2S_4 */ @@ -1083,10 +1083,10 @@ static struct device DEVICE_NAME_GET(i2s_stm32_5); static void i2s_stm32_irq_config_func_5(struct device *dev); static const struct i2s_stm32_cfg i2s_stm32_config_5 = { - .i2s = (SPI_TypeDef *) CONFIG_I2S_5_BASE_ADDRESS, + .i2s = (SPI_TypeDef *) DT_I2S_5_BASE_ADDRESS, .pclken = { - .enr = CONFIG_I2S_5_CLOCK_BITS, - .bus = CONFIG_I2S_5_CLOCK_BUS, + .enr = DT_I2S_5_CLOCK_BITS, + .bus = DT_I2S_5_CLOCK_BUS, }, .i2s_clk_sel = CLK_SEL_2, .irq_config = i2s_stm32_irq_config_func_5, @@ -1134,15 +1134,15 @@ static struct i2s_stm32_data i2s_stm32_data_5 = { .mem_block_queue.len = ARRAY_SIZE(tx_5_ring_buf), }, }; -DEVICE_AND_API_INIT(i2s_stm32_5, CONFIG_I2S_5_NAME, &i2s_stm32_initialize, +DEVICE_AND_API_INIT(i2s_stm32_5, DT_I2S_5_NAME, &i2s_stm32_initialize, &i2s_stm32_data_5, &i2s_stm32_config_5, POST_KERNEL, CONFIG_I2S_INIT_PRIORITY, &i2s_stm32_driver_api); static void i2s_stm32_irq_config_func_5(struct device *dev) { - IRQ_CONNECT(CONFIG_I2S_5_IRQ, CONFIG_I2S_5_IRQ_PRI, i2s_stm32_isr, + IRQ_CONNECT(DT_I2S_5_IRQ, DT_I2S_5_IRQ_PRI, i2s_stm32_isr, DEVICE_GET(i2s_stm32_5), 0); - irq_enable(CONFIG_I2S_5_IRQ); + irq_enable(DT_I2S_5_IRQ); } #endif /* CONFIG_I2S_5 */ diff --git a/drivers/interrupt_controller/cavs_ictl.c b/drivers/interrupt_controller/cavs_ictl.c index c521ce4eb73..9f057ab4f1d 100644 --- a/drivers/interrupt_controller/cavs_ictl.c +++ b/drivers/interrupt_controller/cavs_ictl.c @@ -89,13 +89,13 @@ static int cavs_ictl_0_initialize(struct device *port) static void cavs_config_0_irq(struct device *port); static const struct cavs_ictl_config cavs_config_0 = { - .irq_num = CAVS_ICTL_0_IRQ, + .irq_num = DT_CAVS_ICTL_0_IRQ, .isr_table_offset = CONFIG_CAVS_ISR_TBL_OFFSET, .config_func = cavs_config_0_irq, }; static struct cavs_ictl_runtime cavs_0_runtime = { - .base_addr = CAVS_ICTL_BASE_ADDR, + .base_addr = DT_CAVS_ICTL_BASE_ADDR, }; DEVICE_AND_API_INIT(cavs_ictl_0, CONFIG_CAVS_ICTL_0_NAME, @@ -104,8 +104,8 @@ DEVICE_AND_API_INIT(cavs_ictl_0, CONFIG_CAVS_ICTL_0_NAME, static void cavs_config_0_irq(struct device *port) { - IRQ_CONNECT(CAVS_ICTL_0_IRQ, CONFIG_CAVS_ICTL_0_IRQ_PRI, cavs_ictl_isr, - DEVICE_GET(cavs_ictl_0), CAVS_ICTL_0_IRQ_FLAGS); + IRQ_CONNECT(DT_CAVS_ICTL_0_IRQ, DT_CAVS_ICTL_0_IRQ_PRI, cavs_ictl_isr, + DEVICE_GET(cavs_ictl_0), DT_CAVS_ICTL_0_IRQ_FLAGS); } static int cavs_ictl_1_initialize(struct device *port) @@ -116,14 +116,14 @@ static int cavs_ictl_1_initialize(struct device *port) static void cavs_config_1_irq(struct device *port); static const struct cavs_ictl_config cavs_config_1 = { - .irq_num = CAVS_ICTL_1_IRQ, + .irq_num = DT_CAVS_ICTL_1_IRQ, .isr_table_offset = CONFIG_CAVS_ISR_TBL_OFFSET + CONFIG_MAX_IRQ_PER_AGGREGATOR, .config_func = cavs_config_1_irq, }; static struct cavs_ictl_runtime cavs_1_runtime = { - .base_addr = CAVS_ICTL_BASE_ADDR + sizeof(struct cavs_registers), + .base_addr = DT_CAVS_ICTL_BASE_ADDR + sizeof(struct cavs_registers), }; DEVICE_AND_API_INIT(cavs_ictl_1, CONFIG_CAVS_ICTL_1_NAME, @@ -132,8 +132,8 @@ DEVICE_AND_API_INIT(cavs_ictl_1, CONFIG_CAVS_ICTL_1_NAME, static void cavs_config_1_irq(struct device *port) { - IRQ_CONNECT(CAVS_ICTL_1_IRQ, CONFIG_CAVS_ICTL_1_IRQ_PRI, cavs_ictl_isr, - DEVICE_GET(cavs_ictl_1), CAVS_ICTL_1_IRQ_FLAGS); + IRQ_CONNECT(DT_CAVS_ICTL_1_IRQ, DT_CAVS_ICTL_1_IRQ_PRI, cavs_ictl_isr, + DEVICE_GET(cavs_ictl_1), DT_CAVS_ICTL_1_IRQ_FLAGS); } static int cavs_ictl_2_initialize(struct device *port) @@ -144,14 +144,14 @@ static int cavs_ictl_2_initialize(struct device *port) static void cavs_config_2_irq(struct device *port); static const struct cavs_ictl_config cavs_config_2 = { - .irq_num = CAVS_ICTL_2_IRQ, + .irq_num = DT_CAVS_ICTL_2_IRQ, .isr_table_offset = CONFIG_CAVS_ISR_TBL_OFFSET + CONFIG_MAX_IRQ_PER_AGGREGATOR * 2, .config_func = cavs_config_2_irq, }; static struct cavs_ictl_runtime cavs_2_runtime = { - .base_addr = CAVS_ICTL_BASE_ADDR + sizeof(struct cavs_registers) * 2, + .base_addr = DT_CAVS_ICTL_BASE_ADDR + sizeof(struct cavs_registers) * 2, }; DEVICE_AND_API_INIT(cavs_ictl_2, CONFIG_CAVS_ICTL_2_NAME, @@ -160,8 +160,8 @@ DEVICE_AND_API_INIT(cavs_ictl_2, CONFIG_CAVS_ICTL_2_NAME, static void cavs_config_2_irq(struct device *port) { - IRQ_CONNECT(CAVS_ICTL_2_IRQ, CONFIG_CAVS_ICTL_2_IRQ_PRI, cavs_ictl_isr, - DEVICE_GET(cavs_ictl_2), CAVS_ICTL_2_IRQ_FLAGS); + IRQ_CONNECT(DT_CAVS_ICTL_2_IRQ, DT_CAVS_ICTL_2_IRQ_PRI, cavs_ictl_isr, + DEVICE_GET(cavs_ictl_2), DT_CAVS_ICTL_2_IRQ_FLAGS); } static int cavs_ictl_3_initialize(struct device *port) @@ -172,14 +172,14 @@ static int cavs_ictl_3_initialize(struct device *port) static void cavs_config_3_irq(struct device *port); static const struct cavs_ictl_config cavs_config_3 = { - .irq_num = CAVS_ICTL_3_IRQ, + .irq_num = DT_CAVS_ICTL_3_IRQ, .isr_table_offset = CONFIG_CAVS_ISR_TBL_OFFSET + CONFIG_MAX_IRQ_PER_AGGREGATOR*3, .config_func = cavs_config_3_irq, }; static struct cavs_ictl_runtime cavs_3_runtime = { - .base_addr = CAVS_ICTL_BASE_ADDR + sizeof(struct cavs_registers) * 3, + .base_addr = DT_CAVS_ICTL_BASE_ADDR + sizeof(struct cavs_registers) * 3, }; DEVICE_AND_API_INIT(cavs_ictl_3, CONFIG_CAVS_ICTL_3_NAME, @@ -188,6 +188,6 @@ DEVICE_AND_API_INIT(cavs_ictl_3, CONFIG_CAVS_ICTL_3_NAME, static void cavs_config_3_irq(struct device *port) { - IRQ_CONNECT(CAVS_ICTL_3_IRQ, CONFIG_CAVS_ICTL_3_IRQ_PRI, cavs_ictl_isr, - DEVICE_GET(cavs_ictl_3), CAVS_ICTL_3_IRQ_FLAGS); + IRQ_CONNECT(DT_CAVS_ICTL_3_IRQ, DT_CAVS_ICTL_3_IRQ_PRI, cavs_ictl_isr, + DEVICE_GET(cavs_ictl_3), DT_CAVS_ICTL_3_IRQ_FLAGS); } diff --git a/drivers/interrupt_controller/dw_ictl.c b/drivers/interrupt_controller/dw_ictl.c index 0ac2a9cd57a..c714aebb774 100644 --- a/drivers/interrupt_controller/dw_ictl.c +++ b/drivers/interrupt_controller/dw_ictl.c @@ -116,14 +116,14 @@ static inline unsigned int dw_ictl_intr_get_state(struct device *dev) static void dw_ictl_config_irq(struct device *port); static const struct dw_ictl_config dw_config = { - .irq_num = DW_ICTL_IRQ, + .irq_num = DT_DW_ICTL_IRQ, .numirqs = DW_ICTL_NUM_IRQS, .isr_table_offset = CONFIG_DW_ISR_TBL_OFFSET, .config_func = dw_ictl_config_irq, }; static struct dw_ictl_runtime dw_runtime = { - .base_addr = DW_ICTL_BASE_ADDR, + .base_addr = DT_DW_ICTL_BASE_ADDR, }; static const struct irq_next_level_api dw_ictl_apis = { @@ -138,6 +138,6 @@ DEVICE_AND_API_INIT(dw_ictl, CONFIG_DW_ICTL_NAME, dw_ictl_initialize, static void dw_ictl_config_irq(struct device *port) { - IRQ_CONNECT(DW_ICTL_IRQ, CONFIG_DW_ICTL_IRQ_PRI, dw_ictl_isr, - DEVICE_GET(dw_ictl), DW_ICTL_IRQ_FLAGS); + IRQ_CONNECT(DT_DW_ICTL_IRQ, DT_DW_ICTL_IRQ_PRI, dw_ictl_isr, + DEVICE_GET(dw_ictl), DT_DW_ICTL_IRQ_FLAGS); } diff --git a/drivers/interrupt_controller/ioapic_intr.c b/drivers/interrupt_controller/ioapic_intr.c index 1249fe06feb..5cbd88857ef 100644 --- a/drivers/interrupt_controller/ioapic_intr.c +++ b/drivers/interrupt_controller/ioapic_intr.c @@ -328,8 +328,8 @@ static u32_t __IoApicGet(s32_t offset) key = irq_lock(); *((volatile u32_t *) - (CONFIG_IOAPIC_BASE_ADDRESS + IOAPIC_IND)) = (char)offset; - value = *((volatile u32_t *)(CONFIG_IOAPIC_BASE_ADDRESS + IOAPIC_DATA)); + (DT_IOAPIC_BASE_ADDRESS + IOAPIC_IND)) = (char)offset; + value = *((volatile u32_t *)(DT_IOAPIC_BASE_ADDRESS + IOAPIC_DATA)); irq_unlock(key); @@ -354,8 +354,8 @@ static void __IoApicSet(s32_t offset, u32_t value) key = irq_lock(); - *(volatile u32_t *)(CONFIG_IOAPIC_BASE_ADDRESS + IOAPIC_IND) = (char)offset; - *((volatile u32_t *)(CONFIG_IOAPIC_BASE_ADDRESS + IOAPIC_DATA)) = value; + *(volatile u32_t *)(DT_IOAPIC_BASE_ADDRESS + IOAPIC_IND) = (char)offset; + *((volatile u32_t *)(DT_IOAPIC_BASE_ADDRESS + IOAPIC_DATA)) = value; irq_unlock(key); } diff --git a/drivers/ipm/ipm_mcux.c b/drivers/ipm/ipm_mcux.c index fdc09a9976c..90466fe5731 100644 --- a/drivers/ipm/ipm_mcux.c +++ b/drivers/ipm/ipm_mcux.c @@ -154,13 +154,13 @@ static const struct ipm_driver_api mcux_mailbox_driver_api = { static void mcux_mailbox_config_func_0(struct device *dev); static const struct mcux_mailbox_config mcux_mailbox_0_config = { - .base = (MAILBOX_Type *)CONFIG_MAILBOX_MCUX_MAILBOX_0_BASE_ADDRESS, + .base = (MAILBOX_Type *)DT_MAILBOX_MCUX_MAILBOX_0_BASE_ADDRESS, .irq_config_func = mcux_mailbox_config_func_0, }; static struct mcux_mailbox_data mcux_mailbox_0_data; -DEVICE_AND_API_INIT(mailbox_0, CONFIG_MAILBOX_MCUX_MAILBOX_0_NAME, +DEVICE_AND_API_INIT(mailbox_0, DT_MAILBOX_MCUX_MAILBOX_0_NAME, &mcux_mailbox_init, &mcux_mailbox_0_data, &mcux_mailbox_0_config, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, @@ -169,9 +169,9 @@ DEVICE_AND_API_INIT(mailbox_0, CONFIG_MAILBOX_MCUX_MAILBOX_0_NAME, static void mcux_mailbox_config_func_0(struct device *dev) { - IRQ_CONNECT(CONFIG_MAILBOX_MCUX_MAILBOX_0_IRQ, - CONFIG_MAILBOX_MCUX_MAILBOX_0_IRQ_PRI, + IRQ_CONNECT(DT_MAILBOX_MCUX_MAILBOX_0_IRQ, + DT_MAILBOX_MCUX_MAILBOX_0_IRQ_PRI, mcux_mailbox_isr, DEVICE_GET(mailbox_0), 0); - irq_enable(CONFIG_MAILBOX_MCUX_MAILBOX_0_IRQ); + irq_enable(DT_MAILBOX_MCUX_MAILBOX_0_IRQ); } diff --git a/drivers/modem/wncm14a2a.c b/drivers/modem/wncm14a2a.c index fc413a2f8a0..e8384bac491 100644 --- a/drivers/modem/wncm14a2a.c +++ b/drivers/modem/wncm14a2a.c @@ -54,7 +54,7 @@ enum mdm_control_pins { MDM_KEEP_AWAKE, MDM_RESET, SHLD_3V3_1V8_SIG_TRANS_ENA, -#ifdef CONFIG_WNCM14A2A_GPIO_MDM_SEND_OK_PIN +#ifdef DT_WNCM14A2A_GPIO_MDM_SEND_OK_PIN MDM_SEND_OK, #endif MAX_MDM_CONTROL_PINS, @@ -62,33 +62,33 @@ enum mdm_control_pins { static const struct mdm_control_pinconfig pinconfig[] = { /* MDM_BOOT_MODE_SEL */ - PINCONFIG(CONFIG_WNCM14A2A_GPIO_MDM_BOOT_MODE_SEL_NAME, - CONFIG_WNCM14A2A_GPIO_MDM_BOOT_MODE_SEL_PIN), + PINCONFIG(DT_WNCM14A2A_GPIO_MDM_BOOT_MODE_SEL_NAME, + DT_WNCM14A2A_GPIO_MDM_BOOT_MODE_SEL_PIN), /* MDM_POWER */ - PINCONFIG(CONFIG_WNCM14A2A_GPIO_MDM_POWER_NAME, - CONFIG_WNCM14A2A_GPIO_MDM_POWER_PIN), + PINCONFIG(DT_WNCM14A2A_GPIO_MDM_POWER_NAME, + DT_WNCM14A2A_GPIO_MDM_POWER_PIN), /* MDM_KEEP_AWAKE */ - PINCONFIG(CONFIG_WNCM14A2A_GPIO_MDM_KEEP_AWAKE_NAME, - CONFIG_WNCM14A2A_GPIO_MDM_KEEP_AWAKE_PIN), + PINCONFIG(DT_WNCM14A2A_GPIO_MDM_KEEP_AWAKE_NAME, + DT_WNCM14A2A_GPIO_MDM_KEEP_AWAKE_PIN), /* MDM_RESET */ - PINCONFIG(CONFIG_WNCM14A2A_GPIO_MDM_RESET_NAME, - CONFIG_WNCM14A2A_GPIO_MDM_RESET_PIN), + PINCONFIG(DT_WNCM14A2A_GPIO_MDM_RESET_NAME, + DT_WNCM14A2A_GPIO_MDM_RESET_PIN), /* SHLD_3V3_1V8_SIG_TRANS_ENA */ - PINCONFIG(CONFIG_WNCM14A2A_GPIO_MDM_SHLD_TRANS_ENA_NAME, - CONFIG_WNCM14A2A_GPIO_MDM_SHLD_TRANS_ENA_PIN), + PINCONFIG(DT_WNCM14A2A_GPIO_MDM_SHLD_TRANS_ENA_NAME, + DT_WNCM14A2A_GPIO_MDM_SHLD_TRANS_ENA_PIN), -#ifdef CONFIG_WNCM14A2A_GPIO_MDM_SEND_OK_PIN +#ifdef DT_WNCM14A2A_GPIO_MDM_SEND_OK_PIN /* MDM_SEND_OK */ - PINCONFIG(CONFIG_WNCM14A2A_GPIO_MDM_SEND_OK_NAME, - CONFIG_WNCM14A2A_GPIO_MDM_SEND_OK_PIN), + PINCONFIG(DT_WNCM14A2A_GPIO_MDM_SEND_OK_NAME, + DT_WNCM14A2A_GPIO_MDM_SEND_OK_PIN), #endif }; -#define MDM_UART_DEV_NAME CONFIG_WNCM14A2A_UART_DRV_NAME +#define MDM_UART_DEV_NAME DT_WNCM14A2A_UART_DRV_NAME #define MDM_BOOT_MODE_SPECIAL 0 #define MDM_BOOT_MODE_NORMAL 1 @@ -1256,7 +1256,7 @@ static int modem_pin_init(void) LOG_DBG("MDM_KEEP_AWAKE_PIN -> ENABLED"); gpio_pin_write(ictx.gpio_port_dev[MDM_KEEP_AWAKE], pinconfig[MDM_KEEP_AWAKE].pin, MDM_KEEP_AWAKE_ENABLED); -#ifdef CONFIG_WNCM14A2A_GPIO_MDM_SEND_OK_PIN +#ifdef DT_WNCM14A2A_GPIO_MDM_SEND_OK_PIN LOG_DBG("MDM_SEND_OK_PIN -> ENABLED"); gpio_pin_write(ictx.gpio_port_dev[MDM_SEND_OK], pinconfig[MDM_SEND_OK].pin, MDM_SEND_OK_ENABLED); diff --git a/drivers/neural_net/intel_gna.c b/drivers/neural_net/intel_gna.c index c81587f1697..8e16eb6e803 100644 --- a/drivers/neural_net/intel_gna.c +++ b/drivers/neural_net/intel_gna.c @@ -141,8 +141,8 @@ static int intel_gna_setup_page_table(void *physical, size_t size, LOG_DBG("physical %p size %u virtual %p", physical, size, virtual); - if (((phys_addr + size - L2_SRAM_BASE) > L2_SRAM_SIZE) || - (phys_addr < L2_SRAM_BASE)) { + if (((phys_addr + size - DT_L2_SRAM_BASE) > DT_L2_SRAM_SIZE) || + (phys_addr < DT_L2_SRAM_BASE)) { LOG_ERR("model at %p of size %u exceeds L2 SRAM space", physical, size); return -EINVAL; diff --git a/drivers/neural_net/intel_gna.h b/drivers/neural_net/intel_gna.h index 8b836278007..a648762b397 100644 --- a/drivers/neural_net/intel_gna.h +++ b/drivers/neural_net/intel_gna.h @@ -63,7 +63,7 @@ extern "C" { #define GNA_LAYER_DESC_ALIGN (128) -#define GNA_ADDRESSABLE_MEM_SIZE L2_SRAM_SIZE +#define GNA_ADDRESSABLE_MEM_SIZE DT_L2_SRAM_SIZE #define GNA_NUM_PG_TABLE_INDEX_BITS 10 #define GNA_NUM_PG_TABLE_ENTRIES BIT(GNA_NUM_PG_TABLE_INDEX_BITS) #define GNA_PG_SIZE_IN_BITSHIFT 12 diff --git a/drivers/pinmux/dev/pinmux_dev_arm_beetle.c b/drivers/pinmux/dev/pinmux_dev_arm_beetle.c index 135be74505c..19886f75a31 100644 --- a/drivers/pinmux/dev/pinmux_dev_arm_beetle.c +++ b/drivers/pinmux/dev/pinmux_dev_arm_beetle.c @@ -17,9 +17,9 @@ #define PINS_PER_PORT 16 #define CMSDK_AHB_GPIO0_DEV \ - ((volatile struct gpio_cmsdk_ahb *)CMSDK_AHB_GPIO0) + ((volatile struct gpio_cmsdk_ahb *)DT_CMSDK_AHB_GPIO0) #define CMSDK_AHB_GPIO1_DEV \ - ((volatile struct gpio_cmsdk_ahb *)CMSDK_AHB_GPIO1) + ((volatile struct gpio_cmsdk_ahb *)DT_CMSDK_AHB_GPIO1) static volatile struct gpio_cmsdk_ahb *_get_port(u32_t pin) { diff --git a/drivers/pinmux/pinmux_sam0.c b/drivers/pinmux/pinmux_sam0.c index 2fc97b36267..30093386c55 100644 --- a/drivers/pinmux/pinmux_sam0.c +++ b/drivers/pinmux/pinmux_sam0.c @@ -69,23 +69,23 @@ const struct pinmux_driver_api pinmux_sam0_api = { .input = pinmux_sam0_input, }; -#if CONFIG_PINMUX_SAM0_A_BASE_ADDRESS +#if DT_PINMUX_SAM0_A_BASE_ADDRESS static const struct pinmux_sam0_config pinmux_sam0_config_0 = { - .regs = (PortGroup *)CONFIG_PINMUX_SAM0_A_BASE_ADDRESS, + .regs = (PortGroup *)DT_PINMUX_SAM0_A_BASE_ADDRESS, }; -DEVICE_AND_API_INIT(pinmux_sam0_0, CONFIG_PINMUX_SAM0_A_LABEL, +DEVICE_AND_API_INIT(pinmux_sam0_0, DT_PINMUX_SAM0_A_LABEL, pinmux_sam0_init, NULL, &pinmux_sam0_config_0, PRE_KERNEL_1, CONFIG_PINMUX_INIT_PRIORITY, &pinmux_sam0_api); #endif -#if CONFIG_PINMUX_SAM0_B_BASE_ADDRESS +#if DT_PINMUX_SAM0_B_BASE_ADDRESS static const struct pinmux_sam0_config pinmux_sam0_config_1 = { - .regs = (PortGroup *)CONFIG_PINMUX_SAM0_B_BASE_ADDRESS, + .regs = (PortGroup *)DT_PINMUX_SAM0_B_BASE_ADDRESS, }; -DEVICE_AND_API_INIT(pinmux_sam0_1, CONFIG_PINMUX_SAM0_B_LABEL, +DEVICE_AND_API_INIT(pinmux_sam0_1, DT_PINMUX_SAM0_B_LABEL, pinmux_sam0_init, NULL, &pinmux_sam0_config_1, PRE_KERNEL_1, CONFIG_PINMUX_INIT_PRIORITY, &pinmux_sam0_api); diff --git a/drivers/pwm/pwm_mcux_ftm.c b/drivers/pwm/pwm_mcux_ftm.c index bfc06ff522e..d2cbc89fedc 100644 --- a/drivers/pwm/pwm_mcux_ftm.c +++ b/drivers/pwm/pwm_mcux_ftm.c @@ -162,7 +162,7 @@ DEVICE_AND_API_INIT(mcux_ftm_0, CONFIG_FTM_0_NAME, &mcux_ftm_init, #ifdef CONFIG_PWM_1 static const struct mcux_ftm_config mcux_ftm_config_1 = { - .base = (FTM_Type *)CONFIG_FTM_1_BASE_ADDRESS, + .base = (FTM_Type *)DT_FTM_1_BASE_ADDRESS, .clock_source = kCLOCK_McgFixedFreqClk, .ftm_clock_source = kFTM_FixedClock, .prescale = kFTM_Prescale_Divide_16, @@ -172,7 +172,7 @@ static const struct mcux_ftm_config mcux_ftm_config_1 = { static struct mcux_ftm_data mcux_ftm_data_1; -DEVICE_AND_API_INIT(mcux_ftm_1, CONFIG_FTM_1_NAME, &mcux_ftm_init, +DEVICE_AND_API_INIT(mcux_ftm_1, DT_FTM_1_NAME, &mcux_ftm_init, &mcux_ftm_data_1, &mcux_ftm_config_1, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &mcux_ftm_driver_api); @@ -198,7 +198,7 @@ DEVICE_AND_API_INIT(mcux_ftm_2, CONFIG_FTM_2_NAME, &mcux_ftm_init, #ifdef CONFIG_PWM_3 static const struct mcux_ftm_config mcux_ftm_config_3 = { - .base = (FTM_Type *)CONFIG_FTM_3_BASE_ADDRESS, + .base = (FTM_Type *)DT_FTM_3_BASE_ADDRESS, .clock_source = kCLOCK_McgFixedFreqClk, .ftm_clock_source = kFTM_FixedClock, .prescale = kFTM_Prescale_Divide_16, @@ -208,7 +208,7 @@ static const struct mcux_ftm_config mcux_ftm_config_3 = { static struct mcux_ftm_data mcux_ftm_data_3; -DEVICE_AND_API_INIT(mcux_ftm_3, CONFIG_FTM_3_NAME, &mcux_ftm_init, +DEVICE_AND_API_INIT(mcux_ftm_3, DT_FTM_3_NAME, &mcux_ftm_init, &mcux_ftm_data_3, &mcux_ftm_config_3, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &mcux_ftm_driver_api); diff --git a/drivers/pwm/pwm_stm32.c b/drivers/pwm/pwm_stm32.c index 5eff169b154..f2b16c45cff 100644 --- a/drivers/pwm/pwm_stm32.c +++ b/drivers/pwm/pwm_stm32.c @@ -215,7 +215,7 @@ static int pwm_stm32_init(struct device *dev) }; \ \ DEVICE_AND_API_INIT(pwm_stm32_ ## n, \ - CONFIG_PWM_STM32_ ## n ## _DEV_NAME, \ + DT_PWM_STM32_ ## n ## _DEV_NAME, \ pwm_stm32_init, \ &pwm_stm32_dev_data_ ## n, \ &pwm_stm32_dev_cfg_ ## n, \ @@ -225,115 +225,115 @@ static int pwm_stm32_init(struct device *dev) #ifdef CONFIG_PWM_STM32_1 /* 16-bit advanced-control timer */ #ifdef CONFIG_SOC_SERIES_STM32F0X -PWM_DEVICE_INIT_STM32(1, APB1, GRP2, CONFIG_PWM_STM32_1_PRESCALER) +PWM_DEVICE_INIT_STM32(1, APB1, GRP2, DT_PWM_STM32_1_PRESCALER) #else -PWM_DEVICE_INIT_STM32(1, APB2, GRP1, CONFIG_PWM_STM32_1_PRESCALER) +PWM_DEVICE_INIT_STM32(1, APB2, GRP1, DT_PWM_STM32_1_PRESCALER) #endif /*CONFIG_SOC_SERIES_STM32F0X */ #endif /* CONFIG_PWM_STM32_1 */ #ifdef CONFIG_PWM_STM32_2 /* 32-bit general-purpose timer */ -PWM_DEVICE_INIT_STM32(2, APB1, GRP1, CONFIG_PWM_STM32_2_PRESCALER) +PWM_DEVICE_INIT_STM32(2, APB1, GRP1, DT_PWM_STM32_2_PRESCALER) #endif /* CONFIG_PWM_STM32_2 */ #ifdef CONFIG_PWM_STM32_3 /* 16-bit general-purpose timer */ -PWM_DEVICE_INIT_STM32(3, APB1, GRP1, CONFIG_PWM_STM32_3_PRESCALER) +PWM_DEVICE_INIT_STM32(3, APB1, GRP1, DT_PWM_STM32_3_PRESCALER) #endif /* CONFIG_PWM_STM32_3 */ #ifdef CONFIG_PWM_STM32_4 /* 16-bit general-purpose timer */ -PWM_DEVICE_INIT_STM32(4, APB1, GRP1, CONFIG_PWM_STM32_4_PRESCALER) +PWM_DEVICE_INIT_STM32(4, APB1, GRP1, DT_PWM_STM32_4_PRESCALER) #endif /* CONFIG_PWM_STM32_4 */ #ifdef CONFIG_PWM_STM32_5 /* 32-bit general-purpose timer */ -PWM_DEVICE_INIT_STM32(5, APB1, GRP1, CONFIG_PWM_STM32_5_PRESCALER) +PWM_DEVICE_INIT_STM32(5, APB1, GRP1, DT_PWM_STM32_5_PRESCALER) #endif /* CONFIG_PWM_STM32_5 */ #ifdef CONFIG_PWM_STM32_6 /* 16-bit basic timer */ -PWM_DEVICE_INIT_STM32(6, APB1, GRP1, CONFIG_PWM_STM32_6_PRESCALER) +PWM_DEVICE_INIT_STM32(6, APB1, GRP1, DT_PWM_STM32_6_PRESCALER) #endif /* CONFIG_PWM_STM32_6 */ #ifdef CONFIG_PWM_STM32_7 /* 16-bit basic timer */ -PWM_DEVICE_INIT_STM32(7, APB1, GRP1, CONFIG_PWM_STM32_7_PRESCALER) +PWM_DEVICE_INIT_STM32(7, APB1, GRP1, DT_PWM_STM32_7_PRESCALER) #endif /* CONFIG_PWM_STM32_7 */ #ifdef CONFIG_PWM_STM32_8 /* 16-bit advanced-control timer */ -PWM_DEVICE_INIT_STM32(8, APB2, GRP1, CONFIG_PWM_STM32_8_PRESCALER) +PWM_DEVICE_INIT_STM32(8, APB2, GRP1, DT_PWM_STM32_8_PRESCALER) #endif /* CONFIG_PWM_STM32_8 */ #ifdef CONFIG_PWM_STM32_9 /* 16-bit general-purpose timer */ -PWM_DEVICE_INIT_STM32(9, APB2, GRP1, CONFIG_PWM_STM32_9_PRESCALER) +PWM_DEVICE_INIT_STM32(9, APB2, GRP1, DT_PWM_STM32_9_PRESCALER) #endif /* CONFIG_PWM_STM32_9 */ #ifdef CONFIG_PWM_STM32_10 /* 16-bit general-purpose timer */ -PWM_DEVICE_INIT_STM32(10, APB2, GRP1, CONFIG_PWM_STM32_10_PRESCALER) +PWM_DEVICE_INIT_STM32(10, APB2, GRP1, DT_PWM_STM32_10_PRESCALER) #endif /* CONFIG_PWM_STM32_10 */ #ifdef CONFIG_PWM_STM32_11 /* 16-bit general-purpose timer */ -PWM_DEVICE_INIT_STM32(11, APB2, GRP1, CONFIG_PWM_STM32_11_PRESCALER) +PWM_DEVICE_INIT_STM32(11, APB2, GRP1, DT_PWM_STM32_11_PRESCALER) #endif /* CONFIG_PWM_STM32_11 */ #ifdef CONFIG_PWM_STM32_12 /* 16-bit general-purpose timer */ -PWM_DEVICE_INIT_STM32(12, APB1, GRP1, CONFIG_PWM_STM32_12_PRESCALER) +PWM_DEVICE_INIT_STM32(12, APB1, GRP1, DT_PWM_STM32_12_PRESCALER) #endif /* CONFIG_PWM_STM32_12 */ #ifdef CONFIG_PWM_STM32_13 /* 16-bit general-purpose timer */ -PWM_DEVICE_INIT_STM32(13, APB1, GRP1, CONFIG_PWM_STM32_13_PRESCALER) +PWM_DEVICE_INIT_STM32(13, APB1, GRP1, DT_PWM_STM32_13_PRESCALER) #endif /* CONFIG_PWM_STM32_13 */ #ifdef CONFIG_PWM_STM32_14 /* 16-bit general-purpose timer */ -PWM_DEVICE_INIT_STM32(14, APB1, GRP1, CONFIG_PWM_STM32_14_PRESCALER) +PWM_DEVICE_INIT_STM32(14, APB1, GRP1, DT_PWM_STM32_14_PRESCALER) #endif /* CONFIG_PWM_STM32_14 */ #ifdef CONFIG_PWM_STM32_15 /* 16-bit general-purpose timer */ #ifdef CONFIG_SOC_SERIES_STM32F0X -PWM_DEVICE_INIT_STM32(15, APB1, GRP2, CONFIG_PWM_STM32_15_PRESCALER) +PWM_DEVICE_INIT_STM32(15, APB1, GRP2, DT_PWM_STM32_15_PRESCALER) #else -PWM_DEVICE_INIT_STM32(15, APB2, GRP1, CONFIG_PWM_STM32_15_PRESCALER) +PWM_DEVICE_INIT_STM32(15, APB2, GRP1, DT_PWM_STM32_15_PRESCALER) #endif /* CONFIG_SOC_SERIES_STM32F0X */ #endif /* CONFIG_PWM_STM32_15 */ #ifdef CONFIG_PWM_STM32_16 /* 16-bit general-purpose timer */ #ifdef CONFIG_SOC_SERIES_STM32F0X -PWM_DEVICE_INIT_STM32(16, APB1, GRP2, CONFIG_PWM_STM32_16_PRESCALER) +PWM_DEVICE_INIT_STM32(16, APB1, GRP2, DT_PWM_STM32_16_PRESCALER) #else -PWM_DEVICE_INIT_STM32(16, APB2, GRP1, CONFIG_PWM_STM32_16_PRESCALER) +PWM_DEVICE_INIT_STM32(16, APB2, GRP1, DT_PWM_STM32_16_PRESCALER) #endif /* CONFIG_SOC_SERIES_STM32F0X */ #endif /* CONFIG_PWM_STM32_16 */ #ifdef CONFIG_PWM_STM32_17 /* 16-bit general-purpose timer */ #ifdef CONFIG_SOC_SERIES_STM32F0X -PWM_DEVICE_INIT_STM32(17, APB1, GRP2, CONFIG_PWM_STM32_17_PRESCALER) +PWM_DEVICE_INIT_STM32(17, APB1, GRP2, DT_PWM_STM32_17_PRESCALER) #else -PWM_DEVICE_INIT_STM32(17, APB2, GRP1, CONFIG_PWM_STM32_17_PRESCALER) +PWM_DEVICE_INIT_STM32(17, APB2, GRP1, DT_PWM_STM32_17_PRESCALER) #endif /* CONFIG_SOC_SERIES_STM32F0X */ #endif /* CONFIG_PWM_STM32_17 */ #ifdef CONFIG_PWM_STM32_18 /* 16-bit advanced timer */ -PWM_DEVICE_INIT_STM32(18, APB1, GRP1, CONFIG_PWM_STM32_18_PRESCALER) +PWM_DEVICE_INIT_STM32(18, APB1, GRP1, DT_PWM_STM32_18_PRESCALER) #endif /* CONFIG_PWM_STM32_18 */ #ifdef CONFIG_PWM_STM32_19 /* 16-bit general-purpose timer */ -PWM_DEVICE_INIT_STM32(19, APB2, GRP1, CONFIG_PWM_STM32_19_PRESCALER) +PWM_DEVICE_INIT_STM32(19, APB2, GRP1, DT_PWM_STM32_19_PRESCALER) #endif /* CONFIG_PWM_STM32_19 */ #ifdef CONFIG_PWM_STM32_20 /* 16-bit advanced timer */ -PWM_DEVICE_INIT_STM32(20, APB2, GRP1, CONFIG_PWM_STM32_20_PRESCALER) +PWM_DEVICE_INIT_STM32(20, APB2, GRP1, DT_PWM_STM32_20_PRESCALER) #endif /* CONFIG_PWM_STM32_20 */ diff --git a/drivers/rtc/rtc_ll_stm32.c b/drivers/rtc/rtc_ll_stm32.c index 5d5e533a5cf..5591cf01ec0 100644 --- a/drivers/rtc/rtc_ll_stm32.c +++ b/drivers/rtc/rtc_ll_stm32.c @@ -302,7 +302,7 @@ DEVICE_AND_API_INIT(rtc_stm32, CONFIG_RTC_0_NAME, &rtc_stm32_init, static void rtc_stm32_irq_config(struct device *dev) { - IRQ_CONNECT(CONFIG_RTC_0_IRQ, CONFIG_RTC_0_IRQ_PRI, + IRQ_CONNECT(DT_RTC_0_IRQ, CONFIG_RTC_0_IRQ_PRI, rtc_stm32_isr, DEVICE_GET(rtc_stm32), 0); - irq_enable(CONFIG_RTC_0_IRQ); + irq_enable(DT_RTC_0_IRQ); } diff --git a/drivers/rtc/rtc_mcux.c b/drivers/rtc/rtc_mcux.c index c7fd385fd7a..a17b6ff7e35 100644 --- a/drivers/rtc/rtc_mcux.c +++ b/drivers/rtc/rtc_mcux.c @@ -190,18 +190,18 @@ static struct mcux_rtc_data rtc_mcux_data_0; static void rtc_mcux_irq_config_0(struct device *dev); static struct mcux_rtc_config rtc_mcux_config_0 = { - .base = (RTC_Type *)CONFIG_RTC_MCUX_0_BASE_ADDRESS, + .base = (RTC_Type *)DT_RTC_MCUX_0_BASE_ADDRESS, .irq_config_func = rtc_mcux_irq_config_0, }; -DEVICE_DEFINE(rtc, CONFIG_RTC_MCUX_0_NAME, +DEVICE_DEFINE(rtc, DT_RTC_MCUX_0_NAME, &mcux_rtc_init, NULL, &rtc_mcux_data_0, &rtc_mcux_config_0, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &mcux_rtc_driver_api); static void rtc_mcux_irq_config_0(struct device *dev) { - IRQ_CONNECT(CONFIG_RTC_MCUX_0_IRQ, CONFIG_RTC_MCUX_0_IRQ_PRI, + IRQ_CONNECT(DT_RTC_MCUX_0_IRQ, DT_RTC_MCUX_0_IRQ_PRI, mcux_rtc_isr, DEVICE_GET(rtc), 0); - irq_enable(CONFIG_RTC_MCUX_0_IRQ); + irq_enable(DT_RTC_MCUX_0_IRQ); } diff --git a/drivers/rtc/rtc_qmsi.c b/drivers/rtc/rtc_qmsi.c index 6ec31f6d9cd..d6ffcd501b6 100644 --- a/drivers/rtc/rtc_qmsi.c +++ b/drivers/rtc/rtc_qmsi.c @@ -142,11 +142,11 @@ static int rtc_qmsi_init(struct device *dev) k_sem_init(RP_GET(dev), 1, UINT_MAX); } - IRQ_CONNECT(CONFIG_RTC_0_IRQ, CONFIG_RTC_0_IRQ_PRI, - qm_rtc_0_isr, NULL, CONFIG_RTC_0_IRQ_FLAGS); + IRQ_CONNECT(DT_RTC_0_IRQ, CONFIG_RTC_0_IRQ_PRI, + qm_rtc_0_isr, NULL, DT_RTC_0_IRQ_FLAGS); /* Unmask RTC interrupt */ - irq_enable(CONFIG_RTC_0_IRQ); + irq_enable(DT_RTC_0_IRQ); /* Route RTC interrupt to the current core */ QM_IR_UNMASK_INTERRUPTS(QM_INTERRUPT_ROUTER->rtc_0_int_mask); diff --git a/drivers/sensor/adt7420/adt7420.c b/drivers/sensor/adt7420/adt7420.c index 46d5e4cb94b..96f018ad136 100644 --- a/drivers/sensor/adt7420/adt7420.c +++ b/drivers/sensor/adt7420/adt7420.c @@ -216,14 +216,14 @@ static int adt7420_init(struct device *dev) static struct adt7420_data adt7420_driver; static const struct adt7420_dev_config adt7420_config = { - .i2c_port = CONFIG_ADT7420_I2C_MASTER_DEV_NAME, - .i2c_addr = CONFIG_ADT7420_I2C_ADDR, + .i2c_port = DT_ADT7420_I2C_MASTER_DEV_NAME, + .i2c_addr = DT_ADT7420_I2C_ADDR, #ifdef CONFIG_ADT7420_TRIGGER - .gpio_port = CONFIG_ADT7420_GPIO_DEV_NAME, - .int_gpio = CONFIG_ADT7420_GPIO_PIN_NUM, + .gpio_port = DT_ADT7420_GPIO_DEV_NAME, + .int_gpio = DT_ADT7420_GPIO_PIN_NUM, #endif }; -DEVICE_AND_API_INIT(adt7420, CONFIG_ADT7420_NAME, adt7420_init, &adt7420_driver, +DEVICE_AND_API_INIT(adt7420, DT_ADT7420_NAME, adt7420_init, &adt7420_driver, &adt7420_config, POST_KERNEL, CONFIG_SENSOR_INIT_PRIORITY, &adt7420_driver_api); diff --git a/drivers/sensor/adxl372/adxl372.c b/drivers/sensor/adxl372/adxl372.c index 25ae8ec6f3b..f2e08497a4f 100644 --- a/drivers/sensor/adxl372/adxl372.c +++ b/drivers/sensor/adxl372/adxl372.c @@ -925,21 +925,21 @@ static struct adxl372_data adxl372_data; static const struct adxl372_dev_config adxl372_config = { #ifdef CONFIG_ADXL372_I2C - .i2c_port = CONFIG_ADXL372_I2C_MASTER_DEV_NAME, - .i2c_addr = CONFIG_ADXL372_I2C_ADDR, + .i2c_port = DT_ADXL372_I2C_MASTER_DEV_NAME, + .i2c_addr = DT_ADXL372_I2C_ADDR, #endif #ifdef CONFIG_ADXL372_SPI - .spi_port = CONFIG_ADXL372_SPI_DEV_NAME, - .spi_slave = CONFIG_ADXL372_SPI_DEV_SLAVE, - .spi_max_frequency = CONFIG_ADXL372_SPI_BUS_FREQ, + .spi_port = DT_ADXL372_SPI_DEV_NAME, + .spi_slave = DT_ADXL372_SPI_DEV_SLAVE, + .spi_max_frequency = DT_ADXL372_SPI_BUS_FREQ, #ifdef CONFIG_ADXL372_SPI_GPIO_CS .gpio_cs_port = CONFIG_ADXL372_SPI_GPIO_CS_DRV_NAME, .cs_gpio = CONFIG_ADXL372_SPI_GPIO_CS_PIN, #endif #endif #ifdef CONFIG_ADXL372_TRIGGER - .gpio_port = CONFIG_ADXL372_GPIO_DEV_NAME, - .int_gpio = CONFIG_ADXL372_GPIO_PIN_NUM, + .gpio_port = DT_ADXL372_GPIO_DEV_NAME, + .int_gpio = DT_ADXL372_GPIO_PIN_NUM, #endif .max_peak_detect_mode = IS_ENABLED(CONFIG_ADXL372_PEAK_DETECT_MODE), @@ -1011,6 +1011,6 @@ static const struct adxl372_dev_config adxl372_config = { .op_mode = ADXL372_FULL_BW_MEASUREMENT, }; -DEVICE_AND_API_INIT(adxl372, CONFIG_ADXL372_DEV_NAME, adxl372_init, +DEVICE_AND_API_INIT(adxl372, DT_ADXL372_DEV_NAME, adxl372_init, &adxl372_data, &adxl372_config, POST_KERNEL, CONFIG_SENSOR_INIT_PRIORITY, &adxl372_api_funcs); diff --git a/drivers/sensor/apds9960/apds9960.c b/drivers/sensor/apds9960/apds9960.c index 6ecb3854b06..60005fa7c61 100644 --- a/drivers/sensor/apds9960/apds9960.c +++ b/drivers/sensor/apds9960/apds9960.c @@ -30,7 +30,7 @@ static void apds9960_gpio_callback(struct device *dev, struct apds9960_data *drv_data = CONTAINER_OF(cb, struct apds9960_data, gpio_cb); - gpio_pin_disable_callback(dev, CONFIG_APDS9960_GPIO_PIN_NUM); + gpio_pin_disable_callback(dev, DT_APDS9960_GPIO_PIN_NUM); #ifdef CONFIG_APDS9960_TRIGGER k_work_submit(&drv_data->work); @@ -51,7 +51,7 @@ static int apds9960_sample_fetch(struct device *dev, enum sensor_channel chan) #ifndef CONFIG_APDS9960_TRIGGER gpio_pin_enable_callback(data->gpio, - CONFIG_APDS9960_GPIO_PIN_NUM); + DT_APDS9960_GPIO_PIN_NUM); if (i2c_reg_update_byte(data->i2c, APDS9960_I2C_ADDRESS, APDS9960_ENABLE_REG, @@ -335,21 +335,21 @@ static int apds9960_init_interrupt(struct device *dev) struct apds9960_data *drv_data = dev->driver_data; /* setup gpio interrupt */ - drv_data->gpio = device_get_binding(CONFIG_APDS9960_GPIO_DEV_NAME); + drv_data->gpio = device_get_binding(DT_APDS9960_GPIO_DEV_NAME); if (drv_data->gpio == NULL) { LOG_ERR("Failed to get pointer to %s device!", - CONFIG_APDS9960_GPIO_DEV_NAME); + DT_APDS9960_GPIO_DEV_NAME); return -EINVAL; } - gpio_pin_configure(drv_data->gpio, CONFIG_APDS9960_GPIO_PIN_NUM, + gpio_pin_configure(drv_data->gpio, DT_APDS9960_GPIO_PIN_NUM, GPIO_DIR_IN | GPIO_INT | GPIO_INT_EDGE | GPIO_INT_ACTIVE_LOW | GPIO_INT_DEBOUNCE | GPIO_PUD_PULL_UP); gpio_init_callback(&drv_data->gpio_cb, apds9960_gpio_callback, - BIT(CONFIG_APDS9960_GPIO_PIN_NUM)); + BIT(DT_APDS9960_GPIO_PIN_NUM)); if (gpio_add_callback(drv_data->gpio, &drv_data->gpio_cb) < 0) { LOG_DBG("Failed to set gpio callback!"); @@ -420,11 +420,11 @@ static int apds9960_init(struct device *dev) /* Initialize time 5.7ms */ k_sleep(6); - data->i2c = device_get_binding(CONFIG_APDS9960_I2C_DEV_NAME); + data->i2c = device_get_binding(DT_APDS9960_I2C_DEV_NAME); if (data->i2c == NULL) { LOG_ERR("Failed to get pointer to %s device!", - CONFIG_APDS9960_I2C_DEV_NAME); + DT_APDS9960_I2C_DEV_NAME); return -EINVAL; } @@ -453,11 +453,11 @@ static const struct sensor_driver_api apds9960_driver_api = { static struct apds9960_data apds9960_data; #ifndef CONFIG_DEVICE_POWER_MANAGEMENT -DEVICE_AND_API_INIT(apds9960, CONFIG_APDS9960_DRV_NAME, &apds9960_init, +DEVICE_AND_API_INIT(apds9960, DT_APDS9960_DRV_NAME, &apds9960_init, &apds9960_data, NULL, POST_KERNEL, CONFIG_SENSOR_INIT_PRIORITY, &apds9960_driver_api); #else -DEVICE_DEFINE(apds9960, CONFIG_APDS9960_DRV_NAME, apds9960_init, +DEVICE_DEFINE(apds9960, DT_APDS9960_DRV_NAME, apds9960_init, apds9960_device_ctrl, &apds9960_data, NULL, POST_KERNEL, CONFIG_SENSOR_INIT_PRIORITY, &apds9960_driver_api); #endif diff --git a/drivers/sensor/apds9960/apds9960_trigger.c b/drivers/sensor/apds9960/apds9960_trigger.c index 90cc6424f06..76e9b986272 100644 --- a/drivers/sensor/apds9960/apds9960_trigger.c +++ b/drivers/sensor/apds9960/apds9960_trigger.c @@ -29,7 +29,7 @@ void apds9960_work_cb(struct k_work *work) data->p_th_handler(dev, &data->p_th_trigger); } - gpio_pin_enable_callback(data->gpio, CONFIG_APDS9960_GPIO_PIN_NUM); + gpio_pin_enable_callback(data->gpio, DT_APDS9960_GPIO_PIN_NUM); } int apds9960_attr_set(struct device *dev, @@ -71,7 +71,7 @@ int apds9960_trigger_set(struct device *dev, { struct apds9960_data *data = dev->driver_data; - gpio_pin_disable_callback(data->gpio, CONFIG_APDS9960_GPIO_PIN_NUM); + gpio_pin_disable_callback(data->gpio, DT_APDS9960_GPIO_PIN_NUM); switch (trig->type) { case SENSOR_TRIG_THRESHOLD: @@ -93,7 +93,7 @@ int apds9960_trigger_set(struct device *dev, return -ENOTSUP; } - gpio_pin_enable_callback(data->gpio, CONFIG_APDS9960_GPIO_PIN_NUM); + gpio_pin_enable_callback(data->gpio, DT_APDS9960_GPIO_PIN_NUM); return 0; } diff --git a/drivers/sensor/bmi160/bmi160.c b/drivers/sensor/bmi160/bmi160.c index 71c281d80a5..885041de8cf 100644 --- a/drivers/sensor/bmi160/bmi160.c +++ b/drivers/sensor/bmi160/bmi160.c @@ -796,16 +796,16 @@ int bmi160_init(struct device *dev) u8_t val = 0; s32_t acc_range, gyr_range; - bmi160->spi = device_get_binding(CONFIG_BMI160_SPI_PORT_NAME); + bmi160->spi = device_get_binding(DT_BMI160_SPI_PORT_NAME); if (!bmi160->spi) { LOG_DBG("SPI master controller not found: %s.", - CONFIG_BMI160_SPI_PORT_NAME); + DT_BMI160_SPI_PORT_NAME); return -EINVAL; } bmi160->spi_cfg.operation = SPI_WORD_SET(8); - bmi160->spi_cfg.frequency = CONFIG_BMI160_SPI_BUS_FREQ; - bmi160->spi_cfg.slave = CONFIG_BMI160_SLAVE; + bmi160->spi_cfg.frequency = DT_BMI160_SPI_BUS_FREQ; + bmi160->spi_cfg.slave = DT_BMI160_SLAVE; /* reboot the chip */ if (bmi160_byte_write(dev, BMI160_REG_CMD, BMI160_CMD_SOFT_RESET) < 0) { @@ -902,12 +902,12 @@ int bmi160_init(struct device *dev) const struct bmi160_device_config bmi160_config = { #if defined(CONFIG_BMI160_TRIGGER) - .gpio_port = CONFIG_BMI160_GPIO_DEV_NAME, - .int_pin = CONFIG_BMI160_GPIO_PIN_NUM, + .gpio_port = DT_BMI160_GPIO_DEV_NAME, + .int_pin = DT_BMI160_GPIO_PIN_NUM, #endif }; -DEVICE_INIT(bmi160, CONFIG_BMI160_NAME, bmi160_init, &bmi160_data, +DEVICE_INIT(bmi160, DT_BMI160_NAME, bmi160_init, &bmi160_data, &bmi160_config, POST_KERNEL, CONFIG_SENSOR_INIT_PRIORITY); diff --git a/drivers/sensor/ccs811/ccs811.c b/drivers/sensor/ccs811/ccs811.c index ef7dd92080d..d2f480e0ca8 100644 --- a/drivers/sensor/ccs811/ccs811.c +++ b/drivers/sensor/ccs811/ccs811.c @@ -28,7 +28,7 @@ static int ccs811_sample_fetch(struct device *dev, enum sensor_channel chan) /* Check data ready flag for the measurement interval of 1 seconds */ while (tries-- > 0) { - if (i2c_reg_read_byte(drv_data->i2c, CONFIG_CCS811_I2C_ADDR, + if (i2c_reg_read_byte(drv_data->i2c, DT_CCS811_I2C_ADDR, CCS811_REG_STATUS, &status) < 0) { LOG_ERR("Failed to read Status register"); return -EIO; @@ -46,7 +46,7 @@ static int ccs811_sample_fetch(struct device *dev, enum sensor_channel chan) return -EIO; } - if (i2c_burst_read(drv_data->i2c, CONFIG_CCS811_I2C_ADDR, + if (i2c_burst_read(drv_data->i2c, DT_CCS811_I2C_ADDR, CCS811_REG_ALG_RESULT_DATA, (u8_t *)buf, 8) < 0) { LOG_ERR("Failed to read conversion data."); return -EIO; @@ -117,7 +117,7 @@ static int switch_to_app_mode(struct device *i2c) LOG_DBG("Switching to Application mode..."); - if (i2c_reg_read_byte(i2c, CONFIG_CCS811_I2C_ADDR, + if (i2c_reg_read_byte(i2c, DT_CCS811_I2C_ADDR, CCS811_REG_STATUS, &status) < 0) { LOG_ERR("Failed to read Status register"); return -EIO; @@ -131,12 +131,12 @@ static int switch_to_app_mode(struct device *i2c) buf = CCS811_REG_APP_START; /* Set the device to application mode */ - if (i2c_write(i2c, &buf, 1, CONFIG_CCS811_I2C_ADDR) < 0) { + if (i2c_write(i2c, &buf, 1, DT_CCS811_I2C_ADDR) < 0) { LOG_ERR("Failed to set Application mode"); return -EIO; } - if (i2c_reg_read_byte(i2c, CONFIG_CCS811_I2C_ADDR, + if (i2c_reg_read_byte(i2c, DT_CCS811_I2C_ADDR, CCS811_REG_STATUS, &status) < 0) { LOG_ERR("Failed to read Status register"); return -EIO; @@ -159,10 +159,10 @@ int ccs811_init(struct device *dev) int ret; u8_t hw_id, status; - drv_data->i2c = device_get_binding(CONFIG_CCS811_I2C_MASTER_DEV_NAME); + drv_data->i2c = device_get_binding(DT_CCS811_I2C_MASTER_DEV_NAME); if (drv_data->i2c == NULL) { LOG_ERR("Failed to get pointer to %s device!", - CONFIG_CCS811_I2C_MASTER_DEV_NAME); + DT_CCS811_I2C_MASTER_DEV_NAME); return -EINVAL; } @@ -202,7 +202,7 @@ int ccs811_init(struct device *dev) } /* Check Hardware ID */ - if (i2c_reg_read_byte(drv_data->i2c, CONFIG_CCS811_I2C_ADDR, + if (i2c_reg_read_byte(drv_data->i2c, DT_CCS811_I2C_ADDR, CCS811_REG_HW_ID, &hw_id) < 0) { LOG_ERR("Failed to read Hardware ID register"); return -EIO; @@ -214,7 +214,7 @@ int ccs811_init(struct device *dev) } /* Set Measurement mode for 1 second */ - if (i2c_reg_write_byte(drv_data->i2c, CONFIG_CCS811_I2C_ADDR, + if (i2c_reg_write_byte(drv_data->i2c, DT_CCS811_I2C_ADDR, CCS811_REG_MEAS_MODE, CCS811_MODE_IAQ_1SEC) < 0) { LOG_ERR("Failed to set Measurement mode"); @@ -222,7 +222,7 @@ int ccs811_init(struct device *dev) } /* Check for error */ - if (i2c_reg_read_byte(drv_data->i2c, CONFIG_CCS811_I2C_ADDR, + if (i2c_reg_read_byte(drv_data->i2c, DT_CCS811_I2C_ADDR, CCS811_REG_STATUS, &status) < 0) { LOG_ERR("Failed to read Status register"); return -EIO; @@ -238,6 +238,6 @@ int ccs811_init(struct device *dev) static struct ccs811_data ccs811_driver; -DEVICE_AND_API_INIT(ccs811, CONFIG_CCS811_NAME, ccs811_init, &ccs811_driver, +DEVICE_AND_API_INIT(ccs811, DT_CCS811_NAME, ccs811_init, &ccs811_driver, NULL, POST_KERNEL, CONFIG_SENSOR_INIT_PRIORITY, &ccs811_driver_api); diff --git a/drivers/sensor/fxas21002/fxas21002.c b/drivers/sensor/fxas21002/fxas21002.c index 5f3369275cc..a511702c5eb 100644 --- a/drivers/sensor/fxas21002/fxas21002.c +++ b/drivers/sensor/fxas21002/fxas21002.c @@ -285,20 +285,20 @@ static const struct sensor_driver_api fxas21002_driver_api = { }; static const struct fxas21002_config fxas21002_config = { - .i2c_name = CONFIG_FXAS21002_I2C_NAME, - .i2c_address = CONFIG_FXAS21002_I2C_ADDRESS, + .i2c_name = DT_FXAS21002_I2C_NAME, + .i2c_address = DT_FXAS21002_I2C_ADDRESS, .whoami = CONFIG_FXAS21002_WHOAMI, .range = CONFIG_FXAS21002_RANGE, .dr = CONFIG_FXAS21002_DR, #ifdef CONFIG_FXAS21002_TRIGGER - .gpio_name = CONFIG_FXAS21002_GPIO_NAME, - .gpio_pin = CONFIG_FXAS21002_GPIO_PIN, + .gpio_name = DT_FXAS21002_GPIO_NAME, + .gpio_pin = DT_FXAS21002_GPIO_PIN, #endif }; static struct fxas21002_data fxas21002_data; -DEVICE_AND_API_INIT(fxas21002, CONFIG_FXAS21002_NAME, fxas21002_init, +DEVICE_AND_API_INIT(fxas21002, DT_FXAS21002_NAME, fxas21002_init, &fxas21002_data, &fxas21002_config, POST_KERNEL, CONFIG_SENSOR_INIT_PRIORITY, &fxas21002_driver_api); diff --git a/drivers/sensor/fxos8700/fxos8700.c b/drivers/sensor/fxos8700/fxos8700.c index 599ca8f394f..f3b6aadc231 100644 --- a/drivers/sensor/fxos8700/fxos8700.c +++ b/drivers/sensor/fxos8700/fxos8700.c @@ -496,8 +496,8 @@ static const struct sensor_driver_api fxos8700_driver_api = { }; static const struct fxos8700_config fxos8700_config = { - .i2c_name = CONFIG_FXOS8700_I2C_NAME, - .i2c_address = CONFIG_FXOS8700_I2C_ADDRESS, + .i2c_name = DT_FXOS8700_I2C_NAME, + .i2c_address = DT_FXOS8700_I2C_ADDRESS, #ifdef CONFIG_FXOS8700_MODE_ACCEL .mode = FXOS8700_MODE_ACCEL, .start_addr = FXOS8700_REG_OUTXMSB, @@ -531,8 +531,8 @@ static const struct fxos8700_config fxos8700_config = { .range = FXOS8700_RANGE_2G, #endif #ifdef CONFIG_FXOS8700_TRIGGER - .gpio_name = CONFIG_FXOS8700_GPIO_NAME, - .gpio_pin = CONFIG_FXOS8700_GPIO_PIN, + .gpio_name = DT_FXOS8700_GPIO_NAME, + .gpio_pin = DT_FXOS8700_GPIO_PIN, #endif #ifdef CONFIG_FXOS8700_PULSE .pulse_cfg = CONFIG_FXOS8700_PULSE_CFG, @@ -547,7 +547,7 @@ static const struct fxos8700_config fxos8700_config = { static struct fxos8700_data fxos8700_data; -DEVICE_AND_API_INIT(fxos8700, CONFIG_FXOS8700_NAME, fxos8700_init, +DEVICE_AND_API_INIT(fxos8700, DT_FXOS8700_NAME, fxos8700_init, &fxos8700_data, &fxos8700_config, POST_KERNEL, CONFIG_SENSOR_INIT_PRIORITY, &fxos8700_driver_api); diff --git a/drivers/sensor/hdc1008/hdc1008.c b/drivers/sensor/hdc1008/hdc1008.c index 753b6e274f3..4e3a5261401 100644 --- a/drivers/sensor/hdc1008/hdc1008.c +++ b/drivers/sensor/hdc1008/hdc1008.c @@ -26,7 +26,7 @@ static void hdc1008_gpio_callback(struct device *dev, ARG_UNUSED(pins); - gpio_pin_disable_callback(dev, CONFIG_HDC1008_GPIO_PIN_NUM); + gpio_pin_disable_callback(dev, DT_HDC1008_GPIO_PIN_NUM); k_sem_give(&drv_data->data_sem); } @@ -37,17 +37,17 @@ static int hdc1008_sample_fetch(struct device *dev, enum sensor_channel chan) __ASSERT_NO_MSG(chan == SENSOR_CHAN_ALL); - gpio_pin_enable_callback(drv_data->gpio, CONFIG_HDC1008_GPIO_PIN_NUM); + gpio_pin_enable_callback(drv_data->gpio, DT_HDC1008_GPIO_PIN_NUM); buf[0] = HDC1008_REG_TEMP; - if (i2c_write(drv_data->i2c, buf, 1, CONFIG_HDC1008_I2C_ADDR) < 0) { + if (i2c_write(drv_data->i2c, buf, 1, DT_HDC1008_I2C_ADDR) < 0) { LOG_DBG("Failed to write address pointer"); return -EIO; } k_sem_take(&drv_data->data_sem, K_FOREVER); - if (i2c_read(drv_data->i2c, buf, 4, CONFIG_HDC1008_I2C_ADDR) < 0) { + if (i2c_read(drv_data->i2c, buf, 4, DT_HDC1008_I2C_ADDR) < 0) { LOG_DBG("Failed to read sample data"); return -EIO; } @@ -108,20 +108,20 @@ static int hdc1008_init(struct device *dev) { struct hdc1008_data *drv_data = dev->driver_data; - drv_data->i2c = device_get_binding(CONFIG_HDC1008_I2C_MASTER_DEV_NAME); + drv_data->i2c = device_get_binding(DT_HDC1008_I2C_MASTER_DEV_NAME); if (drv_data->i2c == NULL) { LOG_DBG("Failed to get pointer to %s device!", - CONFIG_HDC1008_I2C_MASTER_DEV_NAME); + DT_HDC1008_I2C_MASTER_DEV_NAME); return -EINVAL; } - if (read16(drv_data->i2c, CONFIG_HDC1008_I2C_ADDR, HDC1000_MANUFID) + if (read16(drv_data->i2c, DT_HDC1008_I2C_ADDR, HDC1000_MANUFID) != 0x5449) { LOG_ERR("Failed to get correct manufacturer ID"); return -EINVAL; } - if (read16(drv_data->i2c, CONFIG_HDC1008_I2C_ADDR, HDC1000_DEVICEID) + if (read16(drv_data->i2c, DT_HDC1008_I2C_ADDR, HDC1000_DEVICEID) != 0x1000) { LOG_ERR("Failed to get correct device ID"); return -EINVAL; @@ -130,23 +130,23 @@ static int hdc1008_init(struct device *dev) k_sem_init(&drv_data->data_sem, 0, UINT_MAX); /* setup data ready gpio interrupt */ - drv_data->gpio = device_get_binding(CONFIG_HDC1008_GPIO_DEV_NAME); + drv_data->gpio = device_get_binding(DT_HDC1008_GPIO_DEV_NAME); if (drv_data->gpio == NULL) { LOG_DBG("Failed to get pointer to %s device", - CONFIG_HDC1008_GPIO_DEV_NAME); + DT_HDC1008_GPIO_DEV_NAME); return -EINVAL; } - gpio_pin_configure(drv_data->gpio, CONFIG_HDC1008_GPIO_PIN_NUM, + gpio_pin_configure(drv_data->gpio, DT_HDC1008_GPIO_PIN_NUM, GPIO_DIR_IN | GPIO_INT | GPIO_INT_EDGE | -#if defined(CONFIG_HDC1008_GPIO_FLAGS) - CONFIG_HDC1008_GPIO_FLAGS | +#if defined(DT_HDC1008_GPIO_FLAGS) + DT_HDC1008_GPIO_FLAGS | #endif GPIO_INT_ACTIVE_LOW | GPIO_INT_DEBOUNCE); gpio_init_callback(&drv_data->gpio_cb, hdc1008_gpio_callback, - BIT(CONFIG_HDC1008_GPIO_PIN_NUM)); + BIT(DT_HDC1008_GPIO_PIN_NUM)); if (gpio_add_callback(drv_data->gpio, &drv_data->gpio_cb) < 0) { LOG_DBG("Failed to set GPIO callback"); @@ -158,6 +158,6 @@ static int hdc1008_init(struct device *dev) static struct hdc1008_data hdc1008_data; -DEVICE_AND_API_INIT(hdc1008, CONFIG_HDC1008_NAME, hdc1008_init, &hdc1008_data, +DEVICE_AND_API_INIT(hdc1008, DT_HDC1008_NAME, hdc1008_init, &hdc1008_data, NULL, POST_KERNEL, CONFIG_SENSOR_INIT_PRIORITY, &hdc1008_driver_api); diff --git a/drivers/sensor/hts221/hts221.c b/drivers/sensor/hts221/hts221.c index 672ead700c8..73b3792bf75 100644 --- a/drivers/sensor/hts221/hts221.c +++ b/drivers/sensor/hts221/hts221.c @@ -111,10 +111,10 @@ int hts221_init(struct device *dev) struct hts221_data *drv_data = dev->driver_data; u8_t id, idx; - drv_data->i2c = device_get_binding(CONFIG_HTS221_I2C_MASTER_DEV_NAME); + drv_data->i2c = device_get_binding(DT_HTS221_I2C_MASTER_DEV_NAME); if (drv_data->i2c == NULL) { LOG_ERR("Could not get pointer to %s device.", - CONFIG_HTS221_I2C_MASTER_DEV_NAME); + DT_HTS221_I2C_MASTER_DEV_NAME); return -EINVAL; } @@ -172,6 +172,6 @@ int hts221_init(struct device *dev) struct hts221_data hts221_driver; -DEVICE_AND_API_INIT(hts221, CONFIG_HTS221_NAME, hts221_init, &hts221_driver, +DEVICE_AND_API_INIT(hts221, DT_HTS221_NAME, hts221_init, &hts221_driver, NULL, POST_KERNEL, CONFIG_SENSOR_INIT_PRIORITY, &hts221_driver_api); diff --git a/drivers/sensor/lis3mdl/lis3mdl.c b/drivers/sensor/lis3mdl/lis3mdl.c index 227c3e86afe..677952d4685 100644 --- a/drivers/sensor/lis3mdl/lis3mdl.c +++ b/drivers/sensor/lis3mdl/lis3mdl.c @@ -65,7 +65,7 @@ int lis3mdl_sample_fetch(struct device *dev, enum sensor_channel chan) __ASSERT_NO_MSG(chan == SENSOR_CHAN_ALL); /* fetch magnetometer sample */ - if (i2c_burst_read(drv_data->i2c, CONFIG_LIS3MDL_I2C_ADDR, + if (i2c_burst_read(drv_data->i2c, DT_LIS3MDL_I2C_ADDR, LIS3MDL_REG_SAMPLE_START, (u8_t *)buf, 8) < 0) { LOG_DBG("Failed to fetch megnetometer sample."); return -EIO; @@ -76,7 +76,7 @@ int lis3mdl_sample_fetch(struct device *dev, enum sensor_channel chan) * the same read as magnetometer data, so do another * burst read to fetch the temperature sample */ - if (i2c_burst_read(drv_data->i2c, CONFIG_LIS3MDL_I2C_ADDR, + if (i2c_burst_read(drv_data->i2c, DT_LIS3MDL_I2C_ADDR, LIS3MDL_REG_SAMPLE_START + 6, (u8_t *)(buf + 3), 2) < 0) { LOG_DBG("Failed to fetch temperature sample."); @@ -105,16 +105,16 @@ int lis3mdl_init(struct device *dev) u8_t chip_cfg[6]; u8_t id, idx; - drv_data->i2c = device_get_binding(CONFIG_LIS3MDL_I2C_MASTER_DEV_NAME); + drv_data->i2c = device_get_binding(DT_LIS3MDL_I2C_MASTER_DEV_NAME); if (drv_data->i2c == NULL) { LOG_ERR("Could not get pointer to %s device.", - CONFIG_LIS3MDL_I2C_MASTER_DEV_NAME); + DT_LIS3MDL_I2C_MASTER_DEV_NAME); return -EINVAL; } /* check chip ID */ - if (i2c_reg_read_byte(drv_data->i2c, CONFIG_LIS3MDL_I2C_ADDR, + if (i2c_reg_read_byte(drv_data->i2c, DT_LIS3MDL_I2C_ADDR, LIS3MDL_REG_WHO_AM_I, &id) < 0) { LOG_ERR("Failed to read chip ID."); return -EIO; @@ -148,7 +148,7 @@ int lis3mdl_init(struct device *dev) chip_cfg[5] = LIS3MDL_BDU_EN; if (i2c_write(drv_data->i2c, - chip_cfg, 6, CONFIG_LIS3MDL_I2C_ADDR) < 0) { + chip_cfg, 6, DT_LIS3MDL_I2C_ADDR) < 0) { LOG_DBG("Failed to configure chip."); return -EIO; } @@ -167,5 +167,5 @@ int lis3mdl_init(struct device *dev) struct lis3mdl_data lis3mdl_driver; -DEVICE_INIT(lis3mdl, CONFIG_LIS3MDL_NAME, lis3mdl_init, &lis3mdl_driver, +DEVICE_INIT(lis3mdl, DT_LIS3MDL_NAME, lis3mdl_init, &lis3mdl_driver, NULL, POST_KERNEL, CONFIG_SENSOR_INIT_PRIORITY); diff --git a/drivers/sensor/lis3mdl/lis3mdl.h b/drivers/sensor/lis3mdl/lis3mdl.h index 1e423b07121..4815e59ba00 100644 --- a/drivers/sensor/lis3mdl/lis3mdl.h +++ b/drivers/sensor/lis3mdl/lis3mdl.h @@ -16,8 +16,8 @@ #define LIS3MDL_I2C_ADDR_MASK (~BIT(1)) /* guard against invalid CONFIG_I2C_ADDR values */ -#if (CONFIG_LIS3MDL_I2C_ADDR & LIS3MDL_I2C_ADDR_MASK) != LIS3MDL_I2C_ADDR_BASE -#error "Invalid value for CONFIG_LIS3MDL_I2C_ADDR" +#if (DT_LIS3MDL_I2C_ADDR & LIS3MDL_I2C_ADDR_MASK) != LIS3MDL_I2C_ADDR_BASE +#error "Invalid value for DT_LIS3MDL_I2C_ADDR" #endif #define LIS3MDL_REG_WHO_AM_I 0x0F diff --git a/drivers/sensor/lis3mdl/lis3mdl_trigger.c b/drivers/sensor/lis3mdl/lis3mdl_trigger.c index ee9f88f9835..356fcd70649 100644 --- a/drivers/sensor/lis3mdl/lis3mdl_trigger.c +++ b/drivers/sensor/lis3mdl/lis3mdl_trigger.c @@ -126,7 +126,7 @@ int lis3mdl_init_interrupt(struct device *dev) } /* enable interrupt */ - if (i2c_reg_write_byte(drv_data->i2c, CONFIG_LIS3MDL_I2C_ADDR, + if (i2c_reg_write_byte(drv_data->i2c, DT_LIS3MDL_I2C_ADDR, LIS3MDL_REG_INT_CFG, LIS3MDL_INT_XYZ_EN) < 0) { LOG_DBG("Could not enable interrupt."); return -EIO; diff --git a/drivers/sensor/lps22hb/lps22hb.c b/drivers/sensor/lps22hb/lps22hb.c index 09153689dbc..ef1603c0d2e 100644 --- a/drivers/sensor/lps22hb/lps22hb.c +++ b/drivers/sensor/lps22hb/lps22hb.c @@ -152,12 +152,12 @@ static int lps22hb_init(struct device *dev) } static const struct lps22hb_config lps22hb_config = { - .i2c_master_dev_name = CONFIG_LPS22HB_I2C_MASTER_DEV_NAME, - .i2c_slave_addr = CONFIG_LPS22HB_I2C_ADDR, + .i2c_master_dev_name = DT_LPS22HB_I2C_MASTER_DEV_NAME, + .i2c_slave_addr = DT_LPS22HB_I2C_ADDR, }; static struct lps22hb_data lps22hb_data; -DEVICE_AND_API_INIT(lps22hb, CONFIG_LPS22HB_DEV_NAME, lps22hb_init, +DEVICE_AND_API_INIT(lps22hb, DT_LPS22HB_DEV_NAME, lps22hb_init, &lps22hb_data, &lps22hb_config, POST_KERNEL, CONFIG_SENSOR_INIT_PRIORITY, &lps22hb_api_funcs); diff --git a/drivers/sensor/lps25hb/lps25hb.c b/drivers/sensor/lps25hb/lps25hb.c index 98cdaaea2e8..6d423a02d33 100644 --- a/drivers/sensor/lps25hb/lps25hb.c +++ b/drivers/sensor/lps25hb/lps25hb.c @@ -180,12 +180,12 @@ static int lps25hb_init(struct device *dev) } static const struct lps25hb_config lps25hb_config = { - .i2c_master_dev_name = CONFIG_LPS25HB_I2C_MASTER_DEV_NAME, - .i2c_slave_addr = CONFIG_LPS25HB_I2C_ADDR, + .i2c_master_dev_name = DT_LPS25HB_I2C_MASTER_DEV_NAME, + .i2c_slave_addr = DT_LPS25HB_I2C_ADDR, }; static struct lps25hb_data lps25hb_data; -DEVICE_AND_API_INIT(lps25hb, CONFIG_LPS25HB_DEV_NAME, lps25hb_init, +DEVICE_AND_API_INIT(lps25hb, DT_LPS25HB_DEV_NAME, lps25hb_init, &lps25hb_data, &lps25hb_config, POST_KERNEL, CONFIG_SENSOR_INIT_PRIORITY, &lps25hb_api_funcs); diff --git a/drivers/sensor/lsm303dlhc_accel/lsm303dlhc_accel.c b/drivers/sensor/lsm303dlhc_accel/lsm303dlhc_accel.c index 347e5dd7343..1ab1cd30a45 100644 --- a/drivers/sensor/lsm303dlhc_accel/lsm303dlhc_accel.c +++ b/drivers/sensor/lsm303dlhc_accel/lsm303dlhc_accel.c @@ -183,13 +183,13 @@ static int lsm303dlhc_accel_init(struct device *dev) } static const struct lsm303dlhc_accel_config lsm303dlhc_accel_config = { - .i2c_name = CONFIG_LSM303DLHC_ACCEL_I2C_MASTER_DEV, - .i2c_address = CONFIG_LSM303DLHC_ACCEL_I2C_ADDR, + .i2c_name = DT_LSM303DLHC_ACCEL_I2C_MASTER_DEV, + .i2c_address = DT_LSM303DLHC_ACCEL_I2C_ADDR, }; static struct lsm303dlhc_accel_data lsm303dlhc_accel_driver; -DEVICE_AND_API_INIT(lsm303dlhc_accel, CONFIG_LSM303DLHC_ACCEL_NAME, +DEVICE_AND_API_INIT(lsm303dlhc_accel, DT_LSM303DLHC_ACCEL_NAME, lsm303dlhc_accel_init, &lsm303dlhc_accel_driver, &lsm303dlhc_accel_config, POST_KERNEL, CONFIG_SENSOR_INIT_PRIORITY, &lsm303dlhc_accel_driver_api); diff --git a/drivers/sensor/lsm303dlhc_magn/lsm303dlhc_magn.c b/drivers/sensor/lsm303dlhc_magn/lsm303dlhc_magn.c index d575a5d9321..5ede98d5c55 100644 --- a/drivers/sensor/lsm303dlhc_magn/lsm303dlhc_magn.c +++ b/drivers/sensor/lsm303dlhc_magn/lsm303dlhc_magn.c @@ -132,13 +132,13 @@ static int lsm303dlhc_magn_init(struct device *dev) } static const struct lsm303dlhc_magn_config lsm303dlhc_magn_config = { - .i2c_name = CONFIG_LSM303DLHC_MAGN_I2C_MASTER_DEV, - .i2c_address = CONFIG_LSM303DLHC_MAGN_I2C_ADDR, + .i2c_name = DT_LSM303DLHC_MAGN_I2C_MASTER_DEV, + .i2c_address = DT_LSM303DLHC_MAGN_I2C_ADDR, }; static struct lsm303dlhc_magn_data lsm303dlhc_magn_driver; -DEVICE_AND_API_INIT(lsm303dlhc_magn, CONFIG_LSM303DLHC_MAGN_NAME, +DEVICE_AND_API_INIT(lsm303dlhc_magn, DT_LSM303DLHC_MAGN_NAME, lsm303dlhc_magn_init, &lsm303dlhc_magn_driver, &lsm303dlhc_magn_config, POST_KERNEL, CONFIG_SENSOR_INIT_PRIORITY, &lsm303dlhc_magn_driver_api); diff --git a/drivers/sensor/lsm6ds0/lsm6ds0.c b/drivers/sensor/lsm6ds0/lsm6ds0.c index 4b9a7f9859c..f5a7b43eba5 100644 --- a/drivers/sensor/lsm6ds0/lsm6ds0.c +++ b/drivers/sensor/lsm6ds0/lsm6ds0.c @@ -500,12 +500,12 @@ static int lsm6ds0_init(struct device *dev) } static const struct lsm6ds0_config lsm6ds0_config = { - .i2c_master_dev_name = CONFIG_LSM6DS0_I2C_MASTER_DEV_NAME, - .i2c_slave_addr = CONFIG_LSM6DS0_I2C_ADDR, + .i2c_master_dev_name = DT_LSM6DS0_I2C_MASTER_DEV_NAME, + .i2c_slave_addr = DT_LSM6DS0_I2C_ADDR, }; static struct lsm6ds0_data lsm6ds0_data; -DEVICE_AND_API_INIT(lsm6ds0, CONFIG_LSM6DS0_DEV_NAME, lsm6ds0_init, +DEVICE_AND_API_INIT(lsm6ds0, DT_LSM6DS0_DEV_NAME, lsm6ds0_init, &lsm6ds0_data, &lsm6ds0_config, POST_KERNEL, CONFIG_SENSOR_INIT_PRIORITY, &lsm6ds0_api_funcs); diff --git a/drivers/sensor/lsm6dsl/lsm6dsl.c b/drivers/sensor/lsm6dsl/lsm6dsl.c index 8a71f516016..9b27fd4c95d 100644 --- a/drivers/sensor/lsm6dsl/lsm6dsl.c +++ b/drivers/sensor/lsm6dsl/lsm6dsl.c @@ -774,9 +774,9 @@ static int lsm6dsl_init_chip(struct device *dev) static struct lsm6dsl_config lsm6dsl_config = { #ifdef CONFIG_LSM6DSL_SPI - .comm_master_dev_name = CONFIG_LSM6DSL_SPI_MASTER_DEV_NAME, + .comm_master_dev_name = DT_LSM6DSL_SPI_MASTER_DEV_NAME, #else - .comm_master_dev_name = CONFIG_LSM6DSL_I2C_MASTER_DEV_NAME, + .comm_master_dev_name = DT_LSM6DSL_I2C_MASTER_DEV_NAME, #endif }; @@ -823,6 +823,6 @@ static int lsm6dsl_init(struct device *dev) static struct lsm6dsl_data lsm6dsl_data; -DEVICE_AND_API_INIT(lsm6dsl, CONFIG_LSM6DSL_DEV_NAME, lsm6dsl_init, +DEVICE_AND_API_INIT(lsm6dsl, DT_LSM6DSL_DEV_NAME, lsm6dsl_init, &lsm6dsl_data, &lsm6dsl_config, POST_KERNEL, CONFIG_SENSOR_INIT_PRIORITY, &lsm6dsl_api_funcs); diff --git a/drivers/sensor/lsm6dsl/lsm6dsl_i2c.c b/drivers/sensor/lsm6dsl/lsm6dsl_i2c.c index a23b7e2e679..25ac3e8339d 100644 --- a/drivers/sensor/lsm6dsl/lsm6dsl_i2c.c +++ b/drivers/sensor/lsm6dsl/lsm6dsl_i2c.c @@ -13,7 +13,7 @@ #include "lsm6dsl.h" -static u16_t lsm6dsl_i2c_slave_addr = CONFIG_LSM6DSL_I2C_ADDR; +static u16_t lsm6dsl_i2c_slave_addr = DT_LSM6DSL_I2C_ADDR; #define LOG_LEVEL CONFIG_SENSOR_LOG_LEVEL LOG_MODULE_DECLARE(LSM6DSL); diff --git a/drivers/sensor/lsm6dsl/lsm6dsl_spi.c b/drivers/sensor/lsm6dsl/lsm6dsl_spi.c index eba7143d2d2..540a63ee531 100644 --- a/drivers/sensor/lsm6dsl/lsm6dsl_spi.c +++ b/drivers/sensor/lsm6dsl/lsm6dsl_spi.c @@ -24,10 +24,10 @@ static struct spi_cs_control lsm6dsl_cs_ctrl; #define SPI_CS NULL static struct spi_config lsm6dsl_spi_conf = { - .frequency = CONFIG_LSM6DSL_SPI_BUS_FREQ, + .frequency = DT_LSM6DSL_SPI_BUS_FREQ, .operation = (SPI_OP_MODE_MASTER | SPI_MODE_CPOL | SPI_MODE_CPHA | SPI_WORD_SET(8) | SPI_LINES_SINGLE), - .slave = CONFIG_LSM6DSL_SPI_SELECT_SLAVE, + .slave = DT_LSM6DSL_SPI_SELECT_SLAVE, .cs = SPI_CS, }; diff --git a/drivers/sensor/lsm6dsl/lsm6dsl_trigger.c b/drivers/sensor/lsm6dsl/lsm6dsl_trigger.c index ebdb61cf9f5..4fbb0cd7633 100644 --- a/drivers/sensor/lsm6dsl/lsm6dsl_trigger.c +++ b/drivers/sensor/lsm6dsl/lsm6dsl_trigger.c @@ -25,7 +25,7 @@ int lsm6dsl_trigger_set(struct device *dev, __ASSERT_NO_MSG(trig->type == SENSOR_TRIG_DATA_READY); - gpio_pin_disable_callback(drv_data->gpio, CONFIG_LSM6DSL_GPIO_PIN_NUM); + gpio_pin_disable_callback(drv_data->gpio, DT_LSM6DSL_GPIO_PIN_NUM); drv_data->data_ready_handler = handler; if (handler == NULL) { @@ -34,7 +34,7 @@ int lsm6dsl_trigger_set(struct device *dev, drv_data->data_ready_trigger = *trig; - gpio_pin_enable_callback(drv_data->gpio, CONFIG_LSM6DSL_GPIO_PIN_NUM); + gpio_pin_enable_callback(drv_data->gpio, DT_LSM6DSL_GPIO_PIN_NUM); return 0; } @@ -47,7 +47,7 @@ static void lsm6dsl_gpio_callback(struct device *dev, ARG_UNUSED(pins); - gpio_pin_disable_callback(dev, CONFIG_LSM6DSL_GPIO_PIN_NUM); + gpio_pin_disable_callback(dev, DT_LSM6DSL_GPIO_PIN_NUM); #if defined(CONFIG_LSM6DSL_TRIGGER_OWN_THREAD) k_sem_give(&drv_data->gpio_sem); @@ -66,7 +66,7 @@ static void lsm6dsl_thread_cb(void *arg) &drv_data->data_ready_trigger); } - gpio_pin_enable_callback(drv_data->gpio, CONFIG_LSM6DSL_GPIO_PIN_NUM); + gpio_pin_enable_callback(drv_data->gpio, DT_LSM6DSL_GPIO_PIN_NUM); } #ifdef CONFIG_LSM6DSL_TRIGGER_OWN_THREAD @@ -99,20 +99,20 @@ int lsm6dsl_init_interrupt(struct device *dev) struct lsm6dsl_data *drv_data = dev->driver_data; /* setup data ready gpio interrupt */ - drv_data->gpio = device_get_binding(CONFIG_LSM6DSL_GPIO_DEV_NAME); + drv_data->gpio = device_get_binding(DT_LSM6DSL_GPIO_DEV_NAME); if (drv_data->gpio == NULL) { LOG_ERR("Cannot get pointer to %s device.", - CONFIG_LSM6DSL_GPIO_DEV_NAME); + DT_LSM6DSL_GPIO_DEV_NAME); return -EINVAL; } - gpio_pin_configure(drv_data->gpio, CONFIG_LSM6DSL_GPIO_PIN_NUM, + gpio_pin_configure(drv_data->gpio, DT_LSM6DSL_GPIO_PIN_NUM, GPIO_DIR_IN | GPIO_INT | GPIO_INT_EDGE | GPIO_INT_ACTIVE_HIGH | GPIO_INT_DEBOUNCE); gpio_init_callback(&drv_data->gpio_cb, lsm6dsl_gpio_callback, - BIT(CONFIG_LSM6DSL_GPIO_PIN_NUM)); + BIT(DT_LSM6DSL_GPIO_PIN_NUM)); if (gpio_add_callback(drv_data->gpio, &drv_data->gpio_cb) < 0) { LOG_ERR("Could not set gpio callback."); @@ -143,7 +143,7 @@ int lsm6dsl_init_interrupt(struct device *dev) drv_data->dev = dev; #endif - gpio_pin_enable_callback(drv_data->gpio, CONFIG_LSM6DSL_GPIO_PIN_NUM); + gpio_pin_enable_callback(drv_data->gpio, DT_LSM6DSL_GPIO_PIN_NUM); return 0; } diff --git a/drivers/sensor/max30101/max30101.c b/drivers/sensor/max30101/max30101.c index 89fa9ed7cf1..0d9df1909db 100644 --- a/drivers/sensor/max30101/max30101.c +++ b/drivers/sensor/max30101/max30101.c @@ -99,7 +99,7 @@ static int max30101_init(struct device *dev) int fifo_chan; /* Get the I2C device */ - data->i2c = device_get_binding(CONFIG_MAX30101_I2C_NAME); + data->i2c = device_get_binding(DT_MAX30101_I2C_NAME); if (!data->i2c) { LOG_ERR("Could not find I2C device"); return -EINVAL; @@ -242,7 +242,7 @@ static struct max30101_config max30101_config = { static struct max30101_data max30101_data; -DEVICE_AND_API_INIT(max30101, CONFIG_MAX30101_NAME, max30101_init, +DEVICE_AND_API_INIT(max30101, DT_MAX30101_NAME, max30101_init, &max30101_data, &max30101_config, POST_KERNEL, CONFIG_SENSOR_INIT_PRIORITY, &max30101_driver_api); diff --git a/drivers/sensor/ms5837/ms5837.c b/drivers/sensor/ms5837/ms5837.c index 02ca8bd2b4c..48f07cb6ea6 100644 --- a/drivers/sensor/ms5837/ms5837.c +++ b/drivers/sensor/ms5837/ms5837.c @@ -260,7 +260,7 @@ static int ms5837_init(struct device *dev) data->i2c_master = device_get_binding(cfg->i2c_name); if (data->i2c_master == NULL) { LOG_ERR("i2c master %s not found", - CONFIG_MS5837_I2C_MASTER_DEV_NAME); + DT_MS5837_I2C_MASTER_DEV_NAME); return -EINVAL; } @@ -318,10 +318,10 @@ static int ms5837_init(struct device *dev) static struct ms5837_data ms5837_data; static const struct ms5837_config ms5837_config = { - .i2c_name = CONFIG_MS5837_I2C_MASTER_DEV_NAME, + .i2c_name = DT_MS5837_I2C_MASTER_DEV_NAME, .i2c_address = MS5837_ADDR }; -DEVICE_AND_API_INIT(ms5837, CONFIG_MS5837_DEV_NAME, ms5837_init, &ms5837_data, +DEVICE_AND_API_INIT(ms5837, DT_MS5837_DEV_NAME, ms5837_init, &ms5837_data, &ms5837_config, POST_KERNEL, CONFIG_SENSOR_INIT_PRIORITY, &ms5837_api_funcs); diff --git a/drivers/sensor/qdec_nrfx/qdec_nrfx.c b/drivers/sensor/qdec_nrfx/qdec_nrfx.c index 4ea926cb77c..59ae526387d 100644 --- a/drivers/sensor/qdec_nrfx/qdec_nrfx.c +++ b/drivers/sensor/qdec_nrfx/qdec_nrfx.c @@ -91,14 +91,14 @@ static int qdec_nrfx_channel_get(struct device *dev, data->acc = 0; irq_unlock(key); - static_assert(CONFIG_QDEC_STEPS > 0, "only positive number valid"); - static_assert(CONFIG_QDEC_STEPS <= 2148, "overflow possible"); + static_assert(DT_QDEC_STEPS > 0, "only positive number valid"); + static_assert(DT_QDEC_STEPS <= 2148, "overflow possible"); - val->val1 = (acc * FULL_ANGLE) / CONFIG_QDEC_STEPS; - val->val2 = (acc * FULL_ANGLE) - (val->val1 * CONFIG_QDEC_STEPS); + val->val1 = (acc * FULL_ANGLE) / DT_QDEC_STEPS; + val->val2 = (acc * FULL_ANGLE) - (val->val1 * DT_QDEC_STEPS); if (val->val2 != 0) { val->val2 *= 1000000; - val->val2 /= CONFIG_QDEC_STEPS; + val->val2 /= DT_QDEC_STEPS; } return 0; @@ -161,11 +161,11 @@ static void qdec_nrfx_event_handler(nrfx_qdec_event_t event) static void qdec_nrfx_gpio_ctrl(bool enable) { -#if defined(CONFIG_QDEC_ENABLE_PIN) +#if defined(DT_QDEC_ENABLE_PIN) uint32_t val = (enable)?(0):(1); - nrf_gpio_pin_write(CONFIG_QDEC_ENABLE_PIN, val); - nrf_gpio_cfg_output(CONFIG_QDEC_ENABLE_PIN); + nrf_gpio_pin_write(DT_QDEC_ENABLE_PIN, val); + nrf_gpio_cfg_output(DT_QDEC_ENABLE_PIN); #endif } @@ -174,14 +174,14 @@ static int qdec_nrfx_init(struct device *dev) static const nrfx_qdec_config_t config = { .reportper = NRF_QDEC_REPORTPER_40, .sampleper = NRF_QDEC_SAMPLEPER_2048us, - .psela = CONFIG_QDEC_A_PIN, - .pselb = CONFIG_QDEC_B_PIN, -#if defined(CONFIG_QDEC_LED_PIN) - .pselled = CONFIG_QDEC_LED_PIN, + .psela = DT_QDEC_A_PIN, + .pselb = DT_QDEC_B_PIN, +#if defined(DT_QDEC_LED_PIN) + .pselled = DT_QDEC_LED_PIN, #else .pselled = 0xFFFFFFFF, /* disabled */ #endif - .ledpre = CONFIG_QDEC_LED_PRE, + .ledpre = DT_QDEC_LED_PRE, .ledpol = NRF_QDEC_LEPOL_ACTIVE_HIGH, .interrupt_priority = NRFX_QDEC_CONFIG_IRQ_PRIORITY, .dbfen = 0, /* disabled */ @@ -192,7 +192,7 @@ static int qdec_nrfx_init(struct device *dev) LOG_DBG(""); - IRQ_CONNECT(CONFIG_QDEC_IRQ, CONFIG_QDEC_IRQ_PRI, + IRQ_CONNECT(DT_QDEC_IRQ, DT_QDEC_IRQ_PRI, nrfx_isr, nrfx_qdec_irq_handler, 0); nerr = nrfx_qdec_init(&config, qdec_nrfx_event_handler); @@ -302,6 +302,6 @@ static const struct sensor_driver_api qdec_nrfx_driver_api = { .trigger_set = qdec_nrfx_trigger_set, }; -DEVICE_DEFINE(qdec_nrfx, CONFIG_QDEC_NAME, qdec_nrfx_init, +DEVICE_DEFINE(qdec_nrfx, DT_QDEC_NAME, qdec_nrfx_init, qdec_nrfx_pm_control, NULL, NULL, POST_KERNEL, CONFIG_SENSOR_INIT_PRIORITY, &qdec_nrfx_driver_api); diff --git a/drivers/sensor/vl53l0x/vl53l0x.c b/drivers/sensor/vl53l0x/vl53l0x.c index efeda843d4d..c265915530e 100644 --- a/drivers/sensor/vl53l0x/vl53l0x.c +++ b/drivers/sensor/vl53l0x/vl53l0x.c @@ -227,15 +227,15 @@ static int vl53l0x_init(struct device *dev) k_sleep(100); #endif - drv_data->i2c = device_get_binding(CONFIG_VL53L0X_I2C_MASTER_DEV_NAME); + drv_data->i2c = device_get_binding(DT_VL53L0X_I2C_MASTER_DEV_NAME); if (drv_data->i2c == NULL) { LOG_ERR("Could not get pointer to %s device.", - CONFIG_VL53L0X_I2C_MASTER_DEV_NAME); + DT_VL53L0X_I2C_MASTER_DEV_NAME); return -EINVAL; } drv_data->vl53l0x.i2c = drv_data->i2c; - drv_data->vl53l0x.I2cDevAddr = CONFIG_VL53L0X_I2C_ADDR; + drv_data->vl53l0x.I2cDevAddr = DT_VL53L0X_I2C_ADDR; /* Get info from sensor */ (void)memset(&vl53l0x_dev_info, 0, sizeof(VL53L0X_DeviceInfo_t)); @@ -281,7 +281,7 @@ static int vl53l0x_init(struct device *dev) static struct vl53l0x_data vl53l0x_driver; -DEVICE_AND_API_INIT(vl53l0x, CONFIG_VL53L0X_NAME, vl53l0x_init, &vl53l0x_driver, +DEVICE_AND_API_INIT(vl53l0x, DT_VL53L0X_NAME, vl53l0x_init, &vl53l0x_driver, NULL, POST_KERNEL, CONFIG_SENSOR_INIT_PRIORITY, &vl53l0x_api_funcs); diff --git a/drivers/serial/leuart_gecko.c b/drivers/serial/leuart_gecko.c index 50a16491994..aedac697147 100644 --- a/drivers/serial/leuart_gecko.c +++ b/drivers/serial/leuart_gecko.c @@ -318,12 +318,12 @@ static void leuart_gecko_config_func_0(struct device *dev); #endif static const struct leuart_gecko_config leuart_gecko_0_config = { - .base = (LEUART_TypeDef *)CONFIG_LEUART_GECKO_0_BASE_ADDRESS, + .base = (LEUART_TypeDef *)DT_LEUART_GECKO_0_BASE_ADDRESS, .clock = cmuClock_LEUART0, - .baud_rate = CONFIG_LEUART_GECKO_0_CURRENT_SPEED, + .baud_rate = DT_LEUART_GECKO_0_CURRENT_SPEED, .pin_rx = PIN_LEUART0_RXD, .pin_tx = PIN_LEUART0_TXD, - .loc = CONFIG_LEUART_GECKO_0_LOCATION, + .loc = DT_LEUART_GECKO_0_LOCATION, #ifdef CONFIG_UART_INTERRUPT_DRIVEN .irq_config_func = leuart_gecko_config_func_0, #endif @@ -331,7 +331,7 @@ static const struct leuart_gecko_config leuart_gecko_0_config = { static struct leuart_gecko_data leuart_gecko_0_data; -DEVICE_AND_API_INIT(leuart_0, CONFIG_LEUART_GECKO_0_LABEL, &leuart_gecko_init, +DEVICE_AND_API_INIT(leuart_0, DT_LEUART_GECKO_0_LABEL, &leuart_gecko_init, &leuart_gecko_0_data, &leuart_gecko_0_config, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &leuart_gecko_driver_api); @@ -339,11 +339,11 @@ DEVICE_AND_API_INIT(leuart_0, CONFIG_LEUART_GECKO_0_LABEL, &leuart_gecko_init, #ifdef CONFIG_UART_INTERRUPT_DRIVEN static void leuart_gecko_config_func_0(struct device *dev) { - IRQ_CONNECT(CONFIG_LEUART_GECKO_0_IRQ, - CONFIG_LEUART_GECKO_0_IRQ_PRIORITY, leuart_gecko_isr, + IRQ_CONNECT(DT_LEUART_GECKO_0_IRQ, + DT_LEUART_GECKO_0_IRQ_PRIORITY, leuart_gecko_isr, DEVICE_GET(leuart_0), 0); - irq_enable(CONFIG_LEUART_GECKO_0_IRQ); + irq_enable(DT_LEUART_GECKO_0_IRQ); } #endif diff --git a/drivers/serial/uart_cc32xx.c b/drivers/serial/uart_cc32xx.c index 94ccd57ea90..f6255a67e6a 100644 --- a/drivers/serial/uart_cc32xx.c +++ b/drivers/serial/uart_cc32xx.c @@ -307,7 +307,7 @@ static const struct uart_driver_api uart_cc32xx_driver_api = { #endif /* CONFIG_UART_INTERRUPT_DRIVEN */ }; -DEVICE_AND_API_INIT(uart_cc32xx_0, CONFIG_UART_CC32XX_NAME, +DEVICE_AND_API_INIT(uart_cc32xx_0, DT_UART_CC32XX_NAME, uart_cc32xx_init, &uart_cc32xx_dev_data_0, &uart_cc32xx_dev_cfg_0, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, diff --git a/drivers/serial/uart_cmsdk_apb.c b/drivers/serial/uart_cmsdk_apb.c index 3c3eb04ffbc..0223f1aef0c 100644 --- a/drivers/serial/uart_cmsdk_apb.c +++ b/drivers/serial/uart_cmsdk_apb.c @@ -454,7 +454,7 @@ static void uart_cmsdk_apb_irq_config_func_0(struct device *dev); #endif static const struct uart_device_config uart_cmsdk_apb_dev_cfg_0 = { - .base = (u8_t *)CMSDK_APB_UART0, + .base = (u8_t *)DT_CMSDK_APB_UART0, .sys_clk_freq = CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC, #ifdef CONFIG_UART_INTERRUPT_DRIVEN .irq_config_func = uart_cmsdk_apb_irq_config_func_0, @@ -462,17 +462,17 @@ static const struct uart_device_config uart_cmsdk_apb_dev_cfg_0 = { }; static struct uart_cmsdk_apb_dev_data uart_cmsdk_apb_dev_data_0 = { - .baud_rate = CONFIG_UART_CMSDK_APB_PORT0_BAUD_RATE, + .baud_rate = DT_UART_CMSDK_APB_PORT0_BAUD_RATE, .uart_cc_as = {.bus = CMSDK_APB, .state = SOC_ACTIVE, - .device = CMSDK_APB_UART0,}, + .device = DT_CMSDK_APB_UART0,}, .uart_cc_ss = {.bus = CMSDK_APB, .state = SOC_SLEEP, - .device = CMSDK_APB_UART0,}, + .device = DT_CMSDK_APB_UART0,}, .uart_cc_dss = {.bus = CMSDK_APB, .state = SOC_DEEPSLEEP, - .device = CMSDK_APB_UART0,}, + .device = DT_CMSDK_APB_UART0,}, }; DEVICE_AND_API_INIT(uart_cmsdk_apb_0, - CONFIG_UART_CMSDK_APB_PORT0_NAME, + DT_UART_CMSDK_APB_PORT0_NAME, &uart_cmsdk_apb_init, &uart_cmsdk_apb_dev_data_0, &uart_cmsdk_apb_dev_cfg_0, PRE_KERNEL_1, @@ -480,32 +480,32 @@ DEVICE_AND_API_INIT(uart_cmsdk_apb_0, &uart_cmsdk_apb_driver_api); #ifdef CONFIG_UART_INTERRUPT_DRIVEN -#ifdef CMSDK_APB_UART_0_IRQ +#ifdef DT_CMSDK_APB_UART_0_IRQ static void uart_cmsdk_apb_irq_config_func_0(struct device *dev) { - IRQ_CONNECT(CMSDK_APB_UART_0_IRQ, - CONFIG_UART_CMSDK_APB_PORT0_IRQ_PRI, + IRQ_CONNECT(DT_CMSDK_APB_UART_0_IRQ, + DT_UART_CMSDK_APB_PORT0_IRQ_PRI, uart_cmsdk_apb_isr, DEVICE_GET(uart_cmsdk_apb_0), 0); - irq_enable(CMSDK_APB_UART_0_IRQ); + irq_enable(DT_CMSDK_APB_UART_0_IRQ); } #else static void uart_cmsdk_apb_irq_config_func_0(struct device *dev) { - IRQ_CONNECT(CMSDK_APB_UART_0_IRQ_TX, - CONFIG_UART_CMSDK_APB_PORT0_IRQ_PRI, + IRQ_CONNECT(DT_CMSDK_APB_UART_0_IRQ_TX, + DT_UART_CMSDK_APB_PORT0_IRQ_PRI, uart_cmsdk_apb_isr, DEVICE_GET(uart_cmsdk_apb_0), 0); - irq_enable(CMSDK_APB_UART_0_IRQ_TX); + irq_enable(DT_CMSDK_APB_UART_0_IRQ_TX); - IRQ_CONNECT(CMSDK_APB_UART_0_IRQ_RX, - CONFIG_UART_CMSDK_APB_PORT0_IRQ_PRI, + IRQ_CONNECT(DT_CMSDK_APB_UART_0_IRQ_RX, + DT_UART_CMSDK_APB_PORT0_IRQ_PRI, uart_cmsdk_apb_isr, DEVICE_GET(uart_cmsdk_apb_0), 0); - irq_enable(CMSDK_APB_UART_0_IRQ_RX); + irq_enable(DT_CMSDK_APB_UART_0_IRQ_RX); } #endif #endif @@ -519,7 +519,7 @@ static void uart_cmsdk_apb_irq_config_func_1(struct device *dev); #endif static const struct uart_device_config uart_cmsdk_apb_dev_cfg_1 = { - .base = (u8_t *)CMSDK_APB_UART1, + .base = (u8_t *)DT_CMSDK_APB_UART1, .sys_clk_freq = CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC, #ifdef CONFIG_UART_INTERRUPT_DRIVEN .irq_config_func = uart_cmsdk_apb_irq_config_func_1, @@ -527,17 +527,17 @@ static const struct uart_device_config uart_cmsdk_apb_dev_cfg_1 = { }; static struct uart_cmsdk_apb_dev_data uart_cmsdk_apb_dev_data_1 = { - .baud_rate = CONFIG_UART_CMSDK_APB_PORT1_BAUD_RATE, + .baud_rate = DT_UART_CMSDK_APB_PORT1_BAUD_RATE, .uart_cc_as = {.bus = CMSDK_APB, .state = SOC_ACTIVE, - .device = CMSDK_APB_UART1,}, + .device = DT_CMSDK_APB_UART1,}, .uart_cc_ss = {.bus = CMSDK_APB, .state = SOC_SLEEP, - .device = CMSDK_APB_UART1,}, + .device = DT_CMSDK_APB_UART1,}, .uart_cc_dss = {.bus = CMSDK_APB, .state = SOC_DEEPSLEEP, - .device = CMSDK_APB_UART1,}, + .device = DT_CMSDK_APB_UART1,}, }; DEVICE_AND_API_INIT(uart_cmsdk_apb_1, - CONFIG_UART_CMSDK_APB_PORT1_NAME, + DT_UART_CMSDK_APB_PORT1_NAME, &uart_cmsdk_apb_init, &uart_cmsdk_apb_dev_data_1, &uart_cmsdk_apb_dev_cfg_1, PRE_KERNEL_1, @@ -545,32 +545,32 @@ DEVICE_AND_API_INIT(uart_cmsdk_apb_1, &uart_cmsdk_apb_driver_api); #ifdef CONFIG_UART_INTERRUPT_DRIVEN -#ifdef CMSDK_APB_UART_1_IRQ +#ifdef DT_CMSDK_APB_UART_1_IRQ static void uart_cmsdk_apb_irq_config_func_1(struct device *dev) { - IRQ_CONNECT(CMSDK_APB_UART_1_IRQ, - CONFIG_UART_CMSDK_APB_PORT1_IRQ_PRI, + IRQ_CONNECT(DT_CMSDK_APB_UART_1_IRQ, + DT_UART_CMSDK_APB_PORT1_IRQ_PRI, uart_cmsdk_apb_isr, DEVICE_GET(uart_cmsdk_apb_1), 0); - irq_enable(CMSDK_APB_UART_1_IRQ); + irq_enable(DT_CMSDK_APB_UART_1_IRQ); } #else static void uart_cmsdk_apb_irq_config_func_1(struct device *dev) { - IRQ_CONNECT(CMSDK_APB_UART_1_IRQ_TX, - CONFIG_UART_CMSDK_APB_PORT1_IRQ_PRI, + IRQ_CONNECT(DT_CMSDK_APB_UART_1_IRQ_TX, + DT_UART_CMSDK_APB_PORT1_IRQ_PRI, uart_cmsdk_apb_isr, DEVICE_GET(uart_cmsdk_apb_1), 0); - irq_enable(CMSDK_APB_UART_1_IRQ_TX); + irq_enable(DT_CMSDK_APB_UART_1_IRQ_TX); - IRQ_CONNECT(CMSDK_APB_UART_1_IRQ_RX, - CONFIG_UART_CMSDK_APB_PORT1_IRQ_PRI, + IRQ_CONNECT(DT_CMSDK_APB_UART_1_IRQ_RX, + DT_UART_CMSDK_APB_PORT1_IRQ_PRI, uart_cmsdk_apb_isr, DEVICE_GET(uart_cmsdk_apb_1), 0); - irq_enable(CMSDK_APB_UART_1_IRQ_RX); + irq_enable(DT_CMSDK_APB_UART_1_IRQ_RX); } #endif #endif @@ -584,7 +584,7 @@ static void uart_cmsdk_apb_irq_config_func_2(struct device *dev); #endif static const struct uart_device_config uart_cmsdk_apb_dev_cfg_2 = { - .base = (u8_t *)CMSDK_APB_UART2, + .base = (u8_t *)DT_CMSDK_APB_UART2, .sys_clk_freq = CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC, #ifdef CONFIG_UART_INTERRUPT_DRIVEN .irq_config_func = uart_cmsdk_apb_irq_config_func_2, @@ -592,17 +592,17 @@ static const struct uart_device_config uart_cmsdk_apb_dev_cfg_2 = { }; static struct uart_cmsdk_apb_dev_data uart_cmsdk_apb_dev_data_2 = { - .baud_rate = CONFIG_UART_CMSDK_APB_PORT2_BAUD_RATE, + .baud_rate = DT_UART_CMSDK_APB_PORT2_BAUD_RATE, .uart_cc_as = {.bus = CMSDK_APB, .state = SOC_ACTIVE, - .device = CMSDK_APB_UART2,}, + .device = DT_CMSDK_APB_UART2,}, .uart_cc_ss = {.bus = CMSDK_APB, .state = SOC_SLEEP, - .device = CMSDK_APB_UART2,}, + .device = DT_CMSDK_APB_UART2,}, .uart_cc_dss = {.bus = CMSDK_APB, .state = SOC_DEEPSLEEP, - .device = CMSDK_APB_UART2,}, + .device = DT_CMSDK_APB_UART2,}, }; DEVICE_AND_API_INIT(uart_cmsdk_apb_2, - CONFIG_UART_CMSDK_APB_PORT2_NAME, + DT_UART_CMSDK_APB_PORT2_NAME, &uart_cmsdk_apb_init, &uart_cmsdk_apb_dev_data_2, &uart_cmsdk_apb_dev_cfg_2, PRE_KERNEL_1, @@ -614,7 +614,7 @@ DEVICE_AND_API_INIT(uart_cmsdk_apb_2, static void uart_cmsdk_apb_irq_config_func_2(struct device *dev) { IRQ_CONNECT(CMSDK_APB_UART_2_IRQ, - CONFIG_UART_CMSDK_APB_PORT2_IRQ_PRI, + DT_UART_CMSDK_APB_PORT2_IRQ_PRI, uart_cmsdk_apb_isr, DEVICE_GET(uart_cmsdk_apb_2), 0); @@ -623,19 +623,19 @@ static void uart_cmsdk_apb_irq_config_func_2(struct device *dev) #else static void uart_cmsdk_apb_irq_config_func_2(struct device *dev) { - IRQ_CONNECT(CMSDK_APB_UART_2_IRQ_TX, - CONFIG_UART_CMSDK_APB_PORT2_IRQ_PRI, + IRQ_CONNECT(DT_CMSDK_APB_UART_2_IRQ_TX, + DT_UART_CMSDK_APB_PORT2_IRQ_PRI, uart_cmsdk_apb_isr, DEVICE_GET(uart_cmsdk_apb_2), 0); - irq_enable(CMSDK_APB_UART_2_IRQ_TX); + irq_enable(DT_CMSDK_APB_UART_2_IRQ_TX); - IRQ_CONNECT(CMSDK_APB_UART_2_IRQ_RX, - CONFIG_UART_CMSDK_APB_PORT2_IRQ_PRI, + IRQ_CONNECT(DT_CMSDK_APB_UART_2_IRQ_RX, + DT_UART_CMSDK_APB_PORT2_IRQ_PRI, uart_cmsdk_apb_isr, DEVICE_GET(uart_cmsdk_apb_2), 0); - irq_enable(CMSDK_APB_UART_2_IRQ_RX); + irq_enable(DT_CMSDK_APB_UART_2_IRQ_RX); } #endif #endif @@ -649,7 +649,7 @@ static void uart_cmsdk_apb_irq_config_func_3(struct device *dev); #endif static const struct uart_device_config uart_cmsdk_apb_dev_cfg_3 = { - .base = (u8_t *)CMSDK_APB_UART3, + .base = (u8_t *)DT_CMSDK_APB_UART3, .sys_clk_freq = CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC, #ifdef CONFIG_UART_INTERRUPT_DRIVEN .irq_config_func = uart_cmsdk_apb_irq_config_func_3, @@ -657,17 +657,17 @@ static const struct uart_device_config uart_cmsdk_apb_dev_cfg_3 = { }; static struct uart_cmsdk_apb_dev_data uart_cmsdk_apb_dev_data_3 = { - .baud_rate = CONFIG_UART_CMSDK_APB_PORT3_BAUD_RATE, + .baud_rate = DT_UART_CMSDK_APB_PORT3_BAUD_RATE, .uart_cc_as = {.bus = CMSDK_APB, .state = SOC_ACTIVE, - .device = CMSDK_APB_UART3,}, + .device = DT_CMSDK_APB_UART3,}, .uart_cc_ss = {.bus = CMSDK_APB, .state = SOC_SLEEP, - .device = CMSDK_APB_UART3,}, + .device = DT_CMSDK_APB_UART3,}, .uart_cc_dss = {.bus = CMSDK_APB, .state = SOC_DEEPSLEEP, - .device = CMSDK_APB_UART3,}, + .device = DT_CMSDK_APB_UART3,}, }; DEVICE_AND_API_INIT(uart_cmsdk_apb_3, - CONFIG_UART_CMSDK_APB_PORT3_NAME, + DT_UART_CMSDK_APB_PORT3_NAME, &uart_cmsdk_apb_init, &uart_cmsdk_apb_dev_data_3, &uart_cmsdk_apb_dev_cfg_3, PRE_KERNEL_1, @@ -679,7 +679,7 @@ DEVICE_AND_API_INIT(uart_cmsdk_apb_3, static void uart_cmsdk_apb_irq_config_func_3(struct device *dev) { IRQ_CONNECT(CMSDK_APB_UART_3_IRQ, - CONFIG_UART_CMSDK_APB_PORT3_IRQ_PRI, + DT_UART_CMSDK_APB_PORT3_IRQ_PRI, uart_cmsdk_apb_isr, DEVICE_GET(uart_cmsdk_apb_3), 0); @@ -688,19 +688,19 @@ static void uart_cmsdk_apb_irq_config_func_3(struct device *dev) #else static void uart_cmsdk_apb_irq_config_func_3(struct device *dev) { - IRQ_CONNECT(CMSDK_APB_UART_3_IRQ_TX, - CONFIG_UART_CMSDK_APB_PORT3_IRQ_PRI, + IRQ_CONNECT(DT_CMSDK_APB_UART_3_IRQ_TX, + DT_UART_CMSDK_APB_PORT3_IRQ_PRI, uart_cmsdk_apb_isr, DEVICE_GET(uart_cmsdk_apb_3), 0); - irq_enable(CMSDK_APB_UART_3_IRQ_TX); + irq_enable(DT_CMSDK_APB_UART_3_IRQ_TX); - IRQ_CONNECT(CMSDK_APB_UART_3_IRQ_RX, - CONFIG_UART_CMSDK_APB_PORT3_IRQ_PRI, + IRQ_CONNECT(DT_CMSDK_APB_UART_3_IRQ_RX, + DT_UART_CMSDK_APB_PORT3_IRQ_PRI, uart_cmsdk_apb_isr, DEVICE_GET(uart_cmsdk_apb_3), 0); - irq_enable(CMSDK_APB_UART_3_IRQ_RX); + irq_enable(DT_CMSDK_APB_UART_3_IRQ_RX); } #endif #endif @@ -714,7 +714,7 @@ static void uart_cmsdk_apb_irq_config_func_4(struct device *dev); #endif static const struct uart_device_config uart_cmsdk_apb_dev_cfg_4 = { - .base = (u8_t *)CMSDK_APB_UART4, + .base = (u8_t *)DT_CMSDK_APB_UART4, .sys_clk_freq = CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC, #ifdef CONFIG_UART_INTERRUPT_DRIVEN .irq_config_func = uart_cmsdk_apb_irq_config_func_4, @@ -722,17 +722,17 @@ static const struct uart_device_config uart_cmsdk_apb_dev_cfg_4 = { }; static struct uart_cmsdk_apb_dev_data uart_cmsdk_apb_dev_data_4 = { - .baud_rate = CONFIG_UART_CMSDK_APB_PORT4_BAUD_RATE, + .baud_rate = DT_UART_CMSDK_APB_PORT4_BAUD_RATE, .uart_cc_as = {.bus = CMSDK_APB, .state = SOC_ACTIVE, - .device = CMSDK_APB_UART4,}, + .device = DT_CMSDK_APB_UART4,}, .uart_cc_ss = {.bus = CMSDK_APB, .state = SOC_SLEEP, - .device = CMSDK_APB_UART4,}, + .device = DT_CMSDK_APB_UART4,}, .uart_cc_dss = {.bus = CMSDK_APB, .state = SOC_DEEPSLEEP, - .device = CMSDK_APB_UART4,}, + .device = DT_CMSDK_APB_UART4,}, }; DEVICE_AND_API_INIT(uart_cmsdk_apb_4, - CONFIG_UART_CMSDK_APB_PORT4_NAME, + DT_UART_CMSDK_APB_PORT4_NAME, &uart_cmsdk_apb_init, &uart_cmsdk_apb_dev_data_4, &uart_cmsdk_apb_dev_cfg_4, PRE_KERNEL_1, @@ -744,7 +744,7 @@ DEVICE_AND_API_INIT(uart_cmsdk_apb_4, static void uart_cmsdk_apb_irq_config_func_4(struct device *dev) { IRQ_CONNECT(CMSDK_APB_UART_4_IRQ, - CONFIG_UART_CMSDK_APB_PORT4_IRQ_PRI, + DT_UART_CMSDK_APB_PORT4_IRQ_PRI, uart_cmsdk_apb_isr, DEVICE_GET(uart_cmsdk_apb_4), 0); @@ -753,19 +753,19 @@ static void uart_cmsdk_apb_irq_config_func_4(struct device *dev) #else static void uart_cmsdk_apb_irq_config_func_4(struct device *dev) { - IRQ_CONNECT(CMSDK_APB_UART_4_IRQ_TX, - CONFIG_UART_CMSDK_APB_PORT4_IRQ_PRI, + IRQ_CONNECT(DT_CMSDK_APB_UART_4_IRQ_TX, + DT_UART_CMSDK_APB_PORT4_IRQ_PRI, uart_cmsdk_apb_isr, DEVICE_GET(uart_cmsdk_apb_4), 0); - irq_enable(CMSDK_APB_UART_4_IRQ_TX); + irq_enable(DT_CMSDK_APB_UART_4_IRQ_TX); - IRQ_CONNECT(CMSDK_APB_UART_4_IRQ_RX, - CONFIG_UART_CMSDK_APB_PORT4_IRQ_PRI, + IRQ_CONNECT(DT_CMSDK_APB_UART_4_IRQ_RX, + DT_UART_CMSDK_APB_PORT4_IRQ_PRI, uart_cmsdk_apb_isr, DEVICE_GET(uart_cmsdk_apb_4), 0); - irq_enable(CMSDK_APB_UART_4_IRQ_RX); + irq_enable(DT_CMSDK_APB_UART_4_IRQ_RX); } #endif #endif diff --git a/drivers/serial/uart_gecko.c b/drivers/serial/uart_gecko.c index efcbae57430..d17265b8a02 100644 --- a/drivers/serial/uart_gecko.c +++ b/drivers/serial/uart_gecko.c @@ -298,12 +298,12 @@ static void uart_gecko_config_func_0(struct device *dev); #endif static const struct uart_gecko_config uart_gecko_0_config = { - .base = (USART_TypeDef *)CONFIG_UART_GECKO_0_BASE_ADDRESS, + .base = (USART_TypeDef *)DT_UART_GECKO_0_BASE_ADDRESS, .clock = cmuClock_UART0, - .baud_rate = CONFIG_UART_GECKO_0_CURRENT_SPEED, + .baud_rate = DT_UART_GECKO_0_CURRENT_SPEED, .pin_rx = PIN_UART0_RXD, .pin_tx = PIN_UART0_TXD, - .loc = CONFIG_UART_GECKO_0_LOCATION, + .loc = DT_UART_GECKO_0_LOCATION, #ifdef CONFIG_UART_INTERRUPT_DRIVEN .irq_config_func = uart_gecko_config_func_0, #endif @@ -311,22 +311,22 @@ static const struct uart_gecko_config uart_gecko_0_config = { static struct uart_gecko_data uart_gecko_0_data; -DEVICE_AND_API_INIT(uart_0, CONFIG_UART_GECKO_0_LABEL, &uart_gecko_init, &uart_gecko_0_data, +DEVICE_AND_API_INIT(uart_0, DT_UART_GECKO_0_LABEL, &uart_gecko_init, &uart_gecko_0_data, &uart_gecko_0_config, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &uart_gecko_driver_api); #ifdef CONFIG_UART_INTERRUPT_DRIVEN static void uart_gecko_config_func_0(struct device *dev) { - IRQ_CONNECT(CONFIG_UART_GECKO_0_IRQ_RX, - CONFIG_UART_GECKO_0_IRQ_RX_PRIORITY, uart_gecko_isr, + IRQ_CONNECT(DT_UART_GECKO_0_IRQ_RX, + DT_UART_GECKO_0_IRQ_RX_PRIORITY, uart_gecko_isr, DEVICE_GET(uart_0), 0); - IRQ_CONNECT(CONFIG_UART_GECKO_0_IRQ_TX, - CONFIG_UART_GECKO_0_IRQ_TX_PRIORITY, uart_gecko_isr, + IRQ_CONNECT(DT_UART_GECKO_0_IRQ_TX, + DT_UART_GECKO_0_IRQ_TX_PRIORITY, uart_gecko_isr, DEVICE_GET(uart_0), 0); - irq_enable(CONFIG_UART_GECKO_0_IRQ_RX); - irq_enable(CONFIG_UART_GECKO_0_IRQ_TX); + irq_enable(DT_UART_GECKO_0_IRQ_RX); + irq_enable(DT_UART_GECKO_0_IRQ_TX); } #endif @@ -339,12 +339,12 @@ static void uart_gecko_config_func_1(struct device *dev); #endif static const struct uart_gecko_config uart_gecko_1_config = { - .base = (USART_TypeDef *)CONFIG_UART_GECKO_1_BASE_ADDRESS, + .base = (USART_TypeDef *)DT_UART_GECKO_1_BASE_ADDRESS, .clock = cmuClock_UART1, - .baud_rate = CONFIG_UART_GECKO_1_CURRENT_SPEED, + .baud_rate = DT_UART_GECKO_1_CURRENT_SPEED, .pin_rx = PIN_UART1_RXD, .pin_tx = PIN_UART1_TXD, - .loc = CONFIG_UART_GECKO_1_LOCATION, + .loc = DT_UART_GECKO_1_LOCATION, #ifdef CONFIG_UART_INTERRUPT_DRIVEN .irq_config_func = uart_gecko_config_func_1, #endif @@ -352,22 +352,22 @@ static const struct uart_gecko_config uart_gecko_1_config = { static struct uart_gecko_data uart_gecko_1_data; -DEVICE_AND_API_INIT(uart_1, CONFIG_UART_GECKO_1_LABEL, &uart_gecko_init, &uart_gecko_1_data, +DEVICE_AND_API_INIT(uart_1, DT_UART_GECKO_1_LABEL, &uart_gecko_init, &uart_gecko_1_data, &uart_gecko_1_config, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &uart_gecko_driver_api); #ifdef CONFIG_UART_INTERRUPT_DRIVEN static void uart_gecko_config_func_1(struct device *dev) { - IRQ_CONNECT(CONFIG_UART_GECKO_1_IRQ_RX, - CONFIG_UART_GECKO_1_IRQ_RX_PRIORITY, uart_gecko_isr, + IRQ_CONNECT(DT_UART_GECKO_1_IRQ_RX, + DT_UART_GECKO_1_IRQ_RX_PRIORITY, uart_gecko_isr, DEVICE_GET(uart_1), 0); - IRQ_CONNECT(CONFIG_UART_GECKO_1_IRQ_TX, - CONFIG_UART_GECKO_1_IRQ_TX_PRIORITY, uart_gecko_isr, + IRQ_CONNECT(DT_UART_GECKO_1_IRQ_TX, + DT_UART_GECKO_1_IRQ_TX_PRIORITY, uart_gecko_isr, DEVICE_GET(uart_1), 0); - irq_enable(CONFIG_UART_GECKO_1_IRQ_RX); - irq_enable(CONFIG_UART_GECKO_1_IRQ_TX); + irq_enable(DT_UART_GECKO_1_IRQ_RX); + irq_enable(DT_UART_GECKO_1_IRQ_TX); } #endif @@ -380,12 +380,12 @@ static void usart_gecko_config_func_0(struct device *dev); #endif static const struct uart_gecko_config usart_gecko_0_config = { - .base = (USART_TypeDef *)CONFIG_USART_GECKO_0_BASE_ADDRESS, + .base = (USART_TypeDef *)DT_USART_GECKO_0_BASE_ADDRESS, .clock = cmuClock_USART0, - .baud_rate = CONFIG_USART_GECKO_0_CURRENT_SPEED, + .baud_rate = DT_USART_GECKO_0_CURRENT_SPEED, .pin_rx = PIN_USART0_RXD, .pin_tx = PIN_USART0_TXD, - .loc = CONFIG_USART_GECKO_0_LOCATION, + .loc = DT_USART_GECKO_0_LOCATION, #ifdef CONFIG_UART_INTERRUPT_DRIVEN .irq_config_func = usart_gecko_config_func_0, #endif @@ -393,22 +393,22 @@ static const struct uart_gecko_config usart_gecko_0_config = { static struct uart_gecko_data usart_gecko_0_data; -DEVICE_AND_API_INIT(usart_0, CONFIG_USART_GECKO_0_LABEL, &uart_gecko_init, +DEVICE_AND_API_INIT(usart_0, DT_USART_GECKO_0_LABEL, &uart_gecko_init, &usart_gecko_0_data, &usart_gecko_0_config, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &uart_gecko_driver_api); #ifdef CONFIG_UART_INTERRUPT_DRIVEN static void usart_gecko_config_func_0(struct device *dev) { - IRQ_CONNECT(CONFIG_USART_GECKO_0_IRQ_RX, - CONFIG_USART_GECKO_0_IRQ_RX_PRIORITY, uart_gecko_isr, + IRQ_CONNECT(DT_USART_GECKO_0_IRQ_RX, + DT_USART_GECKO_0_IRQ_RX_PRIORITY, uart_gecko_isr, DEVICE_GET(usart_0), 0); - IRQ_CONNECT(CONFIG_USART_GECKO_0_IRQ_TX, - CONFIG_USART_GECKO_0_IRQ_TX_PRIORITY, uart_gecko_isr, + IRQ_CONNECT(DT_USART_GECKO_0_IRQ_TX, + DT_USART_GECKO_0_IRQ_TX_PRIORITY, uart_gecko_isr, DEVICE_GET(usart_0), 0); - irq_enable(CONFIG_USART_GECKO_0_IRQ_RX); - irq_enable(CONFIG_USART_GECKO_0_IRQ_TX); + irq_enable(DT_USART_GECKO_0_IRQ_RX); + irq_enable(DT_USART_GECKO_0_IRQ_TX); } #endif @@ -421,12 +421,12 @@ static void usart_gecko_config_func_1(struct device *dev); #endif static const struct uart_gecko_config usart_gecko_1_config = { - .base = (USART_TypeDef *)CONFIG_USART_GECKO_1_BASE_ADDRESS, + .base = (USART_TypeDef *)DT_USART_GECKO_1_BASE_ADDRESS, .clock = cmuClock_USART1, - .baud_rate = CONFIG_USART_GECKO_1_CURRENT_SPEED, + .baud_rate = DT_USART_GECKO_1_CURRENT_SPEED, .pin_rx = PIN_USART1_RXD, .pin_tx = PIN_USART1_TXD, - .loc = CONFIG_USART_GECKO_1_LOCATION, + .loc = DT_USART_GECKO_1_LOCATION, #ifdef CONFIG_UART_INTERRUPT_DRIVEN .irq_config_func = usart_gecko_config_func_1, #endif @@ -434,22 +434,22 @@ static const struct uart_gecko_config usart_gecko_1_config = { static struct uart_gecko_data usart_gecko_1_data; -DEVICE_AND_API_INIT(usart_1, CONFIG_USART_GECKO_1_LABEL, &uart_gecko_init, +DEVICE_AND_API_INIT(usart_1, DT_USART_GECKO_1_LABEL, &uart_gecko_init, &usart_gecko_1_data, &usart_gecko_1_config, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &uart_gecko_driver_api); #ifdef CONFIG_UART_INTERRUPT_DRIVEN static void usart_gecko_config_func_1(struct device *dev) { - IRQ_CONNECT(CONFIG_USART_GECKO_1_IRQ_RX, - CONFIG_USART_GECKO_1_IRQ_RX_PRIORITY, uart_gecko_isr, + IRQ_CONNECT(DT_USART_GECKO_1_IRQ_RX, + DT_USART_GECKO_1_IRQ_RX_PRIORITY, uart_gecko_isr, DEVICE_GET(usart_1), 0); - IRQ_CONNECT(CONFIG_USART_GECKO_1_IRQ_TX, - CONFIG_USART_GECKO_1_IRQ_TX_PRIORITY, uart_gecko_isr, + IRQ_CONNECT(DT_USART_GECKO_1_IRQ_TX, + DT_USART_GECKO_1_IRQ_TX_PRIORITY, uart_gecko_isr, DEVICE_GET(usart_1), 0); - irq_enable(CONFIG_USART_GECKO_1_IRQ_RX); - irq_enable(CONFIG_USART_GECKO_1_IRQ_TX); + irq_enable(DT_USART_GECKO_1_IRQ_RX); + irq_enable(DT_USART_GECKO_1_IRQ_TX); } #endif @@ -462,12 +462,12 @@ static void usart_gecko_config_func_2(struct device *dev); #endif static const struct uart_gecko_config usart_gecko_2_config = { - .base = (USART_TypeDef *)CONFIG_USART_GECKO_2_BASE_ADDRESS, + .base = (USART_TypeDef *)DT_USART_GECKO_2_BASE_ADDRESS, .clock = cmuClock_USART2, - .baud_rate = CONFIG_USART_GECKO_2_CURRENT_SPEED, + .baud_rate = DT_USART_GECKO_2_CURRENT_SPEED, .pin_rx = PIN_USART2_RXD, .pin_tx = PIN_USART2_TXD, - .loc = CONFIG_USART_GECKO_2_LOCATION, + .loc = DT_USART_GECKO_2_LOCATION, #ifdef CONFIG_UART_INTERRUPT_DRIVEN .irq_config_func = usart_gecko_config_func_2, #endif @@ -475,22 +475,22 @@ static const struct uart_gecko_config usart_gecko_2_config = { static struct uart_gecko_data usart_gecko_2_data; -DEVICE_AND_API_INIT(usart_2, CONFIG_USART_GECKO_2_LABEL, &uart_gecko_init, +DEVICE_AND_API_INIT(usart_2, DT_USART_GECKO_2_LABEL, &uart_gecko_init, &usart_gecko_2_data, &usart_gecko_2_config, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &uart_gecko_driver_api); #ifdef CONFIG_UART_INTERRUPT_DRIVEN static void usart_gecko_config_func_2(struct device *dev) { - IRQ_CONNECT(CONFIG_USART_GECKO_2_IRQ_RX, - CONFIG_USART_GECKO_2_IRQ_RX_PRIORITY, uart_gecko_isr, + IRQ_CONNECT(DT_USART_GECKO_2_IRQ_RX, + DT_USART_GECKO_2_IRQ_RX_PRIORITY, uart_gecko_isr, DEVICE_GET(usart_2), 0); - IRQ_CONNECT(CONFIG_USART_GECKO_2_IRQ_TX, - CONFIG_USART_GECKO_2_IRQ_TX_PRIORITY, uart_gecko_isr, + IRQ_CONNECT(DT_USART_GECKO_2_IRQ_TX, + DT_USART_GECKO_2_IRQ_TX_PRIORITY, uart_gecko_isr, DEVICE_GET(usart_2), 0); - irq_enable(CONFIG_USART_GECKO_2_IRQ_RX); - irq_enable(CONFIG_USART_GECKO_2_IRQ_TX); + irq_enable(DT_USART_GECKO_2_IRQ_RX); + irq_enable(DT_USART_GECKO_2_IRQ_TX); } #endif @@ -503,12 +503,12 @@ static void usart_gecko_config_func_3(struct device *dev); #endif static const struct uart_gecko_config usart_gecko_3_config = { - .base = (USART_TypeDef *)CONFIG_USART_GECKO_3_BASE_ADDRESS, + .base = (USART_TypeDef *)DT_USART_GECKO_3_BASE_ADDRESS, .clock = cmuClock_USART3, - .baud_rate = CONFIG_USART_GECKO_3_CURRENT_SPEED, + .baud_rate = DT_USART_GECKO_3_CURRENT_SPEED, .pin_rx = PIN_USART3_RXD, .pin_tx = PIN_USART3_TXD, - .loc = CONFIG_USART_GECKO_3_LOCATION, + .loc = DT_USART_GECKO_3_LOCATION, #ifdef CONFIG_UART_INTERRUPT_DRIVEN .irq_config_func = usart_gecko_config_func_3, #endif @@ -516,22 +516,22 @@ static const struct uart_gecko_config usart_gecko_3_config = { static struct uart_gecko_data usart_gecko_3_data; -DEVICE_AND_API_INIT(usart_3, CONFIG_USART_GECKO_3_LABEL, &uart_gecko_init, +DEVICE_AND_API_INIT(usart_3, DT_USART_GECKO_3_LABEL, &uart_gecko_init, &usart_gecko_3_data, &usart_gecko_3_config, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &uart_gecko_driver_api); #ifdef CONFIG_UART_INTERRUPT_DRIVEN static void usart_gecko_config_func_3(struct device *dev) { - IRQ_CONNECT(CONFIG_USART_GECKO_3_IRQ_RX, - CONFIG_USART_GECKO_3_IRQ_RX_PRIORITY, uart_gecko_isr, + IRQ_CONNECT(DT_USART_GECKO_3_IRQ_RX, + DT_USART_GECKO_3_IRQ_RX_PRIORITY, uart_gecko_isr, DEVICE_GET(usart_3), 0); - IRQ_CONNECT(CONFIG_USART_GECKO_3_IRQ_TX, - CONFIG_USART_GECKO_3_IRQ_TX_PRIORITY, uart_gecko_isr, + IRQ_CONNECT(DT_USART_GECKO_3_IRQ_TX, + DT_USART_GECKO_3_IRQ_TX_PRIORITY, uart_gecko_isr, DEVICE_GET(usart_3), 0); - irq_enable(CONFIG_USART_GECKO_3_IRQ_RX); - irq_enable(CONFIG_USART_GECKO_3_IRQ_TX); + irq_enable(DT_USART_GECKO_3_IRQ_RX); + irq_enable(DT_USART_GECKO_3_IRQ_TX); } #endif diff --git a/drivers/serial/uart_imx.c b/drivers/serial/uart_imx.c index a26c71a4292..cf29af5d71a 100644 --- a/drivers/serial/uart_imx.c +++ b/drivers/serial/uart_imx.c @@ -291,9 +291,9 @@ static void irq_config_func_1(struct device *port); #endif static const struct imx_uart_config imx_uart_1_config = { - .base = (UART_Type *) CONFIG_UART_IMX_UART_1_BASE_ADDRESS, - .baud_rate = CONFIG_UART_IMX_UART_1_BAUD_RATE, - .modem_mode = CONFIG_UART_IMX_UART_1_MODEM_MODE, + .base = (UART_Type *) DT_UART_IMX_UART_1_BASE_ADDRESS, + .baud_rate = DT_UART_IMX_UART_1_BAUD_RATE, + .modem_mode = DT_UART_IMX_UART_1_MODEM_MODE, #ifdef CONFIG_UART_INTERRUPT_DRIVEN .irq_config_func = irq_config_func_1, #endif @@ -301,7 +301,7 @@ static const struct imx_uart_config imx_uart_1_config = { static struct imx_uart_data imx_uart_1_data; -DEVICE_AND_API_INIT(uart_1, CONFIG_UART_IMX_UART_1_NAME, &uart_imx_init, +DEVICE_AND_API_INIT(uart_1, DT_UART_IMX_UART_1_NAME, &uart_imx_init, &imx_uart_1_data, &imx_uart_1_config, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &uart_imx_driver_api); @@ -309,11 +309,11 @@ DEVICE_AND_API_INIT(uart_1, CONFIG_UART_IMX_UART_1_NAME, &uart_imx_init, #ifdef CONFIG_UART_INTERRUPT_DRIVEN static void irq_config_func_1(struct device *dev) { - IRQ_CONNECT(CONFIG_UART_IMX_UART_1_IRQ_NUM, - CONFIG_UART_IMX_UART_1_IRQ_PRI, + IRQ_CONNECT(DT_UART_IMX_UART_1_IRQ_NUM, + DT_UART_IMX_UART_1_IRQ_PRI, uart_imx_isr, DEVICE_GET(uart_1), 0); - irq_enable(CONFIG_UART_IMX_UART_1_IRQ_NUM); + irq_enable(DT_UART_IMX_UART_1_IRQ_NUM); } #endif @@ -327,9 +327,9 @@ static void irq_config_func_2(struct device *port); #endif static const struct imx_uart_config imx_uart_2_config = { - .base = (UART_Type *) CONFIG_UART_IMX_UART_2_BASE_ADDRESS, - .baud_rate = CONFIG_UART_IMX_UART_2_BAUD_RATE, - .modem_mode = CONFIG_UART_IMX_UART_2_MODEM_MODE, + .base = (UART_Type *) DT_UART_IMX_UART_2_BASE_ADDRESS, + .baud_rate = DT_UART_IMX_UART_2_BAUD_RATE, + .modem_mode = DT_UART_IMX_UART_2_MODEM_MODE, #ifdef CONFIG_UART_INTERRUPT_DRIVEN .irq_config_func = irq_config_func_2, #endif @@ -337,7 +337,7 @@ static const struct imx_uart_config imx_uart_2_config = { static struct imx_uart_data imx_uart_2_data; -DEVICE_AND_API_INIT(uart_2, CONFIG_UART_IMX_UART_2_NAME, &uart_imx_init, +DEVICE_AND_API_INIT(uart_2, DT_UART_IMX_UART_2_NAME, &uart_imx_init, &imx_uart_2_data, &imx_uart_2_config, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &uart_imx_driver_api); @@ -345,11 +345,11 @@ DEVICE_AND_API_INIT(uart_2, CONFIG_UART_IMX_UART_2_NAME, &uart_imx_init, #ifdef CONFIG_UART_INTERRUPT_DRIVEN static void irq_config_func_2(struct device *dev) { - IRQ_CONNECT(CONFIG_UART_IMX_UART_2_IRQ_NUM, - CONFIG_UART_IMX_UART_2_IRQ_PRI, + IRQ_CONNECT(DT_UART_IMX_UART_2_IRQ_NUM, + DT_UART_IMX_UART_2_IRQ_PRI, uart_imx_isr, DEVICE_GET(uart_2), 0); - irq_enable(CONFIG_UART_IMX_UART_2_IRQ_NUM); + irq_enable(DT_UART_IMX_UART_2_IRQ_NUM); } #endif @@ -362,9 +362,9 @@ static void irq_config_func_3(struct device *port); #endif static const struct imx_uart_config imx_uart_3_config = { - .base = (UART_Type *) CONFIG_UART_IMX_UART_3_BASE_ADDRESS, - .baud_rate = CONFIG_UART_IMX_UART_3_BAUD_RATE, - .modem_mode = CONFIG_UART_IMX_UART_3_MODEM_MODE, + .base = (UART_Type *) DT_UART_IMX_UART_3_BASE_ADDRESS, + .baud_rate = DT_UART_IMX_UART_3_BAUD_RATE, + .modem_mode = DT_UART_IMX_UART_3_MODEM_MODE, #ifdef CONFIG_UART_INTERRUPT_DRIVEN .irq_config_func = irq_config_func_3, #endif @@ -372,7 +372,7 @@ static const struct imx_uart_config imx_uart_3_config = { static struct imx_uart_data imx_uart_3_data; -DEVICE_AND_API_INIT(uart_3, CONFIG_UART_IMX_UART_3_NAME, &uart_imx_init, +DEVICE_AND_API_INIT(uart_3, DT_UART_IMX_UART_3_NAME, &uart_imx_init, &imx_uart_3_data, &imx_uart_3_config, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &uart_imx_driver_api); @@ -380,11 +380,11 @@ DEVICE_AND_API_INIT(uart_3, CONFIG_UART_IMX_UART_3_NAME, &uart_imx_init, #ifdef CONFIG_UART_INTERRUPT_DRIVEN static void irq_config_func_3(struct device *dev) { - IRQ_CONNECT(CONFIG_UART_IMX_UART_3_IRQ_NUM, - CONFIG_UART_IMX_UART_3_IRQ_PRI, + IRQ_CONNECT(DT_UART_IMX_UART_3_IRQ_NUM, + DT_UART_IMX_UART_3_IRQ_PRI, uart_imx_isr, DEVICE_GET(uart_3), 0); - irq_enable(CONFIG_UART_IMX_UART_3_IRQ_NUM); + irq_enable(DT_UART_IMX_UART_3_IRQ_NUM); } #endif @@ -397,9 +397,9 @@ static void irq_config_func_4(struct device *port); #endif static const struct imx_uart_config imx_uart_4_config = { - .base = (UART_Type *) CONFIG_UART_IMX_UART_4_BASE_ADDRESS, - .baud_rate = CONFIG_UART_IMX_UART_4_BAUD_RATE, - .modem_mode = CONFIG_UART_IMX_UART_4_MODEM_MODE, + .base = (UART_Type *) DT_UART_IMX_UART_4_BASE_ADDRESS, + .baud_rate = DT_UART_IMX_UART_4_BAUD_RATE, + .modem_mode = DT_UART_IMX_UART_4_MODEM_MODE, #ifdef CONFIG_UART_INTERRUPT_DRIVEN .irq_config_func = irq_config_func_4, #endif @@ -407,7 +407,7 @@ static const struct imx_uart_config imx_uart_4_config = { static struct imx_uart_data imx_uart_4_data; -DEVICE_AND_API_INIT(uart_4, CONFIG_UART_IMX_UART_4_NAME, &uart_imx_init, +DEVICE_AND_API_INIT(uart_4, DT_UART_IMX_UART_4_NAME, &uart_imx_init, &imx_uart_4_data, &imx_uart_4_config, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &uart_imx_driver_api); @@ -415,11 +415,11 @@ DEVICE_AND_API_INIT(uart_4, CONFIG_UART_IMX_UART_4_NAME, &uart_imx_init, #ifdef CONFIG_UART_INTERRUPT_DRIVEN static void irq_config_func_4(struct device *dev) { - IRQ_CONNECT(CONFIG_UART_IMX_UART_4_IRQ_NUM, - CONFIG_UART_IMX_UART_4_IRQ_PRI, + IRQ_CONNECT(DT_UART_IMX_UART_4_IRQ_NUM, + DT_UART_IMX_UART_4_IRQ_PRI, uart_imx_isr, DEVICE_GET(uart_4), 0); - irq_enable(CONFIG_UART_IMX_UART_4_IRQ_NUM); + irq_enable(DT_UART_IMX_UART_4_IRQ_NUM); } #endif @@ -432,9 +432,9 @@ static void irq_config_func_5(struct device *port); #endif static const struct imx_uart_config imx_uart_5_config = { - .base = (UART_Type *) CONFIG_UART_IMX_UART_5_BASE_ADDRESS, - .baud_rate = CONFIG_UART_IMX_UART_5_BAUD_RATE, - .modem_mode = CONFIG_UART_IMX_UART_5_MODEM_MODE, + .base = (UART_Type *) DT_UART_IMX_UART_5_BASE_ADDRESS, + .baud_rate = DT_UART_IMX_UART_5_BAUD_RATE, + .modem_mode = DT_UART_IMX_UART_5_MODEM_MODE, #ifdef CONFIG_UART_INTERRUPT_DRIVEN .irq_config_func = irq_config_func_5, #endif @@ -442,7 +442,7 @@ static const struct imx_uart_config imx_uart_5_config = { static struct imx_uart_data imx_uart_5_data; -DEVICE_AND_API_INIT(uart_5, CONFIG_UART_IMX_UART_5_NAME, &uart_imx_init, +DEVICE_AND_API_INIT(uart_5, DT_UART_IMX_UART_5_NAME, &uart_imx_init, &imx_uart_5_data, &imx_uart_5_config, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &uart_imx_driver_api); @@ -450,11 +450,11 @@ DEVICE_AND_API_INIT(uart_5, CONFIG_UART_IMX_UART_5_NAME, &uart_imx_init, #ifdef CONFIG_UART_INTERRUPT_DRIVEN static void irq_config_func_5(struct device *dev) { - IRQ_CONNECT(CONFIG_UART_IMX_UART_5_IRQ_NUM, - CONFIG_UART_IMX_UART_5_IRQ_PRI, + IRQ_CONNECT(DT_UART_IMX_UART_5_IRQ_NUM, + DT_UART_IMX_UART_5_IRQ_PRI, uart_imx_isr, DEVICE_GET(uart_5), 0); - irq_enable(CONFIG_UART_IMX_UART_5_IRQ_NUM); + irq_enable(DT_UART_IMX_UART_5_IRQ_NUM); } #endif @@ -467,9 +467,9 @@ static void irq_config_func_6(struct device *port); #endif static const struct imx_uart_config imx_uart_6_config = { - .base = (UART_Type *) CONFIG_UART_IMX_UART_6_BASE_ADDRESS, - .baud_rate = CONFIG_UART_IMX_UART_6_BAUD_RATE, - .modem_mode = CONFIG_UART_IMX_UART_6_MODEM_MODE, + .base = (UART_Type *) DT_UART_IMX_UART_6_BASE_ADDRESS, + .baud_rate = DT_UART_IMX_UART_6_BAUD_RATE, + .modem_mode = DT_UART_IMX_UART_6_MODEM_MODE, #ifdef CONFIG_UART_INTERRUPT_DRIVEN .irq_config_func = irq_config_func_6, #endif @@ -477,7 +477,7 @@ static const struct imx_uart_config imx_uart_6_config = { static struct imx_uart_data imx_uart_6_data; -DEVICE_AND_API_INIT(uart_6, CONFIG_UART_IMX_UART_6_NAME, &uart_imx_init, +DEVICE_AND_API_INIT(uart_6, DT_UART_IMX_UART_6_NAME, &uart_imx_init, &imx_uart_6_data, &imx_uart_6_config, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &uart_imx_driver_api); @@ -485,11 +485,11 @@ DEVICE_AND_API_INIT(uart_6, CONFIG_UART_IMX_UART_6_NAME, &uart_imx_init, #ifdef CONFIG_UART_INTERRUPT_DRIVEN static void irq_config_func_6(struct device *dev) { - IRQ_CONNECT(CONFIG_UART_IMX_UART_6_IRQ_NUM, - CONFIG_UART_IMX_UART_6_IRQ_PRI, + IRQ_CONNECT(DT_UART_IMX_UART_6_IRQ_NUM, + DT_UART_IMX_UART_6_IRQ_PRI, uart_imx_isr, DEVICE_GET(uart_6), 0); - irq_enable(CONFIG_UART_IMX_UART_6_IRQ_NUM); + irq_enable(DT_UART_IMX_UART_6_IRQ_NUM); } #endif @@ -502,9 +502,9 @@ static void irq_config_func_7(struct device *port); #endif static const struct imx_uart_config imx_uart_7_config = { - .base = (UART_Type *) CONFIG_UART_IMX_UART_7_BASE_ADDRESS, - .baud_rate = CONFIG_UART_IMX_UART_7_BAUD_RATE, - .modem_mode = CONFIG_UART_IMX_UART_7_MODEM_MODE, + .base = (UART_Type *) DT_UART_IMX_UART_7_BASE_ADDRESS, + .baud_rate = DT_UART_IMX_UART_7_BAUD_RATE, + .modem_mode = DT_UART_IMX_UART_7_MODEM_MODE, #ifdef CONFIG_UART_INTERRUPT_DRIVEN .irq_config_func = irq_config_func_7, #endif @@ -512,7 +512,7 @@ static const struct imx_uart_config imx_uart_7_config = { static struct imx_uart_data imx_uart_7_data; -DEVICE_AND_API_INIT(uart_7, CONFIG_UART_IMX_UART_7_NAME, &uart_imx_init, +DEVICE_AND_API_INIT(uart_7, DT_UART_IMX_UART_7_NAME, &uart_imx_init, &imx_uart_7_data, &imx_uart_7_config, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &uart_imx_driver_api); @@ -520,11 +520,11 @@ DEVICE_AND_API_INIT(uart_7, CONFIG_UART_IMX_UART_7_NAME, &uart_imx_init, #ifdef CONFIG_UART_INTERRUPT_DRIVEN static void irq_config_func_7(struct device *dev) { - IRQ_CONNECT(CONFIG_UART_IMX_UART_7_IRQ_NUM, - CONFIG_UART_IMX_UART_7_IRQ_PRI, + IRQ_CONNECT(DT_UART_IMX_UART_7_IRQ_NUM, + DT_UART_IMX_UART_7_IRQ_PRI, uart_imx_isr, DEVICE_GET(uart_7), 0); - irq_enable(CONFIG_UART_IMX_UART_7_IRQ_NUM); + irq_enable(DT_UART_IMX_UART_7_IRQ_NUM); } #endif diff --git a/drivers/serial/uart_mcux.c b/drivers/serial/uart_mcux.c index a61080988f1..b6d13ca9f79 100644 --- a/drivers/serial/uart_mcux.c +++ b/drivers/serial/uart_mcux.c @@ -288,9 +288,9 @@ static void uart_mcux_config_func_0(struct device *dev); static const struct uart_mcux_config uart_mcux_0_config = { .base = UART0, - .clock_name = CONFIG_UART_MCUX_0_CLOCK_NAME, - .clock_subsys = (clock_control_subsys_t)CONFIG_UART_MCUX_0_CLOCK_SUBSYS, - .baud_rate = CONFIG_UART_MCUX_0_BAUD_RATE, + .clock_name = DT_UART_MCUX_0_CLOCK_NAME, + .clock_subsys = (clock_control_subsys_t)DT_UART_MCUX_0_CLOCK_SUBSYS, + .baud_rate = DT_UART_MCUX_0_BAUD_RATE, #ifdef CONFIG_UART_INTERRUPT_DRIVEN .irq_config_func = uart_mcux_config_func_0, #endif @@ -298,7 +298,7 @@ static const struct uart_mcux_config uart_mcux_0_config = { static struct uart_mcux_data uart_mcux_0_data; -DEVICE_AND_API_INIT(uart_0, CONFIG_UART_MCUX_0_NAME, +DEVICE_AND_API_INIT(uart_0, DT_UART_MCUX_0_NAME, &uart_mcux_init, &uart_mcux_0_data, &uart_mcux_0_config, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, @@ -307,17 +307,17 @@ DEVICE_AND_API_INIT(uart_0, CONFIG_UART_MCUX_0_NAME, #ifdef CONFIG_UART_INTERRUPT_DRIVEN static void uart_mcux_config_func_0(struct device *dev) { - IRQ_CONNECT(CONFIG_UART_MCUX_0_IRQ_STATUS, - CONFIG_UART_MCUX_0_IRQ_STATUS_PRI, + IRQ_CONNECT(DT_UART_MCUX_0_IRQ_STATUS, + DT_UART_MCUX_0_IRQ_STATUS_PRI, uart_mcux_isr, DEVICE_GET(uart_0), 0); - irq_enable(CONFIG_UART_MCUX_0_IRQ_STATUS); + irq_enable(DT_UART_MCUX_0_IRQ_STATUS); - IRQ_CONNECT(CONFIG_UART_MCUX_0_IRQ_ERROR, - CONFIG_UART_MCUX_0_IRQ_ERROR_PRI, + IRQ_CONNECT(DT_UART_MCUX_0_IRQ_ERROR, + DT_UART_MCUX_0_IRQ_ERROR_PRI, uart_mcux_isr, DEVICE_GET(uart_0), 0); - irq_enable(CONFIG_UART_MCUX_0_IRQ_ERROR); + irq_enable(DT_UART_MCUX_0_IRQ_ERROR); } #endif @@ -331,9 +331,9 @@ static void uart_mcux_config_func_1(struct device *dev); static const struct uart_mcux_config uart_mcux_1_config = { .base = UART1, - .clock_name = CONFIG_UART_MCUX_1_CLOCK_NAME, - .clock_subsys = (clock_control_subsys_t)CONFIG_UART_MCUX_1_CLOCK_SUBSYS, - .baud_rate = CONFIG_UART_MCUX_1_BAUD_RATE, + .clock_name = DT_UART_MCUX_1_CLOCK_NAME, + .clock_subsys = (clock_control_subsys_t)DT_UART_MCUX_1_CLOCK_SUBSYS, + .baud_rate = DT_UART_MCUX_1_BAUD_RATE, #ifdef CONFIG_UART_INTERRUPT_DRIVEN .irq_config_func = uart_mcux_config_func_1, #endif @@ -341,7 +341,7 @@ static const struct uart_mcux_config uart_mcux_1_config = { static struct uart_mcux_data uart_mcux_1_data; -DEVICE_AND_API_INIT(uart_1, CONFIG_UART_MCUX_1_NAME, +DEVICE_AND_API_INIT(uart_1, DT_UART_MCUX_1_NAME, &uart_mcux_init, &uart_mcux_1_data, &uart_mcux_1_config, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, @@ -350,17 +350,17 @@ DEVICE_AND_API_INIT(uart_1, CONFIG_UART_MCUX_1_NAME, #ifdef CONFIG_UART_INTERRUPT_DRIVEN static void uart_mcux_config_func_1(struct device *dev) { - IRQ_CONNECT(CONFIG_UART_MCUX_1_IRQ_STATUS, - CONFIG_UART_MCUX_1_IRQ_STATUS_PRI, + IRQ_CONNECT(DT_UART_MCUX_1_IRQ_STATUS, + DT_UART_MCUX_1_IRQ_STATUS_PRI, uart_mcux_isr, DEVICE_GET(uart_1), 0); - irq_enable(CONFIG_UART_MCUX_1_IRQ_STATUS); + irq_enable(DT_UART_MCUX_1_IRQ_STATUS); - IRQ_CONNECT(CONFIG_UART_MCUX_1_IRQ_ERROR, - CONFIG_UART_MCUX_1_IRQ_ERROR_PRI, + IRQ_CONNECT(DT_UART_MCUX_1_IRQ_ERROR, + DT_UART_MCUX_1_IRQ_ERROR_PRI, uart_mcux_isr, DEVICE_GET(uart_1), 0); - irq_enable(CONFIG_UART_MCUX_1_IRQ_ERROR); + irq_enable(DT_UART_MCUX_1_IRQ_ERROR); } #endif @@ -374,9 +374,9 @@ static void uart_mcux_config_func_2(struct device *dev); static const struct uart_mcux_config uart_mcux_2_config = { .base = UART2, - .clock_name = CONFIG_UART_MCUX_2_CLOCK_NAME, - .clock_subsys = (clock_control_subsys_t)CONFIG_UART_MCUX_2_CLOCK_SUBSYS, - .baud_rate = CONFIG_UART_MCUX_2_BAUD_RATE, + .clock_name = DT_UART_MCUX_2_CLOCK_NAME, + .clock_subsys = (clock_control_subsys_t)DT_UART_MCUX_2_CLOCK_SUBSYS, + .baud_rate = DT_UART_MCUX_2_BAUD_RATE, #ifdef CONFIG_UART_INTERRUPT_DRIVEN .irq_config_func = uart_mcux_config_func_2, #endif @@ -384,7 +384,7 @@ static const struct uart_mcux_config uart_mcux_2_config = { static struct uart_mcux_data uart_mcux_2_data; -DEVICE_AND_API_INIT(uart_2, CONFIG_UART_MCUX_2_NAME, +DEVICE_AND_API_INIT(uart_2, DT_UART_MCUX_2_NAME, &uart_mcux_init, &uart_mcux_2_data, &uart_mcux_2_config, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, @@ -393,17 +393,17 @@ DEVICE_AND_API_INIT(uart_2, CONFIG_UART_MCUX_2_NAME, #ifdef CONFIG_UART_INTERRUPT_DRIVEN static void uart_mcux_config_func_2(struct device *dev) { - IRQ_CONNECT(CONFIG_UART_MCUX_2_IRQ_STATUS, - CONFIG_UART_MCUX_2_IRQ_STATUS_PRI, + IRQ_CONNECT(DT_UART_MCUX_2_IRQ_STATUS, + DT_UART_MCUX_2_IRQ_STATUS_PRI, uart_mcux_isr, DEVICE_GET(uart_2), 0); - irq_enable(CONFIG_UART_MCUX_2_IRQ_STATUS); + irq_enable(DT_UART_MCUX_2_IRQ_STATUS); - IRQ_CONNECT(CONFIG_UART_MCUX_2_IRQ_ERROR, - CONFIG_UART_MCUX_2_IRQ_ERROR_PRI, + IRQ_CONNECT(DT_UART_MCUX_2_IRQ_ERROR, + DT_UART_MCUX_2_IRQ_ERROR_PRI, uart_mcux_isr, DEVICE_GET(uart_2), 0); - irq_enable(CONFIG_UART_MCUX_2_IRQ_ERROR); + irq_enable(DT_UART_MCUX_2_IRQ_ERROR); } #endif @@ -417,9 +417,9 @@ static void uart_mcux_config_func_3(struct device *dev); static const struct uart_mcux_config uart_mcux_3_config = { .base = UART3, - .clock_name = CONFIG_UART_MCUX_3_CLOCK_NAME, - .clock_subsys = (clock_control_subsys_t)CONFIG_UART_MCUX_3_CLOCK_SUBSYS, - .baud_rate = CONFIG_UART_MCUX_3_BAUD_RATE, + .clock_name = DT_UART_MCUX_3_CLOCK_NAME, + .clock_subsys = (clock_control_subsys_t)DT_UART_MCUX_3_CLOCK_SUBSYS, + .baud_rate = DT_UART_MCUX_3_BAUD_RATE, #ifdef CONFIG_UART_INTERRUPT_DRIVEN .irq_config_func = uart_mcux_config_func_3, #endif @@ -427,7 +427,7 @@ static const struct uart_mcux_config uart_mcux_3_config = { static struct uart_mcux_data uart_mcux_3_data; -DEVICE_AND_API_INIT(uart_3, CONFIG_UART_MCUX_3_NAME, +DEVICE_AND_API_INIT(uart_3, DT_UART_MCUX_3_NAME, &uart_mcux_init, &uart_mcux_3_data, &uart_mcux_3_config, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, @@ -436,17 +436,17 @@ DEVICE_AND_API_INIT(uart_3, CONFIG_UART_MCUX_3_NAME, #ifdef CONFIG_UART_INTERRUPT_DRIVEN static void uart_mcux_config_func_3(struct device *dev) { - IRQ_CONNECT(CONFIG_UART_MCUX_3_IRQ_STATUS, - CONFIG_UART_MCUX_3_IRQ_STATUS_PRI, + IRQ_CONNECT(DT_UART_MCUX_3_IRQ_STATUS, + DT_UART_MCUX_3_IRQ_STATUS_PRI, uart_mcux_isr, DEVICE_GET(uart_3), 0); - irq_enable(CONFIG_UART_MCUX_3_IRQ_STATUS); + irq_enable(DT_UART_MCUX_3_IRQ_STATUS); - IRQ_CONNECT(CONFIG_UART_MCUX_3_IRQ_ERROR, - CONFIG_UART_MCUX_3_IRQ_ERROR_PRI, + IRQ_CONNECT(DT_UART_MCUX_3_IRQ_ERROR, + DT_UART_MCUX_3_IRQ_ERROR_PRI, uart_mcux_isr, DEVICE_GET(uart_3), 0); - irq_enable(CONFIG_UART_MCUX_3_IRQ_ERROR); + irq_enable(DT_UART_MCUX_3_IRQ_ERROR); } #endif @@ -460,9 +460,9 @@ static void uart_mcux_config_func_4(struct device *dev); static const struct uart_mcux_config uart_mcux_4_config = { .base = UART4, - .clock_name = CONFIG_UART_MCUX_4_CLOCK_NAME, - .clock_subsys = (clock_control_subsys_t)CONFIG_UART_MCUX_4_CLOCK_SUBSYS, - .baud_rate = CONFIG_UART_MCUX_4_BAUD_RATE, + .clock_name = DT_UART_MCUX_4_CLOCK_NAME, + .clock_subsys = (clock_control_subsys_t)DT_UART_MCUX_4_CLOCK_SUBSYS, + .baud_rate = DT_UART_MCUX_4_BAUD_RATE, #ifdef CONFIG_UART_INTERRUPT_DRIVEN .irq_config_func = uart_mcux_config_func_4, #endif @@ -470,7 +470,7 @@ static const struct uart_mcux_config uart_mcux_4_config = { static struct uart_mcux_data uart_mcux_4_data; -DEVICE_AND_API_INIT(uart_4, CONFIG_UART_MCUX_4_NAME, +DEVICE_AND_API_INIT(uart_4, DT_UART_MCUX_4_NAME, &uart_mcux_init, &uart_mcux_4_data, &uart_mcux_4_config, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, @@ -479,17 +479,17 @@ DEVICE_AND_API_INIT(uart_4, CONFIG_UART_MCUX_4_NAME, #ifdef CONFIG_UART_INTERRUPT_DRIVEN static void uart_mcux_config_func_4(struct device *dev) { - IRQ_CONNECT(CONFIG_UART_MCUX_4_IRQ_STATUS, - CONFIG_UART_MCUX_4_IRQ_STATUS_PRI, + IRQ_CONNECT(DT_UART_MCUX_4_IRQ_STATUS, + DT_UART_MCUX_4_IRQ_STATUS_PRI, uart_mcux_isr, DEVICE_GET(uart_4), 0); - irq_enable(CONFIG_UART_MCUX_4_IRQ_STATUS); + irq_enable(DT_UART_MCUX_4_IRQ_STATUS); - IRQ_CONNECT(CONFIG_UART_MCUX_4_IRQ_ERROR, - CONFIG_UART_MCUX_4_IRQ_ERROR_PRI, + IRQ_CONNECT(DT_UART_MCUX_4_IRQ_ERROR, + DT_UART_MCUX_4_IRQ_ERROR_PRI, uart_mcux_isr, DEVICE_GET(uart_4), 0); - irq_enable(CONFIG_UART_MCUX_4_IRQ_ERROR); + irq_enable(DT_UART_MCUX_4_IRQ_ERROR); } #endif @@ -503,9 +503,9 @@ static void uart_mcux_config_func_5(struct device *dev); static const struct uart_mcux_config uart_mcux_5_config = { .base = UART5, - .clock_name = CONFIG_UART_MCUX_5_CLOCK_NAME, - .clock_subsys = (clock_control_subsys_t)CONFIG_UART_MCUX_5_CLOCK_SUBSYS, - .baud_rate = CONFIG_UART_MCUX_5_BAUD_RATE, + .clock_name = DT_UART_MCUX_5_CLOCK_NAME, + .clock_subsys = (clock_control_subsys_t)DT_UART_MCUX_5_CLOCK_SUBSYS, + .baud_rate = DT_UART_MCUX_5_BAUD_RATE, #ifdef CONFIG_UART_INTERRUPT_DRIVEN .irq_config_func = uart_mcux_config_func_5, #endif @@ -513,7 +513,7 @@ static const struct uart_mcux_config uart_mcux_5_config = { static struct uart_mcux_data uart_mcux_5_data; -DEVICE_AND_API_INIT(uart_5, CONFIG_UART_MCUX_5_NAME, +DEVICE_AND_API_INIT(uart_5, DT_UART_MCUX_5_NAME, &uart_mcux_init, &uart_mcux_5_data, &uart_mcux_5_config, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, @@ -522,17 +522,17 @@ DEVICE_AND_API_INIT(uart_5, CONFIG_UART_MCUX_5_NAME, #ifdef CONFIG_UART_INTERRUPT_DRIVEN static void uart_mcux_config_func_5(struct device *dev) { - IRQ_CONNECT(CONFIG_UART_MCUX_5_IRQ_STATUS, - CONFIG_UART_MCUX_5_IRQ_STATUS_PRI, + IRQ_CONNECT(DT_UART_MCUX_5_IRQ_STATUS, + DT_UART_MCUX_5_IRQ_STATUS_PRI, uart_mcux_isr, DEVICE_GET(uart_5), 0); - irq_enable(CONFIG_UART_MCUX_5_IRQ_STATUS); + irq_enable(DT_UART_MCUX_5_IRQ_STATUS); - IRQ_CONNECT(CONFIG_UART_MCUX_5_IRQ_ERROR, - CONFIG_UART_MCUX_5_IRQ_ERROR_PRI, + IRQ_CONNECT(DT_UART_MCUX_5_IRQ_ERROR, + DT_UART_MCUX_5_IRQ_ERROR_PRI, uart_mcux_isr, DEVICE_GET(uart_5), 0); - irq_enable(CONFIG_UART_MCUX_5_IRQ_ERROR); + irq_enable(DT_UART_MCUX_5_IRQ_ERROR); } #endif diff --git a/drivers/serial/uart_mcux_lpsci.c b/drivers/serial/uart_mcux_lpsci.c index 3c1d503ab99..c7b16dc016b 100644 --- a/drivers/serial/uart_mcux_lpsci.c +++ b/drivers/serial/uart_mcux_lpsci.c @@ -292,9 +292,9 @@ static void mcux_lpsci_config_func_0(struct device *dev); static const struct mcux_lpsci_config mcux_lpsci_0_config = { .base = UART0, - .clock_name = CONFIG_UART_MCUX_LPSCI_0_CLOCK_NAME, + .clock_name = DT_UART_MCUX_LPSCI_0_CLOCK_NAME, .clock_subsys = - (clock_control_subsys_t)CONFIG_UART_MCUX_LPSCI_0_CLOCK_SUBSYS, + (clock_control_subsys_t)DT_UART_MCUX_LPSCI_0_CLOCK_SUBSYS, .baud_rate = DT_NXP_KINETIS_LPSCI_4006A000_CURRENT_SPEED, #ifdef CONFIG_UART_INTERRUPT_DRIVEN .irq_config_func = mcux_lpsci_config_func_0, @@ -303,7 +303,7 @@ static const struct mcux_lpsci_config mcux_lpsci_0_config = { static struct mcux_lpsci_data mcux_lpsci_0_data; -DEVICE_AND_API_INIT(uart_0, CONFIG_UART_MCUX_LPSCI_0_NAME, +DEVICE_AND_API_INIT(uart_0, DT_UART_MCUX_LPSCI_0_NAME, &mcux_lpsci_init, &mcux_lpsci_0_data, &mcux_lpsci_0_config, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, diff --git a/drivers/serial/uart_mcux_lpuart.c b/drivers/serial/uart_mcux_lpuart.c index 2d280bd0fd2..f7fe5188928 100644 --- a/drivers/serial/uart_mcux_lpuart.c +++ b/drivers/serial/uart_mcux_lpuart.c @@ -292,10 +292,10 @@ static void mcux_lpuart_config_func_0(struct device *dev); static const struct mcux_lpuart_config mcux_lpuart_0_config = { .base = LPUART0, - .clock_name = CONFIG_UART_MCUX_LPUART_0_CLOCK_NAME, + .clock_name = DT_UART_MCUX_LPUART_0_CLOCK_NAME, .clock_subsys = - (clock_control_subsys_t)CONFIG_UART_MCUX_LPUART_0_CLOCK_SUBSYS, - .baud_rate = CONFIG_UART_MCUX_LPUART_0_BAUD_RATE, + (clock_control_subsys_t)DT_UART_MCUX_LPUART_0_CLOCK_SUBSYS, + .baud_rate = DT_UART_MCUX_LPUART_0_BAUD_RATE, #ifdef CONFIG_UART_INTERRUPT_DRIVEN .irq_config_func = mcux_lpuart_config_func_0, #endif @@ -303,7 +303,7 @@ static const struct mcux_lpuart_config mcux_lpuart_0_config = { static struct mcux_lpuart_data mcux_lpuart_0_data; -DEVICE_AND_API_INIT(uart_0, CONFIG_UART_MCUX_LPUART_0_NAME, +DEVICE_AND_API_INIT(uart_0, DT_UART_MCUX_LPUART_0_NAME, &mcux_lpuart_init, &mcux_lpuart_0_data, &mcux_lpuart_0_config, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, @@ -312,11 +312,11 @@ DEVICE_AND_API_INIT(uart_0, CONFIG_UART_MCUX_LPUART_0_NAME, #ifdef CONFIG_UART_INTERRUPT_DRIVEN static void mcux_lpuart_config_func_0(struct device *dev) { - IRQ_CONNECT(CONFIG_UART_MCUX_LPUART_0_IRQ, - CONFIG_UART_MCUX_LPUART_0_IRQ_PRI, + IRQ_CONNECT(DT_UART_MCUX_LPUART_0_IRQ, + DT_UART_MCUX_LPUART_0_IRQ_PRI, mcux_lpuart_isr, DEVICE_GET(uart_0), 0); - irq_enable(CONFIG_UART_MCUX_LPUART_0_IRQ); + irq_enable(DT_UART_MCUX_LPUART_0_IRQ); } #endif @@ -329,11 +329,11 @@ static void mcux_lpuart_config_func_1(struct device *dev); #endif static const struct mcux_lpuart_config mcux_lpuart_1_config = { - .base = (LPUART_Type *) CONFIG_UART_MCUX_LPUART_1_BASE_ADDRESS, - .clock_name = CONFIG_UART_MCUX_LPUART_1_CLOCK_NAME, + .base = (LPUART_Type *) DT_UART_MCUX_LPUART_1_BASE_ADDRESS, + .clock_name = DT_UART_MCUX_LPUART_1_CLOCK_NAME, .clock_subsys = - (clock_control_subsys_t)CONFIG_UART_MCUX_LPUART_1_CLOCK_SUBSYS, - .baud_rate = CONFIG_UART_MCUX_LPUART_1_BAUD_RATE, + (clock_control_subsys_t)DT_UART_MCUX_LPUART_1_CLOCK_SUBSYS, + .baud_rate = DT_UART_MCUX_LPUART_1_BAUD_RATE, #ifdef CONFIG_UART_INTERRUPT_DRIVEN .irq_config_func = mcux_lpuart_config_func_1, #endif @@ -341,7 +341,7 @@ static const struct mcux_lpuart_config mcux_lpuart_1_config = { static struct mcux_lpuart_data mcux_lpuart_1_data; -DEVICE_AND_API_INIT(uart_1, CONFIG_UART_MCUX_LPUART_1_NAME, +DEVICE_AND_API_INIT(uart_1, DT_UART_MCUX_LPUART_1_NAME, &mcux_lpuart_init, &mcux_lpuart_1_data, &mcux_lpuart_1_config, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, @@ -350,11 +350,11 @@ DEVICE_AND_API_INIT(uart_1, CONFIG_UART_MCUX_LPUART_1_NAME, #ifdef CONFIG_UART_INTERRUPT_DRIVEN static void mcux_lpuart_config_func_1(struct device *dev) { - IRQ_CONNECT(CONFIG_UART_MCUX_LPUART_1_IRQ, - CONFIG_UART_MCUX_LPUART_1_IRQ_PRI, + IRQ_CONNECT(DT_UART_MCUX_LPUART_1_IRQ, + DT_UART_MCUX_LPUART_1_IRQ_PRI, mcux_lpuart_isr, DEVICE_GET(uart_1), 0); - irq_enable(CONFIG_UART_MCUX_LPUART_1_IRQ); + irq_enable(DT_UART_MCUX_LPUART_1_IRQ); } #endif @@ -405,11 +405,11 @@ static void mcux_lpuart_config_func_3(struct device *dev); #endif static const struct mcux_lpuart_config mcux_lpuart_3_config = { - .base = (LPUART_Type *) CONFIG_UART_MCUX_LPUART_3_BASE_ADDRESS, - .clock_name = CONFIG_UART_MCUX_LPUART_3_CLOCK_NAME, + .base = (LPUART_Type *) DT_UART_MCUX_LPUART_3_BASE_ADDRESS, + .clock_name = DT_UART_MCUX_LPUART_3_CLOCK_NAME, .clock_subsys = - (clock_control_subsys_t)CONFIG_UART_MCUX_LPUART_3_CLOCK_SUBSYS, - .baud_rate = CONFIG_UART_MCUX_LPUART_3_BAUD_RATE, + (clock_control_subsys_t)DT_UART_MCUX_LPUART_3_CLOCK_SUBSYS, + .baud_rate = DT_UART_MCUX_LPUART_3_BAUD_RATE, #ifdef CONFIG_UART_INTERRUPT_DRIVEN .irq_config_func = mcux_lpuart_config_func_3, #endif @@ -417,7 +417,7 @@ static const struct mcux_lpuart_config mcux_lpuart_3_config = { static struct mcux_lpuart_data mcux_lpuart_3_data; -DEVICE_AND_API_INIT(uart_3, CONFIG_UART_MCUX_LPUART_3_NAME, +DEVICE_AND_API_INIT(uart_3, DT_UART_MCUX_LPUART_3_NAME, &mcux_lpuart_init, &mcux_lpuart_3_data, &mcux_lpuart_3_config, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, @@ -426,11 +426,11 @@ DEVICE_AND_API_INIT(uart_3, CONFIG_UART_MCUX_LPUART_3_NAME, #ifdef CONFIG_UART_INTERRUPT_DRIVEN static void mcux_lpuart_config_func_3(struct device *dev) { - IRQ_CONNECT(CONFIG_UART_MCUX_LPUART_3_IRQ, - CONFIG_UART_MCUX_LPUART_3_IRQ_PRI, + IRQ_CONNECT(DT_UART_MCUX_LPUART_3_IRQ, + DT_UART_MCUX_LPUART_3_IRQ_PRI, mcux_lpuart_isr, DEVICE_GET(uart_3), 0); - irq_enable(CONFIG_UART_MCUX_LPUART_3_IRQ); + irq_enable(DT_UART_MCUX_LPUART_3_IRQ); } #endif diff --git a/drivers/serial/uart_miv.c b/drivers/serial/uart_miv.c index 9de9e6aef66..ebf1572125a 100644 --- a/drivers/serial/uart_miv.c +++ b/drivers/serial/uart_miv.c @@ -390,16 +390,16 @@ static void uart_miv_irq_cfg_func_0(struct device *dev); #endif static const struct uart_miv_device_config uart_miv_dev_cfg_0 = { - .uart_addr = CONFIG_MIV_UART_0_BASE_ADDR, - .sys_clk_freq = CONFIG_MIV_UART_0_CLOCK_FREQUENCY, + .uart_addr = DT_MIV_UART_0_BASE_ADDR, + .sys_clk_freq = DT_MIV_UART_0_CLOCK_FREQUENCY, .line_config = MIV_UART_0_LINECFG, - .baud_rate = CONFIG_MIV_UART_0_BAUD_RATE, + .baud_rate = DT_MIV_UART_0_BAUD_RATE, #ifdef CONFIG_UART_INTERRUPT_DRIVEN .cfg_func = uart_miv_irq_cfg_func_0, #endif }; -DEVICE_AND_API_INIT(uart_miv_0, CONFIG_MIV_UART_0_NAME, +DEVICE_AND_API_INIT(uart_miv_0, DT_MIV_UART_0_NAME, uart_miv_init, &uart_miv_data_0, &uart_miv_dev_cfg_0, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, (void *)&uart_miv_driver_api); diff --git a/drivers/serial/uart_msp432p4xx.c b/drivers/serial/uart_msp432p4xx.c index 480fa7bed52..de6fcae2d4d 100644 --- a/drivers/serial/uart_msp432p4xx.c +++ b/drivers/serial/uart_msp432p4xx.c @@ -38,7 +38,7 @@ static void uart_msp432p4xx_isr(void *arg); #endif static const struct uart_device_config uart_msp432p4xx_dev_cfg_0 = { - .base = (void *)CONFIG_UART_MSP432P4XX_BASE_ADDRESS, + .base = (void *)DT_UART_MSP432P4XX_BASE_ADDRESS, .sys_clk_freq = CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC, }; @@ -133,7 +133,7 @@ static int uart_msp432p4xx_init(struct device *dev) UartConfig.overSampling = EUSCI_A_UART_OVERSAMPLING_BAUDRATE_GENERATION; /* Baud rate settings calculated for 48MHz */ - err = baudrate_set(&UartConfig, CONFIG_UART_MSP432P4XX_BAUD_RATE); + err = baudrate_set(&UartConfig, DT_UART_MSP432P4XX_BAUD_RATE); if (err) { return err; } @@ -360,7 +360,7 @@ static const struct uart_driver_api uart_msp432p4xx_driver_api = { #endif /* CONFIG_UART_INTERRUPT_DRIVEN */ }; -DEVICE_AND_API_INIT(uart_msp432p4xx_0, CONFIG_UART_MSP432P4XX_NAME, +DEVICE_AND_API_INIT(uart_msp432p4xx_0, DT_UART_MSP432P4XX_NAME, uart_msp432p4xx_init, &uart_msp432p4xx_dev_data_0, &uart_msp432p4xx_dev_cfg_0, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, diff --git a/drivers/serial/uart_nrfx_uart.c b/drivers/serial/uart_nrfx_uart.c index a520b41c9c6..56b902be470 100644 --- a/drivers/serial/uart_nrfx_uart.c +++ b/drivers/serial/uart_nrfx_uart.c @@ -13,7 +13,7 @@ #include -static NRF_UART_Type *const uart0_addr = (NRF_UART_Type *)CONFIG_UART_0_BASE; +static NRF_UART_Type *const uart0_addr = (NRF_UART_Type *)DT_UART_0_BASE; #ifdef CONFIG_UART_0_INTERRUPT_DRIVEN @@ -281,7 +281,7 @@ static void uart_nrfx_irq_tx_enable(struct device *dev) /* Due to HW limitation first TXDRDY interrupt shall be * triggered by the software. */ - NVIC_SetPendingIRQ(CONFIG_UART_0_IRQ_NUM); + NVIC_SetPendingIRQ(DT_UART_0_IRQ_NUM); } irq_unlock(key); } @@ -404,33 +404,33 @@ static int uart_nrfx_init(struct device *dev) /* Setting default height state of the TX PIN to avoid glitches * on the line during peripheral activation/deactivation. */ - nrf_gpio_pin_write(CONFIG_UART_0_TX_PIN, 1); - nrf_gpio_cfg_output(CONFIG_UART_0_TX_PIN); + nrf_gpio_pin_write(DT_UART_0_TX_PIN, 1); + nrf_gpio_cfg_output(DT_UART_0_TX_PIN); - nrf_gpio_cfg_input(CONFIG_UART_0_RX_PIN, NRF_GPIO_PIN_NOPULL); + nrf_gpio_cfg_input(DT_UART_0_RX_PIN, NRF_GPIO_PIN_NOPULL); nrf_uart_txrx_pins_set(uart0_addr, - CONFIG_UART_0_TX_PIN, - CONFIG_UART_0_RX_PIN); + DT_UART_0_TX_PIN, + DT_UART_0_RX_PIN); #ifdef CONFIG_UART_0_NRF_FLOW_CONTROL -#ifndef CONFIG_UART_0_RTS_PIN +#ifndef DT_UART_0_RTS_PIN #error Flow control for UART0 is enabled, but RTS pin is not defined. #endif -#ifndef CONFIG_UART_0_CTS_PIN +#ifndef DT_UART_0_CTS_PIN #error Flow control for UART0 is enabled, but CTS pin is not defined. #endif /* Setting default height state of the RTS PIN to avoid glitches * on the line during peripheral activation/deactivation. */ - nrf_gpio_pin_write(CONFIG_UART_0_RTS_PIN, 1); - nrf_gpio_cfg_output(CONFIG_UART_0_RTS_PIN); + nrf_gpio_pin_write(DT_UART_0_RTS_PIN, 1); + nrf_gpio_cfg_output(DT_UART_0_RTS_PIN); - nrf_gpio_cfg_input(CONFIG_UART_0_CTS_PIN, NRF_GPIO_PIN_NOPULL); + nrf_gpio_cfg_input(DT_UART_0_CTS_PIN, NRF_GPIO_PIN_NOPULL); nrf_uart_hwfc_pins_set(uart0_addr, - CONFIG_UART_0_RTS_PIN, - CONFIG_UART_0_CTS_PIN); + DT_UART_0_RTS_PIN, + DT_UART_0_CTS_PIN); #endif /* CONFIG_UART_0_NRF_FLOW_CONTROL */ nrf_uart_configure(uart0_addr, @@ -446,7 +446,7 @@ static int uart_nrfx_init(struct device *dev) #endif /* CONFIG_UART_0_NRF_PARITY_BIT */ /* Set baud rate */ - err = baudrate_set(dev, CONFIG_UART_0_BAUD_RATE); + err = baudrate_set(dev, DT_UART_0_BAUD_RATE); if (err) { return err; } @@ -467,12 +467,12 @@ static int uart_nrfx_init(struct device *dev) */ uart_sw_event_txdrdy = 1; - IRQ_CONNECT(CONFIG_UART_0_IRQ_NUM, - CONFIG_UART_0_IRQ_PRI, + IRQ_CONNECT(DT_UART_0_IRQ_NUM, + DT_UART_0_IRQ_PRI, uart_nrfx_isr, DEVICE_GET(uart_nrfx_uart0), 0); - irq_enable(CONFIG_UART_0_IRQ_NUM); + irq_enable(DT_UART_0_IRQ_NUM); #endif return 0; @@ -540,7 +540,7 @@ static int uart_nrfx_pm_control(struct device *dev, #endif /* CONFIG_DEVICE_POWER_MANAGEMENT */ DEVICE_DEFINE(uart_nrfx_uart0, - CONFIG_UART_0_NAME, + DT_UART_0_NAME, uart_nrfx_init, uart_nrfx_pm_control, NULL, diff --git a/drivers/serial/uart_nrfx_uarte.c b/drivers/serial/uart_nrfx_uarte.c index 95b0b29b695..5d2b2896afe 100644 --- a/drivers/serial/uart_nrfx_uarte.c +++ b/drivers/serial/uart_nrfx_uarte.c @@ -509,17 +509,17 @@ static int uarte_instance_init(struct device *dev, UARTE_##idx##_DATA_INIT \ }; \ static const struct uarte_nrfx_config uarte_##idx##_config = { \ - .uarte_regs = (NRF_UARTE_Type *)CONFIG_UART_##idx##_BASE, \ + .uarte_regs = (NRF_UARTE_Type *)DT_UART_##idx##_BASE, \ UARTE_##idx##_CONFIG_INIT \ }; \ static int uarte_##idx##_init(struct device *dev) \ { \ const struct uarte_init_config init_config = { \ - .pseltxd = CONFIG_UART_##idx##_TX_PIN, \ - .pselrxd = CONFIG_UART_##idx##_RX_PIN, \ + .pseltxd = DT_UART_##idx##_TX_PIN, \ + .pselrxd = DT_UART_##idx##_RX_PIN, \ UARTE_##idx##_NRF_HWFC_CONFIG \ .parity = UARTE_##idx##_NRF_PARITY_BIT, \ - .baudrate = CONFIG_UART_##idx##_BAUD_RATE \ + .baudrate = DT_UART_##idx##_BAUD_RATE \ }; \ UARTE_##idx##_INTERRUPTS_INIT(); \ return uarte_instance_init(dev, \ @@ -527,7 +527,7 @@ static int uarte_instance_init(struct device *dev, UARTE_##idx##_INTERRUPT_DRIVEN); \ } \ DEVICE_AND_API_INIT(uart_nrfx_uarte##idx, \ - CONFIG_UART_##idx##_NAME, \ + DT_UART_##idx##_NAME, \ uarte_##idx##_init, \ &uarte_##idx##_data, \ &uarte_##idx##_config, \ @@ -536,8 +536,8 @@ static int uarte_instance_init(struct device *dev, &uart_nrfx_uarte_driver_api) #define UARTE_NRF_HWFC_ENABLED(idx) \ - .pselcts = CONFIG_UART_##idx##_CTS_PIN, \ - .pselrts = CONFIG_UART_##idx##_RTS_PIN, \ + .pselcts = DT_UART_##idx##_CTS_PIN, \ + .pselrts = DT_UART_##idx##_RTS_PIN, \ .hwfc = NRF_UARTE_HWFC_ENABLED, #define UARTE_NRF_HWFC_DISABLED \ .pselcts = NRF_UARTE_PSEL_DISCONNECTED, \ @@ -546,11 +546,11 @@ static int uarte_instance_init(struct device *dev, #define UARTE_NRF_IRQ_ENABLED(idx) \ IRQ_CONNECT(NRFX_IRQ_NUMBER_GET(NRF_UARTE##idx), \ - CONFIG_UART_##idx##_IRQ_PRI, \ + DT_UART_##idx##_IRQ_PRI, \ uarte_nrfx_isr, \ DEVICE_GET(uart_nrfx_uarte##idx), \ 0); \ - irq_enable(CONFIG_UART_##idx##_IRQ_NUM) + irq_enable(DT_UART_##idx##_IRQ_NUM) #define UARTE_TX_BUFFER_SIZE(idx) \ CONFIG_UART_##idx##_NRF_TX_BUFFER_SIZE < \ @@ -584,10 +584,10 @@ static int uarte_instance_init(struct device *dev, #ifdef CONFIG_UART_0_NRF_FLOW_CONTROL #define UARTE_0_NRF_HWFC_CONFIG UARTE_NRF_HWFC_ENABLED(0) - #ifndef CONFIG_UART_0_RTS_PIN + #ifndef DT_UART_0_RTS_PIN #error Flow control for UARTE0 is enabled, but RTS pin is not defined. #endif - #ifndef CONFIG_UART_0_CTS_PIN + #ifndef DT_UART_0_CTS_PIN #error Flow control for UARTE0 is enabled, but CTS pin is not defined. #endif #else @@ -620,10 +620,10 @@ static int uarte_instance_init(struct device *dev, #ifdef CONFIG_UART_1_NRF_FLOW_CONTROL #define UARTE_1_NRF_HWFC_CONFIG UARTE_NRF_HWFC_ENABLED(1) - #ifndef CONFIG_UART_1_RTS_PIN + #ifndef DT_UART_1_RTS_PIN #error Flow control for UARTE1 is enabled, but RTS pin is not defined. #endif - #ifndef CONFIG_UART_1_CTS_PIN + #ifndef DT_UART_1_CTS_PIN #error Flow control for UARTE1 is enabled, but CTS pin is not defined. #endif #else diff --git a/drivers/serial/uart_ns16550.c b/drivers/serial/uart_ns16550.c index 0e5a5139405..703db7ea98b 100644 --- a/drivers/serial/uart_ns16550.c +++ b/drivers/serial/uart_ns16550.c @@ -752,7 +752,7 @@ static void irq_config_func_0(struct device *port); #endif static const struct uart_ns16550_device_config uart_ns16550_dev_cfg_0 = { - .sys_clk_freq = CONFIG_UART_NS16550_PORT_0_CLK_FREQ, + .sys_clk_freq = DT_UART_NS16550_PORT_0_CLK_FREQ, #ifdef CONFIG_UART_INTERRUPT_DRIVEN .irq_config_func = irq_config_func_0, @@ -770,7 +770,7 @@ static struct uart_ns16550_dev_data_t uart_ns16550_dev_data_0 = { .pci_dev.bar = UART_NS16550_PORT_0_PCI_BAR, #endif /* CONFIG_UART_NS16550_PORT_0_PCI */ - .port = CONFIG_UART_NS16550_PORT_0_BASE_ADDR, + .port = DT_UART_NS16550_PORT_0_BASE_ADDR, .baud_rate = CONFIG_UART_NS16550_PORT_0_BAUD_RATE, .options = CONFIG_UART_NS16550_PORT_0_OPTIONS, @@ -789,11 +789,11 @@ static void irq_config_func_0(struct device *dev) { ARG_UNUSED(dev); - IRQ_CONNECT(CONFIG_UART_NS16550_PORT_0_IRQ, + IRQ_CONNECT(DT_UART_NS16550_PORT_0_IRQ, CONFIG_UART_NS16550_PORT_0_IRQ_PRI, uart_ns16550_isr, DEVICE_GET(uart_ns16550_0), - CONFIG_UART_NS16550_PORT_0_IRQ_FLAGS); - irq_enable(CONFIG_UART_NS16550_PORT_0_IRQ); + DT_UART_NS16550_PORT_0_IRQ_FLAGS); + irq_enable(DT_UART_NS16550_PORT_0_IRQ); } #endif @@ -806,7 +806,7 @@ static void irq_config_func_1(struct device *port); #endif static const struct uart_ns16550_device_config uart_ns16550_dev_cfg_1 = { - .sys_clk_freq = CONFIG_UART_NS16550_PORT_1_CLK_FREQ, + .sys_clk_freq = DT_UART_NS16550_PORT_1_CLK_FREQ, #ifdef CONFIG_UART_INTERRUPT_DRIVEN .irq_config_func = irq_config_func_1, @@ -824,7 +824,7 @@ static struct uart_ns16550_dev_data_t uart_ns16550_dev_data_1 = { .pci_dev.bar = UART_NS16550_PORT_1_PCI_BAR, #endif /* CONFIG_UART_NS16550_PORT_1_PCI */ - .port = CONFIG_UART_NS16550_PORT_1_BASE_ADDR, + .port = DT_UART_NS16550_PORT_1_BASE_ADDR, .baud_rate = CONFIG_UART_NS16550_PORT_1_BAUD_RATE, .options = CONFIG_UART_NS16550_PORT_1_OPTIONS, @@ -843,11 +843,11 @@ static void irq_config_func_1(struct device *dev) { ARG_UNUSED(dev); - IRQ_CONNECT(CONFIG_UART_NS16550_PORT_1_IRQ, + IRQ_CONNECT(DT_UART_NS16550_PORT_1_IRQ, CONFIG_UART_NS16550_PORT_1_IRQ_PRI, uart_ns16550_isr, DEVICE_GET(uart_ns16550_1), - CONFIG_UART_NS16550_PORT_1_IRQ_FLAGS); - irq_enable(CONFIG_UART_NS16550_PORT_1_IRQ); + DT_UART_NS16550_PORT_1_IRQ_FLAGS); + irq_enable(DT_UART_NS16550_PORT_1_IRQ); } #endif @@ -860,7 +860,7 @@ static void irq_config_func_2(struct device *port); #endif static const struct uart_ns16550_device_config uart_ns16550_dev_cfg_2 = { - .sys_clk_freq = CONFIG_UART_NS16550_PORT_2_CLK_FREQ, + .sys_clk_freq = DT_UART_NS16550_PORT_2_CLK_FREQ, #ifdef CONFIG_UART_INTERRUPT_DRIVEN .irq_config_func = irq_config_func_2, @@ -878,8 +878,8 @@ static struct uart_ns16550_dev_data_t uart_ns16550_dev_data_2 = { .pci_dev.bar = UART_NS16550_PORT_2_PCI_BAR, #endif /* CONFIG_UART_NS16550_PORT_2_PCI */ - .port = CONFIG_UART_NS16550_PORT_2_BASE_ADDR, - .baud_rate = CONFIG_UART_NS16550_PORT_2_BAUD_RATE, + .port = DT_UART_NS16550_PORT_2_BASE_ADDR, + .baud_rate = DT_UART_NS16550_PORT_2_BAUD_RATE, .options = CONFIG_UART_NS16550_PORT_2_OPTIONS, #ifdef CONFIG_UART_NS16550_PORT_2_DLF @@ -887,7 +887,7 @@ static struct uart_ns16550_dev_data_t uart_ns16550_dev_data_2 = { #endif }; -DEVICE_AND_API_INIT(uart_ns16550_2, CONFIG_UART_NS16550_PORT_2_NAME, &uart_ns16550_init, +DEVICE_AND_API_INIT(uart_ns16550_2, DT_UART_NS16550_PORT_2_NAME, &uart_ns16550_init, &uart_ns16550_dev_data_2, &uart_ns16550_dev_cfg_2, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &uart_ns16550_driver_api); @@ -897,11 +897,11 @@ static void irq_config_func_2(struct device *dev) { ARG_UNUSED(dev); - IRQ_CONNECT(CONFIG_UART_NS16550_PORT_2_IRQ, - CONFIG_UART_NS16550_PORT_2_IRQ_PRI, + IRQ_CONNECT(DT_UART_NS16550_PORT_2_IRQ, + DT_UART_NS16550_PORT_2_IRQ_PRI, uart_ns16550_isr, DEVICE_GET(uart_ns16550_2), CONFIG_UART_NS16550_PORT_2_IRQ_FLAGS); - irq_enable(CONFIG_UART_NS16550_PORT_2_IRQ); + irq_enable(DT_UART_NS16550_PORT_2_IRQ); } #endif diff --git a/drivers/serial/uart_psoc6.c b/drivers/serial/uart_psoc6.c index 58cbb4184e7..6fe08c3dccd 100644 --- a/drivers/serial/uart_psoc6.c +++ b/drivers/serial/uart_psoc6.c @@ -44,14 +44,14 @@ static const cy_stc_scb_uart_config_t uartConfig = { .irdaInvertRx = false, .irdaEnableLowPowerReceiver = false, - .oversample = CONFIG_UART_PSOC6_CONFIG_OVERSAMPLE, + .oversample = DT_UART_PSOC6_CONFIG_OVERSAMPLE, .enableMsbFirst = false, - .dataWidth = CONFIG_UART_PSOC6_CONFIG_DATAWIDTH, + .dataWidth = DT_UART_PSOC6_CONFIG_DATAWIDTH, .parity = CY_SCB_UART_PARITY_NONE, .stopBits = CY_SCB_UART_STOP_BITS_1, .enableInputFilter = false, - .breakWidth = CONFIG_UART_PSOC6_CONFIG_BREAKWIDTH, + .breakWidth = DT_UART_PSOC6_CONFIG_BREAKWIDTH, .dropOnFrameError = false, .dropOnParityError = false, @@ -91,14 +91,14 @@ static int uart_psoc6_init(struct device *dev) /* Connect assigned divider to be a clock source for UART */ Cy_SysClk_PeriphAssignDivider(config->scb_clock, - CONFIG_UART_PSOC6_UART_CLK_DIV_TYPE, - CONFIG_UART_PSOC6_UART_CLK_DIV_NUMBER); + DT_UART_PSOC6_UART_CLK_DIV_TYPE, + DT_UART_PSOC6_UART_CLK_DIV_NUMBER); - Cy_SysClk_PeriphSetDivider(CONFIG_UART_PSOC6_UART_CLK_DIV_TYPE, - CONFIG_UART_PSOC6_UART_CLK_DIV_NUMBER, - CONFIG_UART_PSOC6_UART_CLK_DIV_VAL); - Cy_SysClk_PeriphEnableDivider(CONFIG_UART_PSOC6_UART_CLK_DIV_TYPE, - CONFIG_UART_PSOC6_UART_CLK_DIV_NUMBER); + Cy_SysClk_PeriphSetDivider(DT_UART_PSOC6_UART_CLK_DIV_TYPE, + DT_UART_PSOC6_UART_CLK_DIV_NUMBER, + DT_UART_PSOC6_UART_CLK_DIV_VAL); + Cy_SysClk_PeriphEnableDivider(DT_UART_PSOC6_UART_CLK_DIV_TYPE, + DT_UART_PSOC6_UART_CLK_DIV_NUMBER); /* Configure UART to operate */ (void) Cy_SCB_UART_Init(config->base, &uartConfig, NULL); @@ -135,16 +135,16 @@ static const struct uart_driver_api uart_psoc6_driver_api = { #ifdef CONFIG_UART_PSOC6_UART_5 static const struct cypress_psoc6_config cypress_psoc6_uart5_config = { - .base = CONFIG_UART_PSOC6_UART_5_BASE_ADDRESS, - .port = CONFIG_UART_PSOC6_UART_5_PORT, - .rx_num = CONFIG_UART_PSOC6_UART_5_RX_NUM, - .tx_num = CONFIG_UART_PSOC6_UART_5_TX_NUM, - .rx_val = CONFIG_UART_PSOC6_UART_5_RX_VAL, - .tx_val = CONFIG_UART_PSOC6_UART_5_TX_VAL, - .scb_clock = CONFIG_UART_PSOC6_UART_5_CLOCK, + .base = DT_UART_PSOC6_UART_5_BASE_ADDRESS, + .port = DT_UART_PSOC6_UART_5_PORT, + .rx_num = DT_UART_PSOC6_UART_5_RX_NUM, + .tx_num = DT_UART_PSOC6_UART_5_TX_NUM, + .rx_val = DT_UART_PSOC6_UART_5_RX_VAL, + .tx_val = DT_UART_PSOC6_UART_5_TX_VAL, + .scb_clock = DT_UART_PSOC6_UART_5_CLOCK, }; -DEVICE_AND_API_INIT(uart_5, CONFIG_UART_PSOC6_UART_5_NAME, +DEVICE_AND_API_INIT(uart_5, DT_UART_PSOC6_UART_5_NAME, uart_psoc6_init, NULL, &cypress_psoc6_uart5_config, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, @@ -153,16 +153,16 @@ DEVICE_AND_API_INIT(uart_5, CONFIG_UART_PSOC6_UART_5_NAME, #ifdef CONFIG_UART_PSOC6_UART_6 static const struct cypress_psoc6_config cypress_psoc6_uart6_config = { - .base = CONFIG_UART_PSOC6_UART_6_BASE_ADDRESS, - .port = CONFIG_UART_PSOC6_UART_6_PORT, - .rx_num = CONFIG_UART_PSOC6_UART_6_RX_NUM, - .tx_num = CONFIG_UART_PSOC6_UART_6_TX_NUM, - .rx_val = CONFIG_UART_PSOC6_UART_6_RX_VAL, - .tx_val = CONFIG_UART_PSOC6_UART_6_TX_VAL, - .scb_clock = CONFIG_UART_PSOC6_UART_6_CLOCK, + .base = DT_UART_PSOC6_UART_6_BASE_ADDRESS, + .port = DT_UART_PSOC6_UART_6_PORT, + .rx_num = DT_UART_PSOC6_UART_6_RX_NUM, + .tx_num = DT_UART_PSOC6_UART_6_TX_NUM, + .rx_val = DT_UART_PSOC6_UART_6_RX_VAL, + .tx_val = DT_UART_PSOC6_UART_6_TX_VAL, + .scb_clock = DT_UART_PSOC6_UART_6_CLOCK, }; -DEVICE_AND_API_INIT(uart_6, CONFIG_UART_PSOC6_UART_6_NAME, +DEVICE_AND_API_INIT(uart_6, DT_UART_PSOC6_UART_6_NAME, uart_psoc6_init, NULL, &cypress_psoc6_uart6_config, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, diff --git a/drivers/serial/uart_qmsi.c b/drivers/serial/uart_qmsi.c index 9d75a9b8b34..49ff37d0148 100644 --- a/drivers/serial/uart_qmsi.c +++ b/drivers/serial/uart_qmsi.c @@ -136,8 +136,8 @@ static const struct uart_qmsi_config_info config_info_0 = { .instance = QM_UART_0, .clock_gate = CLK_PERIPH_UARTA_REGISTER | CLK_PERIPH_CLK, .baud_divisor = QM_UART_CFG_BAUD_DL_PACK( - DIVISOR_HIGH(CONFIG_UART_QMSI_0_BAUDRATE), - DIVISOR_LOW(CONFIG_UART_QMSI_0_BAUDRATE), + DIVISOR_HIGH(DT_UART_QMSI_0_BAUDRATE), + DIVISOR_LOW(DT_UART_QMSI_0_BAUDRATE), 0), #ifdef CONFIG_UART_QMSI_0_HW_FC .hw_fc = true, @@ -150,7 +150,7 @@ static const struct uart_qmsi_config_info config_info_0 = { static struct uart_qmsi_drv_data drv_data_0; -DEVICE_DEFINE(uart_0, CONFIG_UART_QMSI_0_NAME, &uart_qmsi_init, +DEVICE_DEFINE(uart_0, DT_UART_QMSI_0_NAME, &uart_qmsi_init, uart_qmsi_device_ctrl, &drv_data_0, &config_info_0, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, NULL); #endif /* CONFIG_UART_QMSI_0 */ @@ -164,8 +164,8 @@ static const struct uart_qmsi_config_info config_info_1 = { .instance = QM_UART_1, .clock_gate = CLK_PERIPH_UARTB_REGISTER | CLK_PERIPH_CLK, .baud_divisor = QM_UART_CFG_BAUD_DL_PACK( - DIVISOR_HIGH(CONFIG_UART_QMSI_1_BAUDRATE), - DIVISOR_LOW(CONFIG_UART_QMSI_1_BAUDRATE), + DIVISOR_HIGH(DT_UART_QMSI_1_BAUDRATE), + DIVISOR_LOW(DT_UART_QMSI_1_BAUDRATE), 0), #ifdef CONFIG_UART_QMSI_1_HW_FC .hw_fc = true, @@ -178,7 +178,7 @@ static const struct uart_qmsi_config_info config_info_1 = { static struct uart_qmsi_drv_data drv_data_1; -DEVICE_DEFINE(uart_1, CONFIG_UART_QMSI_1_NAME, &uart_qmsi_init, +DEVICE_DEFINE(uart_1, DT_UART_QMSI_1_NAME, &uart_qmsi_init, uart_qmsi_device_ctrl, &drv_data_1, &config_info_1, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, NULL); #endif /* CONFIG_UART_QMSI_1 */ @@ -375,10 +375,10 @@ static void irq_config_func_0(struct device *dev) { ARG_UNUSED(dev); - IRQ_CONNECT(CONFIG_UART_QMSI_0_IRQ, + IRQ_CONNECT(DT_UART_QMSI_0_IRQ, CONFIG_UART_QMSI_0_IRQ_PRI, uart_qmsi_isr, - DEVICE_GET(uart_0), CONFIG_UART_QMSI_0_IRQ_FLAGS); - irq_enable(CONFIG_UART_QMSI_0_IRQ); + DEVICE_GET(uart_0), DT_UART_QMSI_0_IRQ_FLAGS); + irq_enable(DT_UART_QMSI_0_IRQ); QM_IR_UNMASK_INTERRUPTS(QM_INTERRUPT_ROUTER->uart_0_int_mask); } #endif /* CONFIG_UART_QMSI_0 */ @@ -388,10 +388,10 @@ static void irq_config_func_1(struct device *dev) { ARG_UNUSED(dev); - IRQ_CONNECT(CONFIG_UART_QMSI_1_IRQ, + IRQ_CONNECT(DT_UART_QMSI_1_IRQ, CONFIG_UART_QMSI_1_IRQ_PRI, uart_qmsi_isr, - DEVICE_GET(uart_1), CONFIG_UART_QMSI_1_IRQ_FLAGS); - irq_enable(CONFIG_UART_QMSI_1_IRQ); + DEVICE_GET(uart_1), DT_UART_QMSI_1_IRQ_FLAGS); + irq_enable(DT_UART_QMSI_1_IRQ); QM_IR_UNMASK_INTERRUPTS(QM_INTERRUPT_ROUTER->uart_1_int_mask); } #endif /* CONFIG_UART_QMSI_1 */ diff --git a/drivers/serial/uart_sam.c b/drivers/serial/uart_sam.c index 36ddc286eea..03dc2eb0725 100644 --- a/drivers/serial/uart_sam.c +++ b/drivers/serial/uart_sam.c @@ -25,40 +25,40 @@ #if CONFIG_UART_SAM_PORT_0 == 1 -#if CONFIG_UART_SAM_PORT_0_BAUD_RATE == 0 -#error "CONFIG_UART_SAM_PORT_0_BAUD_RATE has to be bigger than 0" +#if DT_UART_SAM_PORT_0_BAUD_RATE == 0 +#error "DT_UART_SAM_PORT_0_BAUD_RATE has to be bigger than 0" #endif #endif #if CONFIG_UART_SAM_PORT_1 == 1 -#if CONFIG_UART_SAM_PORT_1_BAUD_RATE == 0 -#error "CONFIG_UART_SAM_PORT_1_BAUD_RATE has to be bigger than 0" +#if DT_UART_SAM_PORT_1_BAUD_RATE == 0 +#error "DT_UART_SAM_PORT_1_BAUD_RATE has to be bigger than 0" #endif #endif #if CONFIG_UART_SAM_PORT_2 == 1 -#if CONFIG_UART_SAM_PORT_2_BAUD_RATE == 0 -#error "CONFIG_UART_SAM_PORT_2_BAUD_RATE has to be bigger than 0" +#if DT_UART_SAM_PORT_2_BAUD_RATE == 0 +#error "DT_UART_SAM_PORT_2_BAUD_RATE has to be bigger than 0" #endif #endif #if CONFIG_UART_SAM_PORT_3 == 1 -#if CONFIG_UART_SAM_PORT_3_BAUD_RATE == 0 -#error "CONFIG_UART_SAM_PORT_3_BAUD_RATE has to be bigger than 0" +#if DT_UART_SAM_PORT_3_BAUD_RATE == 0 +#error "DT_UART_SAM_PORT_3_BAUD_RATE has to be bigger than 0" #endif #endif #if CONFIG_UART_SAM_PORT_4 == 1 -#if CONFIG_UART_SAM_PORT_4_BAUD_RATE == 0 -#error "CONFIG_UART_SAM_PORT_4_BAUD_RATE has to be bigger than 0" +#if DT_UART_SAM_PORT_4_BAUD_RATE == 0 +#error "DT_UART_SAM_PORT_4_BAUD_RATE has to be bigger than 0" #endif #endif @@ -386,21 +386,21 @@ static const struct uart_sam_dev_cfg uart0_sam_config = { }; static struct uart_sam_dev_data uart0_sam_data = { - .baud_rate = CONFIG_UART_SAM_PORT_0_BAUD_RATE, + .baud_rate = DT_UART_SAM_PORT_0_BAUD_RATE, }; -DEVICE_AND_API_INIT(uart0_sam, CONFIG_UART_SAM_PORT_0_NAME, &uart_sam_init, +DEVICE_AND_API_INIT(uart0_sam, DT_UART_SAM_PORT_0_NAME, &uart_sam_init, &uart0_sam_data, &uart0_sam_config, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &uart_sam_driver_api); #ifdef CONFIG_UART_INTERRUPT_DRIVEN static void uart0_sam_irq_config_func(struct device *port) { - IRQ_CONNECT(CONFIG_UART_SAM_PORT_0_IRQ, - CONFIG_UART_SAM_PORT_0_IRQ_PRIO, + IRQ_CONNECT(DT_UART_SAM_PORT_0_IRQ, + DT_UART_SAM_PORT_0_IRQ_PRIO, uart_sam_isr, DEVICE_GET(uart0_sam), 0); - irq_enable(CONFIG_UART_SAM_PORT_0_IRQ); + irq_enable(DT_UART_SAM_PORT_0_IRQ); } #endif /* CONFIG_UART_INTERRUPT_DRIVEN */ #endif /* CONFIG_UART_SAM_PORT_0 */ @@ -426,21 +426,21 @@ static const struct uart_sam_dev_cfg uart1_sam_config = { }; static struct uart_sam_dev_data uart1_sam_data = { - .baud_rate = CONFIG_UART_SAM_PORT_1_BAUD_RATE, + .baud_rate = DT_UART_SAM_PORT_1_BAUD_RATE, }; -DEVICE_AND_API_INIT(uart1_sam, CONFIG_UART_SAM_PORT_1_NAME, &uart_sam_init, +DEVICE_AND_API_INIT(uart1_sam, DT_UART_SAM_PORT_1_NAME, &uart_sam_init, &uart1_sam_data, &uart1_sam_config, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &uart_sam_driver_api); #ifdef CONFIG_UART_INTERRUPT_DRIVEN static void uart1_sam_irq_config_func(struct device *port) { - IRQ_CONNECT(CONFIG_UART_SAM_PORT_1_IRQ, - CONFIG_UART_SAM_PORT_1_IRQ_PRIO, + IRQ_CONNECT(DT_UART_SAM_PORT_1_IRQ, + DT_UART_SAM_PORT_1_IRQ_PRIO, uart_sam_isr, DEVICE_GET(uart1_sam), 0); - irq_enable(CONFIG_UART_SAM_PORT_1_IRQ); + irq_enable(DT_UART_SAM_PORT_1_IRQ); } #endif /* CONFIG_UART_INTERRUPT_DRIVEN */ @@ -467,21 +467,21 @@ static const struct uart_sam_dev_cfg uart2_sam_config = { }; static struct uart_sam_dev_data uart2_sam_data = { - .baud_rate = CONFIG_UART_SAM_PORT_2_BAUD_RATE, + .baud_rate = DT_UART_SAM_PORT_2_BAUD_RATE, }; -DEVICE_AND_API_INIT(uart2_sam, CONFIG_UART_SAM_PORT_2_NAME, &uart_sam_init, +DEVICE_AND_API_INIT(uart2_sam, DT_UART_SAM_PORT_2_NAME, &uart_sam_init, &uart2_sam_data, &uart2_sam_config, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &uart_sam_driver_api); #ifdef CONFIG_UART_INTERRUPT_DRIVEN static void uart2_sam_irq_config_func(struct device *port) { - IRQ_CONNECT(CONFIG_UART_SAM_PORT_2_IRQ, - CONFIG_UART_SAM_PORT_2_IRQ_PRIO, + IRQ_CONNECT(DT_UART_SAM_PORT_2_IRQ, + DT_UART_SAM_PORT_2_IRQ_PRIO, uart_sam_isr, DEVICE_GET(uart2_sam), 0); - irq_enable(CONFIG_UART_SAM_PORT_2_IRQ); + irq_enable(DT_UART_SAM_PORT_2_IRQ); } #endif /* CONFIG_UART_INTERRUPT_DRIVEN */ @@ -508,21 +508,21 @@ static const struct uart_sam_dev_cfg uart3_sam_config = { }; static struct uart_sam_dev_data uart3_sam_data = { - .baud_rate = CONFIG_UART_SAM_PORT_3_BAUD_RATE, + .baud_rate = DT_UART_SAM_PORT_3_BAUD_RATE, }; -DEVICE_AND_API_INIT(uart3_sam, CONFIG_UART_SAM_PORT_3_NAME, &uart_sam_init, +DEVICE_AND_API_INIT(uart3_sam, DT_UART_SAM_PORT_3_NAME, &uart_sam_init, &uart3_sam_data, &uart3_sam_config, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &uart_sam_driver_api); #ifdef CONFIG_UART_INTERRUPT_DRIVEN static void uart3_sam_irq_config_func(struct device *port) { - IRQ_CONNECT(CONFIG_UART_SAM_PORT_3_IRQ, - CONFIG_UART_SAM_PORT_3_IRQ_PRIO, + IRQ_CONNECT(DT_UART_SAM_PORT_3_IRQ, + DT_UART_SAM_PORT_3_IRQ_PRIO, uart_sam_isr, DEVICE_GET(uart3_sam), 0); - irq_enable(CONFIG_UART_SAM_PORT_3_IRQ); + irq_enable(DT_UART_SAM_PORT_3_IRQ); } #endif /* CONFIG_UART_INTERRUPT_DRIVEN */ @@ -549,21 +549,21 @@ static const struct uart_sam_dev_cfg uart4_sam_config = { }; static struct uart_sam_dev_data uart4_sam_data = { - .baud_rate = CONFIG_UART_SAM_PORT_4_BAUD_RATE, + .baud_rate = DT_UART_SAM_PORT_4_BAUD_RATE, }; -DEVICE_AND_API_INIT(uart4_sam, CONFIG_UART_SAM_PORT_4_NAME, &uart_sam_init, +DEVICE_AND_API_INIT(uart4_sam, DT_UART_SAM_PORT_4_NAME, &uart_sam_init, &uart4_sam_data, &uart4_sam_config, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &uart_sam_driver_api); #ifdef CONFIG_UART_INTERRUPT_DRIVEN static void uart4_sam_irq_config_func(struct device *port) { - IRQ_CONNECT(CONFIG_UART_SAM_PORT_4_IRQ, - CONFIG_UART_SAM_PORT_4_IRQ_PRIO, + IRQ_CONNECT(DT_UART_SAM_PORT_4_IRQ, + DT_UART_SAM_PORT_4_IRQ_PRIO, uart_sam_isr, DEVICE_GET(uart4_sam), 0); - irq_enable(CONFIG_UART_SAM_PORT_4_IRQ); + irq_enable(DT_UART_SAM_PORT_4_IRQ); } #endif /* CONFIG_UART_INTERRUPT_DRIVEN */ diff --git a/drivers/serial/uart_sam0.c b/drivers/serial/uart_sam0.c index 8e78c5d81cc..9695a6a4e21 100644 --- a/drivers/serial/uart_sam0.c +++ b/drivers/serial/uart_sam0.c @@ -276,11 +276,11 @@ static void uart_sam0_irq_config_##n(struct device *dev) #define UART_SAM0_IRQ_HANDLER(n) \ static void uart_sam0_irq_config_##n(struct device *dev) \ { \ - IRQ_CONNECT(CONFIG_UART_SAM0_SERCOM##n##_IRQ, \ - CONFIG_UART_SAM0_SERCOM##n##_IRQ_PRIORITY, \ + IRQ_CONNECT(DT_UART_SAM0_SERCOM##n##_IRQ, \ + DT_UART_SAM0_SERCOM##n##_IRQ_PRIORITY, \ uart_sam0_isr, DEVICE_GET(uart_sam0_##n), \ 0); \ - irq_enable(CONFIG_UART_SAM0_SERCOM##n##_IRQ); \ + irq_enable(DT_UART_SAM0_SERCOM##n##_IRQ); \ } #else #define UART_SAM0_IRQ_HANDLER_DECL(n) @@ -289,13 +289,13 @@ static void uart_sam0_irq_config_##n(struct device *dev) \ #endif #define CONFIG_UART_SAM0_SERCOM_PADS(n) \ - (CONFIG_UART_SAM0_SERCOM##n##_RXPO << SERCOM_USART_CTRLA_RXPO_Pos) | \ - (CONFIG_UART_SAM0_SERCOM##n##_TXPO << SERCOM_USART_CTRLA_TXPO_Pos) + (DT_UART_SAM0_SERCOM##n##_RXPO << SERCOM_USART_CTRLA_RXPO_Pos) | \ + (DT_UART_SAM0_SERCOM##n##_TXPO << SERCOM_USART_CTRLA_TXPO_Pos) #define UART_SAM0_CONFIG_DEFN(n) \ static const struct uart_sam0_dev_cfg uart_sam0_config_##n = { \ - .regs = (SercomUsart *)CONFIG_UART_SAM0_SERCOM##n##_BASE_ADDRESS, \ - .baudrate = CONFIG_UART_SAM0_SERCOM##n##_CURRENT_SPEED, \ + .regs = (SercomUsart *)DT_UART_SAM0_SERCOM##n##_BASE_ADDRESS, \ + .baudrate = DT_UART_SAM0_SERCOM##n##_CURRENT_SPEED, \ .pm_apbcmask = PM_APBCMASK_SERCOM##n, \ .gclk_clkctrl_id = GCLK_CLKCTRL_ID_SERCOM##n##_CORE, \ .pads = CONFIG_UART_SAM0_SERCOM_PADS(n), \ @@ -306,33 +306,33 @@ static const struct uart_sam0_dev_cfg uart_sam0_config_##n = { \ static struct uart_sam0_dev_data uart_sam0_data_##n; \ UART_SAM0_IRQ_HANDLER_DECL(n); \ UART_SAM0_CONFIG_DEFN(n); \ -DEVICE_AND_API_INIT(uart_sam0_##n, CONFIG_UART_SAM0_SERCOM##n##_LABEL, \ +DEVICE_AND_API_INIT(uart_sam0_##n, DT_UART_SAM0_SERCOM##n##_LABEL, \ uart_sam0_init, &uart_sam0_data_##n, \ &uart_sam0_config_##n, PRE_KERNEL_1, \ CONFIG_KERNEL_INIT_PRIORITY_DEVICE, \ &uart_sam0_driver_api); \ UART_SAM0_IRQ_HANDLER(n) -#if CONFIG_UART_SAM0_SERCOM0_BASE_ADDRESS +#if DT_UART_SAM0_SERCOM0_BASE_ADDRESS UART_SAM0_DEVICE_INIT(0) #endif -#if CONFIG_UART_SAM0_SERCOM1_BASE_ADDRESS +#if DT_UART_SAM0_SERCOM1_BASE_ADDRESS UART_SAM0_DEVICE_INIT(1) #endif -#if CONFIG_UART_SAM0_SERCOM2_BASE_ADDRESS +#if DT_UART_SAM0_SERCOM2_BASE_ADDRESS UART_SAM0_DEVICE_INIT(2) #endif -#if CONFIG_UART_SAM0_SERCOM3_BASE_ADDRESS +#if DT_UART_SAM0_SERCOM3_BASE_ADDRESS UART_SAM0_DEVICE_INIT(3) #endif -#if CONFIG_UART_SAM0_SERCOM4_BASE_ADDRESS +#if DT_UART_SAM0_SERCOM4_BASE_ADDRESS UART_SAM0_DEVICE_INIT(4) #endif -#if CONFIG_UART_SAM0_SERCOM5_BASE_ADDRESS +#if DT_UART_SAM0_SERCOM5_BASE_ADDRESS UART_SAM0_DEVICE_INIT(5) #endif diff --git a/drivers/serial/uart_sifive.c b/drivers/serial/uart_sifive.c index 4988c996830..01f21a855df 100644 --- a/drivers/serial/uart_sifive.c +++ b/drivers/serial/uart_sifive.c @@ -384,9 +384,9 @@ static void uart_sifive_irq_cfg_func_0(void); #endif static const struct uart_sifive_device_config uart_sifive_dev_cfg_0 = { - .port = CONFIG_SIFIVE_UART_0_BASE_ADDR, - .sys_clk_freq = CONFIG_SIFIVE_UART_0_CLK_FREQ, - .baud_rate = CONFIG_SIFIVE_UART_0_CURRENT_SPEED, + .port = DT_SIFIVE_UART_0_BASE_ADDR, + .sys_clk_freq = DT_SIFIVE_UART_0_CLK_FREQ, + .baud_rate = DT_SIFIVE_UART_0_CURRENT_SPEED, .rxcnt_irq = CONFIG_UART_SIFIVE_PORT_0_RXCNT_IRQ, .txcnt_irq = CONFIG_UART_SIFIVE_PORT_0_TXCNT_IRQ, #ifdef CONFIG_UART_INTERRUPT_DRIVEN @@ -394,7 +394,7 @@ static const struct uart_sifive_device_config uart_sifive_dev_cfg_0 = { #endif }; -DEVICE_AND_API_INIT(uart_sifive_0, CONFIG_SIFIVE_UART_0_LABEL, +DEVICE_AND_API_INIT(uart_sifive_0, DT_SIFIVE_UART_0_LABEL, uart_sifive_init, &uart_sifive_data_0, &uart_sifive_dev_cfg_0, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, @@ -403,12 +403,12 @@ DEVICE_AND_API_INIT(uart_sifive_0, CONFIG_SIFIVE_UART_0_LABEL, #ifdef CONFIG_UART_INTERRUPT_DRIVEN static void uart_sifive_irq_cfg_func_0(void) { - IRQ_CONNECT(CONFIG_SIFIVE_UART_0_IRQ_0, + IRQ_CONNECT(DT_SIFIVE_UART_0_IRQ_0, CONFIG_UART_SIFIVE_PORT_0_IRQ_PRIORITY, uart_sifive_irq_handler, DEVICE_GET(uart_sifive_0), 0); - irq_enable(CONFIG_SIFIVE_UART_0_IRQ_0); + irq_enable(DT_SIFIVE_UART_0_IRQ_0); } #endif @@ -423,9 +423,9 @@ static void uart_sifive_irq_cfg_func_1(void); #endif static const struct uart_sifive_device_config uart_sifive_dev_cfg_1 = { - .port = CONFIG_SIFIVE_UART_1_BASE_ADDR, - .sys_clk_freq = CONFIG_SIFIVE_UART_1_CLK_FREQ, - .baud_rate = CONFIG_SIFIVE_UART_1_CURRENT_SPEED, + .port = DT_SIFIVE_UART_1_BASE_ADDR, + .sys_clk_freq = DT_SIFIVE_UART_1_CLK_FREQ, + .baud_rate = DT_SIFIVE_UART_1_CURRENT_SPEED, .rxcnt_irq = CONFIG_UART_SIFIVE_PORT_1_RXCNT_IRQ, .txcnt_irq = CONFIG_UART_SIFIVE_PORT_1_TXCNT_IRQ, #ifdef CONFIG_UART_INTERRUPT_DRIVEN @@ -442,12 +442,12 @@ DEVICE_AND_API_INIT(uart_sifive_1, CONFIG_SIFIVE_UART_1_LABEL, #ifdef CONFIG_UART_INTERRUPT_DRIVEN static void uart_sifive_irq_cfg_func_1(void) { - IRQ_CONNECT(CONFIG_SIFIVE_UART_1_IRQ_0, + IRQ_CONNECT(DT_SIFIVE_UART_1_IRQ_0, CONFIG_UART_SIFIVE_PORT_1_IRQ_PRIORITY, uart_sifive_irq_handler, DEVICE_GET(uart_sifive_1), 0); - irq_enable(CONFIG_SIFIVE_UART_1_IRQ_0); + irq_enable(DT_SIFIVE_UART_1_IRQ_0); } #endif diff --git a/drivers/serial/uart_stellaris.c b/drivers/serial/uart_stellaris.c index 5a64201ee34..c545de6a122 100644 --- a/drivers/serial/uart_stellaris.c +++ b/drivers/serial/uart_stellaris.c @@ -636,7 +636,7 @@ static void irq_config_func_0(struct device *port); static const struct uart_device_config uart_stellaris_dev_cfg_0 = { .base = (u8_t *)DT_TI_STELLARIS_UART_4000C000_BASE_ADDRESS, - .sys_clk_freq = UART_STELLARIS_CLK_FREQ, + .sys_clk_freq = DT_UART_STELLARIS_CLK_FREQ, #ifdef CONFIG_UART_INTERRUPT_DRIVEN .irq_config_func = irq_config_func_0, @@ -674,7 +674,7 @@ static void irq_config_func_1(struct device *port); static struct uart_device_config uart_stellaris_dev_cfg_1 = { .base = (u8_t *)DT_TI_STELLARIS_UART_4000D000_BASE_ADDRESS, - .sys_clk_freq = UART_STELLARIS_CLK_FREQ, + .sys_clk_freq = DT_UART_STELLARIS_CLK_FREQ, #ifdef CONFIG_UART_INTERRUPT_DRIVEN .irq_config_func = irq_config_func_1, @@ -712,7 +712,7 @@ static void irq_config_func_2(struct device *port); static const struct uart_device_config uart_stellaris_dev_cfg_2 = { .base = (u8_t *)DT_TI_STELLARIS_UART_4000E000_BASE_ADDRESS, - .sys_clk_freq = UART_STELLARIS_CLK_FREQ, + .sys_clk_freq = DT_UART_STELLARIS_CLK_FREQ, #ifdef CONFIG_UART_INTERRUPT_DRIVEN .irq_config_func = irq_config_func_2, diff --git a/drivers/serial/uart_stm32.c b/drivers/serial/uart_stm32.c index e60cff79ab1..a274e8cfec8 100644 --- a/drivers/serial/uart_stm32.c +++ b/drivers/serial/uart_stm32.c @@ -372,11 +372,11 @@ static int uart_stm32_init(struct device *dev) #define STM32_UART_IRQ_HANDLER(name) \ static void uart_stm32_irq_config_func_##name(struct device *dev) \ { \ - IRQ_CONNECT(name##_IRQ, \ - CONFIG_UART_STM32_##name##_IRQ_PRI, \ + IRQ_CONNECT(DT_##name##_IRQ, \ + DT_UART_STM32_##name##_IRQ_PRI, \ uart_stm32_isr, DEVICE_GET(uart_stm32_##name), \ 0); \ - irq_enable(name##_IRQ); \ + irq_enable(DT_##name##_IRQ); \ } #else #define STM32_UART_IRQ_HANDLER_DECL(name) @@ -389,19 +389,19 @@ STM32_UART_IRQ_HANDLER_DECL(name); \ \ static const struct uart_stm32_config uart_stm32_cfg_##name = { \ .uconf = { \ - .base = (u8_t *)CONFIG_UART_STM32_##name##_BASE_ADDRESS,\ + .base = (u8_t *)DT_UART_STM32_##name##_BASE_ADDRESS,\ STM32_UART_IRQ_HANDLER_FUNC(name) \ }, \ - .pclken = { .bus = CONFIG_UART_STM32_##name##_CLOCK_BUS, \ - .enr = CONFIG_UART_STM32_##name##_CLOCK_BITS \ + .pclken = { .bus = DT_UART_STM32_##name##_CLOCK_BUS, \ + .enr = DT_UART_STM32_##name##_CLOCK_BITS \ }, \ - .baud_rate = CONFIG_UART_STM32_##name##_BAUD_RATE \ + .baud_rate = DT_UART_STM32_##name##_BAUD_RATE \ }; \ \ static struct uart_stm32_data uart_stm32_data_##name = { \ }; \ \ -DEVICE_AND_API_INIT(uart_stm32_##name, CONFIG_UART_STM32_##name##_NAME, \ +DEVICE_AND_API_INIT(uart_stm32_##name, DT_UART_STM32_##name##_NAME, \ &uart_stm32_init, \ &uart_stm32_data_##name, &uart_stm32_cfg_##name, \ PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, \ diff --git a/drivers/serial/usart_mcux_lpc.c b/drivers/serial/usart_mcux_lpc.c index 2c9a70da4bf..eb8e69a7535 100644 --- a/drivers/serial/usart_mcux_lpc.c +++ b/drivers/serial/usart_mcux_lpc.c @@ -111,14 +111,14 @@ static const struct uart_driver_api usart_mcux_lpc_driver_api = { #ifdef CONFIG_USART_MCUX_LPC_0 static const struct usart_mcux_lpc_config usart_mcux_lpc_0_config = { - .base = (USART_Type *)CONFIG_USART_MCUX_LPC_0_BASE_ADDRESS, + .base = (USART_Type *)DT_USART_MCUX_LPC_0_BASE_ADDRESS, .clock_source = kCLOCK_Flexcomm0, - .baud_rate = CONFIG_USART_MCUX_LPC_0_BAUD_RATE, + .baud_rate = DT_USART_MCUX_LPC_0_BAUD_RATE, }; static struct usart_mcux_lpc_data usart_mcux_lpc_0_data; -DEVICE_AND_API_INIT(usart_0, CONFIG_USART_MCUX_LPC_0_NAME, +DEVICE_AND_API_INIT(usart_0, DT_USART_MCUX_LPC_0_NAME, &usart_mcux_lpc_init, &usart_mcux_lpc_0_data, &usart_mcux_lpc_0_config, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, diff --git a/drivers/serial/usart_sam.c b/drivers/serial/usart_sam.c index 56601e2323d..3e056a6e036 100644 --- a/drivers/serial/usart_sam.c +++ b/drivers/serial/usart_sam.c @@ -25,24 +25,24 @@ #if CONFIG_USART_SAM_PORT_0 == 1 -#if CONFIG_USART_SAM_PORT_0_BAUD_RATE == 0 -#error "CONFIG_USART_SAM_PORT_0_BAUD_RATE has to be bigger than 0" +#if DT_USART_SAM_PORT_0_BAUD_RATE == 0 +#error "DT_USART_SAM_PORT_0_BAUD_RATE has to be bigger than 0" #endif #endif #if CONFIG_USART_SAM_PORT_1 == 1 -#if CONFIG_USART_SAM_PORT_1_BAUD_RATE == 0 -#error "CONFIG_USART_SAM_PORT_1_BAUD_RATE has to be bigger than 0" +#if DT_USART_SAM_PORT_1_BAUD_RATE == 0 +#error "DT_USART_SAM_PORT_1_BAUD_RATE has to be bigger than 0" #endif #endif #if CONFIG_USART_SAM_PORT_2 == 1 -#if CONFIG_USART_SAM_PORT_2_BAUD_RATE == 0 -#error "CONFIG_USART_SAM_PORT_2_BAUD_RATE has to be bigger than 0" +#if DT_USART_SAM_PORT_2_BAUD_RATE == 0 +#error "DT_USART_SAM_PORT_2_BAUD_RATE has to be bigger than 0" #endif #endif @@ -363,7 +363,7 @@ static void usart0_sam_irq_config_func(struct device *port); static const struct usart_sam_dev_cfg usart0_sam_config = { .regs = USART0, - .periph_id = CONFIG_USART_SAM_PORT_0_PERIPHERAL_ID, + .periph_id = DT_USART_SAM_PORT_0_PERIPHERAL_ID, .pin_rx = PIN_USART0_RXD, .pin_tx = PIN_USART0_TXD, @@ -373,21 +373,21 @@ static const struct usart_sam_dev_cfg usart0_sam_config = { }; static struct usart_sam_dev_data usart0_sam_data = { - .baud_rate = CONFIG_USART_SAM_PORT_0_BAUD_RATE, + .baud_rate = DT_USART_SAM_PORT_0_BAUD_RATE, }; -DEVICE_AND_API_INIT(usart0_sam, CONFIG_USART_SAM_PORT_0_NAME, &usart_sam_init, +DEVICE_AND_API_INIT(usart0_sam, DT_USART_SAM_PORT_0_NAME, &usart_sam_init, &usart0_sam_data, &usart0_sam_config, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &usart_sam_driver_api); #ifdef CONFIG_UART_INTERRUPT_DRIVEN static void usart0_sam_irq_config_func(struct device *port) { - IRQ_CONNECT(CONFIG_USART_SAM_PORT_0_IRQ, - CONFIG_USART_SAM_PORT_0_IRQ_PRIO, + IRQ_CONNECT(DT_USART_SAM_PORT_0_IRQ, + DT_USART_SAM_PORT_0_IRQ_PRIO, usart_sam_isr, DEVICE_GET(usart0_sam), 0); - irq_enable(CONFIG_USART_SAM_PORT_0_IRQ); + irq_enable(DT_USART_SAM_PORT_0_IRQ); } #endif /* CONFIG_UART_INTERRUPT_DRIVEN */ @@ -404,7 +404,7 @@ static void usart1_sam_irq_config_func(struct device *port); static const struct usart_sam_dev_cfg usart1_sam_config = { .regs = USART1, - .periph_id = CONFIG_USART_SAM_PORT_1_PERIPHERAL_ID, + .periph_id = DT_USART_SAM_PORT_1_PERIPHERAL_ID, .pin_rx = PIN_USART1_RXD, .pin_tx = PIN_USART1_TXD, @@ -414,21 +414,21 @@ static const struct usart_sam_dev_cfg usart1_sam_config = { }; static struct usart_sam_dev_data usart1_sam_data = { - .baud_rate = CONFIG_USART_SAM_PORT_1_BAUD_RATE, + .baud_rate = DT_USART_SAM_PORT_1_BAUD_RATE, }; -DEVICE_AND_API_INIT(usart1_sam, CONFIG_USART_SAM_PORT_1_NAME, &usart_sam_init, +DEVICE_AND_API_INIT(usart1_sam, DT_USART_SAM_PORT_1_NAME, &usart_sam_init, &usart1_sam_data, &usart1_sam_config, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &usart_sam_driver_api); #ifdef CONFIG_UART_INTERRUPT_DRIVEN static void usart1_sam_irq_config_func(struct device *port) { - IRQ_CONNECT(CONFIG_USART_SAM_PORT_1_IRQ, - CONFIG_USART_SAM_PORT_1_IRQ_PRIO, + IRQ_CONNECT(DT_USART_SAM_PORT_1_IRQ, + DT_USART_SAM_PORT_1_IRQ_PRIO, usart_sam_isr, DEVICE_GET(usart1_sam), 0); - irq_enable(CONFIG_USART_SAM_PORT_1_IRQ); + irq_enable(DT_USART_SAM_PORT_1_IRQ); } #endif /* CONFIG_UART_INTERRUPT_DRIVEN */ @@ -445,7 +445,7 @@ static void usart2_sam_irq_config_func(struct device *port); static const struct usart_sam_dev_cfg usart2_sam_config = { .regs = USART2, - .periph_id = CONFIG_USART_SAM_PORT_2_PERIPHERAL_ID, + .periph_id = DT_USART_SAM_PORT_2_PERIPHERAL_ID, .pin_rx = PIN_USART2_RXD, .pin_tx = PIN_USART2_TXD, @@ -455,21 +455,21 @@ static const struct usart_sam_dev_cfg usart2_sam_config = { }; static struct usart_sam_dev_data usart2_sam_data = { - .baud_rate = CONFIG_USART_SAM_PORT_2_BAUD_RATE, + .baud_rate = DT_USART_SAM_PORT_2_BAUD_RATE, }; -DEVICE_AND_API_INIT(usart2_sam, CONFIG_USART_SAM_PORT_2_NAME, &usart_sam_init, +DEVICE_AND_API_INIT(usart2_sam, DT_USART_SAM_PORT_2_NAME, &usart_sam_init, &usart2_sam_data, &usart2_sam_config, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &usart_sam_driver_api); #ifdef CONFIG_UART_INTERRUPT_DRIVEN static void usart2_sam_irq_config_func(struct device *port) { - IRQ_CONNECT(CONFIG_USART_SAM_PORT_2_IRQ, - CONFIG_USART_SAM_PORT_2_IRQ_PRIO, + IRQ_CONNECT(DT_USART_SAM_PORT_2_IRQ, + DT_USART_SAM_PORT_2_IRQ_PRIO, usart_sam_isr, DEVICE_GET(usart2_sam), 0); - irq_enable(CONFIG_USART_SAM_PORT_2_IRQ); + irq_enable(DT_USART_SAM_PORT_2_IRQ); } #endif /* CONFIG_UART_INTERRUPT_DRIVEN */ diff --git a/drivers/spi/spi_dw.c b/drivers/spi/spi_dw.c index a359c47fdf2..ed36ee34eaf 100644 --- a/drivers/spi/spi_dw.c +++ b/drivers/spi/spi_dw.c @@ -534,7 +534,7 @@ struct spi_dw_data spi_dw_data_port_0 = { }; const struct spi_dw_config spi_dw_config_0 = { - .regs = CONFIG_SPI_0_BASE_ADDRESS, + .regs = DT_SPI_0_BASE_ADDRESS, #ifdef CONFIG_SPI_DW_PORT_0_CLOCK_GATE .clock_name = CONFIG_SPI_DW_PORT_1_CLOCK_GATE_DRV_NAME, .clock_data = UINT_TO_POINTER(CONFIG_SPI_DW_PORT_0_CLOCK_GATE_SUBSYS), @@ -551,21 +551,21 @@ DEVICE_AND_API_INIT(spi_dw_port_0, CONFIG_SPI_0_NAME, spi_dw_init, void spi_config_0_irq(void) { #ifdef CONFIG_SPI_DW_PORT_0_INTERRUPT_SINGLE_LINE - IRQ_CONNECT(CONFIG_SPI_0_IRQ, CONFIG_SPI_0_IRQ_PRI, - spi_dw_isr, DEVICE_GET(spi_dw_port_0), SPI_DW_IRQ_FLAGS); - irq_enable(CONFIG_SPI_0_IRQ); + IRQ_CONNECT(DT_SPI_0_IRQ, CONFIG_SPI_0_IRQ_PRI, + spi_dw_isr, DEVICE_GET(spi_dw_port_0), DT_SPI_DW_IRQ_FLAGS); + irq_enable(DT_SPI_0_IRQ); _spi_int_unmask(SPI_DW_PORT_0_INT_MASK); #else - IRQ_CONNECT(CONFIG_SPI_0_IRQ_RX_AVAIL, CONFIG_SPI_0_IRQ_RX_AVAIL_PRI, - spi_dw_isr, DEVICE_GET(spi_dw_port_0), SPI_DW_IRQ_FLAGS); - IRQ_CONNECT(CONFIG_SPI_0_IRQ_TX_REQ, CONFIG_SPI_0_IRQ_TX_REQ_PRI, - spi_dw_isr, DEVICE_GET(spi_dw_port_0), SPI_DW_IRQ_FLAGS); - IRQ_CONNECT(CONFIG_SPI_0_IRQ_ERR_INT, CONFIG_SPI_0_IRQ_ERR_INT_PRI, - spi_dw_isr, DEVICE_GET(spi_dw_port_0), SPI_DW_IRQ_FLAGS); + IRQ_CONNECT(DT_SPI_0_IRQ_RX_AVAIL, DT_SPI_0_IRQ_RX_AVAIL_PRI, + spi_dw_isr, DEVICE_GET(spi_dw_port_0), DT_SPI_DW_IRQ_FLAGS); + IRQ_CONNECT(DT_SPI_0_IRQ_TX_REQ, DT_SPI_0_IRQ_TX_REQ_PRI, + spi_dw_isr, DEVICE_GET(spi_dw_port_0), DT_SPI_DW_IRQ_FLAGS); + IRQ_CONNECT(DT_SPI_0_IRQ_ERR_INT, DT_SPI_0_IRQ_ERR_INT_PRI, + spi_dw_isr, DEVICE_GET(spi_dw_port_0), DT_SPI_DW_IRQ_FLAGS); - irq_enable(CONFIG_SPI_0_IRQ_RX_AVAIL); - irq_enable(CONFIG_SPI_0_IRQ_TX_REQ); - irq_enable(CONFIG_SPI_0_IRQ_ERR_INT); + irq_enable(DT_SPI_0_IRQ_RX_AVAIL); + irq_enable(DT_SPI_0_IRQ_TX_REQ); + irq_enable(DT_SPI_0_IRQ_ERR_INT); _spi_int_unmask(SPI_DW_PORT_0_RX_INT_MASK); _spi_int_unmask(SPI_DW_PORT_0_TX_INT_MASK); @@ -582,7 +582,7 @@ struct spi_dw_data spi_dw_data_port_1 = { }; static const struct spi_dw_config spi_dw_config_1 = { - .regs = CONFIG_SPI_1_BASE_ADDRESS, + .regs = DT_SPI_1_BASE_ADDRESS, #ifdef CONFIG_SPI_DW_PORT_1_CLOCK_GATE .clock_name = CONFIG_SPI_DW_PORT_1_CLOCK_GATE_DRV_NAME, .clock_data = UINT_TO_POINTER(CONFIG_SPI_DW_PORT_1_CLOCK_GATE_SUBSYS), @@ -599,21 +599,21 @@ DEVICE_AND_API_INIT(spi_dw_port_1, CONFIG_SPI_1_NAME, spi_dw_init, void spi_config_1_irq(void) { #ifdef CONFIG_SPI_DW_PORT_1_INTERRUPT_SINGLE_LINE - IRQ_CONNECT(CONFIG_SPI_1_IRQ, CONFIG_SPI_1_IRQ_PRI, - spi_dw_isr, DEVICE_GET(spi_dw_port_1), SPI_DW_IRQ_FLAGS); - irq_enable(CONFIG_SPI_1_IRQ); + IRQ_CONNECT(DT_SPI_1_IRQ, CONFIG_SPI_1_IRQ_PRI, + spi_dw_isr, DEVICE_GET(spi_dw_port_1), DT_SPI_DW_IRQ_FLAGS); + irq_enable(DT_SPI_1_IRQ); _spi_int_unmask(SPI_DW_PORT_1_INT_MASK); #else - IRQ_CONNECT(CONFIG_SPI_1_IRQ_RX_AVAIL, CONFIG_SPI_1_IRQ_RX_AVAIL_PRI, - spi_dw_isr, DEVICE_GET(spi_dw_port_1), SPI_DW_IRQ_FLAGS); - IRQ_CONNECT(CONFIG_SPI_1_IRQ_TX_REQ, CONFIG_SPI_1_IRQ_TX_REQ_PRI, - spi_dw_isr, DEVICE_GET(spi_dw_port_1), SPI_DW_IRQ_FLAGS); - IRQ_CONNECT(CONFIG_SPI_1_IRQ_ERR_INT, CONFIG_SPI_1_IRQ_ERR_INT_PRI, - spi_dw_isr, DEVICE_GET(spi_dw_port_1), SPI_DW_IRQ_FLAGS); + IRQ_CONNECT(DT_SPI_1_IRQ_RX_AVAIL, DT_SPI_1_IRQ_RX_AVAIL_PRI, + spi_dw_isr, DEVICE_GET(spi_dw_port_1), DT_SPI_DW_IRQ_FLAGS); + IRQ_CONNECT(DT_SPI_1_IRQ_TX_REQ, DT_SPI_1_IRQ_TX_REQ_PRI, + spi_dw_isr, DEVICE_GET(spi_dw_port_1), DT_SPI_DW_IRQ_FLAGS); + IRQ_CONNECT(DT_SPI_1_IRQ_ERR_INT, DT_SPI_1_IRQ_ERR_INT_PRI, + spi_dw_isr, DEVICE_GET(spi_dw_port_1), DT_SPI_DW_IRQ_FLAGS); - irq_enable(CONFIG_SPI_1_IRQ_RX_AVAIL); - irq_enable(CONFIG_SPI_1_IRQ_TX_REQ); - irq_enable(CONFIG_SPI_1_IRQ_ERR_INT); + irq_enable(DT_SPI_1_IRQ_RX_AVAIL); + irq_enable(DT_SPI_1_IRQ_TX_REQ); + irq_enable(DT_SPI_1_IRQ_ERR_INT); _spi_int_unmask(SPI_DW_PORT_1_RX_INT_MASK); _spi_int_unmask(SPI_DW_PORT_1_TX_INT_MASK); @@ -630,7 +630,7 @@ struct spi_dw_data spi_dw_data_port_2 = { }; static const struct spi_dw_config spi_dw_config_2 = { - .regs = CONFIG_SPI_2_BASE_ADDRESS, + .regs = DT_SPI_2_BASE_ADDRESS, #ifdef CONFIG_SPI_DW_PORT_2_CLOCK_GATE .clock_name = CONFIG_SPI_DW_PORT_2_CLOCK_GATE_DRV_NAME, .clock_data = UINT_TO_POINTER(CONFIG_SPI_DW_PORT_2_CLOCK_GATE_SUBSYS), @@ -647,17 +647,17 @@ DEVICE_AND_API_INIT(spi_dw_port_2, CONFIG_SPI_2_NAME, spi_dw_init, void spi_config_2_irq(void) { #ifdef CONFIG_SPI_DW_PORT_2_INTERRUPT_SINGLE_LINE - IRQ_CONNECT(CONFIG_SPI_2_IRQ, CONFIG_SPI_2_IRQ_PRI, - spi_dw_isr, DEVICE_GET(spi_dw_port_2), SPI_DW_IRQ_FLAGS); - irq_enable(CONFIG_SPI_2_IRQ); + IRQ_CONNECT(DT_SPI_2_IRQ, CONFIG_SPI_2_IRQ_PRI, + spi_dw_isr, DEVICE_GET(spi_dw_port_2), DT_SPI_DW_IRQ_FLAGS); + irq_enable(DT_SPI_2_IRQ); _spi_int_unmask(SPI_DW_PORT_2_INT_MASK); #else IRQ_CONNECT(CONFIG_SPI_2_IRQ_RX_AVAIL, CONFIG_SPI_2_IRQ_RX_AVAIL_PRI, - spi_dw_isr, DEVICE_GET(spi_dw_port_2), SPI_DW_IRQ_FLAGS); + spi_dw_isr, DEVICE_GET(spi_dw_port_2), DT_SPI_DW_IRQ_FLAGS); IRQ_CONNECT(CONFIG_SPI_2_IRQ_TX_REQ, CONFIG_SPI_2_IRQ_TX_REQ_PRI, - spi_dw_isr, DEVICE_GET(spi_dw_port_2), SPI_DW_IRQ_FLAGS); + spi_dw_isr, DEVICE_GET(spi_dw_port_2), DT_SPI_DW_IRQ_FLAGS); IRQ_CONNECT(CONFIG_SPI_2_IRQ_ERR_INT, CONFIG_SPI_2_IRQ_ERR_INT_PRI, - spi_dw_isr, DEVICE_GET(spi_dw_port_2), SPI_DW_IRQ_FLAGS); + spi_dw_isr, DEVICE_GET(spi_dw_port_2), DT_SPI_DW_IRQ_FLAGS); irq_enable(CONFIG_SPI_2_IRQ_RX_AVAIL); irq_enable(CONFIG_SPI_2_IRQ_TX_REQ); @@ -678,7 +678,7 @@ struct spi_dw_data spi_dw_data_port_3 = { }; static const struct spi_dw_config spi_dw_config_3 = { - .regs = CONFIG_SPI_3_BASE_ADDRESS, + .regs = DT_SPI_3_BASE_ADDRESS, #ifdef CONFIG_SPI_DW_PORT_3_CLOCK_GATE .clock_name = CONFIG_SPI_DW_PORT_3_CLOCK_GATE_DRV_NAME, .clock_data = UINT_TO_POINTER(CONFIG_SPI_DW_PORT_3_CLOCK_GATE_SUBSYS), @@ -695,17 +695,17 @@ DEVICE_AND_API_INIT(spi_dw_port_3, CONFIG_SPI_3_NAME, spi_dw_init, void spi_config_3_irq(void) { #ifdef CONFIG_SPI_DW_PORT_3_INTERRUPT_SINGLE_LINE - IRQ_CONNECT(CONFIG_SPI_3_IRQ, CONFIG_SPI_3_IRQ_PRI, - spi_dw_isr, DEVICE_GET(spi_dw_port_3), SPI_DW_IRQ_FLAGS); - irq_enable(CONFIG_SPI_3_IRQ); + IRQ_CONNECT(DT_SPI_3_IRQ, CONFIG_SPI_3_IRQ_PRI, + spi_dw_isr, DEVICE_GET(spi_dw_port_3), DT_SPI_DW_IRQ_FLAGS); + irq_enable(DT_SPI_3_IRQ); _spi_int_unmask(SPI_DW_PORT_3_INT_MASK); #else IRQ_CONNECT(CONFIG_SPI_3_IRQ_RX_AVAIL, CONFIG_SPI_3_IRQ_RX_AVAIL_PRI, - spi_dw_isr, DEVICE_GET(spi_dw_port_3), SPI_DW_IRQ_FLAGS); + spi_dw_isr, DEVICE_GET(spi_dw_port_3), DT_SPI_DW_IRQ_FLAGS); IRQ_CONNECT(CONFIG_SPI_3_IRQ_TX_REQ, CONFIG_SPI_3_IRQ_TX_REQ_PRI, - spi_dw_isr, DEVICE_GET(spi_dw_port_3), SPI_DW_IRQ_FLAGS); + spi_dw_isr, DEVICE_GET(spi_dw_port_3), DT_SPI_DW_IRQ_FLAGS); IRQ_CONNECT(CONFIG_SPI_3_IRQ_ERR_INT, CONFIG_SPI_3_IRQ_ERR_INT_PRI, - spi_dw_isr, DEVICE_GET(spi_dw_port_3), SPI_DW_IRQ_FLAGS); + spi_dw_isr, DEVICE_GET(spi_dw_port_3), DT_SPI_DW_IRQ_FLAGS); irq_enable(CONFIG_SPI_3_IRQ_RX_AVAIL); irq_enable(CONFIG_SPI_3_IRQ_TX_REQ); diff --git a/drivers/spi/spi_dw.h b/drivers/spi/spi_dw.h index 7acb96c8b88..f43e7bee000 100644 --- a/drivers/spi/spi_dw.h +++ b/drivers/spi/spi_dw.h @@ -42,9 +42,9 @@ struct spi_dw_data { /* Helper macros */ -#ifdef SPI_DW_SPI_CLOCK +#ifdef DT_SPI_DW_SPI_CLOCK #define SPI_DW_CLK_DIVIDER(ssi_clk_hz) \ - ((SPI_DW_SPI_CLOCK / ssi_clk_hz) & 0xFFFF) + ((DT_SPI_DW_SPI_CLOCK / ssi_clk_hz) & 0xFFFF) /* provision for soc.h providing a clock that is different than CPU clock */ #else #define SPI_DW_CLK_DIVIDER(ssi_clk_hz) \ diff --git a/drivers/spi/spi_intel.c b/drivers/spi/spi_intel.c index 097c5d86a9c..af789912087 100644 --- a/drivers/spi/spi_intel.c +++ b/drivers/spi/spi_intel.c @@ -416,7 +416,7 @@ void spi_config_0_irq(void); struct spi_intel_data spi_intel_data_port_0 = { SPI_CONTEXT_INIT_LOCK(spi_intel_data_port_0, ctx), SPI_CONTEXT_INIT_SYNC(spi_intel_data_port_0, ctx), - .regs = CONFIG_SPI_0_BASE_ADDRESS, + .regs = DT_SPI_0_BASE_ADDRESS, #if CONFIG_PCI .pci_dev.class_type = SPI_INTEL_CLASS, .pci_dev.bus = SPI_INTEL_PORT_0_BUS, @@ -428,7 +428,7 @@ struct spi_intel_data spi_intel_data_port_0 = { }; const struct spi_intel_config spi_intel_config_0 = { - .irq = CONFIG_SPI_0_IRQ, + .irq = DT_SPI_0_IRQ, .config_func = spi_config_0_irq }; @@ -439,9 +439,9 @@ DEVICE_DEFINE(spi_intel_port_0, CONFIG_SPI_0_NAME, spi_intel_init, void spi_config_0_irq(void) { - IRQ_CONNECT(CONFIG_SPI_0_IRQ, CONFIG_SPI_0_IRQ_PRI, + IRQ_CONNECT(DT_SPI_0_IRQ, CONFIG_SPI_0_IRQ_PRI, spi_intel_isr, DEVICE_GET(spi_intel_port_0), - CONFIG_SPI_0_IRQ_FLAGS); + DT_SPI_0_IRQ_FLAGS); } #endif /* CONFIG_SPI_0 */ @@ -452,7 +452,7 @@ void spi_config_1_irq(void); struct spi_intel_data spi_intel_data_port_1 = { SPI_CONTEXT_INIT_LOCK(spi_intel_data_port_1, ctx), SPI_CONTEXT_INIT_SYNC(spi_intel_data_port_1, ctx), - .regs = CONFIG_SPI_1_BASE_ADDRESS, + .regs = DT_SPI_1_BASE_ADDRESS, #if CONFIG_PCI .pci_dev.class_type = SPI_INTEL_CLASS, .pci_dev.bus = SPI_INTEL_PORT_1_BUS, @@ -464,7 +464,7 @@ struct spi_intel_data spi_intel_data_port_1 = { }; const struct spi_intel_config spi_intel_config_1 = { - .irq = CONFIG_SPI_1_IRQ, + .irq = DT_SPI_1_IRQ, .config_func = spi_config_1_irq }; @@ -475,9 +475,9 @@ DEVICE_DEFINE(spi_intel_port_1, CONFIG_SPI_1_NAME, spi_intel_init, void spi_config_1_irq(void) { - IRQ_CONNECT(CONFIG_SPI_1_IRQ, CONFIG_SPI_1_IRQ_PRI, + IRQ_CONNECT(DT_SPI_1_IRQ, CONFIG_SPI_1_IRQ_PRI, spi_intel_isr, DEVICE_GET(spi_intel_port_1), - CONFIG_SPI_1_IRQ_FLAGS); + DT_SPI_1_IRQ_FLAGS); } #endif /* CONFIG_SPI_1 */ diff --git a/drivers/spi/spi_ll_stm32.c b/drivers/spi/spi_ll_stm32.c index 8290297f6c8..c2d57585b8b 100644 --- a/drivers/spi/spi_ll_stm32.c +++ b/drivers/spi/spi_ll_stm32.c @@ -484,7 +484,7 @@ static void spi_stm32_irq_config_func_1(struct device *port); #endif static const struct spi_stm32_config spi_stm32_cfg_1 = { - .spi = (SPI_TypeDef *) CONFIG_SPI_1_BASE_ADDRESS, + .spi = (SPI_TypeDef *) DT_SPI_1_BASE_ADDRESS, .pclken = { #ifdef CONFIG_SOC_SERIES_STM32F0X .enr = LL_APB1_GRP2_PERIPH_SPI1, @@ -512,9 +512,9 @@ DEVICE_AND_API_INIT(spi_stm32_1, CONFIG_SPI_1_NAME, &spi_stm32_init, #ifdef CONFIG_SPI_STM32_INTERRUPT static void spi_stm32_irq_config_func_1(struct device *dev) { - IRQ_CONNECT(CONFIG_SPI_1_IRQ, CONFIG_SPI_1_IRQ_PRI, + IRQ_CONNECT(DT_SPI_1_IRQ, CONFIG_SPI_1_IRQ_PRI, spi_stm32_isr, DEVICE_GET(spi_stm32_1), 0); - irq_enable(CONFIG_SPI_1_IRQ); + irq_enable(DT_SPI_1_IRQ); } #endif @@ -527,7 +527,7 @@ static void spi_stm32_irq_config_func_2(struct device *port); #endif static const struct spi_stm32_config spi_stm32_cfg_2 = { - .spi = (SPI_TypeDef *) CONFIG_SPI_2_BASE_ADDRESS, + .spi = (SPI_TypeDef *) DT_SPI_2_BASE_ADDRESS, .pclken = { .enr = LL_APB1_GRP1_PERIPH_SPI2, .bus = STM32_CLOCK_BUS_APB1 @@ -550,9 +550,9 @@ DEVICE_AND_API_INIT(spi_stm32_2, CONFIG_SPI_2_NAME, &spi_stm32_init, #ifdef CONFIG_SPI_STM32_INTERRUPT static void spi_stm32_irq_config_func_2(struct device *dev) { - IRQ_CONNECT(CONFIG_SPI_2_IRQ, CONFIG_SPI_2_IRQ_PRI, + IRQ_CONNECT(DT_SPI_2_IRQ, CONFIG_SPI_2_IRQ_PRI, spi_stm32_isr, DEVICE_GET(spi_stm32_2), 0); - irq_enable(CONFIG_SPI_2_IRQ); + irq_enable(DT_SPI_2_IRQ); } #endif @@ -565,7 +565,7 @@ static void spi_stm32_irq_config_func_3(struct device *port); #endif static const struct spi_stm32_config spi_stm32_cfg_3 = { - .spi = (SPI_TypeDef *) CONFIG_SPI_3_BASE_ADDRESS, + .spi = (SPI_TypeDef *) DT_SPI_3_BASE_ADDRESS, .pclken = { .enr = LL_APB1_GRP1_PERIPH_SPI3, .bus = STM32_CLOCK_BUS_APB1 @@ -588,9 +588,9 @@ DEVICE_AND_API_INIT(spi_stm32_3, CONFIG_SPI_3_NAME, &spi_stm32_init, #ifdef CONFIG_SPI_STM32_INTERRUPT static void spi_stm32_irq_config_func_3(struct device *dev) { - IRQ_CONNECT(CONFIG_SPI_3_IRQ, CONFIG_SPI_3_IRQ_PRI, + IRQ_CONNECT(DT_SPI_3_IRQ, CONFIG_SPI_3_IRQ_PRI, spi_stm32_isr, DEVICE_GET(spi_stm32_3), 0); - irq_enable(CONFIG_SPI_3_IRQ); + irq_enable(DT_SPI_3_IRQ); } #endif diff --git a/drivers/spi/spi_mcux_dspi.c b/drivers/spi/spi_mcux_dspi.c index aa716a5fd87..8c57c8bfe66 100644 --- a/drivers/spi/spi_mcux_dspi.c +++ b/drivers/spi/spi_mcux_dspi.c @@ -266,9 +266,9 @@ static const struct spi_driver_api spi_mcux_driver_api = { static void spi_mcux_config_func_0(struct device *dev); static const struct spi_mcux_config spi_mcux_config_0 = { - .base = (SPI_Type *) CONFIG_SPI_0_BASE_ADDRESS, - .clock_name = CONFIG_SPI_0_CLOCK_NAME, - .clock_subsys = (clock_control_subsys_t) CONFIG_SPI_0_CLOCK_SUBSYS, + .base = (SPI_Type *) DT_SPI_0_BASE_ADDRESS, + .clock_name = DT_SPI_0_CLOCK_NAME, + .clock_subsys = (clock_control_subsys_t) DT_SPI_0_CLOCK_SUBSYS, .irq_config_func = spi_mcux_config_func_0, }; @@ -284,10 +284,10 @@ DEVICE_AND_API_INIT(spi_mcux_0, CONFIG_SPI_0_NAME, &spi_mcux_init, static void spi_mcux_config_func_0(struct device *dev) { - IRQ_CONNECT(CONFIG_SPI_0_IRQ, CONFIG_SPI_0_IRQ_PRI, + IRQ_CONNECT(DT_SPI_0_IRQ, CONFIG_SPI_0_IRQ_PRI, spi_mcux_isr, DEVICE_GET(spi_mcux_0), 0); - irq_enable(CONFIG_SPI_0_IRQ); + irq_enable(DT_SPI_0_IRQ); } #endif /* CONFIG_SPI_0 */ @@ -295,9 +295,9 @@ static void spi_mcux_config_func_0(struct device *dev) static void spi_mcux_config_func_1(struct device *dev); static const struct spi_mcux_config spi_mcux_config_1 = { - .base = (SPI_Type *) CONFIG_SPI_1_BASE_ADDRESS, - .clock_name = CONFIG_SPI_1_CLOCK_NAME, - .clock_subsys = (clock_control_subsys_t) CONFIG_SPI_1_CLOCK_SUBSYS, + .base = (SPI_Type *) DT_SPI_1_BASE_ADDRESS, + .clock_name = DT_SPI_1_CLOCK_NAME, + .clock_subsys = (clock_control_subsys_t) DT_SPI_1_CLOCK_SUBSYS, .irq_config_func = spi_mcux_config_func_1, }; @@ -313,10 +313,10 @@ DEVICE_AND_API_INIT(spi_mcux_1, CONFIG_SPI_1_NAME, &spi_mcux_init, static void spi_mcux_config_func_1(struct device *dev) { - IRQ_CONNECT(CONFIG_SPI_1_IRQ, CONFIG_SPI_1_IRQ_PRI, + IRQ_CONNECT(DT_SPI_1_IRQ, CONFIG_SPI_1_IRQ_PRI, spi_mcux_isr, DEVICE_GET(spi_mcux_1), 0); - irq_enable(CONFIG_SPI_1_IRQ); + irq_enable(DT_SPI_1_IRQ); } #endif /* CONFIG_SPI_1 */ @@ -324,9 +324,9 @@ static void spi_mcux_config_func_1(struct device *dev) static void spi_mcux_config_func_2(struct device *dev); static const struct spi_mcux_config spi_mcux_config_2 = { - .base = (SPI_Type *) CONFIG_SPI_2_BASE_ADDRESS, - .clock_name = CONFIG_SPI_2_CLOCK_NAME, - .clock_subsys = (clock_control_subsys_t) CONFIG_SPI_2_CLOCK_SUBSYS, + .base = (SPI_Type *) DT_SPI_2_BASE_ADDRESS, + .clock_name = DT_SPI_2_CLOCK_NAME, + .clock_subsys = (clock_control_subsys_t) DT_SPI_2_CLOCK_SUBSYS, .irq_config_func = spi_mcux_config_func_2, }; @@ -342,9 +342,9 @@ DEVICE_AND_API_INIT(spi_mcux_2, CONFIG_SPI_2_NAME, &spi_mcux_init, static void spi_mcux_config_func_2(struct device *dev) { - IRQ_CONNECT(CONFIG_SPI_2_IRQ, CONFIG_SPI_2_IRQ_PRI, + IRQ_CONNECT(DT_SPI_2_IRQ, CONFIG_SPI_2_IRQ_PRI, spi_mcux_isr, DEVICE_GET(spi_mcux_2), 0); - irq_enable(CONFIG_SPI_2_IRQ); + irq_enable(DT_SPI_2_IRQ); } #endif /* CONFIG_SPI_2 */ diff --git a/drivers/spi/spi_nrfx_spi.c b/drivers/spi/spi_nrfx_spi.c index 192aad50885..61aa9c8a36b 100644 --- a/drivers/spi/spi_nrfx_spi.c +++ b/drivers/spi/spi_nrfx_spi.c @@ -278,9 +278,9 @@ static int init_spi(struct device *dev, const nrfx_spi_config_t *config) CONFIG_SPI_##idx##_IRQ_PRI, \ nrfx_isr, nrfx_spi_##idx##_irq_handler, 0); \ const nrfx_spi_config_t config = { \ - .sck_pin = CONFIG_SPI_##idx##_NRF_SCK_PIN, \ - .mosi_pin = CONFIG_SPI_##idx##_NRF_MOSI_PIN, \ - .miso_pin = CONFIG_SPI_##idx##_NRF_MISO_PIN, \ + .sck_pin = DT_SPI_##idx##_NRF_SCK_PIN, \ + .mosi_pin = DT_SPI_##idx##_NRF_MOSI_PIN, \ + .miso_pin = DT_SPI_##idx##_NRF_MISO_PIN, \ .ss_pin = NRFX_SPI_PIN_NOT_USED, \ .orc = CONFIG_SPI_##idx##_NRF_ORC, \ .frequency = NRF_SPI_FREQ_4M, \ diff --git a/drivers/spi/spi_nrfx_spim.c b/drivers/spi/spi_nrfx_spim.c index fb55e58b7f9..bc37dc2e243 100644 --- a/drivers/spi/spi_nrfx_spim.c +++ b/drivers/spi/spi_nrfx_spim.c @@ -314,9 +314,9 @@ static int init_spim(struct device *dev, const nrfx_spim_config_t *config) CONFIG_SPI_##idx##_IRQ_PRI, \ nrfx_isr, nrfx_spim_##idx##_irq_handler, 0); \ const nrfx_spim_config_t config = { \ - .sck_pin = CONFIG_SPI_##idx##_NRF_SCK_PIN, \ - .mosi_pin = CONFIG_SPI_##idx##_NRF_MOSI_PIN, \ - .miso_pin = CONFIG_SPI_##idx##_NRF_MISO_PIN, \ + .sck_pin = DT_SPI_##idx##_NRF_SCK_PIN, \ + .mosi_pin = DT_SPI_##idx##_NRF_MOSI_PIN, \ + .miso_pin = DT_SPI_##idx##_NRF_MISO_PIN, \ .ss_pin = NRFX_SPIM_PIN_NOT_USED, \ .orc = CONFIG_SPI_##idx##_NRF_ORC, \ .frequency = NRF_SPIM_FREQ_4M, \ diff --git a/drivers/spi/spi_nrfx_spis.c b/drivers/spi/spi_nrfx_spis.c index a44b7feeb8b..1135781c9c7 100644 --- a/drivers/spi/spi_nrfx_spis.c +++ b/drivers/spi/spi_nrfx_spis.c @@ -254,10 +254,10 @@ static int init_spis(struct device *dev, const nrfx_spis_config_t *config) CONFIG_SPI_##idx##_IRQ_PRI, \ nrfx_isr, nrfx_spis_##idx##_irq_handler, 0); \ const nrfx_spis_config_t config = { \ - .sck_pin = CONFIG_SPI_##idx##_NRF_SCK_PIN, \ - .mosi_pin = CONFIG_SPI_##idx##_NRF_MOSI_PIN, \ - .miso_pin = CONFIG_SPI_##idx##_NRF_MISO_PIN, \ - .csn_pin = CONFIG_SPI_##idx##_NRF_CSN_PIN, \ + .sck_pin = DT_SPI_##idx##_NRF_SCK_PIN, \ + .mosi_pin = DT_SPI_##idx##_NRF_MOSI_PIN, \ + .miso_pin = DT_SPI_##idx##_NRF_MISO_PIN, \ + .csn_pin = DT_SPI_##idx##_NRF_CSN_PIN, \ .mode = NRF_SPIS_MODE_0, \ .bit_order = NRF_SPIS_BIT_ORDER_MSB_FIRST, \ .csn_pullup = NRFX_SPIS_DEFAULT_CSN_PULLUP, \ diff --git a/drivers/spi/spi_sam.c b/drivers/spi/spi_sam.c index 4f18dcba7be..c1b0bfca6ef 100644 --- a/drivers/spi/spi_sam.c +++ b/drivers/spi/spi_sam.c @@ -452,8 +452,8 @@ static const struct spi_driver_api spi_sam_driver_api = { #define SPI_SAM_DEFINE_CONFIG(n) \ static const struct spi_sam_config spi_sam_config_##n = { \ - .regs = (Spi *)CONFIG_SPI_##n##_BASE_ADDRESS, \ - .periph_id = CONFIG_SPI_##n##_PERIPHERAL_ID, \ + .regs = (Spi *)DT_SPI_##n##_BASE_ADDRESS, \ + .periph_id = DT_SPI_##n##_PERIPHERAL_ID, \ .pins = PINS_SPI##n, \ .cs = PINS_SPI##n##_CS, \ } @@ -470,11 +470,11 @@ static const struct spi_driver_api spi_sam_driver_api = { &spi_sam_config_##n, POST_KERNEL, \ CONFIG_SPI_INIT_PRIORITY, &spi_sam_driver_api) -#if CONFIG_SPI_0_BASE_ADDRESS +#if DT_SPI_0_BASE_ADDRESS SPI_SAM_DEVICE_INIT(0); #endif -#if CONFIG_SPI_1_BASE_ADDRESS +#if DT_SPI_1_BASE_ADDRESS SPI_SAM_DEVICE_INIT(1); #endif diff --git a/drivers/spi/spi_sam0.c b/drivers/spi/spi_sam0.c index 61dc295326e..91a61152894 100644 --- a/drivers/spi/spi_sam0.c +++ b/drivers/spi/spi_sam0.c @@ -452,12 +452,12 @@ static const struct spi_driver_api spi_sam0_driver_api = { }; #define CONFIG_SPI_SAM0_SERCOM_PADS(n) \ - SERCOM_SPI_CTRLA_DIPO(CONFIG_SPI_SAM0_SERCOM##n##_DIPO) | \ - SERCOM_SPI_CTRLA_DOPO(CONFIG_SPI_SAM0_SERCOM##n##_DOPO) + SERCOM_SPI_CTRLA_DIPO(DT_SPI_SAM0_SERCOM##n##_DIPO) | \ + SERCOM_SPI_CTRLA_DOPO(DT_SPI_SAM0_SERCOM##n##_DOPO) #define SPI_SAM0_DEFINE_CONFIG(n) \ static const struct spi_sam0_config spi_sam0_config_##n = { \ - .regs = (SercomSpi *)CONFIG_SPI_SAM0_SERCOM##n##_BASE_ADDRESS, \ + .regs = (SercomSpi *)DT_SPI_SAM0_SERCOM##n##_BASE_ADDRESS, \ .pm_apbcmask = PM_APBCMASK_SERCOM##n, \ .gclk_clkctrl_id = GCLK_CLKCTRL_ID_SERCOM##n##_CORE, \ .pads = CONFIG_SPI_SAM0_SERCOM_PADS(n) \ @@ -470,31 +470,31 @@ static const struct spi_driver_api spi_sam0_driver_api = { SPI_CONTEXT_INIT_SYNC(spi_sam0_dev_data_##n, ctx), \ }; \ DEVICE_AND_API_INIT(spi_sam0_##n, \ - CONFIG_SPI_SAM0_SERCOM##n##_LABEL, \ + DT_SPI_SAM0_SERCOM##n##_LABEL, \ &spi_sam0_init, &spi_sam0_dev_data_##n, \ &spi_sam0_config_##n, POST_KERNEL, \ CONFIG_SPI_INIT_PRIORITY, &spi_sam0_driver_api) -#if CONFIG_SPI_SAM0_SERCOM0_BASE_ADDRESS +#if DT_SPI_SAM0_SERCOM0_BASE_ADDRESS SPI_SAM0_DEVICE_INIT(0); #endif -#if CONFIG_SPI_SAM0_SERCOM1_BASE_ADDRESS +#if DT_SPI_SAM0_SERCOM1_BASE_ADDRESS SPI_SAM0_DEVICE_INIT(1); #endif -#if CONFIG_SPI_SAM0_SERCOM2_BASE_ADDRESS +#if DT_SPI_SAM0_SERCOM2_BASE_ADDRESS SPI_SAM0_DEVICE_INIT(2); #endif -#if CONFIG_SPI_SAM0_SERCOM3_BASE_ADDRESS +#if DT_SPI_SAM0_SERCOM3_BASE_ADDRESS SPI_SAM0_DEVICE_INIT(3); #endif -#if CONFIG_SPI_SAM0_SERCOM4_BASE_ADDRESS +#if DT_SPI_SAM0_SERCOM4_BASE_ADDRESS SPI_SAM0_DEVICE_INIT(4); #endif -#if CONFIG_SPI_SAM0_SERCOM5_BASE_ADDRESS +#if DT_SPI_SAM0_SERCOM5_BASE_ADDRESS SPI_SAM0_DEVICE_INIT(5); #endif diff --git a/drivers/usb/device/usb_dc_kinetis.c b/drivers/usb/device/usb_dc_kinetis.c index 67a50753f39..c43e5959075 100644 --- a/drivers/usb/device/usb_dc_kinetis.c +++ b/drivers/usb/device/usb_dc_kinetis.c @@ -18,7 +18,7 @@ #include LOG_MODULE_REGISTER(usb_dc_kinetis); -#define NUM_OF_EP_MAX CONFIG_USBD_KINETIS_NUM_BIDIR_EP +#define NUM_OF_EP_MAX DT_USBD_KINETIS_NUM_BIDIR_EP #define BD_OWN_MASK (1 << 5) #define BD_DATA01_MASK (1 << 4) @@ -177,10 +177,10 @@ static int kinetis_usb_init(void) K_PRIO_COOP(2), 0, K_NO_WAIT); /* Connect and enable USB interrupt */ - IRQ_CONNECT(CONFIG_USBD_KINETIS_IRQ, CONFIG_USBD_KINETIS_IRQ_PRI, + IRQ_CONNECT(DT_USBD_KINETIS_IRQ, DT_USBD_KINETIS_IRQ_PRI, usb_kinetis_isr_handler, 0, 0); - irq_enable(CONFIG_USBD_KINETIS_IRQ); + irq_enable(DT_USBD_KINETIS_IRQ); LOG_DBG(""); diff --git a/drivers/usb/device/usb_dc_nrfx.c b/drivers/usb/device/usb_dc_nrfx.c index ef35799af71..2bc9d0f6807 100644 --- a/drivers/usb/device/usb_dc_nrfx.c +++ b/drivers/usb/device/usb_dc_nrfx.c @@ -162,18 +162,18 @@ K_MEM_POOL_DEFINE(fifo_elem_pool, FIFO_ELEM_MIN_SZ, FIFO_ELEM_MAX_SZ, */ /** Number of IN Endpoints configured (including control) */ -#define CFG_EPIN_CNT (CONFIG_USBD_NRF_NUM_IN_EP + \ - CONFIG_USBD_NRF_NUM_BIDIR_EP) +#define CFG_EPIN_CNT (DT_USBD_NRF_NUM_IN_EP + \ + DT_USBD_NRF_NUM_BIDIR_EP) /** Number of OUT Endpoints configured (including control) */ -#define CFG_EPOUT_CNT (CONFIG_USBD_NRF_NUM_OUT_EP + \ - CONFIG_USBD_NRF_NUM_BIDIR_EP) +#define CFG_EPOUT_CNT (DT_USBD_NRF_NUM_OUT_EP + \ + DT_USBD_NRF_NUM_BIDIR_EP) /** Number of ISO IN Endpoints */ -#define CFG_EP_ISOIN_CNT CONFIG_USBD_NRF_NUM_ISOIN_EP +#define CFG_EP_ISOIN_CNT DT_USBD_NRF_NUM_ISOIN_EP /** Number of ISO OUT Endpoints */ -#define CFG_EP_ISOOUT_CNT CONFIG_USBD_NRF_NUM_ISOOUT_EP +#define CFG_EP_ISOOUT_CNT DT_USBD_NRF_NUM_ISOOUT_EP /** ISO endpoint index */ #define EP_ISOIN_INDEX CFG_EPIN_CNT @@ -1038,8 +1038,8 @@ int usb_dc_attach(void) k_fifo_init(&ctx->work_queue); k_sem_init(&ctx->dma_in_use, 1, 1); - IRQ_CONNECT(CONFIG_USBD_NRF_IRQ, - CONFIG_USBD_NRF_IRQ_PRI, + IRQ_CONNECT(DT_USBD_NRF_IRQ, + DT_USBD_NRF_IRQ_PRI, nrfx_isr, nrfx_usbd_irq_handler, 0); /* NOTE: Non-blocking HF clock enable can return -EINPROGRESS diff --git a/drivers/usb/device/usb_dc_sam.c b/drivers/usb/device/usb_dc_sam.c index 1f5be233235..1fb85703fc5 100644 --- a/drivers/usb/device/usb_dc_sam.c +++ b/drivers/usb/device/usb_dc_sam.c @@ -34,7 +34,7 @@ struct usb_device_ep_data { struct usb_device_data { bool addr_enabled; usb_dc_status_callback status_cb; - struct usb_device_ep_data ep_data[CONFIG_USBHS_NUM_BIDIR_EP]; + struct usb_device_ep_data ep_data[DT_USBHS_NUM_BIDIR_EP]; }; static struct usb_device_data dev_data; @@ -245,7 +245,7 @@ static void usb_dc_isr(void) } /* Other endpoints interrupt */ - for (int ep_idx = 1; ep_idx < CONFIG_USBHS_NUM_BIDIR_EP; ep_idx++) { + for (int ep_idx = 1; ep_idx < DT_USBHS_NUM_BIDIR_EP; ep_idx++) { if (sr & BIT(USBHS_DEVISR_PEP_0_Pos + ep_idx)) { usb_dc_ep_isr(ep_idx); } @@ -258,7 +258,7 @@ int usb_dc_attach(void) u32_t regval; /* Start the peripheral clock */ - soc_pmc_peripheral_enable(CONFIG_USBHS_PERIPHERAL_ID); + soc_pmc_peripheral_enable(DT_USBHS_PERIPHERAL_ID); /* Enable the USB controller in device mode with the clock frozen */ USBHS->USBHS_CTRL = USBHS_CTRL_UIMOD | USBHS_CTRL_USBE | @@ -267,12 +267,12 @@ int usb_dc_attach(void) /* Select the speed */ regval = USBHS_DEVCTRL_DETACH; -#ifdef CONFIG_USBHS_MAXIMUM_SPEED - if (!strncmp(CONFIG_USBHS_MAXIMUM_SPEED, "high-speed", 10)) { +#ifdef DT_USBHS_MAXIMUM_SPEED + if (!strncmp(DT_USBHS_MAXIMUM_SPEED, "high-speed", 10)) { regval |= USBHS_DEVCTRL_SPDCONF_NORMAL; - } else if (!strncmp(CONFIG_USBHS_MAXIMUM_SPEED, "full-speed", 10)) { + } else if (!strncmp(DT_USBHS_MAXIMUM_SPEED, "full-speed", 10)) { regval |= USBHS_DEVCTRL_SPDCONF_LOW_POWER; - } else if (!strncmp(CONFIG_USBHS_MAXIMUM_SPEED, "low-speed", 9)) { + } else if (!strncmp(DT_USBHS_MAXIMUM_SPEED, "low-speed", 9)) { regval |= USBHS_DEVCTRL_LS; regval |= USBHS_DEVCTRL_SPDCONF_LOW_POWER; } else { @@ -298,8 +298,8 @@ int usb_dc_attach(void) USBHS->USBHS_DEVIER = USBHS_DEVIER_SUSPES; /* Connect and enable the interrupt */ - IRQ_CONNECT(CONFIG_USBHS_IRQ, CONFIG_USBHS_IRQ_PRI, usb_dc_isr, 0, 0); - irq_enable(CONFIG_USBHS_IRQ); + IRQ_CONNECT(DT_USBHS_IRQ, DT_USBHS_IRQ_PRI, usb_dc_isr, 0, 0); + irq_enable(DT_USBHS_IRQ); /* Attach the device */ USBHS->USBHS_DEVCTRL &= ~USBHS_DEVCTRL_DETACH; @@ -321,10 +321,10 @@ int usb_dc_detach(void) USBHS->USBHS_CTRL = USBHS_CTRL_UIMOD | USBHS_CTRL_FRZCLK; /* Disable the peripheral clock */ - soc_pmc_peripheral_enable(CONFIG_USBHS_PERIPHERAL_ID); + soc_pmc_peripheral_enable(DT_USBHS_PERIPHERAL_ID); /* Disable interrupt */ - irq_disable(CONFIG_USBHS_IRQ); + irq_disable(DT_USBHS_IRQ); LOG_DBG(""); return 0; @@ -371,7 +371,7 @@ int usb_dc_ep_check_cap(const struct usb_dc_ep_cfg_data * const cfg) { u8_t ep_idx = EP_ADDR2IDX(cfg->ep_addr); - if (ep_idx >= CONFIG_USBHS_NUM_BIDIR_EP) { + if (ep_idx >= DT_USBHS_NUM_BIDIR_EP) { LOG_ERR("endpoint index/address out of range"); return -1; } @@ -406,8 +406,8 @@ int usb_dc_ep_check_cap(const struct usb_dc_ep_cfg_data * const cfg) int usb_dc_ep_configure(const struct usb_dc_ep_cfg_data *const cfg) { u8_t ep_idx = EP_ADDR2IDX(cfg->ep_addr); - bool ep_configured[CONFIG_USBHS_NUM_BIDIR_EP]; - bool ep_enabled[CONFIG_USBHS_NUM_BIDIR_EP]; + bool ep_configured[DT_USBHS_NUM_BIDIR_EP]; + bool ep_enabled[DT_USBHS_NUM_BIDIR_EP]; u32_t regval = 0; int log2ceil_mps; @@ -482,7 +482,7 @@ int usb_dc_ep_configure(const struct usb_dc_ep_cfg_data *const cfg) * enabled, deallocate their memory if needed. Then loop again through * all the above endpoints to allocate and enabled them. */ - for (int i = CONFIG_USBHS_NUM_BIDIR_EP - 1; i > ep_idx; i--) { + for (int i = DT_USBHS_NUM_BIDIR_EP - 1; i > ep_idx; i--) { ep_configured[i] = usb_dc_ep_is_configured(i); ep_enabled[i] = usb_dc_ep_is_enabled(i); @@ -495,7 +495,7 @@ int usb_dc_ep_configure(const struct usb_dc_ep_cfg_data *const cfg) } ep_configured[ep_idx] = true; ep_enabled[ep_idx] = false; - for (int i = ep_idx; i < CONFIG_USBHS_NUM_BIDIR_EP; i++) { + for (int i = ep_idx; i < DT_USBHS_NUM_BIDIR_EP; i++) { if (ep_configured[i]) { USBHS->USBHS_DEVEPTCFG[i] |= USBHS_DEVEPTCFG_ALLOC; } @@ -518,7 +518,7 @@ int usb_dc_ep_set_stall(u8_t ep) { u8_t ep_idx = EP_ADDR2IDX(ep); - if (ep_idx >= CONFIG_USBHS_NUM_BIDIR_EP) { + if (ep_idx >= DT_USBHS_NUM_BIDIR_EP) { LOG_ERR("wrong endpoint index/address"); return -EINVAL; } @@ -534,7 +534,7 @@ int usb_dc_ep_clear_stall(u8_t ep) { u8_t ep_idx = EP_ADDR2IDX(ep); - if (ep_idx >= CONFIG_USBHS_NUM_BIDIR_EP) { + if (ep_idx >= DT_USBHS_NUM_BIDIR_EP) { LOG_ERR("wrong endpoint index/address"); return -EINVAL; } @@ -550,7 +550,7 @@ int usb_dc_ep_is_stalled(u8_t ep, u8_t *stalled) { u8_t ep_idx = EP_ADDR2IDX(ep); - if (ep_idx >= CONFIG_USBHS_NUM_BIDIR_EP) { + if (ep_idx >= DT_USBHS_NUM_BIDIR_EP) { LOG_ERR("wrong endpoint index/address"); return -EINVAL; } @@ -573,7 +573,7 @@ int usb_dc_ep_enable(u8_t ep) { u8_t ep_idx = EP_ADDR2IDX(ep); - if (ep_idx >= CONFIG_USBHS_NUM_BIDIR_EP) { + if (ep_idx >= DT_USBHS_NUM_BIDIR_EP) { LOG_ERR("wrong endpoint index/address"); return -EINVAL; } @@ -601,7 +601,7 @@ int usb_dc_ep_disable(u8_t ep) { u8_t ep_idx = EP_ADDR2IDX(ep); - if (ep_idx >= CONFIG_USBHS_NUM_BIDIR_EP) { + if (ep_idx >= DT_USBHS_NUM_BIDIR_EP) { LOG_ERR("wrong endpoint index/address"); return -EINVAL; } @@ -621,7 +621,7 @@ int usb_dc_ep_flush(u8_t ep) { u8_t ep_idx = EP_ADDR2IDX(ep); - if (ep_idx >= CONFIG_USBHS_NUM_BIDIR_EP) { + if (ep_idx >= DT_USBHS_NUM_BIDIR_EP) { LOG_ERR("wrong endpoint index/address"); return -EINVAL; } @@ -660,7 +660,7 @@ int usb_dc_ep_write(u8_t ep, const u8_t *data, u32_t data_len, u32_t *ret_bytes) u8_t ep_idx = EP_ADDR2IDX(ep); u32_t packet_len = min(data_len, usb_dc_ep_mps(ep)); - if (ep_idx >= CONFIG_USBHS_NUM_BIDIR_EP) { + if (ep_idx >= DT_USBHS_NUM_BIDIR_EP) { LOG_ERR("wrong endpoint index/address"); return -EINVAL; } @@ -743,7 +743,7 @@ int usb_dc_ep_set_callback(u8_t ep, const usb_dc_ep_callback cb) { u8_t ep_idx = EP_ADDR2IDX(ep); - if (ep_idx >= CONFIG_USBHS_NUM_BIDIR_EP) { + if (ep_idx >= DT_USBHS_NUM_BIDIR_EP) { LOG_ERR("wrong endpoint index/address"); return -EINVAL; } @@ -766,7 +766,7 @@ int usb_dc_ep_read_wait(u8_t ep, u8_t *data, u32_t max_data_len, u32_t data_len = (USBHS->USBHS_DEVEPTISR[ep_idx] & USBHS_DEVEPTISR_BYCT_Msk) >> USBHS_DEVEPTISR_BYCT_Pos; - if (ep_idx >= CONFIG_USBHS_NUM_BIDIR_EP) { + if (ep_idx >= DT_USBHS_NUM_BIDIR_EP) { LOG_ERR("wrong endpoint index/address"); return -EINVAL; } @@ -821,7 +821,7 @@ int usb_dc_ep_read_continue(u8_t ep) { u8_t ep_idx = EP_ADDR2IDX(ep); - if (ep_idx >= CONFIG_USBHS_NUM_BIDIR_EP) { + if (ep_idx >= DT_USBHS_NUM_BIDIR_EP) { LOG_ERR("wrong endpoint index/address"); return -EINVAL; } @@ -861,7 +861,7 @@ int usb_dc_ep_mps(u8_t ep) { u8_t ep_idx = EP_ADDR2IDX(ep); - if (ep_idx >= CONFIG_USBHS_NUM_BIDIR_EP) { + if (ep_idx >= DT_USBHS_NUM_BIDIR_EP) { LOG_ERR("wrong endpoint index/address"); return -EINVAL; } diff --git a/drivers/usb/device/usb_dc_sam0.c b/drivers/usb/device/usb_dc_sam0.c index f55ace6c7e4..20708bf1883 100644 --- a/drivers/usb/device/usb_dc_sam0.c +++ b/drivers/usb/device/usb_dc_sam0.c @@ -21,8 +21,8 @@ LOG_MODULE_REGISTER(usb_dc_sam0); #define USB_SAM0_IN_EP 0x80 -#define REGS ((Usb *)CONFIG_USB_DC_SAM0_BASE_ADDRESS) -#define USB_NUM_ENDPOINTS CONFIG_USB_DC_SAM0_NUM_BIDIR_ENDPOINTS +#define REGS ((Usb *)DT_USB_DC_SAM0_BASE_ADDRESS) +#define USB_NUM_ENDPOINTS DT_USB_DC_SAM0_NUM_BIDIR_ENDPOINTS struct usb_sam0_data { UsbDeviceDescriptor descriptors[USB_NUM_ENDPOINTS]; @@ -203,9 +203,9 @@ int usb_dc_attach(void) regs->INTENSET.reg = USB_DEVICE_INTENSET_EORST; /* Connect and enable the interrupt */ - IRQ_CONNECT(CONFIG_USB_DC_SAM0_IRQ, CONFIG_USB_DC_SAM0_IRQ_PRIORITY, + IRQ_CONNECT(DT_USB_DC_SAM0_IRQ, DT_USB_DC_SAM0_IRQ_PRIORITY, usb_sam0_isr, 0, 0); - irq_enable(CONFIG_USB_DC_SAM0_IRQ); + irq_enable(DT_USB_DC_SAM0_IRQ); /* Enable and attach */ regs->CTRLA.bit.ENABLE = 1; @@ -231,7 +231,7 @@ int usb_dc_reset(void) { UsbDevice *regs = ®S->DEVICE; - irq_disable(CONFIG_USB_DC_SAM0_IRQ); + irq_disable(DT_USB_DC_SAM0_IRQ); regs->CTRLA.bit.SWRST = 1; usb_sam0_wait_syncbusy(); @@ -269,7 +269,7 @@ int usb_dc_ep_check_cap(const struct usb_dc_ep_cfg_data * const cfg) return -1; } - if (ep_idx > CONFIG_USB_DC_SAM0_NUM_BIDIR_ENDPOINTS) { + if (ep_idx > DT_USB_DC_SAM0_NUM_BIDIR_ENDPOINTS) { LOG_ERR("endpoint index/address too high"); return -1; } diff --git a/drivers/usb/device/usb_dc_stm32.c b/drivers/usb/device/usb_dc_stm32.c index c1c79248355..38cdbdae38b 100644 --- a/drivers/usb/device/usb_dc_stm32.c +++ b/drivers/usb/device/usb_dc_stm32.c @@ -55,7 +55,7 @@ #include LOG_MODULE_REGISTER(usb_dc_stm32); -#if defined(CONFIG_USB_BASE_ADDRESS) && defined(CONFIG_USB_HS_BASE_ADDRES) +#if defined(DT_USB_BASE_ADDRESS) && defined(CONFIG_USB_HS_BASE_ADDRES) #error "Only one interface should be enabled at a time, OTG FS or OTG HS" #endif @@ -92,7 +92,7 @@ LOG_MODULE_REGISTER(usb_dc_stm32); * per endpoint. * */ -#define USB_BTABLE_SIZE (8 * CONFIG_USB_NUM_BIDIR_ENDPOINTS) +#define USB_BTABLE_SIZE (8 * DT_USB_NUM_BIDIR_ENDPOINTS) #else /* USB_OTG_FS */ @@ -106,17 +106,17 @@ LOG_MODULE_REGISTER(usb_dc_stm32); #endif /* CONFIG_SOC_SERIES_STM32L4X */ #define EP0_MPS USB_OTG_MAX_EP0_SIZE -#ifdef CONFIG_USB_HS_BASE_ADDRESS +#ifdef DT_USB_HS_BASE_ADDRESS #define EP_MPS USB_OTG_HS_MAX_PACKET_SIZE #else #define EP_MPS USB_OTG_FS_MAX_PACKET_SIZE -#endif /* CONFIG_USB_HS_BASE_ADDRESS */ +#endif /* DT_USB_HS_BASE_ADDRESS */ /* We need one RX FIFO and n TX-IN FIFOs */ -#define FIFO_NUM (1 + CONFIG_USB_NUM_BIDIR_ENDPOINTS) +#define FIFO_NUM (1 + DT_USB_NUM_BIDIR_ENDPOINTS) /* 4-byte words FIFO */ -#define FIFO_WORDS (CONFIG_USB_RAM_SIZE / 4) +#define FIFO_WORDS (DT_USB_RAM_SIZE / 4) /* Allocate FIFO memory evenly between the FIFOs */ #define FIFO_EP_WORDS (FIFO_WORDS / FIFO_NUM) @@ -150,9 +150,9 @@ struct usb_dc_stm32_ep_state { struct usb_dc_stm32_state { PCD_HandleTypeDef pcd; /* Storage for the HAL_PCD api */ usb_dc_status_callback status_cb; /* Status callback */ - struct usb_dc_stm32_ep_state out_ep_state[CONFIG_USB_NUM_BIDIR_ENDPOINTS]; - struct usb_dc_stm32_ep_state in_ep_state[CONFIG_USB_NUM_BIDIR_ENDPOINTS]; - u8_t ep_buf[CONFIG_USB_NUM_BIDIR_ENDPOINTS][EP_MPS]; + struct usb_dc_stm32_ep_state out_ep_state[DT_USB_NUM_BIDIR_ENDPOINTS]; + struct usb_dc_stm32_ep_state in_ep_state[DT_USB_NUM_BIDIR_ENDPOINTS]; + u8_t ep_buf[DT_USB_NUM_BIDIR_ENDPOINTS][EP_MPS]; #ifdef USB u32_t pma_offset; @@ -167,7 +167,7 @@ static struct usb_dc_stm32_ep_state *usb_dc_stm32_get_ep_state(u8_t ep) { struct usb_dc_stm32_ep_state *ep_state_base; - if (EP_IDX(ep) >= CONFIG_USB_NUM_BIDIR_ENDPOINTS) { + if (EP_IDX(ep) >= DT_USB_NUM_BIDIR_ENDPOINTS) { return NULL; } @@ -190,10 +190,10 @@ static int usb_dc_stm32_clock_enable(void) struct device *clk = device_get_binding(STM32_CLOCK_CONTROL_NAME); struct stm32_pclken pclken = { -#ifdef CONFIG_USB_HS_BASE_ADDRESS +#ifdef DT_USB_HS_BASE_ADDRESS .bus = STM32_CLOCK_BUS_AHB1, .enr = LL_AHB1_GRP1_PERIPH_OTGHS -#else /* CONFIG_USB_HS_BASE_ADDRESS */ +#else /* DT_USB_HS_BASE_ADDRESS */ #ifdef USB .bus = STM32_CLOCK_BUS_APB1, @@ -211,7 +211,7 @@ static int usb_dc_stm32_clock_enable(void) #endif /* USB */ -#endif /* CONFIG_USB_HS_BASE_ADDRESS */ +#endif /* DT_USB_HS_BASE_ADDRESS */ }; /* @@ -255,7 +255,7 @@ static int usb_dc_stm32_clock_enable(void) clock_control_on(clk, (clock_control_subsys_t *)&pclken); -#ifdef CONFIG_USB_HS_BASE_ADDRESS +#ifdef DT_USB_HS_BASE_ADDRESS #ifdef USB_HS_PHYC @@ -267,7 +267,7 @@ static int usb_dc_stm32_clock_enable(void) LL_AHB1_GRP1_DisableClockLowPower(LL_AHB1_GRP1_PERIPH_OTGHSULPI); #endif /* USB_HS_PHYC */ -#endif /* CONFIG_USB_HS_BASE_ADDRESS */ +#endif /* DT_USB_HS_BASE_ADDRESS */ return 0; } @@ -279,23 +279,23 @@ static u32_t usb_dc_stm32_get_maximum_speed(void) * If max-speed is not passed via DT, set it to USB controller's * maximum hardware capability. */ -#if defined(USB_HS_PHYC) && defined(CONFIG_USB_HS_BASE_ADDRESS) +#if defined(USB_HS_PHYC) && defined(DT_USB_HS_BASE_ADDRESS) u32_t speed = USB_OTG_SPEED_HIGH; #else u32_t speed = USB_OTG_SPEED_FULL; -#endif /* USB_HS_PHYC && CONFIG_USB_HS_BASE_ADDRESS */ +#endif /* USB_HS_PHYC && DT_USB_HS_BASE_ADDRESS */ -#ifdef CONFIG_USB_MAXIMUM_SPEED +#ifdef DT_USB_MAXIMUM_SPEED - if (!strncmp(CONFIG_USB_MAXIMUM_SPEED, "high-speed", 10)) { + if (!strncmp(DT_USB_MAXIMUM_SPEED, "high-speed", 10)) { speed = USB_OTG_SPEED_HIGH; - } else if (!strncmp(CONFIG_USB_MAXIMUM_SPEED, "full-speed", 10)) { -#if defined(USB_HS_PHYC) && defined(CONFIG_USB_HS_BASE_ADDRESS) + } else if (!strncmp(DT_USB_MAXIMUM_SPEED, "full-speed", 10)) { +#if defined(USB_HS_PHYC) && defined(DT_USB_HS_BASE_ADDRESS) speed = USB_OTG_SPEED_HIGH_IN_FULL; #else speed = USB_OTG_SPEED_FULL; -#endif /* USB_HS_PHYC && CONFIG_USB_HS_BASE_ADDRESS */ - } else if (!strncmp(CONFIG_USB_MAXIMUM_SPEED, "low-speed", 9)) { +#endif /* USB_HS_PHYC && DT_USB_HS_BASE_ADDRESS */ + } else if (!strncmp(DT_USB_MAXIMUM_SPEED, "low-speed", 9)) { speed = USB_OTG_SPEED_LOW; } else { LOG_DBG("Unsupported maximum speed defined in device tree. " @@ -316,19 +316,19 @@ static int usb_dc_stm32_init(void) #ifdef USB usb_dc_stm32_state.pcd.Instance = USB; usb_dc_stm32_state.pcd.Init.speed = PCD_SPEED_FULL; - usb_dc_stm32_state.pcd.Init.dev_endpoints = CONFIG_USB_NUM_BIDIR_ENDPOINTS; + usb_dc_stm32_state.pcd.Init.dev_endpoints = DT_USB_NUM_BIDIR_ENDPOINTS; usb_dc_stm32_state.pcd.Init.phy_itface = PCD_PHY_EMBEDDED; usb_dc_stm32_state.pcd.Init.ep0_mps = PCD_EP0MPS_64; usb_dc_stm32_state.pcd.Init.low_power_enable = 0; #else /* USB_OTG_FS || USB_OTG_HS */ -#ifdef CONFIG_USB_HS_BASE_ADDRESS +#ifdef DT_USB_HS_BASE_ADDRESS usb_dc_stm32_state.pcd.Instance = USB_OTG_HS; #else usb_dc_stm32_state.pcd.Instance = USB_OTG_FS; #endif - usb_dc_stm32_state.pcd.Init.dev_endpoints = CONFIG_USB_NUM_BIDIR_ENDPOINTS; + usb_dc_stm32_state.pcd.Init.dev_endpoints = DT_USB_NUM_BIDIR_ENDPOINTS; usb_dc_stm32_state.pcd.Init.speed = usb_dc_stm32_get_maximum_speed(); -#if defined(USB_HS_PHYC) && defined(CONFIG_USB_HS_BASE_ADDRESS) +#if defined(USB_HS_PHYC) && defined(DT_USB_HS_BASE_ADDRESS) usb_dc_stm32_state.pcd.Init.phy_itface = USB_OTG_HS_EMBEDDED_PHY; #else usb_dc_stm32_state.pcd.Init.phy_itface = PCD_PHY_EMBEDDED; @@ -365,22 +365,22 @@ static int usb_dc_stm32_init(void) /* Start PMA configuration for the endpoints after the BTABLE. */ usb_dc_stm32_state.pma_offset = USB_BTABLE_SIZE; - for (i = 0; i < CONFIG_USB_NUM_BIDIR_ENDPOINTS; i++) { + for (i = 0; i < DT_USB_NUM_BIDIR_ENDPOINTS; i++) { k_sem_init(&usb_dc_stm32_state.in_ep_state[i].write_sem, 1, 1); } #else /* USB_OTG_FS */ /* TODO: make this dynamic (depending usage) */ HAL_PCDEx_SetRxFiFo(&usb_dc_stm32_state.pcd, FIFO_EP_WORDS); - for (i = 0; i < CONFIG_USB_NUM_BIDIR_ENDPOINTS; i++) { + for (i = 0; i < DT_USB_NUM_BIDIR_ENDPOINTS; i++) { HAL_PCDEx_SetTxFiFo(&usb_dc_stm32_state.pcd, i, FIFO_EP_WORDS); k_sem_init(&usb_dc_stm32_state.in_ep_state[i].write_sem, 1, 1); } #endif /* USB */ - IRQ_CONNECT(CONFIG_USB_IRQ, CONFIG_USB_IRQ_PRI, + IRQ_CONNECT(DT_USB_IRQ, DT_USB_IRQ_PRI, usb_dc_stm32_isr, 0, 0); - irq_enable(CONFIG_USB_IRQ); + irq_enable(DT_USB_IRQ); return 0; } @@ -526,7 +526,7 @@ int usb_dc_ep_check_cap(const struct usb_dc_ep_cfg_data * const cfg) return -1; } - if (ep_idx > CONFIG_USB_NUM_BIDIR_ENDPOINTS) { + if (ep_idx > DT_USB_NUM_BIDIR_ENDPOINTS) { LOG_ERR("endpoint index/address out of range"); return -1; } @@ -547,7 +547,7 @@ int usb_dc_ep_configure(const struct usb_dc_ep_cfg_data * const ep_cfg) } #ifdef USB - if (CONFIG_USB_RAM_SIZE <= + if (DT_USB_RAM_SIZE <= (usb_dc_stm32_state.pma_offset + ep_cfg->ep_mps)) { return -EINVAL; } @@ -713,7 +713,7 @@ int usb_dc_ep_write(const u8_t ep, const u8_t *const data, } if (!k_is_in_isr()) { - irq_disable(CONFIG_USB_IRQ); + irq_disable(DT_USB_IRQ); } if (ep == EP0_IN && len > MAX_PACKET_SIZE0) { @@ -737,7 +737,7 @@ int usb_dc_ep_write(const u8_t ep, const u8_t *const data, } if (!k_is_in_isr()) { - irq_enable(CONFIG_USB_IRQ); + irq_enable(DT_USB_IRQ); } if (ret_bytes) { @@ -942,18 +942,18 @@ void HAL_PCDEx_SetConnectionState(PCD_HandleTypeDef *hpcd, uint8_t state) struct device *usb_disconnect; usb_disconnect = device_get_binding( - CONFIG_USB_DC_STM32_DISCONN_GPIO_PORT_NAME); + DT_USB_DC_STM32_DISCONN_GPIO_PORT_NAME); gpio_pin_configure(usb_disconnect, - CONFIG_USB_DC_STM32_DISCONN_PIN, GPIO_DIR_OUT); + DT_USB_DC_STM32_DISCONN_PIN, GPIO_DIR_OUT); if (state) { gpio_pin_write(usb_disconnect, - CONFIG_USB_DC_STM32_DISCONN_PIN, - CONFIG_USB_DC_STM32_DISCONN_PIN_LEVEL); + DT_USB_DC_STM32_DISCONN_PIN, + DT_USB_DC_STM32_DISCONN_PIN_LEVEL); } else { gpio_pin_write(usb_disconnect, - CONFIG_USB_DC_STM32_DISCONN_PIN, - !CONFIG_USB_DC_STM32_DISCONN_PIN_LEVEL); + DT_USB_DC_STM32_DISCONN_PIN, + !DT_USB_DC_STM32_DISCONN_PIN_LEVEL); } } #endif /* USB && CONFIG_USB_DC_STM32_DISCONN_ENABLE */ diff --git a/drivers/watchdog/wdog_cmsdk_apb.c b/drivers/watchdog/wdog_cmsdk_apb.c index cebb4199a9c..eaf1eb2e84e 100644 --- a/drivers/watchdog/wdog_cmsdk_apb.c +++ b/drivers/watchdog/wdog_cmsdk_apb.c @@ -57,7 +57,7 @@ struct wdog_cmsdk_apb { #define CMSDK_APB_WDOG_LOCK_VALUE (0x2BDDF662) #define WDOG_STRUCT \ - ((volatile struct wdog_cmsdk_apb *)(CMSDK_APB_WDOG)) + ((volatile struct wdog_cmsdk_apb *)(DT_CMSDK_APB_WDOG)) /* Keep reference of the device to pass it to the callback */ struct device *wdog_r; diff --git a/drivers/watchdog/wdt_mcux_wdog.c b/drivers/watchdog/wdt_mcux_wdog.c index a35d1aa02e7..20d93805ece 100644 --- a/drivers/watchdog/wdt_mcux_wdog.c +++ b/drivers/watchdog/wdt_mcux_wdog.c @@ -165,9 +165,9 @@ static const struct wdt_driver_api mcux_wdog_api = { static void mcux_wdog_config_func_0(struct device *dev); static const struct mcux_wdog_config mcux_wdog_config_0 = { - .base = (WDOG_Type *) CONFIG_WDT_0_BASE_ADDRESS, - .clock_name = CONFIG_WDT_0_CLOCK_NAME, - .clock_subsys = (clock_control_subsys_t) CONFIG_WDT_0_CLOCK_SUBSYS, + .base = (WDOG_Type *) DT_WDT_0_BASE_ADDRESS, + .clock_name = DT_WDT_0_CLOCK_NAME, + .clock_subsys = (clock_control_subsys_t) DT_WDT_0_CLOCK_SUBSYS, .irq_config_func = mcux_wdog_config_func_0, }; @@ -180,8 +180,8 @@ DEVICE_AND_API_INIT(mcux_wdog_0, CONFIG_WDT_0_NAME, &mcux_wdog_init, static void mcux_wdog_config_func_0(struct device *dev) { - IRQ_CONNECT(CONFIG_WDT_0_IRQ, CONFIG_WDT_0_IRQ_PRI, + IRQ_CONNECT(DT_WDT_0_IRQ, DT_WDT_0_IRQ_PRI, mcux_wdog_isr, DEVICE_GET(mcux_wdog_0), 0); - irq_enable(CONFIG_WDT_0_IRQ); + irq_enable(DT_WDT_0_IRQ); } diff --git a/drivers/watchdog/wdt_nrfx.c b/drivers/watchdog/wdt_nrfx.c index 4297789c6a3..063f2fa44cc 100644 --- a/drivers/watchdog/wdt_nrfx.c +++ b/drivers/watchdog/wdt_nrfx.c @@ -197,9 +197,9 @@ static int init_wdt(struct device *dev) return -EBUSY; } - IRQ_CONNECT(CONFIG_WDT_NRF_IRQ, CONFIG_WDT_NRF_IRQ_PRI, + IRQ_CONNECT(DT_WDT_NRF_IRQ, DT_WDT_NRF_IRQ_PRI, nrfx_isr, nrfx_wdt_irq_handler, 0); - irq_enable(CONFIG_WDT_NRF_IRQ); + irq_enable(DT_WDT_NRF_IRQ); return 0; } diff --git a/drivers/watchdog/wdt_qmsi.c b/drivers/watchdog/wdt_qmsi.c index d160af4d182..5a9a5374492 100644 --- a/drivers/watchdog/wdt_qmsi.c +++ b/drivers/watchdog/wdt_qmsi.c @@ -218,8 +218,8 @@ static int init(struct device *dev) k_sem_init(RP_GET(dev), 1, UINT_MAX); } - IRQ_CONNECT(CONFIG_WDT_0_IRQ, CONFIG_WDT_0_IRQ_PRI, - qm_wdt_0_isr, 0, CONFIG_WDT_0_IRQ_FLAGS); + IRQ_CONNECT(DT_WDT_0_IRQ, DT_WDT_0_IRQ_PRI, + qm_wdt_0_isr, 0, DT_WDT_0_IRQ_FLAGS); /* Unmask watchdog interrupt */ irq_enable(IRQ_GET_NUMBER(QM_IRQ_WDT_0_INT)); diff --git a/drivers/watchdog/wdt_sam.c b/drivers/watchdog/wdt_sam.c index c0e749400c2..b073e3fcdc6 100644 --- a/drivers/watchdog/wdt_sam.c +++ b/drivers/watchdog/wdt_sam.c @@ -228,15 +228,15 @@ static const struct wdt_driver_api wdt_sam_api = { }; static const struct wdt_sam_dev_cfg wdt_sam_cfg = { - .regs = (Wdt *)CONFIG_WDT_SAM_BASE_ADDRESS, + .regs = (Wdt *)DT_WDT_SAM_BASE_ADDRESS, }; static void wdt_sam_irq_config(void) { - IRQ_CONNECT(CONFIG_WDT_SAM_IRQ, - CONFIG_WDT_SAM_IRQ_PRIORITY, wdt_sam_isr, + IRQ_CONNECT(DT_WDT_SAM_IRQ, + DT_WDT_SAM_IRQ_PRIORITY, wdt_sam_isr, DEVICE_GET(wdt_sam), 0); - irq_enable(CONFIG_WDT_SAM_IRQ); + irq_enable(DT_WDT_SAM_IRQ); } static int wdt_sam_init(struct device *dev) diff --git a/drivers/watchdog/wdt_sam0.c b/drivers/watchdog/wdt_sam0.c index ef11f33e5d3..3501cf62dc0 100644 --- a/drivers/watchdog/wdt_sam0.c +++ b/drivers/watchdog/wdt_sam0.c @@ -7,7 +7,7 @@ #include #include -#define WDT_REGS ((Wdt *)CONFIG_WDT_SAM0_BASE_ADDRESS) +#define WDT_REGS ((Wdt *)DT_WDT_SAM0_BASE_ADDRESS) struct wdt_sam0_dev_data { void (*cb)(struct device *dev); @@ -143,10 +143,10 @@ static int wdt_sam0_init(struct device *dev) | GCLK_CLKCTRL_GEN_GCLK2 | GCLK_CLKCTRL_CLKEN; - IRQ_CONNECT(CONFIG_WDT_SAM0_IRQ, - CONFIG_WDT_SAM0_IRQ_PRIORITY, wdt_sam0_isr, + IRQ_CONNECT(DT_WDT_SAM0_IRQ, + DT_WDT_SAM0_IRQ_PRIORITY, wdt_sam0_isr, DEVICE_GET(wdt_sam0), 0); - irq_enable(CONFIG_WDT_SAM0_IRQ); + irq_enable(DT_WDT_SAM0_IRQ); return 0; } diff --git a/drivers/wifi/eswifi/eswifi_bus_spi.c b/drivers/wifi/eswifi/eswifi_bus_spi.c index 21508ba5825..9b3398b1a61 100644 --- a/drivers/wifi/eswifi/eswifi_bus_spi.c +++ b/drivers/wifi/eswifi/eswifi_bus_spi.c @@ -225,8 +225,8 @@ int eswifi_spi_init(struct eswifi_dev *eswifi) SPI_WORD_SET(16) | SPI_LINES_SINGLE | SPI_HOLD_ON_CS | SPI_LOCK_ON); spi->spi_cfg.slave = ESWIFI0_BASE_ADDRESS; - spi->spi_cs.gpio_dev = device_get_binding(ESWIFI0_CS_GPIOS_CONTROLLER); - spi->spi_cs.gpio_pin = ESWIFI0_CS_GPIOS_PIN; + spi->spi_cs.gpio_dev = device_get_binding(DT_ESWIFI0_CS_GPIOS_CONTROLLER); + spi->spi_cs.gpio_pin = DT_ESWIFI0_CS_GPIOS_PIN; spi->spi_cs.delay = 1000; spi->spi_cfg.cs = &spi->spi_cs; diff --git a/ext/lib/mgmt/mcumgr/cmd/img_mgmt/port/zephyr/src/zephyr_img_mgmt.c b/ext/lib/mgmt/mcumgr/cmd/img_mgmt/port/zephyr/src/zephyr_img_mgmt.c index 8693451fea3..84072282b33 100644 --- a/ext/lib/mgmt/mcumgr/cmd/img_mgmt/port/zephyr/src/zephyr_img_mgmt.c +++ b/ext/lib/mgmt/mcumgr/cmd/img_mgmt/port/zephyr/src/zephyr_img_mgmt.c @@ -218,7 +218,7 @@ zephyr_img_mgmt_init(struct device *dev) { ARG_UNUSED(dev); - zephyr_img_mgmt_flash_dev = device_get_binding(FLASH_DEV_NAME); + zephyr_img_mgmt_flash_dev = device_get_binding(DT_FLASH_DEV_NAME); if (zephyr_img_mgmt_flash_dev == NULL) { return -ENODEV; } diff --git a/include/arch/arm/cortex_m/cmsis.h b/include/arch/arm/cortex_m/cmsis.h index 01bfb90b8ee..07d8090e900 100644 --- a/include/arch/arm/cortex_m/cmsis.h +++ b/include/arch/arm/cortex_m/cmsis.h @@ -84,12 +84,12 @@ typedef enum { #ifndef __MPU_PRESENT #define __MPU_PRESENT 0U #endif -#define __NVIC_PRIO_BITS CONFIG_NUM_IRQ_PRIO_BITS +#define __NVIC_PRIO_BITS DT_NUM_IRQ_PRIO_BITS #define __Vendor_SysTickConfig 0 /* Default to standard SysTick */ #endif /* __NVIC_PRIO_BITS */ -#if __NVIC_PRIO_BITS != CONFIG_NUM_IRQ_PRIO_BITS -#error "CONFIG_NUM_IRQ_PRIO_BITS and __NVIC_PRIO_BITS are not set to the same value" +#if __NVIC_PRIO_BITS != DT_NUM_IRQ_PRIO_BITS +#error "DT_NUM_IRQ_PRIO_BITS and __NVIC_PRIO_BITS are not set to the same value" #endif #if defined(CONFIG_CPU_CORTEX_M0) diff --git a/include/arch/arm/cortex_m/exc.h b/include/arch/arm/cortex_m/exc.h index adde516add7..23e4341ca3a 100644 --- a/include/arch/arm/cortex_m/exc.h +++ b/include/arch/arm/cortex_m/exc.h @@ -19,7 +19,7 @@ extern "C" { #endif /* for assembler, only works with constants */ -#define _EXC_PRIO(pri) (((pri) << (8 - CONFIG_NUM_IRQ_PRIO_BITS)) & 0xff) +#define _EXC_PRIO(pri) (((pri) << (8 - DT_NUM_IRQ_PRIO_BITS)) & 0xff) #if defined(CONFIG_CPU_CORTEX_M_HAS_PROGRAMMABLE_FAULT_PRIOS) #define _EXCEPTION_RESERVED_PRIO 1 diff --git a/include/arch/x86/linker.ld b/include/arch/x86/linker.ld index 62b34964487..2bc38a77d3f 100644 --- a/include/arch/x86/linker.ld +++ b/include/arch/x86/linker.ld @@ -156,7 +156,7 @@ SECTIONS /* Kernel ROM extends to the end of flash. Need to do this to program * the MMU */ - _image_rom_end = _image_rom_start + KB(CONFIG_ROM_SIZE); + _image_rom_end = _image_rom_start + KB(DT_ROM_SIZE); #else /* ROM ends here, position counter will now be in RAM areas */ _image_rom_end = .; @@ -358,11 +358,11 @@ SECTIONS __data_ram_end = .; /* All unused memory also owned by the kernel for heaps */ - __kernel_ram_end = PHYS_RAM_ADDR + KB(CONFIG_RAM_SIZE); + __kernel_ram_end = PHYS_RAM_ADDR + KB(DT_RAM_SIZE); __kernel_ram_size = __kernel_ram_end - __kernel_ram_start; _image_ram_end = .; - _image_ram_all = (PHYS_RAM_ADDR + KB(CONFIG_RAM_SIZE)) - _image_ram_start; + _image_ram_all = (PHYS_RAM_ADDR + KB(DT_RAM_SIZE)) - _image_ram_start; _end = .; /* end of image */ diff --git a/lib/libc/newlib/libc-hooks.c b/lib/libc/newlib/libc-hooks.c index 0e72a8a5181..545035bee2a 100644 --- a/lib/libc/newlib/libc-hooks.c +++ b/lib/libc/newlib/libc-hooks.c @@ -25,8 +25,8 @@ static unsigned char __kernel __aligned(CONFIG_NEWLIB_LIBC_ALIGNED_HEAP_SIZE) #else #if CONFIG_X86 -#define USED_RAM_SIZE (USED_RAM_END_ADDR - CONFIG_PHYS_RAM_ADDR) -#define MAX_HEAP_SIZE ((KB(CONFIG_RAM_SIZE)) - USED_RAM_SIZE) +#define USED_RAM_SIZE (USED_RAM_END_ADDR - DT_PHYS_RAM_ADDR) +#define MAX_HEAP_SIZE ((KB(DT_RAM_SIZE)) - USED_RAM_SIZE) #elif CONFIG_NIOS2 #include #define USED_RAM_SIZE (USED_RAM_END_ADDR - _RAM_ADDR) diff --git a/samples/application_development/out_of_tree_board/boards/arm/nrf52840_pca10056/board.h b/samples/application_development/out_of_tree_board/boards/arm/nrf52840_pca10056/board.h index 8ecd5a33423..9419db12ea3 100644 --- a/samples/application_development/out_of_tree_board/boards/arm/nrf52840_pca10056/board.h +++ b/samples/application_development/out_of_tree_board/boards/arm/nrf52840_pca10056/board.h @@ -11,34 +11,34 @@ /* Push button switch 0 */ #define SW0_GPIO_PIN 11 -#define SW0_GPIO_NAME CONFIG_GPIO_P0_DEV_NAME +#define SW0_GPIO_NAME DT_GPIO_P0_DEV_NAME /* Push button switch 1 */ #define SW1_GPIO_PIN 12 -#define SW1_GPIO_NAME CONFIG_GPIO_P0_DEV_NAME +#define SW1_GPIO_NAME DT_GPIO_P0_DEV_NAME /* Push button switch 2 */ #define SW2_GPIO_PIN 24 -#define SW2_GPIO_NAME CONFIG_GPIO_P0_DEV_NAME +#define SW2_GPIO_NAME DT_GPIO_P0_DEV_NAME /* Push button switch 3 */ #define SW3_GPIO_PIN 25 -#define SW3_GPIO_NAME CONFIG_GPIO_P0_DEV_NAME +#define SW3_GPIO_NAME DT_GPIO_P0_DEV_NAME /* Onboard GREEN LED 0 */ #define LED0_GPIO_PIN 13 -#define LED0_GPIO_PORT CONFIG_GPIO_P0_DEV_NAME +#define LED0_GPIO_PORT DT_GPIO_P0_DEV_NAME /* Onboard GREEN LED 1 */ #define LED1_GPIO_PIN 14 -#define LED1_GPIO_PORT CONFIG_GPIO_P0_DEV_NAME +#define LED1_GPIO_PORT DT_GPIO_P0_DEV_NAME /* Onboard GREEN LED 2 */ #define LED2_GPIO_PIN 15 -#define LED2_GPIO_PORT CONFIG_GPIO_P0_DEV_NAME +#define LED2_GPIO_PORT DT_GPIO_P0_DEV_NAME /* Onboard GREEN LED 3 */ #define LED3_GPIO_PIN 16 -#define LED3_GPIO_PORT CONFIG_GPIO_P0_DEV_NAME +#define LED3_GPIO_PORT DT_GPIO_P0_DEV_NAME #endif /* __INC_BOARD_H */ diff --git a/samples/basic/blink_led/src/main.c b/samples/basic/blink_led/src/main.c index c6adf876048..a805558a442 100644 --- a/samples/basic/blink_led/src/main.c +++ b/samples/basic/blink_led/src/main.c @@ -18,10 +18,10 @@ #if defined(CONFIG_SOC_STM32F401XE) || defined(CONFIG_SOC_STM32F412ZG) || \ defined(CONFIG_SOC_STM32F413XX) || defined(CONFIG_SOC_STM32L476XG) || \ defined(CONFIG_SOC_STM32F407XG) || defined(CONFIG_SOC_STM32F302X8) -#define PWM_DRIVER CONFIG_PWM_STM32_2_DEV_NAME +#define PWM_DRIVER DT_PWM_STM32_2_DEV_NAME #define PWM_CHANNEL 1 #elif CONFIG_SOC_STM32F103XB -#define PWM_DRIVER CONFIG_PWM_STM32_1_DEV_NAME +#define PWM_DRIVER DT_PWM_STM32_1_DEV_NAME #define PWM_CHANNEL 1 #elif defined(CONFIG_SOC_QUARK_SE_C1000) || defined(CONFIG_SOC_QUARK_D2000) #define PWM_DRIVER CONFIG_PWM_QMSI_DEV_NAME diff --git a/samples/basic/fade_led/src/main.c b/samples/basic/fade_led/src/main.c index 141253b571e..96087a28b23 100644 --- a/samples/basic/fade_led/src/main.c +++ b/samples/basic/fade_led/src/main.c @@ -16,10 +16,10 @@ #include #if defined(CONFIG_SOC_STM32F401XE) || defined(CONFIG_SOC_STM32L476XG) -#define PWM_DRIVER CONFIG_PWM_STM32_2_DEV_NAME +#define PWM_DRIVER DT_PWM_STM32_2_DEV_NAME #define PWM_CHANNEL 1 #elif CONFIG_SOC_STM32F103XB -#define PWM_DRIVER CONFIG_PWM_STM32_1_DEV_NAME +#define PWM_DRIVER DT_PWM_STM32_1_DEV_NAME #define PWM_CHANNEL 1 #elif defined(CONFIG_SOC_QUARK_SE_C1000) || defined(CONFIG_SOC_QUARK_D2000) #define PWM_DRIVER CONFIG_PWM_QMSI_DEV_NAME diff --git a/samples/bluetooth/mesh_demo/src/microbit.c b/samples/bluetooth/mesh_demo/src/microbit.c index 4cc71edc6ab..509f46a0885 100644 --- a/samples/bluetooth/mesh_demo/src/microbit.c +++ b/samples/bluetooth/mesh_demo/src/microbit.c @@ -248,7 +248,7 @@ void board_init(u16_t *addr) { struct mb_display *disp = mb_display_get(); - nvm = device_get_binding(FLASH_DEV_NAME); + nvm = device_get_binding(DT_FLASH_DEV_NAME); pwm = device_get_binding(CONFIG_PWM_NRF5_SW_0_DEV_NAME); *addr = NRF_UICR->CUSTOMER[0]; diff --git a/samples/boards/96b_argonkey/src/main.c b/samples/boards/96b_argonkey/src/main.c index 7cb2701ea60..677bd9ec4ee 100644 --- a/samples/boards/96b_argonkey/src/main.c +++ b/samples/boards/96b_argonkey/src/main.c @@ -149,31 +149,31 @@ void main(void) printk("ArgonKey test!!\n"); #ifdef CONFIG_LPS22HB - struct device *baro_dev = device_get_binding(CONFIG_LPS22HB_DEV_NAME); + struct device *baro_dev = device_get_binding(DT_LPS22HB_DEV_NAME); if (!baro_dev) { printk("Could not get pointer to %s sensor\n", - CONFIG_LPS22HB_DEV_NAME); + DT_LPS22HB_DEV_NAME); return; } #endif #ifdef CONFIG_HTS221 - struct device *hum_dev = device_get_binding(CONFIG_HTS221_NAME); + struct device *hum_dev = device_get_binding(DT_HTS221_NAME); if (!hum_dev) { printk("Could not get pointer to %s sensor\n", - CONFIG_HTS221_NAME); + DT_HTS221_NAME); return; } #endif #ifdef CONFIG_LSM6DSL - struct device *accel_dev = device_get_binding(CONFIG_LSM6DSL_DEV_NAME); + struct device *accel_dev = device_get_binding(DT_LSM6DSL_DEV_NAME); if (!accel_dev) { printk("Could not get pointer to %s sensor\n", - CONFIG_LSM6DSL_DEV_NAME); + DT_LSM6DSL_DEV_NAME); return; } @@ -234,11 +234,11 @@ void main(void) #endif #ifdef CONFIG_VL53L0X - struct device *tof_dev = device_get_binding(CONFIG_VL53L0X_NAME); + struct device *tof_dev = device_get_binding(DT_VL53L0X_NAME); if (!tof_dev) { printk("Could not get pointer to %s sensor\n", - CONFIG_VL53L0X_NAME); + DT_VL53L0X_NAME); return; } #endif diff --git a/samples/boards/arduino_101/environmental_sensing/sensor/dts_fixup.h b/samples/boards/arduino_101/environmental_sensing/sensor/dts_fixup.h index 9ced47753df..b09c36e7a61 100644 --- a/samples/boards/arduino_101/environmental_sensing/sensor/dts_fixup.h +++ b/samples/boards/arduino_101/environmental_sensing/sensor/dts_fixup.h @@ -6,15 +6,15 @@ #if defined(CONFIG_HAS_DTS_I2C) -#define CONFIG_HDC1008_NAME DT_INTEL_QMSI_SS_I2C_80012000_TI_HDC1008_40_LABEL -#define CONFIG_HDC1008_I2C_MASTER_DEV_NAME DT_INTEL_QMSI_SS_I2C_80012000_TI_HDC1008_40_BUS_NAME -#define CONFIG_HDC1008_I2C_ADDR DT_INTEL_QMSI_SS_I2C_80012000_TI_HDC1008_40_BASE_ADDRESS +#define DT_HDC1008_NAME DT_INTEL_QMSI_SS_I2C_80012000_TI_HDC1008_40_LABEL +#define DT_HDC1008_I2C_MASTER_DEV_NAME DT_INTEL_QMSI_SS_I2C_80012000_TI_HDC1008_40_BUS_NAME +#define DT_HDC1008_I2C_ADDR DT_INTEL_QMSI_SS_I2C_80012000_TI_HDC1008_40_BASE_ADDRESS #endif /* CONFIG_HAS_DTS_I2C */ #if defined(CONFIG_HAS_DTS_GPIO) -#define CONFIG_HDC1008_GPIO_DEV_NAME DT_INTEL_QMSI_SS_I2C_80012000_TI_HDC1008_40_DRDY_GPIOS_CONTROLLER -#define CONFIG_HDC1008_GPIO_PIN_NUM DT_INTEL_QMSI_SS_I2C_80012000_TI_HDC1008_40_DRDY_GPIOS_PIN +#define DT_HDC1008_GPIO_DEV_NAME DT_INTEL_QMSI_SS_I2C_80012000_TI_HDC1008_40_DRDY_GPIOS_CONTROLLER +#define DT_HDC1008_GPIO_PIN_NUM DT_INTEL_QMSI_SS_I2C_80012000_TI_HDC1008_40_DRDY_GPIOS_PIN #endif /* CONFIG_HAS_DTS_GPIO */ diff --git a/samples/boards/reel_board/mesh_badge/src/periphs.c b/samples/boards/reel_board/mesh_badge/src/periphs.c index a6a8d753c37..7024be6a204 100644 --- a/samples/boards/reel_board/mesh_badge/src/periphs.c +++ b/samples/boards/reel_board/mesh_badge/src/periphs.c @@ -29,10 +29,10 @@ static struct led_device_info led_dev_info[] = { static struct device_info dev_info[] = { {NULL, SW0_GPIO_CONTROLLER}, - {NULL, CONFIG_HDC1008_NAME}, - {NULL, CONFIG_FXOS8700_NAME}, - {NULL, CONFIG_APDS9960_DRV_NAME}, - {NULL, CONFIG_SSD1673_DEV_NAME}, + {NULL, DT_HDC1008_NAME}, + {NULL, DT_FXOS8700_NAME}, + {NULL, DT_APDS9960_DRV_NAME}, + {NULL, DT_SSD1673_DEV_NAME}, }; static void configure_gpios(void) diff --git a/samples/boards/reel_board/mesh_badge/src/reel_board.c b/samples/boards/reel_board/mesh_badge/src/reel_board.c index 0debd172739..e92ed8bb574 100644 --- a/samples/boards/reel_board/mesh_badge/src/reel_board.c +++ b/samples/boards/reel_board/mesh_badge/src/reel_board.c @@ -555,7 +555,7 @@ static int erase_storage(void) { struct device *dev; - dev = device_get_binding(FLASH_DEV_NAME); + dev = device_get_binding(DT_FLASH_DEV_NAME); return flash_erase(dev, FLASH_AREA_STORAGE_OFFSET, FLASH_AREA_STORAGE_SIZE); @@ -568,7 +568,7 @@ void board_refresh_display(void) int board_init(void) { - epd_dev = device_get_binding(CONFIG_SSD1673_DEV_NAME); + epd_dev = device_get_binding(DT_SSD1673_DEV_NAME); if (epd_dev == NULL) { printk("SSD1673 device not found\n"); return -ENODEV; diff --git a/samples/boards/up_squared/gpio_counter/src/main.c b/samples/boards/up_squared/gpio_counter/src/main.c index 9b047f3c8a9..6b36e3688e5 100644 --- a/samples/boards/up_squared/gpio_counter/src/main.c +++ b/samples/boards/up_squared/gpio_counter/src/main.c @@ -63,7 +63,7 @@ K_SEM_DEFINE(counter_sem, 0, 1); #define NUM_PINS ARRAY_SIZE(counter_pins) #define MASK (BIT(NUM_PINS) - 1) -#define GPIO_DEV CONFIG_APL_GPIO_LABEL +#define GPIO_DEV DT_APL_GPIO_LABEL void button_cb(struct device *gpiodev, struct gpio_callback *cb, u32_t pin) { diff --git a/samples/display/cfb/dts_fixup.h b/samples/display/cfb/dts_fixup.h index c56712a8a06..7e0801c8490 100644 --- a/samples/display/cfb/dts_fixup.h +++ b/samples/display/cfb/dts_fixup.h @@ -1,15 +1,15 @@ #if defined(CONFIG_HAS_DTS_I2C) && defined(CONFIG_SSD1306) -#define CONFIG_SSD1306_I2C_ADDR DT_NXP_KINETIS_I2C_40066000_SOLOMON_SSD1306FB_I2C_3C_BASE_ADDRESS -#define CONFIG_SSD1306_I2C_MASTER_DEV_NAME DT_NXP_KINETIS_I2C_40066000_SOLOMON_SSD1306FB_I2C_3C_BUS_NAME -#define CONFIG_SSD1306_DEV_NAME DT_NXP_KINETIS_I2C_40066000_SOLOMON_SSD1306FB_I2C_3C_LABEL -#define CONFIG_SSD1306_PANEL_COM_INVDIR DT_NXP_KINETIS_I2C_40066000_SOLOMON_SSD1306FB_I2C_3C_COM_INVDIR -#define SSD1306_PANEL_DISPLAY_OFFSET DT_NXP_KINETIS_I2C_40066000_SOLOMON_SSD1306FB_I2C_3C_DISPLAY_OFFSET -#define SSD1306_PANEL_HEIGHT DT_NXP_KINETIS_I2C_40066000_SOLOMON_SSD1306FB_I2C_3C_HEIGHT -#define SSD1306_PANEL_PAGE_OFFSET DT_NXP_KINETIS_I2C_40066000_SOLOMON_SSD1306FB_I2C_3C_PAGE_OFFSET -#define SSD1306_PANEL_PRECHARGE_PERIOD DT_NXP_KINETIS_I2C_40066000_SOLOMON_SSD1306FB_I2C_3C_PRECHARGEP -#define SSD1306_PANEL_FIRST_SEG DT_NXP_KINETIS_I2C_40066000_SOLOMON_SSD1306FB_I2C_3C_SEGMENT_OFFSET -#define CONFIG_SSD1306_PANEL_SEGMENT_REMAP DT_NXP_KINETIS_I2C_40066000_SOLOMON_SSD1306FB_I2C_3C_SEGMENT_REMAP -#define SSD1306_PANEL_WIDTH DT_NXP_KINETIS_I2C_40066000_SOLOMON_SSD1306FB_I2C_3C_WIDTH +#define DT_SSD1306_I2C_ADDR DT_NXP_KINETIS_I2C_40066000_SOLOMON_SSD1306FB_I2C_3C_BASE_ADDRESS +#define DT_SSD1306_I2C_MASTER_DEV_NAME DT_NXP_KINETIS_I2C_40066000_SOLOMON_SSD1306FB_I2C_3C_BUS_NAME +#define DT_SSD1306_DEV_NAME DT_NXP_KINETIS_I2C_40066000_SOLOMON_SSD1306FB_I2C_3C_LABEL +#define DT_SSD1306_PANEL_COM_INVDIR DT_NXP_KINETIS_I2C_40066000_SOLOMON_SSD1306FB_I2C_3C_COM_INVDIR +#define DT_SSD1306_PANEL_DISPLAY_OFFSET DT_NXP_KINETIS_I2C_40066000_SOLOMON_SSD1306FB_I2C_3C_DISPLAY_OFFSET +#define DT_SSD1306_PANEL_HEIGHT DT_NXP_KINETIS_I2C_40066000_SOLOMON_SSD1306FB_I2C_3C_HEIGHT +#define DT_SSD1306_PANEL_PAGE_OFFSET DT_NXP_KINETIS_I2C_40066000_SOLOMON_SSD1306FB_I2C_3C_PAGE_OFFSET +#define DT_SSD1306_PANEL_PRECHARGE_PERIOD DT_NXP_KINETIS_I2C_40066000_SOLOMON_SSD1306FB_I2C_3C_PRECHARGEP +#define DT_SSD1306_PANEL_FIRST_SEG DT_NXP_KINETIS_I2C_40066000_SOLOMON_SSD1306FB_I2C_3C_SEGMENT_OFFSET +#define DT_SSD1306_PANEL_SEGMENT_REMAP DT_NXP_KINETIS_I2C_40066000_SOLOMON_SSD1306FB_I2C_3C_SEGMENT_REMAP +#define DT_SSD1306_PANEL_WIDTH DT_NXP_KINETIS_I2C_40066000_SOLOMON_SSD1306FB_I2C_3C_WIDTH #endif diff --git a/samples/display/ili9340/dts_fixup.h b/samples/display/ili9340/dts_fixup.h index b7d1e217317..dd404ade37e 100644 --- a/samples/display/ili9340/dts_fixup.h +++ b/samples/display/ili9340/dts_fixup.h @@ -6,28 +6,28 @@ #if defined(CONFIG_SPI_STM32) && defined(CONFIG_ILI9340) -#define CONFIG_ILI9340_SPI_DEV_NAME \ +#define DT_ILI9340_SPI_DEV_NAME \ DT_ST_STM32_SPI_FIFO_40013000_ILITEK_ILI9340_0_BUS_NAME -#define CONFIG_ILI9340_SPI_SLAVE_NUMBER \ +#define DT_ILI9340_SPI_SLAVE_NUMBER \ DT_ST_STM32_SPI_FIFO_40013000_ILITEK_ILI9340_0_BASE_ADDRESS -#define CONFIG_ILI9340_CMD_DATA_GPIO_PORT_NAME \ +#define DT_ILI9340_CMD_DATA_GPIO_PORT_NAME \ DT_ST_STM32_SPI_FIFO_40013000_ILITEK_ILI9340_0_CMD_DATA_GPIOS_CONTROLLER -#define CONFIG_ILI9340_CMD_DATA_PIN \ +#define DT_ILI9340_CMD_DATA_PIN \ DT_ST_STM32_SPI_FIFO_40013000_ILITEK_ILI9340_0_CMD_DATA_GPIOS_PIN -#define CONFIG_ILI9340_DEV_NAME \ +#define DT_ILI9340_DEV_NAME \ DT_ST_STM32_SPI_FIFO_40013000_ILITEK_ILI9340_0_LABEL -#define CONFIG_ILI9340_RESET_GPIO_PORT_NAME \ +#define DT_ILI9340_RESET_GPIO_PORT_NAME \ DT_ST_STM32_SPI_FIFO_40013000_ILITEK_ILI9340_0_RESET_GPIOS_CONTROLLER -#define CONFIG_ILI9340_RESET_PIN \ +#define DT_ILI9340_RESET_PIN \ DT_ST_STM32_SPI_FIFO_40013000_ILITEK_ILI9340_0_RESET_GPIOS_PIN -#define CONFIG_ILI9340_SPI_FREQ \ +#define DT_ILI9340_SPI_FREQ \ DT_ST_STM32_SPI_FIFO_40013000_ILITEK_ILI9340_0_SPI_MAX_FREQUENCY #endif diff --git a/samples/drivers/flash_shell/src/main.c b/samples/drivers/flash_shell/src/main.c index dc7fbf4958f..d66eda98447 100644 --- a/samples/drivers/flash_shell/src/main.c +++ b/samples/drivers/flash_shell/src/main.c @@ -28,11 +28,11 @@ LOG_MODULE_REGISTER(app); #define PR_WARNING(shell, fmt, ...) \ shell_fprintf(shell, SHELL_WARNING, fmt, ##__VA_ARGS__) /* - * When FLASH_DEV_NAME is available, we use it here. Otherwise, + * When DT_FLASH_DEV_NAME is available, we use it here. Otherwise, * the device can be set at runtime with the set_device command. */ -#ifndef FLASH_DEV_NAME -#define FLASH_DEV_NAME "" +#ifndef DT_FLASH_DEV_NAME +#define DT_FLASH_DEV_NAME "" #endif /* Command usage info. */ @@ -627,9 +627,9 @@ static int cmd_set_dev(const struct shell *shell, size_t argc, char **argv) void main(void) { - flash_device = device_get_binding(FLASH_DEV_NAME); + flash_device = device_get_binding(DT_FLASH_DEV_NAME); if (flash_device) { - printk("Found flash device %s.\n", FLASH_DEV_NAME); + printk("Found flash device %s.\n", DT_FLASH_DEV_NAME); printk("Flash I/O commands can be run.\n"); } else { printk("**No flash device found!**\n"); diff --git a/samples/drivers/gpio/src/main.c b/samples/drivers/gpio/src/main.c index 525a00dc3a1..a744ab7e4a9 100644 --- a/samples/drivers/gpio/src/main.c +++ b/samples/drivers/gpio/src/main.c @@ -161,9 +161,9 @@ #if defined(CONFIG_GPIO_DW_0) #define GPIO_DRV_NAME CONFIG_GPIO_DW_0_NAME #elif defined(CONFIG_GPIO_QMSI_0) && defined(CONFIG_SOC_QUARK_SE_C1000) -#define GPIO_DRV_NAME CONFIG_GPIO_QMSI_0_NAME +#define GPIO_DRV_NAME DT_GPIO_QMSI_0_NAME #elif defined(CONFIG_GPIO_QMSI_SS_0) -#define GPIO_DRV_NAME CONFIG_GPIO_QMSI_SS_0_NAME +#define GPIO_DRV_NAME DT_GPIO_QMSI_SS_0_NAME #elif defined(CONFIG_GPIO_ATMEL_SAM3) #define GPIO_DRV_NAME CONFIG_GPIO_ATMEL_SAM3_PORTB_DEV_NAME #elif defined(CONFIG_GPIO_ESP32) diff --git a/samples/drivers/i2c_fujitsu_fram/src/main.c b/samples/drivers/i2c_fujitsu_fram/src/main.c index d9695151160..8cf5ba8a245 100644 --- a/samples/drivers/i2c_fujitsu_fram/src/main.c +++ b/samples/drivers/i2c_fujitsu_fram/src/main.c @@ -11,7 +11,7 @@ #include #if defined(CONFIG_SOC_QUARK_SE_C1000_SS) -#define I2C_DEV CONFIG_I2C_SS_0_NAME +#define I2C_DEV DT_I2C_SS_0_NAME #else #define I2C_DEV CONFIG_I2C_0_NAME #endif diff --git a/samples/drivers/led_apa102c/src/main.c b/samples/drivers/led_apa102c/src/main.c index 7171da8031f..85157206d34 100644 --- a/samples/drivers/led_apa102c/src/main.c +++ b/samples/drivers/led_apa102c/src/main.c @@ -35,7 +35,7 @@ #define GPIO_CLK_PIN 19 #define GPIO_NAME "GPIO_" -#define GPIO_DRV_NAME CONFIG_GPIO_QMSI_0_NAME +#define GPIO_DRV_NAME DT_GPIO_QMSI_0_NAME #define APA102C_START_FRAME 0x00000000 #define APA102C_END_FRAME 0xFFFFFFFF diff --git a/samples/drivers/soc_flash_nrf/src/main.c b/samples/drivers/soc_flash_nrf/src/main.c index ebc4a117002..f59aaed8351 100644 --- a/samples/drivers/soc_flash_nrf/src/main.c +++ b/samples/drivers/soc_flash_nrf/src/main.c @@ -38,7 +38,7 @@ void main(void) printf("\nNordic nRF5 Flash Testing\n"); printf("=========================\n"); - flash_dev = device_get_binding(FLASH_DEV_NAME); + flash_dev = device_get_binding(DT_FLASH_DEV_NAME); if (!flash_dev) { printf("Nordic nRF5 flash driver was not found!\n"); diff --git a/samples/mpu/mpu_test/src/main.c b/samples/mpu/mpu_test/src/main.c index 8eddfda57a2..0787756298f 100644 --- a/samples/mpu/mpu_test/src/main.c +++ b/samples/mpu/mpu_test/src/main.c @@ -60,7 +60,7 @@ static int cmd_write_mcux(const struct shell *shell, size_t argc, char *argv[]) return 0; } - flash_dev = device_get_binding(FLASH_DEV_NAME); + flash_dev = device_get_binding(DT_FLASH_DEV_NAME); /* 128K reserved to the application */ offset = FLASH_MEM + 0x20000; @@ -95,7 +95,7 @@ static int cmd_write_stm32(const struct shell *shell, size_t argc, char *argv[]) return 0; } - flash_dev = device_get_binding(FLASH_DEV_NAME); + flash_dev = device_get_binding(DT_FLASH_DEV_NAME); /* 16K reserved to the application */ u32_t offset = FLASH_MEM + 0x4000; diff --git a/samples/net/lwm2m_client/dts_fixup.h b/samples/net/lwm2m_client/dts_fixup.h index 9d2314495a2..f1d35ca4e44 100644 --- a/samples/net/lwm2m_client/dts_fixup.h +++ b/samples/net/lwm2m_client/dts_fixup.h @@ -5,19 +5,19 @@ */ #ifdef CONFIG_BOARD_FRDM_K64F -#define CONFIG_WNCM14A2A_UART_DRV_NAME DT_NXP_KINETIS_UART_4006C000_WNCM14A2A_BUS_NAME -#define CONFIG_WNCM14A2A_GPIO_MDM_BOOT_MODE_SEL_NAME DT_NXP_KINETIS_UART_4006C000_WNCM14A2A_MDM_BOOT_MODE_SEL_GPIOS_CONTROLLER -#define CONFIG_WNCM14A2A_GPIO_MDM_BOOT_MODE_SEL_PIN DT_NXP_KINETIS_UART_4006C000_WNCM14A2A_MDM_BOOT_MODE_SEL_GPIOS_PIN -#define CONFIG_WNCM14A2A_GPIO_MDM_POWER_NAME DT_NXP_KINETIS_UART_4006C000_WNCM14A2A_MDM_POWER_GPIOS_CONTROLLER -#define CONFIG_WNCM14A2A_GPIO_MDM_POWER_PIN DT_NXP_KINETIS_UART_4006C000_WNCM14A2A_MDM_POWER_GPIOS_PIN -#define CONFIG_WNCM14A2A_GPIO_MDM_KEEP_AWAKE_NAME DT_NXP_KINETIS_UART_4006C000_WNCM14A2A_MDM_KEEP_AWAKE_GPIOS_CONTROLLER -#define CONFIG_WNCM14A2A_GPIO_MDM_KEEP_AWAKE_PIN DT_NXP_KINETIS_UART_4006C000_WNCM14A2A_MDM_KEEP_AWAKE_GPIOS_PIN -#define CONFIG_WNCM14A2A_GPIO_MDM_RESET_NAME DT_NXP_KINETIS_UART_4006C000_WNCM14A2A_MDM_RESET_GPIOS_CONTROLLER -#define CONFIG_WNCM14A2A_GPIO_MDM_RESET_PIN DT_NXP_KINETIS_UART_4006C000_WNCM14A2A_MDM_RESET_GPIOS_PIN -#define CONFIG_WNCM14A2A_GPIO_MDM_SHLD_TRANS_ENA_NAME DT_NXP_KINETIS_UART_4006C000_WNCM14A2A_MDM_SHLD_TRANS_ENA_GPIOS_CONTROLLER -#define CONFIG_WNCM14A2A_GPIO_MDM_SHLD_TRANS_ENA_PIN DT_NXP_KINETIS_UART_4006C000_WNCM14A2A_MDM_SHLD_TRANS_ENA_GPIOS_PIN +#define DT_WNCM14A2A_UART_DRV_NAME DT_NXP_KINETIS_UART_4006C000_WNCM14A2A_BUS_NAME +#define DT_WNCM14A2A_GPIO_MDM_BOOT_MODE_SEL_NAME DT_NXP_KINETIS_UART_4006C000_WNCM14A2A_MDM_BOOT_MODE_SEL_GPIOS_CONTROLLER +#define DT_WNCM14A2A_GPIO_MDM_BOOT_MODE_SEL_PIN DT_NXP_KINETIS_UART_4006C000_WNCM14A2A_MDM_BOOT_MODE_SEL_GPIOS_PIN +#define DT_WNCM14A2A_GPIO_MDM_POWER_NAME DT_NXP_KINETIS_UART_4006C000_WNCM14A2A_MDM_POWER_GPIOS_CONTROLLER +#define DT_WNCM14A2A_GPIO_MDM_POWER_PIN DT_NXP_KINETIS_UART_4006C000_WNCM14A2A_MDM_POWER_GPIOS_PIN +#define DT_WNCM14A2A_GPIO_MDM_KEEP_AWAKE_NAME DT_NXP_KINETIS_UART_4006C000_WNCM14A2A_MDM_KEEP_AWAKE_GPIOS_CONTROLLER +#define DT_WNCM14A2A_GPIO_MDM_KEEP_AWAKE_PIN DT_NXP_KINETIS_UART_4006C000_WNCM14A2A_MDM_KEEP_AWAKE_GPIOS_PIN +#define DT_WNCM14A2A_GPIO_MDM_RESET_NAME DT_NXP_KINETIS_UART_4006C000_WNCM14A2A_MDM_RESET_GPIOS_CONTROLLER +#define DT_WNCM14A2A_GPIO_MDM_RESET_PIN DT_NXP_KINETIS_UART_4006C000_WNCM14A2A_MDM_RESET_GPIOS_PIN +#define DT_WNCM14A2A_GPIO_MDM_SHLD_TRANS_ENA_NAME DT_NXP_KINETIS_UART_4006C000_WNCM14A2A_MDM_SHLD_TRANS_ENA_GPIOS_CONTROLLER +#define DT_WNCM14A2A_GPIO_MDM_SHLD_TRANS_ENA_PIN DT_NXP_KINETIS_UART_4006C000_WNCM14A2A_MDM_SHLD_TRANS_ENA_GPIOS_PIN #ifdef DT_NXP_KINETIS_UART_4006C000_WNCM14A2A_MDM_SEND_OK_GPIOS_PIN -#define CONFIG_WNCM14A2A_GPIO_MDM_SEND_OK_NAME DT_NXP_KINETIS_UART_4006C000_WNCM14A2A_MDM_SEND_OK_GPIOS_CONTROLLER -#define CONFIG_WNCM14A2A_GPIO_MDM_SEND_OK_PIN DT_NXP_KINETIS_UART_4006C000_WNCM14A2A_MDM_SEND_OK_GPIOS_PIN +#define DT_WNCM14A2A_GPIO_MDM_SEND_OK_NAME DT_NXP_KINETIS_UART_4006C000_WNCM14A2A_MDM_SEND_OK_GPIOS_CONTROLLER +#define DT_WNCM14A2A_GPIO_MDM_SEND_OK_PIN DT_NXP_KINETIS_UART_4006C000_WNCM14A2A_MDM_SEND_OK_GPIOS_PIN #endif #endif diff --git a/samples/sensor/adt7420/dts_fixup.h b/samples/sensor/adt7420/dts_fixup.h index 4b6b94f5ff6..bbbe3fd1d73 100644 --- a/samples/sensor/adt7420/dts_fixup.h +++ b/samples/sensor/adt7420/dts_fixup.h @@ -1,9 +1,9 @@ #if defined(CONFIG_HAS_DTS_I2C) -#ifndef CONFIG_ADT7420_NAME -#define CONFIG_ADT7420_NAME "" -#define CONFIG_ADT7420_I2C_ADDR 0 -#define CONFIG_ADT7420_I2C_MASTER_DEV_NAME "" +#ifndef DT_ADT7420_NAME +#define DT_ADT7420_NAME "" +#define DT_ADT7420_I2C_ADDR 0 +#define DT_ADT7420_I2C_MASTER_DEV_NAME "" #endif #endif /* CONFIG_HAS_DTS_I2C */ diff --git a/samples/sensor/adt7420/src/main.c b/samples/sensor/adt7420/src/main.c index 064548b6f6a..920938e1de5 100644 --- a/samples/sensor/adt7420/src/main.c +++ b/samples/sensor/adt7420/src/main.c @@ -91,7 +91,7 @@ static void process(struct device *dev) void main(void) { - struct device *dev = device_get_binding(CONFIG_ADT7420_NAME); + struct device *dev = device_get_binding(DT_ADT7420_NAME); __ASSERT(dev != NULL, "Failed to get device binding"); printf("device is %p, name is %s\n", dev, dev->config->name); diff --git a/samples/sensor/adxl372/dts_fixup.h b/samples/sensor/adxl372/dts_fixup.h index e1b7749c5a8..82b43986c62 100644 --- a/samples/sensor/adxl372/dts_fixup.h +++ b/samples/sensor/adxl372/dts_fixup.h @@ -1,24 +1,24 @@ #if defined(CONFIG_HAS_DTS_I2C) -#ifndef CONFIG_ADXL372_DEV_NAME -#define CONFIG_ADXL372_DEV_NAME "" +#ifndef DT_ADXL372_DEV_NAME +#define DT_ADXL372_DEV_NAME "" #endif -#ifndef CONFIG_ADXL372_I2C_ADDR -#define CONFIG_ADXL372_I2C_ADDR 0 -#define CONFIG_ADXL372_I2C_MASTER_DEV_NAME "" +#ifndef DT_ADXL372_I2C_ADDR +#define DT_ADXL372_I2C_ADDR 0 +#define DT_ADXL372_I2C_MASTER_DEV_NAME "" #endif #endif /* CONFIG_HAS_DTS_I2C */ #if defined(CONFIG_HAS_DTS_SPI) -#ifndef CONFIG_ADXL372_DEV_NAME -#define CONFIG_ADXL372_DEV_NAME "" +#ifndef DT_ADXL372_DEV_NAME +#define DT_ADXL372_DEV_NAME "" #endif -#ifndef CONFIG_ADXL372_SPI_DEV_NAME -#define CONFIG_ADXL372_SPI_DEV_NAME "" -#define CONFIG_ADXL372_SPI_DEV_SLAVE 0 -#define CONFIG_ADXL372_SPI_BUS_FREQ 8000000 +#ifndef DT_ADXL372_SPI_DEV_NAME +#define DT_ADXL372_SPI_DEV_NAME "" +#define DT_ADXL372_SPI_DEV_SLAVE 0 +#define DT_ADXL372_SPI_BUS_FREQ 8000000 #endif #endif /* CONFIG_HAS_DTS_SPI */ diff --git a/samples/sensor/adxl372/src/main.c b/samples/sensor/adxl372/src/main.c index 512900ac60f..bbeaaaba66c 100644 --- a/samples/sensor/adxl372/src/main.c +++ b/samples/sensor/adxl372/src/main.c @@ -47,10 +47,10 @@ void main(void) int i; char meter[200]; - struct device *dev = device_get_binding(CONFIG_ADXL372_DEV_NAME); + struct device *dev = device_get_binding(DT_ADXL372_DEV_NAME); if (dev == NULL) { - printf("Could not get %s device\n", CONFIG_ADXL372_DEV_NAME); + printf("Could not get %s device\n", DT_ADXL372_DEV_NAME); return; } diff --git a/samples/sensor/apds9960/src/main.c b/samples/sensor/apds9960/src/main.c index 964cb231c37..7c268554009 100644 --- a/samples/sensor/apds9960/src/main.c +++ b/samples/sensor/apds9960/src/main.c @@ -29,7 +29,7 @@ void main(void) struct sensor_value intensity, pdata; printk("APDS9960 sample application\n"); - dev = device_get_binding(CONFIG_APDS9960_DRV_NAME); + dev = device_get_binding(DT_APDS9960_DRV_NAME); if (!dev) { printk("sensor: device not found.\n"); return; diff --git a/samples/sensor/bmi160/src/bmi160.c b/samples/sensor/bmi160/src/bmi160.c index e2da352b252..165043606ca 100644 --- a/samples/sensor/bmi160/src/bmi160.c +++ b/samples/sensor/bmi160/src/bmi160.c @@ -417,7 +417,7 @@ void main(void) #endif printk("IMU: Binding...\n"); - bmi160 = device_get_binding(CONFIG_BMI160_NAME); + bmi160 = device_get_binding(DT_BMI160_NAME); if (!bmi160) { printk("Gyro: Device not found.\n"); return; diff --git a/samples/sensor/ccs811/dts_fixup.h b/samples/sensor/ccs811/dts_fixup.h index 5a57e4a128b..b600f4898de 100644 --- a/samples/sensor/ccs811/dts_fixup.h +++ b/samples/sensor/ccs811/dts_fixup.h @@ -1,9 +1,9 @@ #if defined(CONFIG_HAS_DTS_I2C) -#ifndef CONFIG_CCS811_NAME -#define CONFIG_CCS811_NAME "" -#define CONFIG_CCS811_I2C_ADDR 0 -#define CONFIG_CCS811_I2C_MASTER_DEV_NAME "" +#ifndef DT_CCS811_NAME +#define DT_CCS811_NAME "" +#define DT_CCS811_I2C_ADDR 0 +#define DT_CCS811_I2C_MASTER_DEV_NAME "" #endif #endif /* CONFIG_HAS_DTS_I2C */ diff --git a/samples/sensor/fxas21002/src/main.c b/samples/sensor/fxas21002/src/main.c index d22f9c105bb..377606614ea 100644 --- a/samples/sensor/fxas21002/src/main.c +++ b/samples/sensor/fxas21002/src/main.c @@ -18,7 +18,7 @@ static void trigger_handler(struct device *dev, struct sensor_trigger *trigger) void main(void) { struct sensor_value gyro[3]; - struct device *dev = device_get_binding(CONFIG_FXAS21002_NAME); + struct device *dev = device_get_binding(DT_FXAS21002_NAME); if (dev == NULL) { printf("Could not get fxas21002 device\n"); diff --git a/samples/sensor/fxos8700/src/main.c b/samples/sensor/fxos8700/src/main.c index 238df02741c..e57a3a28b62 100644 --- a/samples/sensor/fxos8700/src/main.c +++ b/samples/sensor/fxos8700/src/main.c @@ -29,7 +29,7 @@ static void trigger_handler(struct device *dev, struct sensor_trigger *trigger) void main(void) { struct sensor_value accel[3]; - struct device *dev = device_get_binding(CONFIG_FXOS8700_NAME); + struct device *dev = device_get_binding(DT_FXOS8700_NAME); if (dev == NULL) { printf("Could not get fxos8700 device\n"); diff --git a/samples/sensor/lsm303dlhc/src/main.c b/samples/sensor/lsm303dlhc/src/main.c index a8e0e6993e6..2aeeb4d10a7 100644 --- a/samples/sensor/lsm303dlhc/src/main.c +++ b/samples/sensor/lsm303dlhc/src/main.c @@ -38,19 +38,19 @@ end: void main(void) { struct device *accelerometer = device_get_binding( - CONFIG_LSM303DLHC_ACCEL_NAME); + DT_LSM303DLHC_ACCEL_NAME); struct device *magnetometer = device_get_binding( - CONFIG_LSM303DLHC_MAGN_NAME); + DT_LSM303DLHC_MAGN_NAME); if (accelerometer == NULL) { printf("Could not get %s device\n", - CONFIG_LSM303DLHC_ACCEL_NAME); + DT_LSM303DLHC_ACCEL_NAME); return; } if (magnetometer == NULL) { printf("Could not get %s device\n", - CONFIG_LSM303DLHC_MAGN_NAME); + DT_LSM303DLHC_MAGN_NAME); return; } diff --git a/samples/sensor/max30101/src/main.c b/samples/sensor/max30101/src/main.c index c65d6cf8fcb..013e2260bd4 100644 --- a/samples/sensor/max30101/src/main.c +++ b/samples/sensor/max30101/src/main.c @@ -11,7 +11,7 @@ void main(void) { struct sensor_value green; - struct device *dev = device_get_binding(CONFIG_MAX30101_NAME); + struct device *dev = device_get_binding(DT_MAX30101_NAME); if (dev == NULL) { printf("Could not get max30101 device\n"); diff --git a/samples/sensor/ms5837/dts_fixup.h b/samples/sensor/ms5837/dts_fixup.h index ee5a890c5d8..d10bdfb79a3 100644 --- a/samples/sensor/ms5837/dts_fixup.h +++ b/samples/sensor/ms5837/dts_fixup.h @@ -8,19 +8,19 @@ #ifdef CONFIG_I2C_NRFX -#ifndef CONFIG_MS5837_DEV_NAME +#ifndef DT_MS5837_DEV_NAME -#define CONFIG_MS5837_DEV_NAME \ +#define DT_MS5837_DEV_NAME \ DT_NORDIC_NRF_I2C_40004000_MEAS_MS5837_76_LABEL -#define CONFIG_MS5837_I2C_MASTER_DEV_NAME \ +#define DT_MS5837_I2C_MASTER_DEV_NAME \ DT_NORDIC_NRF_I2C_40004000_MEAS_MS5837_76_BUS_NAME #endif #else -#ifndef CONFIG_MS5837_DEV_NAME -#define CONFIG_MS5837_DEV_NAME "" -#define CONFIG_MS5837_I2C_MASTER_DEV_NAME "" +#ifndef DT_MS5837_DEV_NAME +#define DT_MS5837_DEV_NAME "" +#define DT_MS5837_I2C_MASTER_DEV_NAME "" #endif #endif diff --git a/samples/sensor/ms5837/src/main.c b/samples/sensor/ms5837/src/main.c index 74715a1fa80..b2193bf74fa 100644 --- a/samples/sensor/ms5837/src/main.c +++ b/samples/sensor/ms5837/src/main.c @@ -15,7 +15,7 @@ LOG_MODULE_REGISTER(main); void main(void) { struct sensor_value oversampling_rate = { 8192, 0 }; - struct device *dev = device_get_binding(CONFIG_MS5837_DEV_NAME); + struct device *dev = device_get_binding(DT_MS5837_DEV_NAME); if (dev == NULL) { LOG_ERR("Could not find MS5837 device, aborting test."); diff --git a/samples/sensor/vl53l0x/src/main.c b/samples/sensor/vl53l0x/src/main.c index 4adb06c400a..f24b6992e9b 100644 --- a/samples/sensor/vl53l0x/src/main.c +++ b/samples/sensor/vl53l0x/src/main.c @@ -12,7 +12,7 @@ void main(void) { - struct device *dev = device_get_binding(CONFIG_VL53L0X_NAME); + struct device *dev = device_get_binding(DT_VL53L0X_NAME); struct sensor_value value; int ret; diff --git a/samples/shields/x_nucleo_iks01a1/src/main.c b/samples/shields/x_nucleo_iks01a1/src/main.c index eb789627e0a..8065383135e 100644 --- a/samples/shields/x_nucleo_iks01a1/src/main.c +++ b/samples/shields/x_nucleo_iks01a1/src/main.c @@ -14,10 +14,10 @@ void main(void) { struct sensor_value temp, hum, press; struct sensor_value magn_xyz[3], accel_xyz[3]; - struct device *hts221 = device_get_binding(CONFIG_HTS221_NAME); - struct device *lis3mdl = device_get_binding(CONFIG_LIS3MDL_NAME); - struct device *lsm6ds0 = device_get_binding(CONFIG_LSM6DS0_DEV_NAME); - struct device *lps25hb = device_get_binding(CONFIG_LPS25HB_DEV_NAME); + struct device *hts221 = device_get_binding(DT_HTS221_NAME); + struct device *lis3mdl = device_get_binding(DT_LIS3MDL_NAME); + struct device *lsm6ds0 = device_get_binding(DT_LSM6DS0_DEV_NAME); + struct device *lps25hb = device_get_binding(DT_LPS25HB_DEV_NAME); if (hts221 == NULL) { printf("Could not get HTS221 device\n"); diff --git a/samples/subsys/nvs/src/main.c b/samples/subsys/nvs/src/main.c index a2e154e56cc..01728b2e922 100644 --- a/samples/subsys/nvs/src/main.c +++ b/samples/subsys/nvs/src/main.c @@ -75,7 +75,7 @@ void main(void) u8_t key[8], longarray[128]; u32_t reboot_counter = 0, reboot_counter_his; - rc = nvs_init(&fs, FLASH_DEV_NAME); + rc = nvs_init(&fs, DT_FLASH_DEV_NAME); if (rc) { printk("Flash Init failed\n"); } diff --git a/soc/arc/quark_se_c1000_ss/dts_fixup.h b/soc/arc/quark_se_c1000_ss/dts_fixup.h index f2e2d9115dd..e5d8037fed4 100644 --- a/soc/arc/quark_se_c1000_ss/dts_fixup.h +++ b/soc/arc/quark_se_c1000_ss/dts_fixup.h @@ -1,13 +1,13 @@ /* SoC level DTS fixup file */ -#define CONFIG_UART_QMSI_0_BAUDRATE DT_INTEL_QMSI_UART_B0002000_CURRENT_SPEED -#define CONFIG_UART_QMSI_0_NAME DT_INTEL_QMSI_UART_B0002000_LABEL -#define CONFIG_UART_QMSI_0_IRQ DT_INTEL_QMSI_UART_B0002000_IRQ_0 +#define DT_UART_QMSI_0_BAUDRATE DT_INTEL_QMSI_UART_B0002000_CURRENT_SPEED +#define DT_UART_QMSI_0_NAME DT_INTEL_QMSI_UART_B0002000_LABEL +#define DT_UART_QMSI_0_IRQ DT_INTEL_QMSI_UART_B0002000_IRQ_0 #define CONFIG_UART_QMSI_0_IRQ_PRI DT_INTEL_QMSI_UART_B0002000_IRQ_0_PRIORITY -#define CONFIG_UART_QMSI_1_BAUDRATE DT_INTEL_QMSI_UART_B0002400_CURRENT_SPEED -#define CONFIG_UART_QMSI_1_NAME DT_INTEL_QMSI_UART_B0002400_LABEL -#define CONFIG_UART_QMSI_1_IRQ DT_INTEL_QMSI_UART_B0002400_IRQ_0 +#define DT_UART_QMSI_1_BAUDRATE DT_INTEL_QMSI_UART_B0002400_CURRENT_SPEED +#define DT_UART_QMSI_1_NAME DT_INTEL_QMSI_UART_B0002400_LABEL +#define DT_UART_QMSI_1_IRQ DT_INTEL_QMSI_UART_B0002400_IRQ_0 #define CONFIG_UART_QMSI_1_IRQ_PRI DT_INTEL_QMSI_UART_B0002400_IRQ_0_PRIORITY #define SRAM_START CONFIG_SRAM_BASE_ADDRESS @@ -16,84 +16,84 @@ #define FLASH_START CONFIG_FLASH_BASE_ADDRESS #define FLASH_SIZE CONFIG_FLASH_SIZE -#define CONFIG_DCCM_BASE_ADDRESS DT_ARC_DCCM_80000000_BASE_ADDRESS -#define CONFIG_DCCM_SIZE (DT_ARC_DCCM_80000000_SIZE >> 10) +#define DT_DCCM_BASE_ADDRESS DT_ARC_DCCM_80000000_BASE_ADDRESS +#define DT_DCCM_SIZE (DT_ARC_DCCM_80000000_SIZE >> 10) -#define CONFIG_I2C_SS_0_NAME DT_INTEL_QMSI_SS_I2C_80012000_LABEL -#define CONFIG_I2C_SS_0_ERR_IRQ DT_INTEL_QMSI_SS_I2C_80012000_IRQ_ERROR -#define CONFIG_I2C_SS_0_ERR_IRQ_PRI DT_INTEL_QMSI_SS_I2C_80012000_IRQ_ERROR_PRIORITY -#define CONFIG_I2C_SS_0_RX_IRQ DT_INTEL_QMSI_SS_I2C_80012000_IRQ_RX -#define CONFIG_I2C_SS_0_RX_IRQ_PRI DT_INTEL_QMSI_SS_I2C_80012000_IRQ_RX_PRIORITY -#define CONFIG_I2C_SS_0_TX_IRQ DT_INTEL_QMSI_SS_I2C_80012000_IRQ_TX -#define CONFIG_I2C_SS_0_TX_IRQ_PRI DT_INTEL_QMSI_SS_I2C_80012000_IRQ_TX_PRIORITY -#define CONFIG_I2C_SS_0_STOP_IRQ DT_INTEL_QMSI_SS_I2C_80012000_IRQ_STOP -#define CONFIG_I2C_SS_0_STOP_IRQ_PRI DT_INTEL_QMSI_SS_I2C_80012000_IRQ_STOP_PRIORITY -#define CONFIG_I2C_SS_0_BITRATE DT_INTEL_QMSI_SS_I2C_80012000_CLOCK_FREQUENCY -#define CONFIG_I2C_SS_1_NAME DT_INTEL_QMSI_SS_I2C_80012100_LABEL -#define CONFIG_I2C_SS_1_ERR_IRQ DT_INTEL_QMSI_SS_I2C_80012100_IRQ_ERROR -#define CONFIG_I2C_SS_1_ERR_IRQ_PRI DT_INTEL_QMSI_SS_I2C_80012100_IRQ_ERROR_PRIORITY -#define CONFIG_I2C_SS_1_RX_IRQ DT_INTEL_QMSI_SS_I2C_80012100_IRQ_RX -#define CONFIG_I2C_SS_1_RX_IRQ_PRI DT_INTEL_QMSI_SS_I2C_80012100_IRQ_RX_PRIORITY -#define CONFIG_I2C_SS_1_TX_IRQ DT_INTEL_QMSI_SS_I2C_80012100_IRQ_TX -#define CONFIG_I2C_SS_1_TX_IRQ_PRI DT_INTEL_QMSI_SS_I2C_80012100_IRQ_TX_PRIORITY -#define CONFIG_I2C_SS_1_STOP_IRQ DT_INTEL_QMSI_SS_I2C_80012100_IRQ_STOP -#define CONFIG_I2C_SS_1_STOP_IRQ_PRI DT_INTEL_QMSI_SS_I2C_80012100_IRQ_STOP_PRIORITY -#define CONFIG_I2C_SS_1_BITRATE DT_INTEL_QMSI_SS_I2C_80012100_CLOCK_FREQUENCY +#define DT_I2C_SS_0_NAME DT_INTEL_QMSI_SS_I2C_80012000_LABEL +#define DT_I2C_SS_0_ERR_IRQ DT_INTEL_QMSI_SS_I2C_80012000_IRQ_ERROR +#define DT_I2C_SS_0_ERR_IRQ_PRI DT_INTEL_QMSI_SS_I2C_80012000_IRQ_ERROR_PRIORITY +#define DT_I2C_SS_0_RX_IRQ DT_INTEL_QMSI_SS_I2C_80012000_IRQ_RX +#define DT_I2C_SS_0_RX_IRQ_PRI DT_INTEL_QMSI_SS_I2C_80012000_IRQ_RX_PRIORITY +#define DT_I2C_SS_0_TX_IRQ DT_INTEL_QMSI_SS_I2C_80012000_IRQ_TX +#define DT_I2C_SS_0_TX_IRQ_PRI DT_INTEL_QMSI_SS_I2C_80012000_IRQ_TX_PRIORITY +#define DT_I2C_SS_0_STOP_IRQ DT_INTEL_QMSI_SS_I2C_80012000_IRQ_STOP +#define DT_I2C_SS_0_STOP_IRQ_PRI DT_INTEL_QMSI_SS_I2C_80012000_IRQ_STOP_PRIORITY +#define DT_I2C_SS_0_BITRATE DT_INTEL_QMSI_SS_I2C_80012000_CLOCK_FREQUENCY +#define DT_I2C_SS_1_NAME DT_INTEL_QMSI_SS_I2C_80012100_LABEL +#define DT_I2C_SS_1_ERR_IRQ DT_INTEL_QMSI_SS_I2C_80012100_IRQ_ERROR +#define DT_I2C_SS_1_ERR_IRQ_PRI DT_INTEL_QMSI_SS_I2C_80012100_IRQ_ERROR_PRIORITY +#define DT_I2C_SS_1_RX_IRQ DT_INTEL_QMSI_SS_I2C_80012100_IRQ_RX +#define DT_I2C_SS_1_RX_IRQ_PRI DT_INTEL_QMSI_SS_I2C_80012100_IRQ_RX_PRIORITY +#define DT_I2C_SS_1_TX_IRQ DT_INTEL_QMSI_SS_I2C_80012100_IRQ_TX +#define DT_I2C_SS_1_TX_IRQ_PRI DT_INTEL_QMSI_SS_I2C_80012100_IRQ_TX_PRIORITY +#define DT_I2C_SS_1_STOP_IRQ DT_INTEL_QMSI_SS_I2C_80012100_IRQ_STOP +#define DT_I2C_SS_1_STOP_IRQ_PRI DT_INTEL_QMSI_SS_I2C_80012100_IRQ_STOP_PRIORITY +#define DT_I2C_SS_1_BITRATE DT_INTEL_QMSI_SS_I2C_80012100_CLOCK_FREQUENCY #define CONFIG_I2C_0_NAME DT_INTEL_QMSI_I2C_B0002800_LABEL -#define CONFIG_I2C_0_BITRATE DT_INTEL_QMSI_I2C_B0002800_CLOCK_FREQUENCY -#define CONFIG_I2C_0_IRQ DT_INTEL_QMSI_I2C_B0002800_IRQ_0 +#define DT_I2C_0_BITRATE DT_INTEL_QMSI_I2C_B0002800_CLOCK_FREQUENCY +#define DT_I2C_0_IRQ DT_INTEL_QMSI_I2C_B0002800_IRQ_0 #define CONFIG_I2C_0_IRQ_PRI DT_INTEL_QMSI_I2C_B0002800_IRQ_0_PRIORITY #define CONFIG_I2C_1_NAME DT_INTEL_QMSI_I2C_B0002C00_LABEL -#define CONFIG_I2C_1_BITRATE DT_INTEL_QMSI_I2C_B0002C00_CLOCK_FREQUENCY -#define CONFIG_I2C_1_IRQ DT_INTEL_QMSI_I2C_B0002C00_IRQ_0 +#define DT_I2C_1_BITRATE DT_INTEL_QMSI_I2C_B0002C00_CLOCK_FREQUENCY +#define DT_I2C_1_IRQ DT_INTEL_QMSI_I2C_B0002C00_IRQ_0 #define CONFIG_I2C_1_IRQ_PRI DT_INTEL_QMSI_I2C_B0002C00_IRQ_0_PRIORITY #define CONFIG_RTC_0_NAME DT_INTEL_QMSI_RTC_B0000400_LABEL -#define CONFIG_RTC_0_IRQ DT_INTEL_QMSI_RTC_B0000400_IRQ_0 +#define DT_RTC_0_IRQ DT_INTEL_QMSI_RTC_B0000400_IRQ_0 #define CONFIG_RTC_0_IRQ_PRI DT_INTEL_QMSI_RTC_B0000400_IRQ_0_PRIORITY -#define CONFIG_GPIO_QMSI_SS_0_NAME DT_INTEL_QMSI_SS_GPIO_80017800_LABEL -#define CONFIG_GPIO_QMSI_SS_0_IRQ DT_INTEL_QMSI_SS_GPIO_80017800_IRQ_0 -#define CONFIG_GPIO_QMSI_SS_0_IRQ_PRI DT_INTEL_QMSI_SS_GPIO_80017800_IRQ_0_PRIORITY +#define DT_GPIO_QMSI_SS_0_NAME DT_INTEL_QMSI_SS_GPIO_80017800_LABEL +#define DT_GPIO_QMSI_SS_0_IRQ DT_INTEL_QMSI_SS_GPIO_80017800_IRQ_0 +#define DT_GPIO_QMSI_SS_0_IRQ_PRI DT_INTEL_QMSI_SS_GPIO_80017800_IRQ_0_PRIORITY -#define CONFIG_GPIO_QMSI_SS_1_NAME DT_INTEL_QMSI_SS_GPIO_80017900_LABEL -#define CONFIG_GPIO_QMSI_SS_1_IRQ DT_INTEL_QMSI_SS_GPIO_80017900_IRQ_0 -#define CONFIG_GPIO_QMSI_SS_1_IRQ_PRI DT_INTEL_QMSI_SS_GPIO_80017900_IRQ_0_PRIORITY +#define DT_GPIO_QMSI_SS_1_NAME DT_INTEL_QMSI_SS_GPIO_80017900_LABEL +#define DT_GPIO_QMSI_SS_1_IRQ DT_INTEL_QMSI_SS_GPIO_80017900_IRQ_0 +#define DT_GPIO_QMSI_SS_1_IRQ_PRI DT_INTEL_QMSI_SS_GPIO_80017900_IRQ_0_PRIORITY -#define CONFIG_GPIO_QMSI_0_NAME DT_INTEL_QMSI_GPIO_B0000C00_LABEL -#define CONFIG_GPIO_QMSI_0_IRQ DT_INTEL_QMSI_GPIO_B0000C00_IRQ_0 +#define DT_GPIO_QMSI_0_NAME DT_INTEL_QMSI_GPIO_B0000C00_LABEL +#define DT_GPIO_QMSI_0_IRQ DT_INTEL_QMSI_GPIO_B0000C00_IRQ_0 #define CONFIG_GPIO_QMSI_0_IRQ_PRI DT_INTEL_QMSI_GPIO_B0000C00_IRQ_0_PRIORITY -#define CONFIG_GPIO_QMSI_1_NAME DT_INTEL_QMSI_GPIO_B0800B00_LABEL -#define CONFIG_GPIO_QMSI_1_IRQ DT_INTEL_QMSI_GPIO_B0800B00_IRQ_0 -#define CONFIG_GPIO_QMSI_1_IRQ_PRI DT_INTEL_QMSI_GPIO_B0800B00_IRQ_0_PRIORITY +#define DT_GPIO_QMSI_1_NAME DT_INTEL_QMSI_GPIO_B0800B00_LABEL +#define DT_GPIO_QMSI_1_IRQ DT_INTEL_QMSI_GPIO_B0800B00_IRQ_0 +#define DT_GPIO_QMSI_1_IRQ_PRI DT_INTEL_QMSI_GPIO_B0800B00_IRQ_0_PRIORITY -#define CONFIG_ADC_0_IRQ DT_SNPS_DW_ADC_80015000_IRQ_NORMAL -#define CONFIG_ADC_IRQ_ERR DT_SNPS_DW_ADC_80015000_IRQ_ERROR +#define DT_ADC_0_IRQ DT_SNPS_DW_ADC_80015000_IRQ_NORMAL +#define DT_ADC_IRQ_ERR DT_SNPS_DW_ADC_80015000_IRQ_ERROR #define CONFIG_ADC_0_IRQ_PRI DT_SNPS_DW_ADC_80015000_IRQ_0_PRIORITY #define CONFIG_ADC_0_NAME DT_SNPS_DW_ADC_80015000_LABEL -#define CONFIG_ADC_0_BASE_ADDRESS DT_SNPS_DW_ADC_80015000_BASE_ADDRESS +#define DT_ADC_0_BASE_ADDRESS DT_SNPS_DW_ADC_80015000_BASE_ADDRESS -#define CONFIG_SPI_0_BASE_ADDRESS DT_SNPS_DESIGNWARE_SPI_80010000_BASE_ADDRESS +#define DT_SPI_0_BASE_ADDRESS DT_SNPS_DESIGNWARE_SPI_80010000_BASE_ADDRESS #define CONFIG_SPI_0_NAME DT_SNPS_DESIGNWARE_SPI_80010000_LABEL -#define CONFIG_SPI_0_IRQ_ERR_INT DT_SNPS_DESIGNWARE_SPI_80010000_IRQ_ERR_INT -#define CONFIG_SPI_0_IRQ_ERR_INT_PRI DT_SNPS_DESIGNWARE_SPI_80010000_IRQ_ERR_INT_PRIORITY -#define CONFIG_SPI_0_IRQ_RX_AVAIL DT_SNPS_DESIGNWARE_SPI_80010000_IRQ_RX_AVAIL -#define CONFIG_SPI_0_IRQ_RX_AVAIL_PRI DT_SNPS_DESIGNWARE_SPI_80010000_IRQ_RX_AVAIL_PRIORITY -#define CONFIG_SPI_0_IRQ_TX_REQ DT_SNPS_DESIGNWARE_SPI_80010000_IRQ_TX_REQ -#define CONFIG_SPI_0_IRQ_TX_REQ_PRI DT_SNPS_DESIGNWARE_SPI_80010000_IRQ_TX_REQ_PRIORITY +#define DT_SPI_0_IRQ_ERR_INT DT_SNPS_DESIGNWARE_SPI_80010000_IRQ_ERR_INT +#define DT_SPI_0_IRQ_ERR_INT_PRI DT_SNPS_DESIGNWARE_SPI_80010000_IRQ_ERR_INT_PRIORITY +#define DT_SPI_0_IRQ_RX_AVAIL DT_SNPS_DESIGNWARE_SPI_80010000_IRQ_RX_AVAIL +#define DT_SPI_0_IRQ_RX_AVAIL_PRI DT_SNPS_DESIGNWARE_SPI_80010000_IRQ_RX_AVAIL_PRIORITY +#define DT_SPI_0_IRQ_TX_REQ DT_SNPS_DESIGNWARE_SPI_80010000_IRQ_TX_REQ +#define DT_SPI_0_IRQ_TX_REQ_PRI DT_SNPS_DESIGNWARE_SPI_80010000_IRQ_TX_REQ_PRIORITY -#define CONFIG_SPI_1_BASE_ADDRESS DT_SNPS_DESIGNWARE_SPI_80010100_BASE_ADDRESS +#define DT_SPI_1_BASE_ADDRESS DT_SNPS_DESIGNWARE_SPI_80010100_BASE_ADDRESS #define CONFIG_SPI_1_NAME DT_SNPS_DESIGNWARE_SPI_80010100_LABEL -#define CONFIG_SPI_1_IRQ_ERR_INT DT_SNPS_DESIGNWARE_SPI_80010100_IRQ_ERR_INT -#define CONFIG_SPI_1_IRQ_ERR_INT_PRI DT_SNPS_DESIGNWARE_SPI_80010100_IRQ_ERR_INT_PRIORITY -#define CONFIG_SPI_1_IRQ_RX_AVAIL DT_SNPS_DESIGNWARE_SPI_80010100_IRQ_RX_AVAIL -#define CONFIG_SPI_1_IRQ_RX_AVAIL_PRI DT_SNPS_DESIGNWARE_SPI_80010100_IRQ_RX_AVAIL_PRIORITY -#define CONFIG_SPI_1_IRQ_TX_REQ DT_SNPS_DESIGNWARE_SPI_80010100_IRQ_TX_REQ -#define CONFIG_SPI_1_IRQ_TX_REQ_PRI DT_SNPS_DESIGNWARE_SPI_80010100_IRQ_TX_REQ_PRIORITY +#define DT_SPI_1_IRQ_ERR_INT DT_SNPS_DESIGNWARE_SPI_80010100_IRQ_ERR_INT +#define DT_SPI_1_IRQ_ERR_INT_PRI DT_SNPS_DESIGNWARE_SPI_80010100_IRQ_ERR_INT_PRIORITY +#define DT_SPI_1_IRQ_RX_AVAIL DT_SNPS_DESIGNWARE_SPI_80010100_IRQ_RX_AVAIL +#define DT_SPI_1_IRQ_RX_AVAIL_PRI DT_SNPS_DESIGNWARE_SPI_80010100_IRQ_RX_AVAIL_PRIORITY +#define DT_SPI_1_IRQ_TX_REQ DT_SNPS_DESIGNWARE_SPI_80010100_IRQ_TX_REQ +#define DT_SPI_1_IRQ_TX_REQ_PRI DT_SNPS_DESIGNWARE_SPI_80010100_IRQ_TX_REQ_PRIORITY #define CONFIG_WDT_0_NAME DT_INTEL_QMSI_WATCHDOG_B0000000_LABEL -#define CONFIG_WDT_0_IRQ DT_INTEL_QMSI_WATCHDOG_B0000000_IRQ_0 -#define CONFIG_WDT_0_IRQ_PRI DT_INTEL_QMSI_WATCHDOG_B0000000_IRQ_0_PRIORITY -#define CONFIG_WDT_0_IRQ_FLAGS 0 +#define DT_WDT_0_IRQ DT_INTEL_QMSI_WATCHDOG_B0000000_IRQ_0 +#define DT_WDT_0_IRQ_PRI DT_INTEL_QMSI_WATCHDOG_B0000000_IRQ_0_PRIORITY +#define DT_WDT_0_IRQ_FLAGS 0 /* End of SoC Level DTS fixup file */ diff --git a/soc/arc/quark_se_c1000_ss/linker.ld b/soc/arc/quark_se_c1000_ss/linker.ld index 3423962d505..72464e6ecd2 100644 --- a/soc/arc/quark_se_c1000_ss/linker.ld +++ b/soc/arc/quark_se_c1000_ss/linker.ld @@ -23,8 +23,8 @@ #define SRAM_SIZE CONFIG_SRAM_SIZE /* Data Closely Coupled Memory (DCCM) base address and size */ -#define DCCM_START CONFIG_DCCM_BASE_ADDRESS -#define DCCM_SIZE CONFIG_DCCM_SIZE +#define DCCM_START DT_DCCM_BASE_ADDRESS +#define DCCM_SIZE DT_DCCM_SIZE #include #include diff --git a/soc/arc/quark_se_c1000_ss/soc.h b/soc/arc/quark_se_c1000_ss/soc.h index 1778fa8e084..ca576977406 100644 --- a/soc/arc/quark_se_c1000_ss/soc.h +++ b/soc/arc/quark_se_c1000_ss/soc.h @@ -125,8 +125,8 @@ #define I2C_SS_1_STOP_VECTOR 29 #define I2C_SS_1_STOP_MASK 0x42C -#define CONFIG_I2C_0_IRQ_FLAGS (IOAPIC_LEVEL | IOAPIC_HIGH) -#define CONFIG_I2C_1_IRQ_FLAGS (IOAPIC_LEVEL | IOAPIC_HIGH) +#define DT_I2C_0_IRQ_FLAGS (IOAPIC_LEVEL | IOAPIC_HIGH) +#define DT_I2C_1_IRQ_FLAGS (IOAPIC_LEVEL | IOAPIC_HIGH) /* @@ -134,32 +134,32 @@ */ #define GPIO_DW_IO_ACCESS -#define GPIO_DW_0_BASE_ADDR 0x80017800 -#define GPIO_DW_0_IRQ 20 -#define GPIO_DW_0_BITS 8 +#define DT_GPIO_DW_0_BASE_ADDR 0x80017800 +#define DT_GPIO_DW_0_IRQ 20 +#define DT_GPIO_DW_0_BITS 8 #define GPIO_DW_PORT_0_INT_MASK (SCSS_REGISTER_BASE + 0x408) -#define GPIO_DW_1_BASE_ADDR 0x80017900 -#define GPIO_DW_1_IRQ 21 -#define GPIO_DW_1_BITS 8 +#define DT_GPIO_DW_1_BASE_ADDR 0x80017900 +#define DT_GPIO_DW_1_IRQ 21 +#define DT_GPIO_DW_1_BITS 8 #define GPIO_DW_PORT_1_INT_MASK (SCSS_REGISTER_BASE + 0x40C) #if defined(CONFIG_IOAPIC) -#define GPIO_DW_0_IRQ_FLAGS (IOAPIC_EDGE | IOAPIC_HIGH) +#define DT_GPIO_DW_0_IRQ_FLAGS (IOAPIC_EDGE | IOAPIC_HIGH) #define GPIO_DW_1_IRQ_FLAGS (IOAPIC_EDGE | IOAPIC_HIGH) #else -#define GPIO_DW_0_IRQ_FLAGS 0 +#define DT_GPIO_DW_0_IRQ_FLAGS 0 #define GPIO_DW_1_IRQ_FLAGS 0 #endif -#define CONFIG_GPIO_QMSI_0_IRQ_FLAGS (IOAPIC_EDGE | IOAPIC_HIGH) -#define CONFIG_GPIO_QMSI_1_IRQ_FLAGS (IOAPIC_EDGE | IOAPIC_HIGH) +#define DT_GPIO_QMSI_0_IRQ_FLAGS (IOAPIC_EDGE | IOAPIC_HIGH) +#define DT_GPIO_QMSI_1_IRQ_FLAGS (IOAPIC_EDGE | IOAPIC_HIGH) /* * UART */ -#define CONFIG_UART_QMSI_0_IRQ_FLAGS 0 -#define CONFIG_UART_QMSI_1_IRQ_FLAGS 0 +#define DT_UART_QMSI_0_IRQ_FLAGS 0 +#define DT_UART_QMSI_1_IRQ_FLAGS 0 /* * SPI @@ -175,7 +175,7 @@ #define SPI_DW_PORT_1_RX_INT_MASK (SCSS_REGISTER_BASE + 0x440) #define SPI_DW_PORT_1_TX_INT_MASK (SCSS_REGISTER_BASE + 0x444) -#define SPI_DW_IRQ_FLAGS 0 +#define DT_SPI_DW_IRQ_FLAGS 0 #define SPI_DW_PORT_2_REGS 0xB0001000 #define SPI_DW_PORT_2_IRQ IRQ_SPI_MST0_INTR @@ -198,7 +198,7 @@ * RTC */ -#define CONFIG_RTC_0_IRQ_FLAGS (IOAPIC_EDGE | IOAPIC_HIGH) +#define DT_RTC_0_IRQ_FLAGS (IOAPIC_EDGE | IOAPIC_HIGH) static inline void _quark_se_ss_ready(void) diff --git a/soc/arc/snps_emsk/dts_fixup.h b/soc/arc/snps_emsk/dts_fixup.h index 14eeab28db5..d82596a4abb 100644 --- a/soc/arc/snps_emsk/dts_fixup.h +++ b/soc/arc/snps_emsk/dts_fixup.h @@ -1,101 +1,101 @@ /* SoC level DTS fixup file */ /* CCM configuration */ -#define CONFIG_DCCM_BASE_ADDRESS DT_ARC_DCCM_80000000_BASE_ADDRESS -#define CONFIG_DCCM_SIZE (DT_ARC_DCCM_80000000_SIZE >> 10) +#define DT_DCCM_BASE_ADDRESS DT_ARC_DCCM_80000000_BASE_ADDRESS +#define DT_DCCM_SIZE (DT_ARC_DCCM_80000000_SIZE >> 10) -#define CONFIG_ICCM_BASE_ADDRESS ARC_ICCM_0_BASE_ADDRESS -#define CONFIG_ICCM_SIZE (ARC_ICCM_0_SIZE >> 10) +#define DT_ICCM_BASE_ADDRESS ARC_ICCM_0_BASE_ADDRESS +#define DT_ICCM_SIZE (ARC_ICCM_0_SIZE >> 10) /* * UART configuration */ -#define CONFIG_UART_NS16550_PORT_0_BASE_ADDR DT_NS16550_F0008000_BASE_ADDRESS -#define CONFIG_UART_NS16550_PORT_0_IRQ DT_NS16550_F0008000_IRQ_0 -#define CONFIG_UART_NS16550_PORT_0_CLK_FREQ DT_NS16550_F0008000_CLOCK_FREQUENCY +#define DT_UART_NS16550_PORT_0_BASE_ADDR DT_NS16550_F0008000_BASE_ADDRESS +#define DT_UART_NS16550_PORT_0_IRQ DT_NS16550_F0008000_IRQ_0 +#define DT_UART_NS16550_PORT_0_CLK_FREQ DT_NS16550_F0008000_CLOCK_FREQUENCY #define CONFIG_UART_NS16550_PORT_0_BAUD_RATE DT_NS16550_F0008000_CURRENT_SPEED #define CONFIG_UART_NS16550_PORT_0_NAME DT_NS16550_F0008000_LABEL #define CONFIG_UART_NS16550_PORT_0_IRQ_PRI DT_NS16550_F0008000_IRQ_0_PRIORITY -#define CONFIG_UART_NS16550_PORT_1_BASE_ADDR DT_NS16550_F0009000_BASE_ADDRESS -#define CONFIG_UART_NS16550_PORT_1_IRQ DT_NS16550_F0009000_IRQ_0 -#define CONFIG_UART_NS16550_PORT_1_CLK_FREQ DT_NS16550_F0009000_CLOCK_FREQUENCY +#define DT_UART_NS16550_PORT_1_BASE_ADDR DT_NS16550_F0009000_BASE_ADDRESS +#define DT_UART_NS16550_PORT_1_IRQ DT_NS16550_F0009000_IRQ_0 +#define DT_UART_NS16550_PORT_1_CLK_FREQ DT_NS16550_F0009000_CLOCK_FREQUENCY #define CONFIG_UART_NS16550_PORT_1_BAUD_RATE DT_NS16550_F0009000_CURRENT_SPEED #define CONFIG_UART_NS16550_PORT_1_NAME DT_NS16550_F0009000_LABEL #define CONFIG_UART_NS16550_PORT_1_IRQ_PRI DT_NS16550_F0009000_IRQ_0_PRIORITY -#define CONFIG_UART_NS16550_PORT_2_BASE_ADDR DT_NS16550_F000A000_BASE_ADDRESS -#define CONFIG_UART_NS16550_PORT_2_IRQ DT_NS16550_F000A000_IRQ_0 -#define CONFIG_UART_NS16550_PORT_2_CLK_FREQ DT_NS16550_F000A000_CLOCK_FREQUENCY -#define CONFIG_UART_NS16550_PORT_2_BAUD_RATE DT_NS16550_F000A000_CURRENT_SPEED -#define CONFIG_UART_NS16550_PORT_2_NAME DT_NS16550_F000A000_LABEL -#define CONFIG_UART_NS16550_PORT_2_IRQ_PRI DT_NS16550_F000A000_IRQ_0_PRIORITY +#define DT_UART_NS16550_PORT_2_BASE_ADDR DT_NS16550_F000A000_BASE_ADDRESS +#define DT_UART_NS16550_PORT_2_IRQ DT_NS16550_F000A000_IRQ_0 +#define DT_UART_NS16550_PORT_2_CLK_FREQ DT_NS16550_F000A000_CLOCK_FREQUENCY +#define DT_UART_NS16550_PORT_2_BAUD_RATE DT_NS16550_F000A000_CURRENT_SPEED +#define DT_UART_NS16550_PORT_2_NAME DT_NS16550_F000A000_LABEL +#define DT_UART_NS16550_PORT_2_IRQ_PRI DT_NS16550_F000A000_IRQ_0_PRIORITY /* * I2C configuration */ /* I2C_0 is on Pmod2 connector */ -#define CONFIG_I2C_0_BASE_ADDR DT_SNPS_DESIGNWARE_I2C_F0004000_BASE_ADDRESS -#define CONFIG_I2C_0_BITRATE DT_SNPS_DESIGNWARE_I2C_F0004000_CLOCK_FREQUENCY -#define CONFIG_I2C_0_IRQ DT_SNPS_DESIGNWARE_I2C_F0004000_IRQ_0 +#define DT_I2C_0_BASE_ADDR DT_SNPS_DESIGNWARE_I2C_F0004000_BASE_ADDRESS +#define DT_I2C_0_BITRATE DT_SNPS_DESIGNWARE_I2C_F0004000_CLOCK_FREQUENCY +#define DT_I2C_0_IRQ DT_SNPS_DESIGNWARE_I2C_F0004000_IRQ_0 #define CONFIG_I2C_0_IRQ_PRI DT_SNPS_DESIGNWARE_I2C_F0004000_IRQ_0_PRIORITY #define CONFIG_I2C_0_NAME DT_SNPS_DESIGNWARE_I2C_F0004000_LABEL -#define CONFIG_I2C_0_IRQ_FLAGS 0 +#define DT_I2C_0_IRQ_FLAGS 0 /* I2C_1 is on Pmod4 connector */ -#define CONFIG_I2C_1_BASE_ADDR DT_SNPS_DESIGNWARE_I2C_F0005000_BASE_ADDRESS -#define CONFIG_I2C_1_BITRATE DT_SNPS_DESIGNWARE_I2C_F0005000_CLOCK_FREQUENCY -#define CONFIG_I2C_1_IRQ DT_SNPS_DESIGNWARE_I2C_F0005000_IRQ_0 +#define DT_I2C_1_BASE_ADDR DT_SNPS_DESIGNWARE_I2C_F0005000_BASE_ADDRESS +#define DT_I2C_1_BITRATE DT_SNPS_DESIGNWARE_I2C_F0005000_CLOCK_FREQUENCY +#define DT_I2C_1_IRQ DT_SNPS_DESIGNWARE_I2C_F0005000_IRQ_0 #define CONFIG_I2C_1_IRQ_PRI DT_SNPS_DESIGNWARE_I2C_F0005000_IRQ_0_PRIORITY #define CONFIG_I2C_1_NAME DT_SNPS_DESIGNWARE_I2C_F0005000_LABEL -#define CONFIG_I2C_1_IRQ_FLAGS 0 +#define DT_I2C_1_IRQ_FLAGS 0 /* * GPIO configuration */ -#define GPIO_DW_0_BASE_ADDR DT_SNPS_DESIGNWARE_GPIO_F0002000_BASE_ADDRESS -#define GPIO_DW_0_BITS DT_SNPS_DESIGNWARE_GPIO_F0002000_BITS +#define DT_GPIO_DW_0_BASE_ADDR DT_SNPS_DESIGNWARE_GPIO_F0002000_BASE_ADDRESS +#define DT_GPIO_DW_0_BITS DT_SNPS_DESIGNWARE_GPIO_F0002000_BITS #define CONFIG_GPIO_DW_0_NAME DT_SNPS_DESIGNWARE_GPIO_F0002000_LABEL -#define GPIO_DW_0_IRQ DT_SNPS_DESIGNWARE_GPIO_F0002000_IRQ_0 +#define DT_GPIO_DW_0_IRQ DT_SNPS_DESIGNWARE_GPIO_F0002000_IRQ_0 #define CONFIG_GPIO_DW_0_IRQ_PRI DT_SNPS_DESIGNWARE_GPIO_F0002000_IRQ_0_PRIORITY -#define GPIO_DW_0_IRQ_FLAGS 0 +#define DT_GPIO_DW_0_IRQ_FLAGS 0 -#define GPIO_DW_1_BASE_ADDR DT_SNPS_DESIGNWARE_GPIO_F000200C_BASE_ADDRESS -#define GPIO_DW_1_BITS DT_SNPS_DESIGNWARE_GPIO_F000200C_BITS +#define DT_GPIO_DW_1_BASE_ADDR DT_SNPS_DESIGNWARE_GPIO_F000200C_BASE_ADDRESS +#define DT_GPIO_DW_1_BITS DT_SNPS_DESIGNWARE_GPIO_F000200C_BITS #define CONFIG_GPIO_DW_1_NAME DT_SNPS_DESIGNWARE_GPIO_F000200C_LABEL -#define GPIO_DW_1_IRQ DT_SNPS_DESIGNWARE_GPIO_F000200C_IRQ_0 +#define DT_GPIO_DW_1_IRQ DT_SNPS_DESIGNWARE_GPIO_F000200C_IRQ_0 #define CONFIG_GPIO_DW_1_IRQ_PRI DT_SNPS_DESIGNWARE_GPIO_F000200C_IRQ_0_PRIORITY -#define GPIO_DW_2_BASE_ADDR DT_SNPS_DESIGNWARE_GPIO_F0002018_BASE_ADDRESS -#define GPIO_DW_2_BITS DT_SNPS_DESIGNWARE_GPIO_F0002018_BITS +#define DT_GPIO_DW_2_BASE_ADDR DT_SNPS_DESIGNWARE_GPIO_F0002018_BASE_ADDRESS +#define DT_GPIO_DW_2_BITS DT_SNPS_DESIGNWARE_GPIO_F0002018_BITS #define CONFIG_GPIO_DW_2_NAME DT_SNPS_DESIGNWARE_GPIO_F0002018_LABEL -#define GPIO_DW_2_IRQ DT_SNPS_DESIGNWARE_GPIO_F0002018_IRQ_0 +#define DT_GPIO_DW_2_IRQ DT_SNPS_DESIGNWARE_GPIO_F0002018_IRQ_0 #define CONFIG_GPIO_DW_2_IRQ_PRI DT_SNPS_DESIGNWARE_GPIO_F0002018_IRQ_0_PRIORITY -#define GPIO_DW_3_BASE_ADDR DT_SNPS_DESIGNWARE_GPIO_F0002024_BASE_ADDRESS -#define GPIO_DW_3_BITS DT_SNPS_DESIGNWARE_GPIO_F0002024_BITS +#define DT_GPIO_DW_3_BASE_ADDR DT_SNPS_DESIGNWARE_GPIO_F0002024_BASE_ADDRESS +#define DT_GPIO_DW_3_BITS DT_SNPS_DESIGNWARE_GPIO_F0002024_BITS #define CONFIG_GPIO_DW_3_NAME DT_SNPS_DESIGNWARE_GPIO_F0002024_LABEL -#define GPIO_DW_3_IRQ DT_SNPS_DESIGNWARE_GPIO_F0002024_IRQ_0 +#define DT_GPIO_DW_3_IRQ DT_SNPS_DESIGNWARE_GPIO_F0002024_IRQ_0 #define CONFIG_GPIO_DW_3_IRQ_PRI DT_SNPS_DESIGNWARE_GPIO_F0002024_IRQ_0_PRIORITY /* * SPI configuration */ -#define CONFIG_SPI_0_BASE_ADDRESS DT_SNPS_DESIGNWARE_SPI_F0006000_BASE_ADDRESS +#define DT_SPI_0_BASE_ADDRESS DT_SNPS_DESIGNWARE_SPI_F0006000_BASE_ADDRESS #define CONFIG_SPI_0_NAME DT_SNPS_DESIGNWARE_SPI_F0006000_LABEL -#define CONFIG_SPI_0_IRQ DT_SNPS_DESIGNWARE_SPI_F0006000_IRQ_0 +#define DT_SPI_0_IRQ DT_SNPS_DESIGNWARE_SPI_F0006000_IRQ_0 #define CONFIG_SPI_0_IRQ_PRI DT_SNPS_DESIGNWARE_SPI_F0006000_IRQ_0_PRIORITY -#define CONFIG_SPI_1_BASE_ADDRESS DT_SNPS_DESIGNWARE_SPI_F0007000_BASE_ADDRESS +#define DT_SPI_1_BASE_ADDRESS DT_SNPS_DESIGNWARE_SPI_F0007000_BASE_ADDRESS #define CONFIG_SPI_1_NAME DT_SNPS_DESIGNWARE_SPI_F0007000_LABEL -#define CONFIG_SPI_1_IRQ DT_SNPS_DESIGNWARE_SPI_F0007000_IRQ_0 +#define DT_SPI_1_IRQ DT_SNPS_DESIGNWARE_SPI_F0007000_IRQ_0 #define CONFIG_SPI_1_IRQ_PRI DT_SNPS_DESIGNWARE_SPI_F0007000_IRQ_0_PRIORITY -#define SPI_DW_IRQ_FLAGS 0 +#define DT_SPI_DW_IRQ_FLAGS 0 -#define SPI_DW_SPI_CLOCK DT_NS16550_F0009000_CLOCK_FREQUENCY +#define DT_SPI_DW_SPI_CLOCK DT_NS16550_F0009000_CLOCK_FREQUENCY /* End of SoC Level DTS fixup file */ diff --git a/soc/arc/snps_emsk/linker.ld b/soc/arc/snps_emsk/linker.ld index 1351502035c..f1b53fed0b8 100644 --- a/soc/arc/snps_emsk/linker.ld +++ b/soc/arc/snps_emsk/linker.ld @@ -22,18 +22,18 @@ #endif /* Instruction Closely Coupled Memory (ICCM) base address and size */ -#if defined(CONFIG_ICCM_BASE_ADDRESS) && (CONFIG_ICCM_SIZE > 0) -#define ICCM_START CONFIG_ICCM_BASE_ADDRESS -#define ICCM_SIZE CONFIG_ICCM_SIZE +#if defined(DT_ICCM_BASE_ADDRESS) && (DT_ICCM_SIZE > 0) +#define ICCM_START DT_ICCM_BASE_ADDRESS +#define ICCM_SIZE DT_ICCM_SIZE #endif /* * DCCM base address and size. DCCM is the data memory. */ /* Data Closely Coupled Memory (DCCM) base address and size */ -#if defined(CONFIG_DCCM_BASE_ADDRESS) && (CONFIG_DCCM_SIZE > 0) -#define DCCM_START CONFIG_DCCM_BASE_ADDRESS -#define DCCM_SIZE CONFIG_DCCM_SIZE +#if defined(DT_DCCM_BASE_ADDRESS) && (DT_DCCM_SIZE > 0) +#define DCCM_START DT_DCCM_BASE_ADDRESS +#define DCCM_SIZE DT_DCCM_SIZE #endif #include diff --git a/soc/arc/snps_emsk/soc.h b/soc/arc/snps_emsk/soc.h index 6c283e99282..64233730e77 100644 --- a/soc/arc/snps_emsk/soc.h +++ b/soc/arc/snps_emsk/soc.h @@ -54,43 +54,43 @@ /* * UARTs: UART0 & UART1 & UART2 */ -#define CONFIG_UART_NS16550_PORT_0_IRQ_FLAGS 0 /* Default */ -#define CONFIG_UART_NS16550_PORT_1_IRQ_FLAGS 0 /* Default */ +#define DT_UART_NS16550_PORT_0_IRQ_FLAGS 0 /* Default */ +#define DT_UART_NS16550_PORT_1_IRQ_FLAGS 0 /* Default */ #define CONFIG_UART_NS16550_PORT_2_IRQ_FLAGS 0 /* Default */ #ifndef CONFIG_HAS_DTS /* I2C */ /* I2C_0 is on Pmod2 connector */ -#define CONFIG_I2C_0_BASE_ADDR 0xF0004000 -#define CONFIG_I2C_0_IRQ_FLAGS 0 +#define DT_I2C_0_BASE_ADDR 0xF0004000 +#define DT_I2C_0_IRQ_FLAGS 0 /* I2C_1 is on Pmod4 connector */ -#define CONFIG_I2C_1_BASE_ADDR 0xF0005000 -#define CONFIG_I2C_1_IRQ_FLAGS 0 +#define DT_I2C_1_BASE_ADDR 0xF0005000 +#define DT_I2C_1_IRQ_FLAGS 0 /* GPIO */ -#define GPIO_DW_0_BASE_ADDR 0xF0002000 /* GPIO 0 : PORTA */ -#define GPIO_DW_0_BITS 32 +#define DT_GPIO_DW_0_BASE_ADDR 0xF0002000 /* GPIO 0 : PORTA */ +#define DT_GPIO_DW_0_BITS 32 #define GPIO_DW_PORT_0_INT_MASK 0 /* n/a */ -#define GPIO_DW_0_IRQ_FLAGS 0 /* Defaults */ +#define DT_GPIO_DW_0_IRQ_FLAGS 0 /* Defaults */ -#define GPIO_DW_1_BASE_ADDR 0xF000200C /* GPIO 1 : PORTB */ -#define GPIO_DW_1_BITS 9 /* 9 LEDs on board */ +#define DT_GPIO_DW_1_BASE_ADDR 0xF000200C /* GPIO 1 : PORTB */ +#define DT_GPIO_DW_1_BITS 9 /* 9 LEDs on board */ #define GPIO_DW_PORT_1_INT_MASK 0 /* n/a */ -#define GPIO_DW_2_BASE_ADDR 0xF0002018 /* GPIO 2 : PORTC */ -#define GPIO_DW_2_BITS 32 +#define DT_GPIO_DW_2_BASE_ADDR 0xF0002018 /* GPIO 2 : PORTC */ +#define DT_GPIO_DW_2_BITS 32 #define GPIO_DW_PORT_2_INT_MASK 0 /* n/a */ -#define GPIO_DW_3_BASE_ADDR 0xF0002024 /* GPIO 3 : PORTD */ -#define GPIO_DW_3_BITS 12 +#define DT_GPIO_DW_3_BASE_ADDR 0xF0002024 /* GPIO 3 : PORTD */ +#define DT_GPIO_DW_3_BITS 12 #define GPIO_DW_PORT_3_INT_MASK 0 /* n/a */ /* SPI */ -#define SPI_DW_SPI_CLOCK SYSCLK_DEFAULT_IOSC_HZ +#define DT_SPI_DW_SPI_CLOCK SYSCLK_DEFAULT_IOSC_HZ -#define SPI_DW_IRQ_FLAGS 0 +#define DT_SPI_DW_IRQ_FLAGS 0 /* * SPI Chip Select Assignments on EM Starter Kit @@ -107,18 +107,18 @@ * Peripheral Interrupt Connection Configurations */ #ifdef CONFIG_BOARD_EM_STARTERKIT_R23 -#define GPIO_DW_0_IRQ 24 -#define CONFIG_I2C_0_IRQ 25 -#define CONFIG_I2C_1_IRQ 26 +#define DT_GPIO_DW_0_IRQ 24 +#define DT_I2C_0_IRQ 25 +#define DT_I2C_1_IRQ 26 #else /* CONFIG_BOARD_EM_STARTERKIT_R23 */ -#define GPIO_DW_0_IRQ 22 -#define CONFIG_I2C_0_IRQ 23 -#define CONFIG_I2C_1_IRQ 24 +#define DT_GPIO_DW_0_IRQ 22 +#define DT_I2C_0_IRQ 23 +#define DT_I2C_1_IRQ 24 #endif /* !CONFIG_BOARD_EM_STARTERKIT_R23 */ -#define GPIO_DW_1_IRQ 0 /* can't interrupt */ -#define GPIO_DW_2_IRQ 0 /* can't interrupt */ -#define GPIO_DW_3_IRQ 0 /* can't interrupt */ +#define DT_GPIO_DW_1_IRQ 0 /* can't interrupt */ +#define DT_GPIO_DW_2_IRQ 0 /* can't interrupt */ +#define DT_GPIO_DW_3_IRQ 0 /* can't interrupt */ #endif /* CONFIG_HAS_DTS */ diff --git a/soc/arc/snps_emsk/soc_config.c b/soc/arc/snps_emsk/soc_config.c index d80b4d0a6a8..c13d42c8c23 100644 --- a/soc/arc/snps_emsk/soc_config.c +++ b/soc/arc/snps_emsk/soc_config.c @@ -19,12 +19,12 @@ static int uart_ns16550_init(struct device *dev) * send the UART the command to clear the interrupt */ #ifdef CONFIG_UART_NS16550_PORT_0 - sys_write32(0, CONFIG_UART_NS16550_PORT_0_BASE_ADDR+0x4); - sys_write32(0, CONFIG_UART_NS16550_PORT_0_BASE_ADDR+0x10); + sys_write32(0, DT_UART_NS16550_PORT_0_BASE_ADDR+0x4); + sys_write32(0, DT_UART_NS16550_PORT_0_BASE_ADDR+0x10); #endif /* CONFIG_UART_NS16550_PORT_0 */ #ifdef CONFIG_UART_NS16550_PORT_1 - sys_write32(0, CONFIG_UART_NS16550_PORT_1_BASE_ADDR+0x4); - sys_write32(0, CONFIG_UART_NS16550_PORT_1_BASE_ADDR+0x10); + sys_write32(0, DT_UART_NS16550_PORT_1_BASE_ADDR+0x4); + sys_write32(0, DT_UART_NS16550_PORT_1_BASE_ADDR+0x10); #endif /* CONFIG_UART_NS16550_PORT_1 */ return 0; diff --git a/soc/arc/snps_nsim/dts_fixup.h b/soc/arc/snps_nsim/dts_fixup.h index 7d9bee31613..6e37c3bed79 100644 --- a/soc/arc/snps_nsim/dts_fixup.h +++ b/soc/arc/snps_nsim/dts_fixup.h @@ -1,10 +1,10 @@ /* SoC level DTS fixup file */ /* CCM configuration */ -#define CONFIG_DCCM_BASE_ADDRESS DT_ARC_DCCM_80000000_BASE_ADDRESS -#define CONFIG_DCCM_SIZE (DT_ARC_DCCM_80000000_SIZE >> 10) +#define DT_DCCM_BASE_ADDRESS DT_ARC_DCCM_80000000_BASE_ADDRESS +#define DT_DCCM_SIZE (DT_ARC_DCCM_80000000_SIZE >> 10) -#define CONFIG_ICCM_BASE_ADDRESS ARC_ICCM_0_BASE_ADDRESS -#define CONFIG_ICCM_SIZE (ARC_ICCM_0_SIZE >> 10) +#define DT_ICCM_BASE_ADDRESS ARC_ICCM_0_BASE_ADDRESS +#define DT_ICCM_SIZE (ARC_ICCM_0_SIZE >> 10) /* End of SoC Level DTS fixup file */ diff --git a/soc/arc/snps_nsim/linker.ld b/soc/arc/snps_nsim/linker.ld index abb29ba8f84..ec7c1300178 100644 --- a/soc/arc/snps_nsim/linker.ld +++ b/soc/arc/snps_nsim/linker.ld @@ -12,18 +12,18 @@ /* Instruction Closely Coupled Memory (ICCM) base address and size */ -#if defined(CONFIG_ICCM_BASE_ADDRESS) && (CONFIG_ICCM_SIZE > 0) -#define ICCM_START CONFIG_ICCM_BASE_ADDRESS -#define ICCM_SIZE CONFIG_ICCM_SIZE +#if defined(DT_ICCM_BASE_ADDRESS) && (DT_ICCM_SIZE > 0) +#define ICCM_START DT_ICCM_BASE_ADDRESS +#define ICCM_SIZE DT_ICCM_SIZE #endif /* * DCCM base address and size. DCCM is the data memory. */ /* Data Closely Coupled Memory (DCCM) base address and size */ -#if defined(CONFIG_DCCM_BASE_ADDRESS) && (CONFIG_DCCM_SIZE > 0) -#define DCCM_START CONFIG_DCCM_BASE_ADDRESS -#define DCCM_SIZE CONFIG_DCCM_SIZE +#if defined(DT_DCCM_BASE_ADDRESS) && (DT_DCCM_SIZE > 0) +#define DCCM_START DT_DCCM_BASE_ADDRESS +#define DCCM_SIZE DT_DCCM_SIZE #endif #include diff --git a/soc/arm/arm/beetle/dts_fixup.h b/soc/arm/arm/beetle/dts_fixup.h index a122c1ff10d..5a3832bc951 100644 --- a/soc/arm/arm/beetle/dts_fixup.h +++ b/soc/arm/arm/beetle/dts_fixup.h @@ -1,45 +1,45 @@ /* SoC level DTS fixup file */ -#define CONFIG_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS +#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS /* CMSDK APB Timers */ -#define CMSDK_APB_TIMER0 DT_ARM_CMSDK_TIMER_40000000_BASE_ADDRESS -#define CMSDK_APB_TIMER_0_IRQ DT_ARM_CMSDK_TIMER_40000000_IRQ_0 +#define DT_CMSDK_APB_TIMER0 DT_ARM_CMSDK_TIMER_40000000_BASE_ADDRESS +#define DT_CMSDK_APB_TIMER_0_IRQ DT_ARM_CMSDK_TIMER_40000000_IRQ_0 -#define CMSDK_APB_TIMER1 DT_ARM_CMSDK_TIMER_40001000_BASE_ADDRESS -#define CMSDK_APB_TIMER_1_IRQ IRQ_TIMER1 DT_ARM_CMSDK_TIMER_40001000_IRQ_0 +#define DT_CMSDK_APB_TIMER1 DT_ARM_CMSDK_TIMER_40001000_BASE_ADDRESS +#define DT_CMSDK_APB_TIMER_1_IRQ IRQ_TIMER1 DT_ARM_CMSDK_TIMER_40001000_IRQ_0 /* CMSDK APB Dual Timer */ -#define CMSDK_APB_DTIMER DT_ARM_CMSDK_DTIMER_40002000_BASE_ADDRESS -#define CMSDK_APB_DUALTIMER_IRQ DT_ARM_CMSDK_DTIMER_40002000_IRQ_0 +#define DT_CMSDK_APB_DTIMER DT_ARM_CMSDK_DTIMER_40002000_BASE_ADDRESS +#define DT_CMSDK_APB_DUALTIMER_IRQ DT_ARM_CMSDK_DTIMER_40002000_IRQ_0 /* CMSDK APB Universal Asynchronous Receiver-Transmitter (UART) */ -#define CMSDK_APB_UART0 DT_ARM_CMSDK_UART_40004000_BASE_ADDRESS -#define CMSDK_APB_UART_0_IRQ DT_ARM_CMSDK_UART_40004000_IRQ_0 -#define CONFIG_UART_CMSDK_APB_PORT0_IRQ_PRI DT_ARM_CMSDK_UART_40004000_IRQ_0_PRIORITY -#define CONFIG_UART_CMSDK_APB_PORT0_BAUD_RATE DT_ARM_CMSDK_UART_40004000_CURRENT_SPEED -#define CONFIG_UART_CMSDK_APB_PORT0_NAME DT_ARM_CMSDK_UART_40004000_LABEL +#define DT_CMSDK_APB_UART0 DT_ARM_CMSDK_UART_40004000_BASE_ADDRESS +#define DT_CMSDK_APB_UART_0_IRQ DT_ARM_CMSDK_UART_40004000_IRQ_0 +#define DT_UART_CMSDK_APB_PORT0_IRQ_PRI DT_ARM_CMSDK_UART_40004000_IRQ_0_PRIORITY +#define DT_UART_CMSDK_APB_PORT0_BAUD_RATE DT_ARM_CMSDK_UART_40004000_CURRENT_SPEED +#define DT_UART_CMSDK_APB_PORT0_NAME DT_ARM_CMSDK_UART_40004000_LABEL -#define CMSDK_APB_UART1 DT_ARM_CMSDK_UART_40005000_BASE_ADDRESS -#define CMSDK_APB_UART_1_IRQ DT_ARM_CMSDK_UART_40005000_IRQ_0 -#define CONFIG_UART_CMSDK_APB_PORT1_IRQ_PRI DT_ARM_CMSDK_UART_40005000_IRQ_0_PRIORITY -#define CONFIG_UART_CMSDK_APB_PORT1_BAUD_RATE DT_ARM_CMSDK_UART_40005000_CURRENT_SPEED -#define CONFIG_UART_CMSDK_APB_PORT1_NAME DT_ARM_CMSDK_UART_40005000_LABEL +#define DT_CMSDK_APB_UART1 DT_ARM_CMSDK_UART_40005000_BASE_ADDRESS +#define DT_CMSDK_APB_UART_1_IRQ DT_ARM_CMSDK_UART_40005000_IRQ_0 +#define DT_UART_CMSDK_APB_PORT1_IRQ_PRI DT_ARM_CMSDK_UART_40005000_IRQ_0_PRIORITY +#define DT_UART_CMSDK_APB_PORT1_BAUD_RATE DT_ARM_CMSDK_UART_40005000_CURRENT_SPEED +#define DT_UART_CMSDK_APB_PORT1_NAME DT_ARM_CMSDK_UART_40005000_LABEL /* CMSDK APB Watchdog */ -#define CMSDK_APB_WDOG DT_ARM_CMSDK_WATCHDOG_40008000_BASE_ADDRESS +#define DT_CMSDK_APB_WDOG DT_ARM_CMSDK_WATCHDOG_40008000_BASE_ADDRESS /* CMSDK AHB General Purpose Input/Output (GPIO) */ -#define CMSDK_AHB_GPIO0 DT_ARM_CMSDK_GPIO_40010000_BASE_ADDRESS -#define IRQ_PORT0_ALL DT_ARM_CMSDK_GPIO_40010000_IRQ_0 +#define DT_CMSDK_AHB_GPIO0 DT_ARM_CMSDK_GPIO_40010000_BASE_ADDRESS +#define DT_IRQ_PORT0_ALL DT_ARM_CMSDK_GPIO_40010000_IRQ_0 -#define CMSDK_AHB_GPIO1 DT_ARM_CMSDK_GPIO_40011000_BASE_ADDRESS -#define IRQ_PORT1_ALL DT_ARM_CMSDK_GPIO_40011000_IRQ_0 +#define DT_CMSDK_AHB_GPIO1 DT_ARM_CMSDK_GPIO_40011000_BASE_ADDRESS +#define DT_IRQ_PORT1_ALL DT_ARM_CMSDK_GPIO_40011000_IRQ_0 -#define CMSDK_AHB_GPIO2 DT_ARM_CMSDK_GPIO_40012000_BASE_ADDRESS -#define IRQ_PORT2_ALL DT_ARM_CMSDK_GPIO_40012000_IRQ_0 +#define DT_CMSDK_AHB_GPIO2 DT_ARM_CMSDK_GPIO_40012000_BASE_ADDRESS +#define DT_IRQ_PORT2_ALL DT_ARM_CMSDK_GPIO_40012000_IRQ_0 -#define CMSDK_AHB_GPIO3 DT_ARM_CMSDK_GPIO_40013000_BASE_ADDRESS -#define IRQ_PORT3_ALL DT_ARM_CMSDK_GPIO_40013000_IRQ_0 +#define DT_CMSDK_AHB_GPIO3 DT_ARM_CMSDK_GPIO_40013000_BASE_ADDRESS +#define DT_IRQ_PORT3_ALL DT_ARM_CMSDK_GPIO_40013000_IRQ_0 /* End of SoC Level DTS fixup file */ diff --git a/soc/arm/atmel_sam/sam3x/dts_fixup.h b/soc/arm/atmel_sam/sam3x/dts_fixup.h index 181e5b36785..ab5cbc15248 100644 --- a/soc/arm/atmel_sam/sam3x/dts_fixup.h +++ b/soc/arm/atmel_sam/sam3x/dts_fixup.h @@ -6,38 +6,38 @@ /* SoC level DTS fixup file */ -#define CONFIG_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS +#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS -#define CONFIG_I2C_0_BASE_ADDRESS DT_ATMEL_SAM_I2C_TWI_4008C000_BASE_ADDRESS +#define DT_I2C_0_BASE_ADDRESS DT_ATMEL_SAM_I2C_TWI_4008C000_BASE_ADDRESS #define CONFIG_I2C_0_NAME DT_ATMEL_SAM_I2C_TWI_4008C000_LABEL -#define CONFIG_I2C_0_BITRATE DT_ATMEL_SAM_I2C_TWI_4008C000_CLOCK_FREQUENCY -#define CONFIG_I2C_0_IRQ DT_ATMEL_SAM_I2C_TWI_4008C000_IRQ_0 +#define DT_I2C_0_BITRATE DT_ATMEL_SAM_I2C_TWI_4008C000_CLOCK_FREQUENCY +#define DT_I2C_0_IRQ DT_ATMEL_SAM_I2C_TWI_4008C000_IRQ_0 #define CONFIG_I2C_0_IRQ_PRI DT_ATMEL_SAM_I2C_TWI_4008C000_IRQ_0_PRIORITY -#define CONFIG_I2C_0_PERIPHERAL_ID DT_ATMEL_SAM_I2C_TWI_4008C000_PERIPHERAL_ID -#define CONFIG_I2C_1_BASE_ADDRESS DT_ATMEL_SAM_I2C_TWI_40090000_BASE_ADDRESS +#define DT_I2C_0_PERIPHERAL_ID DT_ATMEL_SAM_I2C_TWI_4008C000_PERIPHERAL_ID +#define DT_I2C_1_BASE_ADDRESS DT_ATMEL_SAM_I2C_TWI_40090000_BASE_ADDRESS #define CONFIG_I2C_1_NAME DT_ATMEL_SAM_I2C_TWI_40090000_LABEL -#define CONFIG_I2C_1_BITRATE DT_ATMEL_SAM_I2C_TWI_40090000_CLOCK_FREQUENCY -#define CONFIG_I2C_1_IRQ DT_ATMEL_SAM_I2C_TWI_40090000_IRQ_0 +#define DT_I2C_1_BITRATE DT_ATMEL_SAM_I2C_TWI_40090000_CLOCK_FREQUENCY +#define DT_I2C_1_IRQ DT_ATMEL_SAM_I2C_TWI_40090000_IRQ_0 #define CONFIG_I2C_1_IRQ_PRI DT_ATMEL_SAM_I2C_TWI_40090000_IRQ_0_PRIORITY -#define CONFIG_I2C_1_PERIPHERAL_ID DT_ATMEL_SAM_I2C_TWI_40090000_PERIPHERAL_ID +#define DT_I2C_1_PERIPHERAL_ID DT_ATMEL_SAM_I2C_TWI_40090000_PERIPHERAL_ID -#define CONFIG_UART_SAM_PORT_0_NAME DT_ATMEL_SAM_UART_400E0800_LABEL -#define CONFIG_UART_SAM_PORT_0_BAUD_RATE DT_ATMEL_SAM_UART_400E0800_CURRENT_SPEED -#define CONFIG_UART_SAM_PORT_0_IRQ DT_ATMEL_SAM_UART_400E0800_IRQ_0 -#define CONFIG_UART_SAM_PORT_0_IRQ_PRIO DT_ATMEL_SAM_UART_400E0800_IRQ_0_PRIORITY +#define DT_UART_SAM_PORT_0_NAME DT_ATMEL_SAM_UART_400E0800_LABEL +#define DT_UART_SAM_PORT_0_BAUD_RATE DT_ATMEL_SAM_UART_400E0800_CURRENT_SPEED +#define DT_UART_SAM_PORT_0_IRQ DT_ATMEL_SAM_UART_400E0800_IRQ_0 +#define DT_UART_SAM_PORT_0_IRQ_PRIO DT_ATMEL_SAM_UART_400E0800_IRQ_0_PRIORITY -#define CONFIG_USART_SAM_PORT_0_NAME DT_ATMEL_SAM_USART_40098000_LABEL -#define CONFIG_USART_SAM_PORT_0_BAUD_RATE DT_ATMEL_SAM_USART_40098000_CURRENT_SPEED -#define CONFIG_USART_SAM_PORT_1_NAME DT_ATMEL_SAM_USART_4009C000_LABEL -#define CONFIG_USART_SAM_PORT_1_BAUD_RATE DT_ATMEL_SAM_USART_4009C000_CURRENT_SPEED -#define CONFIG_USART_SAM_PORT_2_NAME DT_ATMEL_SAM_USART_400A0000_LABEL -#define CONFIG_USART_SAM_PORT_2_BAUD_RATE DT_ATMEL_SAM_USART_400A0000_CURRENT_SPEED -#define CONFIG_USART_SAM_PORT_3_NAME DT_ATMEL_SAM_USART_400A4000_LABEL -#define CONFIG_USART_SAM_PORT_3_BAUD_RATE DT_ATMEL_SAM_USART_400A4000_CURRENT_SPEED +#define DT_USART_SAM_PORT_0_NAME DT_ATMEL_SAM_USART_40098000_LABEL +#define DT_USART_SAM_PORT_0_BAUD_RATE DT_ATMEL_SAM_USART_40098000_CURRENT_SPEED +#define DT_USART_SAM_PORT_1_NAME DT_ATMEL_SAM_USART_4009C000_LABEL +#define DT_USART_SAM_PORT_1_BAUD_RATE DT_ATMEL_SAM_USART_4009C000_CURRENT_SPEED +#define DT_USART_SAM_PORT_2_NAME DT_ATMEL_SAM_USART_400A0000_LABEL +#define DT_USART_SAM_PORT_2_BAUD_RATE DT_ATMEL_SAM_USART_400A0000_CURRENT_SPEED +#define DT_USART_SAM_PORT_3_NAME DT_ATMEL_SAM_USART_400A4000_LABEL +#define DT_USART_SAM_PORT_3_BAUD_RATE DT_ATMEL_SAM_USART_400A4000_CURRENT_SPEED -#define CONFIG_WDT_SAM_IRQ DT_ATMEL_SAM_WATCHDOG_400E1A50_IRQ_0 -#define CONFIG_WDT_SAM_IRQ_PRIORITY DT_ATMEL_SAM_WATCHDOG_400E1A50_IRQ_0_PRIORITY -#define CONFIG_WDT_SAM_LABEL DT_ATMEL_SAM_WATCHDOG_400E1A50_LABEL -#define CONFIG_WDT_SAM_BASE_ADDRESS DT_ATMEL_SAM_WATCHDOG_400E1A50_BASE_ADDRESS +#define DT_WDT_SAM_IRQ DT_ATMEL_SAM_WATCHDOG_400E1A50_IRQ_0 +#define DT_WDT_SAM_IRQ_PRIORITY DT_ATMEL_SAM_WATCHDOG_400E1A50_IRQ_0_PRIORITY +#define DT_WDT_SAM_LABEL DT_ATMEL_SAM_WATCHDOG_400E1A50_LABEL +#define DT_WDT_SAM_BASE_ADDRESS DT_ATMEL_SAM_WATCHDOG_400E1A50_BASE_ADDRESS /* End of SoC Level DTS fixup file */ diff --git a/soc/arm/atmel_sam/sam4s/dts_fixup.h b/soc/arm/atmel_sam/sam4s/dts_fixup.h index 1fa9413a706..b2c58857349 100644 --- a/soc/arm/atmel_sam/sam4s/dts_fixup.h +++ b/soc/arm/atmel_sam/sam4s/dts_fixup.h @@ -6,52 +6,52 @@ /* SoC level DTS fixup file */ -#define CONFIG_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS +#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS -#define CONFIG_GPIO_SAM_PORTA_LABEL DT_ATMEL_SAM_GPIO_400E0E00_LABEL -#define CONFIG_GPIO_SAM_PORTA_BASE_ADDRESS DT_ATMEL_SAM_GPIO_400E0E00_BASE_ADDRESS -#define CONFIG_GPIO_SAM_PORTA_IRQ DT_ATMEL_SAM_GPIO_400E0E00_IRQ_0 -#define CONFIG_GPIO_SAM_PORTA_IRQ_PRIO DT_ATMEL_SAM_GPIO_400E0E00_IRQ_0_PRIORITY -#define CONFIG_GPIO_SAM_PORTA_PERIPHERAL_ID DT_ATMEL_SAM_GPIO_400E0E00_PERIPHERAL_ID -#define CONFIG_GPIO_SAM_PORTB_LABEL DT_ATMEL_SAM_GPIO_400E1000_LABEL -#define CONFIG_GPIO_SAM_PORTB_BASE_ADDRESS DT_ATMEL_SAM_GPIO_400E1000_BASE_ADDRESS -#define CONFIG_GPIO_SAM_PORTB_IRQ DT_ATMEL_SAM_GPIO_400E1000_IRQ_0 -#define CONFIG_GPIO_SAM_PORTB_IRQ_PRIO DT_ATMEL_SAM_GPIO_400E1000_IRQ_0_PRIORITY -#define CONFIG_GPIO_SAM_PORTB_PERIPHERAL_ID DT_ATMEL_SAM_GPIO_400E1000_PERIPHERAL_ID -#define CONFIG_GPIO_SAM_PORTC_LABEL DT_ATMEL_SAM_GPIO_400E1200_LABEL -#define CONFIG_GPIO_SAM_PORTC_BASE_ADDRESS DT_ATMEL_SAM_GPIO_400E1200_BASE_ADDRESS -#define CONFIG_GPIO_SAM_PORTC_IRQ DT_ATMEL_SAM_GPIO_400E1200_IRQ_0 -#define CONFIG_GPIO_SAM_PORTC_IRQ_PRIO DT_ATMEL_SAM_GPIO_400E1200_IRQ_0_PRIORITY -#define CONFIG_GPIO_SAM_PORTC_PERIPHERAL_ID DT_ATMEL_SAM_GPIO_400E1200_PERIPHERAL_ID +#define DT_GPIO_SAM_PORTA_LABEL DT_ATMEL_SAM_GPIO_400E0E00_LABEL +#define DT_GPIO_SAM_PORTA_BASE_ADDRESS DT_ATMEL_SAM_GPIO_400E0E00_BASE_ADDRESS +#define DT_GPIO_SAM_PORTA_IRQ DT_ATMEL_SAM_GPIO_400E0E00_IRQ_0 +#define DT_GPIO_SAM_PORTA_IRQ_PRIO DT_ATMEL_SAM_GPIO_400E0E00_IRQ_0_PRIORITY +#define DT_GPIO_SAM_PORTA_PERIPHERAL_ID DT_ATMEL_SAM_GPIO_400E0E00_PERIPHERAL_ID +#define DT_GPIO_SAM_PORTB_LABEL DT_ATMEL_SAM_GPIO_400E1000_LABEL +#define DT_GPIO_SAM_PORTB_BASE_ADDRESS DT_ATMEL_SAM_GPIO_400E1000_BASE_ADDRESS +#define DT_GPIO_SAM_PORTB_IRQ DT_ATMEL_SAM_GPIO_400E1000_IRQ_0 +#define DT_GPIO_SAM_PORTB_IRQ_PRIO DT_ATMEL_SAM_GPIO_400E1000_IRQ_0_PRIORITY +#define DT_GPIO_SAM_PORTB_PERIPHERAL_ID DT_ATMEL_SAM_GPIO_400E1000_PERIPHERAL_ID +#define DT_GPIO_SAM_PORTC_LABEL DT_ATMEL_SAM_GPIO_400E1200_LABEL +#define DT_GPIO_SAM_PORTC_BASE_ADDRESS DT_ATMEL_SAM_GPIO_400E1200_BASE_ADDRESS +#define DT_GPIO_SAM_PORTC_IRQ DT_ATMEL_SAM_GPIO_400E1200_IRQ_0 +#define DT_GPIO_SAM_PORTC_IRQ_PRIO DT_ATMEL_SAM_GPIO_400E1200_IRQ_0_PRIORITY +#define DT_GPIO_SAM_PORTC_PERIPHERAL_ID DT_ATMEL_SAM_GPIO_400E1200_PERIPHERAL_ID -#define CONFIG_I2C_0_BASE_ADDRESS DT_ATMEL_SAM_I2C_TWI_40018000_BASE_ADDRESS +#define DT_I2C_0_BASE_ADDRESS DT_ATMEL_SAM_I2C_TWI_40018000_BASE_ADDRESS #define CONFIG_I2C_0_NAME DT_ATMEL_SAM_I2C_TWI_40018000_LABEL -#define CONFIG_I2C_0_BITRATE DT_ATMEL_SAM_I2C_TWI_40018000_CLOCK_FREQUENCY -#define CONFIG_I2C_0_IRQ DT_ATMEL_SAM_I2C_TWI_40018000_IRQ_0 +#define DT_I2C_0_BITRATE DT_ATMEL_SAM_I2C_TWI_40018000_CLOCK_FREQUENCY +#define DT_I2C_0_IRQ DT_ATMEL_SAM_I2C_TWI_40018000_IRQ_0 #define CONFIG_I2C_0_IRQ_PRI DT_ATMEL_SAM_I2C_TWI_40018000_IRQ_0_PRIORITY -#define CONFIG_I2C_0_PERIPHERAL_ID DT_ATMEL_SAM_I2C_TWI_40018000_PERIPHERAL_ID -#define CONFIG_I2C_1_BASE_ADDRESS DT_ATMEL_SAM_I2C_TWI_4001C000_BASE_ADDRESS +#define DT_I2C_0_PERIPHERAL_ID DT_ATMEL_SAM_I2C_TWI_40018000_PERIPHERAL_ID +#define DT_I2C_1_BASE_ADDRESS DT_ATMEL_SAM_I2C_TWI_4001C000_BASE_ADDRESS #define CONFIG_I2C_1_NAME DT_ATMEL_SAM_I2C_TWI_4001C000_LABEL -#define CONFIG_I2C_1_BITRATE DT_ATMEL_SAM_I2C_TWI_4001C000_CLOCK_FREQUENCY -#define CONFIG_I2C_1_IRQ DT_ATMEL_SAM_I2C_TWI_4001C000_IRQ_0 +#define DT_I2C_1_BITRATE DT_ATMEL_SAM_I2C_TWI_4001C000_CLOCK_FREQUENCY +#define DT_I2C_1_IRQ DT_ATMEL_SAM_I2C_TWI_4001C000_IRQ_0 #define CONFIG_I2C_1_IRQ_PRI DT_ATMEL_SAM_I2C_TWI_4001C000_IRQ_0_PRIORITY -#define CONFIG_I2C_1_PERIPHERAL_ID DT_ATMEL_SAM_I2C_TWI_4001C000_PERIPHERAL_ID +#define DT_I2C_1_PERIPHERAL_ID DT_ATMEL_SAM_I2C_TWI_4001C000_PERIPHERAL_ID -#define CONFIG_UART_SAM_PORT_0_NAME DT_ATMEL_SAM_UART_400E0600_LABEL -#define CONFIG_UART_SAM_PORT_0_BAUD_RATE DT_ATMEL_SAM_UART_400E0600_CURRENT_SPEED -#define CONFIG_UART_SAM_PORT_0_IRQ DT_ATMEL_SAM_UART_400E0600_IRQ_0 -#define CONFIG_UART_SAM_PORT_0_IRQ_PRIO DT_ATMEL_SAM_UART_400E0600_IRQ_0_PRIORITY -#define CONFIG_UART_SAM_PORT_1_NAME DT_ATMEL_SAM_UART_400E0800_LABEL -#define CONFIG_UART_SAM_PORT_1_BAUD_RATE DT_ATMEL_SAM_UART_400E0800_CURRENT_SPEED -#define CONFIG_UART_SAM_PORT_1_IRQ DT_ATMEL_SAM_UART_400E0800_IRQ_0 -#define CONFIG_UART_SAM_PORT_1_IRQ_PRIO DT_ATMEL_SAM_UART_400E0800_IRQ_0_PRIORITY -#define CONFIG_USART_SAM_PORT_0_NAME DT_ATMEL_SAM_USART_40024000_LABEL -#define CONFIG_USART_SAM_PORT_0_BAUD_RATE DT_ATMEL_SAM_USART_40024000_CURRENT_SPEED -#define CONFIG_USART_SAM_PORT_1_NAME DT_ATMEL_SAM_USART_40028000_LABEL -#define CONFIG_USART_SAM_PORT_1_BAUD_RATE DT_ATMEL_SAM_USART_40028000_CURRENT_SPEED +#define DT_UART_SAM_PORT_0_NAME DT_ATMEL_SAM_UART_400E0600_LABEL +#define DT_UART_SAM_PORT_0_BAUD_RATE DT_ATMEL_SAM_UART_400E0600_CURRENT_SPEED +#define DT_UART_SAM_PORT_0_IRQ DT_ATMEL_SAM_UART_400E0600_IRQ_0 +#define DT_UART_SAM_PORT_0_IRQ_PRIO DT_ATMEL_SAM_UART_400E0600_IRQ_0_PRIORITY +#define DT_UART_SAM_PORT_1_NAME DT_ATMEL_SAM_UART_400E0800_LABEL +#define DT_UART_SAM_PORT_1_BAUD_RATE DT_ATMEL_SAM_UART_400E0800_CURRENT_SPEED +#define DT_UART_SAM_PORT_1_IRQ DT_ATMEL_SAM_UART_400E0800_IRQ_0 +#define DT_UART_SAM_PORT_1_IRQ_PRIO DT_ATMEL_SAM_UART_400E0800_IRQ_0_PRIORITY +#define DT_USART_SAM_PORT_0_NAME DT_ATMEL_SAM_USART_40024000_LABEL +#define DT_USART_SAM_PORT_0_BAUD_RATE DT_ATMEL_SAM_USART_40024000_CURRENT_SPEED +#define DT_USART_SAM_PORT_1_NAME DT_ATMEL_SAM_USART_40028000_LABEL +#define DT_USART_SAM_PORT_1_BAUD_RATE DT_ATMEL_SAM_USART_40028000_CURRENT_SPEED -#define CONFIG_WDT_SAM_IRQ DT_ATMEL_SAM_WATCHDOG_400E1450_IRQ_0 -#define CONFIG_WDT_SAM_IRQ_PRIORITY DT_ATMEL_SAM_WATCHDOG_400E1450_IRQ_0_PRIORITY -#define CONFIG_WDT_SAM_LABEL DT_ATMEL_SAM_WATCHDOG_400E1450_LABEL -#define CONFIG_WDT_SAM_BASE_ADDRESS DT_ATMEL_SAM_WATCHDOG_400E1450_BASE_ADDRESS +#define DT_WDT_SAM_IRQ DT_ATMEL_SAM_WATCHDOG_400E1450_IRQ_0 +#define DT_WDT_SAM_IRQ_PRIORITY DT_ATMEL_SAM_WATCHDOG_400E1450_IRQ_0_PRIORITY +#define DT_WDT_SAM_LABEL DT_ATMEL_SAM_WATCHDOG_400E1450_LABEL +#define DT_WDT_SAM_BASE_ADDRESS DT_ATMEL_SAM_WATCHDOG_400E1450_BASE_ADDRESS /* End of SoC Level DTS fixup file */ diff --git a/soc/arm/atmel_sam/same70/dts_fixup.h b/soc/arm/atmel_sam/same70/dts_fixup.h index 5931ebdcc93..ad0813bc1dc 100644 --- a/soc/arm/atmel_sam/same70/dts_fixup.h +++ b/soc/arm/atmel_sam/same70/dts_fixup.h @@ -6,126 +6,126 @@ /* SoC level DTS fixup file */ -#define CONFIG_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS +#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS -#define CONFIG_GPIO_SAM_PORTA_LABEL DT_ATMEL_SAM_GPIO_400E0E00_LABEL -#define CONFIG_GPIO_SAM_PORTA_BASE_ADDRESS DT_ATMEL_SAM_GPIO_400E0E00_BASE_ADDRESS -#define CONFIG_GPIO_SAM_PORTA_IRQ DT_ATMEL_SAM_GPIO_400E0E00_IRQ_0 -#define CONFIG_GPIO_SAM_PORTA_IRQ_PRIO DT_ATMEL_SAM_GPIO_400E0E00_IRQ_0_PRIORITY -#define CONFIG_GPIO_SAM_PORTA_PERIPHERAL_ID DT_ATMEL_SAM_GPIO_400E0E00_PERIPHERAL_ID -#define CONFIG_GPIO_SAM_PORTB_LABEL DT_ATMEL_SAM_GPIO_400E1000_LABEL -#define CONFIG_GPIO_SAM_PORTB_BASE_ADDRESS DT_ATMEL_SAM_GPIO_400E1000_BASE_ADDRESS -#define CONFIG_GPIO_SAM_PORTB_IRQ DT_ATMEL_SAM_GPIO_400E1000_IRQ_0 -#define CONFIG_GPIO_SAM_PORTB_IRQ_PRIO DT_ATMEL_SAM_GPIO_400E1000_IRQ_0_PRIORITY -#define CONFIG_GPIO_SAM_PORTB_PERIPHERAL_ID DT_ATMEL_SAM_GPIO_400E1000_PERIPHERAL_ID -#define CONFIG_GPIO_SAM_PORTC_LABEL DT_ATMEL_SAM_GPIO_400E1200_LABEL -#define CONFIG_GPIO_SAM_PORTC_BASE_ADDRESS DT_ATMEL_SAM_GPIO_400E1200_BASE_ADDRESS -#define CONFIG_GPIO_SAM_PORTC_IRQ DT_ATMEL_SAM_GPIO_400E1200_IRQ_0 -#define CONFIG_GPIO_SAM_PORTC_IRQ_PRIO DT_ATMEL_SAM_GPIO_400E1200_IRQ_0_PRIORITY -#define CONFIG_GPIO_SAM_PORTC_PERIPHERAL_ID DT_ATMEL_SAM_GPIO_400E1200_PERIPHERAL_ID -#define CONFIG_GPIO_SAM_PORTD_LABEL DT_ATMEL_SAM_GPIO_400E1400_LABEL -#define CONFIG_GPIO_SAM_PORTD_BASE_ADDRESS DT_ATMEL_SAM_GPIO_400E1400_BASE_ADDRESS -#define CONFIG_GPIO_SAM_PORTD_IRQ DT_ATMEL_SAM_GPIO_400E1400_IRQ_0 -#define CONFIG_GPIO_SAM_PORTD_IRQ_PRIO DT_ATMEL_SAM_GPIO_400E1400_IRQ_0_PRIORITY -#define CONFIG_GPIO_SAM_PORTD_PERIPHERAL_ID DT_ATMEL_SAM_GPIO_400E1400_PERIPHERAL_ID -#define CONFIG_GPIO_SAM_PORTE_LABEL DT_ATMEL_SAM_GPIO_400E1600_LABEL -#define CONFIG_GPIO_SAM_PORTE_BASE_ADDRESS DT_ATMEL_SAM_GPIO_400E1600_BASE_ADDRESS -#define CONFIG_GPIO_SAM_PORTE_IRQ DT_ATMEL_SAM_GPIO_400E1600_IRQ_0 -#define CONFIG_GPIO_SAM_PORTE_IRQ_PRIO DT_ATMEL_SAM_GPIO_400E1600_IRQ_0_PRIORITY -#define CONFIG_GPIO_SAM_PORTE_PERIPHERAL_ID DT_ATMEL_SAM_GPIO_400E1600_PERIPHERAL_ID +#define DT_GPIO_SAM_PORTA_LABEL DT_ATMEL_SAM_GPIO_400E0E00_LABEL +#define DT_GPIO_SAM_PORTA_BASE_ADDRESS DT_ATMEL_SAM_GPIO_400E0E00_BASE_ADDRESS +#define DT_GPIO_SAM_PORTA_IRQ DT_ATMEL_SAM_GPIO_400E0E00_IRQ_0 +#define DT_GPIO_SAM_PORTA_IRQ_PRIO DT_ATMEL_SAM_GPIO_400E0E00_IRQ_0_PRIORITY +#define DT_GPIO_SAM_PORTA_PERIPHERAL_ID DT_ATMEL_SAM_GPIO_400E0E00_PERIPHERAL_ID +#define DT_GPIO_SAM_PORTB_LABEL DT_ATMEL_SAM_GPIO_400E1000_LABEL +#define DT_GPIO_SAM_PORTB_BASE_ADDRESS DT_ATMEL_SAM_GPIO_400E1000_BASE_ADDRESS +#define DT_GPIO_SAM_PORTB_IRQ DT_ATMEL_SAM_GPIO_400E1000_IRQ_0 +#define DT_GPIO_SAM_PORTB_IRQ_PRIO DT_ATMEL_SAM_GPIO_400E1000_IRQ_0_PRIORITY +#define DT_GPIO_SAM_PORTB_PERIPHERAL_ID DT_ATMEL_SAM_GPIO_400E1000_PERIPHERAL_ID +#define DT_GPIO_SAM_PORTC_LABEL DT_ATMEL_SAM_GPIO_400E1200_LABEL +#define DT_GPIO_SAM_PORTC_BASE_ADDRESS DT_ATMEL_SAM_GPIO_400E1200_BASE_ADDRESS +#define DT_GPIO_SAM_PORTC_IRQ DT_ATMEL_SAM_GPIO_400E1200_IRQ_0 +#define DT_GPIO_SAM_PORTC_IRQ_PRIO DT_ATMEL_SAM_GPIO_400E1200_IRQ_0_PRIORITY +#define DT_GPIO_SAM_PORTC_PERIPHERAL_ID DT_ATMEL_SAM_GPIO_400E1200_PERIPHERAL_ID +#define DT_GPIO_SAM_PORTD_LABEL DT_ATMEL_SAM_GPIO_400E1400_LABEL +#define DT_GPIO_SAM_PORTD_BASE_ADDRESS DT_ATMEL_SAM_GPIO_400E1400_BASE_ADDRESS +#define DT_GPIO_SAM_PORTD_IRQ DT_ATMEL_SAM_GPIO_400E1400_IRQ_0 +#define DT_GPIO_SAM_PORTD_IRQ_PRIO DT_ATMEL_SAM_GPIO_400E1400_IRQ_0_PRIORITY +#define DT_GPIO_SAM_PORTD_PERIPHERAL_ID DT_ATMEL_SAM_GPIO_400E1400_PERIPHERAL_ID +#define DT_GPIO_SAM_PORTE_LABEL DT_ATMEL_SAM_GPIO_400E1600_LABEL +#define DT_GPIO_SAM_PORTE_BASE_ADDRESS DT_ATMEL_SAM_GPIO_400E1600_BASE_ADDRESS +#define DT_GPIO_SAM_PORTE_IRQ DT_ATMEL_SAM_GPIO_400E1600_IRQ_0 +#define DT_GPIO_SAM_PORTE_IRQ_PRIO DT_ATMEL_SAM_GPIO_400E1600_IRQ_0_PRIORITY +#define DT_GPIO_SAM_PORTE_PERIPHERAL_ID DT_ATMEL_SAM_GPIO_400E1600_PERIPHERAL_ID -#define CONFIG_I2C_0_BASE_ADDRESS DT_ATMEL_SAM_I2C_TWIHS_40018000_BASE_ADDRESS +#define DT_I2C_0_BASE_ADDRESS DT_ATMEL_SAM_I2C_TWIHS_40018000_BASE_ADDRESS #define CONFIG_I2C_0_NAME DT_ATMEL_SAM_I2C_TWIHS_40018000_LABEL -#define CONFIG_I2C_0_BITRATE DT_ATMEL_SAM_I2C_TWIHS_40018000_CLOCK_FREQUENCY -#define CONFIG_I2C_0_IRQ DT_ATMEL_SAM_I2C_TWIHS_40018000_IRQ_0 +#define DT_I2C_0_BITRATE DT_ATMEL_SAM_I2C_TWIHS_40018000_CLOCK_FREQUENCY +#define DT_I2C_0_IRQ DT_ATMEL_SAM_I2C_TWIHS_40018000_IRQ_0 #define CONFIG_I2C_0_IRQ_PRI DT_ATMEL_SAM_I2C_TWIHS_40018000_IRQ_0_PRIORITY -#define CONFIG_I2C_0_PERIPHERAL_ID DT_ATMEL_SAM_I2C_TWIHS_40018000_PERIPHERAL_ID +#define DT_I2C_0_PERIPHERAL_ID DT_ATMEL_SAM_I2C_TWIHS_40018000_PERIPHERAL_ID -#define CONFIG_I2C_1_BASE_ADDRESS DT_ATMEL_SAM_I2C_TWIHS_4001C000_BASE_ADDRESS +#define DT_I2C_1_BASE_ADDRESS DT_ATMEL_SAM_I2C_TWIHS_4001C000_BASE_ADDRESS #define CONFIG_I2C_1_NAME DT_ATMEL_SAM_I2C_TWIHS_4001C000_LABEL -#define CONFIG_I2C_1_BITRATE DT_ATMEL_SAM_I2C_TWIHS_4001C000_CLOCK_FREQUENCY -#define CONFIG_I2C_1_IRQ DT_ATMEL_SAM_I2C_TWIHS_4001C000_IRQ_0 +#define DT_I2C_1_BITRATE DT_ATMEL_SAM_I2C_TWIHS_4001C000_CLOCK_FREQUENCY +#define DT_I2C_1_IRQ DT_ATMEL_SAM_I2C_TWIHS_4001C000_IRQ_0 #define CONFIG_I2C_1_IRQ_PRI DT_ATMEL_SAM_I2C_TWIHS_4001C000_IRQ_0_PRIORITY -#define CONFIG_I2C_1_PERIPHERAL_ID DT_ATMEL_SAM_I2C_TWIHS_4001C000_PERIPHERAL_ID +#define DT_I2C_1_PERIPHERAL_ID DT_ATMEL_SAM_I2C_TWIHS_4001C000_PERIPHERAL_ID -#define CONFIG_I2C_2_BASE_ADDRESS DT_ATMEL_SAM_I2C_TWIHS_40060000_BASE_ADDRESS +#define DT_I2C_2_BASE_ADDRESS DT_ATMEL_SAM_I2C_TWIHS_40060000_BASE_ADDRESS #define CONFIG_I2C_2_NAME DT_ATMEL_SAM_I2C_TWIHS_40060000_LABEL -#define CONFIG_I2C_2_BITRATE DT_ATMEL_SAM_I2C_TWIHS_40060000_CLOCK_FREQUENCY -#define CONFIG_I2C_2_IRQ DT_ATMEL_SAM_I2C_TWIHS_40060000_IRQ_0 +#define DT_I2C_2_BITRATE DT_ATMEL_SAM_I2C_TWIHS_40060000_CLOCK_FREQUENCY +#define DT_I2C_2_IRQ DT_ATMEL_SAM_I2C_TWIHS_40060000_IRQ_0 #define CONFIG_I2C_2_IRQ_PRI DT_ATMEL_SAM_I2C_TWIHS_40060000_IRQ_0_PRIORITY -#define CONFIG_I2C_2_PERIPHERAL_ID DT_ATMEL_SAM_I2C_TWIHS_40060000_PERIPHERAL_ID +#define DT_I2C_2_PERIPHERAL_ID DT_ATMEL_SAM_I2C_TWIHS_40060000_PERIPHERAL_ID -#define CONFIG_SPI_0_BASE_ADDRESS DT_ATMEL_SAM_SPI_40008000_BASE_ADDRESS +#define DT_SPI_0_BASE_ADDRESS DT_ATMEL_SAM_SPI_40008000_BASE_ADDRESS #define CONFIG_SPI_0_NAME DT_ATMEL_SAM_SPI_40008000_LABEL -#define CONFIG_SPI_0_IRQ DT_ATMEL_SAM_SPI_40008000_IRQ_0 +#define DT_SPI_0_IRQ DT_ATMEL_SAM_SPI_40008000_IRQ_0 #define CONFIG_SPI_0_IRQ_PRI DT_ATMEL_SAM_SPI_40008000_IRQ_0_PRIORITY -#define CONFIG_SPI_0_PERIPHERAL_ID DT_ATMEL_SAM_SPI_40008000_PERIPHERAL_ID +#define DT_SPI_0_PERIPHERAL_ID DT_ATMEL_SAM_SPI_40008000_PERIPHERAL_ID -#define CONFIG_SPI_1_BASE_ADDRESS DT_ATMEL_SAM_SPI_40058000_BASE_ADDRESS +#define DT_SPI_1_BASE_ADDRESS DT_ATMEL_SAM_SPI_40058000_BASE_ADDRESS #define CONFIG_SPI_1_NAME DT_ATMEL_SAM_SPI_40058000_LABEL -#define CONFIG_SPI_1_IRQ DT_ATMEL_SAM_SPI_40058000_IRQ_0 +#define DT_SPI_1_IRQ DT_ATMEL_SAM_SPI_40058000_IRQ_0 #define CONFIG_SPI_1_IRQ_PRI DT_ATMEL_SAM_SPI_40058000_IRQ_0_PRIORITY -#define CONFIG_SPI_1_PERIPHERAL_ID DT_ATMEL_SAM_SPI_40058000_PERIPHERAL_ID +#define DT_SPI_1_PERIPHERAL_ID DT_ATMEL_SAM_SPI_40058000_PERIPHERAL_ID -#define CONFIG_UART_SAM_PORT_0_NAME DT_ATMEL_SAM_UART_400E0800_LABEL -#define CONFIG_UART_SAM_PORT_0_BAUD_RATE DT_ATMEL_SAM_UART_400E0800_CURRENT_SPEED -#define CONFIG_UART_SAM_PORT_0_IRQ DT_ATMEL_SAM_UART_400E0800_IRQ_0 -#define CONFIG_UART_SAM_PORT_0_IRQ_PRIO DT_ATMEL_SAM_UART_400E0800_IRQ_0_PRIORITY -#define CONFIG_UART_SAM_PORT_1_NAME DT_ATMEL_SAM_UART_400E0A00_LABEL -#define CONFIG_UART_SAM_PORT_1_BAUD_RATE DT_ATMEL_SAM_UART_400E0A00_CURRENT_SPEED -#define CONFIG_UART_SAM_PORT_1_IRQ DT_ATMEL_SAM_UART_400E0A00_IRQ_0 -#define CONFIG_UART_SAM_PORT_1_IRQ_PRIO DT_ATMEL_SAM_UART_400E0A00_IRQ_0_PRIORITY -#define CONFIG_UART_SAM_PORT_2_NAME DT_ATMEL_SAM_UART_400E1A00_LABEL -#define CONFIG_UART_SAM_PORT_2_BAUD_RATE DT_ATMEL_SAM_UART_400E1A00_CURRENT_SPEED -#define CONFIG_UART_SAM_PORT_2_IRQ DT_ATMEL_SAM_UART_400E1A00_IRQ_0 -#define CONFIG_UART_SAM_PORT_2_IRQ_PRIO DT_ATMEL_SAM_UART_400E1A00_IRQ_0_PRIORITY -#define CONFIG_UART_SAM_PORT_3_NAME DT_ATMEL_SAM_UART_400E1C00_LABEL -#define CONFIG_UART_SAM_PORT_3_BAUD_RATE DT_ATMEL_SAM_UART_400E1C00_CURRENT_SPEED -#define CONFIG_UART_SAM_PORT_3_IRQ DT_ATMEL_SAM_UART_400E1C00_IRQ_0 -#define CONFIG_UART_SAM_PORT_3_IRQ_PRIO DT_ATMEL_SAM_UART_400E1C00_IRQ_0_PRIORITY -#define CONFIG_UART_SAM_PORT_4_NAME DT_ATMEL_SAM_UART_400E1E00_LABEL -#define CONFIG_UART_SAM_PORT_4_BAUD_RATE DT_ATMEL_SAM_UART_400E1E00_CURRENT_SPEED -#define CONFIG_UART_SAM_PORT_4_IRQ DT_ATMEL_SAM_UART_400E1E00_IRQ_0 -#define CONFIG_UART_SAM_PORT_4_IRQ_PRIO DT_ATMEL_SAM_UART_400E1E00_IRQ_0_PRIORITY -#define CONFIG_USART_SAM_PORT_0_NAME DT_ATMEL_SAM_USART_40024000_LABEL -#define CONFIG_USART_SAM_PORT_0_BAUD_RATE DT_ATMEL_SAM_USART_40024000_CURRENT_SPEED -#define CONFIG_USART_SAM_PORT_0_IRQ DT_ATMEL_SAM_USART_40024000_IRQ_0 -#define CONFIG_USART_SAM_PORT_0_IRQ_PRIO DT_ATMEL_SAM_USART_40024000_IRQ_0_PRIORITY -#define CONFIG_USART_SAM_PORT_0_PERIPHERAL_ID DT_ATMEL_SAM_USART_40024000_PERIPHERAL_ID -#define CONFIG_USART_SAM_PORT_1_NAME DT_ATMEL_SAM_USART_40028000_LABEL -#define CONFIG_USART_SAM_PORT_1_BAUD_RATE DT_ATMEL_SAM_USART_40028000_CURRENT_SPEED -#define CONFIG_USART_SAM_PORT_1_IRQ DT_ATMEL_SAM_USART_40028000_IRQ_0 -#define CONFIG_USART_SAM_PORT_1_IRQ_PRIO DT_ATMEL_SAM_USART_40028000_IRQ_0_PRIORITY -#define CONFIG_USART_SAM_PORT_1_PERIPHERAL_ID DT_ATMEL_SAM_USART_40028000_PERIPHERAL_ID -#define CONFIG_USART_SAM_PORT_2_NAME DT_ATMEL_SAM_USART_4002C000_LABEL -#define CONFIG_USART_SAM_PORT_2_BAUD_RATE DT_ATMEL_SAM_USART_4002C000_CURRENT_SPEED -#define CONFIG_USART_SAM_PORT_2_IRQ DT_ATMEL_SAM_USART_4002C000_IRQ_0 -#define CONFIG_USART_SAM_PORT_2_IRQ_PRIO DT_ATMEL_SAM_USART_4002C000_IRQ_0_PRIORITY -#define CONFIG_USART_SAM_PORT_2_PERIPHERAL_ID DT_ATMEL_SAM_USART_4002C000_PERIPHERAL_ID +#define DT_UART_SAM_PORT_0_NAME DT_ATMEL_SAM_UART_400E0800_LABEL +#define DT_UART_SAM_PORT_0_BAUD_RATE DT_ATMEL_SAM_UART_400E0800_CURRENT_SPEED +#define DT_UART_SAM_PORT_0_IRQ DT_ATMEL_SAM_UART_400E0800_IRQ_0 +#define DT_UART_SAM_PORT_0_IRQ_PRIO DT_ATMEL_SAM_UART_400E0800_IRQ_0_PRIORITY +#define DT_UART_SAM_PORT_1_NAME DT_ATMEL_SAM_UART_400E0A00_LABEL +#define DT_UART_SAM_PORT_1_BAUD_RATE DT_ATMEL_SAM_UART_400E0A00_CURRENT_SPEED +#define DT_UART_SAM_PORT_1_IRQ DT_ATMEL_SAM_UART_400E0A00_IRQ_0 +#define DT_UART_SAM_PORT_1_IRQ_PRIO DT_ATMEL_SAM_UART_400E0A00_IRQ_0_PRIORITY +#define DT_UART_SAM_PORT_2_NAME DT_ATMEL_SAM_UART_400E1A00_LABEL +#define DT_UART_SAM_PORT_2_BAUD_RATE DT_ATMEL_SAM_UART_400E1A00_CURRENT_SPEED +#define DT_UART_SAM_PORT_2_IRQ DT_ATMEL_SAM_UART_400E1A00_IRQ_0 +#define DT_UART_SAM_PORT_2_IRQ_PRIO DT_ATMEL_SAM_UART_400E1A00_IRQ_0_PRIORITY +#define DT_UART_SAM_PORT_3_NAME DT_ATMEL_SAM_UART_400E1C00_LABEL +#define DT_UART_SAM_PORT_3_BAUD_RATE DT_ATMEL_SAM_UART_400E1C00_CURRENT_SPEED +#define DT_UART_SAM_PORT_3_IRQ DT_ATMEL_SAM_UART_400E1C00_IRQ_0 +#define DT_UART_SAM_PORT_3_IRQ_PRIO DT_ATMEL_SAM_UART_400E1C00_IRQ_0_PRIORITY +#define DT_UART_SAM_PORT_4_NAME DT_ATMEL_SAM_UART_400E1E00_LABEL +#define DT_UART_SAM_PORT_4_BAUD_RATE DT_ATMEL_SAM_UART_400E1E00_CURRENT_SPEED +#define DT_UART_SAM_PORT_4_IRQ DT_ATMEL_SAM_UART_400E1E00_IRQ_0 +#define DT_UART_SAM_PORT_4_IRQ_PRIO DT_ATMEL_SAM_UART_400E1E00_IRQ_0_PRIORITY +#define DT_USART_SAM_PORT_0_NAME DT_ATMEL_SAM_USART_40024000_LABEL +#define DT_USART_SAM_PORT_0_BAUD_RATE DT_ATMEL_SAM_USART_40024000_CURRENT_SPEED +#define DT_USART_SAM_PORT_0_IRQ DT_ATMEL_SAM_USART_40024000_IRQ_0 +#define DT_USART_SAM_PORT_0_IRQ_PRIO DT_ATMEL_SAM_USART_40024000_IRQ_0_PRIORITY +#define DT_USART_SAM_PORT_0_PERIPHERAL_ID DT_ATMEL_SAM_USART_40024000_PERIPHERAL_ID +#define DT_USART_SAM_PORT_1_NAME DT_ATMEL_SAM_USART_40028000_LABEL +#define DT_USART_SAM_PORT_1_BAUD_RATE DT_ATMEL_SAM_USART_40028000_CURRENT_SPEED +#define DT_USART_SAM_PORT_1_IRQ DT_ATMEL_SAM_USART_40028000_IRQ_0 +#define DT_USART_SAM_PORT_1_IRQ_PRIO DT_ATMEL_SAM_USART_40028000_IRQ_0_PRIORITY +#define DT_USART_SAM_PORT_1_PERIPHERAL_ID DT_ATMEL_SAM_USART_40028000_PERIPHERAL_ID +#define DT_USART_SAM_PORT_2_NAME DT_ATMEL_SAM_USART_4002C000_LABEL +#define DT_USART_SAM_PORT_2_BAUD_RATE DT_ATMEL_SAM_USART_4002C000_CURRENT_SPEED +#define DT_USART_SAM_PORT_2_IRQ DT_ATMEL_SAM_USART_4002C000_IRQ_0 +#define DT_USART_SAM_PORT_2_IRQ_PRIO DT_ATMEL_SAM_USART_4002C000_IRQ_0_PRIORITY +#define DT_USART_SAM_PORT_2_PERIPHERAL_ID DT_ATMEL_SAM_USART_4002C000_PERIPHERAL_ID -#define CONFIG_ADC_0_BASE_ADDRESS DT_ATMEL_SAM_AFEC_4003C000_BASE_ADDRESS -#define CONFIG_ADC_0_IRQ DT_ATMEL_SAM_AFEC_4003C000_IRQ_0 +#define DT_ADC_0_BASE_ADDRESS DT_ATMEL_SAM_AFEC_4003C000_BASE_ADDRESS +#define DT_ADC_0_IRQ DT_ATMEL_SAM_AFEC_4003C000_IRQ_0 #define CONFIG_ADC_0_IRQ_PRI DT_ATMEL_SAM_AFEC_4003C000_IRQ_0_PRIORITY #define CONFIG_ADC_0_NAME DT_ATMEL_SAM_AFEC_4003C000_LABEL -#define CONFIG_ADC_0_PERIPHERAL_ID DT_ATMEL_SAM_AFEC_4003C000_PERIPHERAL_ID +#define DT_ADC_0_PERIPHERAL_ID DT_ATMEL_SAM_AFEC_4003C000_PERIPHERAL_ID -#define CONFIG_ADC_1_BASE_ADDRESS DT_ATMEL_SAM_AFEC_40064000_BASE_ADDRESS -#define CONFIG_ADC_1_IRQ DT_ATMEL_SAM_AFEC_40064000_IRQ_0 +#define DT_ADC_1_BASE_ADDRESS DT_ATMEL_SAM_AFEC_40064000_BASE_ADDRESS +#define DT_ADC_1_IRQ DT_ATMEL_SAM_AFEC_40064000_IRQ_0 #define CONFIG_ADC_1_IRQ_PRI DT_ATMEL_SAM_AFEC_40064000_IRQ_0_PRIORITY #define CONFIG_ADC_1_NAME DT_ATMEL_SAM_AFEC_40064000_LABEL -#define CONFIG_ADC_1_PERIPHERAL_ID DT_ATMEL_SAM_AFEC_40064000_PERIPHERAL_ID +#define DT_ADC_1_PERIPHERAL_ID DT_ATMEL_SAM_AFEC_40064000_PERIPHERAL_ID -#define CONFIG_WDT_SAM_IRQ DT_ATMEL_SAM_WATCHDOG_400E1850_IRQ_0 -#define CONFIG_WDT_SAM_IRQ_PRIORITY DT_ATMEL_SAM_WATCHDOG_400E1850_IRQ_0_PRIORITY -#define CONFIG_WDT_SAM_LABEL DT_ATMEL_SAM_WATCHDOG_400E1850_LABEL -#define CONFIG_WDT_SAM_BASE_ADDRESS DT_ATMEL_SAM_WATCHDOG_400E1850_BASE_ADDRESS +#define DT_WDT_SAM_IRQ DT_ATMEL_SAM_WATCHDOG_400E1850_IRQ_0 +#define DT_WDT_SAM_IRQ_PRIORITY DT_ATMEL_SAM_WATCHDOG_400E1850_IRQ_0_PRIORITY +#define DT_WDT_SAM_LABEL DT_ATMEL_SAM_WATCHDOG_400E1850_LABEL +#define DT_WDT_SAM_BASE_ADDRESS DT_ATMEL_SAM_WATCHDOG_400E1850_BASE_ADDRESS -#define CONFIG_USBHS_IRQ DT_ATMEL_SAM_USBHS_40038000_IRQ_0 -#define CONFIG_USBHS_IRQ_PRI DT_ATMEL_SAM_USBHS_40038000_IRQ_0_PRIORITY -#define CONFIG_USBHS_MAXIMUM_SPEED DT_ATMEL_SAM_USBHS_40038000_MAXIMUM_SPEED -#define CONFIG_USBHS_NUM_BIDIR_EP DT_ATMEL_SAM_USBHS_40038000_NUM_BIDIR_ENDPOINTS -#define CONFIG_USBHS_PERIPHERAL_ID DT_ATMEL_SAM_USBHS_40038000_PERIPHERAL_ID -#define CONFIG_USBHS_RAM_BASE_ADDRESS DT_ATMEL_SAM_USBHS_40038000_RAM_0 +#define DT_USBHS_IRQ DT_ATMEL_SAM_USBHS_40038000_IRQ_0 +#define DT_USBHS_IRQ_PRI DT_ATMEL_SAM_USBHS_40038000_IRQ_0_PRIORITY +#define DT_USBHS_MAXIMUM_SPEED DT_ATMEL_SAM_USBHS_40038000_MAXIMUM_SPEED +#define DT_USBHS_NUM_BIDIR_EP DT_ATMEL_SAM_USBHS_40038000_NUM_BIDIR_ENDPOINTS +#define DT_USBHS_PERIPHERAL_ID DT_ATMEL_SAM_USBHS_40038000_PERIPHERAL_ID +#define DT_USBHS_RAM_BASE_ADDRESS DT_ATMEL_SAM_USBHS_40038000_RAM_0 /* End of SoC Level DTS fixup file */ diff --git a/soc/arm/atmel_sam0/samd20/dts_fixup.h b/soc/arm/atmel_sam0/samd20/dts_fixup.h index 056b1e7718c..fde2a0752f9 100644 --- a/soc/arm/atmel_sam0/samd20/dts_fixup.h +++ b/soc/arm/atmel_sam0/samd20/dts_fixup.h @@ -1,103 +1,103 @@ /* SoC level DTS fixup file */ -#define FLASH_DEV_BASE_ADDRESS DT_ATMEL_SAM0_NVMCTRL_41004000_BASE_ADDRESS_0 -#define FLASH_DEV_NAME DT_ATMEL_SAM0_NVMCTRL_41004000_LABEL +#define DT_FLASH_DEV_BASE_ADDRESS DT_ATMEL_SAM0_NVMCTRL_41004000_BASE_ADDRESS_0 +#define DT_FLASH_DEV_NAME DT_ATMEL_SAM0_NVMCTRL_41004000_LABEL -#define CONFIG_GPIO_SAM0_PORTA_LABEL DT_ATMEL_SAM0_GPIO_41004400_LABEL -#define CONFIG_GPIO_SAM0_PORTA_BASE_ADDRESS DT_ATMEL_SAM0_GPIO_41004400_BASE_ADDRESS +#define DT_GPIO_SAM0_PORTA_LABEL DT_ATMEL_SAM0_GPIO_41004400_LABEL +#define DT_GPIO_SAM0_PORTA_BASE_ADDRESS DT_ATMEL_SAM0_GPIO_41004400_BASE_ADDRESS -#define CONFIG_GPIO_SAM0_PORTB_LABEL DT_ATMEL_SAM0_GPIO_41004480_LABEL -#define CONFIG_GPIO_SAM0_PORTB_BASE_ADDRESS DT_ATMEL_SAM0_GPIO_41004480_BASE_ADDRESS +#define DT_GPIO_SAM0_PORTB_LABEL DT_ATMEL_SAM0_GPIO_41004480_LABEL +#define DT_GPIO_SAM0_PORTB_BASE_ADDRESS DT_ATMEL_SAM0_GPIO_41004480_BASE_ADDRESS -#define CONFIG_UART_SAM0_SERCOM0_CURRENT_SPEED DT_ATMEL_SAM0_UART_42000800_CURRENT_SPEED -#define CONFIG_UART_SAM0_SERCOM0_IRQ DT_ATMEL_SAM0_UART_42000800_IRQ_0 -#define CONFIG_UART_SAM0_SERCOM0_IRQ_PRIORITY DT_ATMEL_SAM0_UART_42000800_IRQ_0_PRIORITY -#define CONFIG_UART_SAM0_SERCOM0_LABEL DT_ATMEL_SAM0_UART_42000800_LABEL -#define CONFIG_UART_SAM0_SERCOM0_BASE_ADDRESS DT_ATMEL_SAM0_UART_42000800_BASE_ADDRESS -#define CONFIG_UART_SAM0_SERCOM0_RXPO DT_ATMEL_SAM0_UART_42000800_RXPO -#define CONFIG_UART_SAM0_SERCOM0_TXPO DT_ATMEL_SAM0_UART_42000800_TXPO +#define DT_UART_SAM0_SERCOM0_CURRENT_SPEED DT_ATMEL_SAM0_UART_42000800_CURRENT_SPEED +#define DT_UART_SAM0_SERCOM0_IRQ DT_ATMEL_SAM0_UART_42000800_IRQ_0 +#define DT_UART_SAM0_SERCOM0_IRQ_PRIORITY DT_ATMEL_SAM0_UART_42000800_IRQ_0_PRIORITY +#define DT_UART_SAM0_SERCOM0_LABEL DT_ATMEL_SAM0_UART_42000800_LABEL +#define DT_UART_SAM0_SERCOM0_BASE_ADDRESS DT_ATMEL_SAM0_UART_42000800_BASE_ADDRESS +#define DT_UART_SAM0_SERCOM0_RXPO DT_ATMEL_SAM0_UART_42000800_RXPO +#define DT_UART_SAM0_SERCOM0_TXPO DT_ATMEL_SAM0_UART_42000800_TXPO -#define CONFIG_UART_SAM0_SERCOM1_CURRENT_SPEED DT_ATMEL_SAM0_UART_42000C00_CURRENT_SPEED -#define CONFIG_UART_SAM0_SERCOM1_IRQ DT_ATMEL_SAM0_UART_42000C00_IRQ_0 -#define CONFIG_UART_SAM0_SERCOM1_IRQ_PRIORITY DT_ATMEL_SAM0_UART_42000C00_IRQ_0_PRIORITY -#define CONFIG_UART_SAM0_SERCOM1_LABEL DT_ATMEL_SAM0_UART_42000C00_LABEL -#define CONFIG_UART_SAM0_SERCOM1_BASE_ADDRESS DT_ATMEL_SAM0_UART_42000C00_BASE_ADDRESS -#define CONFIG_UART_SAM0_SERCOM1_RXPO DT_ATMEL_SAM0_UART_42000C00_RXPO -#define CONFIG_UART_SAM0_SERCOM1_TXPO DT_ATMEL_SAM0_UART_42000C00_TXPO +#define DT_UART_SAM0_SERCOM1_CURRENT_SPEED DT_ATMEL_SAM0_UART_42000C00_CURRENT_SPEED +#define DT_UART_SAM0_SERCOM1_IRQ DT_ATMEL_SAM0_UART_42000C00_IRQ_0 +#define DT_UART_SAM0_SERCOM1_IRQ_PRIORITY DT_ATMEL_SAM0_UART_42000C00_IRQ_0_PRIORITY +#define DT_UART_SAM0_SERCOM1_LABEL DT_ATMEL_SAM0_UART_42000C00_LABEL +#define DT_UART_SAM0_SERCOM1_BASE_ADDRESS DT_ATMEL_SAM0_UART_42000C00_BASE_ADDRESS +#define DT_UART_SAM0_SERCOM1_RXPO DT_ATMEL_SAM0_UART_42000C00_RXPO +#define DT_UART_SAM0_SERCOM1_TXPO DT_ATMEL_SAM0_UART_42000C00_TXPO -#define CONFIG_UART_SAM0_SERCOM2_CURRENT_SPEED DT_ATMEL_SAM0_UART_42001000_CURRENT_SPEED -#define CONFIG_UART_SAM0_SERCOM2_IRQ DT_ATMEL_SAM0_UART_42001000_IRQ_0 -#define CONFIG_UART_SAM0_SERCOM2_IRQ_PRIORITY DT_ATMEL_SAM0_UART_42001000_IRQ_0_PRIORITY -#define CONFIG_UART_SAM0_SERCOM2_LABEL DT_ATMEL_SAM0_UART_42001000_LABEL -#define CONFIG_UART_SAM0_SERCOM2_BASE_ADDRESS DT_ATMEL_SAM0_UART_42001000_BASE_ADDRESS -#define CONFIG_UART_SAM0_SERCOM2_RXPO DT_ATMEL_SAM0_UART_42001000_RXPO -#define CONFIG_UART_SAM0_SERCOM2_TXPO DT_ATMEL_SAM0_UART_42001000_TXPO +#define DT_UART_SAM0_SERCOM2_CURRENT_SPEED DT_ATMEL_SAM0_UART_42001000_CURRENT_SPEED +#define DT_UART_SAM0_SERCOM2_IRQ DT_ATMEL_SAM0_UART_42001000_IRQ_0 +#define DT_UART_SAM0_SERCOM2_IRQ_PRIORITY DT_ATMEL_SAM0_UART_42001000_IRQ_0_PRIORITY +#define DT_UART_SAM0_SERCOM2_LABEL DT_ATMEL_SAM0_UART_42001000_LABEL +#define DT_UART_SAM0_SERCOM2_BASE_ADDRESS DT_ATMEL_SAM0_UART_42001000_BASE_ADDRESS +#define DT_UART_SAM0_SERCOM2_RXPO DT_ATMEL_SAM0_UART_42001000_RXPO +#define DT_UART_SAM0_SERCOM2_TXPO DT_ATMEL_SAM0_UART_42001000_TXPO -#define CONFIG_UART_SAM0_SERCOM3_CURRENT_SPEED DT_ATMEL_SAM0_UART_42001400_CURRENT_SPEED -#define CONFIG_UART_SAM0_SERCOM3_IRQ DT_ATMEL_SAM0_UART_42001400_IRQ_0 -#define CONFIG_UART_SAM0_SERCOM3_IRQ_PRIORITY DT_ATMEL_SAM0_UART_42001400_IRQ_0_PRIORITY -#define CONFIG_UART_SAM0_SERCOM3_LABEL DT_ATMEL_SAM0_UART_42001400_LABEL -#define CONFIG_UART_SAM0_SERCOM3_BASE_ADDRESS DT_ATMEL_SAM0_UART_42001400_BASE_ADDRESS -#define CONFIG_UART_SAM0_SERCOM3_RXPO DT_ATMEL_SAM0_UART_42001400_RXPO -#define CONFIG_UART_SAM0_SERCOM3_TXPO DT_ATMEL_SAM0_UART_42001400_TXPO +#define DT_UART_SAM0_SERCOM3_CURRENT_SPEED DT_ATMEL_SAM0_UART_42001400_CURRENT_SPEED +#define DT_UART_SAM0_SERCOM3_IRQ DT_ATMEL_SAM0_UART_42001400_IRQ_0 +#define DT_UART_SAM0_SERCOM3_IRQ_PRIORITY DT_ATMEL_SAM0_UART_42001400_IRQ_0_PRIORITY +#define DT_UART_SAM0_SERCOM3_LABEL DT_ATMEL_SAM0_UART_42001400_LABEL +#define DT_UART_SAM0_SERCOM3_BASE_ADDRESS DT_ATMEL_SAM0_UART_42001400_BASE_ADDRESS +#define DT_UART_SAM0_SERCOM3_RXPO DT_ATMEL_SAM0_UART_42001400_RXPO +#define DT_UART_SAM0_SERCOM3_TXPO DT_ATMEL_SAM0_UART_42001400_TXPO -#define CONFIG_UART_SAM0_SERCOM4_CURRENT_SPEED DT_ATMEL_SAM0_UART_42001800_CURRENT_SPEED -#define CONFIG_UART_SAM0_SERCOM4_IRQ DT_ATMEL_SAM0_UART_42001800_IRQ_0 -#define CONFIG_UART_SAM0_SERCOM4_IRQ_PRIORITY DT_ATMEL_SAM0_UART_42001800_IRQ_0_PRIORITY -#define CONFIG_UART_SAM0_SERCOM4_LABEL DT_ATMEL_SAM0_UART_42001800_LABEL -#define CONFIG_UART_SAM0_SERCOM4_BASE_ADDRESS DT_ATMEL_SAM0_UART_42001800_BASE_ADDRESS -#define CONFIG_UART_SAM0_SERCOM4_RXPO DT_ATMEL_SAM0_UART_42001800_RXPO -#define CONFIG_UART_SAM0_SERCOM4_TXPO DT_ATMEL_SAM0_UART_42001800_TXPO +#define DT_UART_SAM0_SERCOM4_CURRENT_SPEED DT_ATMEL_SAM0_UART_42001800_CURRENT_SPEED +#define DT_UART_SAM0_SERCOM4_IRQ DT_ATMEL_SAM0_UART_42001800_IRQ_0 +#define DT_UART_SAM0_SERCOM4_IRQ_PRIORITY DT_ATMEL_SAM0_UART_42001800_IRQ_0_PRIORITY +#define DT_UART_SAM0_SERCOM4_LABEL DT_ATMEL_SAM0_UART_42001800_LABEL +#define DT_UART_SAM0_SERCOM4_BASE_ADDRESS DT_ATMEL_SAM0_UART_42001800_BASE_ADDRESS +#define DT_UART_SAM0_SERCOM4_RXPO DT_ATMEL_SAM0_UART_42001800_RXPO +#define DT_UART_SAM0_SERCOM4_TXPO DT_ATMEL_SAM0_UART_42001800_TXPO -#define CONFIG_UART_SAM0_SERCOM5_CURRENT_SPEED DT_ATMEL_SAM0_UART_42001C00_CURRENT_SPEED -#define CONFIG_UART_SAM0_SERCOM5_IRQ DT_ATMEL_SAM0_UART_42001C00_IRQ_0 -#define CONFIG_UART_SAM0_SERCOM5_IRQ_PRIORITY DT_ATMEL_SAM0_UART_42001C00_IRQ_0_PRIORITY -#define CONFIG_UART_SAM0_SERCOM5_LABEL DT_ATMEL_SAM0_UART_42001C00_LABEL -#define CONFIG_UART_SAM0_SERCOM5_BASE_ADDRESS DT_ATMEL_SAM0_UART_42001C00_BASE_ADDRESS -#define CONFIG_UART_SAM0_SERCOM5_RXPO DT_ATMEL_SAM0_UART_42001C00_RXPO -#define CONFIG_UART_SAM0_SERCOM5_TXPO DT_ATMEL_SAM0_UART_42001C00_TXPO +#define DT_UART_SAM0_SERCOM5_CURRENT_SPEED DT_ATMEL_SAM0_UART_42001C00_CURRENT_SPEED +#define DT_UART_SAM0_SERCOM5_IRQ DT_ATMEL_SAM0_UART_42001C00_IRQ_0 +#define DT_UART_SAM0_SERCOM5_IRQ_PRIORITY DT_ATMEL_SAM0_UART_42001C00_IRQ_0_PRIORITY +#define DT_UART_SAM0_SERCOM5_LABEL DT_ATMEL_SAM0_UART_42001C00_LABEL +#define DT_UART_SAM0_SERCOM5_BASE_ADDRESS DT_ATMEL_SAM0_UART_42001C00_BASE_ADDRESS +#define DT_UART_SAM0_SERCOM5_RXPO DT_ATMEL_SAM0_UART_42001C00_RXPO +#define DT_UART_SAM0_SERCOM5_TXPO DT_ATMEL_SAM0_UART_42001C00_TXPO -#define CONFIG_SPI_SAM0_SERCOM0_LABEL DT_ATMEL_SAM0_SPI_42000800_LABEL -#define CONFIG_SPI_SAM0_SERCOM0_BASE_ADDRESS DT_ATMEL_SAM0_SPI_42000800_BASE_ADDRESS -#define CONFIG_SPI_SAM0_SERCOM0_DIPO DT_ATMEL_SAM0_SPI_42000800_DIPO -#define CONFIG_SPI_SAM0_SERCOM0_DOPO DT_ATMEL_SAM0_SPI_42000800_DOPO +#define DT_SPI_SAM0_SERCOM0_LABEL DT_ATMEL_SAM0_SPI_42000800_LABEL +#define DT_SPI_SAM0_SERCOM0_BASE_ADDRESS DT_ATMEL_SAM0_SPI_42000800_BASE_ADDRESS +#define DT_SPI_SAM0_SERCOM0_DIPO DT_ATMEL_SAM0_SPI_42000800_DIPO +#define DT_SPI_SAM0_SERCOM0_DOPO DT_ATMEL_SAM0_SPI_42000800_DOPO -#define CONFIG_SPI_SAM0_SERCOM1_LABEL DT_ATMEL_SAM0_SPI_42000C00_LABEL -#define CONFIG_SPI_SAM0_SERCOM1_BASE_ADDRESS DT_ATMEL_SAM0_SPI_42000C00_BASE_ADDRESS -#define CONFIG_SPI_SAM0_SERCOM1_DIPO DT_ATMEL_SAM0_SPI_42000C00_DIPO -#define CONFIG_SPI_SAM0_SERCOM1_DOPO DT_ATMEL_SAM0_SPI_42000C00_DOPO +#define DT_SPI_SAM0_SERCOM1_LABEL DT_ATMEL_SAM0_SPI_42000C00_LABEL +#define DT_SPI_SAM0_SERCOM1_BASE_ADDRESS DT_ATMEL_SAM0_SPI_42000C00_BASE_ADDRESS +#define DT_SPI_SAM0_SERCOM1_DIPO DT_ATMEL_SAM0_SPI_42000C00_DIPO +#define DT_SPI_SAM0_SERCOM1_DOPO DT_ATMEL_SAM0_SPI_42000C00_DOPO -#define CONFIG_SPI_SAM0_SERCOM2_LABEL DT_ATMEL_SAM0_SPI_42001000_LABEL -#define CONFIG_SPI_SAM0_SERCOM2_BASE_ADDRESS DT_ATMEL_SAM0_SPI_42001000_BASE_ADDRESS -#define CONFIG_SPI_SAM0_SERCOM2_DIPO DT_ATMEL_SAM0_SPI_42001000_DIPO -#define CONFIG_SPI_SAM0_SERCOM2_DOPO DT_ATMEL_SAM0_SPI_42001000_DOPO +#define DT_SPI_SAM0_SERCOM2_LABEL DT_ATMEL_SAM0_SPI_42001000_LABEL +#define DT_SPI_SAM0_SERCOM2_BASE_ADDRESS DT_ATMEL_SAM0_SPI_42001000_BASE_ADDRESS +#define DT_SPI_SAM0_SERCOM2_DIPO DT_ATMEL_SAM0_SPI_42001000_DIPO +#define DT_SPI_SAM0_SERCOM2_DOPO DT_ATMEL_SAM0_SPI_42001000_DOPO -#define CONFIG_SPI_SAM0_SERCOM3_LABEL DT_ATMEL_SAM0_SPI_42001400_LABEL -#define CONFIG_SPI_SAM0_SERCOM3_BASE_ADDRESS DT_ATMEL_SAM0_SPI_42001400_BASE_ADDRESS -#define CONFIG_SPI_SAM0_SERCOM3_DIPO DT_ATMEL_SAM0_SPI_42001400_DIPO -#define CONFIG_SPI_SAM0_SERCOM3_DOPO DT_ATMEL_SAM0_SPI_42001400_DOPO +#define DT_SPI_SAM0_SERCOM3_LABEL DT_ATMEL_SAM0_SPI_42001400_LABEL +#define DT_SPI_SAM0_SERCOM3_BASE_ADDRESS DT_ATMEL_SAM0_SPI_42001400_BASE_ADDRESS +#define DT_SPI_SAM0_SERCOM3_DIPO DT_ATMEL_SAM0_SPI_42001400_DIPO +#define DT_SPI_SAM0_SERCOM3_DOPO DT_ATMEL_SAM0_SPI_42001400_DOPO -#define CONFIG_SPI_SAM0_SERCOM4_LABEL DT_ATMEL_SAM0_SPI_42001800_LABEL -#define CONFIG_SPI_SAM0_SERCOM4_BASE_ADDRESS DT_ATMEL_SAM0_SPI_42001800_BASE_ADDRESS -#define CONFIG_SPI_SAM0_SERCOM4_DIPO DT_ATMEL_SAM0_SPI_42001800_DIPO -#define CONFIG_SPI_SAM0_SERCOM4_DOPO DT_ATMEL_SAM0_SPI_42001800_DOPO +#define DT_SPI_SAM0_SERCOM4_LABEL DT_ATMEL_SAM0_SPI_42001800_LABEL +#define DT_SPI_SAM0_SERCOM4_BASE_ADDRESS DT_ATMEL_SAM0_SPI_42001800_BASE_ADDRESS +#define DT_SPI_SAM0_SERCOM4_DIPO DT_ATMEL_SAM0_SPI_42001800_DIPO +#define DT_SPI_SAM0_SERCOM4_DOPO DT_ATMEL_SAM0_SPI_42001800_DOPO -#define CONFIG_SPI_SAM0_SERCOM5_LABEL DT_ATMEL_SAM0_SPI_42001C00_LABEL -#define CONFIG_SPI_SAM0_SERCOM5_BASE_ADDRESS DT_ATMEL_SAM0_SPI_42001C00_BASE_ADDRESS -#define CONFIG_SPI_SAM0_SERCOM5_DIPO DT_ATMEL_SAM0_SPI_42001C00_DIPO -#define CONFIG_SPI_SAM0_SERCOM5_DOPO DT_ATMEL_SAM0_SPI_42001C00_DOPO +#define DT_SPI_SAM0_SERCOM5_LABEL DT_ATMEL_SAM0_SPI_42001C00_LABEL +#define DT_SPI_SAM0_SERCOM5_BASE_ADDRESS DT_ATMEL_SAM0_SPI_42001C00_BASE_ADDRESS +#define DT_SPI_SAM0_SERCOM5_DIPO DT_ATMEL_SAM0_SPI_42001C00_DIPO +#define DT_SPI_SAM0_SERCOM5_DOPO DT_ATMEL_SAM0_SPI_42001C00_DOPO -#define CONFIG_WDT_SAM0_IRQ DT_ATMEL_SAM0_WATCHDOG_40001000_IRQ_0 -#define CONFIG_WDT_SAM0_IRQ_PRIORITY DT_ATMEL_SAM0_WATCHDOG_40001000_IRQ_0_PRIORITY -#define CONFIG_WDT_SAM0_LABEL DT_ATMEL_SAM0_WATCHDOG_40001000_LABEL -#define CONFIG_WDT_SAM0_BASE_ADDRESS DT_ATMEL_SAM0_WATCHDOG_40001000_BASE_ADDRESS +#define DT_WDT_SAM0_IRQ DT_ATMEL_SAM0_WATCHDOG_40001000_IRQ_0 +#define DT_WDT_SAM0_IRQ_PRIORITY DT_ATMEL_SAM0_WATCHDOG_40001000_IRQ_0_PRIORITY +#define DT_WDT_SAM0_LABEL DT_ATMEL_SAM0_WATCHDOG_40001000_LABEL +#define DT_WDT_SAM0_BASE_ADDRESS DT_ATMEL_SAM0_WATCHDOG_40001000_BASE_ADDRESS -#define CONFIG_PINMUX_SAM0_A_BASE_ADDRESS DT_ATMEL_SAM0_PINMUX_41004400_BASE_ADDRESS -#define CONFIG_PINMUX_SAM0_A_LABEL DT_ATMEL_SAM0_PINMUX_41004400_LABEL +#define DT_PINMUX_SAM0_A_BASE_ADDRESS DT_ATMEL_SAM0_PINMUX_41004400_BASE_ADDRESS +#define DT_PINMUX_SAM0_A_LABEL DT_ATMEL_SAM0_PINMUX_41004400_LABEL -#define CONFIG_PINMUX_SAM0_B_BASE_ADDRESS DT_ATMEL_SAM0_PINMUX_41004480_BASE_ADDRESS -#define CONFIG_PINMUX_SAM0_B_LABEL DT_ATMEL_SAM0_PINMUX_41004480_LABEL +#define DT_PINMUX_SAM0_B_BASE_ADDRESS DT_ATMEL_SAM0_PINMUX_41004480_BASE_ADDRESS +#define DT_PINMUX_SAM0_B_LABEL DT_ATMEL_SAM0_PINMUX_41004480_LABEL -#define CONFIG_NUM_IRQ_PRIO_BITS DT_ARM_V6M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS +#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V6M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS /* End of SoC Level DTS fixup file */ diff --git a/soc/arm/atmel_sam0/samd21/dts_fixup.h b/soc/arm/atmel_sam0/samd21/dts_fixup.h index c882f58f8ea..fe206c84b87 100644 --- a/soc/arm/atmel_sam0/samd21/dts_fixup.h +++ b/soc/arm/atmel_sam0/samd21/dts_fixup.h @@ -1,108 +1,108 @@ /* SoC level DTS fixup file */ -#define FLASH_DEV_BASE_ADDRESS DT_ATMEL_SAM0_NVMCTRL_41004000_BASE_ADDRESS -#define FLASH_DEV_NAME DT_ATMEL_SAM0_NVMCTRL_41004000_LABEL +#define DT_FLASH_DEV_BASE_ADDRESS DT_ATMEL_SAM0_NVMCTRL_41004000_BASE_ADDRESS +#define DT_FLASH_DEV_NAME DT_ATMEL_SAM0_NVMCTRL_41004000_LABEL -#define CONFIG_GPIO_SAM0_PORTA_LABEL DT_ATMEL_SAM0_GPIO_41004400_LABEL -#define CONFIG_GPIO_SAM0_PORTA_BASE_ADDRESS DT_ATMEL_SAM0_GPIO_41004400_BASE_ADDRESS +#define DT_GPIO_SAM0_PORTA_LABEL DT_ATMEL_SAM0_GPIO_41004400_LABEL +#define DT_GPIO_SAM0_PORTA_BASE_ADDRESS DT_ATMEL_SAM0_GPIO_41004400_BASE_ADDRESS -#define CONFIG_GPIO_SAM0_PORTB_LABEL DT_ATMEL_SAM0_GPIO_41004480_LABEL -#define CONFIG_GPIO_SAM0_PORTB_BASE_ADDRESS DT_ATMEL_SAM0_GPIO_41004480_BASE_ADDRESS +#define DT_GPIO_SAM0_PORTB_LABEL DT_ATMEL_SAM0_GPIO_41004480_LABEL +#define DT_GPIO_SAM0_PORTB_BASE_ADDRESS DT_ATMEL_SAM0_GPIO_41004480_BASE_ADDRESS -#define CONFIG_UART_SAM0_SERCOM0_CURRENT_SPEED DT_ATMEL_SAM0_UART_42000800_CURRENT_SPEED -#define CONFIG_UART_SAM0_SERCOM0_IRQ DT_ATMEL_SAM0_UART_42000800_IRQ_0 -#define CONFIG_UART_SAM0_SERCOM0_IRQ_PRIORITY DT_ATMEL_SAM0_UART_42000800_IRQ_0_PRIORITY -#define CONFIG_UART_SAM0_SERCOM0_LABEL DT_ATMEL_SAM0_UART_42000800_LABEL -#define CONFIG_UART_SAM0_SERCOM0_BASE_ADDRESS DT_ATMEL_SAM0_UART_42000800_BASE_ADDRESS -#define CONFIG_UART_SAM0_SERCOM0_RXPO DT_ATMEL_SAM0_UART_42000800_RXPO -#define CONFIG_UART_SAM0_SERCOM0_TXPO DT_ATMEL_SAM0_UART_42000800_TXPO +#define DT_UART_SAM0_SERCOM0_CURRENT_SPEED DT_ATMEL_SAM0_UART_42000800_CURRENT_SPEED +#define DT_UART_SAM0_SERCOM0_IRQ DT_ATMEL_SAM0_UART_42000800_IRQ_0 +#define DT_UART_SAM0_SERCOM0_IRQ_PRIORITY DT_ATMEL_SAM0_UART_42000800_IRQ_0_PRIORITY +#define DT_UART_SAM0_SERCOM0_LABEL DT_ATMEL_SAM0_UART_42000800_LABEL +#define DT_UART_SAM0_SERCOM0_BASE_ADDRESS DT_ATMEL_SAM0_UART_42000800_BASE_ADDRESS +#define DT_UART_SAM0_SERCOM0_RXPO DT_ATMEL_SAM0_UART_42000800_RXPO +#define DT_UART_SAM0_SERCOM0_TXPO DT_ATMEL_SAM0_UART_42000800_TXPO -#define CONFIG_UART_SAM0_SERCOM1_CURRENT_SPEED DT_ATMEL_SAM0_UART_42000C00_CURRENT_SPEED -#define CONFIG_UART_SAM0_SERCOM1_IRQ DT_ATMEL_SAM0_UART_42000C00_IRQ_0 -#define CONFIG_UART_SAM0_SERCOM1_IRQ_PRIORITY DT_ATMEL_SAM0_UART_42000C00_IRQ_0_PRIORITY -#define CONFIG_UART_SAM0_SERCOM1_LABEL DT_ATMEL_SAM0_UART_42000C00_LABEL -#define CONFIG_UART_SAM0_SERCOM1_BASE_ADDRESS DT_ATMEL_SAM0_UART_42000C00_BASE_ADDRESS -#define CONFIG_UART_SAM0_SERCOM1_RXPO DT_ATMEL_SAM0_UART_42000C00_RXPO -#define CONFIG_UART_SAM0_SERCOM1_TXPO DT_ATMEL_SAM0_UART_42000C00_TXPO +#define DT_UART_SAM0_SERCOM1_CURRENT_SPEED DT_ATMEL_SAM0_UART_42000C00_CURRENT_SPEED +#define DT_UART_SAM0_SERCOM1_IRQ DT_ATMEL_SAM0_UART_42000C00_IRQ_0 +#define DT_UART_SAM0_SERCOM1_IRQ_PRIORITY DT_ATMEL_SAM0_UART_42000C00_IRQ_0_PRIORITY +#define DT_UART_SAM0_SERCOM1_LABEL DT_ATMEL_SAM0_UART_42000C00_LABEL +#define DT_UART_SAM0_SERCOM1_BASE_ADDRESS DT_ATMEL_SAM0_UART_42000C00_BASE_ADDRESS +#define DT_UART_SAM0_SERCOM1_RXPO DT_ATMEL_SAM0_UART_42000C00_RXPO +#define DT_UART_SAM0_SERCOM1_TXPO DT_ATMEL_SAM0_UART_42000C00_TXPO -#define CONFIG_UART_SAM0_SERCOM2_CURRENT_SPEED DT_ATMEL_SAM0_UART_42001000_CURRENT_SPEED -#define CONFIG_UART_SAM0_SERCOM2_IRQ DT_ATMEL_SAM0_UART_42001000_IRQ_0 -#define CONFIG_UART_SAM0_SERCOM2_IRQ_PRIORITY DT_ATMEL_SAM0_UART_42001000_IRQ_0_PRIORITY -#define CONFIG_UART_SAM0_SERCOM2_LABEL DT_ATMEL_SAM0_UART_42001000_LABEL -#define CONFIG_UART_SAM0_SERCOM2_BASE_ADDRESS DT_ATMEL_SAM0_UART_42001000_BASE_ADDRESS -#define CONFIG_UART_SAM0_SERCOM2_RXPO DT_ATMEL_SAM0_UART_42001000_RXPO -#define CONFIG_UART_SAM0_SERCOM2_TXPO DT_ATMEL_SAM0_UART_42001000_TXPO +#define DT_UART_SAM0_SERCOM2_CURRENT_SPEED DT_ATMEL_SAM0_UART_42001000_CURRENT_SPEED +#define DT_UART_SAM0_SERCOM2_IRQ DT_ATMEL_SAM0_UART_42001000_IRQ_0 +#define DT_UART_SAM0_SERCOM2_IRQ_PRIORITY DT_ATMEL_SAM0_UART_42001000_IRQ_0_PRIORITY +#define DT_UART_SAM0_SERCOM2_LABEL DT_ATMEL_SAM0_UART_42001000_LABEL +#define DT_UART_SAM0_SERCOM2_BASE_ADDRESS DT_ATMEL_SAM0_UART_42001000_BASE_ADDRESS +#define DT_UART_SAM0_SERCOM2_RXPO DT_ATMEL_SAM0_UART_42001000_RXPO +#define DT_UART_SAM0_SERCOM2_TXPO DT_ATMEL_SAM0_UART_42001000_TXPO -#define CONFIG_UART_SAM0_SERCOM3_CURRENT_SPEED DT_ATMEL_SAM0_UART_42001400_CURRENT_SPEED -#define CONFIG_UART_SAM0_SERCOM3_IRQ DT_ATMEL_SAM0_UART_42001400_IRQ_0 -#define CONFIG_UART_SAM0_SERCOM3_IRQ_PRIORITY DT_ATMEL_SAM0_UART_42001400_IRQ_0_PRIORITY -#define CONFIG_UART_SAM0_SERCOM3_LABEL DT_ATMEL_SAM0_UART_42001400_LABEL -#define CONFIG_UART_SAM0_SERCOM3_BASE_ADDRESS DT_ATMEL_SAM0_UART_42001400_BASE_ADDRESS -#define CONFIG_UART_SAM0_SERCOM3_RXPO DT_ATMEL_SAM0_UART_42001400_RXPO -#define CONFIG_UART_SAM0_SERCOM3_TXPO DT_ATMEL_SAM0_UART_42001400_TXPO +#define DT_UART_SAM0_SERCOM3_CURRENT_SPEED DT_ATMEL_SAM0_UART_42001400_CURRENT_SPEED +#define DT_UART_SAM0_SERCOM3_IRQ DT_ATMEL_SAM0_UART_42001400_IRQ_0 +#define DT_UART_SAM0_SERCOM3_IRQ_PRIORITY DT_ATMEL_SAM0_UART_42001400_IRQ_0_PRIORITY +#define DT_UART_SAM0_SERCOM3_LABEL DT_ATMEL_SAM0_UART_42001400_LABEL +#define DT_UART_SAM0_SERCOM3_BASE_ADDRESS DT_ATMEL_SAM0_UART_42001400_BASE_ADDRESS +#define DT_UART_SAM0_SERCOM3_RXPO DT_ATMEL_SAM0_UART_42001400_RXPO +#define DT_UART_SAM0_SERCOM3_TXPO DT_ATMEL_SAM0_UART_42001400_TXPO -#define CONFIG_UART_SAM0_SERCOM4_CURRENT_SPEED DT_ATMEL_SAM0_UART_42001800_CURRENT_SPEED -#define CONFIG_UART_SAM0_SERCOM4_IRQ DT_ATMEL_SAM0_UART_42001800_IRQ_0 -#define CONFIG_UART_SAM0_SERCOM4_IRQ_PRIORITY DT_ATMEL_SAM0_UART_42001800_IRQ_0_PRIORITY -#define CONFIG_UART_SAM0_SERCOM4_LABEL DT_ATMEL_SAM0_UART_42001800_LABEL -#define CONFIG_UART_SAM0_SERCOM4_BASE_ADDRESS DT_ATMEL_SAM0_UART_42001800_BASE_ADDRESS -#define CONFIG_UART_SAM0_SERCOM4_RXPO DT_ATMEL_SAM0_UART_42001800_RXPO -#define CONFIG_UART_SAM0_SERCOM4_TXPO DT_ATMEL_SAM0_UART_42001800_TXPO +#define DT_UART_SAM0_SERCOM4_CURRENT_SPEED DT_ATMEL_SAM0_UART_42001800_CURRENT_SPEED +#define DT_UART_SAM0_SERCOM4_IRQ DT_ATMEL_SAM0_UART_42001800_IRQ_0 +#define DT_UART_SAM0_SERCOM4_IRQ_PRIORITY DT_ATMEL_SAM0_UART_42001800_IRQ_0_PRIORITY +#define DT_UART_SAM0_SERCOM4_LABEL DT_ATMEL_SAM0_UART_42001800_LABEL +#define DT_UART_SAM0_SERCOM4_BASE_ADDRESS DT_ATMEL_SAM0_UART_42001800_BASE_ADDRESS +#define DT_UART_SAM0_SERCOM4_RXPO DT_ATMEL_SAM0_UART_42001800_RXPO +#define DT_UART_SAM0_SERCOM4_TXPO DT_ATMEL_SAM0_UART_42001800_TXPO -#define CONFIG_UART_SAM0_SERCOM5_CURRENT_SPEED DT_ATMEL_SAM0_UART_42001C00_CURRENT_SPEED -#define CONFIG_UART_SAM0_SERCOM5_IRQ DT_ATMEL_SAM0_UART_42001C00_IRQ_0 -#define CONFIG_UART_SAM0_SERCOM5_IRQ_PRIORITY DT_ATMEL_SAM0_UART_42001C00_IRQ_0_PRIORITY -#define CONFIG_UART_SAM0_SERCOM5_LABEL DT_ATMEL_SAM0_UART_42001C00_LABEL -#define CONFIG_UART_SAM0_SERCOM5_BASE_ADDRESS DT_ATMEL_SAM0_UART_42001C00_BASE_ADDRESS -#define CONFIG_UART_SAM0_SERCOM5_RXPO DT_ATMEL_SAM0_UART_42001C00_RXPO -#define CONFIG_UART_SAM0_SERCOM5_TXPO DT_ATMEL_SAM0_UART_42001C00_TXPO +#define DT_UART_SAM0_SERCOM5_CURRENT_SPEED DT_ATMEL_SAM0_UART_42001C00_CURRENT_SPEED +#define DT_UART_SAM0_SERCOM5_IRQ DT_ATMEL_SAM0_UART_42001C00_IRQ_0 +#define DT_UART_SAM0_SERCOM5_IRQ_PRIORITY DT_ATMEL_SAM0_UART_42001C00_IRQ_0_PRIORITY +#define DT_UART_SAM0_SERCOM5_LABEL DT_ATMEL_SAM0_UART_42001C00_LABEL +#define DT_UART_SAM0_SERCOM5_BASE_ADDRESS DT_ATMEL_SAM0_UART_42001C00_BASE_ADDRESS +#define DT_UART_SAM0_SERCOM5_RXPO DT_ATMEL_SAM0_UART_42001C00_RXPO +#define DT_UART_SAM0_SERCOM5_TXPO DT_ATMEL_SAM0_UART_42001C00_TXPO -#define CONFIG_SPI_SAM0_SERCOM0_LABEL DT_ATMEL_SAM0_SPI_42000800_LABEL -#define CONFIG_SPI_SAM0_SERCOM0_BASE_ADDRESS DT_ATMEL_SAM0_SPI_42000800_BASE_ADDRESS -#define CONFIG_SPI_SAM0_SERCOM0_DIPO DT_ATMEL_SAM0_SPI_42000800_DIPO -#define CONFIG_SPI_SAM0_SERCOM0_DOPO DT_ATMEL_SAM0_SPI_42000800_DOPO +#define DT_SPI_SAM0_SERCOM0_LABEL DT_ATMEL_SAM0_SPI_42000800_LABEL +#define DT_SPI_SAM0_SERCOM0_BASE_ADDRESS DT_ATMEL_SAM0_SPI_42000800_BASE_ADDRESS +#define DT_SPI_SAM0_SERCOM0_DIPO DT_ATMEL_SAM0_SPI_42000800_DIPO +#define DT_SPI_SAM0_SERCOM0_DOPO DT_ATMEL_SAM0_SPI_42000800_DOPO -#define CONFIG_SPI_SAM0_SERCOM1_LABEL DT_ATMEL_SAM0_SPI_42000C00_LABEL -#define CONFIG_SPI_SAM0_SERCOM1_BASE_ADDRESS DT_ATMEL_SAM0_SPI_42000C00_BASE_ADDRESS -#define CONFIG_SPI_SAM0_SERCOM1_DIPO DT_ATMEL_SAM0_SPI_42000C00_DIPO -#define CONFIG_SPI_SAM0_SERCOM1_DOPO DT_ATMEL_SAM0_SPI_42000C00_DOPO +#define DT_SPI_SAM0_SERCOM1_LABEL DT_ATMEL_SAM0_SPI_42000C00_LABEL +#define DT_SPI_SAM0_SERCOM1_BASE_ADDRESS DT_ATMEL_SAM0_SPI_42000C00_BASE_ADDRESS +#define DT_SPI_SAM0_SERCOM1_DIPO DT_ATMEL_SAM0_SPI_42000C00_DIPO +#define DT_SPI_SAM0_SERCOM1_DOPO DT_ATMEL_SAM0_SPI_42000C00_DOPO -#define CONFIG_SPI_SAM0_SERCOM2_LABEL DT_ATMEL_SAM0_SPI_42001000_LABEL -#define CONFIG_SPI_SAM0_SERCOM2_BASE_ADDRESS DT_ATMEL_SAM0_SPI_42001000_BASE_ADDRESS -#define CONFIG_SPI_SAM0_SERCOM2_DIPO DT_ATMEL_SAM0_SPI_42001000_DIPO -#define CONFIG_SPI_SAM0_SERCOM2_DOPO DT_ATMEL_SAM0_SPI_42001000_DOPO +#define DT_SPI_SAM0_SERCOM2_LABEL DT_ATMEL_SAM0_SPI_42001000_LABEL +#define DT_SPI_SAM0_SERCOM2_BASE_ADDRESS DT_ATMEL_SAM0_SPI_42001000_BASE_ADDRESS +#define DT_SPI_SAM0_SERCOM2_DIPO DT_ATMEL_SAM0_SPI_42001000_DIPO +#define DT_SPI_SAM0_SERCOM2_DOPO DT_ATMEL_SAM0_SPI_42001000_DOPO -#define CONFIG_SPI_SAM0_SERCOM3_LABEL DT_ATMEL_SAM0_SPI_42001400_LABEL -#define CONFIG_SPI_SAM0_SERCOM3_BASE_ADDRESS DT_ATMEL_SAM0_SPI_42001400_BASE_ADDRESS -#define CONFIG_SPI_SAM0_SERCOM3_DIPO DT_ATMEL_SAM0_SPI_42001400_DIPO -#define CONFIG_SPI_SAM0_SERCOM3_DOPO DT_ATMEL_SAM0_SPI_42001400_DOPO +#define DT_SPI_SAM0_SERCOM3_LABEL DT_ATMEL_SAM0_SPI_42001400_LABEL +#define DT_SPI_SAM0_SERCOM3_BASE_ADDRESS DT_ATMEL_SAM0_SPI_42001400_BASE_ADDRESS +#define DT_SPI_SAM0_SERCOM3_DIPO DT_ATMEL_SAM0_SPI_42001400_DIPO +#define DT_SPI_SAM0_SERCOM3_DOPO DT_ATMEL_SAM0_SPI_42001400_DOPO -#define CONFIG_SPI_SAM0_SERCOM4_LABEL DT_ATMEL_SAM0_SPI_42001800_LABEL -#define CONFIG_SPI_SAM0_SERCOM4_BASE_ADDRESS DT_ATMEL_SAM0_SPI_42001800_BASE_ADDRESS -#define CONFIG_SPI_SAM0_SERCOM4_DIPO DT_ATMEL_SAM0_SPI_42001800_DIPO -#define CONFIG_SPI_SAM0_SERCOM4_DOPO DT_ATMEL_SAM0_SPI_42001800_DOPO +#define DT_SPI_SAM0_SERCOM4_LABEL DT_ATMEL_SAM0_SPI_42001800_LABEL +#define DT_SPI_SAM0_SERCOM4_BASE_ADDRESS DT_ATMEL_SAM0_SPI_42001800_BASE_ADDRESS +#define DT_SPI_SAM0_SERCOM4_DIPO DT_ATMEL_SAM0_SPI_42001800_DIPO +#define DT_SPI_SAM0_SERCOM4_DOPO DT_ATMEL_SAM0_SPI_42001800_DOPO -#define CONFIG_SPI_SAM0_SERCOM5_LABEL DT_ATMEL_SAM0_SPI_42001C00_LABEL -#define CONFIG_SPI_SAM0_SERCOM5_BASE_ADDRESS DT_ATMEL_SAM0_SPI_42001C00_BASE_ADDRESS -#define CONFIG_SPI_SAM0_SERCOM5_DIPO DT_ATMEL_SAM0_SPI_42001C00_DIPO -#define CONFIG_SPI_SAM0_SERCOM5_DOPO DT_ATMEL_SAM0_SPI_42001C00_DOPO +#define DT_SPI_SAM0_SERCOM5_LABEL DT_ATMEL_SAM0_SPI_42001C00_LABEL +#define DT_SPI_SAM0_SERCOM5_BASE_ADDRESS DT_ATMEL_SAM0_SPI_42001C00_BASE_ADDRESS +#define DT_SPI_SAM0_SERCOM5_DIPO DT_ATMEL_SAM0_SPI_42001C00_DIPO +#define DT_SPI_SAM0_SERCOM5_DOPO DT_ATMEL_SAM0_SPI_42001C00_DOPO -#define CONFIG_WDT_SAM0_IRQ DT_ATMEL_SAM0_WATCHDOG_40001000_IRQ_0 -#define CONFIG_WDT_SAM0_IRQ_PRIORITY DT_ATMEL_SAM0_WATCHDOG_40001000_IRQ_0_PRIORITY -#define CONFIG_WDT_SAM0_LABEL DT_ATMEL_SAM0_WATCHDOG_40001000_LABEL -#define CONFIG_WDT_SAM0_BASE_ADDRESS DT_ATMEL_SAM0_WATCHDOG_40001000_BASE_ADDRESS +#define DT_WDT_SAM0_IRQ DT_ATMEL_SAM0_WATCHDOG_40001000_IRQ_0 +#define DT_WDT_SAM0_IRQ_PRIORITY DT_ATMEL_SAM0_WATCHDOG_40001000_IRQ_0_PRIORITY +#define DT_WDT_SAM0_LABEL DT_ATMEL_SAM0_WATCHDOG_40001000_LABEL +#define DT_WDT_SAM0_BASE_ADDRESS DT_ATMEL_SAM0_WATCHDOG_40001000_BASE_ADDRESS -#define CONFIG_PINMUX_SAM0_A_BASE_ADDRESS DT_ATMEL_SAM0_PINMUX_41004400_BASE_ADDRESS -#define CONFIG_PINMUX_SAM0_A_LABEL DT_ATMEL_SAM0_PINMUX_41004400_LABEL +#define DT_PINMUX_SAM0_A_BASE_ADDRESS DT_ATMEL_SAM0_PINMUX_41004400_BASE_ADDRESS +#define DT_PINMUX_SAM0_A_LABEL DT_ATMEL_SAM0_PINMUX_41004400_LABEL -#define CONFIG_PINMUX_SAM0_B_BASE_ADDRESS DT_ATMEL_SAM0_PINMUX_41004480_BASE_ADDRESS -#define CONFIG_PINMUX_SAM0_B_LABEL DT_ATMEL_SAM0_PINMUX_41004480_LABEL +#define DT_PINMUX_SAM0_B_BASE_ADDRESS DT_ATMEL_SAM0_PINMUX_41004480_BASE_ADDRESS +#define DT_PINMUX_SAM0_B_LABEL DT_ATMEL_SAM0_PINMUX_41004480_LABEL -#define CONFIG_USB_DC_SAM0_BASE_ADDRESS DT_ATMEL_SAM0_USB_41005000_BASE_ADDRESS -#define CONFIG_USB_DC_SAM0_IRQ DT_ATMEL_SAM0_USB_41005000_IRQ_0 -#define CONFIG_USB_DC_SAM0_IRQ_PRIORITY DT_ATMEL_SAM0_USB_41005000_IRQ_0_PRIORITY -#define CONFIG_USB_DC_SAM0_NUM_BIDIR_ENDPOINTS DT_ATMEL_SAM0_USB_41005000_NUM_BIDIR_ENDPOINTS +#define DT_USB_DC_SAM0_BASE_ADDRESS DT_ATMEL_SAM0_USB_41005000_BASE_ADDRESS +#define DT_USB_DC_SAM0_IRQ DT_ATMEL_SAM0_USB_41005000_IRQ_0 +#define DT_USB_DC_SAM0_IRQ_PRIORITY DT_ATMEL_SAM0_USB_41005000_IRQ_0_PRIORITY +#define DT_USB_DC_SAM0_NUM_BIDIR_ENDPOINTS DT_ATMEL_SAM0_USB_41005000_NUM_BIDIR_ENDPOINTS -#define CONFIG_NUM_IRQ_PRIO_BITS DT_ARM_V6M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS +#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V6M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS /* End of SoC Level DTS fixup file */ diff --git a/soc/arm/cypress/psoc6/dts_fixup.h b/soc/arm/cypress/psoc6/dts_fixup.h index d4863ac66f5..ce0a1b557f1 100644 --- a/soc/arm/cypress/psoc6/dts_fixup.h +++ b/soc/arm/cypress/psoc6/dts_fixup.h @@ -7,42 +7,42 @@ /* SoC level DTS fixup file */ #if defined(CONFIG_SOC_PSOC6_M0) -#define CONFIG_NUM_IRQ_PRIO_BITS DT_ARM_V6M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS +#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V6M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS #else -#define CONFIG_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS +#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS #endif -#define CONFIG_UART_PSOC6_UART_5_NAME "uart_5" -#define CONFIG_UART_PSOC6_UART_5_BASE_ADDRESS SCB5 -#define CONFIG_UART_PSOC6_UART_5_PORT P5_0_PORT -#define CONFIG_UART_PSOC6_UART_5_RX_NUM P5_0_NUM -#define CONFIG_UART_PSOC6_UART_5_TX_NUM P5_1_NUM -#define CONFIG_UART_PSOC6_UART_5_RX_VAL P5_0_SCB5_UART_RX -#define CONFIG_UART_PSOC6_UART_5_TX_VAL P5_1_SCB5_UART_TX -#define CONFIG_UART_PSOC6_UART_5_CLOCK PCLK_SCB5_CLOCK +#define DT_UART_PSOC6_UART_5_NAME "uart_5" +#define DT_UART_PSOC6_UART_5_BASE_ADDRESS SCB5 +#define DT_UART_PSOC6_UART_5_PORT P5_0_PORT +#define DT_UART_PSOC6_UART_5_RX_NUM P5_0_NUM +#define DT_UART_PSOC6_UART_5_TX_NUM P5_1_NUM +#define DT_UART_PSOC6_UART_5_RX_VAL P5_0_SCB5_UART_RX +#define DT_UART_PSOC6_UART_5_TX_VAL P5_1_SCB5_UART_TX +#define DT_UART_PSOC6_UART_5_CLOCK PCLK_SCB5_CLOCK -#define CONFIG_UART_PSOC6_UART_6_NAME "uart_6" -#define CONFIG_UART_PSOC6_UART_6_BASE_ADDRESS SCB6 -#define CONFIG_UART_PSOC6_UART_6_PORT P12_0_PORT -#define CONFIG_UART_PSOC6_UART_6_RX_NUM P12_0_NUM -#define CONFIG_UART_PSOC6_UART_6_TX_NUM P12_1_NUM -#define CONFIG_UART_PSOC6_UART_6_RX_VAL P12_0_SCB6_UART_RX -#define CONFIG_UART_PSOC6_UART_6_TX_VAL P12_1_SCB6_UART_TX -#define CONFIG_UART_PSOC6_UART_6_CLOCK PCLK_SCB6_CLOCK +#define DT_UART_PSOC6_UART_6_NAME "uart_6" +#define DT_UART_PSOC6_UART_6_BASE_ADDRESS SCB6 +#define DT_UART_PSOC6_UART_6_PORT P12_0_PORT +#define DT_UART_PSOC6_UART_6_RX_NUM P12_0_NUM +#define DT_UART_PSOC6_UART_6_TX_NUM P12_1_NUM +#define DT_UART_PSOC6_UART_6_RX_VAL P12_0_SCB6_UART_RX +#define DT_UART_PSOC6_UART_6_TX_VAL P12_1_SCB6_UART_TX +#define DT_UART_PSOC6_UART_6_CLOCK PCLK_SCB6_CLOCK /* UART desired baud rate is 115200 bps (Standard mode). * The UART baud rate = (SCB clock frequency / Oversample). * For PeriClk = 50 MHz, select divider value 36 and get SCB clock = (50 MHz / 36) = 1,389 MHz. * Select Oversample = 12. These setting results UART data rate = 1,389 MHz / 12 = 115750 bps. */ -#define CONFIG_UART_PSOC6_CONFIG_OVERSAMPLE (12UL) -#define CONFIG_UART_PSOC6_CONFIG_BREAKWIDTH (11UL) -#define CONFIG_UART_PSOC6_CONFIG_DATAWIDTH (8UL) +#define DT_UART_PSOC6_CONFIG_OVERSAMPLE (12UL) +#define DT_UART_PSOC6_CONFIG_BREAKWIDTH (11UL) +#define DT_UART_PSOC6_CONFIG_DATAWIDTH (8UL) /* Assign divider type and number for UART */ -#define CONFIG_UART_PSOC6_UART_CLK_DIV_TYPE (CY_SYSCLK_DIV_8_BIT) -#define CONFIG_UART_PSOC6_UART_CLK_DIV_NUMBER (PERI_DIV_8_NR - 1u) -#define CONFIG_UART_PSOC6_UART_CLK_DIV_VAL (35UL) +#define DT_UART_PSOC6_UART_CLK_DIV_TYPE (CY_SYSCLK_DIV_8_BIT) +#define DT_UART_PSOC6_UART_CLK_DIV_NUMBER (PERI_DIV_8_NR - 1u) +#define DT_UART_PSOC6_UART_CLK_DIV_VAL (35UL) /* End of SoC Level DTS fixup file */ diff --git a/soc/arm/nordic_nrf/nrf51/dts_fixup.h b/soc/arm/nordic_nrf/nrf51/dts_fixup.h index 4a5fd24c500..b802f4e8e2e 100644 --- a/soc/arm/nordic_nrf/nrf51/dts_fixup.h +++ b/soc/arm/nordic_nrf/nrf51/dts_fixup.h @@ -1,82 +1,82 @@ /* SoC level DTS fixup file */ -#define CONFIG_NUM_IRQ_PRIO_BITS DT_ARM_V6M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS +#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V6M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS -#define CONFIG_ADC_0_IRQ DT_NORDIC_NRF_ADC_40007000_IRQ_0 +#define DT_ADC_0_IRQ DT_NORDIC_NRF_ADC_40007000_IRQ_0 #define CONFIG_ADC_0_IRQ_PRI DT_NORDIC_NRF_ADC_40007000_IRQ_0_PRIORITY #define CONFIG_ADC_0_NAME DT_NORDIC_NRF_ADC_40007000_LABEL -#define CONFIG_UART_0_BASE DT_NORDIC_NRF_UART_40002000_BASE_ADDRESS -#define CONFIG_UART_0_IRQ_PRI DT_NORDIC_NRF_UART_40002000_IRQ_0_PRIORITY -#define CONFIG_UART_0_IRQ_NUM DT_NORDIC_NRF_UART_40002000_IRQ_0 -#define CONFIG_UART_0_BAUD_RATE DT_NORDIC_NRF_UART_40002000_CURRENT_SPEED -#define CONFIG_UART_0_NAME DT_NORDIC_NRF_UART_40002000_LABEL -#define CONFIG_UART_0_TX_PIN DT_NORDIC_NRF_UART_40002000_TX_PIN -#define CONFIG_UART_0_RX_PIN DT_NORDIC_NRF_UART_40002000_RX_PIN +#define DT_UART_0_BASE DT_NORDIC_NRF_UART_40002000_BASE_ADDRESS +#define DT_UART_0_IRQ_PRI DT_NORDIC_NRF_UART_40002000_IRQ_0_PRIORITY +#define DT_UART_0_IRQ_NUM DT_NORDIC_NRF_UART_40002000_IRQ_0 +#define DT_UART_0_BAUD_RATE DT_NORDIC_NRF_UART_40002000_CURRENT_SPEED +#define DT_UART_0_NAME DT_NORDIC_NRF_UART_40002000_LABEL +#define DT_UART_0_TX_PIN DT_NORDIC_NRF_UART_40002000_TX_PIN +#define DT_UART_0_RX_PIN DT_NORDIC_NRF_UART_40002000_RX_PIN #if defined(DT_NORDIC_NRF_UART_40002000_RTS_PIN) -#define CONFIG_UART_0_RTS_PIN DT_NORDIC_NRF_UART_40002000_RTS_PIN +#define DT_UART_0_RTS_PIN DT_NORDIC_NRF_UART_40002000_RTS_PIN #endif #if defined(DT_NORDIC_NRF_UART_40002000_CTS_PIN) -#define CONFIG_UART_0_CTS_PIN DT_NORDIC_NRF_UART_40002000_CTS_PIN +#define DT_UART_0_CTS_PIN DT_NORDIC_NRF_UART_40002000_CTS_PIN #endif -#define FLASH_DEV_NAME DT_NRF_NRF51_FLASH_CONTROLLER_4001E000_LABEL +#define DT_FLASH_DEV_NAME DT_NRF_NRF51_FLASH_CONTROLLER_4001E000_LABEL -#define CONFIG_GPIO_P0_DEV_NAME DT_NORDIC_NRF_GPIO_50000000_LABEL -#define CONFIG_GPIOTE_IRQ_PRI DT_NORDIC_NRF_GPIOTE_40006000_IRQ_0_PRIORITY -#define CONFIG_GPIOTE_IRQ DT_NORDIC_NRF_GPIOTE_40006000_IRQ_0 +#define DT_GPIO_P0_DEV_NAME DT_NORDIC_NRF_GPIO_50000000_LABEL +#define DT_GPIOTE_IRQ_PRI DT_NORDIC_NRF_GPIOTE_40006000_IRQ_0_PRIORITY +#define DT_GPIOTE_IRQ DT_NORDIC_NRF_GPIOTE_40006000_IRQ_0 -#define CONFIG_I2C_0_BASE_ADDR DT_NORDIC_NRF_I2C_40003000_BASE_ADDRESS +#define DT_I2C_0_BASE_ADDR DT_NORDIC_NRF_I2C_40003000_BASE_ADDRESS #define CONFIG_I2C_0_NAME DT_NORDIC_NRF_I2C_40003000_LABEL -#define CONFIG_I2C_0_BITRATE DT_NORDIC_NRF_I2C_40003000_CLOCK_FREQUENCY +#define DT_I2C_0_BITRATE DT_NORDIC_NRF_I2C_40003000_CLOCK_FREQUENCY #define CONFIG_I2C_0_IRQ_PRI DT_NORDIC_NRF_I2C_40003000_IRQ_0_PRIORITY -#define CONFIG_I2C_0_IRQ DT_NORDIC_NRF_I2C_40003000_IRQ_0 -#define CONFIG_I2C_0_SDA_PIN DT_NORDIC_NRF_I2C_40003000_SDA_PIN -#define CONFIG_I2C_0_SCL_PIN DT_NORDIC_NRF_I2C_40003000_SCL_PIN +#define DT_I2C_0_IRQ DT_NORDIC_NRF_I2C_40003000_IRQ_0 +#define DT_I2C_0_SDA_PIN DT_NORDIC_NRF_I2C_40003000_SDA_PIN +#define DT_I2C_0_SCL_PIN DT_NORDIC_NRF_I2C_40003000_SCL_PIN -#define CONFIG_I2C_1_BASE_ADDR DT_NORDIC_NRF_I2C_40004000_BASE_ADDRESS +#define DT_I2C_1_BASE_ADDR DT_NORDIC_NRF_I2C_40004000_BASE_ADDRESS #define CONFIG_I2C_1_NAME DT_NORDIC_NRF_I2C_40004000_LABEL -#define CONFIG_I2C_1_BITRATE DT_NORDIC_NRF_I2C_40004000_CLOCK_FREQUENCY +#define DT_I2C_1_BITRATE DT_NORDIC_NRF_I2C_40004000_CLOCK_FREQUENCY #define CONFIG_I2C_1_IRQ_PRI DT_NORDIC_NRF_I2C_40004000_IRQ_0_PRIORITY -#define CONFIG_I2C_1_IRQ DT_NORDIC_NRF_I2C_40004000_IRQ_0 -#define CONFIG_I2C_1_SDA_PIN DT_NORDIC_NRF_I2C_40004000_SDA_PIN -#define CONFIG_I2C_1_SCL_PIN DT_NORDIC_NRF_I2C_40004000_SCL_PIN +#define DT_I2C_1_IRQ DT_NORDIC_NRF_I2C_40004000_IRQ_0 +#define DT_I2C_1_SDA_PIN DT_NORDIC_NRF_I2C_40004000_SDA_PIN +#define DT_I2C_1_SCL_PIN DT_NORDIC_NRF_I2C_40004000_SCL_PIN -#define CONFIG_QDEC_BASE_ADDR DT_NORDIC_NRF_QDEC_40012000_BASE_ADDRESS -#define CONFIG_QDEC_NAME DT_NORDIC_NRF_QDEC_40012000_LABEL -#define CONFIG_QDEC_IRQ_PRI DT_NORDIC_NRF_QDEC_40012000_IRQ_0_PRIORITY -#define CONFIG_QDEC_IRQ DT_NORDIC_NRF_QDEC_40012000_IRQ_0 -#define CONFIG_QDEC_A_PIN DT_NORDIC_NRF_QDEC_40012000_A_PIN -#define CONFIG_QDEC_B_PIN DT_NORDIC_NRF_QDEC_40012000_B_PIN +#define DT_QDEC_BASE_ADDR DT_NORDIC_NRF_QDEC_40012000_BASE_ADDRESS +#define DT_QDEC_NAME DT_NORDIC_NRF_QDEC_40012000_LABEL +#define DT_QDEC_IRQ_PRI DT_NORDIC_NRF_QDEC_40012000_IRQ_0_PRIORITY +#define DT_QDEC_IRQ DT_NORDIC_NRF_QDEC_40012000_IRQ_0 +#define DT_QDEC_A_PIN DT_NORDIC_NRF_QDEC_40012000_A_PIN +#define DT_QDEC_B_PIN DT_NORDIC_NRF_QDEC_40012000_B_PIN #if defined(DT_NORDIC_NRF_QDEC_40012000_LED_PIN) -#define CONFIG_QDEC_LED_PIN DT_NORDIC_NRF_QDEC_40012000_LED_PIN +#define DT_QDEC_LED_PIN DT_NORDIC_NRF_QDEC_40012000_LED_PIN #endif #if defined(DT_NORDIC_NRF_QDEC_40012000_ENABLE_PIN) -#define CONFIG_QDEC_ENABLE_PIN DT_NORDIC_NRF_QDEC_40012000_ENABLE_PIN +#define DT_QDEC_ENABLE_PIN DT_NORDIC_NRF_QDEC_40012000_ENABLE_PIN #endif -#define CONFIG_QDEC_LED_PRE DT_NORDIC_NRF_QDEC_40012000_LED_PRE -#define CONFIG_QDEC_STEPS DT_NORDIC_NRF_QDEC_40012000_STEPS +#define DT_QDEC_LED_PRE DT_NORDIC_NRF_QDEC_40012000_LED_PRE +#define DT_QDEC_STEPS DT_NORDIC_NRF_QDEC_40012000_STEPS -#define CONFIG_SPI_0_BASE_ADDRESS DT_NORDIC_NRF_SPI_40003000_BASE_ADDRESS +#define DT_SPI_0_BASE_ADDRESS DT_NORDIC_NRF_SPI_40003000_BASE_ADDRESS #define CONFIG_SPI_0_NAME DT_NORDIC_NRF_SPI_40003000_LABEL #define CONFIG_SPI_0_IRQ_PRI DT_NORDIC_NRF_SPI_40003000_IRQ_0_PRIORITY -#define CONFIG_SPI_0_IRQ DT_NORDIC_NRF_SPI_40003000_IRQ_0 -#define CONFIG_SPI_0_NRF_SCK_PIN DT_NORDIC_NRF_SPI_40003000_SCK_PIN -#define CONFIG_SPI_0_NRF_MOSI_PIN DT_NORDIC_NRF_SPI_40003000_MOSI_PIN -#define CONFIG_SPI_0_NRF_MISO_PIN DT_NORDIC_NRF_SPI_40003000_MISO_PIN -#define CONFIG_SPI_0_NRF_CSN_PIN DT_NORDIC_NRF_SPI_40003000_CSN_PIN +#define DT_SPI_0_IRQ DT_NORDIC_NRF_SPI_40003000_IRQ_0 +#define DT_SPI_0_NRF_SCK_PIN DT_NORDIC_NRF_SPI_40003000_SCK_PIN +#define DT_SPI_0_NRF_MOSI_PIN DT_NORDIC_NRF_SPI_40003000_MOSI_PIN +#define DT_SPI_0_NRF_MISO_PIN DT_NORDIC_NRF_SPI_40003000_MISO_PIN +#define DT_SPI_0_NRF_CSN_PIN DT_NORDIC_NRF_SPI_40003000_CSN_PIN -#define CONFIG_SPI_1_BASE_ADDRESS DT_NORDIC_NRF_SPI_40004000_BASE_ADDRESS +#define DT_SPI_1_BASE_ADDRESS DT_NORDIC_NRF_SPI_40004000_BASE_ADDRESS #define CONFIG_SPI_1_NAME DT_NORDIC_NRF_SPI_40004000_LABEL #define CONFIG_SPI_1_IRQ_PRI DT_NORDIC_NRF_SPI_40004000_IRQ_0_PRIORITY -#define CONFIG_SPI_1_IRQ DT_NORDIC_NRF_SPI_40004000_IRQ_0 -#define CONFIG_SPI_1_NRF_SCK_PIN DT_NORDIC_NRF_SPI_40004000_SCK_PIN -#define CONFIG_SPI_1_NRF_MOSI_PIN DT_NORDIC_NRF_SPI_40004000_MOSI_PIN -#define CONFIG_SPI_1_NRF_MISO_PIN DT_NORDIC_NRF_SPI_40004000_MISO_PIN -#define CONFIG_SPI_1_NRF_CSN_PIN DT_NORDIC_NRF_SPI_40004000_CSN_PIN +#define DT_SPI_1_IRQ DT_NORDIC_NRF_SPI_40004000_IRQ_0 +#define DT_SPI_1_NRF_SCK_PIN DT_NORDIC_NRF_SPI_40004000_SCK_PIN +#define DT_SPI_1_NRF_MOSI_PIN DT_NORDIC_NRF_SPI_40004000_MOSI_PIN +#define DT_SPI_1_NRF_MISO_PIN DT_NORDIC_NRF_SPI_40004000_MISO_PIN +#define DT_SPI_1_NRF_CSN_PIN DT_NORDIC_NRF_SPI_40004000_CSN_PIN #define CONFIG_WDT_0_NAME DT_NORDIC_NRF_WATCHDOG_40010000_LABEL -#define CONFIG_WDT_NRF_IRQ DT_NORDIC_NRF_WATCHDOG_40010000_IRQ_WDT -#define CONFIG_WDT_NRF_IRQ_PRI DT_NORDIC_NRF_WATCHDOG_40010000_IRQ_WDT_PRIORITY +#define DT_WDT_NRF_IRQ DT_NORDIC_NRF_WATCHDOG_40010000_IRQ_WDT +#define DT_WDT_NRF_IRQ_PRI DT_NORDIC_NRF_WATCHDOG_40010000_IRQ_WDT_PRIORITY /* End of SoC Level DTS fixup file */ diff --git a/soc/arm/nordic_nrf/nrf52/dts_fixup.h b/soc/arm/nordic_nrf/nrf52/dts_fixup.h index 1d6e42805ac..fcacdbacbe9 100644 --- a/soc/arm/nordic_nrf/nrf52/dts_fixup.h +++ b/soc/arm/nordic_nrf/nrf52/dts_fixup.h @@ -1,167 +1,167 @@ /* SoC level DTS fixup file */ -#define CONFIG_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS +#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS -#define CONFIG_ADC_0_IRQ DT_NORDIC_NRF_SAADC_40007000_IRQ_0 +#define DT_ADC_0_IRQ DT_NORDIC_NRF_SAADC_40007000_IRQ_0 #define CONFIG_ADC_0_IRQ_PRI DT_NORDIC_NRF_SAADC_40007000_IRQ_0_PRIORITY #define CONFIG_ADC_0_NAME DT_NORDIC_NRF_SAADC_40007000_LABEL #if defined(DT_NORDIC_NRF_UARTE_40002000_BASE_ADDRESS) -#define CONFIG_UART_0_BASE DT_NORDIC_NRF_UARTE_40002000_BASE_ADDRESS -#define CONFIG_UART_0_IRQ_PRI DT_NORDIC_NRF_UARTE_40002000_IRQ_0_PRIORITY -#define CONFIG_UART_0_IRQ_NUM DT_NORDIC_NRF_UARTE_40002000_IRQ_0 -#define CONFIG_UART_0_BAUD_RATE DT_NORDIC_NRF_UARTE_40002000_CURRENT_SPEED -#define CONFIG_UART_0_NAME DT_NORDIC_NRF_UARTE_40002000_LABEL -#define CONFIG_UART_0_TX_PIN DT_NORDIC_NRF_UARTE_40002000_TX_PIN -#define CONFIG_UART_0_RX_PIN DT_NORDIC_NRF_UARTE_40002000_RX_PIN +#define DT_UART_0_BASE DT_NORDIC_NRF_UARTE_40002000_BASE_ADDRESS +#define DT_UART_0_IRQ_PRI DT_NORDIC_NRF_UARTE_40002000_IRQ_0_PRIORITY +#define DT_UART_0_IRQ_NUM DT_NORDIC_NRF_UARTE_40002000_IRQ_0 +#define DT_UART_0_BAUD_RATE DT_NORDIC_NRF_UARTE_40002000_CURRENT_SPEED +#define DT_UART_0_NAME DT_NORDIC_NRF_UARTE_40002000_LABEL +#define DT_UART_0_TX_PIN DT_NORDIC_NRF_UARTE_40002000_TX_PIN +#define DT_UART_0_RX_PIN DT_NORDIC_NRF_UARTE_40002000_RX_PIN #if defined(DT_NORDIC_NRF_UARTE_40002000_RTS_PIN) - #define CONFIG_UART_0_RTS_PIN DT_NORDIC_NRF_UARTE_40002000_RTS_PIN + #define DT_UART_0_RTS_PIN DT_NORDIC_NRF_UARTE_40002000_RTS_PIN #endif #if defined(DT_NORDIC_NRF_UARTE_40002000_CTS_PIN) - #define CONFIG_UART_0_CTS_PIN DT_NORDIC_NRF_UARTE_40002000_CTS_PIN + #define DT_UART_0_CTS_PIN DT_NORDIC_NRF_UARTE_40002000_CTS_PIN #endif #else -#define CONFIG_UART_0_BASE DT_NORDIC_NRF_UART_40002000_BASE_ADDRESS -#define CONFIG_UART_0_IRQ_PRI DT_NORDIC_NRF_UART_40002000_IRQ_0_PRIORITY -#define CONFIG_UART_0_IRQ_NUM DT_NORDIC_NRF_UART_40002000_IRQ_0 -#define CONFIG_UART_0_BAUD_RATE DT_NORDIC_NRF_UART_40002000_CURRENT_SPEED -#define CONFIG_UART_0_NAME DT_NORDIC_NRF_UART_40002000_LABEL -#define CONFIG_UART_0_TX_PIN DT_NORDIC_NRF_UART_40002000_TX_PIN -#define CONFIG_UART_0_RX_PIN DT_NORDIC_NRF_UART_40002000_RX_PIN +#define DT_UART_0_BASE DT_NORDIC_NRF_UART_40002000_BASE_ADDRESS +#define DT_UART_0_IRQ_PRI DT_NORDIC_NRF_UART_40002000_IRQ_0_PRIORITY +#define DT_UART_0_IRQ_NUM DT_NORDIC_NRF_UART_40002000_IRQ_0 +#define DT_UART_0_BAUD_RATE DT_NORDIC_NRF_UART_40002000_CURRENT_SPEED +#define DT_UART_0_NAME DT_NORDIC_NRF_UART_40002000_LABEL +#define DT_UART_0_TX_PIN DT_NORDIC_NRF_UART_40002000_TX_PIN +#define DT_UART_0_RX_PIN DT_NORDIC_NRF_UART_40002000_RX_PIN #if defined(DT_NORDIC_NRF_UART_40002000_RTS_PIN) - #define CONFIG_UART_0_RTS_PIN DT_NORDIC_NRF_UART_40002000_RTS_PIN + #define DT_UART_0_RTS_PIN DT_NORDIC_NRF_UART_40002000_RTS_PIN #endif #if defined(DT_NORDIC_NRF_UART_40002000_RTS_PIN) - #define CONFIG_UART_0_CTS_PIN DT_NORDIC_NRF_UART_40002000_CTS_PIN + #define DT_UART_0_CTS_PIN DT_NORDIC_NRF_UART_40002000_CTS_PIN #endif #endif -#define CONFIG_UART_1_BASE DT_NORDIC_NRF_UARTE_40028000_BASE_ADDRESS -#define CONFIG_UART_1_IRQ_PRI DT_NORDIC_NRF_UARTE_40028000_IRQ_0_PRIORITY -#define CONFIG_UART_1_IRQ_NUM DT_NORDIC_NRF_UARTE_40028000_IRQ_0 -#define CONFIG_UART_1_BAUD_RATE DT_NORDIC_NRF_UARTE_40028000_CURRENT_SPEED -#define CONFIG_UART_1_NAME DT_NORDIC_NRF_UARTE_40028000_LABEL -#define CONFIG_UART_1_TX_PIN DT_NORDIC_NRF_UARTE_40028000_TX_PIN -#define CONFIG_UART_1_RX_PIN DT_NORDIC_NRF_UARTE_40028000_RX_PIN +#define DT_UART_1_BASE DT_NORDIC_NRF_UARTE_40028000_BASE_ADDRESS +#define DT_UART_1_IRQ_PRI DT_NORDIC_NRF_UARTE_40028000_IRQ_0_PRIORITY +#define DT_UART_1_IRQ_NUM DT_NORDIC_NRF_UARTE_40028000_IRQ_0 +#define DT_UART_1_BAUD_RATE DT_NORDIC_NRF_UARTE_40028000_CURRENT_SPEED +#define DT_UART_1_NAME DT_NORDIC_NRF_UARTE_40028000_LABEL +#define DT_UART_1_TX_PIN DT_NORDIC_NRF_UARTE_40028000_TX_PIN +#define DT_UART_1_RX_PIN DT_NORDIC_NRF_UARTE_40028000_RX_PIN #if defined(DT_NORDIC_NRF_UARTE_40028000_RTS_PIN) -#define CONFIG_UART_1_RTS_PIN DT_NORDIC_NRF_UARTE_40028000_RTS_PIN +#define DT_UART_1_RTS_PIN DT_NORDIC_NRF_UARTE_40028000_RTS_PIN #endif #if defined(DT_NORDIC_NRF_UARTE_40028000_CTS_PIN) -#define CONFIG_UART_1_CTS_PIN DT_NORDIC_NRF_UARTE_40028000_CTS_PIN +#define DT_UART_1_CTS_PIN DT_NORDIC_NRF_UARTE_40028000_CTS_PIN #endif -#define FLASH_DEV_NAME DT_NRF_NRF52_FLASH_CONTROLLER_4001E000_LABEL +#define DT_FLASH_DEV_NAME DT_NRF_NRF52_FLASH_CONTROLLER_4001E000_LABEL -#define CONFIG_GPIO_P0_DEV_NAME DT_NORDIC_NRF_GPIO_50000000_LABEL +#define DT_GPIO_P0_DEV_NAME DT_NORDIC_NRF_GPIO_50000000_LABEL #if CONFIG_HAS_HW_NRF_GPIO1 -#define CONFIG_GPIO_P1_DEV_NAME DT_NORDIC_NRF_GPIO_50000300_LABEL +#define DT_GPIO_P1_DEV_NAME DT_NORDIC_NRF_GPIO_50000300_LABEL #endif -#define CONFIG_GPIOTE_IRQ_PRI DT_NORDIC_NRF_GPIOTE_40006000_IRQ_0_PRIORITY -#define CONFIG_GPIOTE_IRQ DT_NORDIC_NRF_GPIOTE_40006000_IRQ_0 +#define DT_GPIOTE_IRQ_PRI DT_NORDIC_NRF_GPIOTE_40006000_IRQ_0_PRIORITY +#define DT_GPIOTE_IRQ DT_NORDIC_NRF_GPIOTE_40006000_IRQ_0 -#define CONFIG_I2C_0_BASE_ADDR DT_NORDIC_NRF_I2C_40003000_BASE_ADDRESS +#define DT_I2C_0_BASE_ADDR DT_NORDIC_NRF_I2C_40003000_BASE_ADDRESS #define CONFIG_I2C_0_NAME DT_NORDIC_NRF_I2C_40003000_LABEL -#define CONFIG_I2C_0_BITRATE DT_NORDIC_NRF_I2C_40003000_CLOCK_FREQUENCY +#define DT_I2C_0_BITRATE DT_NORDIC_NRF_I2C_40003000_CLOCK_FREQUENCY #define CONFIG_I2C_0_IRQ_PRI DT_NORDIC_NRF_I2C_40003000_IRQ_0_PRIORITY -#define CONFIG_I2C_0_IRQ DT_NORDIC_NRF_I2C_40003000_IRQ_0 -#define CONFIG_I2C_0_SDA_PIN DT_NORDIC_NRF_I2C_40003000_SDA_PIN -#define CONFIG_I2C_0_SCL_PIN DT_NORDIC_NRF_I2C_40003000_SCL_PIN +#define DT_I2C_0_IRQ DT_NORDIC_NRF_I2C_40003000_IRQ_0 +#define DT_I2C_0_SDA_PIN DT_NORDIC_NRF_I2C_40003000_SDA_PIN +#define DT_I2C_0_SCL_PIN DT_NORDIC_NRF_I2C_40003000_SCL_PIN -#define CONFIG_I2C_1_BASE_ADDR DT_NORDIC_NRF_I2C_40004000_BASE_ADDRESS +#define DT_I2C_1_BASE_ADDR DT_NORDIC_NRF_I2C_40004000_BASE_ADDRESS #define CONFIG_I2C_1_NAME DT_NORDIC_NRF_I2C_40004000_LABEL -#define CONFIG_I2C_1_BITRATE DT_NORDIC_NRF_I2C_40004000_CLOCK_FREQUENCY +#define DT_I2C_1_BITRATE DT_NORDIC_NRF_I2C_40004000_CLOCK_FREQUENCY #define CONFIG_I2C_1_IRQ_PRI DT_NORDIC_NRF_I2C_40004000_IRQ_0_PRIORITY -#define CONFIG_I2C_1_IRQ DT_NORDIC_NRF_I2C_40004000_IRQ_0 -#define CONFIG_I2C_1_SDA_PIN DT_NORDIC_NRF_I2C_40004000_SDA_PIN -#define CONFIG_I2C_1_SCL_PIN DT_NORDIC_NRF_I2C_40004000_SCL_PIN +#define DT_I2C_1_IRQ DT_NORDIC_NRF_I2C_40004000_IRQ_0 +#define DT_I2C_1_SDA_PIN DT_NORDIC_NRF_I2C_40004000_SDA_PIN +#define DT_I2C_1_SCL_PIN DT_NORDIC_NRF_I2C_40004000_SCL_PIN -#define CONFIG_QDEC_BASE_ADDR DT_NORDIC_NRF_QDEC_40012000_BASE_ADDRESS -#define CONFIG_QDEC_NAME DT_NORDIC_NRF_QDEC_40012000_LABEL -#define CONFIG_QDEC_IRQ_PRI DT_NORDIC_NRF_QDEC_40012000_IRQ_0_PRIORITY -#define CONFIG_QDEC_IRQ DT_NORDIC_NRF_QDEC_40012000_IRQ_0 -#define CONFIG_QDEC_A_PIN DT_NORDIC_NRF_QDEC_40012000_A_PIN -#define CONFIG_QDEC_B_PIN DT_NORDIC_NRF_QDEC_40012000_B_PIN +#define DT_QDEC_BASE_ADDR DT_NORDIC_NRF_QDEC_40012000_BASE_ADDRESS +#define DT_QDEC_NAME DT_NORDIC_NRF_QDEC_40012000_LABEL +#define DT_QDEC_IRQ_PRI DT_NORDIC_NRF_QDEC_40012000_IRQ_0_PRIORITY +#define DT_QDEC_IRQ DT_NORDIC_NRF_QDEC_40012000_IRQ_0 +#define DT_QDEC_A_PIN DT_NORDIC_NRF_QDEC_40012000_A_PIN +#define DT_QDEC_B_PIN DT_NORDIC_NRF_QDEC_40012000_B_PIN #if defined(DT_NORDIC_NRF_QDEC_40012000_LED_PIN) -#define CONFIG_QDEC_LED_PIN DT_NORDIC_NRF_QDEC_40012000_LED_PIN +#define DT_QDEC_LED_PIN DT_NORDIC_NRF_QDEC_40012000_LED_PIN #endif #if defined(DT_NORDIC_NRF_QDEC_40012000_ENABLE_PIN) -#define CONFIG_QDEC_ENABLE_PIN DT_NORDIC_NRF_QDEC_40012000_ENABLE_PIN +#define DT_QDEC_ENABLE_PIN DT_NORDIC_NRF_QDEC_40012000_ENABLE_PIN #endif -#define CONFIG_QDEC_LED_PRE DT_NORDIC_NRF_QDEC_40012000_LED_PRE -#define CONFIG_QDEC_STEPS DT_NORDIC_NRF_QDEC_40012000_STEPS +#define DT_QDEC_LED_PRE DT_NORDIC_NRF_QDEC_40012000_LED_PRE +#define DT_QDEC_STEPS DT_NORDIC_NRF_QDEC_40012000_STEPS -#define CONFIG_SPI_0_BASE_ADDRESS DT_NORDIC_NRF_SPI_40003000_BASE_ADDRESS +#define DT_SPI_0_BASE_ADDRESS DT_NORDIC_NRF_SPI_40003000_BASE_ADDRESS #define CONFIG_SPI_0_NAME DT_NORDIC_NRF_SPI_40003000_LABEL #define CONFIG_SPI_0_IRQ_PRI DT_NORDIC_NRF_SPI_40003000_IRQ_0_PRIORITY -#define CONFIG_SPI_0_IRQ DT_NORDIC_NRF_SPI_40003000_IRQ_0 -#define CONFIG_SPI_0_NRF_SCK_PIN DT_NORDIC_NRF_SPI_40003000_SCK_PIN -#define CONFIG_SPI_0_NRF_MOSI_PIN DT_NORDIC_NRF_SPI_40003000_MOSI_PIN -#define CONFIG_SPI_0_NRF_MISO_PIN DT_NORDIC_NRF_SPI_40003000_MISO_PIN -#define CONFIG_SPI_0_NRF_CSN_PIN DT_NORDIC_NRF_SPI_40003000_CSN_PIN +#define DT_SPI_0_IRQ DT_NORDIC_NRF_SPI_40003000_IRQ_0 +#define DT_SPI_0_NRF_SCK_PIN DT_NORDIC_NRF_SPI_40003000_SCK_PIN +#define DT_SPI_0_NRF_MOSI_PIN DT_NORDIC_NRF_SPI_40003000_MOSI_PIN +#define DT_SPI_0_NRF_MISO_PIN DT_NORDIC_NRF_SPI_40003000_MISO_PIN +#define DT_SPI_0_NRF_CSN_PIN DT_NORDIC_NRF_SPI_40003000_CSN_PIN -#define CONFIG_SPI_1_BASE_ADDRESS DT_NORDIC_NRF_SPI_40004000_BASE_ADDRESS +#define DT_SPI_1_BASE_ADDRESS DT_NORDIC_NRF_SPI_40004000_BASE_ADDRESS #define CONFIG_SPI_1_NAME DT_NORDIC_NRF_SPI_40004000_LABEL #define CONFIG_SPI_1_IRQ_PRI DT_NORDIC_NRF_SPI_40004000_IRQ_0_PRIORITY -#define CONFIG_SPI_1_IRQ DT_NORDIC_NRF_SPI_40004000_IRQ_0 -#define CONFIG_SPI_1_NRF_SCK_PIN DT_NORDIC_NRF_SPI_40004000_SCK_PIN -#define CONFIG_SPI_1_NRF_MOSI_PIN DT_NORDIC_NRF_SPI_40004000_MOSI_PIN -#define CONFIG_SPI_1_NRF_MISO_PIN DT_NORDIC_NRF_SPI_40004000_MISO_PIN -#define CONFIG_SPI_1_NRF_CSN_PIN DT_NORDIC_NRF_SPI_40004000_CSN_PIN +#define DT_SPI_1_IRQ DT_NORDIC_NRF_SPI_40004000_IRQ_0 +#define DT_SPI_1_NRF_SCK_PIN DT_NORDIC_NRF_SPI_40004000_SCK_PIN +#define DT_SPI_1_NRF_MOSI_PIN DT_NORDIC_NRF_SPI_40004000_MOSI_PIN +#define DT_SPI_1_NRF_MISO_PIN DT_NORDIC_NRF_SPI_40004000_MISO_PIN +#define DT_SPI_1_NRF_CSN_PIN DT_NORDIC_NRF_SPI_40004000_CSN_PIN -#define CONFIG_SPI_2_BASE_ADDRESS DT_NORDIC_NRF_SPI_40023000_BASE_ADDRESS +#define DT_SPI_2_BASE_ADDRESS DT_NORDIC_NRF_SPI_40023000_BASE_ADDRESS #define CONFIG_SPI_2_NAME DT_NORDIC_NRF_SPI_40023000_LABEL #define CONFIG_SPI_2_IRQ_PRI DT_NORDIC_NRF_SPI_40023000_IRQ_0_PRIORITY -#define CONFIG_SPI_2_IRQ DT_NORDIC_NRF_SPI_40023000_IRQ_0 -#define CONFIG_SPI_2_NRF_SCK_PIN DT_NORDIC_NRF_SPI_40023000_SCK_PIN -#define CONFIG_SPI_2_NRF_MOSI_PIN DT_NORDIC_NRF_SPI_40023000_MOSI_PIN -#define CONFIG_SPI_2_NRF_MISO_PIN DT_NORDIC_NRF_SPI_40023000_MISO_PIN -#define CONFIG_SPI_2_NRF_CSN_PIN DT_NORDIC_NRF_SPI_40023000_CSN_PIN +#define DT_SPI_2_IRQ DT_NORDIC_NRF_SPI_40023000_IRQ_0 +#define DT_SPI_2_NRF_SCK_PIN DT_NORDIC_NRF_SPI_40023000_SCK_PIN +#define DT_SPI_2_NRF_MOSI_PIN DT_NORDIC_NRF_SPI_40023000_MOSI_PIN +#define DT_SPI_2_NRF_MISO_PIN DT_NORDIC_NRF_SPI_40023000_MISO_PIN +#define DT_SPI_2_NRF_CSN_PIN DT_NORDIC_NRF_SPI_40023000_CSN_PIN -#define CONFIG_SPI_3_BASE_ADDRESS DT_NORDIC_NRF_SPI_4002B000_BASE_ADDRESS +#define DT_SPI_3_BASE_ADDRESS DT_NORDIC_NRF_SPI_4002B000_BASE_ADDRESS #define CONFIG_SPI_3_NAME DT_NORDIC_NRF_SPI_4002B000_LABEL #define CONFIG_SPI_3_IRQ_PRI DT_NORDIC_NRF_SPI_4002B000_IRQ_0_PRIORITY -#define CONFIG_SPI_3_IRQ DT_NORDIC_NRF_SPI_4002B000_IRQ_0 -#define CONFIG_SPI_3_NRF_SCK_PIN DT_NORDIC_NRF_SPI_4002B000_SCK_PIN -#define CONFIG_SPI_3_NRF_MOSI_PIN DT_NORDIC_NRF_SPI_4002B000_MOSI_PIN -#define CONFIG_SPI_3_NRF_MISO_PIN DT_NORDIC_NRF_SPI_4002B000_MISO_PIN -#define CONFIG_SPI_3_NRF_CSN_PIN DT_NORDIC_NRF_SPI_4002B000_CSN_PIN +#define DT_SPI_3_IRQ DT_NORDIC_NRF_SPI_4002B000_IRQ_0 +#define DT_SPI_3_NRF_SCK_PIN DT_NORDIC_NRF_SPI_4002B000_SCK_PIN +#define DT_SPI_3_NRF_MOSI_PIN DT_NORDIC_NRF_SPI_4002B000_MOSI_PIN +#define DT_SPI_3_NRF_MISO_PIN DT_NORDIC_NRF_SPI_4002B000_MISO_PIN +#define DT_SPI_3_NRF_CSN_PIN DT_NORDIC_NRF_SPI_4002B000_CSN_PIN -#define CONFIG_USBD_NRF_IRQ DT_NORDIC_NRF_USBD_40027000_IRQ_USBD -#define CONFIG_USBD_NRF_IRQ_PRI DT_NORDIC_NRF_USBD_40027000_IRQ_USBD_PRIORITY -#define CONFIG_USBD_NRF_NUM_BIDIR_EP DT_NORDIC_NRF_USBD_40027000_NUM_BIDIR_ENDPOINTS -#define CONFIG_USBD_NRF_NUM_IN_EP DT_NORDIC_NRF_USBD_40027000_NUM_IN_ENDPOINTS -#define CONFIG_USBD_NRF_NUM_OUT_EP DT_NORDIC_NRF_USBD_40027000_NUM_OUT_ENDPOINTS -#define CONFIG_USBD_NRF_NUM_ISOIN_EP DT_NORDIC_NRF_USBD_40027000_NUM_ISOIN_ENDPOINTS -#define CONFIG_USBD_NRF_NUM_ISOOUT_EP DT_NORDIC_NRF_USBD_40027000_NUM_ISOOUT_ENDPOINTS -#define CONFIG_USBD_NRF_NAME DT_NORDIC_NRF_USBD_40027000_LABEL +#define DT_USBD_NRF_IRQ DT_NORDIC_NRF_USBD_40027000_IRQ_USBD +#define DT_USBD_NRF_IRQ_PRI DT_NORDIC_NRF_USBD_40027000_IRQ_USBD_PRIORITY +#define DT_USBD_NRF_NUM_BIDIR_EP DT_NORDIC_NRF_USBD_40027000_NUM_BIDIR_ENDPOINTS +#define DT_USBD_NRF_NUM_IN_EP DT_NORDIC_NRF_USBD_40027000_NUM_IN_ENDPOINTS +#define DT_USBD_NRF_NUM_OUT_EP DT_NORDIC_NRF_USBD_40027000_NUM_OUT_ENDPOINTS +#define DT_USBD_NRF_NUM_ISOIN_EP DT_NORDIC_NRF_USBD_40027000_NUM_ISOIN_ENDPOINTS +#define DT_USBD_NRF_NUM_ISOOUT_EP DT_NORDIC_NRF_USBD_40027000_NUM_ISOOUT_ENDPOINTS +#define DT_USBD_NRF_NAME DT_NORDIC_NRF_USBD_40027000_LABEL #define CONFIG_WDT_0_NAME DT_NORDIC_NRF_WATCHDOG_40010000_LABEL -#define CONFIG_WDT_NRF_IRQ DT_NORDIC_NRF_WATCHDOG_40010000_IRQ_WDT -#define CONFIG_WDT_NRF_IRQ_PRI DT_NORDIC_NRF_WATCHDOG_40010000_IRQ_WDT_PRIORITY +#define DT_WDT_NRF_IRQ DT_NORDIC_NRF_WATCHDOG_40010000_IRQ_WDT +#define DT_WDT_NRF_IRQ_PRI DT_NORDIC_NRF_WATCHDOG_40010000_IRQ_WDT_PRIORITY #if defined(DT_NORDIC_NRF_CC310_5002A000_BASE_ADDRESS) -#define CONFIG_CC310_CTL_BASE_ADDR DT_NORDIC_NRF_CC310_5002A000_BASE_ADDRESS -#define CONFIG_CC310_CTL_NAME DT_NORDIC_NRF_CC310_5002A000_LABEL -#define CONFIG_CC310_BASE_ADDR DT_ARM_CRYPTOCELL_310_5002B000_BASE_ADDRESS -#define CONFIG_CC310_NAME DT_ARM_CRYPTOCELL_310_5002B000_LABEL -#define CONFIG_CC310_IRQ DT_ARM_CRYPTOCELL_310_5002B000_IRQ_0 -#define CONFIG_CC310_IRQ_PRI DT_ARM_CRYPTOCELL_310_5002B000_IRQ_0_PRIORITY +#define DT_CC310_CTL_BASE_ADDR DT_NORDIC_NRF_CC310_5002A000_BASE_ADDRESS +#define DT_CC310_CTL_NAME DT_NORDIC_NRF_CC310_5002A000_LABEL +#define DT_CC310_BASE_ADDR DT_ARM_CRYPTOCELL_310_5002B000_BASE_ADDRESS +#define DT_CC310_NAME DT_ARM_CRYPTOCELL_310_5002B000_LABEL +#define DT_CC310_IRQ DT_ARM_CRYPTOCELL_310_5002B000_IRQ_0 +#define DT_CC310_IRQ_PRI DT_ARM_CRYPTOCELL_310_5002B000_IRQ_0_PRIORITY #endif -#define CONFIG_WNCM14A2A_UART_DRV_NAME DT_NORDIC_NRF_UARTE_40028000_WNCM14A2A_BUS_NAME -#define CONFIG_WNCM14A2A_GPIO_MDM_BOOT_MODE_SEL_NAME DT_NORDIC_NRF_UARTE_40028000_WNCM14A2A_MDM_BOOT_MODE_SEL_GPIOS_CONTROLLER -#define CONFIG_WNCM14A2A_GPIO_MDM_BOOT_MODE_SEL_PIN DT_NORDIC_NRF_UARTE_40028000_WNCM14A2A_MDM_BOOT_MODE_SEL_GPIOS_PIN -#define CONFIG_WNCM14A2A_GPIO_MDM_POWER_NAME DT_NORDIC_NRF_UARTE_40028000_WNCM14A2A_MDM_POWER_GPIOS_CONTROLLER -#define CONFIG_WNCM14A2A_GPIO_MDM_POWER_PIN DT_NORDIC_NRF_UARTE_40028000_WNCM14A2A_MDM_POWER_GPIOS_PIN -#define CONFIG_WNCM14A2A_GPIO_MDM_KEEP_AWAKE_NAME DT_NORDIC_NRF_UARTE_40028000_WNCM14A2A_MDM_KEEP_AWAKE_GPIOS_CONTROLLER -#define CONFIG_WNCM14A2A_GPIO_MDM_KEEP_AWAKE_PIN DT_NORDIC_NRF_UARTE_40028000_WNCM14A2A_MDM_KEEP_AWAKE_GPIOS_PIN -#define CONFIG_WNCM14A2A_GPIO_MDM_RESET_NAME DT_NORDIC_NRF_UARTE_40028000_WNCM14A2A_MDM_RESET_GPIOS_CONTROLLER -#define CONFIG_WNCM14A2A_GPIO_MDM_RESET_PIN DT_NORDIC_NRF_UARTE_40028000_WNCM14A2A_MDM_RESET_GPIOS_PIN -#define CONFIG_WNCM14A2A_GPIO_MDM_SHLD_TRANS_ENA_NAME DT_NORDIC_NRF_UARTE_40028000_WNCM14A2A_MDM_SHLD_TRANS_ENA_GPIOS_CONTROLLER -#define CONFIG_WNCM14A2A_GPIO_MDM_SHLD_TRANS_ENA_PIN DT_NORDIC_NRF_UARTE_40028000_WNCM14A2A_MDM_SHLD_TRANS_ENA_GPIOS_PIN +#define DT_WNCM14A2A_UART_DRV_NAME DT_NORDIC_NRF_UARTE_40028000_WNCM14A2A_BUS_NAME +#define DT_WNCM14A2A_GPIO_MDM_BOOT_MODE_SEL_NAME DT_NORDIC_NRF_UARTE_40028000_WNCM14A2A_MDM_BOOT_MODE_SEL_GPIOS_CONTROLLER +#define DT_WNCM14A2A_GPIO_MDM_BOOT_MODE_SEL_PIN DT_NORDIC_NRF_UARTE_40028000_WNCM14A2A_MDM_BOOT_MODE_SEL_GPIOS_PIN +#define DT_WNCM14A2A_GPIO_MDM_POWER_NAME DT_NORDIC_NRF_UARTE_40028000_WNCM14A2A_MDM_POWER_GPIOS_CONTROLLER +#define DT_WNCM14A2A_GPIO_MDM_POWER_PIN DT_NORDIC_NRF_UARTE_40028000_WNCM14A2A_MDM_POWER_GPIOS_PIN +#define DT_WNCM14A2A_GPIO_MDM_KEEP_AWAKE_NAME DT_NORDIC_NRF_UARTE_40028000_WNCM14A2A_MDM_KEEP_AWAKE_GPIOS_CONTROLLER +#define DT_WNCM14A2A_GPIO_MDM_KEEP_AWAKE_PIN DT_NORDIC_NRF_UARTE_40028000_WNCM14A2A_MDM_KEEP_AWAKE_GPIOS_PIN +#define DT_WNCM14A2A_GPIO_MDM_RESET_NAME DT_NORDIC_NRF_UARTE_40028000_WNCM14A2A_MDM_RESET_GPIOS_CONTROLLER +#define DT_WNCM14A2A_GPIO_MDM_RESET_PIN DT_NORDIC_NRF_UARTE_40028000_WNCM14A2A_MDM_RESET_GPIOS_PIN +#define DT_WNCM14A2A_GPIO_MDM_SHLD_TRANS_ENA_NAME DT_NORDIC_NRF_UARTE_40028000_WNCM14A2A_MDM_SHLD_TRANS_ENA_GPIOS_CONTROLLER +#define DT_WNCM14A2A_GPIO_MDM_SHLD_TRANS_ENA_PIN DT_NORDIC_NRF_UARTE_40028000_WNCM14A2A_MDM_SHLD_TRANS_ENA_GPIOS_PIN #ifdef DT_NORDIC_NRF_UARTE_40028000_WNCM14A2A_MDM_SEND_OK_GPIOS_PIN -#define CONFIG_WNCM14A2A_GPIO_MDM_SEND_OK_NAME DT_NORDIC_NRF_UARTE_40028000_WNCM14A2A_MDM_SEND_OK_GPIOS_CONTROLLER -#define CONFIG_WNCM14A2A_GPIO_MDM_SEND_OK_PIN DT_NORDIC_NRF_UARTE_40028000_WNCM14A2A_MDM_SEND_OK_GPIOS_PIN +#define DT_WNCM14A2A_GPIO_MDM_SEND_OK_NAME DT_NORDIC_NRF_UARTE_40028000_WNCM14A2A_MDM_SEND_OK_GPIOS_CONTROLLER +#define DT_WNCM14A2A_GPIO_MDM_SEND_OK_PIN DT_NORDIC_NRF_UARTE_40028000_WNCM14A2A_MDM_SEND_OK_GPIOS_PIN #endif /* End of SoC Level DTS fixup file */ diff --git a/soc/arm/nxp_imx/mcimx6x_m4/dts_fixup.h b/soc/arm/nxp_imx/mcimx6x_m4/dts_fixup.h index bdb7f28cda9..11ac892aa92 100644 --- a/soc/arm/nxp_imx/mcimx6x_m4/dts_fixup.h +++ b/soc/arm/nxp_imx/mcimx6x_m4/dts_fixup.h @@ -4,95 +4,95 @@ * SPDX-License-Identifier: Apache-2.0 */ -#define CONFIG_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS +#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS -#define CONFIG_GPIO_IMX_PORT_1_BASE_ADDRESS DT_NXP_IMX_GPIO_4209C000_BASE_ADDRESS -#define CONFIG_GPIO_IMX_PORT_1_NAME DT_NXP_IMX_GPIO_4209C000_LABEL -#define CONFIG_GPIO_IMX_PORT_1_IRQ_0 DT_NXP_IMX_GPIO_4209C000_IRQ_0 -#define CONFIG_GPIO_IMX_PORT_1_IRQ_0_PRI DT_NXP_IMX_GPIO_4209C000_IRQ_0_PRIORITY -#define CONFIG_GPIO_IMX_PORT_1_IRQ_1 DT_NXP_IMX_GPIO_4209C000_IRQ_1 -#define CONFIG_GPIO_IMX_PORT_1_IRQ_1_PRI DT_NXP_IMX_GPIO_4209C000_IRQ_1_PRIORITY +#define DT_GPIO_IMX_PORT_1_BASE_ADDRESS DT_NXP_IMX_GPIO_4209C000_BASE_ADDRESS +#define DT_GPIO_IMX_PORT_1_NAME DT_NXP_IMX_GPIO_4209C000_LABEL +#define DT_GPIO_IMX_PORT_1_IRQ_0 DT_NXP_IMX_GPIO_4209C000_IRQ_0 +#define DT_GPIO_IMX_PORT_1_IRQ_0_PRI DT_NXP_IMX_GPIO_4209C000_IRQ_0_PRIORITY +#define DT_GPIO_IMX_PORT_1_IRQ_1 DT_NXP_IMX_GPIO_4209C000_IRQ_1 +#define DT_GPIO_IMX_PORT_1_IRQ_1_PRI DT_NXP_IMX_GPIO_4209C000_IRQ_1_PRIORITY -#define CONFIG_GPIO_IMX_PORT_2_BASE_ADDRESS DT_NXP_IMX_GPIO_420A0000_BASE_ADDRESS -#define CONFIG_GPIO_IMX_PORT_2_NAME DT_NXP_IMX_GPIO_420A0000_LABEL -#define CONFIG_GPIO_IMX_PORT_2_IRQ_0 DT_NXP_IMX_GPIO_420A0000_IRQ_0 -#define CONFIG_GPIO_IMX_PORT_2_IRQ_0_PRI DT_NXP_IMX_GPIO_420A0000_IRQ_0_PRIORITY -#define CONFIG_GPIO_IMX_PORT_2_IRQ_1 DT_NXP_IMX_GPIO_420A0000_IRQ_1 -#define CONFIG_GPIO_IMX_PORT_2_IRQ_1_PRI DT_NXP_IMX_GPIO_420A0000_IRQ_1_PRIORITY +#define DT_GPIO_IMX_PORT_2_BASE_ADDRESS DT_NXP_IMX_GPIO_420A0000_BASE_ADDRESS +#define DT_GPIO_IMX_PORT_2_NAME DT_NXP_IMX_GPIO_420A0000_LABEL +#define DT_GPIO_IMX_PORT_2_IRQ_0 DT_NXP_IMX_GPIO_420A0000_IRQ_0 +#define DT_GPIO_IMX_PORT_2_IRQ_0_PRI DT_NXP_IMX_GPIO_420A0000_IRQ_0_PRIORITY +#define DT_GPIO_IMX_PORT_2_IRQ_1 DT_NXP_IMX_GPIO_420A0000_IRQ_1 +#define DT_GPIO_IMX_PORT_2_IRQ_1_PRI DT_NXP_IMX_GPIO_420A0000_IRQ_1_PRIORITY -#define CONFIG_GPIO_IMX_PORT_3_BASE_ADDRESS DT_NXP_IMX_GPIO_420A4000_BASE_ADDRESS -#define CONFIG_GPIO_IMX_PORT_3_NAME DT_NXP_IMX_GPIO_420A4000_LABEL -#define CONFIG_GPIO_IMX_PORT_3_IRQ_0 DT_NXP_IMX_GPIO_420A4000_IRQ_0 -#define CONFIG_GPIO_IMX_PORT_3_IRQ_0_PRI DT_NXP_IMX_GPIO_420A4000_IRQ_0_PRIORITY -#define CONFIG_GPIO_IMX_PORT_3_IRQ_1 DT_NXP_IMX_GPIO_420A4000_IRQ_1 -#define CONFIG_GPIO_IMX_PORT_3_IRQ_1_PRI DT_NXP_IMX_GPIO_420A4000_IRQ_1_PRIORITY +#define DT_GPIO_IMX_PORT_3_BASE_ADDRESS DT_NXP_IMX_GPIO_420A4000_BASE_ADDRESS +#define DT_GPIO_IMX_PORT_3_NAME DT_NXP_IMX_GPIO_420A4000_LABEL +#define DT_GPIO_IMX_PORT_3_IRQ_0 DT_NXP_IMX_GPIO_420A4000_IRQ_0 +#define DT_GPIO_IMX_PORT_3_IRQ_0_PRI DT_NXP_IMX_GPIO_420A4000_IRQ_0_PRIORITY +#define DT_GPIO_IMX_PORT_3_IRQ_1 DT_NXP_IMX_GPIO_420A4000_IRQ_1 +#define DT_GPIO_IMX_PORT_3_IRQ_1_PRI DT_NXP_IMX_GPIO_420A4000_IRQ_1_PRIORITY -#define CONFIG_GPIO_IMX_PORT_4_BASE_ADDRESS DT_NXP_IMX_GPIO_420A8000_BASE_ADDRESS -#define CONFIG_GPIO_IMX_PORT_4_NAME DT_NXP_IMX_GPIO_420A8000_LABEL -#define CONFIG_GPIO_IMX_PORT_4_IRQ_0 DT_NXP_IMX_GPIO_420A8000_IRQ_0 -#define CONFIG_GPIO_IMX_PORT_4_IRQ_0_PRI DT_NXP_IMX_GPIO_420A8000_IRQ_0_PRIORITY -#define CONFIG_GPIO_IMX_PORT_4_IRQ_1 DT_NXP_IMX_GPIO_420A8000_IRQ_1 -#define CONFIG_GPIO_IMX_PORT_4_IRQ_1_PRI DT_NXP_IMX_GPIO_420A8000_IRQ_1_PRIORITY +#define DT_GPIO_IMX_PORT_4_BASE_ADDRESS DT_NXP_IMX_GPIO_420A8000_BASE_ADDRESS +#define DT_GPIO_IMX_PORT_4_NAME DT_NXP_IMX_GPIO_420A8000_LABEL +#define DT_GPIO_IMX_PORT_4_IRQ_0 DT_NXP_IMX_GPIO_420A8000_IRQ_0 +#define DT_GPIO_IMX_PORT_4_IRQ_0_PRI DT_NXP_IMX_GPIO_420A8000_IRQ_0_PRIORITY +#define DT_GPIO_IMX_PORT_4_IRQ_1 DT_NXP_IMX_GPIO_420A8000_IRQ_1 +#define DT_GPIO_IMX_PORT_4_IRQ_1_PRI DT_NXP_IMX_GPIO_420A8000_IRQ_1_PRIORITY -#define CONFIG_GPIO_IMX_PORT_5_BASE_ADDRESS DT_NXP_IMX_GPIO_420AC000_BASE_ADDRESS -#define CONFIG_GPIO_IMX_PORT_5_NAME DT_NXP_IMX_GPIO_420AC000_LABEL -#define CONFIG_GPIO_IMX_PORT_5_IRQ_0 DT_NXP_IMX_GPIO_420AC000_IRQ_0 -#define CONFIG_GPIO_IMX_PORT_5_IRQ_0_PRI DT_NXP_IMX_GPIO_420AC000_IRQ_0_PRIORITY -#define CONFIG_GPIO_IMX_PORT_5_IRQ_1 DT_NXP_IMX_GPIO_420AC000_IRQ_1 -#define CONFIG_GPIO_IMX_PORT_5_IRQ_1_PRI DT_NXP_IMX_GPIO_420AC000_IRQ_1_PRIORITY +#define DT_GPIO_IMX_PORT_5_BASE_ADDRESS DT_NXP_IMX_GPIO_420AC000_BASE_ADDRESS +#define DT_GPIO_IMX_PORT_5_NAME DT_NXP_IMX_GPIO_420AC000_LABEL +#define DT_GPIO_IMX_PORT_5_IRQ_0 DT_NXP_IMX_GPIO_420AC000_IRQ_0 +#define DT_GPIO_IMX_PORT_5_IRQ_0_PRI DT_NXP_IMX_GPIO_420AC000_IRQ_0_PRIORITY +#define DT_GPIO_IMX_PORT_5_IRQ_1 DT_NXP_IMX_GPIO_420AC000_IRQ_1 +#define DT_GPIO_IMX_PORT_5_IRQ_1_PRI DT_NXP_IMX_GPIO_420AC000_IRQ_1_PRIORITY -#define CONFIG_GPIO_IMX_PORT_6_BASE_ADDRESS DT_NXP_IMX_GPIO_420B0000_BASE_ADDRESS -#define CONFIG_GPIO_IMX_PORT_6_NAME DT_NXP_IMX_GPIO_420B0000_LABEL -#define CONFIG_GPIO_IMX_PORT_6_IRQ_0 DT_NXP_IMX_GPIO_420B0000_IRQ_0 -#define CONFIG_GPIO_IMX_PORT_6_IRQ_0_PRI DT_NXP_IMX_GPIO_420B0000_IRQ_0_PRIORITY -#define CONFIG_GPIO_IMX_PORT_6_IRQ_1 DT_NXP_IMX_GPIO_420B0000_IRQ_1 -#define CONFIG_GPIO_IMX_PORT_6_IRQ_1_PRI DT_NXP_IMX_GPIO_420B0000_IRQ_1_PRIORITY +#define DT_GPIO_IMX_PORT_6_BASE_ADDRESS DT_NXP_IMX_GPIO_420B0000_BASE_ADDRESS +#define DT_GPIO_IMX_PORT_6_NAME DT_NXP_IMX_GPIO_420B0000_LABEL +#define DT_GPIO_IMX_PORT_6_IRQ_0 DT_NXP_IMX_GPIO_420B0000_IRQ_0 +#define DT_GPIO_IMX_PORT_6_IRQ_0_PRI DT_NXP_IMX_GPIO_420B0000_IRQ_0_PRIORITY +#define DT_GPIO_IMX_PORT_6_IRQ_1 DT_NXP_IMX_GPIO_420B0000_IRQ_1 +#define DT_GPIO_IMX_PORT_6_IRQ_1_PRI DT_NXP_IMX_GPIO_420B0000_IRQ_1_PRIORITY -#define CONFIG_GPIO_IMX_PORT_7_BASE_ADDRESS DT_NXP_IMX_GPIO_420B4000_BASE_ADDRESS -#define CONFIG_GPIO_IMX_PORT_7_NAME DT_NXP_IMX_GPIO_420B4000_LABEL -#define CONFIG_GPIO_IMX_PORT_7_IRQ_0 DT_NXP_IMX_GPIO_420B4000_IRQ_0 -#define CONFIG_GPIO_IMX_PORT_7_IRQ_0_PRI DT_NXP_IMX_GPIO_420B4000_IRQ_0_PRIORITY -#define CONFIG_GPIO_IMX_PORT_7_IRQ_1 DT_NXP_IMX_GPIO_420B4000_IRQ_1 -#define CONFIG_GPIO_IMX_PORT_7_IRQ_1_PRI DT_NXP_IMX_GPIO_420B4000_IRQ_1_PRIORITY +#define DT_GPIO_IMX_PORT_7_BASE_ADDRESS DT_NXP_IMX_GPIO_420B4000_BASE_ADDRESS +#define DT_GPIO_IMX_PORT_7_NAME DT_NXP_IMX_GPIO_420B4000_LABEL +#define DT_GPIO_IMX_PORT_7_IRQ_0 DT_NXP_IMX_GPIO_420B4000_IRQ_0 +#define DT_GPIO_IMX_PORT_7_IRQ_0_PRI DT_NXP_IMX_GPIO_420B4000_IRQ_0_PRIORITY +#define DT_GPIO_IMX_PORT_7_IRQ_1 DT_NXP_IMX_GPIO_420B4000_IRQ_1 +#define DT_GPIO_IMX_PORT_7_IRQ_1_PRI DT_NXP_IMX_GPIO_420B4000_IRQ_1_PRIORITY -#define CONFIG_UART_IMX_UART_1_BASE_ADDRESS DT_NXP_IMX_UART_42020000_BASE_ADDRESS -#define CONFIG_UART_IMX_UART_1_NAME DT_NXP_IMX_UART_42020000_LABEL -#define CONFIG_UART_IMX_UART_1_IRQ_NUM DT_NXP_IMX_UART_42020000_IRQ_0 -#define CONFIG_UART_IMX_UART_1_IRQ_PRI DT_NXP_IMX_UART_42020000_IRQ_0_PRIORITY -#define CONFIG_UART_IMX_UART_1_BAUD_RATE DT_NXP_IMX_UART_42020000_CURRENT_SPEED -#define CONFIG_UART_IMX_UART_1_MODEM_MODE DT_NXP_IMX_UART_42020000_MODEM_MODE +#define DT_UART_IMX_UART_1_BASE_ADDRESS DT_NXP_IMX_UART_42020000_BASE_ADDRESS +#define DT_UART_IMX_UART_1_NAME DT_NXP_IMX_UART_42020000_LABEL +#define DT_UART_IMX_UART_1_IRQ_NUM DT_NXP_IMX_UART_42020000_IRQ_0 +#define DT_UART_IMX_UART_1_IRQ_PRI DT_NXP_IMX_UART_42020000_IRQ_0_PRIORITY +#define DT_UART_IMX_UART_1_BAUD_RATE DT_NXP_IMX_UART_42020000_CURRENT_SPEED +#define DT_UART_IMX_UART_1_MODEM_MODE DT_NXP_IMX_UART_42020000_MODEM_MODE -#define CONFIG_UART_IMX_UART_2_BASE_ADDRESS DT_NXP_IMX_UART_421E8000_BASE_ADDRESS -#define CONFIG_UART_IMX_UART_2_NAME DT_NXP_IMX_UART_421E8000_LABEL -#define CONFIG_UART_IMX_UART_2_IRQ_NUM DT_NXP_IMX_UART_421E8000_IRQ_0 -#define CONFIG_UART_IMX_UART_2_IRQ_PRI DT_NXP_IMX_UART_421E8000_IRQ_0_PRIORITY -#define CONFIG_UART_IMX_UART_2_BAUD_RATE DT_NXP_IMX_UART_421E8000_CURRENT_SPEED -#define CONFIG_UART_IMX_UART_2_MODEM_MODE DT_NXP_IMX_UART_421E8000_MODEM_MODE +#define DT_UART_IMX_UART_2_BASE_ADDRESS DT_NXP_IMX_UART_421E8000_BASE_ADDRESS +#define DT_UART_IMX_UART_2_NAME DT_NXP_IMX_UART_421E8000_LABEL +#define DT_UART_IMX_UART_2_IRQ_NUM DT_NXP_IMX_UART_421E8000_IRQ_0 +#define DT_UART_IMX_UART_2_IRQ_PRI DT_NXP_IMX_UART_421E8000_IRQ_0_PRIORITY +#define DT_UART_IMX_UART_2_BAUD_RATE DT_NXP_IMX_UART_421E8000_CURRENT_SPEED +#define DT_UART_IMX_UART_2_MODEM_MODE DT_NXP_IMX_UART_421E8000_MODEM_MODE -#define CONFIG_UART_IMX_UART_3_BASE_ADDRESS DT_NXP_IMX_UART_421EC000_BASE_ADDRESS -#define CONFIG_UART_IMX_UART_3_NAME DT_NXP_IMX_UART_421EC000_LABEL -#define CONFIG_UART_IMX_UART_3_IRQ_NUM DT_NXP_IMX_UART_421EC000_IRQ_0 -#define CONFIG_UART_IMX_UART_3_IRQ_PRI DT_NXP_IMX_UART_421EC000_IRQ_0_PRIORITY -#define CONFIG_UART_IMX_UART_3_BAUD_RATE DT_NXP_IMX_UART_421EC000_CURRENT_SPEED -#define CONFIG_UART_IMX_UART_3_MODEM_MODE DT_NXP_IMX_UART_421EC000_MODEM_MODE +#define DT_UART_IMX_UART_3_BASE_ADDRESS DT_NXP_IMX_UART_421EC000_BASE_ADDRESS +#define DT_UART_IMX_UART_3_NAME DT_NXP_IMX_UART_421EC000_LABEL +#define DT_UART_IMX_UART_3_IRQ_NUM DT_NXP_IMX_UART_421EC000_IRQ_0 +#define DT_UART_IMX_UART_3_IRQ_PRI DT_NXP_IMX_UART_421EC000_IRQ_0_PRIORITY +#define DT_UART_IMX_UART_3_BAUD_RATE DT_NXP_IMX_UART_421EC000_CURRENT_SPEED +#define DT_UART_IMX_UART_3_MODEM_MODE DT_NXP_IMX_UART_421EC000_MODEM_MODE -#define CONFIG_UART_IMX_UART_4_BASE_ADDRESS DT_NXP_IMX_UART_421F0000_BASE_ADDRESS -#define CONFIG_UART_IMX_UART_4_NAME DT_NXP_IMX_UART_421F0000_LABEL -#define CONFIG_UART_IMX_UART_4_IRQ_NUM DT_NXP_IMX_UART_421F0000_IRQ_0 -#define CONFIG_UART_IMX_UART_4_IRQ_PRI DT_NXP_IMX_UART_421F0000_IRQ_0_PRIORITY -#define CONFIG_UART_IMX_UART_4_BAUD_RATE DT_NXP_IMX_UART_421F0000_CURRENT_SPEED -#define CONFIG_UART_IMX_UART_4_MODEM_MODE DT_NXP_IMX_UART_421F0000_MODEM_MODE +#define DT_UART_IMX_UART_4_BASE_ADDRESS DT_NXP_IMX_UART_421F0000_BASE_ADDRESS +#define DT_UART_IMX_UART_4_NAME DT_NXP_IMX_UART_421F0000_LABEL +#define DT_UART_IMX_UART_4_IRQ_NUM DT_NXP_IMX_UART_421F0000_IRQ_0 +#define DT_UART_IMX_UART_4_IRQ_PRI DT_NXP_IMX_UART_421F0000_IRQ_0_PRIORITY +#define DT_UART_IMX_UART_4_BAUD_RATE DT_NXP_IMX_UART_421F0000_CURRENT_SPEED +#define DT_UART_IMX_UART_4_MODEM_MODE DT_NXP_IMX_UART_421F0000_MODEM_MODE -#define CONFIG_UART_IMX_UART_5_BASE_ADDRESS DT_NXP_IMX_UART_421F4000_BASE_ADDRESS -#define CONFIG_UART_IMX_UART_5_NAME DT_NXP_IMX_UART_421F4000_LABEL -#define CONFIG_UART_IMX_UART_5_IRQ_NUM DT_NXP_IMX_UART_421F4000_IRQ_0 -#define CONFIG_UART_IMX_UART_5_IRQ_PRI DT_NXP_IMX_UART_421F4000_IRQ_0_PRIORITY -#define CONFIG_UART_IMX_UART_5_BAUD_RATE DT_NXP_IMX_UART_421F4000_CURRENT_SPEED -#define CONFIG_UART_IMX_UART_5_MODEM_MODE DT_NXP_IMX_UART_421F4000_MODEM_MODE +#define DT_UART_IMX_UART_5_BASE_ADDRESS DT_NXP_IMX_UART_421F4000_BASE_ADDRESS +#define DT_UART_IMX_UART_5_NAME DT_NXP_IMX_UART_421F4000_LABEL +#define DT_UART_IMX_UART_5_IRQ_NUM DT_NXP_IMX_UART_421F4000_IRQ_0 +#define DT_UART_IMX_UART_5_IRQ_PRI DT_NXP_IMX_UART_421F4000_IRQ_0_PRIORITY +#define DT_UART_IMX_UART_5_BAUD_RATE DT_NXP_IMX_UART_421F4000_CURRENT_SPEED +#define DT_UART_IMX_UART_5_MODEM_MODE DT_NXP_IMX_UART_421F4000_MODEM_MODE -#define CONFIG_UART_IMX_UART_6_BASE_ADDRESS DT_NXP_IMX_UART_422A0000_BASE_ADDRESS -#define CONFIG_UART_IMX_UART_6_NAME DT_NXP_IMX_UART_422A0000_LABEL -#define CONFIG_UART_IMX_UART_6_IRQ_NUM DT_NXP_IMX_UART_422A0000_IRQ_0 -#define CONFIG_UART_IMX_UART_6_IRQ_PRI DT_NXP_IMX_UART_422A0000_IRQ_0_PRIORITY -#define CONFIG_UART_IMX_UART_6_BAUD_RATE DT_NXP_IMX_UART_422A0000_CURRENT_SPEED -#define CONFIG_UART_IMX_UART_6_MODEM_MODE DT_NXP_IMX_UART_422A0000_MODEM_MODE +#define DT_UART_IMX_UART_6_BASE_ADDRESS DT_NXP_IMX_UART_422A0000_BASE_ADDRESS +#define DT_UART_IMX_UART_6_NAME DT_NXP_IMX_UART_422A0000_LABEL +#define DT_UART_IMX_UART_6_IRQ_NUM DT_NXP_IMX_UART_422A0000_IRQ_0 +#define DT_UART_IMX_UART_6_IRQ_PRI DT_NXP_IMX_UART_422A0000_IRQ_0_PRIORITY +#define DT_UART_IMX_UART_6_BAUD_RATE DT_NXP_IMX_UART_422A0000_CURRENT_SPEED +#define DT_UART_IMX_UART_6_MODEM_MODE DT_NXP_IMX_UART_422A0000_MODEM_MODE diff --git a/soc/arm/nxp_imx/mcimx7_m4/dts_fixup.h b/soc/arm/nxp_imx/mcimx7_m4/dts_fixup.h index 0d90cc9d4c0..0154f65150d 100644 --- a/soc/arm/nxp_imx/mcimx7_m4/dts_fixup.h +++ b/soc/arm/nxp_imx/mcimx7_m4/dts_fixup.h @@ -6,105 +6,105 @@ /* SoC level DTS fixup file */ -#define CONFIG_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS +#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS -#define CONFIG_GPIO_IMX_PORT_1_NAME DT_NXP_IMX_GPIO_30200000_LABEL -#define CONFIG_GPIO_IMX_PORT_1_BASE_ADDRESS DT_NXP_IMX_GPIO_30200000_BASE_ADDRESS -#define CONFIG_GPIO_IMX_PORT_1_IRQ_0 DT_NXP_IMX_GPIO_30200000_IRQ_0 -#define CONFIG_GPIO_IMX_PORT_1_IRQ_0_PRI DT_NXP_IMX_GPIO_30200000_IRQ_0_PRIORITY -#define CONFIG_GPIO_IMX_PORT_1_IRQ_1 DT_NXP_IMX_GPIO_30200000_IRQ_1 -#define CONFIG_GPIO_IMX_PORT_1_IRQ_1_PRI DT_NXP_IMX_GPIO_30200000_IRQ_1_PRIORITY +#define DT_GPIO_IMX_PORT_1_NAME DT_NXP_IMX_GPIO_30200000_LABEL +#define DT_GPIO_IMX_PORT_1_BASE_ADDRESS DT_NXP_IMX_GPIO_30200000_BASE_ADDRESS +#define DT_GPIO_IMX_PORT_1_IRQ_0 DT_NXP_IMX_GPIO_30200000_IRQ_0 +#define DT_GPIO_IMX_PORT_1_IRQ_0_PRI DT_NXP_IMX_GPIO_30200000_IRQ_0_PRIORITY +#define DT_GPIO_IMX_PORT_1_IRQ_1 DT_NXP_IMX_GPIO_30200000_IRQ_1 +#define DT_GPIO_IMX_PORT_1_IRQ_1_PRI DT_NXP_IMX_GPIO_30200000_IRQ_1_PRIORITY -#define CONFIG_GPIO_IMX_PORT_2_NAME DT_NXP_IMX_GPIO_30210000_LABEL -#define CONFIG_GPIO_IMX_PORT_2_BASE_ADDRESS DT_NXP_IMX_GPIO_30210000_BASE_ADDRESS -#define CONFIG_GPIO_IMX_PORT_2_IRQ_0 DT_NXP_IMX_GPIO_30210000_IRQ_0 -#define CONFIG_GPIO_IMX_PORT_2_IRQ_0_PRI DT_NXP_IMX_GPIO_30210000_IRQ_0_PRIORITY -#define CONFIG_GPIO_IMX_PORT_2_IRQ_1 DT_NXP_IMX_GPIO_30210000_IRQ_1 -#define CONFIG_GPIO_IMX_PORT_2_IRQ_1_PRI DT_NXP_IMX_GPIO_30210000_IRQ_1_PRIORITY +#define DT_GPIO_IMX_PORT_2_NAME DT_NXP_IMX_GPIO_30210000_LABEL +#define DT_GPIO_IMX_PORT_2_BASE_ADDRESS DT_NXP_IMX_GPIO_30210000_BASE_ADDRESS +#define DT_GPIO_IMX_PORT_2_IRQ_0 DT_NXP_IMX_GPIO_30210000_IRQ_0 +#define DT_GPIO_IMX_PORT_2_IRQ_0_PRI DT_NXP_IMX_GPIO_30210000_IRQ_0_PRIORITY +#define DT_GPIO_IMX_PORT_2_IRQ_1 DT_NXP_IMX_GPIO_30210000_IRQ_1 +#define DT_GPIO_IMX_PORT_2_IRQ_1_PRI DT_NXP_IMX_GPIO_30210000_IRQ_1_PRIORITY -#define CONFIG_GPIO_IMX_PORT_3_NAME DT_NXP_IMX_GPIO_30220000_LABEL -#define CONFIG_GPIO_IMX_PORT_3_BASE_ADDRESS DT_NXP_IMX_GPIO_30220000_BASE_ADDRESS -#define CONFIG_GPIO_IMX_PORT_3_IRQ_0 DT_NXP_IMX_GPIO_30220000_IRQ_0 -#define CONFIG_GPIO_IMX_PORT_3_IRQ_0_PRI DT_NXP_IMX_GPIO_30220000_IRQ_0_PRIORITY -#define CONFIG_GPIO_IMX_PORT_3_IRQ_1 DT_NXP_IMX_GPIO_30220000_IRQ_1 -#define CONFIG_GPIO_IMX_PORT_3_IRQ_1_PRI DT_NXP_IMX_GPIO_30220000_IRQ_1_PRIORITY +#define DT_GPIO_IMX_PORT_3_NAME DT_NXP_IMX_GPIO_30220000_LABEL +#define DT_GPIO_IMX_PORT_3_BASE_ADDRESS DT_NXP_IMX_GPIO_30220000_BASE_ADDRESS +#define DT_GPIO_IMX_PORT_3_IRQ_0 DT_NXP_IMX_GPIO_30220000_IRQ_0 +#define DT_GPIO_IMX_PORT_3_IRQ_0_PRI DT_NXP_IMX_GPIO_30220000_IRQ_0_PRIORITY +#define DT_GPIO_IMX_PORT_3_IRQ_1 DT_NXP_IMX_GPIO_30220000_IRQ_1 +#define DT_GPIO_IMX_PORT_3_IRQ_1_PRI DT_NXP_IMX_GPIO_30220000_IRQ_1_PRIORITY -#define CONFIG_GPIO_IMX_PORT_4_NAME DT_NXP_IMX_GPIO_30230000_LABEL -#define CONFIG_GPIO_IMX_PORT_4_BASE_ADDRESS DT_NXP_IMX_GPIO_30230000_BASE_ADDRESS -#define CONFIG_GPIO_IMX_PORT_4_IRQ_0 DT_NXP_IMX_GPIO_30230000_IRQ_0 -#define CONFIG_GPIO_IMX_PORT_4_IRQ_0_PRI DT_NXP_IMX_GPIO_30230000_IRQ_0_PRIORITY -#define CONFIG_GPIO_IMX_PORT_4_IRQ_1 DT_NXP_IMX_GPIO_30230000_IRQ_1 -#define CONFIG_GPIO_IMX_PORT_4_IRQ_1_PRI DT_NXP_IMX_GPIO_30230000_IRQ_1_PRIORITY +#define DT_GPIO_IMX_PORT_4_NAME DT_NXP_IMX_GPIO_30230000_LABEL +#define DT_GPIO_IMX_PORT_4_BASE_ADDRESS DT_NXP_IMX_GPIO_30230000_BASE_ADDRESS +#define DT_GPIO_IMX_PORT_4_IRQ_0 DT_NXP_IMX_GPIO_30230000_IRQ_0 +#define DT_GPIO_IMX_PORT_4_IRQ_0_PRI DT_NXP_IMX_GPIO_30230000_IRQ_0_PRIORITY +#define DT_GPIO_IMX_PORT_4_IRQ_1 DT_NXP_IMX_GPIO_30230000_IRQ_1 +#define DT_GPIO_IMX_PORT_4_IRQ_1_PRI DT_NXP_IMX_GPIO_30230000_IRQ_1_PRIORITY -#define CONFIG_GPIO_IMX_PORT_5_NAME DT_NXP_IMX_GPIO_30240000_LABEL -#define CONFIG_GPIO_IMX_PORT_5_BASE_ADDRESS DT_NXP_IMX_GPIO_30240000_BASE_ADDRESS -#define CONFIG_GPIO_IMX_PORT_5_IRQ_0 DT_NXP_IMX_GPIO_30240000_IRQ_0 -#define CONFIG_GPIO_IMX_PORT_5_IRQ_0_PRI DT_NXP_IMX_GPIO_30240000_IRQ_0_PRIORITY -#define CONFIG_GPIO_IMX_PORT_5_IRQ_1 DT_NXP_IMX_GPIO_30240000_IRQ_1 -#define CONFIG_GPIO_IMX_PORT_5_IRQ_1_PRI DT_NXP_IMX_GPIO_30240000_IRQ_1_PRIORITY +#define DT_GPIO_IMX_PORT_5_NAME DT_NXP_IMX_GPIO_30240000_LABEL +#define DT_GPIO_IMX_PORT_5_BASE_ADDRESS DT_NXP_IMX_GPIO_30240000_BASE_ADDRESS +#define DT_GPIO_IMX_PORT_5_IRQ_0 DT_NXP_IMX_GPIO_30240000_IRQ_0 +#define DT_GPIO_IMX_PORT_5_IRQ_0_PRI DT_NXP_IMX_GPIO_30240000_IRQ_0_PRIORITY +#define DT_GPIO_IMX_PORT_5_IRQ_1 DT_NXP_IMX_GPIO_30240000_IRQ_1 +#define DT_GPIO_IMX_PORT_5_IRQ_1_PRI DT_NXP_IMX_GPIO_30240000_IRQ_1_PRIORITY -#define CONFIG_GPIO_IMX_PORT_6_NAME DT_NXP_IMX_GPIO_30250000_LABEL -#define CONFIG_GPIO_IMX_PORT_6_BASE_ADDRESS DT_NXP_IMX_GPIO_30250000_BASE_ADDRESS -#define CONFIG_GPIO_IMX_PORT_6_IRQ_0 DT_NXP_IMX_GPIO_30250000_IRQ_0 -#define CONFIG_GPIO_IMX_PORT_6_IRQ_0_PRI DT_NXP_IMX_GPIO_30250000_IRQ_0_PRIORITY -#define CONFIG_GPIO_IMX_PORT_6_IRQ_1 DT_NXP_IMX_GPIO_30250000_IRQ_1 -#define CONFIG_GPIO_IMX_PORT_6_IRQ_1_PRI DT_NXP_IMX_GPIO_30250000_IRQ_1_PRIORITY +#define DT_GPIO_IMX_PORT_6_NAME DT_NXP_IMX_GPIO_30250000_LABEL +#define DT_GPIO_IMX_PORT_6_BASE_ADDRESS DT_NXP_IMX_GPIO_30250000_BASE_ADDRESS +#define DT_GPIO_IMX_PORT_6_IRQ_0 DT_NXP_IMX_GPIO_30250000_IRQ_0 +#define DT_GPIO_IMX_PORT_6_IRQ_0_PRI DT_NXP_IMX_GPIO_30250000_IRQ_0_PRIORITY +#define DT_GPIO_IMX_PORT_6_IRQ_1 DT_NXP_IMX_GPIO_30250000_IRQ_1 +#define DT_GPIO_IMX_PORT_6_IRQ_1_PRI DT_NXP_IMX_GPIO_30250000_IRQ_1_PRIORITY -#define CONFIG_GPIO_IMX_PORT_7_NAME DT_NXP_IMX_GPIO_30260000_LABEL -#define CONFIG_GPIO_IMX_PORT_7_BASE_ADDRESS DT_NXP_IMX_GPIO_30260000_BASE_ADDRESS -#define CONFIG_GPIO_IMX_PORT_7_IRQ_0 DT_NXP_IMX_GPIO_30260000_IRQ_0 -#define CONFIG_GPIO_IMX_PORT_7_IRQ_0_PRI DT_NXP_IMX_GPIO_30260000_IRQ_0_PRIORITY -#define CONFIG_GPIO_IMX_PORT_7_IRQ_1 DT_NXP_IMX_GPIO_30260000_IRQ_1 -#define CONFIG_GPIO_IMX_PORT_7_IRQ_1_PRI DT_NXP_IMX_GPIO_30260000_IRQ_1_PRIORITY +#define DT_GPIO_IMX_PORT_7_NAME DT_NXP_IMX_GPIO_30260000_LABEL +#define DT_GPIO_IMX_PORT_7_BASE_ADDRESS DT_NXP_IMX_GPIO_30260000_BASE_ADDRESS +#define DT_GPIO_IMX_PORT_7_IRQ_0 DT_NXP_IMX_GPIO_30260000_IRQ_0 +#define DT_GPIO_IMX_PORT_7_IRQ_0_PRI DT_NXP_IMX_GPIO_30260000_IRQ_0_PRIORITY +#define DT_GPIO_IMX_PORT_7_IRQ_1 DT_NXP_IMX_GPIO_30260000_IRQ_1 +#define DT_GPIO_IMX_PORT_7_IRQ_1_PRI DT_NXP_IMX_GPIO_30260000_IRQ_1_PRIORITY -#define CONFIG_UART_IMX_UART_1_NAME DT_NXP_IMX_UART_30860000_LABEL -#define CONFIG_UART_IMX_UART_1_BASE_ADDRESS DT_NXP_IMX_UART_30860000_BASE_ADDRESS -#define CONFIG_UART_IMX_UART_1_BAUD_RATE DT_NXP_IMX_UART_30860000_CURRENT_SPEED -#define CONFIG_UART_IMX_UART_1_IRQ_NUM DT_NXP_IMX_UART_30860000_IRQ_0 -#define CONFIG_UART_IMX_UART_1_IRQ_PRI DT_NXP_IMX_UART_30860000_IRQ_0_PRIORITY -#define CONFIG_UART_IMX_UART_1_MODEM_MODE DT_NXP_IMX_UART_30860000_MODEM_MODE +#define DT_UART_IMX_UART_1_NAME DT_NXP_IMX_UART_30860000_LABEL +#define DT_UART_IMX_UART_1_BASE_ADDRESS DT_NXP_IMX_UART_30860000_BASE_ADDRESS +#define DT_UART_IMX_UART_1_BAUD_RATE DT_NXP_IMX_UART_30860000_CURRENT_SPEED +#define DT_UART_IMX_UART_1_IRQ_NUM DT_NXP_IMX_UART_30860000_IRQ_0 +#define DT_UART_IMX_UART_1_IRQ_PRI DT_NXP_IMX_UART_30860000_IRQ_0_PRIORITY +#define DT_UART_IMX_UART_1_MODEM_MODE DT_NXP_IMX_UART_30860000_MODEM_MODE -#define CONFIG_UART_IMX_UART_2_NAME DT_NXP_IMX_UART_30890000_LABEL -#define CONFIG_UART_IMX_UART_2_BASE_ADDRESS DT_NXP_IMX_UART_30890000_BASE_ADDRESS -#define CONFIG_UART_IMX_UART_2_BAUD_RATE DT_NXP_IMX_UART_30890000_CURRENT_SPEED -#define CONFIG_UART_IMX_UART_2_IRQ_NUM DT_NXP_IMX_UART_30890000_IRQ_0 -#define CONFIG_UART_IMX_UART_2_IRQ_PRI DT_NXP_IMX_UART_30890000_IRQ_0_PRIORITY -#define CONFIG_UART_IMX_UART_2_MODEM_MODE DT_NXP_IMX_UART_30890000_MODEM_MODE +#define DT_UART_IMX_UART_2_NAME DT_NXP_IMX_UART_30890000_LABEL +#define DT_UART_IMX_UART_2_BASE_ADDRESS DT_NXP_IMX_UART_30890000_BASE_ADDRESS +#define DT_UART_IMX_UART_2_BAUD_RATE DT_NXP_IMX_UART_30890000_CURRENT_SPEED +#define DT_UART_IMX_UART_2_IRQ_NUM DT_NXP_IMX_UART_30890000_IRQ_0 +#define DT_UART_IMX_UART_2_IRQ_PRI DT_NXP_IMX_UART_30890000_IRQ_0_PRIORITY +#define DT_UART_IMX_UART_2_MODEM_MODE DT_NXP_IMX_UART_30890000_MODEM_MODE -#define CONFIG_UART_IMX_UART_3_NAME DT_NXP_IMX_UART_30880000_LABEL -#define CONFIG_UART_IMX_UART_3_BASE_ADDRESS DT_NXP_IMX_UART_30880000_BASE_ADDRESS -#define CONFIG_UART_IMX_UART_3_BAUD_RATE DT_NXP_IMX_UART_30880000_CURRENT_SPEED -#define CONFIG_UART_IMX_UART_3_IRQ_NUM DT_NXP_IMX_UART_30880000_IRQ_0 -#define CONFIG_UART_IMX_UART_3_IRQ_PRI DT_NXP_IMX_UART_30880000_IRQ_0_PRIORITY -#define CONFIG_UART_IMX_UART_3_MODEM_MODE DT_NXP_IMX_UART_30880000_MODEM_MODE +#define DT_UART_IMX_UART_3_NAME DT_NXP_IMX_UART_30880000_LABEL +#define DT_UART_IMX_UART_3_BASE_ADDRESS DT_NXP_IMX_UART_30880000_BASE_ADDRESS +#define DT_UART_IMX_UART_3_BAUD_RATE DT_NXP_IMX_UART_30880000_CURRENT_SPEED +#define DT_UART_IMX_UART_3_IRQ_NUM DT_NXP_IMX_UART_30880000_IRQ_0 +#define DT_UART_IMX_UART_3_IRQ_PRI DT_NXP_IMX_UART_30880000_IRQ_0_PRIORITY +#define DT_UART_IMX_UART_3_MODEM_MODE DT_NXP_IMX_UART_30880000_MODEM_MODE -#define CONFIG_UART_IMX_UART_4_NAME DT_NXP_IMX_UART_30A60000_LABEL -#define CONFIG_UART_IMX_UART_4_BASE_ADDRESS DT_NXP_IMX_UART_30A60000_BASE_ADDRESS -#define CONFIG_UART_IMX_UART_4_BAUD_RATE DT_NXP_IMX_UART_30A60000_CURRENT_SPEED -#define CONFIG_UART_IMX_UART_4_IRQ_NUM DT_NXP_IMX_UART_30A60000_IRQ_0 -#define CONFIG_UART_IMX_UART_4_IRQ_PRI DT_NXP_IMX_UART_30A60000_IRQ_0_PRIORITY -#define CONFIG_UART_IMX_UART_4_MODEM_MODE DT_NXP_IMX_UART_30A60000_MODEM_MODE +#define DT_UART_IMX_UART_4_NAME DT_NXP_IMX_UART_30A60000_LABEL +#define DT_UART_IMX_UART_4_BASE_ADDRESS DT_NXP_IMX_UART_30A60000_BASE_ADDRESS +#define DT_UART_IMX_UART_4_BAUD_RATE DT_NXP_IMX_UART_30A60000_CURRENT_SPEED +#define DT_UART_IMX_UART_4_IRQ_NUM DT_NXP_IMX_UART_30A60000_IRQ_0 +#define DT_UART_IMX_UART_4_IRQ_PRI DT_NXP_IMX_UART_30A60000_IRQ_0_PRIORITY +#define DT_UART_IMX_UART_4_MODEM_MODE DT_NXP_IMX_UART_30A60000_MODEM_MODE -#define CONFIG_UART_IMX_UART_5_NAME DT_NXP_IMX_UART_30A70000_LABEL -#define CONFIG_UART_IMX_UART_5_BASE_ADDRESS DT_NXP_IMX_UART_30A70000_BASE_ADDRESS -#define CONFIG_UART_IMX_UART_5_BAUD_RATE DT_NXP_IMX_UART_30A70000_CURRENT_SPEED -#define CONFIG_UART_IMX_UART_5_IRQ_NUM DT_NXP_IMX_UART_30A70000_IRQ_0 -#define CONFIG_UART_IMX_UART_5_IRQ_PRI DT_NXP_IMX_UART_30A70000_IRQ_0_PRIORITY -#define CONFIG_UART_IMX_UART_5_MODEM_MODE DT_NXP_IMX_UART_30A70000_MODEM_MODE +#define DT_UART_IMX_UART_5_NAME DT_NXP_IMX_UART_30A70000_LABEL +#define DT_UART_IMX_UART_5_BASE_ADDRESS DT_NXP_IMX_UART_30A70000_BASE_ADDRESS +#define DT_UART_IMX_UART_5_BAUD_RATE DT_NXP_IMX_UART_30A70000_CURRENT_SPEED +#define DT_UART_IMX_UART_5_IRQ_NUM DT_NXP_IMX_UART_30A70000_IRQ_0 +#define DT_UART_IMX_UART_5_IRQ_PRI DT_NXP_IMX_UART_30A70000_IRQ_0_PRIORITY +#define DT_UART_IMX_UART_5_MODEM_MODE DT_NXP_IMX_UART_30A70000_MODEM_MODE -#define CONFIG_UART_IMX_UART_6_NAME DT_NXP_IMX_UART_30A80000_LABEL -#define CONFIG_UART_IMX_UART_6_BASE_ADDRESS DT_NXP_IMX_UART_30A80000_BASE_ADDRESS -#define CONFIG_UART_IMX_UART_6_BAUD_RATE DT_NXP_IMX_UART_30A80000_CURRENT_SPEED -#define CONFIG_UART_IMX_UART_6_IRQ_NUM DT_NXP_IMX_UART_30A80000_IRQ_0 -#define CONFIG_UART_IMX_UART_6_IRQ_PRI DT_NXP_IMX_UART_30A80000_IRQ_0_PRIORITY -#define CONFIG_UART_IMX_UART_6_MODEM_MODE DT_NXP_IMX_UART_30A80000_MODEM_MODE +#define DT_UART_IMX_UART_6_NAME DT_NXP_IMX_UART_30A80000_LABEL +#define DT_UART_IMX_UART_6_BASE_ADDRESS DT_NXP_IMX_UART_30A80000_BASE_ADDRESS +#define DT_UART_IMX_UART_6_BAUD_RATE DT_NXP_IMX_UART_30A80000_CURRENT_SPEED +#define DT_UART_IMX_UART_6_IRQ_NUM DT_NXP_IMX_UART_30A80000_IRQ_0 +#define DT_UART_IMX_UART_6_IRQ_PRI DT_NXP_IMX_UART_30A80000_IRQ_0_PRIORITY +#define DT_UART_IMX_UART_6_MODEM_MODE DT_NXP_IMX_UART_30A80000_MODEM_MODE -#define CONFIG_UART_IMX_UART_7_NAME DT_NXP_IMX_UART_30A90000_LABEL -#define CONFIG_UART_IMX_UART_7_BASE_ADDRESS DT_NXP_IMX_UART_30A90000_BASE_ADDRESS -#define CONFIG_UART_IMX_UART_7_BAUD_RATE DT_NXP_IMX_UART_30A90000_CURRENT_SPEED -#define CONFIG_UART_IMX_UART_7_IRQ_NUM DT_NXP_IMX_UART_30A90000_IRQ_0 -#define CONFIG_UART_IMX_UART_7_IRQ_PRI DT_NXP_IMX_UART_30A90000_IRQ_0_PRIORITY -#define CONFIG_UART_IMX_UART_7_MODEM_MODE DT_NXP_IMX_UART_30A90000_MODEM_MODE +#define DT_UART_IMX_UART_7_NAME DT_NXP_IMX_UART_30A90000_LABEL +#define DT_UART_IMX_UART_7_BASE_ADDRESS DT_NXP_IMX_UART_30A90000_BASE_ADDRESS +#define DT_UART_IMX_UART_7_BAUD_RATE DT_NXP_IMX_UART_30A90000_CURRENT_SPEED +#define DT_UART_IMX_UART_7_IRQ_NUM DT_NXP_IMX_UART_30A90000_IRQ_0 +#define DT_UART_IMX_UART_7_IRQ_PRI DT_NXP_IMX_UART_30A90000_IRQ_0_PRIORITY +#define DT_UART_IMX_UART_7_MODEM_MODE DT_NXP_IMX_UART_30A90000_MODEM_MODE /* End of SoC Level DTS fixup file */ diff --git a/soc/arm/nxp_imx/rt/dts_fixup.h b/soc/arm/nxp_imx/rt/dts_fixup.h index 0d530ffdbfe..ec3efcf68fd 100644 --- a/soc/arm/nxp_imx/rt/dts_fixup.h +++ b/soc/arm/nxp_imx/rt/dts_fixup.h @@ -6,39 +6,39 @@ /* SoC level DTS fixup file */ -#define CONFIG_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS +#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS -#define CONFIG_MCUX_CCM_BASE_ADDRESS DT_NXP_IMX_CCM_400FC000_BASE_ADDRESS -#define CONFIG_MCUX_CCM_NAME DT_NXP_IMX_CCM_400FC000_LABEL +#define DT_MCUX_CCM_BASE_ADDRESS DT_NXP_IMX_CCM_400FC000_BASE_ADDRESS +#define DT_MCUX_CCM_NAME DT_NXP_IMX_CCM_400FC000_LABEL -#define CONFIG_MCUX_IGPIO_1_BASE_ADDRESS DT_NXP_IMX_GPIO_401B8000_BASE_ADDRESS -#define CONFIG_MCUX_IGPIO_1_NAME DT_NXP_IMX_GPIO_401B8000_LABEL -#define CONFIG_MCUX_IGPIO_1_IRQ_0 DT_NXP_IMX_GPIO_401B8000_IRQ_0 -#define CONFIG_MCUX_IGPIO_1_IRQ_0_PRI DT_NXP_IMX_GPIO_401B8000_IRQ_0_PRIORITY -#define CONFIG_MCUX_IGPIO_1_IRQ_1 DT_NXP_IMX_GPIO_401B8000_IRQ_1 -#define CONFIG_MCUX_IGPIO_1_IRQ_1_PRI DT_NXP_IMX_GPIO_401B8000_IRQ_1_PRIORITY +#define DT_MCUX_IGPIO_1_BASE_ADDRESS DT_NXP_IMX_GPIO_401B8000_BASE_ADDRESS +#define DT_MCUX_IGPIO_1_NAME DT_NXP_IMX_GPIO_401B8000_LABEL +#define DT_MCUX_IGPIO_1_IRQ_0 DT_NXP_IMX_GPIO_401B8000_IRQ_0 +#define DT_MCUX_IGPIO_1_IRQ_0_PRI DT_NXP_IMX_GPIO_401B8000_IRQ_0_PRIORITY +#define DT_MCUX_IGPIO_1_IRQ_1 DT_NXP_IMX_GPIO_401B8000_IRQ_1 +#define DT_MCUX_IGPIO_1_IRQ_1_PRI DT_NXP_IMX_GPIO_401B8000_IRQ_1_PRIORITY -#define CONFIG_MCUX_IGPIO_5_BASE_ADDRESS DT_NXP_IMX_GPIO_400C0000_BASE_ADDRESS -#define CONFIG_MCUX_IGPIO_5_NAME DT_NXP_IMX_GPIO_400C0000_LABEL -#define CONFIG_MCUX_IGPIO_5_IRQ_0 DT_NXP_IMX_GPIO_400C0000_IRQ_0 -#define CONFIG_MCUX_IGPIO_5_IRQ_0_PRI DT_NXP_IMX_GPIO_400C0000_IRQ_0_PRIORITY -#define CONFIG_MCUX_IGPIO_5_IRQ_1 DT_NXP_IMX_GPIO_400C0000_IRQ_1 -#define CONFIG_MCUX_IGPIO_5_IRQ_1_PRI DT_NXP_IMX_GPIO_400C0000_IRQ_1_PRIORITY +#define DT_MCUX_IGPIO_5_BASE_ADDRESS DT_NXP_IMX_GPIO_400C0000_BASE_ADDRESS +#define DT_MCUX_IGPIO_5_NAME DT_NXP_IMX_GPIO_400C0000_LABEL +#define DT_MCUX_IGPIO_5_IRQ_0 DT_NXP_IMX_GPIO_400C0000_IRQ_0 +#define DT_MCUX_IGPIO_5_IRQ_0_PRI DT_NXP_IMX_GPIO_400C0000_IRQ_0_PRIORITY +#define DT_MCUX_IGPIO_5_IRQ_1 DT_NXP_IMX_GPIO_400C0000_IRQ_1 +#define DT_MCUX_IGPIO_5_IRQ_1_PRI DT_NXP_IMX_GPIO_400C0000_IRQ_1_PRIORITY -#define CONFIG_UART_MCUX_LPUART_1_BASE_ADDRESS DT_NXP_KINETIS_LPUART_40184000_BASE_ADDRESS -#define CONFIG_UART_MCUX_LPUART_1_NAME DT_NXP_KINETIS_LPUART_40184000_LABEL -#define CONFIG_UART_MCUX_LPUART_1_IRQ DT_NXP_KINETIS_LPUART_40184000_IRQ_0 -#define CONFIG_UART_MCUX_LPUART_1_IRQ_PRI DT_NXP_KINETIS_LPUART_40184000_IRQ_0_PRIORITY -#define CONFIG_UART_MCUX_LPUART_1_BAUD_RATE DT_NXP_KINETIS_LPUART_40184000_CURRENT_SPEED -#define CONFIG_UART_MCUX_LPUART_1_CLOCK_NAME DT_NXP_KINETIS_LPUART_40184000_CLOCK_CONTROLLER -#define CONFIG_UART_MCUX_LPUART_1_CLOCK_SUBSYS DT_NXP_KINETIS_LPUART_40184000_CLOCK_NAME +#define DT_UART_MCUX_LPUART_1_BASE_ADDRESS DT_NXP_KINETIS_LPUART_40184000_BASE_ADDRESS +#define DT_UART_MCUX_LPUART_1_NAME DT_NXP_KINETIS_LPUART_40184000_LABEL +#define DT_UART_MCUX_LPUART_1_IRQ DT_NXP_KINETIS_LPUART_40184000_IRQ_0 +#define DT_UART_MCUX_LPUART_1_IRQ_PRI DT_NXP_KINETIS_LPUART_40184000_IRQ_0_PRIORITY +#define DT_UART_MCUX_LPUART_1_BAUD_RATE DT_NXP_KINETIS_LPUART_40184000_CURRENT_SPEED +#define DT_UART_MCUX_LPUART_1_CLOCK_NAME DT_NXP_KINETIS_LPUART_40184000_CLOCK_CONTROLLER +#define DT_UART_MCUX_LPUART_1_CLOCK_SUBSYS DT_NXP_KINETIS_LPUART_40184000_CLOCK_NAME -#define CONFIG_UART_MCUX_LPUART_3_BASE_ADDRESS DT_NXP_KINETIS_LPUART_4018C000_BASE_ADDRESS -#define CONFIG_UART_MCUX_LPUART_3_NAME DT_NXP_KINETIS_LPUART_4018C000_LABEL -#define CONFIG_UART_MCUX_LPUART_3_IRQ DT_NXP_KINETIS_LPUART_4018C000_IRQ_0 -#define CONFIG_UART_MCUX_LPUART_3_IRQ_PRI DT_NXP_KINETIS_LPUART_4018C000_IRQ_0_PRIORITY -#define CONFIG_UART_MCUX_LPUART_3_BAUD_RATE DT_NXP_KINETIS_LPUART_4018C000_CURRENT_SPEED -#define CONFIG_UART_MCUX_LPUART_3_CLOCK_NAME DT_NXP_KINETIS_LPUART_4018C000_CLOCK_CONTROLLER -#define CONFIG_UART_MCUX_LPUART_3_CLOCK_SUBSYS DT_NXP_KINETIS_LPUART_4018C000_CLOCK_NAME +#define DT_UART_MCUX_LPUART_3_BASE_ADDRESS DT_NXP_KINETIS_LPUART_4018C000_BASE_ADDRESS +#define DT_UART_MCUX_LPUART_3_NAME DT_NXP_KINETIS_LPUART_4018C000_LABEL +#define DT_UART_MCUX_LPUART_3_IRQ DT_NXP_KINETIS_LPUART_4018C000_IRQ_0 +#define DT_UART_MCUX_LPUART_3_IRQ_PRI DT_NXP_KINETIS_LPUART_4018C000_IRQ_0_PRIORITY +#define DT_UART_MCUX_LPUART_3_BAUD_RATE DT_NXP_KINETIS_LPUART_4018C000_CURRENT_SPEED +#define DT_UART_MCUX_LPUART_3_CLOCK_NAME DT_NXP_KINETIS_LPUART_4018C000_CLOCK_CONTROLLER +#define DT_UART_MCUX_LPUART_3_CLOCK_SUBSYS DT_NXP_KINETIS_LPUART_4018C000_CLOCK_NAME /* End of SoC Level DTS fixup file */ diff --git a/soc/arm/nxp_kinetis/k6x/dts_fixup.h b/soc/arm/nxp_kinetis/k6x/dts_fixup.h index 7576e871d9c..603f8c270c6 100644 --- a/soc/arm/nxp_kinetis/k6x/dts_fixup.h +++ b/soc/arm/nxp_kinetis/k6x/dts_fixup.h @@ -1,144 +1,144 @@ /* SoC level DTS fixup file */ -#define CONFIG_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS +#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS -#define CONFIG_UART_MCUX_0_BAUD_RATE DT_NXP_KINETIS_UART_4006A000_CURRENT_SPEED -#define CONFIG_UART_MCUX_0_NAME DT_NXP_KINETIS_UART_4006A000_LABEL -#define CONFIG_UART_MCUX_0_IRQ_ERROR DT_NXP_KINETIS_UART_4006A000_IRQ_ERROR -#define CONFIG_UART_MCUX_0_IRQ_ERROR_PRI DT_NXP_KINETIS_UART_4006A000_IRQ_ERROR_PRIORITY -#define CONFIG_UART_MCUX_0_IRQ_STATUS DT_NXP_KINETIS_UART_4006A000_IRQ_STATUS -#define CONFIG_UART_MCUX_0_IRQ_STATUS_PRI DT_NXP_KINETIS_UART_4006A000_IRQ_STATUS_PRIORITY -#define CONFIG_UART_MCUX_0_CLOCK_NAME DT_NXP_KINETIS_UART_4006A000_CLOCK_CONTROLLER -#define CONFIG_UART_MCUX_0_CLOCK_SUBSYS DT_NXP_KINETIS_UART_4006A000_CLOCK_NAME +#define DT_UART_MCUX_0_BAUD_RATE DT_NXP_KINETIS_UART_4006A000_CURRENT_SPEED +#define DT_UART_MCUX_0_NAME DT_NXP_KINETIS_UART_4006A000_LABEL +#define DT_UART_MCUX_0_IRQ_ERROR DT_NXP_KINETIS_UART_4006A000_IRQ_ERROR +#define DT_UART_MCUX_0_IRQ_ERROR_PRI DT_NXP_KINETIS_UART_4006A000_IRQ_ERROR_PRIORITY +#define DT_UART_MCUX_0_IRQ_STATUS DT_NXP_KINETIS_UART_4006A000_IRQ_STATUS +#define DT_UART_MCUX_0_IRQ_STATUS_PRI DT_NXP_KINETIS_UART_4006A000_IRQ_STATUS_PRIORITY +#define DT_UART_MCUX_0_CLOCK_NAME DT_NXP_KINETIS_UART_4006A000_CLOCK_CONTROLLER +#define DT_UART_MCUX_0_CLOCK_SUBSYS DT_NXP_KINETIS_UART_4006A000_CLOCK_NAME -#define CONFIG_UART_MCUX_1_BAUD_RATE DT_NXP_KINETIS_UART_4006B000_CURRENT_SPEED -#define CONFIG_UART_MCUX_1_NAME DT_NXP_KINETIS_UART_4006B000_LABEL -#define CONFIG_UART_MCUX_1_IRQ_ERROR DT_NXP_KINETIS_UART_4006B000_IRQ_ERROR -#define CONFIG_UART_MCUX_1_IRQ_ERROR_PRI DT_NXP_KINETIS_UART_4006B000_IRQ_ERROR_PRIORITY -#define CONFIG_UART_MCUX_1_IRQ_STATUS DT_NXP_KINETIS_UART_4006B000_IRQ_STATUS -#define CONFIG_UART_MCUX_1_IRQ_STATUS_PRI DT_NXP_KINETIS_UART_4006B000_IRQ_STATUS_PRIORITY -#define CONFIG_UART_MCUX_1_CLOCK_NAME DT_NXP_KINETIS_UART_4006B000_CLOCK_CONTROLLER -#define CONFIG_UART_MCUX_1_CLOCK_SUBSYS DT_NXP_KINETIS_UART_4006B000_CLOCK_NAME +#define DT_UART_MCUX_1_BAUD_RATE DT_NXP_KINETIS_UART_4006B000_CURRENT_SPEED +#define DT_UART_MCUX_1_NAME DT_NXP_KINETIS_UART_4006B000_LABEL +#define DT_UART_MCUX_1_IRQ_ERROR DT_NXP_KINETIS_UART_4006B000_IRQ_ERROR +#define DT_UART_MCUX_1_IRQ_ERROR_PRI DT_NXP_KINETIS_UART_4006B000_IRQ_ERROR_PRIORITY +#define DT_UART_MCUX_1_IRQ_STATUS DT_NXP_KINETIS_UART_4006B000_IRQ_STATUS +#define DT_UART_MCUX_1_IRQ_STATUS_PRI DT_NXP_KINETIS_UART_4006B000_IRQ_STATUS_PRIORITY +#define DT_UART_MCUX_1_CLOCK_NAME DT_NXP_KINETIS_UART_4006B000_CLOCK_CONTROLLER +#define DT_UART_MCUX_1_CLOCK_SUBSYS DT_NXP_KINETIS_UART_4006B000_CLOCK_NAME -#define CONFIG_UART_MCUX_2_BAUD_RATE DT_NXP_KINETIS_UART_4006C000_CURRENT_SPEED -#define CONFIG_UART_MCUX_2_NAME DT_NXP_KINETIS_UART_4006C000_LABEL -#define CONFIG_UART_MCUX_2_IRQ_ERROR DT_NXP_KINETIS_UART_4006C000_IRQ_ERROR -#define CONFIG_UART_MCUX_2_IRQ_ERROR_PRI DT_NXP_KINETIS_UART_4006C000_IRQ_ERROR_PRIORITY -#define CONFIG_UART_MCUX_2_IRQ_STATUS DT_NXP_KINETIS_UART_4006C000_IRQ_STATUS -#define CONFIG_UART_MCUX_2_IRQ_STATUS_PRI DT_NXP_KINETIS_UART_4006C000_IRQ_STATUS_PRIORITY -#define CONFIG_UART_MCUX_2_CLOCK_NAME DT_NXP_KINETIS_UART_4006C000_CLOCK_CONTROLLER -#define CONFIG_UART_MCUX_2_CLOCK_SUBSYS DT_NXP_KINETIS_UART_4006C000_CLOCK_NAME +#define DT_UART_MCUX_2_BAUD_RATE DT_NXP_KINETIS_UART_4006C000_CURRENT_SPEED +#define DT_UART_MCUX_2_NAME DT_NXP_KINETIS_UART_4006C000_LABEL +#define DT_UART_MCUX_2_IRQ_ERROR DT_NXP_KINETIS_UART_4006C000_IRQ_ERROR +#define DT_UART_MCUX_2_IRQ_ERROR_PRI DT_NXP_KINETIS_UART_4006C000_IRQ_ERROR_PRIORITY +#define DT_UART_MCUX_2_IRQ_STATUS DT_NXP_KINETIS_UART_4006C000_IRQ_STATUS +#define DT_UART_MCUX_2_IRQ_STATUS_PRI DT_NXP_KINETIS_UART_4006C000_IRQ_STATUS_PRIORITY +#define DT_UART_MCUX_2_CLOCK_NAME DT_NXP_KINETIS_UART_4006C000_CLOCK_CONTROLLER +#define DT_UART_MCUX_2_CLOCK_SUBSYS DT_NXP_KINETIS_UART_4006C000_CLOCK_NAME -#define CONFIG_UART_MCUX_3_BAUD_RATE DT_NXP_KINETIS_UART_4006D000_CURRENT_SPEED -#define CONFIG_UART_MCUX_3_NAME DT_NXP_KINETIS_UART_4006D000_LABEL -#define CONFIG_UART_MCUX_3_IRQ_ERROR DT_NXP_KINETIS_UART_4006D000_IRQ_ERROR -#define CONFIG_UART_MCUX_3_IRQ_ERROR_PRI DT_NXP_KINETIS_UART_4006D000_IRQ_ERROR_PRIORITY -#define CONFIG_UART_MCUX_3_IRQ_STATUS DT_NXP_KINETIS_UART_4006D000_IRQ_STATUS -#define CONFIG_UART_MCUX_3_IRQ_STATUS_PRI DT_NXP_KINETIS_UART_4006D000_IRQ_STATUS_PRIORITY -#define CONFIG_UART_MCUX_3_CLOCK_NAME DT_NXP_KINETIS_UART_4006D000_CLOCK_CONTROLLER -#define CONFIG_UART_MCUX_3_CLOCK_SUBSYS DT_NXP_KINETIS_UART_4006D000_CLOCK_NAME +#define DT_UART_MCUX_3_BAUD_RATE DT_NXP_KINETIS_UART_4006D000_CURRENT_SPEED +#define DT_UART_MCUX_3_NAME DT_NXP_KINETIS_UART_4006D000_LABEL +#define DT_UART_MCUX_3_IRQ_ERROR DT_NXP_KINETIS_UART_4006D000_IRQ_ERROR +#define DT_UART_MCUX_3_IRQ_ERROR_PRI DT_NXP_KINETIS_UART_4006D000_IRQ_ERROR_PRIORITY +#define DT_UART_MCUX_3_IRQ_STATUS DT_NXP_KINETIS_UART_4006D000_IRQ_STATUS +#define DT_UART_MCUX_3_IRQ_STATUS_PRI DT_NXP_KINETIS_UART_4006D000_IRQ_STATUS_PRIORITY +#define DT_UART_MCUX_3_CLOCK_NAME DT_NXP_KINETIS_UART_4006D000_CLOCK_CONTROLLER +#define DT_UART_MCUX_3_CLOCK_SUBSYS DT_NXP_KINETIS_UART_4006D000_CLOCK_NAME -#define CONFIG_UART_MCUX_4_BAUD_RATE DT_NXP_KINETIS_UART_400EA000_CURRENT_SPEED -#define CONFIG_UART_MCUX_4_NAME DT_NXP_KINETIS_UART_400EA000_LABEL -#define CONFIG_UART_MCUX_4_IRQ_ERROR DT_NXP_KINETIS_UART_400EA000_IRQ_ERROR -#define CONFIG_UART_MCUX_4_IRQ_ERROR_PRI DT_NXP_KINETIS_UART_400EA000_IRQ_ERROR_PRIORITY -#define CONFIG_UART_MCUX_4_IRQ_STATUS DT_NXP_KINETIS_UART_400EA000_IRQ_STATUS -#define CONFIG_UART_MCUX_4_IRQ_STATUS_PRI DT_NXP_KINETIS_UART_400EA000_IRQ_STATUS_PRIORITY -#define CONFIG_UART_MCUX_4_CLOCK_NAME DT_NXP_KINETIS_UART_400EA000_CLOCK_CONTROLLER -#define CONFIG_UART_MCUX_4_CLOCK_SUBSYS DT_NXP_KINETIS_UART_400EA000_CLOCK_NAME +#define DT_UART_MCUX_4_BAUD_RATE DT_NXP_KINETIS_UART_400EA000_CURRENT_SPEED +#define DT_UART_MCUX_4_NAME DT_NXP_KINETIS_UART_400EA000_LABEL +#define DT_UART_MCUX_4_IRQ_ERROR DT_NXP_KINETIS_UART_400EA000_IRQ_ERROR +#define DT_UART_MCUX_4_IRQ_ERROR_PRI DT_NXP_KINETIS_UART_400EA000_IRQ_ERROR_PRIORITY +#define DT_UART_MCUX_4_IRQ_STATUS DT_NXP_KINETIS_UART_400EA000_IRQ_STATUS +#define DT_UART_MCUX_4_IRQ_STATUS_PRI DT_NXP_KINETIS_UART_400EA000_IRQ_STATUS_PRIORITY +#define DT_UART_MCUX_4_CLOCK_NAME DT_NXP_KINETIS_UART_400EA000_CLOCK_CONTROLLER +#define DT_UART_MCUX_4_CLOCK_SUBSYS DT_NXP_KINETIS_UART_400EA000_CLOCK_NAME -#define CONFIG_UART_MCUX_5_BAUD_RATE DT_NXP_KINETIS_UART_400EB000_CURRENT_SPEED -#define CONFIG_UART_MCUX_5_NAME DT_NXP_KINETIS_UART_400EB000_LABEL -#define CONFIG_UART_MCUX_5_IRQ_ERROR DT_NXP_KINETIS_UART_400EB000_IRQ_ERROR -#define CONFIG_UART_MCUX_5_IRQ_ERROR_PRI DT_NXP_KINETIS_UART_400EB000_IRQ_ERROR_PRIORITY -#define CONFIG_UART_MCUX_5_IRQ_STATUS DT_NXP_KINETIS_UART_400EB000_IRQ_STATUS -#define CONFIG_UART_MCUX_5_IRQ_STATUS_PRI DT_NXP_KINETIS_UART_400EB000_IRQ_STATUS_PRIORITY -#define CONFIG_UART_MCUX_5_CLOCK_NAME DT_NXP_KINETIS_UART_400EB000_CLOCK_CONTROLLER -#define CONFIG_UART_MCUX_5_CLOCK_SUBSYS DT_NXP_KINETIS_UART_400EB000_CLOCK_NAME +#define DT_UART_MCUX_5_BAUD_RATE DT_NXP_KINETIS_UART_400EB000_CURRENT_SPEED +#define DT_UART_MCUX_5_NAME DT_NXP_KINETIS_UART_400EB000_LABEL +#define DT_UART_MCUX_5_IRQ_ERROR DT_NXP_KINETIS_UART_400EB000_IRQ_ERROR +#define DT_UART_MCUX_5_IRQ_ERROR_PRI DT_NXP_KINETIS_UART_400EB000_IRQ_ERROR_PRIORITY +#define DT_UART_MCUX_5_IRQ_STATUS DT_NXP_KINETIS_UART_400EB000_IRQ_STATUS +#define DT_UART_MCUX_5_IRQ_STATUS_PRI DT_NXP_KINETIS_UART_400EB000_IRQ_STATUS_PRIORITY +#define DT_UART_MCUX_5_CLOCK_NAME DT_NXP_KINETIS_UART_400EB000_CLOCK_CONTROLLER +#define DT_UART_MCUX_5_CLOCK_SUBSYS DT_NXP_KINETIS_UART_400EB000_CLOCK_NAME -#define CONFIG_ADC_0_BASE_ADDRESS DT_NXP_KINETIS_ADC16_4003B000_BASE_ADDRESS -#define CONFIG_ADC_0_IRQ DT_NXP_KINETIS_ADC16_4003B000_IRQ_0 +#define DT_ADC_0_BASE_ADDRESS DT_NXP_KINETIS_ADC16_4003B000_BASE_ADDRESS +#define DT_ADC_0_IRQ DT_NXP_KINETIS_ADC16_4003B000_IRQ_0 #define CONFIG_ADC_0_IRQ_PRI DT_NXP_KINETIS_ADC16_4003B000_IRQ_0_PRIORITY #define CONFIG_ADC_0_NAME DT_NXP_KINETIS_ADC16_4003B000_LABEL -#define CONFIG_ADC_1_BASE_ADDRESS DT_NXP_KINETIS_ADC16_400BB000_BASE_ADDRESS -#define CONFIG_ADC_1_IRQ DT_NXP_KINETIS_ADC16_400BB000_IRQ_0 +#define DT_ADC_1_BASE_ADDRESS DT_NXP_KINETIS_ADC16_400BB000_BASE_ADDRESS +#define DT_ADC_1_IRQ DT_NXP_KINETIS_ADC16_400BB000_IRQ_0 #define CONFIG_ADC_1_IRQ_PRI DT_NXP_KINETIS_ADC16_400BB000_IRQ_0_PRIORITY #define CONFIG_ADC_1_NAME DT_NXP_KINETIS_ADC16_400BB000_LABEL -#define CONFIG_FTM_3_BASE_ADDRESS DT_NXP_KINETIS_FTM_400B9000_BASE_ADDRESS -#define CONFIG_FTM_3_IRQ DT_NXP_KINETIS_FTM_400B9000_IRQ_0 -#define CONFIG_FTM_3_IRQ_PRI DT_NXP_KINETIS_FTM_400B9000_IRQ_0_PRIORITY -#define CONFIG_FTM_3_NAME DT_NXP_KINETIS_FTM_400B9000_LABEL +#define DT_FTM_3_BASE_ADDRESS DT_NXP_KINETIS_FTM_400B9000_BASE_ADDRESS +#define DT_FTM_3_IRQ DT_NXP_KINETIS_FTM_400B9000_IRQ_0 +#define DT_FTM_3_IRQ_PRI DT_NXP_KINETIS_FTM_400B9000_IRQ_0_PRIORITY +#define DT_FTM_3_NAME DT_NXP_KINETIS_FTM_400B9000_LABEL -#define CONFIG_SIM_BASE_ADDRESS DT_NXP_KINETIS_SIM_40047000_BASE_ADDRESS -#define CONFIG_SIM_NAME DT_NXP_KINETIS_SIM_40047000_LABEL +#define DT_SIM_BASE_ADDRESS DT_NXP_KINETIS_SIM_40047000_BASE_ADDRESS +#define DT_SIM_NAME DT_NXP_KINETIS_SIM_40047000_LABEL #define CONFIG_I2C_0_NAME DT_NXP_KINETIS_I2C_40066000_LABEL -#define CONFIG_I2C_MCUX_0_BASE_ADDRESS DT_NXP_KINETIS_I2C_40066000_BASE_ADDRESS -#define CONFIG_I2C_MCUX_0_IRQ DT_NXP_KINETIS_I2C_40066000_IRQ_0 -#define CONFIG_I2C_MCUX_0_IRQ_PRI DT_NXP_KINETIS_I2C_40066000_IRQ_0_PRIORITY -#define CONFIG_I2C_MCUX_0_BITRATE DT_NXP_KINETIS_I2C_40066000_CLOCK_FREQUENCY +#define DT_I2C_MCUX_0_BASE_ADDRESS DT_NXP_KINETIS_I2C_40066000_BASE_ADDRESS +#define DT_I2C_MCUX_0_IRQ DT_NXP_KINETIS_I2C_40066000_IRQ_0 +#define DT_I2C_MCUX_0_IRQ_PRI DT_NXP_KINETIS_I2C_40066000_IRQ_0_PRIORITY +#define DT_I2C_MCUX_0_BITRATE DT_NXP_KINETIS_I2C_40066000_CLOCK_FREQUENCY #define CONFIG_I2C_1_NAME DT_NXP_KINETIS_I2C_40067000_LABEL -#define CONFIG_I2C_MCUX_1_BASE_ADDRESS DT_NXP_KINETIS_I2C_40067000_BASE_ADDRESS -#define CONFIG_I2C_MCUX_1_IRQ DT_NXP_KINETIS_I2C_40067000_IRQ_0 -#define CONFIG_I2C_MCUX_1_IRQ_PRI DT_NXP_KINETIS_I2C_40067000_IRQ_0_PRIORITY -#define CONFIG_I2C_MCUX_1_BITRATE DT_NXP_KINETIS_I2C_40067000_CLOCK_FREQUENCY +#define DT_I2C_MCUX_1_BASE_ADDRESS DT_NXP_KINETIS_I2C_40067000_BASE_ADDRESS +#define DT_I2C_MCUX_1_IRQ DT_NXP_KINETIS_I2C_40067000_IRQ_0 +#define DT_I2C_MCUX_1_IRQ_PRI DT_NXP_KINETIS_I2C_40067000_IRQ_0_PRIORITY +#define DT_I2C_MCUX_1_BITRATE DT_NXP_KINETIS_I2C_40067000_CLOCK_FREQUENCY -#define FLASH_DEV_BASE_ADDRESS DT_NXP_KINETIS_FTFE_40020000_BASE_ADDRESS -#define FLASH_DEV_NAME DT_NXP_KINETIS_FTFE_40020000_LABEL +#define DT_FLASH_DEV_BASE_ADDRESS DT_NXP_KINETIS_FTFE_40020000_BASE_ADDRESS +#define DT_FLASH_DEV_NAME DT_NXP_KINETIS_FTFE_40020000_LABEL #define CONFIG_WDT_0_NAME DT_NXP_KINETIS_WDOG_40052000_LABEL -#define CONFIG_WDT_0_BASE_ADDRESS DT_NXP_KINETIS_WDOG_40052000_BASE_ADDRESS -#define CONFIG_WDT_0_IRQ DT_NXP_KINETIS_WDOG_40052000_IRQ_0 -#define CONFIG_WDT_0_IRQ_PRI DT_NXP_KINETIS_WDOG_40052000_IRQ_0_PRIORITY -#define CONFIG_WDT_0_CLOCK_NAME DT_NXP_KINETIS_WDOG_40052000_CLOCK_CONTROLLER -#define CONFIG_WDT_0_CLOCK_SUBSYS DT_NXP_KINETIS_WDOG_40052000_CLOCK_NAME +#define DT_WDT_0_BASE_ADDRESS DT_NXP_KINETIS_WDOG_40052000_BASE_ADDRESS +#define DT_WDT_0_IRQ DT_NXP_KINETIS_WDOG_40052000_IRQ_0 +#define DT_WDT_0_IRQ_PRI DT_NXP_KINETIS_WDOG_40052000_IRQ_0_PRIORITY +#define DT_WDT_0_CLOCK_NAME DT_NXP_KINETIS_WDOG_40052000_CLOCK_CONTROLLER +#define DT_WDT_0_CLOCK_SUBSYS DT_NXP_KINETIS_WDOG_40052000_CLOCK_NAME #define CONFIG_SPI_0_NAME DT_NXP_KINETIS_DSPI_4002C000_LABEL -#define CONFIG_SPI_0_BASE_ADDRESS DT_NXP_KINETIS_DSPI_4002C000_BASE_ADDRESS -#define CONFIG_SPI_0_IRQ DT_NXP_KINETIS_DSPI_4002C000_IRQ_0 +#define DT_SPI_0_BASE_ADDRESS DT_NXP_KINETIS_DSPI_4002C000_BASE_ADDRESS +#define DT_SPI_0_IRQ DT_NXP_KINETIS_DSPI_4002C000_IRQ_0 #define CONFIG_SPI_0_IRQ_PRI DT_NXP_KINETIS_DSPI_4002C000_IRQ_0_PRIORITY -#define CONFIG_SPI_0_CLOCK_NAME DT_NXP_KINETIS_DSPI_4002C000_CLOCK_CONTROLLER -#define CONFIG_SPI_0_CLOCK_SUBSYS DT_NXP_KINETIS_DSPI_4002C000_CLOCK_NAME +#define DT_SPI_0_CLOCK_NAME DT_NXP_KINETIS_DSPI_4002C000_CLOCK_CONTROLLER +#define DT_SPI_0_CLOCK_SUBSYS DT_NXP_KINETIS_DSPI_4002C000_CLOCK_NAME #define CONFIG_SPI_1_NAME DT_NXP_KINETIS_DSPI_4002D000_LABEL -#define CONFIG_SPI_1_BASE_ADDRESS DT_NXP_KINETIS_DSPI_4002D000_BASE_ADDRESS -#define CONFIG_SPI_1_IRQ DT_NXP_KINETIS_DSPI_4002D000_IRQ_0 +#define DT_SPI_1_BASE_ADDRESS DT_NXP_KINETIS_DSPI_4002D000_BASE_ADDRESS +#define DT_SPI_1_IRQ DT_NXP_KINETIS_DSPI_4002D000_IRQ_0 #define CONFIG_SPI_1_IRQ_PRI DT_NXP_KINETIS_DSPI_4002D000_IRQ_0_PRIORITY -#define CONFIG_SPI_1_CLOCK_NAME DT_NXP_KINETIS_DSPI_4002D000_CLOCK_CONTROLLER -#define CONFIG_SPI_1_CLOCK_SUBSYS DT_NXP_KINETIS_DSPI_4002D000_CLOCK_NAME +#define DT_SPI_1_CLOCK_NAME DT_NXP_KINETIS_DSPI_4002D000_CLOCK_CONTROLLER +#define DT_SPI_1_CLOCK_SUBSYS DT_NXP_KINETIS_DSPI_4002D000_CLOCK_NAME #define CONFIG_SPI_2_NAME DT_NXP_KINETIS_DSPI_400AC000_LABEL -#define CONFIG_SPI_2_BASE_ADDRESS DT_NXP_KINETIS_DSPI_400AC000_BASE_ADDRESS -#define CONFIG_SPI_2_IRQ DT_NXP_KINETIS_DSPI_400AC000_IRQ_0 +#define DT_SPI_2_BASE_ADDRESS DT_NXP_KINETIS_DSPI_400AC000_BASE_ADDRESS +#define DT_SPI_2_IRQ DT_NXP_KINETIS_DSPI_400AC000_IRQ_0 #define CONFIG_SPI_2_IRQ_PRI DT_NXP_KINETIS_DSPI_400AC000_IRQ_0_PRIORITY -#define CONFIG_SPI_2_CLOCK_NAME DT_NXP_KINETIS_DSPI_400AC000_CLOCK_CONTROLLER -#define CONFIG_SPI_2_CLOCK_SUBSYS DT_NXP_KINETIS_DSPI_400AC000_CLOCK_NAME +#define DT_SPI_2_CLOCK_NAME DT_NXP_KINETIS_DSPI_400AC000_CLOCK_CONTROLLER +#define DT_SPI_2_CLOCK_SUBSYS DT_NXP_KINETIS_DSPI_400AC000_CLOCK_NAME -#define CONFIG_USBD_KINETIS_NAME DT_NXP_KINETIS_USBD_40072000_LABEL -#define CONFIG_USBD_KINETIS_IRQ DT_NXP_KINETIS_USBD_40072000_IRQ_USB_OTG -#define CONFIG_USBD_KINETIS_IRQ_PRI DT_NXP_KINETIS_USBD_40072000_IRQ_USB_OTG_PRIORITY -#define CONFIG_USBD_KINETIS_BASE_ADDRESS DT_NXP_KINETIS_USBD_40072000_BASE_ADDRESS -#define CONFIG_USBD_KINETIS_NUM_BIDIR_EP DT_NXP_KINETIS_USBD_40072000_NUM_BIDIR_ENDPOINTS +#define DT_USBD_KINETIS_NAME DT_NXP_KINETIS_USBD_40072000_LABEL +#define DT_USBD_KINETIS_IRQ DT_NXP_KINETIS_USBD_40072000_IRQ_USB_OTG +#define DT_USBD_KINETIS_IRQ_PRI DT_NXP_KINETIS_USBD_40072000_IRQ_USB_OTG_PRIORITY +#define DT_USBD_KINETIS_BASE_ADDRESS DT_NXP_KINETIS_USBD_40072000_BASE_ADDRESS +#define DT_USBD_KINETIS_NUM_BIDIR_EP DT_NXP_KINETIS_USBD_40072000_NUM_BIDIR_ENDPOINTS -#define CONFIG_ETH_MCUX_0_NAME ETH_LABEL +#define DT_ETH_MCUX_0_NAME ETH_LABEL -#define CONFIG_ETH_MCUX_0_MAC3 DT_NXP_KINETIS_ETHERNET_400C0004_LOCAL_MAC_ADDRESS_3 -#define CONFIG_ETH_MCUX_0_MAC4 DT_NXP_KINETIS_ETHERNET_400C0004_LOCAL_MAC_ADDRESS_4 -#define CONFIG_ETH_MCUX_0_MAC5 DT_NXP_KINETIS_ETHERNET_400C0004_LOCAL_MAC_ADDRESS_5 +#define DT_ETH_MCUX_0_MAC3 DT_NXP_KINETIS_ETHERNET_400C0004_LOCAL_MAC_ADDRESS_3 +#define DT_ETH_MCUX_0_MAC4 DT_NXP_KINETIS_ETHERNET_400C0004_LOCAL_MAC_ADDRESS_4 +#define DT_ETH_MCUX_0_MAC5 DT_NXP_KINETIS_ETHERNET_400C0004_LOCAL_MAC_ADDRESS_5 /* IRQs */ -#define CONFIG_IRQ_ETH_IEEE1588_TMR DT_NXP_KINETIS_ETHERNET_400C0004_IRQ_ERR_MISC -#define CONFIG_IRQ_ETH_RX DT_NXP_KINETIS_ETHERNET_400C0004_IRQ_RX -#define CONFIG_IRQ_ETH_TX DT_NXP_KINETIS_ETHERNET_400C0004_IRQ_TX -#define CONFIG_IRQ_ETH_ERR_MISC DT_NXP_KINETIS_ETHERNET_400C0004_IRQ_ERR_MISC -#define CONFIG_ETH_MCUX_0_IRQ_PRI DT_NXP_KINETIS_ETHERNET_400C0004_IRQ_RX_PRIORITY +#define DT_IRQ_ETH_IEEE1588_TMR DT_NXP_KINETIS_ETHERNET_400C0004_IRQ_ERR_MISC +#define DT_IRQ_ETH_RX DT_NXP_KINETIS_ETHERNET_400C0004_IRQ_RX +#define DT_IRQ_ETH_TX DT_NXP_KINETIS_ETHERNET_400C0004_IRQ_TX +#define DT_IRQ_ETH_ERR_MISC DT_NXP_KINETIS_ETHERNET_400C0004_IRQ_ERR_MISC +#define DT_ETH_MCUX_0_IRQ_PRI DT_NXP_KINETIS_ETHERNET_400C0004_IRQ_RX_PRIORITY -#define CONFIG_ENTROPY_MCUX_RNGA_BASE_ADDRESS DT_NXP_KINETIS_RNGA_40029000_BASE_ADDRESS -#define CONFIG_ENTROPY_MCUX_RNGA_IRQ DT_NXP_KINETIS_RNGA_40029000_IRQ_0 -#define CONFIG_ENTROPY_MCUX_RNGA_IRQ_PRI DT_NXP_KINETIS_RNGA_40029000_IRQ_0_PRIORITY -#define CONFIG_ENTROPY_MCUX_RNGA_NAME DT_NXP_KINETIS_RNGA_40029000_LABEL +#define DT_ENTROPY_MCUX_RNGA_BASE_ADDRESS DT_NXP_KINETIS_RNGA_40029000_BASE_ADDRESS +#define DT_ENTROPY_MCUX_RNGA_IRQ DT_NXP_KINETIS_RNGA_40029000_IRQ_0 +#define DT_ENTROPY_MCUX_RNGA_IRQ_PRI DT_NXP_KINETIS_RNGA_40029000_IRQ_0_PRIORITY +#define DT_ENTROPY_MCUX_RNGA_NAME DT_NXP_KINETIS_RNGA_40029000_LABEL #define CONFIG_ENTROPY_NAME DT_NXP_KINETIS_RNGA_40029000_LABEL /* End of SoC Level DTS fixup file */ diff --git a/soc/arm/nxp_kinetis/kl2x/dts_fixup.h b/soc/arm/nxp_kinetis/kl2x/dts_fixup.h index 3da06a9861e..3affdf9b715 100644 --- a/soc/arm/nxp_kinetis/kl2x/dts_fixup.h +++ b/soc/arm/nxp_kinetis/kl2x/dts_fixup.h @@ -1,30 +1,30 @@ /* SoC level DTS fixup file */ -#define CONFIG_NUM_IRQ_PRIO_BITS DT_ARM_V6M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS -#define CONFIG_UART_MCUX_LPSCI_0_NAME DT_NXP_KINETIS_LPSCI_4006A000_LABEL -#define CONFIG_UART_MCUX_LPSCI_0_CLOCK_NAME DT_NXP_KINETIS_LPSCI_4006A000_CLOCK_CONTROLLER -#define CONFIG_UART_MCUX_LPSCI_0_CLOCK_SUBSYS DT_NXP_KINETIS_LPSCI_4006A000_CLOCK_NAME +#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V6M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS +#define DT_UART_MCUX_LPSCI_0_NAME DT_NXP_KINETIS_LPSCI_4006A000_LABEL +#define DT_UART_MCUX_LPSCI_0_CLOCK_NAME DT_NXP_KINETIS_LPSCI_4006A000_CLOCK_CONTROLLER +#define DT_UART_MCUX_LPSCI_0_CLOCK_SUBSYS DT_NXP_KINETIS_LPSCI_4006A000_CLOCK_NAME -#define CONFIG_ADC_0_BASE_ADDRESS DT_NXP_KINETIS_ADC16_4003B000_BASE_ADDRESS -#define CONFIG_ADC_0_IRQ DT_NXP_KINETIS_ADC16_4003B000_IRQ_0 +#define DT_ADC_0_BASE_ADDRESS DT_NXP_KINETIS_ADC16_4003B000_BASE_ADDRESS +#define DT_ADC_0_IRQ DT_NXP_KINETIS_ADC16_4003B000_IRQ_0 #define CONFIG_ADC_0_IRQ_PRI DT_NXP_KINETIS_ADC16_4003B000_IRQ_0_PRIORITY #define CONFIG_ADC_0_NAME DT_NXP_KINETIS_ADC16_4003B000_LABEL -#define CONFIG_SIM_BASE_ADDRESS DT_NXP_KINETIS_SIM_40047000_BASE_ADDRESS -#define CONFIG_SIM_NAME DT_NXP_KINETIS_SIM_40047000_LABEL +#define DT_SIM_BASE_ADDRESS DT_NXP_KINETIS_SIM_40047000_BASE_ADDRESS +#define DT_SIM_NAME DT_NXP_KINETIS_SIM_40047000_LABEL #define CONFIG_I2C_0_NAME DT_NXP_KINETIS_I2C_40066000_LABEL -#define CONFIG_I2C_MCUX_0_BASE_ADDRESS DT_NXP_KINETIS_I2C_40066000_BASE_ADDRESS -#define CONFIG_I2C_MCUX_0_IRQ DT_NXP_KINETIS_I2C_40066000_IRQ_0 -#define CONFIG_I2C_MCUX_0_IRQ_PRI DT_NXP_KINETIS_I2C_40066000_IRQ_0_PRIORITY -#define CONFIG_I2C_MCUX_0_BITRATE DT_NXP_KINETIS_I2C_40066000_CLOCK_FREQUENCY +#define DT_I2C_MCUX_0_BASE_ADDRESS DT_NXP_KINETIS_I2C_40066000_BASE_ADDRESS +#define DT_I2C_MCUX_0_IRQ DT_NXP_KINETIS_I2C_40066000_IRQ_0 +#define DT_I2C_MCUX_0_IRQ_PRI DT_NXP_KINETIS_I2C_40066000_IRQ_0_PRIORITY +#define DT_I2C_MCUX_0_BITRATE DT_NXP_KINETIS_I2C_40066000_CLOCK_FREQUENCY -#define FLASH_DEV_BASE_ADDRESS DT_NXP_KINETIS_FTFA_40020000_BASE_ADDRESS -#define FLASH_DEV_NAME DT_NXP_KINETIS_FTFA_40020000_LABEL +#define DT_FLASH_DEV_BASE_ADDRESS DT_NXP_KINETIS_FTFA_40020000_BASE_ADDRESS +#define DT_FLASH_DEV_NAME DT_NXP_KINETIS_FTFA_40020000_LABEL -#define CONFIG_USBD_KINETIS_NAME DT_NXP_KINETIS_USBD_40072000_LABEL -#define CONFIG_USBD_KINETIS_IRQ DT_NXP_KINETIS_USBD_40072000_IRQ_USB_OTG -#define CONFIG_USBD_KINETIS_IRQ_PRI DT_NXP_KINETIS_USBD_40072000_IRQ_USB_OTG_PRIORITY -#define CONFIG_USBD_KINETIS_BASE_ADDRESS DT_NXP_KINETIS_USBD_40072000_BASE_ADDRESS -#define CONFIG_USBD_KINETIS_NUM_BIDIR_EP DT_NXP_KINETIS_USBD_40072000_NUM_BIDIR_ENDPOINTS +#define DT_USBD_KINETIS_NAME DT_NXP_KINETIS_USBD_40072000_LABEL +#define DT_USBD_KINETIS_IRQ DT_NXP_KINETIS_USBD_40072000_IRQ_USB_OTG +#define DT_USBD_KINETIS_IRQ_PRI DT_NXP_KINETIS_USBD_40072000_IRQ_USB_OTG_PRIORITY +#define DT_USBD_KINETIS_BASE_ADDRESS DT_NXP_KINETIS_USBD_40072000_BASE_ADDRESS +#define DT_USBD_KINETIS_NUM_BIDIR_EP DT_NXP_KINETIS_USBD_40072000_NUM_BIDIR_ENDPOINTS /* End of SoC Level DTS fixup file */ diff --git a/soc/arm/nxp_kinetis/kwx/dts_fixup.h b/soc/arm/nxp_kinetis/kwx/dts_fixup.h index 751962a90e5..d197e2db792 100644 --- a/soc/arm/nxp_kinetis/kwx/dts_fixup.h +++ b/soc/arm/nxp_kinetis/kwx/dts_fixup.h @@ -1,99 +1,99 @@ /* SoC level DTS fixup file */ -#define CONFIG_ADC_0_BASE_ADDRESS DT_NXP_KINETIS_ADC16_4003B000_BASE_ADDRESS -#define CONFIG_ADC_0_IRQ DT_NXP_KINETIS_ADC16_4003B000_IRQ_0 +#define DT_ADC_0_BASE_ADDRESS DT_NXP_KINETIS_ADC16_4003B000_BASE_ADDRESS +#define DT_ADC_0_IRQ DT_NXP_KINETIS_ADC16_4003B000_IRQ_0 #define CONFIG_ADC_0_IRQ_PRI DT_NXP_KINETIS_ADC16_4003B000_IRQ_0_PRIORITY #define CONFIG_ADC_0_NAME DT_NXP_KINETIS_ADC16_4003B000_LABEL #define CONFIG_I2C_0_NAME DT_NXP_KINETIS_I2C_40066000_LABEL -#define CONFIG_I2C_MCUX_0_BASE_ADDRESS DT_NXP_KINETIS_I2C_40066000_BASE_ADDRESS -#define CONFIG_I2C_MCUX_0_IRQ DT_NXP_KINETIS_I2C_40066000_IRQ_0 -#define CONFIG_I2C_MCUX_0_IRQ_PRI DT_NXP_KINETIS_I2C_40066000_IRQ_0_PRIORITY -#define CONFIG_I2C_MCUX_0_BITRATE DT_NXP_KINETIS_I2C_40066000_CLOCK_FREQUENCY +#define DT_I2C_MCUX_0_BASE_ADDRESS DT_NXP_KINETIS_I2C_40066000_BASE_ADDRESS +#define DT_I2C_MCUX_0_IRQ DT_NXP_KINETIS_I2C_40066000_IRQ_0 +#define DT_I2C_MCUX_0_IRQ_PRI DT_NXP_KINETIS_I2C_40066000_IRQ_0_PRIORITY +#define DT_I2C_MCUX_0_BITRATE DT_NXP_KINETIS_I2C_40066000_CLOCK_FREQUENCY #define CONFIG_I2C_1_NAME DT_NXP_KINETIS_I2C_40067000_LABEL -#define CONFIG_I2C_MCUX_1_BASE_ADDRESS DT_NXP_KINETIS_I2C_40067000_BASE_ADDRESS -#define CONFIG_I2C_MCUX_1_IRQ DT_NXP_KINETIS_I2C_40067000_IRQ_0 -#define CONFIG_I2C_MCUX_1_IRQ_PRI DT_NXP_KINETIS_I2C_40067000_IRQ_0_PRIORITY -#define CONFIG_I2C_MCUX_1_BITRATE DT_NXP_KINETIS_I2C_40067000_CLOCK_FREQUENCY +#define DT_I2C_MCUX_1_BASE_ADDRESS DT_NXP_KINETIS_I2C_40067000_BASE_ADDRESS +#define DT_I2C_MCUX_1_IRQ DT_NXP_KINETIS_I2C_40067000_IRQ_0 +#define DT_I2C_MCUX_1_IRQ_PRI DT_NXP_KINETIS_I2C_40067000_IRQ_0_PRIORITY +#define DT_I2C_MCUX_1_BITRATE DT_NXP_KINETIS_I2C_40067000_CLOCK_FREQUENCY -#define CONFIG_FTM_1_BASE_ADDRESS DT_NXP_KINETIS_FTM_40039000_BASE_ADDRESS -#define CONFIG_FTM_1_IRQ DT_NXP_KINETIS_FTM_40039000_IRQ_0 -#define CONFIG_FTM_1_IRQ_PRI DT_NXP_KINETIS_FTM_40039000_IRQ_0_PRIORITY -#define CONFIG_FTM_1_NAME DT_NXP_KINETIS_FTM_40039000_LABEL +#define DT_FTM_1_BASE_ADDRESS DT_NXP_KINETIS_FTM_40039000_BASE_ADDRESS +#define DT_FTM_1_IRQ DT_NXP_KINETIS_FTM_40039000_IRQ_0 +#define DT_FTM_1_IRQ_PRI DT_NXP_KINETIS_FTM_40039000_IRQ_0_PRIORITY +#define DT_FTM_1_NAME DT_NXP_KINETIS_FTM_40039000_LABEL -#define CONFIG_SIM_BASE_ADDRESS DT_NXP_KINETIS_SIM_40047000_BASE_ADDRESS -#define CONFIG_SIM_NAME DT_NXP_KINETIS_SIM_40047000_LABEL +#define DT_SIM_BASE_ADDRESS DT_NXP_KINETIS_SIM_40047000_BASE_ADDRESS +#define DT_SIM_NAME DT_NXP_KINETIS_SIM_40047000_LABEL -#define CONFIG_RTC_MCUX_0_BASE_ADDRESS DT_NXP_KINETIS_RTC_4003D000_BASE_ADDRESS -#define CONFIG_RTC_MCUX_0_IRQ_PRI DT_NXP_KINETIS_RTC_4003D000_IRQ_0_PRIORITY -#define CONFIG_RTC_MCUX_0_IRQ DT_NXP_KINETIS_RTC_4003D000_IRQ_0 -#define CONFIG_RTC_MCUX_0_NAME DT_NXP_KINETIS_RTC_4003D000_LABEL +#define DT_RTC_MCUX_0_BASE_ADDRESS DT_NXP_KINETIS_RTC_4003D000_BASE_ADDRESS +#define DT_RTC_MCUX_0_IRQ_PRI DT_NXP_KINETIS_RTC_4003D000_IRQ_0_PRIORITY +#define DT_RTC_MCUX_0_IRQ DT_NXP_KINETIS_RTC_4003D000_IRQ_0 +#define DT_RTC_MCUX_0_NAME DT_NXP_KINETIS_RTC_4003D000_LABEL #define CONFIG_RTC_PRESCALER DT_NXP_KINETIS_RTC_4003D000_PRESCALER #define CONFIG_RTC_0_NAME DT_NXP_KINETIS_RTC_4003D000_LABEL #if defined(CONFIG_SOC_MKW22D5) || defined(CONFIG_SOC_MKW24D5) -#define CONFIG_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS +#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS -#define CONFIG_UART_MCUX_0_BAUD_RATE DT_NXP_KINETIS_UART_4006A000_CURRENT_SPEED -#define CONFIG_UART_MCUX_0_NAME DT_NXP_KINETIS_UART_4006A000_LABEL -#define CONFIG_UART_MCUX_0_IRQ_ERROR DT_NXP_KINETIS_UART_4006A000_IRQ_ERROR -#define CONFIG_UART_MCUX_0_IRQ_ERROR_PRI DT_NXP_KINETIS_UART_4006A000_IRQ_ERROR_PRIORITY -#define CONFIG_UART_MCUX_0_IRQ_STATUS DT_NXP_KINETIS_UART_4006A000_IRQ_STATUS -#define CONFIG_UART_MCUX_0_IRQ_STATUS_PRI DT_NXP_KINETIS_UART_4006A000_IRQ_STATUS_PRIORITY -#define CONFIG_UART_MCUX_0_CLOCK_NAME DT_NXP_KINETIS_UART_4006A000_CLOCK_CONTROLLER -#define CONFIG_UART_MCUX_0_CLOCK_SUBSYS DT_NXP_KINETIS_UART_4006A000_CLOCK_NAME +#define DT_UART_MCUX_0_BAUD_RATE DT_NXP_KINETIS_UART_4006A000_CURRENT_SPEED +#define DT_UART_MCUX_0_NAME DT_NXP_KINETIS_UART_4006A000_LABEL +#define DT_UART_MCUX_0_IRQ_ERROR DT_NXP_KINETIS_UART_4006A000_IRQ_ERROR +#define DT_UART_MCUX_0_IRQ_ERROR_PRI DT_NXP_KINETIS_UART_4006A000_IRQ_ERROR_PRIORITY +#define DT_UART_MCUX_0_IRQ_STATUS DT_NXP_KINETIS_UART_4006A000_IRQ_STATUS +#define DT_UART_MCUX_0_IRQ_STATUS_PRI DT_NXP_KINETIS_UART_4006A000_IRQ_STATUS_PRIORITY +#define DT_UART_MCUX_0_CLOCK_NAME DT_NXP_KINETIS_UART_4006A000_CLOCK_CONTROLLER +#define DT_UART_MCUX_0_CLOCK_SUBSYS DT_NXP_KINETIS_UART_4006A000_CLOCK_NAME -#define CONFIG_UART_MCUX_1_BAUD_RATE DT_NXP_KINETIS_UART_4006B000_CURRENT_SPEED -#define CONFIG_UART_MCUX_1_NAME DT_NXP_KINETIS_UART_4006B000_LABEL -#define CONFIG_UART_MCUX_1_IRQ_ERROR DT_NXP_KINETIS_UART_4006B000_IRQ_ERROR -#define CONFIG_UART_MCUX_1_IRQ_ERROR_PRI DT_NXP_KINETIS_UART_4006B000_IRQ_ERROR_PRIORITY -#define CONFIG_UART_MCUX_1_IRQ_STATUS DT_NXP_KINETIS_UART_4006B000_IRQ_STATUS -#define CONFIG_UART_MCUX_1_IRQ_STATUS_PRI DT_NXP_KINETIS_UART_4006B000_IRQ_STATUS_PRIORITY -#define CONFIG_UART_MCUX_1_CLOCK_NAME DT_NXP_KINETIS_UART_4006B000_CLOCK_CONTROLLER -#define CONFIG_UART_MCUX_1_CLOCK_SUBSYS DT_NXP_KINETIS_UART_4006B000_CLOCK_NAME +#define DT_UART_MCUX_1_BAUD_RATE DT_NXP_KINETIS_UART_4006B000_CURRENT_SPEED +#define DT_UART_MCUX_1_NAME DT_NXP_KINETIS_UART_4006B000_LABEL +#define DT_UART_MCUX_1_IRQ_ERROR DT_NXP_KINETIS_UART_4006B000_IRQ_ERROR +#define DT_UART_MCUX_1_IRQ_ERROR_PRI DT_NXP_KINETIS_UART_4006B000_IRQ_ERROR_PRIORITY +#define DT_UART_MCUX_1_IRQ_STATUS DT_NXP_KINETIS_UART_4006B000_IRQ_STATUS +#define DT_UART_MCUX_1_IRQ_STATUS_PRI DT_NXP_KINETIS_UART_4006B000_IRQ_STATUS_PRIORITY +#define DT_UART_MCUX_1_CLOCK_NAME DT_NXP_KINETIS_UART_4006B000_CLOCK_CONTROLLER +#define DT_UART_MCUX_1_CLOCK_SUBSYS DT_NXP_KINETIS_UART_4006B000_CLOCK_NAME -#define CONFIG_UART_MCUX_2_BAUD_RATE DT_NXP_KINETIS_UART_4006C000_CURRENT_SPEED -#define CONFIG_UART_MCUX_2_NAME DT_NXP_KINETIS_UART_4006C000_LABEL -#define CONFIG_UART_MCUX_2_IRQ_ERROR DT_NXP_KINETIS_UART_4006C000_IRQ_ERROR -#define CONFIG_UART_MCUX_2_IRQ_ERROR_PRI DT_NXP_KINETIS_UART_4006C000_IRQ_ERROR_PRIORITY -#define CONFIG_UART_MCUX_2_IRQ_STATUS DT_NXP_KINETIS_UART_4006C000_IRQ_STATUS -#define CONFIG_UART_MCUX_2_IRQ_STATUS_PRI DT_NXP_KINETIS_UART_4006C000_IRQ_STATUS_PRIORITY -#define CONFIG_UART_MCUX_2_CLOCK_NAME DT_NXP_KINETIS_UART_4006C000_CLOCK_CONTROLLER -#define CONFIG_UART_MCUX_2_CLOCK_SUBSYS DT_NXP_KINETIS_UART_4006C000_CLOCK_NAME +#define DT_UART_MCUX_2_BAUD_RATE DT_NXP_KINETIS_UART_4006C000_CURRENT_SPEED +#define DT_UART_MCUX_2_NAME DT_NXP_KINETIS_UART_4006C000_LABEL +#define DT_UART_MCUX_2_IRQ_ERROR DT_NXP_KINETIS_UART_4006C000_IRQ_ERROR +#define DT_UART_MCUX_2_IRQ_ERROR_PRI DT_NXP_KINETIS_UART_4006C000_IRQ_ERROR_PRIORITY +#define DT_UART_MCUX_2_IRQ_STATUS DT_NXP_KINETIS_UART_4006C000_IRQ_STATUS +#define DT_UART_MCUX_2_IRQ_STATUS_PRI DT_NXP_KINETIS_UART_4006C000_IRQ_STATUS_PRIORITY +#define DT_UART_MCUX_2_CLOCK_NAME DT_NXP_KINETIS_UART_4006C000_CLOCK_CONTROLLER +#define DT_UART_MCUX_2_CLOCK_SUBSYS DT_NXP_KINETIS_UART_4006C000_CLOCK_NAME -#define CONFIG_UART_MCUX_3_BAUD_RATE DT_NXP_KINETIS_UART_4006D000_CURRENT_SPEED -#define CONFIG_UART_MCUX_3_NAME DT_NXP_KINETIS_UART_4006D000_LABEL -#define CONFIG_UART_MCUX_3_IRQ_ERROR DT_NXP_KINETIS_UART_4006D000_IRQ_ERROR -#define CONFIG_UART_MCUX_3_IRQ_ERROR_PRI DT_NXP_KINETIS_UART_4006D000_IRQ_ERROR_PRIORITY -#define CONFIG_UART_MCUX_3_IRQ_STATUS DT_NXP_KINETIS_UART_4006D000_IRQ_STATUS -#define CONFIG_UART_MCUX_3_IRQ_STATUS_PRI DT_NXP_KINETIS_UART_4006D000_IRQ_STATUS_PRIORITY -#define CONFIG_UART_MCUX_3_CLOCK_NAME DT_NXP_KINETIS_UART_4006D000_CLOCK_CONTROLLER -#define CONFIG_UART_MCUX_3_CLOCK_SUBSYS DT_NXP_KINETIS_UART_4006D000_CLOCK_NAME +#define DT_UART_MCUX_3_BAUD_RATE DT_NXP_KINETIS_UART_4006D000_CURRENT_SPEED +#define DT_UART_MCUX_3_NAME DT_NXP_KINETIS_UART_4006D000_LABEL +#define DT_UART_MCUX_3_IRQ_ERROR DT_NXP_KINETIS_UART_4006D000_IRQ_ERROR +#define DT_UART_MCUX_3_IRQ_ERROR_PRI DT_NXP_KINETIS_UART_4006D000_IRQ_ERROR_PRIORITY +#define DT_UART_MCUX_3_IRQ_STATUS DT_NXP_KINETIS_UART_4006D000_IRQ_STATUS +#define DT_UART_MCUX_3_IRQ_STATUS_PRI DT_NXP_KINETIS_UART_4006D000_IRQ_STATUS_PRIORITY +#define DT_UART_MCUX_3_CLOCK_NAME DT_NXP_KINETIS_UART_4006D000_CLOCK_CONTROLLER +#define DT_UART_MCUX_3_CLOCK_SUBSYS DT_NXP_KINETIS_UART_4006D000_CLOCK_NAME -#define FLASH_DEV_BASE_ADDRESS DT_NXP_KINETIS_FTFL_40020000_BASE_ADDRESS -#define FLASH_DEV_NAME DT_NXP_KINETIS_FTFL_40020000_LABEL +#define DT_FLASH_DEV_BASE_ADDRESS DT_NXP_KINETIS_FTFL_40020000_BASE_ADDRESS +#define DT_FLASH_DEV_NAME DT_NXP_KINETIS_FTFL_40020000_LABEL #define CONFIG_WDT_0_NAME DT_NXP_KINETIS_WDOG_40052000_LABEL -#define CONFIG_WDT_0_BASE_ADDRESS DT_NXP_KINETIS_WDOG_40052000_BASE_ADDRESS -#define CONFIG_WDT_0_IRQ DT_NXP_KINETIS_WDOG_40052000_IRQ_0 -#define CONFIG_WDT_0_IRQ_PRI DT_NXP_KINETIS_WDOG_40052000_IRQ_0_PRIORITY -#define CONFIG_WDT_0_CLOCK_NAME DT_NXP_KINETIS_WDOG_40052000_CLOCK_CONTROLLER -#define CONFIG_WDT_0_CLOCK_SUBSYS DT_NXP_KINETIS_WDOG_40052000_CLOCK_NAME +#define DT_WDT_0_BASE_ADDRESS DT_NXP_KINETIS_WDOG_40052000_BASE_ADDRESS +#define DT_WDT_0_IRQ DT_NXP_KINETIS_WDOG_40052000_IRQ_0 +#define DT_WDT_0_IRQ_PRI DT_NXP_KINETIS_WDOG_40052000_IRQ_0_PRIORITY +#define DT_WDT_0_CLOCK_NAME DT_NXP_KINETIS_WDOG_40052000_CLOCK_CONTROLLER +#define DT_WDT_0_CLOCK_SUBSYS DT_NXP_KINETIS_WDOG_40052000_CLOCK_NAME #define CONFIG_SPI_0_NAME DT_NXP_KINETIS_DSPI_4002C000_LABEL -#define CONFIG_SPI_0_BASE_ADDRESS DT_NXP_KINETIS_DSPI_4002C000_BASE_ADDRESS -#define CONFIG_SPI_0_IRQ DT_NXP_KINETIS_DSPI_4002C000_IRQ_0 +#define DT_SPI_0_BASE_ADDRESS DT_NXP_KINETIS_DSPI_4002C000_BASE_ADDRESS +#define DT_SPI_0_IRQ DT_NXP_KINETIS_DSPI_4002C000_IRQ_0 #define CONFIG_SPI_0_IRQ_PRI DT_NXP_KINETIS_DSPI_4002C000_IRQ_0_PRIORITY -#define CONFIG_SPI_0_CLOCK_NAME DT_NXP_KINETIS_DSPI_4002C000_CLOCK_CONTROLLER -#define CONFIG_SPI_0_CLOCK_SUBSYS DT_NXP_KINETIS_DSPI_4002C000_CLOCK_NAME +#define DT_SPI_0_CLOCK_NAME DT_NXP_KINETIS_DSPI_4002C000_CLOCK_CONTROLLER +#define DT_SPI_0_CLOCK_SUBSYS DT_NXP_KINETIS_DSPI_4002C000_CLOCK_NAME #define CONFIG_SPI_1_NAME DT_NXP_KINETIS_DSPI_4002D000_LABEL -#define CONFIG_SPI_1_BASE_ADDRESS DT_NXP_KINETIS_DSPI_4002D000_BASE_ADDRESS -#define CONFIG_SPI_1_IRQ DT_NXP_KINETIS_DSPI_4002D000_IRQ_0 +#define DT_SPI_1_BASE_ADDRESS DT_NXP_KINETIS_DSPI_4002D000_BASE_ADDRESS +#define DT_SPI_1_IRQ DT_NXP_KINETIS_DSPI_4002D000_IRQ_0 #define CONFIG_SPI_1_IRQ_PRI DT_NXP_KINETIS_DSPI_4002D000_IRQ_0_PRIORITY -#define CONFIG_SPI_1_CLOCK_NAME DT_NXP_KINETIS_DSPI_4002D000_CLOCK_CONTROLLER -#define CONFIG_SPI_1_CLOCK_SUBSYS DT_NXP_KINETIS_DSPI_4002D000_CLOCK_NAME +#define DT_SPI_1_CLOCK_NAME DT_NXP_KINETIS_DSPI_4002D000_CLOCK_CONTROLLER +#define DT_SPI_1_CLOCK_SUBSYS DT_NXP_KINETIS_DSPI_4002D000_CLOCK_NAME #define CONFIG_IEEE802154_MCR20A_SPI_DRV_NAME DT_NXP_KINETIS_DSPI_4002D000_NXP_MCR20A_0_BUS_NAME #define CONFIG_IEEE802154_MCR20A_SPI_SLAVE DT_NXP_KINETIS_DSPI_4002D000_NXP_MCR20A_0_BASE_ADDRESS @@ -105,50 +105,50 @@ #define CONFIG_MCR20A_GPIO_RESET_NAME DT_NXP_KINETIS_DSPI_4002D000_NXP_MCR20A_0_RESET_GPIOS_CONTROLLER #define CONFIG_MCR20A_GPIO_RESET_PIN DT_NXP_KINETIS_DSPI_4002D000_NXP_MCR20A_0_RESET_GPIOS_PIN -#define CONFIG_USBD_KINETIS_NAME DT_NXP_KINETIS_USBD_40072000_LABEL -#define CONFIG_USBD_KINETIS_IRQ DT_NXP_KINETIS_USBD_40072000_IRQ_USB_OTG -#define CONFIG_USBD_KINETIS_IRQ_PRI DT_NXP_KINETIS_USBD_40072000_IRQ_USB_OTG_PRIORITY -#define CONFIG_USBD_KINETIS_BASE_ADDRESS DT_NXP_KINETIS_USBD_40072000_BASE_ADDRESS -#define CONFIG_USBD_KINETIS_NUM_BIDIR_EP DT_NXP_KINETIS_USBD_40072000_NUM_BIDIR_ENDPOINTS +#define DT_USBD_KINETIS_NAME DT_NXP_KINETIS_USBD_40072000_LABEL +#define DT_USBD_KINETIS_IRQ DT_NXP_KINETIS_USBD_40072000_IRQ_USB_OTG +#define DT_USBD_KINETIS_IRQ_PRI DT_NXP_KINETIS_USBD_40072000_IRQ_USB_OTG_PRIORITY +#define DT_USBD_KINETIS_BASE_ADDRESS DT_NXP_KINETIS_USBD_40072000_BASE_ADDRESS +#define DT_USBD_KINETIS_NUM_BIDIR_EP DT_NXP_KINETIS_USBD_40072000_NUM_BIDIR_ENDPOINTS -#define CONFIG_ENTROPY_MCUX_RNGA_BASE_ADDRESS DT_NXP_KINETIS_RNGA_40029000_BASE_ADDRESS -#define CONFIG_ENTROPY_MCUX_RNGA_IRQ DT_NXP_KINETIS_RNGA_40029000_IRQ_0 -#define CONFIG_ENTROPY_MCUX_RNGA_IRQ_PRI DT_NXP_KINETIS_RNGA_40029000_IRQ_0_PRIORITY -#define CONFIG_ENTROPY_MCUX_RNGA_NAME DT_NXP_KINETIS_RNGA_40029000_LABEL +#define DT_ENTROPY_MCUX_RNGA_BASE_ADDRESS DT_NXP_KINETIS_RNGA_40029000_BASE_ADDRESS +#define DT_ENTROPY_MCUX_RNGA_IRQ DT_NXP_KINETIS_RNGA_40029000_IRQ_0 +#define DT_ENTROPY_MCUX_RNGA_IRQ_PRI DT_NXP_KINETIS_RNGA_40029000_IRQ_0_PRIORITY +#define DT_ENTROPY_MCUX_RNGA_NAME DT_NXP_KINETIS_RNGA_40029000_LABEL #define CONFIG_ENTROPY_NAME DT_NXP_KINETIS_RNGA_40029000_LABEL #endif /* CONFIG_SOC_MKW22D5 || CONFIG_SOC_MKW24D5 */ #if defined(CONFIG_SOC_MKW40Z4) || defined(CONFIG_SOC_MKW41Z4) -#define CONFIG_NUM_IRQ_PRIO_BITS DT_ARM_V6M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS +#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V6M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS -#define CONFIG_UART_MCUX_LPUART_0_BAUD_RATE DT_NXP_KINETIS_LPUART_40054000_CURRENT_SPEED -#define CONFIG_UART_MCUX_LPUART_0_IRQ DT_NXP_KINETIS_LPUART_40054000_IRQ_0 -#define CONFIG_UART_MCUX_LPUART_0_IRQ_PRI DT_NXP_KINETIS_LPUART_40054000_IRQ_0_PRIORITY -#define CONFIG_UART_MCUX_LPUART_0_NAME DT_NXP_KINETIS_LPUART_40054000_LABEL -#define CONFIG_UART_MCUX_LPUART_0_CLOCK_NAME DT_NXP_KINETIS_LPUART_40054000_CLOCK_CONTROLLER -#define CONFIG_UART_MCUX_LPUART_0_CLOCK_SUBSYS DT_NXP_KINETIS_LPUART_40054000_CLOCK_NAME +#define DT_UART_MCUX_LPUART_0_BAUD_RATE DT_NXP_KINETIS_LPUART_40054000_CURRENT_SPEED +#define DT_UART_MCUX_LPUART_0_IRQ DT_NXP_KINETIS_LPUART_40054000_IRQ_0 +#define DT_UART_MCUX_LPUART_0_IRQ_PRI DT_NXP_KINETIS_LPUART_40054000_IRQ_0_PRIORITY +#define DT_UART_MCUX_LPUART_0_NAME DT_NXP_KINETIS_LPUART_40054000_LABEL +#define DT_UART_MCUX_LPUART_0_CLOCK_NAME DT_NXP_KINETIS_LPUART_40054000_CLOCK_CONTROLLER +#define DT_UART_MCUX_LPUART_0_CLOCK_SUBSYS DT_NXP_KINETIS_LPUART_40054000_CLOCK_NAME -#define FLASH_DEV_BASE_ADDRESS DT_NXP_KINETIS_FTFA_40020000_BASE_ADDRESS -#define FLASH_DEV_NAME DT_NXP_KINETIS_FTFA_40020000_LABEL +#define DT_FLASH_DEV_BASE_ADDRESS DT_NXP_KINETIS_FTFA_40020000_BASE_ADDRESS +#define DT_FLASH_DEV_NAME DT_NXP_KINETIS_FTFA_40020000_LABEL #define CONFIG_SPI_0_NAME DT_NXP_KINETIS_DSPI_4002C000_LABEL -#define CONFIG_SPI_0_BASE_ADDRESS DT_NXP_KINETIS_DSPI_4002C000_BASE_ADDRESS -#define CONFIG_SPI_0_IRQ DT_NXP_KINETIS_DSPI_4002C000_IRQ_0 +#define DT_SPI_0_BASE_ADDRESS DT_NXP_KINETIS_DSPI_4002C000_BASE_ADDRESS +#define DT_SPI_0_IRQ DT_NXP_KINETIS_DSPI_4002C000_IRQ_0 #define CONFIG_SPI_0_IRQ_PRI DT_NXP_KINETIS_DSPI_4002C000_IRQ_0_PRIORITY -#define CONFIG_SPI_0_CLOCK_NAME DT_NXP_KINETIS_DSPI_4002C000_CLOCK_CONTROLLER -#define CONFIG_SPI_0_CLOCK_SUBSYS DT_NXP_KINETIS_DSPI_4002C000_CLOCK_NAME +#define DT_SPI_0_CLOCK_NAME DT_NXP_KINETIS_DSPI_4002C000_CLOCK_CONTROLLER +#define DT_SPI_0_CLOCK_SUBSYS DT_NXP_KINETIS_DSPI_4002C000_CLOCK_NAME #define CONFIG_SPI_1_NAME DT_NXP_KINETIS_DSPI_4002D000_LABEL -#define CONFIG_SPI_1_BASE_ADDRESS DT_NXP_KINETIS_DSPI_4002D000_BASE_ADDRESS -#define CONFIG_SPI_1_IRQ DT_NXP_KINETIS_DSPI_4002D000_IRQ_0 +#define DT_SPI_1_BASE_ADDRESS DT_NXP_KINETIS_DSPI_4002D000_BASE_ADDRESS +#define DT_SPI_1_IRQ DT_NXP_KINETIS_DSPI_4002D000_IRQ_0 #define CONFIG_SPI_1_IRQ_PRI DT_NXP_KINETIS_DSPI_4002D000_IRQ_0_PRIORITY -#define CONFIG_SPI_1_CLOCK_NAME DT_NXP_KINETIS_DSPI_4002D000_CLOCK_CONTROLLER -#define CONFIG_SPI_1_CLOCK_SUBSYS DT_NXP_KINETIS_DSPI_4002D000_CLOCK_NAME +#define DT_SPI_1_CLOCK_NAME DT_NXP_KINETIS_DSPI_4002D000_CLOCK_CONTROLLER +#define DT_SPI_1_CLOCK_SUBSYS DT_NXP_KINETIS_DSPI_4002D000_CLOCK_NAME -#define CONFIG_ENTROPY_MCUX_TRNG_BASE_ADDRESS DT_NXP_KINETIS_TRNG_40029000_BASE_ADDRESS -#define CONFIG_ENTROPY_MCUX_TRNG_IRQ DT_NXP_KINETIS_TRNG_40029000_IRQ_0 -#define CONFIG_ENTROPY_MCUX_TRNG_IRQ_PRI DT_NXP_KINETIS_TRNG_40029000_IRQ_0_PRIORITY -#define CONFIG_ENTROPY_MCUX_TRNG_NAME DT_NXP_KINETIS_TRNG_40029000_LABEL +#define DT_ENTROPY_MCUX_TRNG_BASE_ADDRESS DT_NXP_KINETIS_TRNG_40029000_BASE_ADDRESS +#define DT_ENTROPY_MCUX_TRNG_IRQ DT_NXP_KINETIS_TRNG_40029000_IRQ_0 +#define DT_ENTROPY_MCUX_TRNG_IRQ_PRI DT_NXP_KINETIS_TRNG_40029000_IRQ_0_PRIORITY +#define DT_ENTROPY_MCUX_TRNG_NAME DT_NXP_KINETIS_TRNG_40029000_LABEL #define CONFIG_ENTROPY_NAME DT_NXP_KINETIS_TRNG_40029000_LABEL #endif /* CONFIG_SOC_MKW40Z4 || CONFIG_SOC_MKW41Z4 */ diff --git a/soc/arm/nxp_lpc/lpc54xxx/dts_fixup.h b/soc/arm/nxp_lpc/lpc54xxx/dts_fixup.h index 0d8b6bff510..c966f078d51 100644 --- a/soc/arm/nxp_lpc/lpc54xxx/dts_fixup.h +++ b/soc/arm/nxp_lpc/lpc54xxx/dts_fixup.h @@ -7,19 +7,19 @@ /* SoC level DTS fixup file */ #if defined(CONFIG_SOC_LPC54114_M0) -#define CONFIG_NUM_IRQ_PRIO_BITS DT_ARM_V6M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS +#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V6M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS #else -#define CONFIG_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS +#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS #endif -#define CONFIG_USART_MCUX_LPC_0_BASE_ADDRESS DT_NXP_LPC_USART_40086000_BASE_ADDRESS -#define CONFIG_USART_MCUX_LPC_0_BAUD_RATE DT_NXP_LPC_USART_40086000_CURRENT_SPEED -#define CONFIG_USART_MCUX_LPC_0_IRQ_PRI DT_NXP_LPC_USART_40086000_IRQ_0_PRIORITY -#define CONFIG_USART_MCUX_LPC_0_NAME DT_NXP_LPC_USART_40086000_LABEL +#define DT_USART_MCUX_LPC_0_BASE_ADDRESS DT_NXP_LPC_USART_40086000_BASE_ADDRESS +#define DT_USART_MCUX_LPC_0_BAUD_RATE DT_NXP_LPC_USART_40086000_CURRENT_SPEED +#define DT_USART_MCUX_LPC_0_IRQ_PRI DT_NXP_LPC_USART_40086000_IRQ_0_PRIORITY +#define DT_USART_MCUX_LPC_0_NAME DT_NXP_LPC_USART_40086000_LABEL -#define CONFIG_MAILBOX_MCUX_MAILBOX_0_IRQ DT_NXP_LPC_MAILBOX_4008B000_IRQ_0 -#define CONFIG_MAILBOX_MCUX_MAILBOX_0_IRQ_PRI DT_NXP_LPC_MAILBOX_4008B000_IRQ_0_PRIORITY -#define CONFIG_MAILBOX_MCUX_MAILBOX_0_NAME DT_NXP_LPC_MAILBOX_4008B000_LABEL -#define CONFIG_MAILBOX_MCUX_MAILBOX_0_BASE_ADDRESS DT_NXP_LPC_MAILBOX_4008B000_BASE_ADDRESS +#define DT_MAILBOX_MCUX_MAILBOX_0_IRQ DT_NXP_LPC_MAILBOX_4008B000_IRQ_0 +#define DT_MAILBOX_MCUX_MAILBOX_0_IRQ_PRI DT_NXP_LPC_MAILBOX_4008B000_IRQ_0_PRIORITY +#define DT_MAILBOX_MCUX_MAILBOX_0_NAME DT_NXP_LPC_MAILBOX_4008B000_LABEL +#define DT_MAILBOX_MCUX_MAILBOX_0_BASE_ADDRESS DT_NXP_LPC_MAILBOX_4008B000_BASE_ADDRESS /* End of SoC Level DTS fixup file */ diff --git a/soc/arm/silabs_exx32/efm32hg/dts_fixup.h b/soc/arm/silabs_exx32/efm32hg/dts_fixup.h index edc704f1a4c..b75e4934a38 100644 --- a/soc/arm/silabs_exx32/efm32hg/dts_fixup.h +++ b/soc/arm/silabs_exx32/efm32hg/dts_fixup.h @@ -6,42 +6,42 @@ /* SoC level DTS fixup file */ -#define CONFIG_NUM_IRQ_PRIO_BITS DT_ARM_V6M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS +#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V6M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS -#define FLASH_DEV_BASE_ADDRESS DT_SILABS_GECKO_FLASH_CONTROLLER_400C0000_BASE_ADDRESS -#define FLASH_DEV_NAME DT_SILABS_GECKO_FLASH_CONTROLLER_400C0000_LABEL +#define DT_FLASH_DEV_BASE_ADDRESS DT_SILABS_GECKO_FLASH_CONTROLLER_400C0000_BASE_ADDRESS +#define DT_FLASH_DEV_NAME DT_SILABS_GECKO_FLASH_CONTROLLER_400C0000_LABEL -#define CONFIG_USART_GECKO_0_BASE_ADDRESS DT_SILABS_GECKO_USART_4000C000_BASE_ADDRESS -#define CONFIG_USART_GECKO_0_CURRENT_SPEED DT_SILABS_GECKO_USART_4000C000_CURRENT_SPEED -#define CONFIG_USART_GECKO_0_IRQ_RX DT_SILABS_GECKO_USART_4000C000_IRQ_0 -#define CONFIG_USART_GECKO_0_IRQ_RX_PRIORITY DT_SILABS_GECKO_USART_4000C000_IRQ_0_PRIORITY -#define CONFIG_USART_GECKO_0_IRQ_TX DT_SILABS_GECKO_USART_4000C000_IRQ_1 -#define CONFIG_USART_GECKO_0_IRQ_TX_PRIORITY DT_SILABS_GECKO_USART_4000C000_IRQ_1_PRIORITY -#define CONFIG_USART_GECKO_0_LABEL DT_SILABS_GECKO_USART_4000C000_LABEL -#define CONFIG_USART_GECKO_0_LOCATION DT_SILABS_GECKO_USART_4000C000_LOCATION -#define CONFIG_USART_GECKO_0_SIZE DT_SILABS_GECKO_USART_4000C000_SIZE +#define DT_USART_GECKO_0_BASE_ADDRESS DT_SILABS_GECKO_USART_4000C000_BASE_ADDRESS +#define DT_USART_GECKO_0_CURRENT_SPEED DT_SILABS_GECKO_USART_4000C000_CURRENT_SPEED +#define DT_USART_GECKO_0_IRQ_RX DT_SILABS_GECKO_USART_4000C000_IRQ_0 +#define DT_USART_GECKO_0_IRQ_RX_PRIORITY DT_SILABS_GECKO_USART_4000C000_IRQ_0_PRIORITY +#define DT_USART_GECKO_0_IRQ_TX DT_SILABS_GECKO_USART_4000C000_IRQ_1 +#define DT_USART_GECKO_0_IRQ_TX_PRIORITY DT_SILABS_GECKO_USART_4000C000_IRQ_1_PRIORITY +#define DT_USART_GECKO_0_LABEL DT_SILABS_GECKO_USART_4000C000_LABEL +#define DT_USART_GECKO_0_LOCATION DT_SILABS_GECKO_USART_4000C000_LOCATION +#define DT_USART_GECKO_0_SIZE DT_SILABS_GECKO_USART_4000C000_SIZE -#define CONFIG_USART_GECKO_1_BASE_ADDRESS DT_SILABS_GECKO_USART_4000C400_BASE_ADDRESS -#define CONFIG_USART_GECKO_1_CURRENT_SPEED DT_SILABS_GECKO_USART_4000C400_CURRENT_SPEED -#define CONFIG_USART_GECKO_1_IRQ_RX DT_SILABS_GECKO_USART_4000C400_IRQ_0 -#define CONFIG_USART_GECKO_1_IRQ_RX_PRIORITY DT_SILABS_GECKO_USART_4000C400_IRQ_0_PRIORITY -#define CONFIG_USART_GECKO_1_IRQ_TX DT_SILABS_GECKO_USART_4000C400_IRQ_1 -#define CONFIG_USART_GECKO_1_IRQ_TX_PRIORITY DT_SILABS_GECKO_USART_4000C400_IRQ_1_PRIORITY -#define CONFIG_USART_GECKO_1_LABEL DT_SILABS_GECKO_USART_4000C400_LABEL -#define CONFIG_USART_GECKO_1_LOCATION DT_SILABS_GECKO_USART_4000C400_LOCATION -#define CONFIG_USART_GECKO_1_SIZE DT_SILABS_GECKO_USART_4000C400_SIZE +#define DT_USART_GECKO_1_BASE_ADDRESS DT_SILABS_GECKO_USART_4000C400_BASE_ADDRESS +#define DT_USART_GECKO_1_CURRENT_SPEED DT_SILABS_GECKO_USART_4000C400_CURRENT_SPEED +#define DT_USART_GECKO_1_IRQ_RX DT_SILABS_GECKO_USART_4000C400_IRQ_0 +#define DT_USART_GECKO_1_IRQ_RX_PRIORITY DT_SILABS_GECKO_USART_4000C400_IRQ_0_PRIORITY +#define DT_USART_GECKO_1_IRQ_TX DT_SILABS_GECKO_USART_4000C400_IRQ_1 +#define DT_USART_GECKO_1_IRQ_TX_PRIORITY DT_SILABS_GECKO_USART_4000C400_IRQ_1_PRIORITY +#define DT_USART_GECKO_1_LABEL DT_SILABS_GECKO_USART_4000C400_LABEL +#define DT_USART_GECKO_1_LOCATION DT_SILABS_GECKO_USART_4000C400_LOCATION +#define DT_USART_GECKO_1_SIZE DT_SILABS_GECKO_USART_4000C400_SIZE -#define CONFIG_GPIO_GECKO_COMMON_NAME DT_SILABS_EFM32_GPIO_40006100_LABEL -#define CONFIG_GPIO_GECKO_COMMON_EVEN_IRQ DT_SILABS_EFM32_GPIO_40006100_IRQ_GPIO_EVEN -#define CONFIG_GPIO_GECKO_COMMON_EVEN_PRI DT_SILABS_EFM32_GPIO_40006100_IRQ_GPIO_EVEN_PRIORITY -#define CONFIG_GPIO_GECKO_COMMON_ODD_IRQ DT_SILABS_EFM32_GPIO_40006100_IRQ_GPIO_ODD -#define CONFIG_GPIO_GECKO_COMMON_ODD_PRI DT_SILABS_EFM32_GPIO_40006100_IRQ_GPIO_ODD_PRIORITY +#define DT_GPIO_GECKO_COMMON_NAME DT_SILABS_EFM32_GPIO_40006100_LABEL +#define DT_GPIO_GECKO_COMMON_EVEN_IRQ DT_SILABS_EFM32_GPIO_40006100_IRQ_GPIO_EVEN +#define DT_GPIO_GECKO_COMMON_EVEN_PRI DT_SILABS_EFM32_GPIO_40006100_IRQ_GPIO_EVEN_PRIORITY +#define DT_GPIO_GECKO_COMMON_ODD_IRQ DT_SILABS_EFM32_GPIO_40006100_IRQ_GPIO_ODD +#define DT_GPIO_GECKO_COMMON_ODD_PRI DT_SILABS_EFM32_GPIO_40006100_IRQ_GPIO_ODD_PRIORITY -#define CONFIG_GPIO_GECKO_PORTA_NAME DT_SILABS_EFM32_GPIO_PORT_40006000_LABEL -#define CONFIG_GPIO_GECKO_PORTB_NAME DT_SILABS_EFM32_GPIO_PORT_40006024_LABEL -#define CONFIG_GPIO_GECKO_PORTC_NAME DT_SILABS_EFM32_GPIO_PORT_40006048_LABEL -#define CONFIG_GPIO_GECKO_PORTD_NAME DT_SILABS_EFM32_GPIO_PORT_4000606C_LABEL -#define CONFIG_GPIO_GECKO_PORTE_NAME DT_SILABS_EFM32_GPIO_PORT_40006090_LABEL -#define CONFIG_GPIO_GECKO_PORTF_NAME DT_SILABS_EFM32_GPIO_PORT_400060B4_LABEL +#define DT_GPIO_GECKO_PORTA_NAME DT_SILABS_EFM32_GPIO_PORT_40006000_LABEL +#define DT_GPIO_GECKO_PORTB_NAME DT_SILABS_EFM32_GPIO_PORT_40006024_LABEL +#define DT_GPIO_GECKO_PORTC_NAME DT_SILABS_EFM32_GPIO_PORT_40006048_LABEL +#define DT_GPIO_GECKO_PORTD_NAME DT_SILABS_EFM32_GPIO_PORT_4000606C_LABEL +#define DT_GPIO_GECKO_PORTE_NAME DT_SILABS_EFM32_GPIO_PORT_40006090_LABEL +#define DT_GPIO_GECKO_PORTF_NAME DT_SILABS_EFM32_GPIO_PORT_400060B4_LABEL /* End of SoC Level DTS fixup file */ diff --git a/soc/arm/silabs_exx32/efm32hg/soc_pinmap.h b/soc/arm/silabs_exx32/efm32hg/soc_pinmap.h index 5e72b51446b..060c70153fa 100644 --- a/soc/arm/silabs_exx32/efm32hg/soc_pinmap.h +++ b/soc/arm/silabs_exx32/efm32hg/soc_pinmap.h @@ -18,17 +18,17 @@ #ifdef CONFIG_SOC_PART_NUMBER_EFM32HG322F64 #ifdef CONFIG_USART_GECKO_0 -#if (CONFIG_USART_GECKO_0_LOCATION == 0) +#if (DT_USART_GECKO_0_LOCATION == 0) #define PIN_USART0_TXD {gpioPortE, 10, gpioModePushPull, 1} #define PIN_USART0_RXD {gpioPortE, 11, gpioModeInput, 1} -#elif (CONFIG_USART_GECKO_0_LOCATION == 3) +#elif (DT_USART_GECKO_0_LOCATION == 3) #define PIN_USART0_TXD {gpioPortE, 13, gpioModePushPull, 1} #define PIN_USART0_RXD {gpioPortE, 12, gpioModeInput, 1} -#elif (CONFIG_USART_GECKO_0_LOCATION == 4) +#elif (DT_USART_GECKO_0_LOCATION == 4) #define PIN_USART0_TXD {gpioPortB, 7, gpioModePushPull, 1} #define PIN_USART0_RXD {gpioPortB, 8, gpioModeInput, 1} -#elif (CONFIG_USART_GECKO_0_LOCATION == 5) || \ - (CONFIG_USART_GECKO_0_LOCATION == 6) +#elif (DT_USART_GECKO_0_LOCATION == 5) || \ + (DT_USART_GECKO_0_LOCATION == 6) #define PIN_USART0_TXD {gpioPortC, 0, gpioModePushPull, 1} #define PIN_USART0_RXD {gpioPortC, 1, gpioModeInput, 1} #else @@ -37,17 +37,17 @@ #endif /* CONFIG_USART_GECKO_0 */ #ifdef CONFIG_USART_GECKO_1 -#if (CONFIG_USART_GECKO_1_LOCATION == 0) +#if (DT_USART_GECKO_1_LOCATION == 0) #define PIN_USART1_TXD {gpioPortC, 0, gpioModePushPull, 1} #define PIN_USART1_RXD {gpioPortC, 1, gpioModeInput, 1} -#elif (CONFIG_USART_GECKO_1_LOCATION == 2) || \ - (CONFIG_USART_GECKO_1_LOCATION == 3) +#elif (DT_USART_GECKO_1_LOCATION == 2) || \ + (DT_USART_GECKO_1_LOCATION == 3) #define PIN_USART1_TXD {gpioPortD, 7, gpioModePushPull, 1} #define PIN_USART1_RXD {gpioPortD, 6, gpioModeInput, 1} -#elif (CONFIG_USART_GECKO_1_LOCATION == 4) +#elif (DT_USART_GECKO_1_LOCATION == 4) #define PIN_USART1_TXD {gpioPortF, 2, gpioModePushPull, 1} #define PIN_USART1_RXD {gpioPortA, 0, gpioModeInput, 1} -#elif (CONFIG_USART_GECKO_1_LOCATION == 5) +#elif (DT_USART_GECKO_1_LOCATION == 5) #define PIN_USART1_TXD {gpioPortC, 1, gpioModePushPull, 1} #define PIN_USART1_RXD {gpioPortC, 2, gpioModeInput, 1} #else diff --git a/soc/arm/silabs_exx32/efm32wg/dts_fixup.h b/soc/arm/silabs_exx32/efm32wg/dts_fixup.h index 94dea703801..a2287615ada 100644 --- a/soc/arm/silabs_exx32/efm32wg/dts_fixup.h +++ b/soc/arm/silabs_exx32/efm32wg/dts_fixup.h @@ -6,73 +6,73 @@ /* SoC level DTS fixup file */ -#define CONFIG_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS +#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS -#define FLASH_DEV_BASE_ADDRESS DT_SILABS_GECKO_FLASH_CONTROLLER_400C0000_BASE_ADDRESS -#define FLASH_DEV_NAME DT_SILABS_GECKO_FLASH_CONTROLLER_400C0000_LABEL +#define DT_FLASH_DEV_BASE_ADDRESS DT_SILABS_GECKO_FLASH_CONTROLLER_400C0000_BASE_ADDRESS +#define DT_FLASH_DEV_NAME DT_SILABS_GECKO_FLASH_CONTROLLER_400C0000_LABEL -#define CONFIG_USART_GECKO_0_BASE_ADDRESS DT_SILABS_GECKO_USART_4000C000_BASE_ADDRESS -#define CONFIG_USART_GECKO_0_CURRENT_SPEED DT_SILABS_GECKO_USART_4000C000_CURRENT_SPEED -#define CONFIG_USART_GECKO_0_IRQ_RX DT_SILABS_GECKO_USART_4000C000_IRQ_0 -#define CONFIG_USART_GECKO_0_IRQ_RX_PRIORITY DT_SILABS_GECKO_USART_4000C000_IRQ_0_PRIORITY -#define CONFIG_USART_GECKO_0_IRQ_TX DT_SILABS_GECKO_USART_4000C000_IRQ_1 -#define CONFIG_USART_GECKO_0_IRQ_TX_PRIORITY DT_SILABS_GECKO_USART_4000C000_IRQ_1_PRIORITY -#define CONFIG_USART_GECKO_0_LABEL DT_SILABS_GECKO_USART_4000C000_LABEL -#define CONFIG_USART_GECKO_0_LOCATION DT_SILABS_GECKO_USART_4000C000_LOCATION -#define CONFIG_USART_GECKO_0_SIZE DT_SILABS_GECKO_USART_4000C000_SIZE +#define DT_USART_GECKO_0_BASE_ADDRESS DT_SILABS_GECKO_USART_4000C000_BASE_ADDRESS +#define DT_USART_GECKO_0_CURRENT_SPEED DT_SILABS_GECKO_USART_4000C000_CURRENT_SPEED +#define DT_USART_GECKO_0_IRQ_RX DT_SILABS_GECKO_USART_4000C000_IRQ_0 +#define DT_USART_GECKO_0_IRQ_RX_PRIORITY DT_SILABS_GECKO_USART_4000C000_IRQ_0_PRIORITY +#define DT_USART_GECKO_0_IRQ_TX DT_SILABS_GECKO_USART_4000C000_IRQ_1 +#define DT_USART_GECKO_0_IRQ_TX_PRIORITY DT_SILABS_GECKO_USART_4000C000_IRQ_1_PRIORITY +#define DT_USART_GECKO_0_LABEL DT_SILABS_GECKO_USART_4000C000_LABEL +#define DT_USART_GECKO_0_LOCATION DT_SILABS_GECKO_USART_4000C000_LOCATION +#define DT_USART_GECKO_0_SIZE DT_SILABS_GECKO_USART_4000C000_SIZE -#define CONFIG_USART_GECKO_1_BASE_ADDRESS DT_SILABS_GECKO_USART_4000C400_BASE_ADDRESS -#define CONFIG_USART_GECKO_1_CURRENT_SPEED DT_SILABS_GECKO_USART_4000C400_CURRENT_SPEED -#define CONFIG_USART_GECKO_1_IRQ_RX DT_SILABS_GECKO_USART_4000C400_IRQ_0 -#define CONFIG_USART_GECKO_1_IRQ_RX_PRIORITY DT_SILABS_GECKO_USART_4000C400_IRQ_0_PRIORITY -#define CONFIG_USART_GECKO_1_IRQ_TX DT_SILABS_GECKO_USART_4000C400_IRQ_1 -#define CONFIG_USART_GECKO_1_IRQ_TX_PRIORITY DT_SILABS_GECKO_USART_4000C400_IRQ_1_PRIORITY -#define CONFIG_USART_GECKO_1_LABEL DT_SILABS_GECKO_USART_4000C400_LABEL -#define CONFIG_USART_GECKO_1_LOCATION DT_SILABS_GECKO_USART_4000C400_LOCATION -#define CONFIG_USART_GECKO_1_SIZE DT_SILABS_GECKO_USART_4000C400_SIZE +#define DT_USART_GECKO_1_BASE_ADDRESS DT_SILABS_GECKO_USART_4000C400_BASE_ADDRESS +#define DT_USART_GECKO_1_CURRENT_SPEED DT_SILABS_GECKO_USART_4000C400_CURRENT_SPEED +#define DT_USART_GECKO_1_IRQ_RX DT_SILABS_GECKO_USART_4000C400_IRQ_0 +#define DT_USART_GECKO_1_IRQ_RX_PRIORITY DT_SILABS_GECKO_USART_4000C400_IRQ_0_PRIORITY +#define DT_USART_GECKO_1_IRQ_TX DT_SILABS_GECKO_USART_4000C400_IRQ_1 +#define DT_USART_GECKO_1_IRQ_TX_PRIORITY DT_SILABS_GECKO_USART_4000C400_IRQ_1_PRIORITY +#define DT_USART_GECKO_1_LABEL DT_SILABS_GECKO_USART_4000C400_LABEL +#define DT_USART_GECKO_1_LOCATION DT_SILABS_GECKO_USART_4000C400_LOCATION +#define DT_USART_GECKO_1_SIZE DT_SILABS_GECKO_USART_4000C400_SIZE -#define CONFIG_USART_GECKO_2_BASE_ADDRESS DT_SILABS_GECKO_USART_4000C800_BASE_ADDRESS -#define CONFIG_USART_GECKO_2_CURRENT_SPEED DT_SILABS_GECKO_USART_4000C800_CURRENT_SPEED -#define CONFIG_USART_GECKO_2_IRQ_RX DT_SILABS_GECKO_USART_4000C800_IRQ_0 -#define CONFIG_USART_GECKO_2_IRQ_RX_PRIORITY DT_SILABS_GECKO_USART_4000C800_IRQ_0_PRIORITY -#define CONFIG_USART_GECKO_2_IRQ_TX DT_SILABS_GECKO_USART_4000C800_IRQ_1 -#define CONFIG_USART_GECKO_2_IRQ_TX_PRIORITY DT_SILABS_GECKO_USART_4000C800_IRQ_1_PRIORITY -#define CONFIG_USART_GECKO_2_LABEL DT_SILABS_GECKO_USART_4000C800_LABEL -#define CONFIG_USART_GECKO_2_LOCATION DT_SILABS_GECKO_USART_4000C800_LOCATION -#define CONFIG_USART_GECKO_2_SIZE DT_SILABS_GECKO_USART_4000C800_SIZE +#define DT_USART_GECKO_2_BASE_ADDRESS DT_SILABS_GECKO_USART_4000C800_BASE_ADDRESS +#define DT_USART_GECKO_2_CURRENT_SPEED DT_SILABS_GECKO_USART_4000C800_CURRENT_SPEED +#define DT_USART_GECKO_2_IRQ_RX DT_SILABS_GECKO_USART_4000C800_IRQ_0 +#define DT_USART_GECKO_2_IRQ_RX_PRIORITY DT_SILABS_GECKO_USART_4000C800_IRQ_0_PRIORITY +#define DT_USART_GECKO_2_IRQ_TX DT_SILABS_GECKO_USART_4000C800_IRQ_1 +#define DT_USART_GECKO_2_IRQ_TX_PRIORITY DT_SILABS_GECKO_USART_4000C800_IRQ_1_PRIORITY +#define DT_USART_GECKO_2_LABEL DT_SILABS_GECKO_USART_4000C800_LABEL +#define DT_USART_GECKO_2_LOCATION DT_SILABS_GECKO_USART_4000C800_LOCATION +#define DT_USART_GECKO_2_SIZE DT_SILABS_GECKO_USART_4000C800_SIZE -#define CONFIG_UART_GECKO_0_BASE_ADDRESS DT_SILABS_GECKO_UART_4000E000_BASE_ADDRESS -#define CONFIG_UART_GECKO_0_CURRENT_SPEED DT_SILABS_GECKO_UART_4000E000_CURRENT_SPEED -#define CONFIG_UART_GECKO_0_IRQ_RX DT_SILABS_GECKO_UART_4000E000_IRQ_0 -#define CONFIG_UART_GECKO_0_IRQ_RX_PRIORITY DT_SILABS_GECKO_UART_4000E000_IRQ_0_PRIORITY -#define CONFIG_UART_GECKO_0_IRQ_TX DT_SILABS_GECKO_UART_4000E000_IRQ_1 -#define CONFIG_UART_GECKO_0_IRQ_TX_PRIORITY DT_SILABS_GECKO_UART_4000E000_IRQ_1_PRIORITY -#define CONFIG_UART_GECKO_0_LABEL DT_SILABS_GECKO_UART_4000E000_LABEL -#define CONFIG_UART_GECKO_0_LOCATION DT_SILABS_GECKO_UART_4000E000_LOCATION -#define CONFIG_UART_GECKO_0_SIZE DT_SILABS_GECKO_UART_4000E000_SIZE +#define DT_UART_GECKO_0_BASE_ADDRESS DT_SILABS_GECKO_UART_4000E000_BASE_ADDRESS +#define DT_UART_GECKO_0_CURRENT_SPEED DT_SILABS_GECKO_UART_4000E000_CURRENT_SPEED +#define DT_UART_GECKO_0_IRQ_RX DT_SILABS_GECKO_UART_4000E000_IRQ_0 +#define DT_UART_GECKO_0_IRQ_RX_PRIORITY DT_SILABS_GECKO_UART_4000E000_IRQ_0_PRIORITY +#define DT_UART_GECKO_0_IRQ_TX DT_SILABS_GECKO_UART_4000E000_IRQ_1 +#define DT_UART_GECKO_0_IRQ_TX_PRIORITY DT_SILABS_GECKO_UART_4000E000_IRQ_1_PRIORITY +#define DT_UART_GECKO_0_LABEL DT_SILABS_GECKO_UART_4000E000_LABEL +#define DT_UART_GECKO_0_LOCATION DT_SILABS_GECKO_UART_4000E000_LOCATION +#define DT_UART_GECKO_0_SIZE DT_SILABS_GECKO_UART_4000E000_SIZE -#define CONFIG_UART_GECKO_1_BASE_ADDRESS DT_SILABS_GECKO_UART_4000E400_BASE_ADDRESS -#define CONFIG_UART_GECKO_1_CURRENT_SPEED DT_SILABS_GECKO_UART_4000E400_CURRENT_SPEED -#define CONFIG_UART_GECKO_1_IRQ_RX DT_SILABS_GECKO_UART_4000E400_IRQ_0 -#define CONFIG_UART_GECKO_1_IRQ_RX_PRIORITY DT_SILABS_GECKO_UART_4000E400_IRQ_0_PRIORITY -#define CONFIG_UART_GECKO_1_IRQ_TX DT_SILABS_GECKO_UART_4000E400_IRQ_1 -#define CONFIG_UART_GECKO_1_IRQ_TX_PRIORITY DT_SILABS_GECKO_UART_4000E400_IRQ_1_PRIORITY -#define CONFIG_UART_GECKO_1_LABEL DT_SILABS_GECKO_UART_4000E400_LABEL -#define CONFIG_UART_GECKO_1_LOCATION DT_SILABS_GECKO_UART_4000E400_LOCATION -#define CONFIG_UART_GECKO_1_SIZE DT_SILABS_GECKO_UART_4000E400_SIZE +#define DT_UART_GECKO_1_BASE_ADDRESS DT_SILABS_GECKO_UART_4000E400_BASE_ADDRESS +#define DT_UART_GECKO_1_CURRENT_SPEED DT_SILABS_GECKO_UART_4000E400_CURRENT_SPEED +#define DT_UART_GECKO_1_IRQ_RX DT_SILABS_GECKO_UART_4000E400_IRQ_0 +#define DT_UART_GECKO_1_IRQ_RX_PRIORITY DT_SILABS_GECKO_UART_4000E400_IRQ_0_PRIORITY +#define DT_UART_GECKO_1_IRQ_TX DT_SILABS_GECKO_UART_4000E400_IRQ_1 +#define DT_UART_GECKO_1_IRQ_TX_PRIORITY DT_SILABS_GECKO_UART_4000E400_IRQ_1_PRIORITY +#define DT_UART_GECKO_1_LABEL DT_SILABS_GECKO_UART_4000E400_LABEL +#define DT_UART_GECKO_1_LOCATION DT_SILABS_GECKO_UART_4000E400_LOCATION +#define DT_UART_GECKO_1_SIZE DT_SILABS_GECKO_UART_4000E400_SIZE -#define CONFIG_GPIO_GECKO_COMMON_NAME DT_SILABS_EFM32_GPIO_40006100_LABEL -#define CONFIG_GPIO_GECKO_COMMON_EVEN_IRQ DT_SILABS_EFM32_GPIO_40006100_IRQ_GPIO_EVEN -#define CONFIG_GPIO_GECKO_COMMON_EVEN_PRI DT_SILABS_EFM32_GPIO_40006100_IRQ_GPIO_EVEN_PRIORITY -#define CONFIG_GPIO_GECKO_COMMON_ODD_IRQ DT_SILABS_EFM32_GPIO_40006100_IRQ_GPIO_ODD -#define CONFIG_GPIO_GECKO_COMMON_ODD_PRI DT_SILABS_EFM32_GPIO_40006100_IRQ_GPIO_ODD_PRIORITY +#define DT_GPIO_GECKO_COMMON_NAME DT_SILABS_EFM32_GPIO_40006100_LABEL +#define DT_GPIO_GECKO_COMMON_EVEN_IRQ DT_SILABS_EFM32_GPIO_40006100_IRQ_GPIO_EVEN +#define DT_GPIO_GECKO_COMMON_EVEN_PRI DT_SILABS_EFM32_GPIO_40006100_IRQ_GPIO_EVEN_PRIORITY +#define DT_GPIO_GECKO_COMMON_ODD_IRQ DT_SILABS_EFM32_GPIO_40006100_IRQ_GPIO_ODD +#define DT_GPIO_GECKO_COMMON_ODD_PRI DT_SILABS_EFM32_GPIO_40006100_IRQ_GPIO_ODD_PRIORITY -#define CONFIG_GPIO_GECKO_PORTA_NAME DT_SILABS_EFM32_GPIO_PORT_40006000_LABEL -#define CONFIG_GPIO_GECKO_PORTB_NAME DT_SILABS_EFM32_GPIO_PORT_40006024_LABEL -#define CONFIG_GPIO_GECKO_PORTC_NAME DT_SILABS_EFM32_GPIO_PORT_40006048_LABEL -#define CONFIG_GPIO_GECKO_PORTD_NAME DT_SILABS_EFM32_GPIO_PORT_4000606C_LABEL -#define CONFIG_GPIO_GECKO_PORTE_NAME DT_SILABS_EFM32_GPIO_PORT_40006090_LABEL -#define CONFIG_GPIO_GECKO_PORTF_NAME DT_SILABS_EFM32_GPIO_PORT_400060B4_LABEL +#define DT_GPIO_GECKO_PORTA_NAME DT_SILABS_EFM32_GPIO_PORT_40006000_LABEL +#define DT_GPIO_GECKO_PORTB_NAME DT_SILABS_EFM32_GPIO_PORT_40006024_LABEL +#define DT_GPIO_GECKO_PORTC_NAME DT_SILABS_EFM32_GPIO_PORT_40006048_LABEL +#define DT_GPIO_GECKO_PORTD_NAME DT_SILABS_EFM32_GPIO_PORT_4000606C_LABEL +#define DT_GPIO_GECKO_PORTE_NAME DT_SILABS_EFM32_GPIO_PORT_40006090_LABEL +#define DT_GPIO_GECKO_PORTF_NAME DT_SILABS_EFM32_GPIO_PORT_400060B4_LABEL /* End of SoC Level DTS fixup file */ diff --git a/soc/arm/silabs_exx32/efm32wg/soc_pinmap.h b/soc/arm/silabs_exx32/efm32wg/soc_pinmap.h index 94e60dcdf62..d7a78b623d7 100644 --- a/soc/arm/silabs_exx32/efm32wg/soc_pinmap.h +++ b/soc/arm/silabs_exx32/efm32wg/soc_pinmap.h @@ -18,13 +18,13 @@ #ifdef CONFIG_SOC_PART_NUMBER_EFM32WG990F256 #ifdef CONFIG_UART_GECKO_0 -#if (CONFIG_UART_GECKO_0_LOCATION == 0) +#if (DT_UART_GECKO_0_LOCATION == 0) #define PIN_UART0_TXD {gpioPortF, 6, gpioModePushPull, 1} #define PIN_UART0_RXD {gpioPortF, 7, gpioModeInput, 1} -#elif (CONFIG_UART_GECKO_0_LOCATION == 1) +#elif (DT_UART_GECKO_0_LOCATION == 1) #define PIN_UART0_TXD {gpioPortE, 0, gpioModePushPull, 1} #define PIN_UART0_RXD {gpioPortE, 1, gpioModeInput, 1} -#elif (CONFIG_UART_GECKO_0_LOCATION == 2) +#elif (DT_UART_GECKO_0_LOCATION == 2) #define PIN_UART0_TXD {gpioPortA, 3, gpioModePushPull, 1} #define PIN_UART0_RXD {gpioPortA, 4, gpioModeInput, 1} #else @@ -33,15 +33,15 @@ #endif /* CONFIG_UART_GECKO_0 */ #ifdef CONFIG_UART_GECKO_1 -#if (CONFIG_UART_GECKO_1_LOCATION == 0) +#if (DT_UART_GECKO_1_LOCATION == 0) #error ("Serial Driver for Gecko MCUs not implemented for this location index") -#elif (CONFIG_UART_GECKO_1_LOCATION == 1) +#elif (DT_UART_GECKO_1_LOCATION == 1) #define PIN_UART1_TXD {gpioPortF, 10, gpioModePushPull, 1} #define PIN_UART1_RXD {gpioPortF, 11, gpioModeInput, 1} -#elif (CONFIG_UART_GECKO_1_LOCATION == 2) +#elif (DT_UART_GECKO_1_LOCATION == 2) #define PIN_UART1_TXD {gpioPortB, 9, gpioModePushPull, 1} #define PIN_UART1_RXD {gpioPortB, 10, gpioModeInput, 1} -#elif (CONFIG_UART_GECKO_1_LOCATION == 3) +#elif (DT_UART_GECKO_1_LOCATION == 3) #define PIN_UART1_TXD {gpioPortE, 2, gpioModePushPull, 1} #define PIN_UART1_RXD {gpioPortE, 3, gpioModeInput, 1} #else diff --git a/soc/arm/silabs_exx32/efr32fg1p/dts_fixup.h b/soc/arm/silabs_exx32/efr32fg1p/dts_fixup.h index d90090cd74d..98f19851def 100644 --- a/soc/arm/silabs_exx32/efr32fg1p/dts_fixup.h +++ b/soc/arm/silabs_exx32/efr32fg1p/dts_fixup.h @@ -6,42 +6,42 @@ /* SoC level DTS fixup file */ -#define CONFIG_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS +#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS -#define FLASH_DEV_BASE_ADDRESS DT_SILABS_GECKO_FLASH_CONTROLLER_400E0000_BASE_ADDRESS -#define FLASH_DEV_NAME DT_SILABS_GECKO_FLASH_CONTROLLER_400E0000_LABEL +#define DT_FLASH_DEV_BASE_ADDRESS DT_SILABS_GECKO_FLASH_CONTROLLER_400E0000_BASE_ADDRESS +#define DT_FLASH_DEV_NAME DT_SILABS_GECKO_FLASH_CONTROLLER_400E0000_LABEL -#define CONFIG_USART_GECKO_0_BASE_ADDRESS DT_SILABS_GECKO_USART_40010000_BASE_ADDRESS -#define CONFIG_USART_GECKO_0_CURRENT_SPEED DT_SILABS_GECKO_USART_40010000_CURRENT_SPEED -#define CONFIG_USART_GECKO_0_IRQ_RX DT_SILABS_GECKO_USART_40010000_IRQ_0 -#define CONFIG_USART_GECKO_0_IRQ_RX_PRIORITY DT_SILABS_GECKO_USART_40010000_IRQ_0_PRIORITY -#define CONFIG_USART_GECKO_0_IRQ_TX DT_SILABS_GECKO_USART_40010000_IRQ_1 -#define CONFIG_USART_GECKO_0_IRQ_TX_PRIORITY DT_SILABS_GECKO_USART_40010000_IRQ_1_PRIORITY -#define CONFIG_USART_GECKO_0_LABEL DT_SILABS_GECKO_USART_40010000_LABEL -#define CONFIG_USART_GECKO_0_LOCATION DT_SILABS_GECKO_USART_40010000_LOCATION -#define CONFIG_USART_GECKO_0_SIZE DT_SILABS_GECKO_USART_40010000_SIZE +#define DT_USART_GECKO_0_BASE_ADDRESS DT_SILABS_GECKO_USART_40010000_BASE_ADDRESS +#define DT_USART_GECKO_0_CURRENT_SPEED DT_SILABS_GECKO_USART_40010000_CURRENT_SPEED +#define DT_USART_GECKO_0_IRQ_RX DT_SILABS_GECKO_USART_40010000_IRQ_0 +#define DT_USART_GECKO_0_IRQ_RX_PRIORITY DT_SILABS_GECKO_USART_40010000_IRQ_0_PRIORITY +#define DT_USART_GECKO_0_IRQ_TX DT_SILABS_GECKO_USART_40010000_IRQ_1 +#define DT_USART_GECKO_0_IRQ_TX_PRIORITY DT_SILABS_GECKO_USART_40010000_IRQ_1_PRIORITY +#define DT_USART_GECKO_0_LABEL DT_SILABS_GECKO_USART_40010000_LABEL +#define DT_USART_GECKO_0_LOCATION DT_SILABS_GECKO_USART_40010000_LOCATION +#define DT_USART_GECKO_0_SIZE DT_SILABS_GECKO_USART_40010000_SIZE -#define CONFIG_USART_GECKO_1_BASE_ADDRESS DT_SILABS_GECKO_USART_40010400_BASE_ADDRESS -#define CONFIG_USART_GECKO_1_CURRENT_SPEED DT_SILABS_GECKO_USART_40010400_CURRENT_SPEED -#define CONFIG_USART_GECKO_1_IRQ_RX DT_SILABS_GECKO_USART_40010400_IRQ_0 -#define CONFIG_USART_GECKO_1_IRQ_RX_PRIORITY DT_SILABS_GECKO_USART_40010400_IRQ_0_PRIORITY -#define CONFIG_USART_GECKO_1_IRQ_TX DT_SILABS_GECKO_USART_40010400_IRQ_1 -#define CONFIG_USART_GECKO_1_IRQ_TX_PRIORITY DT_SILABS_GECKO_USART_40010400_IRQ_1_PRIORITY -#define CONFIG_USART_GECKO_1_LABEL DT_SILABS_GECKO_USART_40010400_LABEL -#define CONFIG_USART_GECKO_1_LOCATION DT_SILABS_GECKO_USART_40010400_LOCATION -#define CONFIG_USART_GECKO_1_SIZE DT_SILABS_GECKO_USART_40010400_SIZE +#define DT_USART_GECKO_1_BASE_ADDRESS DT_SILABS_GECKO_USART_40010400_BASE_ADDRESS +#define DT_USART_GECKO_1_CURRENT_SPEED DT_SILABS_GECKO_USART_40010400_CURRENT_SPEED +#define DT_USART_GECKO_1_IRQ_RX DT_SILABS_GECKO_USART_40010400_IRQ_0 +#define DT_USART_GECKO_1_IRQ_RX_PRIORITY DT_SILABS_GECKO_USART_40010400_IRQ_0_PRIORITY +#define DT_USART_GECKO_1_IRQ_TX DT_SILABS_GECKO_USART_40010400_IRQ_1 +#define DT_USART_GECKO_1_IRQ_TX_PRIORITY DT_SILABS_GECKO_USART_40010400_IRQ_1_PRIORITY +#define DT_USART_GECKO_1_LABEL DT_SILABS_GECKO_USART_40010400_LABEL +#define DT_USART_GECKO_1_LOCATION DT_SILABS_GECKO_USART_40010400_LOCATION +#define DT_USART_GECKO_1_SIZE DT_SILABS_GECKO_USART_40010400_SIZE -#define CONFIG_GPIO_GECKO_COMMON_NAME DT_SILABS_EFR32XG1_GPIO_4000A400_LABEL -#define CONFIG_GPIO_GECKO_COMMON_EVEN_IRQ DT_SILABS_EFR32XG1_GPIO_4000A400_IRQ_GPIO_EVEN -#define CONFIG_GPIO_GECKO_COMMON_EVEN_PRI DT_SILABS_EFR32XG1_GPIO_4000A400_IRQ_GPIO_EVEN_PRIORITY -#define CONFIG_GPIO_GECKO_COMMON_ODD_IRQ DT_SILABS_EFR32XG1_GPIO_4000A400_IRQ_GPIO_ODD -#define CONFIG_GPIO_GECKO_COMMON_ODD_PRI DT_SILABS_EFR32XG1_GPIO_4000A400_IRQ_GPIO_ODD_PRIORITY +#define DT_GPIO_GECKO_COMMON_NAME DT_SILABS_EFR32XG1_GPIO_4000A400_LABEL +#define DT_GPIO_GECKO_COMMON_EVEN_IRQ DT_SILABS_EFR32XG1_GPIO_4000A400_IRQ_GPIO_EVEN +#define DT_GPIO_GECKO_COMMON_EVEN_PRI DT_SILABS_EFR32XG1_GPIO_4000A400_IRQ_GPIO_EVEN_PRIORITY +#define DT_GPIO_GECKO_COMMON_ODD_IRQ DT_SILABS_EFR32XG1_GPIO_4000A400_IRQ_GPIO_ODD +#define DT_GPIO_GECKO_COMMON_ODD_PRI DT_SILABS_EFR32XG1_GPIO_4000A400_IRQ_GPIO_ODD_PRIORITY -#define CONFIG_GPIO_GECKO_PORTA_NAME DT_SILABS_EFR32XG1_GPIO_PORT_4000A000_LABEL -#define CONFIG_GPIO_GECKO_PORTB_NAME DT_SILABS_EFR32XG1_GPIO_PORT_4000A030_LABEL -#define CONFIG_GPIO_GECKO_PORTC_NAME DT_SILABS_EFR32XG1_GPIO_PORT_4000A060_LABEL -#define CONFIG_GPIO_GECKO_PORTD_NAME DT_SILABS_EFR32XG1_GPIO_PORT_4000A090_LABEL -#define CONFIG_GPIO_GECKO_PORTE_NAME DT_SILABS_EFR32XG1_GPIO_PORT_4000A0C0_LABEL -#define CONFIG_GPIO_GECKO_PORTF_NAME DT_SILABS_EFR32XG1_GPIO_PORT_4000A0F0_LABEL +#define DT_GPIO_GECKO_PORTA_NAME DT_SILABS_EFR32XG1_GPIO_PORT_4000A000_LABEL +#define DT_GPIO_GECKO_PORTB_NAME DT_SILABS_EFR32XG1_GPIO_PORT_4000A030_LABEL +#define DT_GPIO_GECKO_PORTC_NAME DT_SILABS_EFR32XG1_GPIO_PORT_4000A060_LABEL +#define DT_GPIO_GECKO_PORTD_NAME DT_SILABS_EFR32XG1_GPIO_PORT_4000A090_LABEL +#define DT_GPIO_GECKO_PORTE_NAME DT_SILABS_EFR32XG1_GPIO_PORT_4000A0C0_LABEL +#define DT_GPIO_GECKO_PORTF_NAME DT_SILABS_EFR32XG1_GPIO_PORT_4000A0F0_LABEL /* End of SoC Level DTS fixup file */ diff --git a/soc/arm/silabs_exx32/efr32fg1p/soc_pinmap.h b/soc/arm/silabs_exx32/efr32fg1p/soc_pinmap.h index de58343c977..0659d12359b 100644 --- a/soc/arm/silabs_exx32/efr32fg1p/soc_pinmap.h +++ b/soc/arm/silabs_exx32/efr32fg1p/soc_pinmap.h @@ -18,13 +18,13 @@ #ifdef CONFIG_SOC_PART_NUMBER_EFR32FG1P133F256GM48 #ifdef CONFIG_USART_GECKO_0 -#if (CONFIG_USART_GECKO_0_LOCATION == 0) +#if (DT_USART_GECKO_0_LOCATION == 0) #define PIN_USART0_TXD {gpioPortA, 0, gpioModePushPull, 1} #define PIN_USART0_RXD {gpioPortA, 1, gpioModeInput, 1} -#elif (CONFIG_USART_GECKO_0_LOCATION == 1) +#elif (DT_USART_GECKO_0_LOCATION == 1) #define PIN_USART0_TXD {gpioPortA, 1, gpioModePushPull, 1} #define PIN_USART0_RXD {gpioPortA, 2, gpioModeInput, 1} -#elif (CONFIG_USART_GECKO_0_LOCATION == 2) +#elif (DT_USART_GECKO_0_LOCATION == 2) #define PIN_USART0_TXD {gpioPortA, 2, gpioModePushPull, 1} #define PIN_USART0_RXD {gpioPortA, 3, gpioModeInput, 1} #else @@ -33,15 +33,15 @@ #endif /* CONFIG_USART_GECKO_0 */ #ifdef CONFIG_USART_GECKO_1 -#if (CONFIG_USART_GECKO_1_LOCATION == 0) +#if (DT_USART_GECKO_1_LOCATION == 0) #error ("Serial Driver for Gecko MCUs not implemented for this location index") -#elif (CONFIG_USART_GECKO_1_LOCATION == 1) +#elif (DT_USART_GECKO_1_LOCATION == 1) #define PIN_USART1_TXD {gpioPortF, 10, gpioModePushPull, 1} #define PIN_USART1_RXD {gpioPortF, 11, gpioModeInput, 1} -#elif (CONFIG_USART_GECKO_1_LOCATION == 2) +#elif (DT_USART_GECKO_1_LOCATION == 2) #define PIN_USART1_TXD {gpioPortB, 9, gpioModePushPull, 1} #define PIN_USART1_RXD {gpioPortB, 10, gpioModeInput, 1} -#elif (CONFIG_USART_GECKO_1_LOCATION == 3) +#elif (DT_USART_GECKO_1_LOCATION == 3) #define PIN_USART1_TXD {gpioPortE, 2, gpioModePushPull, 1} #define PIN_USART1_RXD {gpioPortE, 3, gpioModeInput, 1} #else diff --git a/soc/arm/silabs_exx32/efr32mg12p/dts_fixup.h b/soc/arm/silabs_exx32/efr32mg12p/dts_fixup.h index 7f71dbb2a39..add39ff77db 100644 --- a/soc/arm/silabs_exx32/efr32mg12p/dts_fixup.h +++ b/soc/arm/silabs_exx32/efr32mg12p/dts_fixup.h @@ -6,86 +6,86 @@ /* SoC level DTS fixup file */ -#define CONFIG_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS +#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS -#define FLASH_DEV_BASE_ADDRESS DT_SILABS_GECKO_FLASH_CONTROLLER_400E0000_BASE_ADDRESS -#define FLASH_DEV_NAME DT_SILABS_GECKO_FLASH_CONTROLLER_400E0000_LABEL +#define DT_FLASH_DEV_BASE_ADDRESS DT_SILABS_GECKO_FLASH_CONTROLLER_400E0000_BASE_ADDRESS +#define DT_FLASH_DEV_NAME DT_SILABS_GECKO_FLASH_CONTROLLER_400E0000_LABEL -#define CONFIG_USART_GECKO_0_BASE_ADDRESS DT_SILABS_GECKO_USART_40010000_BASE_ADDRESS -#define CONFIG_USART_GECKO_0_CURRENT_SPEED DT_SILABS_GECKO_USART_40010000_CURRENT_SPEED -#define CONFIG_USART_GECKO_0_IRQ_RX DT_SILABS_GECKO_USART_40010000_IRQ_0 -#define CONFIG_USART_GECKO_0_IRQ_RX_PRIORITY DT_SILABS_GECKO_USART_40010000_IRQ_0_PRIORITY -#define CONFIG_USART_GECKO_0_IRQ_TX DT_SILABS_GECKO_USART_40010000_IRQ_1 -#define CONFIG_USART_GECKO_0_IRQ_TX_PRIORITY DT_SILABS_GECKO_USART_40010000_IRQ_1_PRIORITY -#define CONFIG_USART_GECKO_0_LABEL DT_SILABS_GECKO_USART_40010000_LABEL -#define CONFIG_USART_GECKO_0_LOCATION DT_SILABS_GECKO_USART_40010000_LOCATION -#define CONFIG_USART_GECKO_0_SIZE DT_SILABS_GECKO_USART_40010000_SIZE +#define DT_USART_GECKO_0_BASE_ADDRESS DT_SILABS_GECKO_USART_40010000_BASE_ADDRESS +#define DT_USART_GECKO_0_CURRENT_SPEED DT_SILABS_GECKO_USART_40010000_CURRENT_SPEED +#define DT_USART_GECKO_0_IRQ_RX DT_SILABS_GECKO_USART_40010000_IRQ_0 +#define DT_USART_GECKO_0_IRQ_RX_PRIORITY DT_SILABS_GECKO_USART_40010000_IRQ_0_PRIORITY +#define DT_USART_GECKO_0_IRQ_TX DT_SILABS_GECKO_USART_40010000_IRQ_1 +#define DT_USART_GECKO_0_IRQ_TX_PRIORITY DT_SILABS_GECKO_USART_40010000_IRQ_1_PRIORITY +#define DT_USART_GECKO_0_LABEL DT_SILABS_GECKO_USART_40010000_LABEL +#define DT_USART_GECKO_0_LOCATION DT_SILABS_GECKO_USART_40010000_LOCATION +#define DT_USART_GECKO_0_SIZE DT_SILABS_GECKO_USART_40010000_SIZE -#define CONFIG_USART_GECKO_1_BASE_ADDRESS DT_SILABS_GECKO_USART_40010400_BASE_ADDRESS -#define CONFIG_USART_GECKO_1_CURRENT_SPEED DT_SILABS_GECKO_USART_40010400_CURRENT_SPEED -#define CONFIG_USART_GECKO_1_IRQ_RX DT_SILABS_GECKO_USART_40010400_IRQ_0 -#define CONFIG_USART_GECKO_1_IRQ_RX_PRIORITY DT_SILABS_GECKO_USART_40010400_IRQ_0_PRIORITY -#define CONFIG_USART_GECKO_1_IRQ_TX DT_SILABS_GECKO_USART_40010400_IRQ_1 -#define CONFIG_USART_GECKO_1_IRQ_TX_PRIORITY DT_SILABS_GECKO_USART_40010400_IRQ_1_PRIORITY -#define CONFIG_USART_GECKO_1_LABEL DT_SILABS_GECKO_USART_40010400_LABEL -#define CONFIG_USART_GECKO_1_LOCATION DT_SILABS_GECKO_USART_40010400_LOCATION -#define CONFIG_USART_GECKO_1_SIZE DT_SILABS_GECKO_USART_40010400_SIZE +#define DT_USART_GECKO_1_BASE_ADDRESS DT_SILABS_GECKO_USART_40010400_BASE_ADDRESS +#define DT_USART_GECKO_1_CURRENT_SPEED DT_SILABS_GECKO_USART_40010400_CURRENT_SPEED +#define DT_USART_GECKO_1_IRQ_RX DT_SILABS_GECKO_USART_40010400_IRQ_0 +#define DT_USART_GECKO_1_IRQ_RX_PRIORITY DT_SILABS_GECKO_USART_40010400_IRQ_0_PRIORITY +#define DT_USART_GECKO_1_IRQ_TX DT_SILABS_GECKO_USART_40010400_IRQ_1 +#define DT_USART_GECKO_1_IRQ_TX_PRIORITY DT_SILABS_GECKO_USART_40010400_IRQ_1_PRIORITY +#define DT_USART_GECKO_1_LABEL DT_SILABS_GECKO_USART_40010400_LABEL +#define DT_USART_GECKO_1_LOCATION DT_SILABS_GECKO_USART_40010400_LOCATION +#define DT_USART_GECKO_1_SIZE DT_SILABS_GECKO_USART_40010400_SIZE -#define CONFIG_USART_GECKO_2_BASE_ADDRESS DT_SILABS_GECKO_USART_40010800_BASE_ADDRESS -#define CONFIG_USART_GECKO_2_CURRENT_SPEED DT_SILABS_GECKO_USART_40010800_CURRENT_SPEED -#define CONFIG_USART_GECKO_2_IRQ_RX DT_SILABS_GECKO_USART_40010800_IRQ_0 -#define CONFIG_USART_GECKO_2_IRQ_RX_PRIORITY DT_SILABS_GECKO_USART_40010800_IRQ_0_PRIORITY -#define CONFIG_USART_GECKO_2_IRQ_TX DT_SILABS_GECKO_USART_40010800_IRQ_1 -#define CONFIG_USART_GECKO_2_IRQ_TX_PRIORITY DT_SILABS_GECKO_USART_40010800_IRQ_1_PRIORITY -#define CONFIG_USART_GECKO_2_LABEL DT_SILABS_GECKO_USART_40010800_LABEL -#define CONFIG_USART_GECKO_2_LOCATION DT_SILABS_GECKO_USART_40010800_LOCATION -#define CONFIG_USART_GECKO_2_SIZE DT_SILABS_GECKO_USART_40010800_SIZE +#define DT_USART_GECKO_2_BASE_ADDRESS DT_SILABS_GECKO_USART_40010800_BASE_ADDRESS +#define DT_USART_GECKO_2_CURRENT_SPEED DT_SILABS_GECKO_USART_40010800_CURRENT_SPEED +#define DT_USART_GECKO_2_IRQ_RX DT_SILABS_GECKO_USART_40010800_IRQ_0 +#define DT_USART_GECKO_2_IRQ_RX_PRIORITY DT_SILABS_GECKO_USART_40010800_IRQ_0_PRIORITY +#define DT_USART_GECKO_2_IRQ_TX DT_SILABS_GECKO_USART_40010800_IRQ_1 +#define DT_USART_GECKO_2_IRQ_TX_PRIORITY DT_SILABS_GECKO_USART_40010800_IRQ_1_PRIORITY +#define DT_USART_GECKO_2_LABEL DT_SILABS_GECKO_USART_40010800_LABEL +#define DT_USART_GECKO_2_LOCATION DT_SILABS_GECKO_USART_40010800_LOCATION +#define DT_USART_GECKO_2_SIZE DT_SILABS_GECKO_USART_40010800_SIZE -#define CONFIG_USART_GECKO_3_BASE_ADDRESS DT_SILABS_GECKO_USART_40010C00_BASE_ADDRESS -#define CONFIG_USART_GECKO_3_CURRENT_SPEED DT_SILABS_GECKO_USART_40010C00_CURRENT_SPEED -#define CONFIG_USART_GECKO_3_IRQ_RX DT_SILABS_GECKO_USART_40010C00_IRQ_0 -#define CONFIG_USART_GECKO_3_IRQ_RX_PRIORITY DT_SILABS_GECKO_USART_40010C00_IRQ_0_PRIORITY -#define CONFIG_USART_GECKO_3_IRQ_TX DT_SILABS_GECKO_USART_40010C00_IRQ_1 -#define CONFIG_USART_GECKO_3_IRQ_TX_PRIORITY DT_SILABS_GECKO_USART_40010C00_IRQ_1_PRIORITY -#define CONFIG_USART_GECKO_3_LABEL DT_SILABS_GECKO_USART_40010C00_LABEL -#define CONFIG_USART_GECKO_3_LOCATION DT_SILABS_GECKO_USART_40010C00_LOCATION -#define CONFIG_USART_GECKO_3_SIZE DT_SILABS_GECKO_USART_40010C00_SIZE +#define DT_USART_GECKO_3_BASE_ADDRESS DT_SILABS_GECKO_USART_40010C00_BASE_ADDRESS +#define DT_USART_GECKO_3_CURRENT_SPEED DT_SILABS_GECKO_USART_40010C00_CURRENT_SPEED +#define DT_USART_GECKO_3_IRQ_RX DT_SILABS_GECKO_USART_40010C00_IRQ_0 +#define DT_USART_GECKO_3_IRQ_RX_PRIORITY DT_SILABS_GECKO_USART_40010C00_IRQ_0_PRIORITY +#define DT_USART_GECKO_3_IRQ_TX DT_SILABS_GECKO_USART_40010C00_IRQ_1 +#define DT_USART_GECKO_3_IRQ_TX_PRIORITY DT_SILABS_GECKO_USART_40010C00_IRQ_1_PRIORITY +#define DT_USART_GECKO_3_LABEL DT_SILABS_GECKO_USART_40010C00_LABEL +#define DT_USART_GECKO_3_LOCATION DT_SILABS_GECKO_USART_40010C00_LOCATION +#define DT_USART_GECKO_3_SIZE DT_SILABS_GECKO_USART_40010C00_SIZE -#define CONFIG_LEUART_GECKO_0_BASE_ADDRESS DT_SILABS_GECKO_LEUART_4004A000_BASE_ADDRESS -#define CONFIG_LEUART_GECKO_0_CURRENT_SPEED DT_SILABS_GECKO_LEUART_4004A000_CURRENT_SPEED -#define CONFIG_LEUART_GECKO_0_IRQ DT_SILABS_GECKO_LEUART_4004A000_IRQ_0 -#define CONFIG_LEUART_GECKO_0_IRQ_PRIORITY DT_SILABS_GECKO_LEUART_4004A000_IRQ_0_PRIORITY -#define CONFIG_LEUART_GECKO_0_LABEL DT_SILABS_GECKO_LEUART_4004A000_LABEL -#define CONFIG_LEUART_GECKO_0_LOCATION DT_SILABS_GECKO_LEUART_4004A000_LOCATION -#define CONFIG_LEUART_GECKO_0_SIZE DT_SILABS_GECKO_LEUART_4004A000_SIZE +#define DT_LEUART_GECKO_0_BASE_ADDRESS DT_SILABS_GECKO_LEUART_4004A000_BASE_ADDRESS +#define DT_LEUART_GECKO_0_CURRENT_SPEED DT_SILABS_GECKO_LEUART_4004A000_CURRENT_SPEED +#define DT_LEUART_GECKO_0_IRQ DT_SILABS_GECKO_LEUART_4004A000_IRQ_0 +#define DT_LEUART_GECKO_0_IRQ_PRIORITY DT_SILABS_GECKO_LEUART_4004A000_IRQ_0_PRIORITY +#define DT_LEUART_GECKO_0_LABEL DT_SILABS_GECKO_LEUART_4004A000_LABEL +#define DT_LEUART_GECKO_0_LOCATION DT_SILABS_GECKO_LEUART_4004A000_LOCATION +#define DT_LEUART_GECKO_0_SIZE DT_SILABS_GECKO_LEUART_4004A000_SIZE -#define CONFIG_GPIO_GECKO_COMMON_NAME DT_SILABS_EFR32MG_GPIO_4000A400_LABEL -#define CONFIG_GPIO_GECKO_COMMON_EVEN_IRQ DT_SILABS_EFR32MG_GPIO_4000A400_IRQ_GPIO_EVEN -#define CONFIG_GPIO_GECKO_COMMON_EVEN_PRI DT_SILABS_EFR32MG_GPIO_4000A400_IRQ_GPIO_EVEN_PRIORITY -#define CONFIG_GPIO_GECKO_COMMON_ODD_IRQ DT_SILABS_EFR32MG_GPIO_4000A400_IRQ_GPIO_ODD -#define CONFIG_GPIO_GECKO_COMMON_ODD_PRI DT_SILABS_EFR32MG_GPIO_4000A400_IRQ_GPIO_ODD_PRIORITY +#define DT_GPIO_GECKO_COMMON_NAME DT_SILABS_EFR32MG_GPIO_4000A400_LABEL +#define DT_GPIO_GECKO_COMMON_EVEN_IRQ DT_SILABS_EFR32MG_GPIO_4000A400_IRQ_GPIO_EVEN +#define DT_GPIO_GECKO_COMMON_EVEN_PRI DT_SILABS_EFR32MG_GPIO_4000A400_IRQ_GPIO_EVEN_PRIORITY +#define DT_GPIO_GECKO_COMMON_ODD_IRQ DT_SILABS_EFR32MG_GPIO_4000A400_IRQ_GPIO_ODD +#define DT_GPIO_GECKO_COMMON_ODD_PRI DT_SILABS_EFR32MG_GPIO_4000A400_IRQ_GPIO_ODD_PRIORITY -#define CONFIG_GPIO_GECKO_PORTA_NAME DT_SILABS_EFR32MG_GPIO_PORT_4000A000_LABEL -#define CONFIG_GPIO_GECKO_PORTB_NAME DT_SILABS_EFR32MG_GPIO_PORT_4000A030_LABEL -#define CONFIG_GPIO_GECKO_PORTC_NAME DT_SILABS_EFR32MG_GPIO_PORT_4000A060_LABEL -#define CONFIG_GPIO_GECKO_PORTD_NAME DT_SILABS_EFR32MG_GPIO_PORT_4000A090_LABEL -#define CONFIG_GPIO_GECKO_PORTE_NAME DT_SILABS_EFR32MG_GPIO_PORT_4000A0C0_LABEL -#define CONFIG_GPIO_GECKO_PORTF_NAME DT_SILABS_EFR32MG_GPIO_PORT_4000A0F0_LABEL +#define DT_GPIO_GECKO_PORTA_NAME DT_SILABS_EFR32MG_GPIO_PORT_4000A000_LABEL +#define DT_GPIO_GECKO_PORTB_NAME DT_SILABS_EFR32MG_GPIO_PORT_4000A030_LABEL +#define DT_GPIO_GECKO_PORTC_NAME DT_SILABS_EFR32MG_GPIO_PORT_4000A060_LABEL +#define DT_GPIO_GECKO_PORTD_NAME DT_SILABS_EFR32MG_GPIO_PORT_4000A090_LABEL +#define DT_GPIO_GECKO_PORTE_NAME DT_SILABS_EFR32MG_GPIO_PORT_4000A0C0_LABEL +#define DT_GPIO_GECKO_PORTF_NAME DT_SILABS_EFR32MG_GPIO_PORT_4000A0F0_LABEL -#define CONFIG_I2C_GECKO_0_BASE_ADDRESS DT_SILABS_GECKO_I2C_4000C000_BASE_ADDRESS -#define CONFIG_I2C_GECKO_0_CLOCK_FREQUENCY DT_SILABS_GECKO_I2C_4000C000_CLOCK_FREQUENCY -#define CONFIG_I2C_GECKO_0_IRQ DT_SILABS_GECKO_I2C_4000C000_IRQ_0 -#define CONFIG_I2C_GECKO_0_IRQ_PRIORITY DT_SILABS_GECKO_I2C_4000C000_IRQ_0_PRIORITY -#define CONFIG_I2C_GECKO_0_LABEL DT_SILABS_GECKO_I2C_4000C000_LABEL -#define CONFIG_I2C_GECKO_0_LOCATION DT_SILABS_GECKO_I2C_4000C000_LOCATION -#define CONFIG_I2C_GECKO_0_SIZE DT_SILABS_GECKO_I2C_4000C000_SIZE +#define DT_I2C_GECKO_0_BASE_ADDRESS DT_SILABS_GECKO_I2C_4000C000_BASE_ADDRESS +#define DT_I2C_GECKO_0_CLOCK_FREQUENCY DT_SILABS_GECKO_I2C_4000C000_CLOCK_FREQUENCY +#define DT_I2C_GECKO_0_IRQ DT_SILABS_GECKO_I2C_4000C000_IRQ_0 +#define DT_I2C_GECKO_0_IRQ_PRIORITY DT_SILABS_GECKO_I2C_4000C000_IRQ_0_PRIORITY +#define DT_I2C_GECKO_0_LABEL DT_SILABS_GECKO_I2C_4000C000_LABEL +#define DT_I2C_GECKO_0_LOCATION DT_SILABS_GECKO_I2C_4000C000_LOCATION +#define DT_I2C_GECKO_0_SIZE DT_SILABS_GECKO_I2C_4000C000_SIZE -#define CONFIG_I2C_GECKO_1_BASE_ADDRESS DT_SILABS_GECKO_I2C_4000C400_BASE_ADDRESS -#define CONFIG_I2C_GECKO_1_CLOCK_FREQUENCY DT_SILABS_GECKO_I2C_4000C400_CLOCK_FREQUENCY -#define CONFIG_I2C_GECKO_1_IRQ DT_SILABS_GECKO_I2C_4000C400_IRQ_0 -#define CONFIG_I2C_GECKO_1_IRQ_PRIORITY DT_SILABS_GECKO_I2C_4000C400_IRQ_0_PRIORITY -#define CONFIG_I2C_GECKO_1_LABEL DT_SILABS_GECKO_I2C_4000C400_LABEL -#define CONFIG_I2C_GECKO_1_LOCATION DT_SILABS_GECKO_I2C_4000C400_LOCATION -#define CONFIG_I2C_GECKO_1_SIZE DT_SILABS_GECKO_I2C_4000C400_SIZE +#define DT_I2C_GECKO_1_BASE_ADDRESS DT_SILABS_GECKO_I2C_4000C400_BASE_ADDRESS +#define DT_I2C_GECKO_1_CLOCK_FREQUENCY DT_SILABS_GECKO_I2C_4000C400_CLOCK_FREQUENCY +#define DT_I2C_GECKO_1_IRQ DT_SILABS_GECKO_I2C_4000C400_IRQ_0 +#define DT_I2C_GECKO_1_IRQ_PRIORITY DT_SILABS_GECKO_I2C_4000C400_IRQ_0_PRIORITY +#define DT_I2C_GECKO_1_LABEL DT_SILABS_GECKO_I2C_4000C400_LABEL +#define DT_I2C_GECKO_1_LOCATION DT_SILABS_GECKO_I2C_4000C400_LOCATION +#define DT_I2C_GECKO_1_SIZE DT_SILABS_GECKO_I2C_4000C400_SIZE /* End of SoC Level DTS fixup file */ diff --git a/soc/arm/silabs_exx32/efr32mg12p/soc_pinmap.h b/soc/arm/silabs_exx32/efr32mg12p/soc_pinmap.h index 255f12dbace..0fdc12712c3 100644 --- a/soc/arm/silabs_exx32/efr32mg12p/soc_pinmap.h +++ b/soc/arm/silabs_exx32/efr32mg12p/soc_pinmap.h @@ -17,7 +17,7 @@ #ifdef CONFIG_UART_GECKO #ifdef CONFIG_USART_GECKO_0 -#if (CONFIG_USART_GECKO_0_LOCATION == 0) +#if (DT_USART_GECKO_0_LOCATION == 0) #define PIN_USART0_TXD {gpioPortA, 0, gpioModePushPull, 1} #define PIN_USART0_RXD {gpioPortA, 1, gpioModeInput, 0} #else @@ -28,7 +28,7 @@ #ifdef CONFIG_LEUART_GECKO #ifdef CONFIG_LEUART_GECKO_0 -#if (CONFIG_LEUART_GECKO_0_LOCATION == 27) +#if (DT_LEUART_GECKO_0_LOCATION == 27) #define PIN_LEUART0_TXD {gpioPortF, 3, gpioModePushPull, 1} #define PIN_LEUART0_RXD {gpioPortF, 4, gpioModeInput, 1} #else @@ -39,7 +39,7 @@ #ifdef CONFIG_I2C_GECKO #ifdef CONFIG_I2C_0 -#if (CONFIG_I2C_GECKO_0_LOCATION == 15) +#if (DT_I2C_GECKO_0_LOCATION == 15) #define PIN_I2C0_SDA {gpioPortC, 10, gpioModeWiredAnd, 1} #define PIN_I2C0_SCL {gpioPortC, 11, gpioModeWiredAnd, 1} #else @@ -48,7 +48,7 @@ #endif /* CONFIG_I2C_0 */ #ifdef CONFIG_I2C_1 -#if (CONFIG_I2C_GECKO_1_LOCATION == 17) +#if (DT_I2C_GECKO_1_LOCATION == 17) #define PIN_I2C1_SDA {gpioPortC, 4, gpioModeWiredAnd, 1} #define PIN_I2C1_SCL {gpioPortC, 5, gpioModeWiredAnd, 1} #else diff --git a/soc/arm/st_stm32/stm32f0/dts_fixup.h b/soc/arm/st_stm32/stm32f0/dts_fixup.h index fbf0cff7ed8..9987b673cd5 100644 --- a/soc/arm/st_stm32/stm32f0/dts_fixup.h +++ b/soc/arm/st_stm32/stm32f0/dts_fixup.h @@ -1,148 +1,148 @@ /* SoC level DTS fixup file */ -#define CONFIG_NUM_IRQ_PRIO_BITS DT_ARM_V6M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS +#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V6M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS -#define CONFIG_GPIO_STM32_GPIOA_BASE_ADDRESS DT_ST_STM32_GPIO_48000000_BASE_ADDRESS -#define CONFIG_GPIO_STM32_GPIOA_CLOCK_BITS_0 DT_ST_STM32_GPIO_48000000_CLOCK_BITS_0 -#define CONFIG_GPIO_STM32_GPIOA_CLOCK_BUS_0 DT_ST_STM32_GPIO_48000000_CLOCK_BUS_0 -#define CONFIG_GPIO_STM32_GPIOA_CLOCK_CONTROLLER DT_ST_STM32_GPIO_48000000_CLOCK_CONTROLLER -#define CONFIG_GPIO_STM32_GPIOA_LABEL DT_ST_STM32_GPIO_48000000_LABEL -#define CONFIG_GPIO_STM32_GPIOA_SIZE DT_ST_STM32_GPIO_48000000_SIZE -#define CONFIG_GPIO_STM32_GPIOA_CLOCK_BITS DT_ST_STM32_GPIO_48000000_CLOCK_BITS -#define CONFIG_GPIO_STM32_GPIOA_CLOCK_BUS DT_ST_STM32_GPIO_48000000_CLOCK_BUS +#define DT_GPIO_STM32_GPIOA_BASE_ADDRESS DT_ST_STM32_GPIO_48000000_BASE_ADDRESS +#define DT_GPIO_STM32_GPIOA_CLOCK_BITS_0 DT_ST_STM32_GPIO_48000000_CLOCK_BITS_0 +#define DT_GPIO_STM32_GPIOA_CLOCK_BUS_0 DT_ST_STM32_GPIO_48000000_CLOCK_BUS_0 +#define DT_GPIO_STM32_GPIOA_CLOCK_CONTROLLER DT_ST_STM32_GPIO_48000000_CLOCK_CONTROLLER +#define DT_GPIO_STM32_GPIOA_LABEL DT_ST_STM32_GPIO_48000000_LABEL +#define DT_GPIO_STM32_GPIOA_SIZE DT_ST_STM32_GPIO_48000000_SIZE +#define DT_GPIO_STM32_GPIOA_CLOCK_BITS DT_ST_STM32_GPIO_48000000_CLOCK_BITS +#define DT_GPIO_STM32_GPIOA_CLOCK_BUS DT_ST_STM32_GPIO_48000000_CLOCK_BUS -#define CONFIG_GPIO_STM32_GPIOB_BASE_ADDRESS DT_ST_STM32_GPIO_48000400_BASE_ADDRESS -#define CONFIG_GPIO_STM32_GPIOB_CLOCK_BITS_0 DT_ST_STM32_GPIO_48000400_CLOCK_BITS_0 -#define CONFIG_GPIO_STM32_GPIOB_CLOCK_BUS_0 DT_ST_STM32_GPIO_48000400_CLOCK_BUS_0 -#define CONFIG_GPIO_STM32_GPIOB_CLOCK_CONTROLLER DT_ST_STM32_GPIO_48000400_CLOCK_CONTROLLER -#define CONFIG_GPIO_STM32_GPIOB_LABEL DT_ST_STM32_GPIO_48000400_LABEL -#define CONFIG_GPIO_STM32_GPIOB_SIZE DT_ST_STM32_GPIO_48000400_SIZE -#define CONFIG_GPIO_STM32_GPIOB_CLOCK_BITS DT_ST_STM32_GPIO_48000400_CLOCK_BITS -#define CONFIG_GPIO_STM32_GPIOB_CLOCK_BUS DT_ST_STM32_GPIO_48000400_CLOCK_BUS +#define DT_GPIO_STM32_GPIOB_BASE_ADDRESS DT_ST_STM32_GPIO_48000400_BASE_ADDRESS +#define DT_GPIO_STM32_GPIOB_CLOCK_BITS_0 DT_ST_STM32_GPIO_48000400_CLOCK_BITS_0 +#define DT_GPIO_STM32_GPIOB_CLOCK_BUS_0 DT_ST_STM32_GPIO_48000400_CLOCK_BUS_0 +#define DT_GPIO_STM32_GPIOB_CLOCK_CONTROLLER DT_ST_STM32_GPIO_48000400_CLOCK_CONTROLLER +#define DT_GPIO_STM32_GPIOB_LABEL DT_ST_STM32_GPIO_48000400_LABEL +#define DT_GPIO_STM32_GPIOB_SIZE DT_ST_STM32_GPIO_48000400_SIZE +#define DT_GPIO_STM32_GPIOB_CLOCK_BITS DT_ST_STM32_GPIO_48000400_CLOCK_BITS +#define DT_GPIO_STM32_GPIOB_CLOCK_BUS DT_ST_STM32_GPIO_48000400_CLOCK_BUS -#define CONFIG_GPIO_STM32_GPIOC_BASE_ADDRESS DT_ST_STM32_GPIO_48000800_BASE_ADDRESS -#define CONFIG_GPIO_STM32_GPIOC_CLOCK_BITS_0 DT_ST_STM32_GPIO_48000800_CLOCK_BITS_0 -#define CONFIG_GPIO_STM32_GPIOC_CLOCK_BUS_0 DT_ST_STM32_GPIO_48000800_CLOCK_BUS_0 -#define CONFIG_GPIO_STM32_GPIOC_CLOCK_CONTROLLER DT_ST_STM32_GPIO_48000800_CLOCK_CONTROLLER -#define CONFIG_GPIO_STM32_GPIOC_LABEL DT_ST_STM32_GPIO_48000800_LABEL -#define CONFIG_GPIO_STM32_GPIOC_SIZE DT_ST_STM32_GPIO_48000800_SIZE -#define CONFIG_GPIO_STM32_GPIOC_CLOCK_BITS DT_ST_STM32_GPIO_48000800_CLOCK_BITS -#define CONFIG_GPIO_STM32_GPIOC_CLOCK_BUS DT_ST_STM32_GPIO_48000800_CLOCK_BUS +#define DT_GPIO_STM32_GPIOC_BASE_ADDRESS DT_ST_STM32_GPIO_48000800_BASE_ADDRESS +#define DT_GPIO_STM32_GPIOC_CLOCK_BITS_0 DT_ST_STM32_GPIO_48000800_CLOCK_BITS_0 +#define DT_GPIO_STM32_GPIOC_CLOCK_BUS_0 DT_ST_STM32_GPIO_48000800_CLOCK_BUS_0 +#define DT_GPIO_STM32_GPIOC_CLOCK_CONTROLLER DT_ST_STM32_GPIO_48000800_CLOCK_CONTROLLER +#define DT_GPIO_STM32_GPIOC_LABEL DT_ST_STM32_GPIO_48000800_LABEL +#define DT_GPIO_STM32_GPIOC_SIZE DT_ST_STM32_GPIO_48000800_SIZE +#define DT_GPIO_STM32_GPIOC_CLOCK_BITS DT_ST_STM32_GPIO_48000800_CLOCK_BITS +#define DT_GPIO_STM32_GPIOC_CLOCK_BUS DT_ST_STM32_GPIO_48000800_CLOCK_BUS -#define CONFIG_GPIO_STM32_GPIOD_BASE_ADDRESS DT_ST_STM32_GPIO_48000C00_BASE_ADDRESS -#define CONFIG_GPIO_STM32_GPIOD_CLOCK_BITS_0 DT_ST_STM32_GPIO_48000C00_CLOCK_BITS_0 -#define CONFIG_GPIO_STM32_GPIOD_CLOCK_BUS_0 DT_ST_STM32_GPIO_48000C00_CLOCK_BUS_0 -#define CONFIG_GPIO_STM32_GPIOD_CLOCK_CONTROLLER DT_ST_STM32_GPIO_48000C00_CLOCK_CONTROLLER -#define CONFIG_GPIO_STM32_GPIOD_LABEL DT_ST_STM32_GPIO_48000C00_LABEL -#define CONFIG_GPIO_STM32_GPIOD_SIZE DT_ST_STM32_GPIO_48000C00_SIZE -#define CONFIG_GPIO_STM32_GPIOD_CLOCK_BITS DT_ST_STM32_GPIO_48000C00_CLOCK_BITS -#define CONFIG_GPIO_STM32_GPIOD_CLOCK_BUS DT_ST_STM32_GPIO_48000C00_CLOCK_BUS +#define DT_GPIO_STM32_GPIOD_BASE_ADDRESS DT_ST_STM32_GPIO_48000C00_BASE_ADDRESS +#define DT_GPIO_STM32_GPIOD_CLOCK_BITS_0 DT_ST_STM32_GPIO_48000C00_CLOCK_BITS_0 +#define DT_GPIO_STM32_GPIOD_CLOCK_BUS_0 DT_ST_STM32_GPIO_48000C00_CLOCK_BUS_0 +#define DT_GPIO_STM32_GPIOD_CLOCK_CONTROLLER DT_ST_STM32_GPIO_48000C00_CLOCK_CONTROLLER +#define DT_GPIO_STM32_GPIOD_LABEL DT_ST_STM32_GPIO_48000C00_LABEL +#define DT_GPIO_STM32_GPIOD_SIZE DT_ST_STM32_GPIO_48000C00_SIZE +#define DT_GPIO_STM32_GPIOD_CLOCK_BITS DT_ST_STM32_GPIO_48000C00_CLOCK_BITS +#define DT_GPIO_STM32_GPIOD_CLOCK_BUS DT_ST_STM32_GPIO_48000C00_CLOCK_BUS -#define CONFIG_GPIO_STM32_GPIOE_BASE_ADDRESS DT_ST_STM32_GPIO_48001000_BASE_ADDRESS -#define CONFIG_GPIO_STM32_GPIOE_CLOCK_BITS_0 DT_ST_STM32_GPIO_48001000_CLOCK_BITS_0 -#define CONFIG_GPIO_STM32_GPIOE_CLOCK_BUS_0 DT_ST_STM32_GPIO_48001000_CLOCK_BUS_0 -#define CONFIG_GPIO_STM32_GPIOE_CLOCK_CONTROLLER DT_ST_STM32_GPIO_48001000_CLOCK_CONTROLLER -#define CONFIG_GPIO_STM32_GPIOE_LABEL DT_ST_STM32_GPIO_48001000_LABEL -#define CONFIG_GPIO_STM32_GPIOE_SIZE DT_ST_STM32_GPIO_48001000_SIZE -#define CONFIG_GPIO_STM32_GPIOE_CLOCK_BITS DT_ST_STM32_GPIO_48001000_CLOCK_BITS -#define CONFIG_GPIO_STM32_GPIOE_CLOCK_BUS DT_ST_STM32_GPIO_48001000_CLOCK_BUS +#define DT_GPIO_STM32_GPIOE_BASE_ADDRESS DT_ST_STM32_GPIO_48001000_BASE_ADDRESS +#define DT_GPIO_STM32_GPIOE_CLOCK_BITS_0 DT_ST_STM32_GPIO_48001000_CLOCK_BITS_0 +#define DT_GPIO_STM32_GPIOE_CLOCK_BUS_0 DT_ST_STM32_GPIO_48001000_CLOCK_BUS_0 +#define DT_GPIO_STM32_GPIOE_CLOCK_CONTROLLER DT_ST_STM32_GPIO_48001000_CLOCK_CONTROLLER +#define DT_GPIO_STM32_GPIOE_LABEL DT_ST_STM32_GPIO_48001000_LABEL +#define DT_GPIO_STM32_GPIOE_SIZE DT_ST_STM32_GPIO_48001000_SIZE +#define DT_GPIO_STM32_GPIOE_CLOCK_BITS DT_ST_STM32_GPIO_48001000_CLOCK_BITS +#define DT_GPIO_STM32_GPIOE_CLOCK_BUS DT_ST_STM32_GPIO_48001000_CLOCK_BUS -#define CONFIG_GPIO_STM32_GPIOF_BASE_ADDRESS DT_ST_STM32_GPIO_48001400_BASE_ADDRESS -#define CONFIG_GPIO_STM32_GPIOF_CLOCK_BITS_0 DT_ST_STM32_GPIO_48001400_CLOCK_BITS_0 -#define CONFIG_GPIO_STM32_GPIOF_CLOCK_BUS_0 DT_ST_STM32_GPIO_48001400_CLOCK_BUS_0 -#define CONFIG_GPIO_STM32_GPIOF_CLOCK_CONTROLLER DT_ST_STM32_GPIO_48001400_CLOCK_CONTROLLER -#define CONFIG_GPIO_STM32_GPIOF_LABEL DT_ST_STM32_GPIO_48001400_LABEL -#define CONFIG_GPIO_STM32_GPIOF_SIZE DT_ST_STM32_GPIO_48001400_SIZE -#define CONFIG_GPIO_STM32_GPIOF_CLOCK_BITS DT_ST_STM32_GPIO_48001400_CLOCK_BITS -#define CONFIG_GPIO_STM32_GPIOF_CLOCK_BUS DT_ST_STM32_GPIO_48001400_CLOCK_BUS +#define DT_GPIO_STM32_GPIOF_BASE_ADDRESS DT_ST_STM32_GPIO_48001400_BASE_ADDRESS +#define DT_GPIO_STM32_GPIOF_CLOCK_BITS_0 DT_ST_STM32_GPIO_48001400_CLOCK_BITS_0 +#define DT_GPIO_STM32_GPIOF_CLOCK_BUS_0 DT_ST_STM32_GPIO_48001400_CLOCK_BUS_0 +#define DT_GPIO_STM32_GPIOF_CLOCK_CONTROLLER DT_ST_STM32_GPIO_48001400_CLOCK_CONTROLLER +#define DT_GPIO_STM32_GPIOF_LABEL DT_ST_STM32_GPIO_48001400_LABEL +#define DT_GPIO_STM32_GPIOF_SIZE DT_ST_STM32_GPIO_48001400_SIZE +#define DT_GPIO_STM32_GPIOF_CLOCK_BITS DT_ST_STM32_GPIO_48001400_CLOCK_BITS +#define DT_GPIO_STM32_GPIOF_CLOCK_BUS DT_ST_STM32_GPIO_48001400_CLOCK_BUS -#define CONFIG_UART_STM32_USART_1_BASE_ADDRESS DT_ST_STM32_USART_40013800_BASE_ADDRESS -#define CONFIG_UART_STM32_USART_1_BAUD_RATE DT_ST_STM32_USART_40013800_CURRENT_SPEED -#define CONFIG_UART_STM32_USART_1_IRQ_PRI DT_ST_STM32_USART_40013800_IRQ_0_PRIORITY -#define CONFIG_UART_STM32_USART_1_NAME DT_ST_STM32_USART_40013800_LABEL -#define USART_1_IRQ DT_ST_STM32_USART_40013800_IRQ_0 -#define CONFIG_UART_STM32_USART_1_CLOCK_BITS DT_ST_STM32_USART_40013800_CLOCK_BITS -#define CONFIG_UART_STM32_USART_1_CLOCK_BUS DT_ST_STM32_USART_40013800_CLOCK_BUS +#define DT_UART_STM32_USART_1_BASE_ADDRESS DT_ST_STM32_USART_40013800_BASE_ADDRESS +#define DT_UART_STM32_USART_1_BAUD_RATE DT_ST_STM32_USART_40013800_CURRENT_SPEED +#define DT_UART_STM32_USART_1_IRQ_PRI DT_ST_STM32_USART_40013800_IRQ_0_PRIORITY +#define DT_UART_STM32_USART_1_NAME DT_ST_STM32_USART_40013800_LABEL +#define DT_USART_1_IRQ DT_ST_STM32_USART_40013800_IRQ_0 +#define DT_UART_STM32_USART_1_CLOCK_BITS DT_ST_STM32_USART_40013800_CLOCK_BITS +#define DT_UART_STM32_USART_1_CLOCK_BUS DT_ST_STM32_USART_40013800_CLOCK_BUS -#define CONFIG_UART_STM32_USART_2_BASE_ADDRESS DT_ST_STM32_USART_40004400_BASE_ADDRESS -#define CONFIG_UART_STM32_USART_2_BAUD_RATE DT_ST_STM32_USART_40004400_CURRENT_SPEED -#define CONFIG_UART_STM32_USART_2_IRQ_PRI DT_ST_STM32_USART_40004400_IRQ_0_PRIORITY -#define CONFIG_UART_STM32_USART_2_NAME DT_ST_STM32_USART_40004400_LABEL -#define USART_2_IRQ DT_ST_STM32_USART_40004400_IRQ_0 -#define CONFIG_UART_STM32_USART_2_CLOCK_BITS DT_ST_STM32_USART_40004400_CLOCK_BITS -#define CONFIG_UART_STM32_USART_2_CLOCK_BUS DT_ST_STM32_USART_40004400_CLOCK_BUS +#define DT_UART_STM32_USART_2_BASE_ADDRESS DT_ST_STM32_USART_40004400_BASE_ADDRESS +#define DT_UART_STM32_USART_2_BAUD_RATE DT_ST_STM32_USART_40004400_CURRENT_SPEED +#define DT_UART_STM32_USART_2_IRQ_PRI DT_ST_STM32_USART_40004400_IRQ_0_PRIORITY +#define DT_UART_STM32_USART_2_NAME DT_ST_STM32_USART_40004400_LABEL +#define DT_USART_2_IRQ DT_ST_STM32_USART_40004400_IRQ_0 +#define DT_UART_STM32_USART_2_CLOCK_BITS DT_ST_STM32_USART_40004400_CLOCK_BITS +#define DT_UART_STM32_USART_2_CLOCK_BUS DT_ST_STM32_USART_40004400_CLOCK_BUS -#define CONFIG_I2C_1_BASE_ADDRESS DT_ST_STM32_I2C_V2_40005400_BASE_ADDRESS -#define CONFIG_I2C_1_COMBINED_IRQ_PRI DT_ST_STM32_I2C_V2_40005400_IRQ_COMBINED_PRIORITY +#define DT_I2C_1_BASE_ADDRESS DT_ST_STM32_I2C_V2_40005400_BASE_ADDRESS +#define DT_I2C_1_COMBINED_IRQ_PRI DT_ST_STM32_I2C_V2_40005400_IRQ_COMBINED_PRIORITY #define CONFIG_I2C_1_NAME DT_ST_STM32_I2C_V2_40005400_LABEL -#define CONFIG_I2C_1_COMBINED_IRQ DT_ST_STM32_I2C_V2_40005400_IRQ_COMBINED -#define CONFIG_I2C_1_BITRATE DT_ST_STM32_I2C_V2_40005400_CLOCK_FREQUENCY -#define CONFIG_I2C_1_CLOCK_BITS DT_ST_STM32_I2C_V2_40005400_CLOCK_BITS -#define CONFIG_I2C_1_CLOCK_BUS DT_ST_STM32_I2C_V2_40005400_CLOCK_BUS +#define DT_I2C_1_COMBINED_IRQ DT_ST_STM32_I2C_V2_40005400_IRQ_COMBINED +#define DT_I2C_1_BITRATE DT_ST_STM32_I2C_V2_40005400_CLOCK_FREQUENCY +#define DT_I2C_1_CLOCK_BITS DT_ST_STM32_I2C_V2_40005400_CLOCK_BITS +#define DT_I2C_1_CLOCK_BUS DT_ST_STM32_I2C_V2_40005400_CLOCK_BUS -#define CONFIG_I2C_2_BASE_ADDRESS DT_ST_STM32_I2C_V2_40005800_BASE_ADDRESS -#define CONFIG_I2C_2_COMBINED_IRQ_PRI DT_ST_STM32_I2C_V2_40005800_IRQ_COMBINED_PRIORITY +#define DT_I2C_2_BASE_ADDRESS DT_ST_STM32_I2C_V2_40005800_BASE_ADDRESS +#define DT_I2C_2_COMBINED_IRQ_PRI DT_ST_STM32_I2C_V2_40005800_IRQ_COMBINED_PRIORITY #define CONFIG_I2C_2_NAME DT_ST_STM32_I2C_V2_40005800_LABEL -#define CONFIG_I2C_2_COMBINED_IRQ DT_ST_STM32_I2C_V2_40005800_IRQ_COMBINED -#define CONFIG_I2C_2_BITRATE DT_ST_STM32_I2C_V2_40005800_CLOCK_FREQUENCY -#define CONFIG_I2C_2_CLOCK_BITS DT_ST_STM32_I2C_V2_40005800_CLOCK_BITS -#define CONFIG_I2C_2_CLOCK_BUS DT_ST_STM32_I2C_V2_40005800_CLOCK_BUS +#define DT_I2C_2_COMBINED_IRQ DT_ST_STM32_I2C_V2_40005800_IRQ_COMBINED +#define DT_I2C_2_BITRATE DT_ST_STM32_I2C_V2_40005800_CLOCK_FREQUENCY +#define DT_I2C_2_CLOCK_BITS DT_ST_STM32_I2C_V2_40005800_CLOCK_BITS +#define DT_I2C_2_CLOCK_BUS DT_ST_STM32_I2C_V2_40005800_CLOCK_BUS -#define CONFIG_SPI_1_BASE_ADDRESS DT_ST_STM32_SPI_FIFO_40013000_BASE_ADDRESS +#define DT_SPI_1_BASE_ADDRESS DT_ST_STM32_SPI_FIFO_40013000_BASE_ADDRESS #define CONFIG_SPI_1_IRQ_PRI DT_ST_STM32_SPI_FIFO_40013000_IRQ_0_PRIORITY #define CONFIG_SPI_1_NAME DT_ST_STM32_SPI_FIFO_40013000_LABEL -#define CONFIG_SPI_1_IRQ DT_ST_STM32_SPI_FIFO_40013000_IRQ_0 +#define DT_SPI_1_IRQ DT_ST_STM32_SPI_FIFO_40013000_IRQ_0 -#define CONFIG_SPI_2_BASE_ADDRESS DT_ST_STM32_SPI_FIFO_40003800_BASE_ADDRESS +#define DT_SPI_2_BASE_ADDRESS DT_ST_STM32_SPI_FIFO_40003800_BASE_ADDRESS #define CONFIG_SPI_2_IRQ_PRI DT_ST_STM32_SPI_FIFO_40003800_IRQ_0_PRIORITY #define CONFIG_SPI_2_NAME DT_ST_STM32_SPI_FIFO_40003800_LABEL -#define CONFIG_SPI_2_IRQ DT_ST_STM32_SPI_FIFO_40003800_IRQ_0 +#define DT_SPI_2_IRQ DT_ST_STM32_SPI_FIFO_40003800_IRQ_0 -#define CONFIG_CAN_1_BASE_ADDRESS DT_ST_STM32_CAN_40006400_BASE_ADDRESS -#define CONFIG_CAN_1_BUS_SPEED DT_ST_STM32_CAN_40006400_BUS_SPEED -#define CONFIG_CAN_1_NAME DT_ST_STM32_CAN_40006400_LABEL -#define CONFIG_CAN_1_IRQ DT_ST_STM32_CAN_40006400_IRQ_0 -#define CONFIG_CAN_1_IRQ_PRIORITY DT_ST_STM32_CAN_40006400_IRQ_0_PRIORITY -#define CONFIG_CAN_1_SJW DT_ST_STM32_CAN_40006400_SJW -#define CONFIG_CAN_1_PROP_SEG_PHASE_SEG1 DT_ST_STM32_CAN_40006400_PROP_SEG_PHASE_SEG1 -#define CONFIG_CAN_1_PHASE_SEG2 DT_ST_STM32_CAN_40006400_PHASE_SEG2 -#define CONFIG_CAN_1_CLOCK_BUS DT_ST_STM32_CAN_40006400_CLOCK_BUS -#define CONFIG_CAN_1_CLOCK_BITS DT_ST_STM32_CAN_40006400_CLOCK_BITS +#define DT_CAN_1_BASE_ADDRESS DT_ST_STM32_CAN_40006400_BASE_ADDRESS +#define DT_CAN_1_BUS_SPEED DT_ST_STM32_CAN_40006400_BUS_SPEED +#define DT_CAN_1_NAME DT_ST_STM32_CAN_40006400_LABEL +#define DT_CAN_1_IRQ DT_ST_STM32_CAN_40006400_IRQ_0 +#define DT_CAN_1_IRQ_PRIORITY DT_ST_STM32_CAN_40006400_IRQ_0_PRIORITY +#define DT_CAN_1_SJW DT_ST_STM32_CAN_40006400_SJW +#define DT_CAN_1_PROP_SEG_PHASE_SEG1 DT_ST_STM32_CAN_40006400_PROP_SEG_PHASE_SEG1 +#define DT_CAN_1_PHASE_SEG2 DT_ST_STM32_CAN_40006400_PHASE_SEG2 +#define DT_CAN_1_CLOCK_BUS DT_ST_STM32_CAN_40006400_CLOCK_BUS +#define DT_CAN_1_CLOCK_BITS DT_ST_STM32_CAN_40006400_CLOCK_BITS -#define FLASH_DEV_BASE_ADDRESS DT_ST_STM32F0_FLASH_CONTROLLER_40022000_BASE_ADDRESS -#define FLASH_DEV_NAME DT_ST_STM32F0_FLASH_CONTROLLER_40022000_LABEL +#define DT_FLASH_DEV_BASE_ADDRESS DT_ST_STM32F0_FLASH_CONTROLLER_40022000_BASE_ADDRESS +#define DT_FLASH_DEV_NAME DT_ST_STM32F0_FLASH_CONTROLLER_40022000_LABEL -#define CONFIG_USB_BASE_ADDRESS DT_ST_STM32_USB_40005C00_BASE_ADDRESS -#define CONFIG_USB_IRQ DT_ST_STM32_USB_40005C00_IRQ_USB -#define CONFIG_USB_IRQ_PRI DT_ST_STM32_USB_40005C00_IRQ_USB_PRIORITY -#define CONFIG_USB_NUM_BIDIR_ENDPOINTS DT_ST_STM32_USB_40005C00_NUM_BIDIR_ENDPOINTS -#define CONFIG_USB_RAM_SIZE DT_ST_STM32_USB_40005C00_RAM_SIZE +#define DT_USB_BASE_ADDRESS DT_ST_STM32_USB_40005C00_BASE_ADDRESS +#define DT_USB_IRQ DT_ST_STM32_USB_40005C00_IRQ_USB +#define DT_USB_IRQ_PRI DT_ST_STM32_USB_40005C00_IRQ_USB_PRIORITY +#define DT_USB_NUM_BIDIR_ENDPOINTS DT_ST_STM32_USB_40005C00_NUM_BIDIR_ENDPOINTS +#define DT_USB_RAM_SIZE DT_ST_STM32_USB_40005C00_RAM_SIZE -#define CONFIG_PWM_STM32_1_DEV_NAME DT_ST_STM32_PWM_40012C00_PWM_LABEL -#define CONFIG_PWM_STM32_1_PRESCALER DT_ST_STM32_PWM_40012C00_PWM_ST_PRESCALER +#define DT_PWM_STM32_1_DEV_NAME DT_ST_STM32_PWM_40012C00_PWM_LABEL +#define DT_PWM_STM32_1_PRESCALER DT_ST_STM32_PWM_40012C00_PWM_ST_PRESCALER -#define CONFIG_PWM_STM32_2_DEV_NAME DT_ST_STM32_PWM_40000000_PWM_LABEL -#define CONFIG_PWM_STM32_2_PRESCALER DT_ST_STM32_PWM_40000000_PWM_ST_PRESCALER +#define DT_PWM_STM32_2_DEV_NAME DT_ST_STM32_PWM_40000000_PWM_LABEL +#define DT_PWM_STM32_2_PRESCALER DT_ST_STM32_PWM_40000000_PWM_ST_PRESCALER -#define CONFIG_PWM_STM32_3_DEV_NAME DT_ST_STM32_PWM_40000400_PWM_LABEL -#define CONFIG_PWM_STM32_3_PRESCALER DT_ST_STM32_PWM_40000400_PWM_ST_PRESCALER +#define DT_PWM_STM32_3_DEV_NAME DT_ST_STM32_PWM_40000400_PWM_LABEL +#define DT_PWM_STM32_3_PRESCALER DT_ST_STM32_PWM_40000400_PWM_ST_PRESCALER -#define CONFIG_PWM_STM32_6_DEV_NAME DT_ST_STM32_PWM_40001000_PWM_LABEL -#define CONFIG_PWM_STM32_6_PRESCALER DT_ST_STM32_PWM_40001000_PWM_ST_PRESCALER +#define DT_PWM_STM32_6_DEV_NAME DT_ST_STM32_PWM_40001000_PWM_LABEL +#define DT_PWM_STM32_6_PRESCALER DT_ST_STM32_PWM_40001000_PWM_ST_PRESCALER -#define CONFIG_PWM_STM32_7_DEV_NAME DT_ST_STM32_PWM_40001400_PWM_LABEL -#define CONFIG_PWM_STM32_7_PRESCALER DT_ST_STM32_PWM_40001400_PWM_ST_PRESCALER +#define DT_PWM_STM32_7_DEV_NAME DT_ST_STM32_PWM_40001400_PWM_LABEL +#define DT_PWM_STM32_7_PRESCALER DT_ST_STM32_PWM_40001400_PWM_ST_PRESCALER -#define CONFIG_PWM_STM32_14_DEV_NAME DT_ST_STM32_PWM_40002000_PWM_LABEL -#define CONFIG_PWM_STM32_14_PRESCALER DT_ST_STM32_PWM_40002000_PWM_ST_PRESCALER +#define DT_PWM_STM32_14_DEV_NAME DT_ST_STM32_PWM_40002000_PWM_LABEL +#define DT_PWM_STM32_14_PRESCALER DT_ST_STM32_PWM_40002000_PWM_ST_PRESCALER -#define CONFIG_PWM_STM32_15_DEV_NAME DT_ST_STM32_PWM_40014000_PWM_LABEL -#define CONFIG_PWM_STM32_15_PRESCALER DT_ST_STM32_PWM_40014000_PWM_ST_PRESCALER +#define DT_PWM_STM32_15_DEV_NAME DT_ST_STM32_PWM_40014000_PWM_LABEL +#define DT_PWM_STM32_15_PRESCALER DT_ST_STM32_PWM_40014000_PWM_ST_PRESCALER -#define CONFIG_PWM_STM32_16_DEV_NAME DT_ST_STM32_PWM_40014400_PWM_LABEL -#define CONFIG_PWM_STM32_16_PRESCALER DT_ST_STM32_PWM_40014400_PWM_ST_PRESCALER +#define DT_PWM_STM32_16_DEV_NAME DT_ST_STM32_PWM_40014400_PWM_LABEL +#define DT_PWM_STM32_16_PRESCALER DT_ST_STM32_PWM_40014400_PWM_ST_PRESCALER -#define CONFIG_PWM_STM32_17_DEV_NAME DT_ST_STM32_PWM_40014800_PWM_LABEL -#define CONFIG_PWM_STM32_17_PRESCALER DT_ST_STM32_PWM_40014800_PWM_ST_PRESCALER +#define DT_PWM_STM32_17_DEV_NAME DT_ST_STM32_PWM_40014800_PWM_LABEL +#define DT_PWM_STM32_17_PRESCALER DT_ST_STM32_PWM_40014800_PWM_ST_PRESCALER /* End of SoC Level DTS fixup file */ diff --git a/soc/arm/st_stm32/stm32f1/dts_fixup.h b/soc/arm/st_stm32/stm32f1/dts_fixup.h index 23152622014..4072e0d3ca9 100644 --- a/soc/arm/st_stm32/stm32f1/dts_fixup.h +++ b/soc/arm/st_stm32/stm32f1/dts_fixup.h @@ -1,165 +1,165 @@ /* SoC level DTS fixup file */ -#define CONFIG_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS +#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS -#define CONFIG_GPIO_STM32_GPIOA_BASE_ADDRESS DT_ST_STM32_GPIO_40010800_BASE_ADDRESS -#define CONFIG_GPIO_STM32_GPIOA_CLOCK_BITS_0 DT_ST_STM32_GPIO_40010800_CLOCK_BITS_0 -#define CONFIG_GPIO_STM32_GPIOA_CLOCK_BUS_0 DT_ST_STM32_GPIO_40010800_CLOCK_BUS_0 -#define CONFIG_GPIO_STM32_GPIOA_CLOCK_CONTROLLER DT_ST_STM32_GPIO_40010800_CLOCK_CONTROLLER -#define CONFIG_GPIO_STM32_GPIOA_LABEL DT_ST_STM32_GPIO_40010800_LABEL -#define CONFIG_GPIO_STM32_GPIOA_SIZE DT_ST_STM32_GPIO_40010800_SIZE -#define CONFIG_GPIO_STM32_GPIOA_CLOCK_BITS DT_ST_STM32_GPIO_40010800_CLOCK_BITS -#define CONFIG_GPIO_STM32_GPIOA_CLOCK_BUS DT_ST_STM32_GPIO_40010800_CLOCK_BUS +#define DT_GPIO_STM32_GPIOA_BASE_ADDRESS DT_ST_STM32_GPIO_40010800_BASE_ADDRESS +#define DT_GPIO_STM32_GPIOA_CLOCK_BITS_0 DT_ST_STM32_GPIO_40010800_CLOCK_BITS_0 +#define DT_GPIO_STM32_GPIOA_CLOCK_BUS_0 DT_ST_STM32_GPIO_40010800_CLOCK_BUS_0 +#define DT_GPIO_STM32_GPIOA_CLOCK_CONTROLLER DT_ST_STM32_GPIO_40010800_CLOCK_CONTROLLER +#define DT_GPIO_STM32_GPIOA_LABEL DT_ST_STM32_GPIO_40010800_LABEL +#define DT_GPIO_STM32_GPIOA_SIZE DT_ST_STM32_GPIO_40010800_SIZE +#define DT_GPIO_STM32_GPIOA_CLOCK_BITS DT_ST_STM32_GPIO_40010800_CLOCK_BITS +#define DT_GPIO_STM32_GPIOA_CLOCK_BUS DT_ST_STM32_GPIO_40010800_CLOCK_BUS -#define CONFIG_GPIO_STM32_GPIOB_BASE_ADDRESS DT_ST_STM32_GPIO_40010C00_BASE_ADDRESS -#define CONFIG_GPIO_STM32_GPIOB_CLOCK_BITS_0 DT_ST_STM32_GPIO_40010C00_CLOCK_BITS_0 -#define CONFIG_GPIO_STM32_GPIOB_CLOCK_BUS_0 DT_ST_STM32_GPIO_40010C00_CLOCK_BUS_0 -#define CONFIG_GPIO_STM32_GPIOB_CLOCK_CONTROLLER DT_ST_STM32_GPIO_40010C00_CLOCK_CONTROLLER -#define CONFIG_GPIO_STM32_GPIOB_LABEL DT_ST_STM32_GPIO_40010C00_LABEL -#define CONFIG_GPIO_STM32_GPIOB_SIZE DT_ST_STM32_GPIO_40010C00_SIZE -#define CONFIG_GPIO_STM32_GPIOB_CLOCK_BITS DT_ST_STM32_GPIO_40010C00_CLOCK_BITS -#define CONFIG_GPIO_STM32_GPIOB_CLOCK_BUS DT_ST_STM32_GPIO_40010C00_CLOCK_BUS +#define DT_GPIO_STM32_GPIOB_BASE_ADDRESS DT_ST_STM32_GPIO_40010C00_BASE_ADDRESS +#define DT_GPIO_STM32_GPIOB_CLOCK_BITS_0 DT_ST_STM32_GPIO_40010C00_CLOCK_BITS_0 +#define DT_GPIO_STM32_GPIOB_CLOCK_BUS_0 DT_ST_STM32_GPIO_40010C00_CLOCK_BUS_0 +#define DT_GPIO_STM32_GPIOB_CLOCK_CONTROLLER DT_ST_STM32_GPIO_40010C00_CLOCK_CONTROLLER +#define DT_GPIO_STM32_GPIOB_LABEL DT_ST_STM32_GPIO_40010C00_LABEL +#define DT_GPIO_STM32_GPIOB_SIZE DT_ST_STM32_GPIO_40010C00_SIZE +#define DT_GPIO_STM32_GPIOB_CLOCK_BITS DT_ST_STM32_GPIO_40010C00_CLOCK_BITS +#define DT_GPIO_STM32_GPIOB_CLOCK_BUS DT_ST_STM32_GPIO_40010C00_CLOCK_BUS -#define CONFIG_GPIO_STM32_GPIOC_BASE_ADDRESS DT_ST_STM32_GPIO_40011000_BASE_ADDRESS -#define CONFIG_GPIO_STM32_GPIOC_CLOCK_BITS_0 DT_ST_STM32_GPIO_40011000_CLOCK_BITS_0 -#define CONFIG_GPIO_STM32_GPIOC_CLOCK_BUS_0 DT_ST_STM32_GPIO_40011000_CLOCK_BUS_0 -#define CONFIG_GPIO_STM32_GPIOC_CLOCK_CONTROLLER DT_ST_STM32_GPIO_40011000_CLOCK_CONTROLLER -#define CONFIG_GPIO_STM32_GPIOC_LABEL DT_ST_STM32_GPIO_40011000_LABEL -#define CONFIG_GPIO_STM32_GPIOC_SIZE DT_ST_STM32_GPIO_40011000_SIZE -#define CONFIG_GPIO_STM32_GPIOC_CLOCK_BITS DT_ST_STM32_GPIO_40011000_CLOCK_BITS -#define CONFIG_GPIO_STM32_GPIOC_CLOCK_BUS DT_ST_STM32_GPIO_40011000_CLOCK_BUS +#define DT_GPIO_STM32_GPIOC_BASE_ADDRESS DT_ST_STM32_GPIO_40011000_BASE_ADDRESS +#define DT_GPIO_STM32_GPIOC_CLOCK_BITS_0 DT_ST_STM32_GPIO_40011000_CLOCK_BITS_0 +#define DT_GPIO_STM32_GPIOC_CLOCK_BUS_0 DT_ST_STM32_GPIO_40011000_CLOCK_BUS_0 +#define DT_GPIO_STM32_GPIOC_CLOCK_CONTROLLER DT_ST_STM32_GPIO_40011000_CLOCK_CONTROLLER +#define DT_GPIO_STM32_GPIOC_LABEL DT_ST_STM32_GPIO_40011000_LABEL +#define DT_GPIO_STM32_GPIOC_SIZE DT_ST_STM32_GPIO_40011000_SIZE +#define DT_GPIO_STM32_GPIOC_CLOCK_BITS DT_ST_STM32_GPIO_40011000_CLOCK_BITS +#define DT_GPIO_STM32_GPIOC_CLOCK_BUS DT_ST_STM32_GPIO_40011000_CLOCK_BUS -#define CONFIG_GPIO_STM32_GPIOD_BASE_ADDRESS DT_ST_STM32_GPIO_40011400_BASE_ADDRESS -#define CONFIG_GPIO_STM32_GPIOD_CLOCK_BITS_0 DT_ST_STM32_GPIO_40011400_CLOCK_BITS_0 -#define CONFIG_GPIO_STM32_GPIOD_CLOCK_BUS_0 DT_ST_STM32_GPIO_40011400_CLOCK_BUS_0 -#define CONFIG_GPIO_STM32_GPIOD_CLOCK_CONTROLLER DT_ST_STM32_GPIO_40011400_CLOCK_CONTROLLER -#define CONFIG_GPIO_STM32_GPIOD_LABEL DT_ST_STM32_GPIO_40011400_LABEL -#define CONFIG_GPIO_STM32_GPIOD_SIZE DT_ST_STM32_GPIO_40011400_SIZE -#define CONFIG_GPIO_STM32_GPIOD_CLOCK_BITS DT_ST_STM32_GPIO_40011400_CLOCK_BITS -#define CONFIG_GPIO_STM32_GPIOD_CLOCK_BUS DT_ST_STM32_GPIO_40011400_CLOCK_BUS +#define DT_GPIO_STM32_GPIOD_BASE_ADDRESS DT_ST_STM32_GPIO_40011400_BASE_ADDRESS +#define DT_GPIO_STM32_GPIOD_CLOCK_BITS_0 DT_ST_STM32_GPIO_40011400_CLOCK_BITS_0 +#define DT_GPIO_STM32_GPIOD_CLOCK_BUS_0 DT_ST_STM32_GPIO_40011400_CLOCK_BUS_0 +#define DT_GPIO_STM32_GPIOD_CLOCK_CONTROLLER DT_ST_STM32_GPIO_40011400_CLOCK_CONTROLLER +#define DT_GPIO_STM32_GPIOD_LABEL DT_ST_STM32_GPIO_40011400_LABEL +#define DT_GPIO_STM32_GPIOD_SIZE DT_ST_STM32_GPIO_40011400_SIZE +#define DT_GPIO_STM32_GPIOD_CLOCK_BITS DT_ST_STM32_GPIO_40011400_CLOCK_BITS +#define DT_GPIO_STM32_GPIOD_CLOCK_BUS DT_ST_STM32_GPIO_40011400_CLOCK_BUS -#define CONFIG_GPIO_STM32_GPIOE_BASE_ADDRESS DT_ST_STM32_GPIO_40011800_BASE_ADDRESS -#define CONFIG_GPIO_STM32_GPIOE_CLOCK_BITS_0 DT_ST_STM32_GPIO_40011800_CLOCK_BITS_0 -#define CONFIG_GPIO_STM32_GPIOE_CLOCK_BUS_0 DT_ST_STM32_GPIO_40011800_CLOCK_BUS_0 -#define CONFIG_GPIO_STM32_GPIOE_CLOCK_CONTROLLER DT_ST_STM32_GPIO_40011800_CLOCK_CONTROLLER -#define CONFIG_GPIO_STM32_GPIOE_LABEL DT_ST_STM32_GPIO_40011800_LABEL -#define CONFIG_GPIO_STM32_GPIOE_SIZE DT_ST_STM32_GPIO_40011800_SIZE -#define CONFIG_GPIO_STM32_GPIOE_CLOCK_BITS DT_ST_STM32_GPIO_40011800_CLOCK_BITS -#define CONFIG_GPIO_STM32_GPIOE_CLOCK_BUS DT_ST_STM32_GPIO_40011800_CLOCK_BUS +#define DT_GPIO_STM32_GPIOE_BASE_ADDRESS DT_ST_STM32_GPIO_40011800_BASE_ADDRESS +#define DT_GPIO_STM32_GPIOE_CLOCK_BITS_0 DT_ST_STM32_GPIO_40011800_CLOCK_BITS_0 +#define DT_GPIO_STM32_GPIOE_CLOCK_BUS_0 DT_ST_STM32_GPIO_40011800_CLOCK_BUS_0 +#define DT_GPIO_STM32_GPIOE_CLOCK_CONTROLLER DT_ST_STM32_GPIO_40011800_CLOCK_CONTROLLER +#define DT_GPIO_STM32_GPIOE_LABEL DT_ST_STM32_GPIO_40011800_LABEL +#define DT_GPIO_STM32_GPIOE_SIZE DT_ST_STM32_GPIO_40011800_SIZE +#define DT_GPIO_STM32_GPIOE_CLOCK_BITS DT_ST_STM32_GPIO_40011800_CLOCK_BITS +#define DT_GPIO_STM32_GPIOE_CLOCK_BUS DT_ST_STM32_GPIO_40011800_CLOCK_BUS -#define CONFIG_GPIO_STM32_GPIOF_BASE_ADDRESS DT_ST_STM32_GPIO_40011C00_BASE_ADDRESS -#define CONFIG_GPIO_STM32_GPIOF_CLOCK_BITS_0 DT_ST_STM32_GPIO_40011C00_CLOCK_BITS_0 -#define CONFIG_GPIO_STM32_GPIOF_CLOCK_BUS_0 DT_ST_STM32_GPIO_40011C00_CLOCK_BUS_0 -#define CONFIG_GPIO_STM32_GPIOF_CLOCK_CONTROLLER DT_ST_STM32_GPIO_40011C00_CLOCK_CONTROLLER -#define CONFIG_GPIO_STM32_GPIOF_LABEL DT_ST_STM32_GPIO_40011C00_LABEL -#define CONFIG_GPIO_STM32_GPIOF_SIZE DT_ST_STM32_GPIO_40011C00_SIZE -#define CONFIG_GPIO_STM32_GPIOF_CLOCK_BITS DT_ST_STM32_GPIO_40011C00_CLOCK_BITS -#define CONFIG_GPIO_STM32_GPIOF_CLOCK_BUS DT_ST_STM32_GPIO_40011C00_CLOCK_BUS +#define DT_GPIO_STM32_GPIOF_BASE_ADDRESS DT_ST_STM32_GPIO_40011C00_BASE_ADDRESS +#define DT_GPIO_STM32_GPIOF_CLOCK_BITS_0 DT_ST_STM32_GPIO_40011C00_CLOCK_BITS_0 +#define DT_GPIO_STM32_GPIOF_CLOCK_BUS_0 DT_ST_STM32_GPIO_40011C00_CLOCK_BUS_0 +#define DT_GPIO_STM32_GPIOF_CLOCK_CONTROLLER DT_ST_STM32_GPIO_40011C00_CLOCK_CONTROLLER +#define DT_GPIO_STM32_GPIOF_LABEL DT_ST_STM32_GPIO_40011C00_LABEL +#define DT_GPIO_STM32_GPIOF_SIZE DT_ST_STM32_GPIO_40011C00_SIZE +#define DT_GPIO_STM32_GPIOF_CLOCK_BITS DT_ST_STM32_GPIO_40011C00_CLOCK_BITS +#define DT_GPIO_STM32_GPIOF_CLOCK_BUS DT_ST_STM32_GPIO_40011C00_CLOCK_BUS -#define CONFIG_GPIO_STM32_GPIOG_BASE_ADDRESS DT_ST_STM32_GPIO_40012000_BASE_ADDRESS -#define CONFIG_GPIO_STM32_GPIOG_CLOCK_BITS_0 DT_ST_STM32_GPIO_40012000_CLOCK_BITS_0 -#define CONFIG_GPIO_STM32_GPIOG_CLOCK_BUS_0 DT_ST_STM32_GPIO_40012000_CLOCK_BUS_0 -#define CONFIG_GPIO_STM32_GPIOG_CLOCK_CONTROLLER DT_ST_STM32_GPIO_40012000_CLOCK_CONTROLLER -#define CONFIG_GPIO_STM32_GPIOG_LABEL DT_ST_STM32_GPIO_40012000_LABEL -#define CONFIG_GPIO_STM32_GPIOG_SIZE DT_ST_STM32_GPIO_40012000_SIZE -#define CONFIG_GPIO_STM32_GPIOG_CLOCK_BITS DT_ST_STM32_GPIO_40012000_CLOCK_BITS -#define CONFIG_GPIO_STM32_GPIOG_CLOCK_BUS DT_ST_STM32_GPIO_40012000_CLOCK_BUS +#define DT_GPIO_STM32_GPIOG_BASE_ADDRESS DT_ST_STM32_GPIO_40012000_BASE_ADDRESS +#define DT_GPIO_STM32_GPIOG_CLOCK_BITS_0 DT_ST_STM32_GPIO_40012000_CLOCK_BITS_0 +#define DT_GPIO_STM32_GPIOG_CLOCK_BUS_0 DT_ST_STM32_GPIO_40012000_CLOCK_BUS_0 +#define DT_GPIO_STM32_GPIOG_CLOCK_CONTROLLER DT_ST_STM32_GPIO_40012000_CLOCK_CONTROLLER +#define DT_GPIO_STM32_GPIOG_LABEL DT_ST_STM32_GPIO_40012000_LABEL +#define DT_GPIO_STM32_GPIOG_SIZE DT_ST_STM32_GPIO_40012000_SIZE +#define DT_GPIO_STM32_GPIOG_CLOCK_BITS DT_ST_STM32_GPIO_40012000_CLOCK_BITS +#define DT_GPIO_STM32_GPIOG_CLOCK_BUS DT_ST_STM32_GPIO_40012000_CLOCK_BUS -#define CONFIG_UART_STM32_USART_1_BASE_ADDRESS DT_ST_STM32_USART_40013800_BASE_ADDRESS -#define CONFIG_UART_STM32_USART_1_BAUD_RATE DT_ST_STM32_USART_40013800_CURRENT_SPEED -#define CONFIG_UART_STM32_USART_1_IRQ_PRI DT_ST_STM32_USART_40013800_IRQ_0_PRIORITY -#define CONFIG_UART_STM32_USART_1_NAME DT_ST_STM32_USART_40013800_LABEL -#define USART_1_IRQ DT_ST_STM32_USART_40013800_IRQ_0 -#define CONFIG_UART_STM32_USART_1_CLOCK_BITS DT_ST_STM32_USART_40013800_CLOCK_BITS -#define CONFIG_UART_STM32_USART_1_CLOCK_BUS DT_ST_STM32_USART_40013800_CLOCK_BUS +#define DT_UART_STM32_USART_1_BASE_ADDRESS DT_ST_STM32_USART_40013800_BASE_ADDRESS +#define DT_UART_STM32_USART_1_BAUD_RATE DT_ST_STM32_USART_40013800_CURRENT_SPEED +#define DT_UART_STM32_USART_1_IRQ_PRI DT_ST_STM32_USART_40013800_IRQ_0_PRIORITY +#define DT_UART_STM32_USART_1_NAME DT_ST_STM32_USART_40013800_LABEL +#define DT_USART_1_IRQ DT_ST_STM32_USART_40013800_IRQ_0 +#define DT_UART_STM32_USART_1_CLOCK_BITS DT_ST_STM32_USART_40013800_CLOCK_BITS +#define DT_UART_STM32_USART_1_CLOCK_BUS DT_ST_STM32_USART_40013800_CLOCK_BUS -#define CONFIG_UART_STM32_USART_2_BASE_ADDRESS DT_ST_STM32_USART_40004400_BASE_ADDRESS -#define CONFIG_UART_STM32_USART_2_BAUD_RATE DT_ST_STM32_USART_40004400_CURRENT_SPEED -#define CONFIG_UART_STM32_USART_2_IRQ_PRI DT_ST_STM32_USART_40004400_IRQ_0_PRIORITY -#define CONFIG_UART_STM32_USART_2_NAME DT_ST_STM32_USART_40004400_LABEL -#define USART_2_IRQ DT_ST_STM32_USART_40004400_IRQ_0 -#define CONFIG_UART_STM32_USART_2_CLOCK_BITS DT_ST_STM32_USART_40004400_CLOCK_BITS -#define CONFIG_UART_STM32_USART_2_CLOCK_BUS DT_ST_STM32_USART_40004400_CLOCK_BUS +#define DT_UART_STM32_USART_2_BASE_ADDRESS DT_ST_STM32_USART_40004400_BASE_ADDRESS +#define DT_UART_STM32_USART_2_BAUD_RATE DT_ST_STM32_USART_40004400_CURRENT_SPEED +#define DT_UART_STM32_USART_2_IRQ_PRI DT_ST_STM32_USART_40004400_IRQ_0_PRIORITY +#define DT_UART_STM32_USART_2_NAME DT_ST_STM32_USART_40004400_LABEL +#define DT_USART_2_IRQ DT_ST_STM32_USART_40004400_IRQ_0 +#define DT_UART_STM32_USART_2_CLOCK_BITS DT_ST_STM32_USART_40004400_CLOCK_BITS +#define DT_UART_STM32_USART_2_CLOCK_BUS DT_ST_STM32_USART_40004400_CLOCK_BUS -#define CONFIG_UART_STM32_USART_3_BASE_ADDRESS DT_ST_STM32_USART_40004800_BASE_ADDRESS -#define CONFIG_UART_STM32_USART_3_BAUD_RATE DT_ST_STM32_USART_40004800_CURRENT_SPEED -#define CONFIG_UART_STM32_USART_3_IRQ_PRI DT_ST_STM32_USART_40004800_IRQ_0_PRIORITY -#define CONFIG_UART_STM32_USART_3_NAME DT_ST_STM32_USART_40004800_LABEL -#define USART_3_IRQ DT_ST_STM32_USART_40004800_IRQ_0 -#define CONFIG_UART_STM32_USART_3_CLOCK_BITS DT_ST_STM32_USART_40004800_CLOCK_BITS -#define CONFIG_UART_STM32_USART_3_CLOCK_BUS DT_ST_STM32_USART_40004800_CLOCK_BUS +#define DT_UART_STM32_USART_3_BASE_ADDRESS DT_ST_STM32_USART_40004800_BASE_ADDRESS +#define DT_UART_STM32_USART_3_BAUD_RATE DT_ST_STM32_USART_40004800_CURRENT_SPEED +#define DT_UART_STM32_USART_3_IRQ_PRI DT_ST_STM32_USART_40004800_IRQ_0_PRIORITY +#define DT_UART_STM32_USART_3_NAME DT_ST_STM32_USART_40004800_LABEL +#define DT_USART_3_IRQ DT_ST_STM32_USART_40004800_IRQ_0 +#define DT_UART_STM32_USART_3_CLOCK_BITS DT_ST_STM32_USART_40004800_CLOCK_BITS +#define DT_UART_STM32_USART_3_CLOCK_BUS DT_ST_STM32_USART_40004800_CLOCK_BUS -#define CONFIG_UART_STM32_UART_4_BASE_ADDRESS DT_ST_STM32_UART_40004C00_BASE_ADDRESS -#define CONFIG_UART_STM32_UART_4_BAUD_RATE DT_ST_STM32_UART_40004C00_CURRENT_SPEED -#define CONFIG_UART_STM32_UART_4_IRQ_PRI DT_ST_STM32_UART_40004C00_IRQ_0_PRIORITY -#define CONFIG_UART_STM32_UART_4_NAME DT_ST_STM32_UART_40004C00_LABEL -#define UART_4_IRQ DT_ST_STM32_UART_40004C00_IRQ_0 -#define CONFIG_UART_STM32_UART_4_CLOCK_BITS DT_ST_STM32_UART_40004C00_CLOCK_BITS -#define CONFIG_UART_STM32_UART_4_CLOCK_BUS DT_ST_STM32_UART_40004C00_CLOCK_BUS +#define DT_UART_STM32_UART_4_BASE_ADDRESS DT_ST_STM32_UART_40004C00_BASE_ADDRESS +#define DT_UART_STM32_UART_4_BAUD_RATE DT_ST_STM32_UART_40004C00_CURRENT_SPEED +#define DT_UART_STM32_UART_4_IRQ_PRI DT_ST_STM32_UART_40004C00_IRQ_0_PRIORITY +#define DT_UART_STM32_UART_4_NAME DT_ST_STM32_UART_40004C00_LABEL +#define DT_UART_4_IRQ DT_ST_STM32_UART_40004C00_IRQ_0 +#define DT_UART_STM32_UART_4_CLOCK_BITS DT_ST_STM32_UART_40004C00_CLOCK_BITS +#define DT_UART_STM32_UART_4_CLOCK_BUS DT_ST_STM32_UART_40004C00_CLOCK_BUS -#define CONFIG_I2C_1_BASE_ADDRESS DT_ST_STM32_I2C_V1_40005400_BASE_ADDRESS -#define CONFIG_I2C_1_EVENT_IRQ_PRI DT_ST_STM32_I2C_V1_40005400_IRQ_EVENT_PRIORITY -#define CONFIG_I2C_1_ERROR_IRQ_PRI DT_ST_STM32_I2C_V1_40005400_IRQ_ERROR_PRIORITY +#define DT_I2C_1_BASE_ADDRESS DT_ST_STM32_I2C_V1_40005400_BASE_ADDRESS +#define DT_I2C_1_EVENT_IRQ_PRI DT_ST_STM32_I2C_V1_40005400_IRQ_EVENT_PRIORITY +#define DT_I2C_1_ERROR_IRQ_PRI DT_ST_STM32_I2C_V1_40005400_IRQ_ERROR_PRIORITY #define CONFIG_I2C_1_NAME DT_ST_STM32_I2C_V1_40005400_LABEL -#define CONFIG_I2C_1_EVENT_IRQ DT_ST_STM32_I2C_V1_40005400_IRQ_EVENT -#define CONFIG_I2C_1_ERROR_IRQ DT_ST_STM32_I2C_V1_40005400_IRQ_ERROR -#define CONFIG_I2C_1_BITRATE DT_ST_STM32_I2C_V1_40005400_CLOCK_FREQUENCY -#define CONFIG_I2C_1_CLOCK_BITS DT_ST_STM32_I2C_V1_40005400_CLOCK_BITS -#define CONFIG_I2C_1_CLOCK_BUS DT_ST_STM32_I2C_V1_40005400_CLOCK_BUS +#define DT_I2C_1_EVENT_IRQ DT_ST_STM32_I2C_V1_40005400_IRQ_EVENT +#define DT_I2C_1_ERROR_IRQ DT_ST_STM32_I2C_V1_40005400_IRQ_ERROR +#define DT_I2C_1_BITRATE DT_ST_STM32_I2C_V1_40005400_CLOCK_FREQUENCY +#define DT_I2C_1_CLOCK_BITS DT_ST_STM32_I2C_V1_40005400_CLOCK_BITS +#define DT_I2C_1_CLOCK_BUS DT_ST_STM32_I2C_V1_40005400_CLOCK_BUS -#define CONFIG_I2C_2_BASE_ADDRESS DT_ST_STM32_I2C_V1_40005800_BASE_ADDRESS -#define CONFIG_I2C_2_EVENT_IRQ_PRI DT_ST_STM32_I2C_V1_40005800_IRQ_EVENT_PRIORITY -#define CONFIG_I2C_2_ERROR_IRQ_PRI DT_ST_STM32_I2C_V1_40005800_IRQ_ERROR_PRIORITY +#define DT_I2C_2_BASE_ADDRESS DT_ST_STM32_I2C_V1_40005800_BASE_ADDRESS +#define DT_I2C_2_EVENT_IRQ_PRI DT_ST_STM32_I2C_V1_40005800_IRQ_EVENT_PRIORITY +#define DT_I2C_2_ERROR_IRQ_PRI DT_ST_STM32_I2C_V1_40005800_IRQ_ERROR_PRIORITY #define CONFIG_I2C_2_NAME DT_ST_STM32_I2C_V1_40005800_LABEL -#define CONFIG_I2C_2_EVENT_IRQ DT_ST_STM32_I2C_V1_40005800_IRQ_EVENT -#define CONFIG_I2C_2_ERROR_IRQ DT_ST_STM32_I2C_V1_40005800_IRQ_ERROR -#define CONFIG_I2C_2_BITRATE DT_ST_STM32_I2C_V1_40005800_CLOCK_FREQUENCY -#define CONFIG_I2C_2_CLOCK_BITS DT_ST_STM32_I2C_V1_40005800_CLOCK_BITS -#define CONFIG_I2C_2_CLOCK_BUS DT_ST_STM32_I2C_V1_40005800_CLOCK_BUS +#define DT_I2C_2_EVENT_IRQ DT_ST_STM32_I2C_V1_40005800_IRQ_EVENT +#define DT_I2C_2_ERROR_IRQ DT_ST_STM32_I2C_V1_40005800_IRQ_ERROR +#define DT_I2C_2_BITRATE DT_ST_STM32_I2C_V1_40005800_CLOCK_FREQUENCY +#define DT_I2C_2_CLOCK_BITS DT_ST_STM32_I2C_V1_40005800_CLOCK_BITS +#define DT_I2C_2_CLOCK_BUS DT_ST_STM32_I2C_V1_40005800_CLOCK_BUS -#define CONFIG_SPI_1_BASE_ADDRESS DT_ST_STM32_SPI_40013000_BASE_ADDRESS +#define DT_SPI_1_BASE_ADDRESS DT_ST_STM32_SPI_40013000_BASE_ADDRESS #define CONFIG_SPI_1_IRQ_PRI DT_ST_STM32_SPI_40013000_IRQ_0_PRIORITY #define CONFIG_SPI_1_NAME DT_ST_STM32_SPI_40013000_LABEL -#define CONFIG_SPI_1_IRQ DT_ST_STM32_SPI_40013000_IRQ_0 +#define DT_SPI_1_IRQ DT_ST_STM32_SPI_40013000_IRQ_0 -#define CONFIG_SPI_2_BASE_ADDRESS DT_ST_STM32_SPI_40003800_BASE_ADDRESS +#define DT_SPI_2_BASE_ADDRESS DT_ST_STM32_SPI_40003800_BASE_ADDRESS #define CONFIG_SPI_2_IRQ_PRI DT_ST_STM32_SPI_40003800_IRQ_0_PRIORITY #define CONFIG_SPI_2_NAME DT_ST_STM32_SPI_40003800_LABEL -#define CONFIG_SPI_2_IRQ DT_ST_STM32_SPI_40003800_IRQ_0 +#define DT_SPI_2_IRQ DT_ST_STM32_SPI_40003800_IRQ_0 -#define CONFIG_SPI_3_BASE_ADDRESS DT_ST_STM32_SPI_40003C00_BASE_ADDRESS +#define DT_SPI_3_BASE_ADDRESS DT_ST_STM32_SPI_40003C00_BASE_ADDRESS #define CONFIG_SPI_3_IRQ_PRI DT_ST_STM32_SPI_40003C00_IRQ_0_PRIORITY #define CONFIG_SPI_3_NAME DT_ST_STM32_SPI_40003C00_LABEL -#define CONFIG_SPI_3_IRQ DT_ST_STM32_SPI_40003C00_IRQ_0 +#define DT_SPI_3_IRQ DT_ST_STM32_SPI_40003C00_IRQ_0 -#define CONFIG_USB_BASE_ADDRESS DT_ST_STM32_USB_40005C00_BASE_ADDRESS -#define CONFIG_USB_IRQ DT_ST_STM32_USB_40005C00_IRQ_USB -#define CONFIG_USB_IRQ_PRI DT_ST_STM32_USB_40005C00_IRQ_USB_PRIORITY -#define CONFIG_USB_NUM_BIDIR_ENDPOINTS DT_ST_STM32_USB_40005C00_NUM_BIDIR_ENDPOINTS -#define CONFIG_USB_RAM_SIZE DT_ST_STM32_USB_40005C00_RAM_SIZE +#define DT_USB_BASE_ADDRESS DT_ST_STM32_USB_40005C00_BASE_ADDRESS +#define DT_USB_IRQ DT_ST_STM32_USB_40005C00_IRQ_USB +#define DT_USB_IRQ_PRI DT_ST_STM32_USB_40005C00_IRQ_USB_PRIORITY +#define DT_USB_NUM_BIDIR_ENDPOINTS DT_ST_STM32_USB_40005C00_NUM_BIDIR_ENDPOINTS +#define DT_USB_RAM_SIZE DT_ST_STM32_USB_40005C00_RAM_SIZE -#define CONFIG_PWM_STM32_1_DEV_NAME DT_ST_STM32_PWM_40012C00_PWM_LABEL -#define CONFIG_PWM_STM32_1_PRESCALER DT_ST_STM32_PWM_40012C00_PWM_ST_PRESCALER +#define DT_PWM_STM32_1_DEV_NAME DT_ST_STM32_PWM_40012C00_PWM_LABEL +#define DT_PWM_STM32_1_PRESCALER DT_ST_STM32_PWM_40012C00_PWM_ST_PRESCALER -#define CONFIG_PWM_STM32_2_DEV_NAME DT_ST_STM32_PWM_40000000_PWM_LABEL -#define CONFIG_PWM_STM32_2_PRESCALER DT_ST_STM32_PWM_40000000_PWM_ST_PRESCALER +#define DT_PWM_STM32_2_DEV_NAME DT_ST_STM32_PWM_40000000_PWM_LABEL +#define DT_PWM_STM32_2_PRESCALER DT_ST_STM32_PWM_40000000_PWM_ST_PRESCALER -#define CONFIG_PWM_STM32_3_DEV_NAME DT_ST_STM32_PWM_40000400_PWM_LABEL -#define CONFIG_PWM_STM32_3_PRESCALER DT_ST_STM32_PWM_40000400_PWM_ST_PRESCALER +#define DT_PWM_STM32_3_DEV_NAME DT_ST_STM32_PWM_40000400_PWM_LABEL +#define DT_PWM_STM32_3_PRESCALER DT_ST_STM32_PWM_40000400_PWM_ST_PRESCALER -#define CONFIG_PWM_STM32_4_DEV_NAME DT_ST_STM32_PWM_40000800_PWM_LABEL -#define CONFIG_PWM_STM32_4_PRESCALER DT_ST_STM32_PWM_40000800_PWM_ST_PRESCALER +#define DT_PWM_STM32_4_DEV_NAME DT_ST_STM32_PWM_40000800_PWM_LABEL +#define DT_PWM_STM32_4_PRESCALER DT_ST_STM32_PWM_40000800_PWM_ST_PRESCALER -#define CONFIG_PWM_STM32_5_DEV_NAME DT_ST_STM32_PWM_40000C00_PWM_LABEL -#define CONFIG_PWM_STM32_5_PRESCALER DT_ST_STM32_PWM_40000C00_PWM_ST_PRESCALER +#define DT_PWM_STM32_5_DEV_NAME DT_ST_STM32_PWM_40000C00_PWM_LABEL +#define DT_PWM_STM32_5_PRESCALER DT_ST_STM32_PWM_40000C00_PWM_ST_PRESCALER -#define CONFIG_PWM_STM32_6_DEV_NAME DT_ST_STM32_PWM_40001000_PWM_LABEL -#define CONFIG_PWM_STM32_6_PRESCALER DT_ST_STM32_PWM_40001000_PWM_ST_PRESCALER +#define DT_PWM_STM32_6_DEV_NAME DT_ST_STM32_PWM_40001000_PWM_LABEL +#define DT_PWM_STM32_6_PRESCALER DT_ST_STM32_PWM_40001000_PWM_ST_PRESCALER -#define CONFIG_PWM_STM32_7_DEV_NAME DT_ST_STM32_PWM_40001400_PWM_LABEL -#define CONFIG_PWM_STM32_7_PRESCALER DT_ST_STM32_PWM_40001400_PWM_ST_PRESCALER +#define DT_PWM_STM32_7_DEV_NAME DT_ST_STM32_PWM_40001400_PWM_LABEL +#define DT_PWM_STM32_7_PRESCALER DT_ST_STM32_PWM_40001400_PWM_ST_PRESCALER -#define CONFIG_PWM_STM32_8_DEV_NAME DT_ST_STM32_PWM_40013400_PWM_LABEL -#define CONFIG_PWM_STM32_8_PRESCALER DT_ST_STM32_PWM_40013400_PWM_ST_PRESCALER +#define DT_PWM_STM32_8_DEV_NAME DT_ST_STM32_PWM_40013400_PWM_LABEL +#define DT_PWM_STM32_8_PRESCALER DT_ST_STM32_PWM_40013400_PWM_ST_PRESCALER /* End of SoC Level DTS fixup file */ diff --git a/soc/arm/st_stm32/stm32f2/dts_fixup.h b/soc/arm/st_stm32/stm32f2/dts_fixup.h index ab8e0bfef3a..a3237b30ce9 100644 --- a/soc/arm/st_stm32/stm32f2/dts_fixup.h +++ b/soc/arm/st_stm32/stm32f2/dts_fixup.h @@ -1,141 +1,141 @@ /* SoC level DTS fixup file */ -#define CONFIG_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS +#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS -#define CONFIG_GPIO_STM32_GPIOA_BASE_ADDRESS DT_ST_STM32_GPIO_40020000_BASE_ADDRESS -#define CONFIG_GPIO_STM32_GPIOA_CLOCK_BITS_0 DT_ST_STM32_GPIO_40020000_CLOCK_BITS_0 -#define CONFIG_GPIO_STM32_GPIOA_CLOCK_BUS_0 DT_ST_STM32_GPIO_40020000_CLOCK_BUS_0 -#define CONFIG_GPIO_STM32_GPIOA_CLOCK_CONTROLLER DT_ST_STM32_GPIO_40020000_CLOCK_CONTROLLER -#define CONFIG_GPIO_STM32_GPIOA_LABEL DT_ST_STM32_GPIO_40020000_LABEL -#define CONFIG_GPIO_STM32_GPIOA_SIZE DT_ST_STM32_GPIO_40020000_SIZE -#define CONFIG_GPIO_STM32_GPIOA_CLOCK_BITS DT_ST_STM32_GPIO_40020000_CLOCK_BITS -#define CONFIG_GPIO_STM32_GPIOA_CLOCK_BUS DT_ST_STM32_GPIO_40020000_CLOCK_BUS +#define DT_GPIO_STM32_GPIOA_BASE_ADDRESS DT_ST_STM32_GPIO_40020000_BASE_ADDRESS +#define DT_GPIO_STM32_GPIOA_CLOCK_BITS_0 DT_ST_STM32_GPIO_40020000_CLOCK_BITS_0 +#define DT_GPIO_STM32_GPIOA_CLOCK_BUS_0 DT_ST_STM32_GPIO_40020000_CLOCK_BUS_0 +#define DT_GPIO_STM32_GPIOA_CLOCK_CONTROLLER DT_ST_STM32_GPIO_40020000_CLOCK_CONTROLLER +#define DT_GPIO_STM32_GPIOA_LABEL DT_ST_STM32_GPIO_40020000_LABEL +#define DT_GPIO_STM32_GPIOA_SIZE DT_ST_STM32_GPIO_40020000_SIZE +#define DT_GPIO_STM32_GPIOA_CLOCK_BITS DT_ST_STM32_GPIO_40020000_CLOCK_BITS +#define DT_GPIO_STM32_GPIOA_CLOCK_BUS DT_ST_STM32_GPIO_40020000_CLOCK_BUS -#define CONFIG_GPIO_STM32_GPIOB_BASE_ADDRESS DT_ST_STM32_GPIO_40020400_BASE_ADDRESS -#define CONFIG_GPIO_STM32_GPIOB_CLOCK_BITS_0 DT_ST_STM32_GPIO_40020400_CLOCK_BITS_0 -#define CONFIG_GPIO_STM32_GPIOB_CLOCK_BUS_0 DT_ST_STM32_GPIO_40020400_CLOCK_BUS_0 -#define CONFIG_GPIO_STM32_GPIOB_CLOCK_CONTROLLER DT_ST_STM32_GPIO_40020400_CLOCK_CONTROLLER -#define CONFIG_GPIO_STM32_GPIOB_LABEL DT_ST_STM32_GPIO_40020400_LABEL -#define CONFIG_GPIO_STM32_GPIOB_SIZE DT_ST_STM32_GPIO_40020400_SIZE -#define CONFIG_GPIO_STM32_GPIOB_CLOCK_BITS DT_ST_STM32_GPIO_40020400_CLOCK_BITS -#define CONFIG_GPIO_STM32_GPIOB_CLOCK_BUS DT_ST_STM32_GPIO_40020400_CLOCK_BUS +#define DT_GPIO_STM32_GPIOB_BASE_ADDRESS DT_ST_STM32_GPIO_40020400_BASE_ADDRESS +#define DT_GPIO_STM32_GPIOB_CLOCK_BITS_0 DT_ST_STM32_GPIO_40020400_CLOCK_BITS_0 +#define DT_GPIO_STM32_GPIOB_CLOCK_BUS_0 DT_ST_STM32_GPIO_40020400_CLOCK_BUS_0 +#define DT_GPIO_STM32_GPIOB_CLOCK_CONTROLLER DT_ST_STM32_GPIO_40020400_CLOCK_CONTROLLER +#define DT_GPIO_STM32_GPIOB_LABEL DT_ST_STM32_GPIO_40020400_LABEL +#define DT_GPIO_STM32_GPIOB_SIZE DT_ST_STM32_GPIO_40020400_SIZE +#define DT_GPIO_STM32_GPIOB_CLOCK_BITS DT_ST_STM32_GPIO_40020400_CLOCK_BITS +#define DT_GPIO_STM32_GPIOB_CLOCK_BUS DT_ST_STM32_GPIO_40020400_CLOCK_BUS -#define CONFIG_GPIO_STM32_GPIOC_BASE_ADDRESS DT_ST_STM32_GPIO_40020800_BASE_ADDRESS -#define CONFIG_GPIO_STM32_GPIOC_CLOCK_BITS_0 DT_ST_STM32_GPIO_40020800_CLOCK_BITS_0 -#define CONFIG_GPIO_STM32_GPIOC_CLOCK_BUS_0 DT_ST_STM32_GPIO_40020800_CLOCK_BUS_0 -#define CONFIG_GPIO_STM32_GPIOC_CLOCK_CONTROLLER DT_ST_STM32_GPIO_40020800_CLOCK_CONTROLLER -#define CONFIG_GPIO_STM32_GPIOC_LABEL DT_ST_STM32_GPIO_40020800_LABEL -#define CONFIG_GPIO_STM32_GPIOC_SIZE DT_ST_STM32_GPIO_40020800_SIZE -#define CONFIG_GPIO_STM32_GPIOC_CLOCK_BITS DT_ST_STM32_GPIO_40020800_CLOCK_BITS -#define CONFIG_GPIO_STM32_GPIOC_CLOCK_BUS DT_ST_STM32_GPIO_40020800_CLOCK_BUS +#define DT_GPIO_STM32_GPIOC_BASE_ADDRESS DT_ST_STM32_GPIO_40020800_BASE_ADDRESS +#define DT_GPIO_STM32_GPIOC_CLOCK_BITS_0 DT_ST_STM32_GPIO_40020800_CLOCK_BITS_0 +#define DT_GPIO_STM32_GPIOC_CLOCK_BUS_0 DT_ST_STM32_GPIO_40020800_CLOCK_BUS_0 +#define DT_GPIO_STM32_GPIOC_CLOCK_CONTROLLER DT_ST_STM32_GPIO_40020800_CLOCK_CONTROLLER +#define DT_GPIO_STM32_GPIOC_LABEL DT_ST_STM32_GPIO_40020800_LABEL +#define DT_GPIO_STM32_GPIOC_SIZE DT_ST_STM32_GPIO_40020800_SIZE +#define DT_GPIO_STM32_GPIOC_CLOCK_BITS DT_ST_STM32_GPIO_40020800_CLOCK_BITS +#define DT_GPIO_STM32_GPIOC_CLOCK_BUS DT_ST_STM32_GPIO_40020800_CLOCK_BUS -#define CONFIG_GPIO_STM32_GPIOD_BASE_ADDRESS DT_ST_STM32_GPIO_40020C00_BASE_ADDRESS -#define CONFIG_GPIO_STM32_GPIOD_CLOCK_BITS_0 DT_ST_STM32_GPIO_40020C00_CLOCK_BITS_0 -#define CONFIG_GPIO_STM32_GPIOD_CLOCK_BUS_0 DT_ST_STM32_GPIO_40020C00_CLOCK_BUS_0 -#define CONFIG_GPIO_STM32_GPIOD_CLOCK_CONTROLLER DT_ST_STM32_GPIO_40020C00_CLOCK_CONTROLLER -#define CONFIG_GPIO_STM32_GPIOD_LABEL DT_ST_STM32_GPIO_40020C00_LABEL -#define CONFIG_GPIO_STM32_GPIOD_SIZE DT_ST_STM32_GPIO_40020C00_SIZE -#define CONFIG_GPIO_STM32_GPIOD_CLOCK_BITS DT_ST_STM32_GPIO_40020C00_CLOCK_BITS -#define CONFIG_GPIO_STM32_GPIOD_CLOCK_BUS DT_ST_STM32_GPIO_40020C00_CLOCK_BUS +#define DT_GPIO_STM32_GPIOD_BASE_ADDRESS DT_ST_STM32_GPIO_40020C00_BASE_ADDRESS +#define DT_GPIO_STM32_GPIOD_CLOCK_BITS_0 DT_ST_STM32_GPIO_40020C00_CLOCK_BITS_0 +#define DT_GPIO_STM32_GPIOD_CLOCK_BUS_0 DT_ST_STM32_GPIO_40020C00_CLOCK_BUS_0 +#define DT_GPIO_STM32_GPIOD_CLOCK_CONTROLLER DT_ST_STM32_GPIO_40020C00_CLOCK_CONTROLLER +#define DT_GPIO_STM32_GPIOD_LABEL DT_ST_STM32_GPIO_40020C00_LABEL +#define DT_GPIO_STM32_GPIOD_SIZE DT_ST_STM32_GPIO_40020C00_SIZE +#define DT_GPIO_STM32_GPIOD_CLOCK_BITS DT_ST_STM32_GPIO_40020C00_CLOCK_BITS +#define DT_GPIO_STM32_GPIOD_CLOCK_BUS DT_ST_STM32_GPIO_40020C00_CLOCK_BUS -#define CONFIG_GPIO_STM32_GPIOE_BASE_ADDRESS DT_ST_STM32_GPIO_40021000_BASE_ADDRESS -#define CONFIG_GPIO_STM32_GPIOE_CLOCK_BITS_0 DT_ST_STM32_GPIO_40021000_CLOCK_BITS_0 -#define CONFIG_GPIO_STM32_GPIOE_CLOCK_BUS_0 DT_ST_STM32_GPIO_40021000_CLOCK_BUS_0 -#define CONFIG_GPIO_STM32_GPIOE_CLOCK_CONTROLLER DT_ST_STM32_GPIO_40021000_CLOCK_CONTROLLER -#define CONFIG_GPIO_STM32_GPIOE_LABEL DT_ST_STM32_GPIO_40021000_LABEL -#define CONFIG_GPIO_STM32_GPIOE_SIZE DT_ST_STM32_GPIO_40021000_SIZE -#define CONFIG_GPIO_STM32_GPIOE_CLOCK_BITS DT_ST_STM32_GPIO_40021000_CLOCK_BITS -#define CONFIG_GPIO_STM32_GPIOE_CLOCK_BUS DT_ST_STM32_GPIO_40021000_CLOCK_BUS +#define DT_GPIO_STM32_GPIOE_BASE_ADDRESS DT_ST_STM32_GPIO_40021000_BASE_ADDRESS +#define DT_GPIO_STM32_GPIOE_CLOCK_BITS_0 DT_ST_STM32_GPIO_40021000_CLOCK_BITS_0 +#define DT_GPIO_STM32_GPIOE_CLOCK_BUS_0 DT_ST_STM32_GPIO_40021000_CLOCK_BUS_0 +#define DT_GPIO_STM32_GPIOE_CLOCK_CONTROLLER DT_ST_STM32_GPIO_40021000_CLOCK_CONTROLLER +#define DT_GPIO_STM32_GPIOE_LABEL DT_ST_STM32_GPIO_40021000_LABEL +#define DT_GPIO_STM32_GPIOE_SIZE DT_ST_STM32_GPIO_40021000_SIZE +#define DT_GPIO_STM32_GPIOE_CLOCK_BITS DT_ST_STM32_GPIO_40021000_CLOCK_BITS +#define DT_GPIO_STM32_GPIOE_CLOCK_BUS DT_ST_STM32_GPIO_40021000_CLOCK_BUS -#define CONFIG_GPIO_STM32_GPIOF_BASE_ADDRESS DT_ST_STM32_GPIO_40021400_BASE_ADDRESS -#define CONFIG_GPIO_STM32_GPIOF_CLOCK_BITS_0 DT_ST_STM32_GPIO_40021400_CLOCK_BITS_0 -#define CONFIG_GPIO_STM32_GPIOF_CLOCK_BUS_0 DT_ST_STM32_GPIO_40021400_CLOCK_BUS_0 -#define CONFIG_GPIO_STM32_GPIOF_CLOCK_CONTROLLER DT_ST_STM32_GPIO_40021400_CLOCK_CONTROLLER -#define CONFIG_GPIO_STM32_GPIOF_LABEL DT_ST_STM32_GPIO_40021400_LABEL -#define CONFIG_GPIO_STM32_GPIOF_SIZE DT_ST_STM32_GPIO_40021400_SIZE -#define CONFIG_GPIO_STM32_GPIOF_CLOCK_BITS DT_ST_STM32_GPIO_40021400_CLOCK_BITS -#define CONFIG_GPIO_STM32_GPIOF_CLOCK_BUS DT_ST_STM32_GPIO_40021400_CLOCK_BUS +#define DT_GPIO_STM32_GPIOF_BASE_ADDRESS DT_ST_STM32_GPIO_40021400_BASE_ADDRESS +#define DT_GPIO_STM32_GPIOF_CLOCK_BITS_0 DT_ST_STM32_GPIO_40021400_CLOCK_BITS_0 +#define DT_GPIO_STM32_GPIOF_CLOCK_BUS_0 DT_ST_STM32_GPIO_40021400_CLOCK_BUS_0 +#define DT_GPIO_STM32_GPIOF_CLOCK_CONTROLLER DT_ST_STM32_GPIO_40021400_CLOCK_CONTROLLER +#define DT_GPIO_STM32_GPIOF_LABEL DT_ST_STM32_GPIO_40021400_LABEL +#define DT_GPIO_STM32_GPIOF_SIZE DT_ST_STM32_GPIO_40021400_SIZE +#define DT_GPIO_STM32_GPIOF_CLOCK_BITS DT_ST_STM32_GPIO_40021400_CLOCK_BITS +#define DT_GPIO_STM32_GPIOF_CLOCK_BUS DT_ST_STM32_GPIO_40021400_CLOCK_BUS -#define CONFIG_GPIO_STM32_GPIOG_BASE_ADDRESS DT_ST_STM32_GPIO_40021800_BASE_ADDRESS -#define CONFIG_GPIO_STM32_GPIOG_CLOCK_BITS_0 DT_ST_STM32_GPIO_40021800_CLOCK_BITS_0 -#define CONFIG_GPIO_STM32_GPIOG_CLOCK_BUS_0 DT_ST_STM32_GPIO_40021800_CLOCK_BUS_0 -#define CONFIG_GPIO_STM32_GPIOG_CLOCK_CONTROLLER DT_ST_STM32_GPIO_40021800_CLOCK_CONTROLLER -#define CONFIG_GPIO_STM32_GPIOG_LABEL DT_ST_STM32_GPIO_40021800_LABEL -#define CONFIG_GPIO_STM32_GPIOG_SIZE DT_ST_STM32_GPIO_40021800_SIZE -#define CONFIG_GPIO_STM32_GPIOG_CLOCK_BITS DT_ST_STM32_GPIO_40021800_CLOCK_BITS -#define CONFIG_GPIO_STM32_GPIOG_CLOCK_BUS DT_ST_STM32_GPIO_40021800_CLOCK_BUS +#define DT_GPIO_STM32_GPIOG_BASE_ADDRESS DT_ST_STM32_GPIO_40021800_BASE_ADDRESS +#define DT_GPIO_STM32_GPIOG_CLOCK_BITS_0 DT_ST_STM32_GPIO_40021800_CLOCK_BITS_0 +#define DT_GPIO_STM32_GPIOG_CLOCK_BUS_0 DT_ST_STM32_GPIO_40021800_CLOCK_BUS_0 +#define DT_GPIO_STM32_GPIOG_CLOCK_CONTROLLER DT_ST_STM32_GPIO_40021800_CLOCK_CONTROLLER +#define DT_GPIO_STM32_GPIOG_LABEL DT_ST_STM32_GPIO_40021800_LABEL +#define DT_GPIO_STM32_GPIOG_SIZE DT_ST_STM32_GPIO_40021800_SIZE +#define DT_GPIO_STM32_GPIOG_CLOCK_BITS DT_ST_STM32_GPIO_40021800_CLOCK_BITS +#define DT_GPIO_STM32_GPIOG_CLOCK_BUS DT_ST_STM32_GPIO_40021800_CLOCK_BUS -#define CONFIG_GPIO_STM32_GPIOH_BASE_ADDRESS DT_ST_STM32_GPIO_40021C00_BASE_ADDRESS -#define CONFIG_GPIO_STM32_GPIOH_CLOCK_BITS_0 DT_ST_STM32_GPIO_40021C00_CLOCK_BITS_0 -#define CONFIG_GPIO_STM32_GPIOH_CLOCK_BUS_0 DT_ST_STM32_GPIO_40021C00_CLOCK_BUS_0 -#define CONFIG_GPIO_STM32_GPIOH_CLOCK_CONTROLLER DT_ST_STM32_GPIO_40021C00_CLOCK_CONTROLLER -#define CONFIG_GPIO_STM32_GPIOH_LABEL DT_ST_STM32_GPIO_40021C00_LABEL -#define CONFIG_GPIO_STM32_GPIOH_SIZE DT_ST_STM32_GPIO_40021C00_SIZE -#define CONFIG_GPIO_STM32_GPIOH_CLOCK_BITS DT_ST_STM32_GPIO_40021C00_CLOCK_BITS -#define CONFIG_GPIO_STM32_GPIOH_CLOCK_BUS DT_ST_STM32_GPIO_40021C00_CLOCK_BUS +#define DT_GPIO_STM32_GPIOH_BASE_ADDRESS DT_ST_STM32_GPIO_40021C00_BASE_ADDRESS +#define DT_GPIO_STM32_GPIOH_CLOCK_BITS_0 DT_ST_STM32_GPIO_40021C00_CLOCK_BITS_0 +#define DT_GPIO_STM32_GPIOH_CLOCK_BUS_0 DT_ST_STM32_GPIO_40021C00_CLOCK_BUS_0 +#define DT_GPIO_STM32_GPIOH_CLOCK_CONTROLLER DT_ST_STM32_GPIO_40021C00_CLOCK_CONTROLLER +#define DT_GPIO_STM32_GPIOH_LABEL DT_ST_STM32_GPIO_40021C00_LABEL +#define DT_GPIO_STM32_GPIOH_SIZE DT_ST_STM32_GPIO_40021C00_SIZE +#define DT_GPIO_STM32_GPIOH_CLOCK_BITS DT_ST_STM32_GPIO_40021C00_CLOCK_BITS +#define DT_GPIO_STM32_GPIOH_CLOCK_BUS DT_ST_STM32_GPIO_40021C00_CLOCK_BUS -#define CONFIG_GPIO_STM32_GPIOI_BASE_ADDRESS DT_ST_STM32_GPIO_40022000_BASE_ADDRESS -#define CONFIG_GPIO_STM32_GPIOI_CLOCK_BITS_0 DT_ST_STM32_GPIO_40022000_CLOCK_BITS_0 -#define CONFIG_GPIO_STM32_GPIOI_CLOCK_BUS_0 DT_ST_STM32_GPIO_40022000_CLOCK_BUS_0 -#define CONFIG_GPIO_STM32_GPIOI_CLOCK_CONTROLLER DT_ST_STM32_GPIO_40022000_CLOCK_CONTROLLER -#define CONFIG_GPIO_STM32_GPIOI_LABEL DT_ST_STM32_GPIO_40022000_LABEL -#define CONFIG_GPIO_STM32_GPIOI_SIZE DT_ST_STM32_GPIO_40022000_SIZE -#define CONFIG_GPIO_STM32_GPIOI_CLOCK_BITS DT_ST_STM32_GPIO_40022000_CLOCK_BITS -#define CONFIG_GPIO_STM32_GPIOI_CLOCK_BUS DT_ST_STM32_GPIO_40022000_CLOCK_BUS +#define DT_GPIO_STM32_GPIOI_BASE_ADDRESS DT_ST_STM32_GPIO_40022000_BASE_ADDRESS +#define DT_GPIO_STM32_GPIOI_CLOCK_BITS_0 DT_ST_STM32_GPIO_40022000_CLOCK_BITS_0 +#define DT_GPIO_STM32_GPIOI_CLOCK_BUS_0 DT_ST_STM32_GPIO_40022000_CLOCK_BUS_0 +#define DT_GPIO_STM32_GPIOI_CLOCK_CONTROLLER DT_ST_STM32_GPIO_40022000_CLOCK_CONTROLLER +#define DT_GPIO_STM32_GPIOI_LABEL DT_ST_STM32_GPIO_40022000_LABEL +#define DT_GPIO_STM32_GPIOI_SIZE DT_ST_STM32_GPIO_40022000_SIZE +#define DT_GPIO_STM32_GPIOI_CLOCK_BITS DT_ST_STM32_GPIO_40022000_CLOCK_BITS +#define DT_GPIO_STM32_GPIOI_CLOCK_BUS DT_ST_STM32_GPIO_40022000_CLOCK_BUS -#define CONFIG_UART_STM32_USART_1_BASE_ADDRESS DT_ST_STM32_USART_40011000_BASE_ADDRESS -#define CONFIG_UART_STM32_USART_1_BAUD_RATE DT_ST_STM32_USART_40011000_CURRENT_SPEED -#define CONFIG_UART_STM32_USART_1_IRQ_PRI DT_ST_STM32_USART_40011000_IRQ_0_PRIORITY -#define CONFIG_UART_STM32_USART_1_NAME DT_ST_STM32_USART_40011000_LABEL -#define USART_1_IRQ DT_ST_STM32_USART_40011000_IRQ_0 -#define CONFIG_UART_STM32_USART_1_CLOCK_BITS DT_ST_STM32_USART_40011000_CLOCK_BITS -#define CONFIG_UART_STM32_USART_1_CLOCK_BUS DT_ST_STM32_USART_40011000_CLOCK_BUS +#define DT_UART_STM32_USART_1_BASE_ADDRESS DT_ST_STM32_USART_40011000_BASE_ADDRESS +#define DT_UART_STM32_USART_1_BAUD_RATE DT_ST_STM32_USART_40011000_CURRENT_SPEED +#define DT_UART_STM32_USART_1_IRQ_PRI DT_ST_STM32_USART_40011000_IRQ_0_PRIORITY +#define DT_UART_STM32_USART_1_NAME DT_ST_STM32_USART_40011000_LABEL +#define DT_USART_1_IRQ DT_ST_STM32_USART_40011000_IRQ_0 +#define DT_UART_STM32_USART_1_CLOCK_BITS DT_ST_STM32_USART_40011000_CLOCK_BITS +#define DT_UART_STM32_USART_1_CLOCK_BUS DT_ST_STM32_USART_40011000_CLOCK_BUS -#define CONFIG_UART_STM32_USART_2_BASE_ADDRESS DT_ST_STM32_USART_40004400_BASE_ADDRESS -#define CONFIG_UART_STM32_USART_2_BAUD_RATE DT_ST_STM32_USART_40004400_CURRENT_SPEED -#define CONFIG_UART_STM32_USART_2_IRQ_PRI DT_ST_STM32_USART_40004400_IRQ_0_PRIORITY -#define CONFIG_UART_STM32_USART_2_NAME DT_ST_STM32_USART_40004400_LABEL -#define USART_2_IRQ DT_ST_STM32_USART_40004400_IRQ_0 -#define CONFIG_UART_STM32_USART_2_CLOCK_BITS DT_ST_STM32_USART_40004400_CLOCK_BITS -#define CONFIG_UART_STM32_USART_2_CLOCK_BUS DT_ST_STM32_USART_40004400_CLOCK_BUS +#define DT_UART_STM32_USART_2_BASE_ADDRESS DT_ST_STM32_USART_40004400_BASE_ADDRESS +#define DT_UART_STM32_USART_2_BAUD_RATE DT_ST_STM32_USART_40004400_CURRENT_SPEED +#define DT_UART_STM32_USART_2_IRQ_PRI DT_ST_STM32_USART_40004400_IRQ_0_PRIORITY +#define DT_UART_STM32_USART_2_NAME DT_ST_STM32_USART_40004400_LABEL +#define DT_USART_2_IRQ DT_ST_STM32_USART_40004400_IRQ_0 +#define DT_UART_STM32_USART_2_CLOCK_BITS DT_ST_STM32_USART_40004400_CLOCK_BITS +#define DT_UART_STM32_USART_2_CLOCK_BUS DT_ST_STM32_USART_40004400_CLOCK_BUS -#define CONFIG_UART_STM32_USART_3_BASE_ADDRESS DT_ST_STM32_USART_40004800_BASE_ADDRESS -#define CONFIG_UART_STM32_USART_3_BAUD_RATE DT_ST_STM32_USART_40004800_CURRENT_SPEED -#define CONFIG_UART_STM32_USART_3_IRQ_PRI DT_ST_STM32_USART_40004800_IRQ_0_PRIORITY -#define CONFIG_UART_STM32_USART_3_NAME DT_ST_STM32_USART_40004800_LABEL -#define USART_3_IRQ DT_ST_STM32_USART_40004800_IRQ_0 -#define CONFIG_UART_STM32_USART_3_CLOCK_BITS DT_ST_STM32_USART_40004800_CLOCK_BITS -#define CONFIG_UART_STM32_USART_3_CLOCK_BUS DT_ST_STM32_USART_40004800_CLOCK_BUS +#define DT_UART_STM32_USART_3_BASE_ADDRESS DT_ST_STM32_USART_40004800_BASE_ADDRESS +#define DT_UART_STM32_USART_3_BAUD_RATE DT_ST_STM32_USART_40004800_CURRENT_SPEED +#define DT_UART_STM32_USART_3_IRQ_PRI DT_ST_STM32_USART_40004800_IRQ_0_PRIORITY +#define DT_UART_STM32_USART_3_NAME DT_ST_STM32_USART_40004800_LABEL +#define DT_USART_3_IRQ DT_ST_STM32_USART_40004800_IRQ_0 +#define DT_UART_STM32_USART_3_CLOCK_BITS DT_ST_STM32_USART_40004800_CLOCK_BITS +#define DT_UART_STM32_USART_3_CLOCK_BUS DT_ST_STM32_USART_40004800_CLOCK_BUS -#define CONFIG_UART_STM32_USART_6_NAME DT_ST_STM32_USART_40011400_LABEL -#define CONFIG_UART_STM32_USART_6_BASE_ADDRESS DT_ST_STM32_USART_40011400_BASE_ADDRESS -#define CONFIG_UART_STM32_USART_6_BAUD_RATE DT_ST_STM32_USART_40011400_CURRENT_SPEED -#define CONFIG_UART_STM32_USART_6_IRQ_PRI DT_ST_STM32_USART_40011400_IRQ_0_PRIORITY -#define USART_6_IRQ DT_ST_STM32_USART_40011400_IRQ_0 -#define CONFIG_UART_STM32_USART_6_CLOCK_BITS DT_ST_STM32_USART_40011400_CLOCK_BITS -#define CONFIG_UART_STM32_USART_6_CLOCK_BUS DT_ST_STM32_USART_40011400_CLOCK_BUS +#define DT_UART_STM32_USART_6_NAME DT_ST_STM32_USART_40011400_LABEL +#define DT_UART_STM32_USART_6_BASE_ADDRESS DT_ST_STM32_USART_40011400_BASE_ADDRESS +#define DT_UART_STM32_USART_6_BAUD_RATE DT_ST_STM32_USART_40011400_CURRENT_SPEED +#define DT_UART_STM32_USART_6_IRQ_PRI DT_ST_STM32_USART_40011400_IRQ_0_PRIORITY +#define DT_USART_6_IRQ DT_ST_STM32_USART_40011400_IRQ_0 +#define DT_UART_STM32_USART_6_CLOCK_BITS DT_ST_STM32_USART_40011400_CLOCK_BITS +#define DT_UART_STM32_USART_6_CLOCK_BUS DT_ST_STM32_USART_40011400_CLOCK_BUS -#define CONFIG_UART_STM32_UART_4_NAME DT_ST_STM32_UART_40004C00_LABEL -#define CONFIG_UART_STM32_UART_4_BASE_ADDRESS DT_ST_STM32_UART_40004C00_BASE_ADDRESS -#define CONFIG_UART_STM32_UART_4_BAUD_RATE DT_ST_STM32_UART_40004C00_CURRENT_SPEED -#define CONFIG_UART_STM32_UART_4_IRQ_PRI DT_ST_STM32_UART_40004C00_IRQ_0_PRIORITY -#define UART_4_IRQ DT_ST_STM32_UART_40004C00_IRQ_0 -#define CONFIG_UART_STM32_UART_4_CLOCK_BITS DT_ST_STM32_UART_40004C00_CLOCK_BITS -#define CONFIG_UART_STM32_UART_4_CLOCK_BUS DT_ST_STM32_UART_40004C00_CLOCK_BUS +#define DT_UART_STM32_UART_4_NAME DT_ST_STM32_UART_40004C00_LABEL +#define DT_UART_STM32_UART_4_BASE_ADDRESS DT_ST_STM32_UART_40004C00_BASE_ADDRESS +#define DT_UART_STM32_UART_4_BAUD_RATE DT_ST_STM32_UART_40004C00_CURRENT_SPEED +#define DT_UART_STM32_UART_4_IRQ_PRI DT_ST_STM32_UART_40004C00_IRQ_0_PRIORITY +#define DT_UART_4_IRQ DT_ST_STM32_UART_40004C00_IRQ_0 +#define DT_UART_STM32_UART_4_CLOCK_BITS DT_ST_STM32_UART_40004C00_CLOCK_BITS +#define DT_UART_STM32_UART_4_CLOCK_BUS DT_ST_STM32_UART_40004C00_CLOCK_BUS -#define CONFIG_UART_STM32_UART_5_NAME DT_ST_STM32_UART_40005000_LABEL -#define CONFIG_UART_STM32_UART_5_BASE_ADDRESS DT_ST_STM32_UART_40005000_BASE_ADDRESS -#define CONFIG_UART_STM32_UART_5_BAUD_RATE DT_ST_STM32_UART_40005000_CURRENT_SPEED -#define CONFIG_UART_STM32_UART_5_IRQ_PRI DT_ST_STM32_UART_40005000_IRQ_0_PRIORITY -#define UART_5_IRQ DT_ST_STM32_UART_40005000_IRQ_0 -#define CONFIG_UART_STM32_UART_5_CLOCK_BITS DT_ST_STM32_UART_40005000_CLOCK_BITS -#define CONFIG_UART_STM32_UART_5_CLOCK_BUS DT_ST_STM32_UART_40005000_CLOCK_BUS +#define DT_UART_STM32_UART_5_NAME DT_ST_STM32_UART_40005000_LABEL +#define DT_UART_STM32_UART_5_BASE_ADDRESS DT_ST_STM32_UART_40005000_BASE_ADDRESS +#define DT_UART_STM32_UART_5_BAUD_RATE DT_ST_STM32_UART_40005000_CURRENT_SPEED +#define DT_UART_STM32_UART_5_IRQ_PRI DT_ST_STM32_UART_40005000_IRQ_0_PRIORITY +#define DT_UART_5_IRQ DT_ST_STM32_UART_40005000_IRQ_0 +#define DT_UART_STM32_UART_5_CLOCK_BITS DT_ST_STM32_UART_40005000_CLOCK_BITS +#define DT_UART_STM32_UART_5_CLOCK_BUS DT_ST_STM32_UART_40005000_CLOCK_BUS -#define CONFIG_USB_BASE_ADDRESS DT_ST_STM32_OTGFS_50000000_BASE_ADDRESS -#define CONFIG_USB_IRQ DT_ST_STM32_OTGFS_50000000_IRQ_OTGFS -#define CONFIG_USB_IRQ_PRI DT_ST_STM32_OTGFS_50000000_IRQ_OTGFS_PRIORITY -#define CONFIG_USB_NUM_BIDIR_ENDPOINTS DT_ST_STM32_OTGFS_50000000_NUM_BIDIR_ENDPOINTS -#define CONFIG_USB_RAM_SIZE DT_ST_STM32_OTGFS_50000000_RAM_SIZE -#define CONFIG_USB_MAXIMUM_SPEED DT_ST_STM32_OTGFS_50000000_MAXIMUM_SPEED +#define DT_USB_BASE_ADDRESS DT_ST_STM32_OTGFS_50000000_BASE_ADDRESS +#define DT_USB_IRQ DT_ST_STM32_OTGFS_50000000_IRQ_OTGFS +#define DT_USB_IRQ_PRI DT_ST_STM32_OTGFS_50000000_IRQ_OTGFS_PRIORITY +#define DT_USB_NUM_BIDIR_ENDPOINTS DT_ST_STM32_OTGFS_50000000_NUM_BIDIR_ENDPOINTS +#define DT_USB_RAM_SIZE DT_ST_STM32_OTGFS_50000000_RAM_SIZE +#define DT_USB_MAXIMUM_SPEED DT_ST_STM32_OTGFS_50000000_MAXIMUM_SPEED /* End of SoC Level DTS fixup file */ diff --git a/soc/arm/st_stm32/stm32f3/dts_fixup.h b/soc/arm/st_stm32/stm32f3/dts_fixup.h index e7e504b1c12..aeafb213c9e 100644 --- a/soc/arm/st_stm32/stm32f3/dts_fixup.h +++ b/soc/arm/st_stm32/stm32f3/dts_fixup.h @@ -1,198 +1,198 @@ /* SoC level DTS fixup file */ -#define CONFIG_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS +#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS -#define CONFIG_GPIO_STM32_GPIOA_BASE_ADDRESS DT_ST_STM32_GPIO_48000000_BASE_ADDRESS -#define CONFIG_GPIO_STM32_GPIOA_CLOCK_BITS_0 DT_ST_STM32_GPIO_48000000_CLOCK_BITS_0 -#define CONFIG_GPIO_STM32_GPIOA_CLOCK_BUS_0 DT_ST_STM32_GPIO_48000000_CLOCK_BUS_0 -#define CONFIG_GPIO_STM32_GPIOA_CLOCK_CONTROLLER DT_ST_STM32_GPIO_48000000_CLOCK_CONTROLLER -#define CONFIG_GPIO_STM32_GPIOA_LABEL DT_ST_STM32_GPIO_48000000_LABEL -#define CONFIG_GPIO_STM32_GPIOA_SIZE DT_ST_STM32_GPIO_48000000_SIZE -#define CONFIG_GPIO_STM32_GPIOA_CLOCK_BITS DT_ST_STM32_GPIO_48000000_CLOCK_BITS -#define CONFIG_GPIO_STM32_GPIOA_CLOCK_BUS DT_ST_STM32_GPIO_48000000_CLOCK_BUS +#define DT_GPIO_STM32_GPIOA_BASE_ADDRESS DT_ST_STM32_GPIO_48000000_BASE_ADDRESS +#define DT_GPIO_STM32_GPIOA_CLOCK_BITS_0 DT_ST_STM32_GPIO_48000000_CLOCK_BITS_0 +#define DT_GPIO_STM32_GPIOA_CLOCK_BUS_0 DT_ST_STM32_GPIO_48000000_CLOCK_BUS_0 +#define DT_GPIO_STM32_GPIOA_CLOCK_CONTROLLER DT_ST_STM32_GPIO_48000000_CLOCK_CONTROLLER +#define DT_GPIO_STM32_GPIOA_LABEL DT_ST_STM32_GPIO_48000000_LABEL +#define DT_GPIO_STM32_GPIOA_SIZE DT_ST_STM32_GPIO_48000000_SIZE +#define DT_GPIO_STM32_GPIOA_CLOCK_BITS DT_ST_STM32_GPIO_48000000_CLOCK_BITS +#define DT_GPIO_STM32_GPIOA_CLOCK_BUS DT_ST_STM32_GPIO_48000000_CLOCK_BUS -#define CONFIG_GPIO_STM32_GPIOB_BASE_ADDRESS DT_ST_STM32_GPIO_48000400_BASE_ADDRESS -#define CONFIG_GPIO_STM32_GPIOB_CLOCK_BITS_0 DT_ST_STM32_GPIO_48000400_CLOCK_BITS_0 -#define CONFIG_GPIO_STM32_GPIOB_CLOCK_BUS_0 DT_ST_STM32_GPIO_48000400_CLOCK_BUS_0 -#define CONFIG_GPIO_STM32_GPIOB_CLOCK_CONTROLLER DT_ST_STM32_GPIO_48000400_CLOCK_CONTROLLER -#define CONFIG_GPIO_STM32_GPIOB_LABEL DT_ST_STM32_GPIO_48000400_LABEL -#define CONFIG_GPIO_STM32_GPIOB_SIZE DT_ST_STM32_GPIO_48000400_SIZE -#define CONFIG_GPIO_STM32_GPIOB_CLOCK_BITS DT_ST_STM32_GPIO_48000400_CLOCK_BITS -#define CONFIG_GPIO_STM32_GPIOB_CLOCK_BUS DT_ST_STM32_GPIO_48000400_CLOCK_BUS +#define DT_GPIO_STM32_GPIOB_BASE_ADDRESS DT_ST_STM32_GPIO_48000400_BASE_ADDRESS +#define DT_GPIO_STM32_GPIOB_CLOCK_BITS_0 DT_ST_STM32_GPIO_48000400_CLOCK_BITS_0 +#define DT_GPIO_STM32_GPIOB_CLOCK_BUS_0 DT_ST_STM32_GPIO_48000400_CLOCK_BUS_0 +#define DT_GPIO_STM32_GPIOB_CLOCK_CONTROLLER DT_ST_STM32_GPIO_48000400_CLOCK_CONTROLLER +#define DT_GPIO_STM32_GPIOB_LABEL DT_ST_STM32_GPIO_48000400_LABEL +#define DT_GPIO_STM32_GPIOB_SIZE DT_ST_STM32_GPIO_48000400_SIZE +#define DT_GPIO_STM32_GPIOB_CLOCK_BITS DT_ST_STM32_GPIO_48000400_CLOCK_BITS +#define DT_GPIO_STM32_GPIOB_CLOCK_BUS DT_ST_STM32_GPIO_48000400_CLOCK_BUS -#define CONFIG_GPIO_STM32_GPIOC_BASE_ADDRESS DT_ST_STM32_GPIO_48000800_BASE_ADDRESS -#define CONFIG_GPIO_STM32_GPIOC_CLOCK_BITS_0 DT_ST_STM32_GPIO_48000800_CLOCK_BITS_0 -#define CONFIG_GPIO_STM32_GPIOC_CLOCK_BUS_0 DT_ST_STM32_GPIO_48000800_CLOCK_BUS_0 -#define CONFIG_GPIO_STM32_GPIOC_CLOCK_CONTROLLER DT_ST_STM32_GPIO_48000800_CLOCK_CONTROLLER -#define CONFIG_GPIO_STM32_GPIOC_LABEL DT_ST_STM32_GPIO_48000800_LABEL -#define CONFIG_GPIO_STM32_GPIOC_SIZE DT_ST_STM32_GPIO_48000800_SIZE -#define CONFIG_GPIO_STM32_GPIOC_CLOCK_BITS DT_ST_STM32_GPIO_48000800_CLOCK_BITS -#define CONFIG_GPIO_STM32_GPIOC_CLOCK_BUS DT_ST_STM32_GPIO_48000800_CLOCK_BUS +#define DT_GPIO_STM32_GPIOC_BASE_ADDRESS DT_ST_STM32_GPIO_48000800_BASE_ADDRESS +#define DT_GPIO_STM32_GPIOC_CLOCK_BITS_0 DT_ST_STM32_GPIO_48000800_CLOCK_BITS_0 +#define DT_GPIO_STM32_GPIOC_CLOCK_BUS_0 DT_ST_STM32_GPIO_48000800_CLOCK_BUS_0 +#define DT_GPIO_STM32_GPIOC_CLOCK_CONTROLLER DT_ST_STM32_GPIO_48000800_CLOCK_CONTROLLER +#define DT_GPIO_STM32_GPIOC_LABEL DT_ST_STM32_GPIO_48000800_LABEL +#define DT_GPIO_STM32_GPIOC_SIZE DT_ST_STM32_GPIO_48000800_SIZE +#define DT_GPIO_STM32_GPIOC_CLOCK_BITS DT_ST_STM32_GPIO_48000800_CLOCK_BITS +#define DT_GPIO_STM32_GPIOC_CLOCK_BUS DT_ST_STM32_GPIO_48000800_CLOCK_BUS -#define CONFIG_GPIO_STM32_GPIOD_BASE_ADDRESS DT_ST_STM32_GPIO_48000C00_BASE_ADDRESS -#define CONFIG_GPIO_STM32_GPIOD_CLOCK_BITS_0 DT_ST_STM32_GPIO_48000C00_CLOCK_BITS_0 -#define CONFIG_GPIO_STM32_GPIOD_CLOCK_BUS_0 DT_ST_STM32_GPIO_48000C00_CLOCK_BUS_0 -#define CONFIG_GPIO_STM32_GPIOD_CLOCK_CONTROLLER DT_ST_STM32_GPIO_48000C00_CLOCK_CONTROLLER -#define CONFIG_GPIO_STM32_GPIOD_LABEL DT_ST_STM32_GPIO_48000C00_LABEL -#define CONFIG_GPIO_STM32_GPIOD_SIZE DT_ST_STM32_GPIO_48000C00_SIZE -#define CONFIG_GPIO_STM32_GPIOD_CLOCK_BITS DT_ST_STM32_GPIO_48000C00_CLOCK_BITS -#define CONFIG_GPIO_STM32_GPIOD_CLOCK_BUS DT_ST_STM32_GPIO_48000C00_CLOCK_BUS +#define DT_GPIO_STM32_GPIOD_BASE_ADDRESS DT_ST_STM32_GPIO_48000C00_BASE_ADDRESS +#define DT_GPIO_STM32_GPIOD_CLOCK_BITS_0 DT_ST_STM32_GPIO_48000C00_CLOCK_BITS_0 +#define DT_GPIO_STM32_GPIOD_CLOCK_BUS_0 DT_ST_STM32_GPIO_48000C00_CLOCK_BUS_0 +#define DT_GPIO_STM32_GPIOD_CLOCK_CONTROLLER DT_ST_STM32_GPIO_48000C00_CLOCK_CONTROLLER +#define DT_GPIO_STM32_GPIOD_LABEL DT_ST_STM32_GPIO_48000C00_LABEL +#define DT_GPIO_STM32_GPIOD_SIZE DT_ST_STM32_GPIO_48000C00_SIZE +#define DT_GPIO_STM32_GPIOD_CLOCK_BITS DT_ST_STM32_GPIO_48000C00_CLOCK_BITS +#define DT_GPIO_STM32_GPIOD_CLOCK_BUS DT_ST_STM32_GPIO_48000C00_CLOCK_BUS -#define CONFIG_GPIO_STM32_GPIOE_BASE_ADDRESS DT_ST_STM32_GPIO_48001000_BASE_ADDRESS -#define CONFIG_GPIO_STM32_GPIOE_CLOCK_BITS_0 DT_ST_STM32_GPIO_48001000_CLOCK_BITS_0 -#define CONFIG_GPIO_STM32_GPIOE_CLOCK_BUS_0 DT_ST_STM32_GPIO_48001000_CLOCK_BUS_0 -#define CONFIG_GPIO_STM32_GPIOE_CLOCK_CONTROLLER DT_ST_STM32_GPIO_48001000_CLOCK_CONTROLLER -#define CONFIG_GPIO_STM32_GPIOE_LABEL DT_ST_STM32_GPIO_48001000_LABEL -#define CONFIG_GPIO_STM32_GPIOE_SIZE DT_ST_STM32_GPIO_48001000_SIZE -#define CONFIG_GPIO_STM32_GPIOE_CLOCK_BITS DT_ST_STM32_GPIO_48001000_CLOCK_BITS -#define CONFIG_GPIO_STM32_GPIOE_CLOCK_BUS DT_ST_STM32_GPIO_48001000_CLOCK_BUS +#define DT_GPIO_STM32_GPIOE_BASE_ADDRESS DT_ST_STM32_GPIO_48001000_BASE_ADDRESS +#define DT_GPIO_STM32_GPIOE_CLOCK_BITS_0 DT_ST_STM32_GPIO_48001000_CLOCK_BITS_0 +#define DT_GPIO_STM32_GPIOE_CLOCK_BUS_0 DT_ST_STM32_GPIO_48001000_CLOCK_BUS_0 +#define DT_GPIO_STM32_GPIOE_CLOCK_CONTROLLER DT_ST_STM32_GPIO_48001000_CLOCK_CONTROLLER +#define DT_GPIO_STM32_GPIOE_LABEL DT_ST_STM32_GPIO_48001000_LABEL +#define DT_GPIO_STM32_GPIOE_SIZE DT_ST_STM32_GPIO_48001000_SIZE +#define DT_GPIO_STM32_GPIOE_CLOCK_BITS DT_ST_STM32_GPIO_48001000_CLOCK_BITS +#define DT_GPIO_STM32_GPIOE_CLOCK_BUS DT_ST_STM32_GPIO_48001000_CLOCK_BUS -#define CONFIG_GPIO_STM32_GPIOF_BASE_ADDRESS DT_ST_STM32_GPIO_48001400_BASE_ADDRESS -#define CONFIG_GPIO_STM32_GPIOF_CLOCK_BITS_0 DT_ST_STM32_GPIO_48001400_CLOCK_BITS_0 -#define CONFIG_GPIO_STM32_GPIOF_CLOCK_BUS_0 DT_ST_STM32_GPIO_48001400_CLOCK_BUS_0 -#define CONFIG_GPIO_STM32_GPIOF_CLOCK_CONTROLLER DT_ST_STM32_GPIO_48001400_CLOCK_CONTROLLER -#define CONFIG_GPIO_STM32_GPIOF_LABEL DT_ST_STM32_GPIO_48001400_LABEL -#define CONFIG_GPIO_STM32_GPIOF_SIZE DT_ST_STM32_GPIO_48001400_SIZE -#define CONFIG_GPIO_STM32_GPIOF_CLOCK_BITS DT_ST_STM32_GPIO_48001400_CLOCK_BITS -#define CONFIG_GPIO_STM32_GPIOF_CLOCK_BUS DT_ST_STM32_GPIO_48001400_CLOCK_BUS +#define DT_GPIO_STM32_GPIOF_BASE_ADDRESS DT_ST_STM32_GPIO_48001400_BASE_ADDRESS +#define DT_GPIO_STM32_GPIOF_CLOCK_BITS_0 DT_ST_STM32_GPIO_48001400_CLOCK_BITS_0 +#define DT_GPIO_STM32_GPIOF_CLOCK_BUS_0 DT_ST_STM32_GPIO_48001400_CLOCK_BUS_0 +#define DT_GPIO_STM32_GPIOF_CLOCK_CONTROLLER DT_ST_STM32_GPIO_48001400_CLOCK_CONTROLLER +#define DT_GPIO_STM32_GPIOF_LABEL DT_ST_STM32_GPIO_48001400_LABEL +#define DT_GPIO_STM32_GPIOF_SIZE DT_ST_STM32_GPIO_48001400_SIZE +#define DT_GPIO_STM32_GPIOF_CLOCK_BITS DT_ST_STM32_GPIO_48001400_CLOCK_BITS +#define DT_GPIO_STM32_GPIOF_CLOCK_BUS DT_ST_STM32_GPIO_48001400_CLOCK_BUS -#define CONFIG_UART_STM32_USART_1_BASE_ADDRESS DT_ST_STM32_USART_40013800_BASE_ADDRESS -#define CONFIG_UART_STM32_USART_1_BAUD_RATE DT_ST_STM32_USART_40013800_CURRENT_SPEED -#define CONFIG_UART_STM32_USART_1_IRQ_PRI DT_ST_STM32_USART_40013800_IRQ_0_PRIORITY -#define CONFIG_UART_STM32_USART_1_NAME DT_ST_STM32_USART_40013800_LABEL -#define USART_1_IRQ DT_ST_STM32_USART_40013800_IRQ_0 -#define CONFIG_UART_STM32_USART_1_CLOCK_BITS DT_ST_STM32_USART_40013800_CLOCK_BITS -#define CONFIG_UART_STM32_USART_1_CLOCK_BUS DT_ST_STM32_USART_40013800_CLOCK_BUS +#define DT_UART_STM32_USART_1_BASE_ADDRESS DT_ST_STM32_USART_40013800_BASE_ADDRESS +#define DT_UART_STM32_USART_1_BAUD_RATE DT_ST_STM32_USART_40013800_CURRENT_SPEED +#define DT_UART_STM32_USART_1_IRQ_PRI DT_ST_STM32_USART_40013800_IRQ_0_PRIORITY +#define DT_UART_STM32_USART_1_NAME DT_ST_STM32_USART_40013800_LABEL +#define DT_USART_1_IRQ DT_ST_STM32_USART_40013800_IRQ_0 +#define DT_UART_STM32_USART_1_CLOCK_BITS DT_ST_STM32_USART_40013800_CLOCK_BITS +#define DT_UART_STM32_USART_1_CLOCK_BUS DT_ST_STM32_USART_40013800_CLOCK_BUS -#define CONFIG_UART_STM32_USART_2_BASE_ADDRESS DT_ST_STM32_USART_40004400_BASE_ADDRESS -#define CONFIG_UART_STM32_USART_2_BAUD_RATE DT_ST_STM32_USART_40004400_CURRENT_SPEED -#define CONFIG_UART_STM32_USART_2_IRQ_PRI DT_ST_STM32_USART_40004400_IRQ_0_PRIORITY -#define CONFIG_UART_STM32_USART_2_NAME DT_ST_STM32_USART_40004400_LABEL -#define USART_2_IRQ DT_ST_STM32_USART_40004400_IRQ_0 -#define CONFIG_UART_STM32_USART_2_CLOCK_BITS DT_ST_STM32_USART_40004400_CLOCK_BITS -#define CONFIG_UART_STM32_USART_2_CLOCK_BUS DT_ST_STM32_USART_40004400_CLOCK_BUS +#define DT_UART_STM32_USART_2_BASE_ADDRESS DT_ST_STM32_USART_40004400_BASE_ADDRESS +#define DT_UART_STM32_USART_2_BAUD_RATE DT_ST_STM32_USART_40004400_CURRENT_SPEED +#define DT_UART_STM32_USART_2_IRQ_PRI DT_ST_STM32_USART_40004400_IRQ_0_PRIORITY +#define DT_UART_STM32_USART_2_NAME DT_ST_STM32_USART_40004400_LABEL +#define DT_USART_2_IRQ DT_ST_STM32_USART_40004400_IRQ_0 +#define DT_UART_STM32_USART_2_CLOCK_BITS DT_ST_STM32_USART_40004400_CLOCK_BITS +#define DT_UART_STM32_USART_2_CLOCK_BUS DT_ST_STM32_USART_40004400_CLOCK_BUS -#define CONFIG_UART_STM32_USART_3_BASE_ADDRESS DT_ST_STM32_USART_40004800_BASE_ADDRESS -#define CONFIG_UART_STM32_USART_3_BAUD_RATE DT_ST_STM32_USART_40004800_CURRENT_SPEED -#define CONFIG_UART_STM32_USART_3_IRQ_PRI DT_ST_STM32_USART_40004800_IRQ_0_PRIORITY -#define CONFIG_UART_STM32_USART_3_NAME DT_ST_STM32_USART_40004800_LABEL -#define USART_3_IRQ DT_ST_STM32_USART_40004800_IRQ_0 -#define CONFIG_UART_STM32_USART_3_CLOCK_BITS DT_ST_STM32_USART_40004800_CLOCK_BITS -#define CONFIG_UART_STM32_USART_3_CLOCK_BUS DT_ST_STM32_USART_40004800_CLOCK_BUS +#define DT_UART_STM32_USART_3_BASE_ADDRESS DT_ST_STM32_USART_40004800_BASE_ADDRESS +#define DT_UART_STM32_USART_3_BAUD_RATE DT_ST_STM32_USART_40004800_CURRENT_SPEED +#define DT_UART_STM32_USART_3_IRQ_PRI DT_ST_STM32_USART_40004800_IRQ_0_PRIORITY +#define DT_UART_STM32_USART_3_NAME DT_ST_STM32_USART_40004800_LABEL +#define DT_USART_3_IRQ DT_ST_STM32_USART_40004800_IRQ_0 +#define DT_UART_STM32_USART_3_CLOCK_BITS DT_ST_STM32_USART_40004800_CLOCK_BITS +#define DT_UART_STM32_USART_3_CLOCK_BUS DT_ST_STM32_USART_40004800_CLOCK_BUS -#define CONFIG_I2C_1_BASE_ADDRESS DT_ST_STM32_I2C_V2_40005400_BASE_ADDRESS -#define CONFIG_I2C_1_EVENT_IRQ_PRI DT_ST_STM32_I2C_V2_40005400_IRQ_EVENT_PRIORITY -#define CONFIG_I2C_1_ERROR_IRQ_PRI DT_ST_STM32_I2C_V2_40005400_IRQ_ERROR_PRIORITY +#define DT_I2C_1_BASE_ADDRESS DT_ST_STM32_I2C_V2_40005400_BASE_ADDRESS +#define DT_I2C_1_EVENT_IRQ_PRI DT_ST_STM32_I2C_V2_40005400_IRQ_EVENT_PRIORITY +#define DT_I2C_1_ERROR_IRQ_PRI DT_ST_STM32_I2C_V2_40005400_IRQ_ERROR_PRIORITY #define CONFIG_I2C_1_NAME DT_ST_STM32_I2C_V2_40005400_LABEL -#define CONFIG_I2C_1_EVENT_IRQ DT_ST_STM32_I2C_V2_40005400_IRQ_EVENT -#define CONFIG_I2C_1_ERROR_IRQ DT_ST_STM32_I2C_V2_40005400_IRQ_ERROR -#define CONFIG_I2C_1_BITRATE DT_ST_STM32_I2C_V2_40005400_CLOCK_FREQUENCY -#define CONFIG_I2C_1_CLOCK_BITS DT_ST_STM32_I2C_V2_40005400_CLOCK_BITS -#define CONFIG_I2C_1_CLOCK_BUS DT_ST_STM32_I2C_V2_40005400_CLOCK_BUS +#define DT_I2C_1_EVENT_IRQ DT_ST_STM32_I2C_V2_40005400_IRQ_EVENT +#define DT_I2C_1_ERROR_IRQ DT_ST_STM32_I2C_V2_40005400_IRQ_ERROR +#define DT_I2C_1_BITRATE DT_ST_STM32_I2C_V2_40005400_CLOCK_FREQUENCY +#define DT_I2C_1_CLOCK_BITS DT_ST_STM32_I2C_V2_40005400_CLOCK_BITS +#define DT_I2C_1_CLOCK_BUS DT_ST_STM32_I2C_V2_40005400_CLOCK_BUS -#define CONFIG_I2C_2_BASE_ADDRESS DT_ST_STM32_I2C_V2_40005800_BASE_ADDRESS -#define CONFIG_I2C_2_EVENT_IRQ_PRI DT_ST_STM32_I2C_V2_40005800_IRQ_EVENT_PRIORITY -#define CONFIG_I2C_2_ERROR_IRQ_PRI DT_ST_STM32_I2C_V2_40005800_IRQ_ERROR_PRIORITY +#define DT_I2C_2_BASE_ADDRESS DT_ST_STM32_I2C_V2_40005800_BASE_ADDRESS +#define DT_I2C_2_EVENT_IRQ_PRI DT_ST_STM32_I2C_V2_40005800_IRQ_EVENT_PRIORITY +#define DT_I2C_2_ERROR_IRQ_PRI DT_ST_STM32_I2C_V2_40005800_IRQ_ERROR_PRIORITY #define CONFIG_I2C_2_NAME DT_ST_STM32_I2C_V2_40005800_LABEL -#define CONFIG_I2C_2_EVENT_IRQ DT_ST_STM32_I2C_V2_40005800_IRQ_EVENT -#define CONFIG_I2C_2_ERROR_IRQ DT_ST_STM32_I2C_V2_40005800_IRQ_ERROR -#define CONFIG_I2C_2_BITRATE DT_ST_STM32_I2C_V2_40005800_CLOCK_FREQUENCY -#define CONFIG_I2C_2_CLOCK_BITS DT_ST_STM32_I2C_V2_40005800_CLOCK_BITS -#define CONFIG_I2C_2_CLOCK_BUS DT_ST_STM32_I2C_V2_40005800_CLOCK_BUS +#define DT_I2C_2_EVENT_IRQ DT_ST_STM32_I2C_V2_40005800_IRQ_EVENT +#define DT_I2C_2_ERROR_IRQ DT_ST_STM32_I2C_V2_40005800_IRQ_ERROR +#define DT_I2C_2_BITRATE DT_ST_STM32_I2C_V2_40005800_CLOCK_FREQUENCY +#define DT_I2C_2_CLOCK_BITS DT_ST_STM32_I2C_V2_40005800_CLOCK_BITS +#define DT_I2C_2_CLOCK_BUS DT_ST_STM32_I2C_V2_40005800_CLOCK_BUS -#define CONFIG_I2C_3_BASE_ADDRESS DT_ST_STM32_I2C_V2_40007800_BASE_ADDRESS -#define CONFIG_I2C_3_EVENT_IRQ_PRI DT_ST_STM32_I2C_V2_40007800_IRQ_EVENT_PRIORITY -#define CONFIG_I2C_3_ERROR_IRQ_PRI DT_ST_STM32_I2C_V2_40007800_IRQ_ERROR_PRIORITY +#define DT_I2C_3_BASE_ADDRESS DT_ST_STM32_I2C_V2_40007800_BASE_ADDRESS +#define DT_I2C_3_EVENT_IRQ_PRI DT_ST_STM32_I2C_V2_40007800_IRQ_EVENT_PRIORITY +#define DT_I2C_3_ERROR_IRQ_PRI DT_ST_STM32_I2C_V2_40007800_IRQ_ERROR_PRIORITY #define CONFIG_I2C_3_NAME DT_ST_STM32_I2C_V2_40007800_LABEL -#define CONFIG_I2C_3_EVENT_IRQ DT_ST_STM32_I2C_V2_40007800_IRQ_EVENT -#define CONFIG_I2C_3_ERROR_IRQ DT_ST_STM32_I2C_V2_40007800_IRQ_ERROR -#define CONFIG_I2C_3_BITRATE DT_ST_STM32_I2C_V2_40007800_CLOCK_FREQUENCY -#define CONFIG_I2C_3_CLOCK_BITS DT_ST_STM32_I2C_V2_40007800_CLOCK_BITS -#define CONFIG_I2C_3_CLOCK_BUS DT_ST_STM32_I2C_V2_40007800_CLOCK_BUS +#define DT_I2C_3_EVENT_IRQ DT_ST_STM32_I2C_V2_40007800_IRQ_EVENT +#define DT_I2C_3_ERROR_IRQ DT_ST_STM32_I2C_V2_40007800_IRQ_ERROR +#define DT_I2C_3_BITRATE DT_ST_STM32_I2C_V2_40007800_CLOCK_FREQUENCY +#define DT_I2C_3_CLOCK_BITS DT_ST_STM32_I2C_V2_40007800_CLOCK_BITS +#define DT_I2C_3_CLOCK_BUS DT_ST_STM32_I2C_V2_40007800_CLOCK_BUS -#define CONFIG_SPI_1_BASE_ADDRESS DT_ST_STM32_SPI_FIFO_40013000_BASE_ADDRESS +#define DT_SPI_1_BASE_ADDRESS DT_ST_STM32_SPI_FIFO_40013000_BASE_ADDRESS #define CONFIG_SPI_1_IRQ_PRI DT_ST_STM32_SPI_FIFO_40013000_IRQ_0_PRIORITY #define CONFIG_SPI_1_NAME DT_ST_STM32_SPI_FIFO_40013000_LABEL -#define CONFIG_SPI_1_IRQ DT_ST_STM32_SPI_FIFO_40013000_IRQ_0 +#define DT_SPI_1_IRQ DT_ST_STM32_SPI_FIFO_40013000_IRQ_0 -#define CONFIG_SPI_2_BASE_ADDRESS DT_ST_STM32_SPI_FIFO_40003800_BASE_ADDRESS +#define DT_SPI_2_BASE_ADDRESS DT_ST_STM32_SPI_FIFO_40003800_BASE_ADDRESS #define CONFIG_SPI_2_IRQ_PRI DT_ST_STM32_SPI_FIFO_40003800_IRQ_0_PRIORITY #define CONFIG_SPI_2_NAME DT_ST_STM32_SPI_FIFO_40003800_LABEL -#define CONFIG_SPI_2_IRQ DT_ST_STM32_SPI_FIFO_40003800_IRQ_0 +#define DT_SPI_2_IRQ DT_ST_STM32_SPI_FIFO_40003800_IRQ_0 -#define CONFIG_SPI_3_BASE_ADDRESS DT_ST_STM32_SPI_FIFO_40003C00_BASE_ADDRESS +#define DT_SPI_3_BASE_ADDRESS DT_ST_STM32_SPI_FIFO_40003C00_BASE_ADDRESS #define CONFIG_SPI_3_IRQ_PRI DT_ST_STM32_SPI_FIFO_40003C00_IRQ_0_PRIORITY #define CONFIG_SPI_3_NAME DT_ST_STM32_SPI_FIFO_40003C00_LABEL -#define CONFIG_SPI_3_IRQ DT_ST_STM32_SPI_FIFO_40003C00_IRQ_0 +#define DT_SPI_3_IRQ DT_ST_STM32_SPI_FIFO_40003C00_IRQ_0 -#define CONFIG_SPI_4_BASE_ADDRESS DT_ST_STM32_SPI_FIFO_40013C00_BASE_ADDRESS -#define CONFIG_SPI_4_IRQ_PRI DT_ST_STM32_SPI_FIFO_40013C00_IRQ_0_PRIORITY +#define DT_SPI_4_BASE_ADDRESS DT_ST_STM32_SPI_FIFO_40013C00_BASE_ADDRESS +#define DT_SPI_4_IRQ_PRI DT_ST_STM32_SPI_FIFO_40013C00_IRQ_0_PRIORITY #define CONFIG_SPI_4_NAME DT_ST_STM32_SPI_FIFO_40013C00_LABEL -#define CONFIG_SPI_4_IRQ DT_ST_STM32_SPI_FIFO_40013C00_IRQ_0 +#define DT_SPI_4_IRQ DT_ST_STM32_SPI_FIFO_40013C00_IRQ_0 -#define FLASH_DEV_BASE_ADDRESS DT_ST_STM32F3_FLASH_CONTROLLER_40022000_BASE_ADDRESS -#define FLASH_DEV_NAME DT_ST_STM32F3_FLASH_CONTROLLER_40022000_LABEL +#define DT_FLASH_DEV_BASE_ADDRESS DT_ST_STM32F3_FLASH_CONTROLLER_40022000_BASE_ADDRESS +#define DT_FLASH_DEV_NAME DT_ST_STM32F3_FLASH_CONTROLLER_40022000_LABEL -#define CONFIG_USB_BASE_ADDRESS DT_ST_STM32_USB_40005C00_BASE_ADDRESS -#define CONFIG_USB_IRQ DT_ST_STM32_USB_40005C00_IRQ_USB -#define CONFIG_USB_IRQ_PRI DT_ST_STM32_USB_40005C00_IRQ_USB_PRIORITY -#define CONFIG_USB_NUM_BIDIR_ENDPOINTS DT_ST_STM32_USB_40005C00_NUM_BIDIR_ENDPOINTS -#define CONFIG_USB_RAM_SIZE DT_ST_STM32_USB_40005C00_RAM_SIZE +#define DT_USB_BASE_ADDRESS DT_ST_STM32_USB_40005C00_BASE_ADDRESS +#define DT_USB_IRQ DT_ST_STM32_USB_40005C00_IRQ_USB +#define DT_USB_IRQ_PRI DT_ST_STM32_USB_40005C00_IRQ_USB_PRIORITY +#define DT_USB_NUM_BIDIR_ENDPOINTS DT_ST_STM32_USB_40005C00_NUM_BIDIR_ENDPOINTS +#define DT_USB_RAM_SIZE DT_ST_STM32_USB_40005C00_RAM_SIZE -#define CONFIG_PWM_STM32_1_DEV_NAME DT_ST_STM32_PWM_40012C00_PWM_LABEL -#define CONFIG_PWM_STM32_1_PRESCALER DT_ST_STM32_PWM_40012C00_PWM_ST_PRESCALER +#define DT_PWM_STM32_1_DEV_NAME DT_ST_STM32_PWM_40012C00_PWM_LABEL +#define DT_PWM_STM32_1_PRESCALER DT_ST_STM32_PWM_40012C00_PWM_ST_PRESCALER -#define CONFIG_PWM_STM32_2_DEV_NAME DT_ST_STM32_PWM_40000000_PWM_LABEL -#define CONFIG_PWM_STM32_2_PRESCALER DT_ST_STM32_PWM_40000000_PWM_ST_PRESCALER +#define DT_PWM_STM32_2_DEV_NAME DT_ST_STM32_PWM_40000000_PWM_LABEL +#define DT_PWM_STM32_2_PRESCALER DT_ST_STM32_PWM_40000000_PWM_ST_PRESCALER -#define CONFIG_PWM_STM32_3_DEV_NAME DT_ST_STM32_PWM_40000400_PWM_LABEL -#define CONFIG_PWM_STM32_3_PRESCALER DT_ST_STM32_PWM_40000400_PWM_ST_PRESCALER +#define DT_PWM_STM32_3_DEV_NAME DT_ST_STM32_PWM_40000400_PWM_LABEL +#define DT_PWM_STM32_3_PRESCALER DT_ST_STM32_PWM_40000400_PWM_ST_PRESCALER -#define CONFIG_PWM_STM32_4_DEV_NAME DT_ST_STM32_PWM_40000800_PWM_LABEL -#define CONFIG_PWM_STM32_4_PRESCALER DT_ST_STM32_PWM_40000800_PWM_ST_PRESCALER +#define DT_PWM_STM32_4_DEV_NAME DT_ST_STM32_PWM_40000800_PWM_LABEL +#define DT_PWM_STM32_4_PRESCALER DT_ST_STM32_PWM_40000800_PWM_ST_PRESCALER -#define CONFIG_PWM_STM32_5_DEV_NAME DT_ST_STM32_PWM_40000C00_PWM_LABEL -#define CONFIG_PWM_STM32_5_PRESCALER DT_ST_STM32_PWM_40000C00_PWM_ST_PRESCALER +#define DT_PWM_STM32_5_DEV_NAME DT_ST_STM32_PWM_40000C00_PWM_LABEL +#define DT_PWM_STM32_5_PRESCALER DT_ST_STM32_PWM_40000C00_PWM_ST_PRESCALER -#define CONFIG_PWM_STM32_6_DEV_NAME DT_ST_STM32_PWM_40001000_PWM_LABEL -#define CONFIG_PWM_STM32_6_PRESCALER DT_ST_STM32_PWM_40001000_PWM_ST_PRESCALER +#define DT_PWM_STM32_6_DEV_NAME DT_ST_STM32_PWM_40001000_PWM_LABEL +#define DT_PWM_STM32_6_PRESCALER DT_ST_STM32_PWM_40001000_PWM_ST_PRESCALER -#define CONFIG_PWM_STM32_7_DEV_NAME DT_ST_STM32_PWM_40001400_PWM_LABEL -#define CONFIG_PWM_STM32_7_PRESCALER DT_ST_STM32_PWM_40001400_PWM_ST_PRESCALER +#define DT_PWM_STM32_7_DEV_NAME DT_ST_STM32_PWM_40001400_PWM_LABEL +#define DT_PWM_STM32_7_PRESCALER DT_ST_STM32_PWM_40001400_PWM_ST_PRESCALER -#define CONFIG_PWM_STM32_8_DEV_NAME DT_ST_STM32_PWM_40013400_PWM_LABEL -#define CONFIG_PWM_STM32_8_PRESCALER DT_ST_STM32_PWM_40013400_PWM_ST_PRESCALER +#define DT_PWM_STM32_8_DEV_NAME DT_ST_STM32_PWM_40013400_PWM_LABEL +#define DT_PWM_STM32_8_PRESCALER DT_ST_STM32_PWM_40013400_PWM_ST_PRESCALER -#define CONFIG_PWM_STM32_12_DEV_NAME DT_ST_STM32_PWM_40001800_PWM_LABEL -#define CONFIG_PWM_STM32_12_PRESCALER DT_ST_STM32_PWM_40001800_PWM_ST_PRESCALER +#define DT_PWM_STM32_12_DEV_NAME DT_ST_STM32_PWM_40001800_PWM_LABEL +#define DT_PWM_STM32_12_PRESCALER DT_ST_STM32_PWM_40001800_PWM_ST_PRESCALER -#define CONFIG_PWM_STM32_13_DEV_NAME DT_ST_STM32_PWM_40001C00_PWM_LABEL -#define CONFIG_PWM_STM32_13_PRESCALER DT_ST_STM32_PWM_40001C00_PWM_ST_PRESCALER +#define DT_PWM_STM32_13_DEV_NAME DT_ST_STM32_PWM_40001C00_PWM_LABEL +#define DT_PWM_STM32_13_PRESCALER DT_ST_STM32_PWM_40001C00_PWM_ST_PRESCALER -#define CONFIG_PWM_STM32_14_DEV_NAME DT_ST_STM32_PWM_40002000_PWM_LABEL -#define CONFIG_PWM_STM32_14_PRESCALER DT_ST_STM32_PWM_40002000_PWM_ST_PRESCALER +#define DT_PWM_STM32_14_DEV_NAME DT_ST_STM32_PWM_40002000_PWM_LABEL +#define DT_PWM_STM32_14_PRESCALER DT_ST_STM32_PWM_40002000_PWM_ST_PRESCALER -#define CONFIG_PWM_STM32_15_DEV_NAME DT_ST_STM32_PWM_40014000_PWM_LABEL -#define CONFIG_PWM_STM32_15_PRESCALER DT_ST_STM32_PWM_40014000_PWM_ST_PRESCALER +#define DT_PWM_STM32_15_DEV_NAME DT_ST_STM32_PWM_40014000_PWM_LABEL +#define DT_PWM_STM32_15_PRESCALER DT_ST_STM32_PWM_40014000_PWM_ST_PRESCALER -#define CONFIG_PWM_STM32_16_DEV_NAME DT_ST_STM32_PWM_40014400_PWM_LABEL -#define CONFIG_PWM_STM32_16_PRESCALER DT_ST_STM32_PWM_40014400_PWM_ST_PRESCALER +#define DT_PWM_STM32_16_DEV_NAME DT_ST_STM32_PWM_40014400_PWM_LABEL +#define DT_PWM_STM32_16_PRESCALER DT_ST_STM32_PWM_40014400_PWM_ST_PRESCALER -#define CONFIG_PWM_STM32_17_DEV_NAME DT_ST_STM32_PWM_40014800_PWM_LABEL -#define CONFIG_PWM_STM32_17_PRESCALER DT_ST_STM32_PWM_40014800_PWM_ST_PRESCALER +#define DT_PWM_STM32_17_DEV_NAME DT_ST_STM32_PWM_40014800_PWM_LABEL +#define DT_PWM_STM32_17_PRESCALER DT_ST_STM32_PWM_40014800_PWM_ST_PRESCALER -#define CONFIG_PWM_STM32_18_DEV_NAME DT_ST_STM32_PWM_40009C00_PWM_LABEL -#define CONFIG_PWM_STM32_18_PRESCALER DT_ST_STM32_PWM_40009C00_PWM_ST_PRESCALER +#define DT_PWM_STM32_18_DEV_NAME DT_ST_STM32_PWM_40009C00_PWM_LABEL +#define DT_PWM_STM32_18_PRESCALER DT_ST_STM32_PWM_40009C00_PWM_ST_PRESCALER -#define CONFIG_PWM_STM32_19_DEV_NAME DT_ST_STM32_PWM_40015C00_PWM_LABEL -#define CONFIG_PWM_STM32_19_PRESCALER DT_ST_STM32_PWM_40015C00_PWM_ST_PRESCALER +#define DT_PWM_STM32_19_DEV_NAME DT_ST_STM32_PWM_40015C00_PWM_LABEL +#define DT_PWM_STM32_19_PRESCALER DT_ST_STM32_PWM_40015C00_PWM_ST_PRESCALER -#define CONFIG_PWM_STM32_20_DEV_NAME DT_ST_STM32_PWM_40015000_PWM_LABEL -#define CONFIG_PWM_STM32_20_PRESCALER DT_ST_STM32_PWM_40015000_PWM_ST_PRESCALER +#define DT_PWM_STM32_20_DEV_NAME DT_ST_STM32_PWM_40015000_PWM_LABEL +#define DT_PWM_STM32_20_PRESCALER DT_ST_STM32_PWM_40015000_PWM_ST_PRESCALER -#define CONFIG_RTC_0_BASE_ADDRESS DT_ST_STM32_RTC_40002800_BASE_ADDRESS +#define DT_RTC_0_BASE_ADDRESS DT_ST_STM32_RTC_40002800_BASE_ADDRESS #define CONFIG_RTC_0_IRQ_PRI DT_ST_STM32_RTC_40002800_IRQ_0_PRIORITY -#define CONFIG_RTC_0_IRQ DT_ST_STM32_RTC_40002800_IRQ_0 +#define DT_RTC_0_IRQ DT_ST_STM32_RTC_40002800_IRQ_0 #define CONFIG_RTC_0_NAME DT_ST_STM32_RTC_40002800_LABEL #define CONFIG_RTC_PRESCALER DT_ST_STM32_RTC_40002800_PRESCALER /* End of SoC Level DTS fixup file */ diff --git a/soc/arm/st_stm32/stm32f4/dts_fixup.h b/soc/arm/st_stm32/stm32f4/dts_fixup.h index ef70d3a318f..8945738f7a2 100644 --- a/soc/arm/st_stm32/stm32f4/dts_fixup.h +++ b/soc/arm/st_stm32/stm32f4/dts_fixup.h @@ -1,306 +1,306 @@ /* SoC level DTS fixup file */ -#define CONFIG_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS +#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS -#define CONFIG_GPIO_STM32_GPIOA_BASE_ADDRESS DT_ST_STM32_GPIO_40020000_BASE_ADDRESS -#define CONFIG_GPIO_STM32_GPIOA_CLOCK_BITS_0 DT_ST_STM32_GPIO_40020000_CLOCK_BITS_0 -#define CONFIG_GPIO_STM32_GPIOA_CLOCK_BUS_0 DT_ST_STM32_GPIO_40020000_CLOCK_BUS_0 -#define CONFIG_GPIO_STM32_GPIOA_CLOCK_CONTROLLER DT_ST_STM32_GPIO_40020000_CLOCK_CONTROLLER -#define CONFIG_GPIO_STM32_GPIOA_LABEL DT_ST_STM32_GPIO_40020000_LABEL -#define CONFIG_GPIO_STM32_GPIOA_SIZE DT_ST_STM32_GPIO_40020000_SIZE -#define CONFIG_GPIO_STM32_GPIOA_CLOCK_BITS DT_ST_STM32_GPIO_40020000_CLOCK_BITS -#define CONFIG_GPIO_STM32_GPIOA_CLOCK_BUS DT_ST_STM32_GPIO_40020000_CLOCK_BUS +#define DT_GPIO_STM32_GPIOA_BASE_ADDRESS DT_ST_STM32_GPIO_40020000_BASE_ADDRESS +#define DT_GPIO_STM32_GPIOA_CLOCK_BITS_0 DT_ST_STM32_GPIO_40020000_CLOCK_BITS_0 +#define DT_GPIO_STM32_GPIOA_CLOCK_BUS_0 DT_ST_STM32_GPIO_40020000_CLOCK_BUS_0 +#define DT_GPIO_STM32_GPIOA_CLOCK_CONTROLLER DT_ST_STM32_GPIO_40020000_CLOCK_CONTROLLER +#define DT_GPIO_STM32_GPIOA_LABEL DT_ST_STM32_GPIO_40020000_LABEL +#define DT_GPIO_STM32_GPIOA_SIZE DT_ST_STM32_GPIO_40020000_SIZE +#define DT_GPIO_STM32_GPIOA_CLOCK_BITS DT_ST_STM32_GPIO_40020000_CLOCK_BITS +#define DT_GPIO_STM32_GPIOA_CLOCK_BUS DT_ST_STM32_GPIO_40020000_CLOCK_BUS -#define CONFIG_GPIO_STM32_GPIOB_BASE_ADDRESS DT_ST_STM32_GPIO_40020400_BASE_ADDRESS -#define CONFIG_GPIO_STM32_GPIOB_CLOCK_BITS_0 DT_ST_STM32_GPIO_40020400_CLOCK_BITS_0 -#define CONFIG_GPIO_STM32_GPIOB_CLOCK_BUS_0 DT_ST_STM32_GPIO_40020400_CLOCK_BUS_0 -#define CONFIG_GPIO_STM32_GPIOB_CLOCK_CONTROLLER DT_ST_STM32_GPIO_40020400_CLOCK_CONTROLLER -#define CONFIG_GPIO_STM32_GPIOB_LABEL DT_ST_STM32_GPIO_40020400_LABEL -#define CONFIG_GPIO_STM32_GPIOB_SIZE DT_ST_STM32_GPIO_40020400_SIZE -#define CONFIG_GPIO_STM32_GPIOB_CLOCK_BITS DT_ST_STM32_GPIO_40020400_CLOCK_BITS -#define CONFIG_GPIO_STM32_GPIOB_CLOCK_BUS DT_ST_STM32_GPIO_40020400_CLOCK_BUS +#define DT_GPIO_STM32_GPIOB_BASE_ADDRESS DT_ST_STM32_GPIO_40020400_BASE_ADDRESS +#define DT_GPIO_STM32_GPIOB_CLOCK_BITS_0 DT_ST_STM32_GPIO_40020400_CLOCK_BITS_0 +#define DT_GPIO_STM32_GPIOB_CLOCK_BUS_0 DT_ST_STM32_GPIO_40020400_CLOCK_BUS_0 +#define DT_GPIO_STM32_GPIOB_CLOCK_CONTROLLER DT_ST_STM32_GPIO_40020400_CLOCK_CONTROLLER +#define DT_GPIO_STM32_GPIOB_LABEL DT_ST_STM32_GPIO_40020400_LABEL +#define DT_GPIO_STM32_GPIOB_SIZE DT_ST_STM32_GPIO_40020400_SIZE +#define DT_GPIO_STM32_GPIOB_CLOCK_BITS DT_ST_STM32_GPIO_40020400_CLOCK_BITS +#define DT_GPIO_STM32_GPIOB_CLOCK_BUS DT_ST_STM32_GPIO_40020400_CLOCK_BUS -#define CONFIG_GPIO_STM32_GPIOC_BASE_ADDRESS DT_ST_STM32_GPIO_40020800_BASE_ADDRESS -#define CONFIG_GPIO_STM32_GPIOC_CLOCK_BITS_0 DT_ST_STM32_GPIO_40020800_CLOCK_BITS_0 -#define CONFIG_GPIO_STM32_GPIOC_CLOCK_BUS_0 DT_ST_STM32_GPIO_40020800_CLOCK_BUS_0 -#define CONFIG_GPIO_STM32_GPIOC_CLOCK_CONTROLLER DT_ST_STM32_GPIO_40020800_CLOCK_CONTROLLER -#define CONFIG_GPIO_STM32_GPIOC_LABEL DT_ST_STM32_GPIO_40020800_LABEL -#define CONFIG_GPIO_STM32_GPIOC_SIZE DT_ST_STM32_GPIO_40020800_SIZE -#define CONFIG_GPIO_STM32_GPIOC_CLOCK_BITS DT_ST_STM32_GPIO_40020800_CLOCK_BITS -#define CONFIG_GPIO_STM32_GPIOC_CLOCK_BUS DT_ST_STM32_GPIO_40020800_CLOCK_BUS +#define DT_GPIO_STM32_GPIOC_BASE_ADDRESS DT_ST_STM32_GPIO_40020800_BASE_ADDRESS +#define DT_GPIO_STM32_GPIOC_CLOCK_BITS_0 DT_ST_STM32_GPIO_40020800_CLOCK_BITS_0 +#define DT_GPIO_STM32_GPIOC_CLOCK_BUS_0 DT_ST_STM32_GPIO_40020800_CLOCK_BUS_0 +#define DT_GPIO_STM32_GPIOC_CLOCK_CONTROLLER DT_ST_STM32_GPIO_40020800_CLOCK_CONTROLLER +#define DT_GPIO_STM32_GPIOC_LABEL DT_ST_STM32_GPIO_40020800_LABEL +#define DT_GPIO_STM32_GPIOC_SIZE DT_ST_STM32_GPIO_40020800_SIZE +#define DT_GPIO_STM32_GPIOC_CLOCK_BITS DT_ST_STM32_GPIO_40020800_CLOCK_BITS +#define DT_GPIO_STM32_GPIOC_CLOCK_BUS DT_ST_STM32_GPIO_40020800_CLOCK_BUS -#define CONFIG_GPIO_STM32_GPIOD_BASE_ADDRESS DT_ST_STM32_GPIO_40020C00_BASE_ADDRESS -#define CONFIG_GPIO_STM32_GPIOD_CLOCK_BITS_0 DT_ST_STM32_GPIO_40020C00_CLOCK_BITS_0 -#define CONFIG_GPIO_STM32_GPIOD_CLOCK_BUS_0 DT_ST_STM32_GPIO_40020C00_CLOCK_BUS_0 -#define CONFIG_GPIO_STM32_GPIOD_CLOCK_CONTROLLER DT_ST_STM32_GPIO_40020C00_CLOCK_CONTROLLER -#define CONFIG_GPIO_STM32_GPIOD_LABEL DT_ST_STM32_GPIO_40020C00_LABEL -#define CONFIG_GPIO_STM32_GPIOD_SIZE DT_ST_STM32_GPIO_40020C00_SIZE -#define CONFIG_GPIO_STM32_GPIOD_CLOCK_BITS DT_ST_STM32_GPIO_40020C00_CLOCK_BITS -#define CONFIG_GPIO_STM32_GPIOD_CLOCK_BUS DT_ST_STM32_GPIO_40020C00_CLOCK_BUS +#define DT_GPIO_STM32_GPIOD_BASE_ADDRESS DT_ST_STM32_GPIO_40020C00_BASE_ADDRESS +#define DT_GPIO_STM32_GPIOD_CLOCK_BITS_0 DT_ST_STM32_GPIO_40020C00_CLOCK_BITS_0 +#define DT_GPIO_STM32_GPIOD_CLOCK_BUS_0 DT_ST_STM32_GPIO_40020C00_CLOCK_BUS_0 +#define DT_GPIO_STM32_GPIOD_CLOCK_CONTROLLER DT_ST_STM32_GPIO_40020C00_CLOCK_CONTROLLER +#define DT_GPIO_STM32_GPIOD_LABEL DT_ST_STM32_GPIO_40020C00_LABEL +#define DT_GPIO_STM32_GPIOD_SIZE DT_ST_STM32_GPIO_40020C00_SIZE +#define DT_GPIO_STM32_GPIOD_CLOCK_BITS DT_ST_STM32_GPIO_40020C00_CLOCK_BITS +#define DT_GPIO_STM32_GPIOD_CLOCK_BUS DT_ST_STM32_GPIO_40020C00_CLOCK_BUS -#define CONFIG_GPIO_STM32_GPIOE_BASE_ADDRESS DT_ST_STM32_GPIO_40021000_BASE_ADDRESS -#define CONFIG_GPIO_STM32_GPIOE_CLOCK_BITS_0 DT_ST_STM32_GPIO_40021000_CLOCK_BITS_0 -#define CONFIG_GPIO_STM32_GPIOE_CLOCK_BUS_0 DT_ST_STM32_GPIO_40021000_CLOCK_BUS_0 -#define CONFIG_GPIO_STM32_GPIOE_CLOCK_CONTROLLER DT_ST_STM32_GPIO_40021000_CLOCK_CONTROLLER -#define CONFIG_GPIO_STM32_GPIOE_LABEL DT_ST_STM32_GPIO_40021000_LABEL -#define CONFIG_GPIO_STM32_GPIOE_SIZE DT_ST_STM32_GPIO_40021000_SIZE -#define CONFIG_GPIO_STM32_GPIOE_CLOCK_BITS DT_ST_STM32_GPIO_40021000_CLOCK_BITS -#define CONFIG_GPIO_STM32_GPIOE_CLOCK_BUS DT_ST_STM32_GPIO_40021000_CLOCK_BUS +#define DT_GPIO_STM32_GPIOE_BASE_ADDRESS DT_ST_STM32_GPIO_40021000_BASE_ADDRESS +#define DT_GPIO_STM32_GPIOE_CLOCK_BITS_0 DT_ST_STM32_GPIO_40021000_CLOCK_BITS_0 +#define DT_GPIO_STM32_GPIOE_CLOCK_BUS_0 DT_ST_STM32_GPIO_40021000_CLOCK_BUS_0 +#define DT_GPIO_STM32_GPIOE_CLOCK_CONTROLLER DT_ST_STM32_GPIO_40021000_CLOCK_CONTROLLER +#define DT_GPIO_STM32_GPIOE_LABEL DT_ST_STM32_GPIO_40021000_LABEL +#define DT_GPIO_STM32_GPIOE_SIZE DT_ST_STM32_GPIO_40021000_SIZE +#define DT_GPIO_STM32_GPIOE_CLOCK_BITS DT_ST_STM32_GPIO_40021000_CLOCK_BITS +#define DT_GPIO_STM32_GPIOE_CLOCK_BUS DT_ST_STM32_GPIO_40021000_CLOCK_BUS -#define CONFIG_GPIO_STM32_GPIOF_BASE_ADDRESS DT_ST_STM32_GPIO_40021400_BASE_ADDRESS -#define CONFIG_GPIO_STM32_GPIOF_CLOCK_BITS_0 DT_ST_STM32_GPIO_40021400_CLOCK_BITS_0 -#define CONFIG_GPIO_STM32_GPIOF_CLOCK_BUS_0 DT_ST_STM32_GPIO_40021400_CLOCK_BUS_0 -#define CONFIG_GPIO_STM32_GPIOF_CLOCK_CONTROLLER DT_ST_STM32_GPIO_40021400_CLOCK_CONTROLLER -#define CONFIG_GPIO_STM32_GPIOF_LABEL DT_ST_STM32_GPIO_40021400_LABEL -#define CONFIG_GPIO_STM32_GPIOF_SIZE DT_ST_STM32_GPIO_40021400_SIZE -#define CONFIG_GPIO_STM32_GPIOF_CLOCK_BITS DT_ST_STM32_GPIO_40021400_CLOCK_BITS -#define CONFIG_GPIO_STM32_GPIOF_CLOCK_BUS DT_ST_STM32_GPIO_40021400_CLOCK_BUS +#define DT_GPIO_STM32_GPIOF_BASE_ADDRESS DT_ST_STM32_GPIO_40021400_BASE_ADDRESS +#define DT_GPIO_STM32_GPIOF_CLOCK_BITS_0 DT_ST_STM32_GPIO_40021400_CLOCK_BITS_0 +#define DT_GPIO_STM32_GPIOF_CLOCK_BUS_0 DT_ST_STM32_GPIO_40021400_CLOCK_BUS_0 +#define DT_GPIO_STM32_GPIOF_CLOCK_CONTROLLER DT_ST_STM32_GPIO_40021400_CLOCK_CONTROLLER +#define DT_GPIO_STM32_GPIOF_LABEL DT_ST_STM32_GPIO_40021400_LABEL +#define DT_GPIO_STM32_GPIOF_SIZE DT_ST_STM32_GPIO_40021400_SIZE +#define DT_GPIO_STM32_GPIOF_CLOCK_BITS DT_ST_STM32_GPIO_40021400_CLOCK_BITS +#define DT_GPIO_STM32_GPIOF_CLOCK_BUS DT_ST_STM32_GPIO_40021400_CLOCK_BUS -#define CONFIG_GPIO_STM32_GPIOG_BASE_ADDRESS DT_ST_STM32_GPIO_40021800_BASE_ADDRESS -#define CONFIG_GPIO_STM32_GPIOG_CLOCK_BITS_0 DT_ST_STM32_GPIO_40021800_CLOCK_BITS_0 -#define CONFIG_GPIO_STM32_GPIOG_CLOCK_BUS_0 DT_ST_STM32_GPIO_40021800_CLOCK_BUS_0 -#define CONFIG_GPIO_STM32_GPIOG_CLOCK_CONTROLLER DT_ST_STM32_GPIO_40021800_CLOCK_CONTROLLER -#define CONFIG_GPIO_STM32_GPIOG_LABEL DT_ST_STM32_GPIO_40021800_LABEL -#define CONFIG_GPIO_STM32_GPIOG_SIZE DT_ST_STM32_GPIO_40021800_SIZE -#define CONFIG_GPIO_STM32_GPIOG_CLOCK_BITS DT_ST_STM32_GPIO_40021800_CLOCK_BITS -#define CONFIG_GPIO_STM32_GPIOG_CLOCK_BUS DT_ST_STM32_GPIO_40021800_CLOCK_BUS +#define DT_GPIO_STM32_GPIOG_BASE_ADDRESS DT_ST_STM32_GPIO_40021800_BASE_ADDRESS +#define DT_GPIO_STM32_GPIOG_CLOCK_BITS_0 DT_ST_STM32_GPIO_40021800_CLOCK_BITS_0 +#define DT_GPIO_STM32_GPIOG_CLOCK_BUS_0 DT_ST_STM32_GPIO_40021800_CLOCK_BUS_0 +#define DT_GPIO_STM32_GPIOG_CLOCK_CONTROLLER DT_ST_STM32_GPIO_40021800_CLOCK_CONTROLLER +#define DT_GPIO_STM32_GPIOG_LABEL DT_ST_STM32_GPIO_40021800_LABEL +#define DT_GPIO_STM32_GPIOG_SIZE DT_ST_STM32_GPIO_40021800_SIZE +#define DT_GPIO_STM32_GPIOG_CLOCK_BITS DT_ST_STM32_GPIO_40021800_CLOCK_BITS +#define DT_GPIO_STM32_GPIOG_CLOCK_BUS DT_ST_STM32_GPIO_40021800_CLOCK_BUS -#define CONFIG_GPIO_STM32_GPIOH_BASE_ADDRESS DT_ST_STM32_GPIO_40021C00_BASE_ADDRESS -#define CONFIG_GPIO_STM32_GPIOH_CLOCK_BITS_0 DT_ST_STM32_GPIO_40021C00_CLOCK_BITS_0 -#define CONFIG_GPIO_STM32_GPIOH_CLOCK_BUS_0 DT_ST_STM32_GPIO_40021C00_CLOCK_BUS_0 -#define CONFIG_GPIO_STM32_GPIOH_CLOCK_CONTROLLER DT_ST_STM32_GPIO_40021C00_CLOCK_CONTROLLER -#define CONFIG_GPIO_STM32_GPIOH_LABEL DT_ST_STM32_GPIO_40021C00_LABEL -#define CONFIG_GPIO_STM32_GPIOH_SIZE DT_ST_STM32_GPIO_40021C00_SIZE -#define CONFIG_GPIO_STM32_GPIOH_CLOCK_BITS DT_ST_STM32_GPIO_40021C00_CLOCK_BITS -#define CONFIG_GPIO_STM32_GPIOH_CLOCK_BUS DT_ST_STM32_GPIO_40021C00_CLOCK_BUS +#define DT_GPIO_STM32_GPIOH_BASE_ADDRESS DT_ST_STM32_GPIO_40021C00_BASE_ADDRESS +#define DT_GPIO_STM32_GPIOH_CLOCK_BITS_0 DT_ST_STM32_GPIO_40021C00_CLOCK_BITS_0 +#define DT_GPIO_STM32_GPIOH_CLOCK_BUS_0 DT_ST_STM32_GPIO_40021C00_CLOCK_BUS_0 +#define DT_GPIO_STM32_GPIOH_CLOCK_CONTROLLER DT_ST_STM32_GPIO_40021C00_CLOCK_CONTROLLER +#define DT_GPIO_STM32_GPIOH_LABEL DT_ST_STM32_GPIO_40021C00_LABEL +#define DT_GPIO_STM32_GPIOH_SIZE DT_ST_STM32_GPIO_40021C00_SIZE +#define DT_GPIO_STM32_GPIOH_CLOCK_BITS DT_ST_STM32_GPIO_40021C00_CLOCK_BITS +#define DT_GPIO_STM32_GPIOH_CLOCK_BUS DT_ST_STM32_GPIO_40021C00_CLOCK_BUS -#define CONFIG_GPIO_STM32_GPIOI_BASE_ADDRESS DT_ST_STM32_GPIO_40022000_BASE_ADDRESS -#define CONFIG_GPIO_STM32_GPIOI_CLOCK_BITS_0 DT_ST_STM32_GPIO_40022000_CLOCK_BITS_0 -#define CONFIG_GPIO_STM32_GPIOI_CLOCK_BUS_0 DT_ST_STM32_GPIO_40022000_CLOCK_BUS_0 -#define CONFIG_GPIO_STM32_GPIOI_CLOCK_CONTROLLER DT_ST_STM32_GPIO_40022000_CLOCK_CONTROLLER -#define CONFIG_GPIO_STM32_GPIOI_LABEL DT_ST_STM32_GPIO_40022000_LABEL -#define CONFIG_GPIO_STM32_GPIOI_SIZE DT_ST_STM32_GPIO_40022000_SIZE -#define CONFIG_GPIO_STM32_GPIOI_CLOCK_BITS DT_ST_STM32_GPIO_40022000_CLOCK_BITS -#define CONFIG_GPIO_STM32_GPIOI_CLOCK_BUS DT_ST_STM32_GPIO_40022000_CLOCK_BUS +#define DT_GPIO_STM32_GPIOI_BASE_ADDRESS DT_ST_STM32_GPIO_40022000_BASE_ADDRESS +#define DT_GPIO_STM32_GPIOI_CLOCK_BITS_0 DT_ST_STM32_GPIO_40022000_CLOCK_BITS_0 +#define DT_GPIO_STM32_GPIOI_CLOCK_BUS_0 DT_ST_STM32_GPIO_40022000_CLOCK_BUS_0 +#define DT_GPIO_STM32_GPIOI_CLOCK_CONTROLLER DT_ST_STM32_GPIO_40022000_CLOCK_CONTROLLER +#define DT_GPIO_STM32_GPIOI_LABEL DT_ST_STM32_GPIO_40022000_LABEL +#define DT_GPIO_STM32_GPIOI_SIZE DT_ST_STM32_GPIO_40022000_SIZE +#define DT_GPIO_STM32_GPIOI_CLOCK_BITS DT_ST_STM32_GPIO_40022000_CLOCK_BITS +#define DT_GPIO_STM32_GPIOI_CLOCK_BUS DT_ST_STM32_GPIO_40022000_CLOCK_BUS -#define CONFIG_GPIO_STM32_GPIOJ_BASE_ADDRESS DT_ST_STM32_GPIO_40022400_BASE_ADDRESS -#define CONFIG_GPIO_STM32_GPIOJ_CLOCK_BITS_0 DT_ST_STM32_GPIO_40022400_CLOCK_BITS_0 -#define CONFIG_GPIO_STM32_GPIOJ_CLOCK_BUS_0 DT_ST_STM32_GPIO_40022400_CLOCK_BUS_0 -#define CONFIG_GPIO_STM32_GPIOJ_CLOCK_CONTROLLER DT_ST_STM32_GPIO_40022400_CLOCK_CONTROLLER -#define CONFIG_GPIO_STM32_GPIOJ_LABEL DT_ST_STM32_GPIO_40022400_LABEL -#define CONFIG_GPIO_STM32_GPIOJ_SIZE DT_ST_STM32_GPIO_40022400_SIZE -#define CONFIG_GPIO_STM32_GPIOJ_CLOCK_BITS DT_ST_STM32_GPIO_40022400_CLOCK_BITS -#define CONFIG_GPIO_STM32_GPIOJ_CLOCK_BUS DT_ST_STM32_GPIO_40022400_CLOCK_BUS +#define DT_GPIO_STM32_GPIOJ_BASE_ADDRESS DT_ST_STM32_GPIO_40022400_BASE_ADDRESS +#define DT_GPIO_STM32_GPIOJ_CLOCK_BITS_0 DT_ST_STM32_GPIO_40022400_CLOCK_BITS_0 +#define DT_GPIO_STM32_GPIOJ_CLOCK_BUS_0 DT_ST_STM32_GPIO_40022400_CLOCK_BUS_0 +#define DT_GPIO_STM32_GPIOJ_CLOCK_CONTROLLER DT_ST_STM32_GPIO_40022400_CLOCK_CONTROLLER +#define DT_GPIO_STM32_GPIOJ_LABEL DT_ST_STM32_GPIO_40022400_LABEL +#define DT_GPIO_STM32_GPIOJ_SIZE DT_ST_STM32_GPIO_40022400_SIZE +#define DT_GPIO_STM32_GPIOJ_CLOCK_BITS DT_ST_STM32_GPIO_40022400_CLOCK_BITS +#define DT_GPIO_STM32_GPIOJ_CLOCK_BUS DT_ST_STM32_GPIO_40022400_CLOCK_BUS -#define CONFIG_GPIO_STM32_GPIOK_BASE_ADDRESS DT_ST_STM32_GPIO_40022800_BASE_ADDRESS -#define CONFIG_GPIO_STM32_GPIOK_CLOCK_BITS_0 DT_ST_STM32_GPIO_40022800_CLOCK_BITS_0 -#define CONFIG_GPIO_STM32_GPIOK_CLOCK_BUS_0 DT_ST_STM32_GPIO_40022800_CLOCK_BUS_0 -#define CONFIG_GPIO_STM32_GPIOK_CLOCK_CONTROLLER DT_ST_STM32_GPIO_40022800_CLOCK_CONTROLLER -#define CONFIG_GPIO_STM32_GPIOK_LABEL DT_ST_STM32_GPIO_40022800_LABEL -#define CONFIG_GPIO_STM32_GPIOK_SIZE DT_ST_STM32_GPIO_40022800_SIZE -#define CONFIG_GPIO_STM32_GPIOK_CLOCK_BITS DT_ST_STM32_GPIO_40022800_CLOCK_BITS -#define CONFIG_GPIO_STM32_GPIOK_CLOCK_BUS DT_ST_STM32_GPIO_40022800_CLOCK_BUS +#define DT_GPIO_STM32_GPIOK_BASE_ADDRESS DT_ST_STM32_GPIO_40022800_BASE_ADDRESS +#define DT_GPIO_STM32_GPIOK_CLOCK_BITS_0 DT_ST_STM32_GPIO_40022800_CLOCK_BITS_0 +#define DT_GPIO_STM32_GPIOK_CLOCK_BUS_0 DT_ST_STM32_GPIO_40022800_CLOCK_BUS_0 +#define DT_GPIO_STM32_GPIOK_CLOCK_CONTROLLER DT_ST_STM32_GPIO_40022800_CLOCK_CONTROLLER +#define DT_GPIO_STM32_GPIOK_LABEL DT_ST_STM32_GPIO_40022800_LABEL +#define DT_GPIO_STM32_GPIOK_SIZE DT_ST_STM32_GPIO_40022800_SIZE +#define DT_GPIO_STM32_GPIOK_CLOCK_BITS DT_ST_STM32_GPIO_40022800_CLOCK_BITS +#define DT_GPIO_STM32_GPIOK_CLOCK_BUS DT_ST_STM32_GPIO_40022800_CLOCK_BUS -#define CONFIG_UART_STM32_USART_1_BASE_ADDRESS DT_ST_STM32_USART_40011000_BASE_ADDRESS -#define CONFIG_UART_STM32_USART_1_BAUD_RATE DT_ST_STM32_USART_40011000_CURRENT_SPEED -#define CONFIG_UART_STM32_USART_1_IRQ_PRI DT_ST_STM32_USART_40011000_IRQ_0_PRIORITY -#define CONFIG_UART_STM32_USART_1_NAME DT_ST_STM32_USART_40011000_LABEL -#define USART_1_IRQ DT_ST_STM32_USART_40011000_IRQ_0 -#define CONFIG_UART_STM32_USART_1_CLOCK_BITS DT_ST_STM32_USART_40011000_CLOCK_BITS -#define CONFIG_UART_STM32_USART_1_CLOCK_BUS DT_ST_STM32_USART_40011000_CLOCK_BUS +#define DT_UART_STM32_USART_1_BASE_ADDRESS DT_ST_STM32_USART_40011000_BASE_ADDRESS +#define DT_UART_STM32_USART_1_BAUD_RATE DT_ST_STM32_USART_40011000_CURRENT_SPEED +#define DT_UART_STM32_USART_1_IRQ_PRI DT_ST_STM32_USART_40011000_IRQ_0_PRIORITY +#define DT_UART_STM32_USART_1_NAME DT_ST_STM32_USART_40011000_LABEL +#define DT_USART_1_IRQ DT_ST_STM32_USART_40011000_IRQ_0 +#define DT_UART_STM32_USART_1_CLOCK_BITS DT_ST_STM32_USART_40011000_CLOCK_BITS +#define DT_UART_STM32_USART_1_CLOCK_BUS DT_ST_STM32_USART_40011000_CLOCK_BUS -#define CONFIG_UART_STM32_USART_2_BASE_ADDRESS DT_ST_STM32_USART_40004400_BASE_ADDRESS -#define CONFIG_UART_STM32_USART_2_BAUD_RATE DT_ST_STM32_USART_40004400_CURRENT_SPEED -#define CONFIG_UART_STM32_USART_2_IRQ_PRI DT_ST_STM32_USART_40004400_IRQ_0_PRIORITY -#define CONFIG_UART_STM32_USART_2_NAME DT_ST_STM32_USART_40004400_LABEL -#define USART_2_IRQ DT_ST_STM32_USART_40004400_IRQ_0 -#define CONFIG_UART_STM32_USART_2_CLOCK_BITS DT_ST_STM32_USART_40004400_CLOCK_BITS -#define CONFIG_UART_STM32_USART_2_CLOCK_BUS DT_ST_STM32_USART_40004400_CLOCK_BUS +#define DT_UART_STM32_USART_2_BASE_ADDRESS DT_ST_STM32_USART_40004400_BASE_ADDRESS +#define DT_UART_STM32_USART_2_BAUD_RATE DT_ST_STM32_USART_40004400_CURRENT_SPEED +#define DT_UART_STM32_USART_2_IRQ_PRI DT_ST_STM32_USART_40004400_IRQ_0_PRIORITY +#define DT_UART_STM32_USART_2_NAME DT_ST_STM32_USART_40004400_LABEL +#define DT_USART_2_IRQ DT_ST_STM32_USART_40004400_IRQ_0 +#define DT_UART_STM32_USART_2_CLOCK_BITS DT_ST_STM32_USART_40004400_CLOCK_BITS +#define DT_UART_STM32_USART_2_CLOCK_BUS DT_ST_STM32_USART_40004400_CLOCK_BUS -#define CONFIG_UART_STM32_USART_3_BASE_ADDRESS DT_ST_STM32_USART_40004800_BASE_ADDRESS -#define CONFIG_UART_STM32_USART_3_BAUD_RATE DT_ST_STM32_USART_40004800_CURRENT_SPEED -#define CONFIG_UART_STM32_USART_3_IRQ_PRI DT_ST_STM32_USART_40004800_IRQ_0_PRIORITY -#define CONFIG_UART_STM32_USART_3_NAME DT_ST_STM32_USART_40004800_LABEL -#define USART_3_IRQ DT_ST_STM32_USART_40004800_IRQ_0 -#define CONFIG_UART_STM32_USART_3_CLOCK_BITS DT_ST_STM32_USART_40004800_CLOCK_BITS -#define CONFIG_UART_STM32_USART_3_CLOCK_BUS DT_ST_STM32_USART_40004800_CLOCK_BUS +#define DT_UART_STM32_USART_3_BASE_ADDRESS DT_ST_STM32_USART_40004800_BASE_ADDRESS +#define DT_UART_STM32_USART_3_BAUD_RATE DT_ST_STM32_USART_40004800_CURRENT_SPEED +#define DT_UART_STM32_USART_3_IRQ_PRI DT_ST_STM32_USART_40004800_IRQ_0_PRIORITY +#define DT_UART_STM32_USART_3_NAME DT_ST_STM32_USART_40004800_LABEL +#define DT_USART_3_IRQ DT_ST_STM32_USART_40004800_IRQ_0 +#define DT_UART_STM32_USART_3_CLOCK_BITS DT_ST_STM32_USART_40004800_CLOCK_BITS +#define DT_UART_STM32_USART_3_CLOCK_BUS DT_ST_STM32_USART_40004800_CLOCK_BUS -#define CONFIG_UART_STM32_USART_6_NAME DT_ST_STM32_USART_40011400_LABEL -#define CONFIG_UART_STM32_USART_6_BASE_ADDRESS DT_ST_STM32_USART_40011400_BASE_ADDRESS -#define CONFIG_UART_STM32_USART_6_BAUD_RATE DT_ST_STM32_USART_40011400_CURRENT_SPEED -#define CONFIG_UART_STM32_USART_6_IRQ_PRI DT_ST_STM32_USART_40011400_IRQ_0_PRIORITY -#define USART_6_IRQ DT_ST_STM32_USART_40011400_IRQ_0 -#define CONFIG_UART_STM32_USART_6_CLOCK_BITS DT_ST_STM32_USART_40011400_CLOCK_BITS -#define CONFIG_UART_STM32_USART_6_CLOCK_BUS DT_ST_STM32_USART_40011400_CLOCK_BUS +#define DT_UART_STM32_USART_6_NAME DT_ST_STM32_USART_40011400_LABEL +#define DT_UART_STM32_USART_6_BASE_ADDRESS DT_ST_STM32_USART_40011400_BASE_ADDRESS +#define DT_UART_STM32_USART_6_BAUD_RATE DT_ST_STM32_USART_40011400_CURRENT_SPEED +#define DT_UART_STM32_USART_6_IRQ_PRI DT_ST_STM32_USART_40011400_IRQ_0_PRIORITY +#define DT_USART_6_IRQ DT_ST_STM32_USART_40011400_IRQ_0 +#define DT_UART_STM32_USART_6_CLOCK_BITS DT_ST_STM32_USART_40011400_CLOCK_BITS +#define DT_UART_STM32_USART_6_CLOCK_BUS DT_ST_STM32_USART_40011400_CLOCK_BUS -#define CONFIG_I2C_1_BASE_ADDRESS DT_ST_STM32_I2C_V1_40005400_BASE_ADDRESS -#define CONFIG_I2C_1_EVENT_IRQ_PRI DT_ST_STM32_I2C_V1_40005400_IRQ_EVENT_PRIORITY -#define CONFIG_I2C_1_ERROR_IRQ_PRI DT_ST_STM32_I2C_V1_40005400_IRQ_ERROR_PRIORITY +#define DT_I2C_1_BASE_ADDRESS DT_ST_STM32_I2C_V1_40005400_BASE_ADDRESS +#define DT_I2C_1_EVENT_IRQ_PRI DT_ST_STM32_I2C_V1_40005400_IRQ_EVENT_PRIORITY +#define DT_I2C_1_ERROR_IRQ_PRI DT_ST_STM32_I2C_V1_40005400_IRQ_ERROR_PRIORITY #define CONFIG_I2C_1_NAME DT_ST_STM32_I2C_V1_40005400_LABEL -#define CONFIG_I2C_1_EVENT_IRQ DT_ST_STM32_I2C_V1_40005400_IRQ_EVENT -#define CONFIG_I2C_1_ERROR_IRQ DT_ST_STM32_I2C_V1_40005400_IRQ_ERROR -#define CONFIG_I2C_1_BITRATE DT_ST_STM32_I2C_V1_40005400_CLOCK_FREQUENCY -#define CONFIG_I2C_1_CLOCK_BITS DT_ST_STM32_I2C_V1_40005400_CLOCK_BITS -#define CONFIG_I2C_1_CLOCK_BUS DT_ST_STM32_I2C_V1_40005400_CLOCK_BUS +#define DT_I2C_1_EVENT_IRQ DT_ST_STM32_I2C_V1_40005400_IRQ_EVENT +#define DT_I2C_1_ERROR_IRQ DT_ST_STM32_I2C_V1_40005400_IRQ_ERROR +#define DT_I2C_1_BITRATE DT_ST_STM32_I2C_V1_40005400_CLOCK_FREQUENCY +#define DT_I2C_1_CLOCK_BITS DT_ST_STM32_I2C_V1_40005400_CLOCK_BITS +#define DT_I2C_1_CLOCK_BUS DT_ST_STM32_I2C_V1_40005400_CLOCK_BUS -#define CONFIG_I2C_2_BASE_ADDRESS DT_ST_STM32_I2C_V1_40005800_BASE_ADDRESS -#define CONFIG_I2C_2_EVENT_IRQ_PRI DT_ST_STM32_I2C_V1_40005800_IRQ_EVENT_PRIORITY -#define CONFIG_I2C_2_ERROR_IRQ_PRI DT_ST_STM32_I2C_V1_40005800_IRQ_ERROR_PRIORITY +#define DT_I2C_2_BASE_ADDRESS DT_ST_STM32_I2C_V1_40005800_BASE_ADDRESS +#define DT_I2C_2_EVENT_IRQ_PRI DT_ST_STM32_I2C_V1_40005800_IRQ_EVENT_PRIORITY +#define DT_I2C_2_ERROR_IRQ_PRI DT_ST_STM32_I2C_V1_40005800_IRQ_ERROR_PRIORITY #define CONFIG_I2C_2_NAME DT_ST_STM32_I2C_V1_40005800_LABEL -#define CONFIG_I2C_2_EVENT_IRQ DT_ST_STM32_I2C_V1_40005800_IRQ_EVENT -#define CONFIG_I2C_2_ERROR_IRQ DT_ST_STM32_I2C_V1_40005800_IRQ_ERROR -#define CONFIG_I2C_2_BITRATE DT_ST_STM32_I2C_V1_40005800_CLOCK_FREQUENCY -#define CONFIG_I2C_2_CLOCK_BITS DT_ST_STM32_I2C_V1_40005800_CLOCK_BITS -#define CONFIG_I2C_2_CLOCK_BUS DT_ST_STM32_I2C_V1_40005800_CLOCK_BUS +#define DT_I2C_2_EVENT_IRQ DT_ST_STM32_I2C_V1_40005800_IRQ_EVENT +#define DT_I2C_2_ERROR_IRQ DT_ST_STM32_I2C_V1_40005800_IRQ_ERROR +#define DT_I2C_2_BITRATE DT_ST_STM32_I2C_V1_40005800_CLOCK_FREQUENCY +#define DT_I2C_2_CLOCK_BITS DT_ST_STM32_I2C_V1_40005800_CLOCK_BITS +#define DT_I2C_2_CLOCK_BUS DT_ST_STM32_I2C_V1_40005800_CLOCK_BUS -#define CONFIG_I2C_3_BASE_ADDRESS DT_ST_STM32_I2C_V1_40005C00_BASE_ADDRESS -#define CONFIG_I2C_3_EVENT_IRQ_PRI DT_ST_STM32_I2C_V1_40005C00_IRQ_EVENT_PRIORITY -#define CONFIG_I2C_3_ERROR_IRQ_PRI DT_ST_STM32_I2C_V1_40005C00_IRQ_ERROR_PRIORITY +#define DT_I2C_3_BASE_ADDRESS DT_ST_STM32_I2C_V1_40005C00_BASE_ADDRESS +#define DT_I2C_3_EVENT_IRQ_PRI DT_ST_STM32_I2C_V1_40005C00_IRQ_EVENT_PRIORITY +#define DT_I2C_3_ERROR_IRQ_PRI DT_ST_STM32_I2C_V1_40005C00_IRQ_ERROR_PRIORITY #define CONFIG_I2C_3_NAME DT_ST_STM32_I2C_V1_40005C00_LABEL -#define CONFIG_I2C_3_EVENT_IRQ DT_ST_STM32_I2C_V1_40005C00_IRQ_EVENT -#define CONFIG_I2C_3_ERROR_IRQ DT_ST_STM32_I2C_V1_40005C00_IRQ_ERROR -#define CONFIG_I2C_3_BITRATE DT_ST_STM32_I2C_V1_40005C00_CLOCK_FREQUENCY -#define CONFIG_I2C_3_CLOCK_BITS DT_ST_STM32_I2C_V1_40005C00_CLOCK_BITS -#define CONFIG_I2C_3_CLOCK_BUS DT_ST_STM32_I2C_V1_40005C00_CLOCK_BUS +#define DT_I2C_3_EVENT_IRQ DT_ST_STM32_I2C_V1_40005C00_IRQ_EVENT +#define DT_I2C_3_ERROR_IRQ DT_ST_STM32_I2C_V1_40005C00_IRQ_ERROR +#define DT_I2C_3_BITRATE DT_ST_STM32_I2C_V1_40005C00_CLOCK_FREQUENCY +#define DT_I2C_3_CLOCK_BITS DT_ST_STM32_I2C_V1_40005C00_CLOCK_BITS +#define DT_I2C_3_CLOCK_BUS DT_ST_STM32_I2C_V1_40005C00_CLOCK_BUS -#define CONFIG_SPI_1_BASE_ADDRESS DT_ST_STM32_SPI_40013000_BASE_ADDRESS +#define DT_SPI_1_BASE_ADDRESS DT_ST_STM32_SPI_40013000_BASE_ADDRESS #define CONFIG_SPI_1_IRQ_PRI DT_ST_STM32_SPI_40013000_IRQ_0_PRIORITY #define CONFIG_SPI_1_NAME DT_ST_STM32_SPI_40013000_LABEL -#define CONFIG_SPI_1_IRQ DT_ST_STM32_SPI_40013000_IRQ_0 +#define DT_SPI_1_IRQ DT_ST_STM32_SPI_40013000_IRQ_0 -#define CONFIG_SPI_2_BASE_ADDRESS DT_ST_STM32_SPI_40003800_BASE_ADDRESS +#define DT_SPI_2_BASE_ADDRESS DT_ST_STM32_SPI_40003800_BASE_ADDRESS #define CONFIG_SPI_2_IRQ_PRI DT_ST_STM32_SPI_40003800_IRQ_0_PRIORITY #define CONFIG_SPI_2_NAME DT_ST_STM32_SPI_40003800_LABEL -#define CONFIG_SPI_2_IRQ DT_ST_STM32_SPI_40003800_IRQ_0 +#define DT_SPI_2_IRQ DT_ST_STM32_SPI_40003800_IRQ_0 -#define CONFIG_SPI_3_BASE_ADDRESS DT_ST_STM32_SPI_40003C00_BASE_ADDRESS +#define DT_SPI_3_BASE_ADDRESS DT_ST_STM32_SPI_40003C00_BASE_ADDRESS #define CONFIG_SPI_3_IRQ_PRI DT_ST_STM32_SPI_40003C00_IRQ_0_PRIORITY #define CONFIG_SPI_3_NAME DT_ST_STM32_SPI_40003C00_LABEL -#define CONFIG_SPI_3_IRQ DT_ST_STM32_SPI_40003C00_IRQ_0 +#define DT_SPI_3_IRQ DT_ST_STM32_SPI_40003C00_IRQ_0 -#define CONFIG_SPI_4_BASE_ADDRESS DT_ST_STM32_SPI_40013400_BASE_ADDRESS -#define CONFIG_SPI_4_IRQ_PRI DT_ST_STM32_SPI_40013400_IRQ_0_PRIORITY +#define DT_SPI_4_BASE_ADDRESS DT_ST_STM32_SPI_40013400_BASE_ADDRESS +#define DT_SPI_4_IRQ_PRI DT_ST_STM32_SPI_40013400_IRQ_0_PRIORITY #define CONFIG_SPI_4_NAME DT_ST_STM32_SPI_40013400_LABEL -#define CONFIG_SPI_4_IRQ DT_ST_STM32_SPI_40013400_IRQ_0 +#define DT_SPI_4_IRQ DT_ST_STM32_SPI_40013400_IRQ_0 -#define CONFIG_SPI_5_BASE_ADDRESS DT_ST_STM32_SPI_40015000_BASE_ADDRESS -#define CONFIG_SPI_5_IRQ_PRI DT_ST_STM32_SPI_40015000_IRQ_0_PRIORITY +#define DT_SPI_5_BASE_ADDRESS DT_ST_STM32_SPI_40015000_BASE_ADDRESS +#define DT_SPI_5_IRQ_PRI DT_ST_STM32_SPI_40015000_IRQ_0_PRIORITY #define CONFIG_SPI_5_NAME DT_ST_STM32_SPI_40015000_LABEL -#define CONFIG_SPI_5_IRQ DT_ST_STM32_SPI_40015000_IRQ_0 +#define DT_SPI_5_IRQ DT_ST_STM32_SPI_40015000_IRQ_0 -#define CONFIG_SPI_6_BASE_ADDRESS DT_ST_STM32_SPI_40015400_BASE_ADDRESS -#define CONFIG_SPI_6_IRQ_PRI DT_ST_STM32_SPI_40015400_IRQ_0_PRIORITY -#define CONFIG_SPI_6_NAME DT_ST_STM32_SPI_40015400_LABEL -#define CONFIG_SPI_6_IRQ DT_ST_STM32_SPI_40015400_IRQ_0 +#define DT_SPI_6_BASE_ADDRESS DT_ST_STM32_SPI_40015400_BASE_ADDRESS +#define DT_SPI_6_IRQ_PRI DT_ST_STM32_SPI_40015400_IRQ_0_PRIORITY +#define DT_SPI_6_NAME DT_ST_STM32_SPI_40015400_LABEL +#define DT_SPI_6_IRQ DT_ST_STM32_SPI_40015400_IRQ_0 -#define CONFIG_I2S_1_BASE_ADDRESS DT_ST_STM32_I2S_40013000_BASE_ADDRESS -#define CONFIG_I2S_1_IRQ_PRI DT_ST_STM32_I2S_40013000_IRQ_0_PRIORITY -#define CONFIG_I2S_1_NAME DT_ST_STM32_I2S_40013000_LABEL -#define CONFIG_I2S_1_IRQ DT_ST_STM32_I2S_40013000_IRQ_0 -#define CONFIG_I2S_1_CLOCK_BITS DT_ST_STM32_I2S_40013000_CLOCK_BITS -#define CONFIG_I2S_1_CLOCK_BUS DT_ST_STM32_I2S_40013000_CLOCK_BUS +#define DT_I2S_1_BASE_ADDRESS DT_ST_STM32_I2S_40013000_BASE_ADDRESS +#define DT_I2S_1_IRQ_PRI DT_ST_STM32_I2S_40013000_IRQ_0_PRIORITY +#define DT_I2S_1_NAME DT_ST_STM32_I2S_40013000_LABEL +#define DT_I2S_1_IRQ DT_ST_STM32_I2S_40013000_IRQ_0 +#define DT_I2S_1_CLOCK_BITS DT_ST_STM32_I2S_40013000_CLOCK_BITS +#define DT_I2S_1_CLOCK_BUS DT_ST_STM32_I2S_40013000_CLOCK_BUS -#define CONFIG_I2S_2_BASE_ADDRESS DT_ST_STM32_I2S_40003800_BASE_ADDRESS -#define CONFIG_I2S_2_IRQ_PRI DT_ST_STM32_I2S_40003800_IRQ_0_PRIORITY -#define CONFIG_I2S_2_NAME DT_ST_STM32_I2S_40003800_LABEL -#define CONFIG_I2S_2_IRQ DT_ST_STM32_I2S_40003800_IRQ_0 -#define CONFIG_I2S_2_CLOCK_BITS DT_ST_STM32_I2S_40003800_CLOCK_BITS -#define CONFIG_I2S_2_CLOCK_BUS DT_ST_STM32_I2S_40003800_CLOCK_BUS +#define DT_I2S_2_BASE_ADDRESS DT_ST_STM32_I2S_40003800_BASE_ADDRESS +#define DT_I2S_2_IRQ_PRI DT_ST_STM32_I2S_40003800_IRQ_0_PRIORITY +#define DT_I2S_2_NAME DT_ST_STM32_I2S_40003800_LABEL +#define DT_I2S_2_IRQ DT_ST_STM32_I2S_40003800_IRQ_0 +#define DT_I2S_2_CLOCK_BITS DT_ST_STM32_I2S_40003800_CLOCK_BITS +#define DT_I2S_2_CLOCK_BUS DT_ST_STM32_I2S_40003800_CLOCK_BUS -#define CONFIG_I2S_3_BASE_ADDRESS DT_ST_STM32_I2S_40003C00_BASE_ADDRESS -#define CONFIG_I2S_3_IRQ_PRI DT_ST_STM32_I2S_40003C00_IRQ_0_PRIORITY -#define CONFIG_I2S_3_NAME DT_ST_STM32_I2S_40003C00_LABEL -#define CONFIG_I2S_3_IRQ DT_ST_STM32_I2S_40003C00_IRQ_0 -#define CONFIG_I2S_3_CLOCK_BITS DT_ST_STM32_I2S_40003C00_CLOCK_BITS -#define CONFIG_I2S_3_CLOCK_BUS DT_ST_STM32_I2S_40003C00_CLOCK_BUS +#define DT_I2S_3_BASE_ADDRESS DT_ST_STM32_I2S_40003C00_BASE_ADDRESS +#define DT_I2S_3_IRQ_PRI DT_ST_STM32_I2S_40003C00_IRQ_0_PRIORITY +#define DT_I2S_3_NAME DT_ST_STM32_I2S_40003C00_LABEL +#define DT_I2S_3_IRQ DT_ST_STM32_I2S_40003C00_IRQ_0 +#define DT_I2S_3_CLOCK_BITS DT_ST_STM32_I2S_40003C00_CLOCK_BITS +#define DT_I2S_3_CLOCK_BUS DT_ST_STM32_I2S_40003C00_CLOCK_BUS -#define CONFIG_I2S_4_BASE_ADDRESS DT_ST_STM32_I2S_40013400_BASE_ADDRESS -#define CONFIG_I2S_4_IRQ_PRI DT_ST_STM32_I2S_40013400_IRQ_0_PRIORITY -#define CONFIG_I2S_4_NAME DT_ST_STM32_I2S_40013400_LABEL -#define CONFIG_I2S_4_IRQ DT_ST_STM32_I2S_40013400_IRQ_0 -#define CONFIG_I2S_4_CLOCK_BITS DT_ST_STM32_I2S_40013400_CLOCK_BITS -#define CONFIG_I2S_4_CLOCK_BUS DT_ST_STM32_I2S_40013400_CLOCK_BUS +#define DT_I2S_4_BASE_ADDRESS DT_ST_STM32_I2S_40013400_BASE_ADDRESS +#define DT_I2S_4_IRQ_PRI DT_ST_STM32_I2S_40013400_IRQ_0_PRIORITY +#define DT_I2S_4_NAME DT_ST_STM32_I2S_40013400_LABEL +#define DT_I2S_4_IRQ DT_ST_STM32_I2S_40013400_IRQ_0 +#define DT_I2S_4_CLOCK_BITS DT_ST_STM32_I2S_40013400_CLOCK_BITS +#define DT_I2S_4_CLOCK_BUS DT_ST_STM32_I2S_40013400_CLOCK_BUS -#define CONFIG_I2S_5_BASE_ADDRESS DT_ST_STM32_I2S_40015000_BASE_ADDRESS -#define CONFIG_I2S_5_IRQ_PRI DT_ST_STM32_I2S_40015000_IRQ_0_PRIORITY -#define CONFIG_I2S_5_NAME DT_ST_STM32_I2S_40015000_LABEL -#define CONFIG_I2S_5_IRQ DT_ST_STM32_I2S_40015000_IRQ_0 -#define CONFIG_I2S_5_CLOCK_BITS DT_ST_STM32_I2S_40015000_CLOCK_BITS -#define CONFIG_I2S_5_CLOCK_BUS DT_ST_STM32_I2S_40015000_CLOCK_BUS +#define DT_I2S_5_BASE_ADDRESS DT_ST_STM32_I2S_40015000_BASE_ADDRESS +#define DT_I2S_5_IRQ_PRI DT_ST_STM32_I2S_40015000_IRQ_0_PRIORITY +#define DT_I2S_5_NAME DT_ST_STM32_I2S_40015000_LABEL +#define DT_I2S_5_IRQ DT_ST_STM32_I2S_40015000_IRQ_0 +#define DT_I2S_5_CLOCK_BITS DT_ST_STM32_I2S_40015000_CLOCK_BITS +#define DT_I2S_5_CLOCK_BUS DT_ST_STM32_I2S_40015000_CLOCK_BUS -#define CONFIG_I2S_6_BASE_ADDRESS DT_ST_STM32_I2S_40015400_BASE_ADDRESS -#define CONFIG_I2S_6_IRQ_PRI DT_ST_STM32_I2S_40015400_IRQ_0_PRIORITY -#define CONFIG_I2S_6_NAME DT_ST_STM32_I2S_40015400_LABEL -#define CONFIG_I2S_6_IRQ DT_ST_STM32_I2S_40015400_IRQ_0 -#define CONFIG_I2S_6_CLOCK_BITS DT_ST_STM32_I2S_40015400_CLOCK_BITS -#define CONFIG_I2S_6_CLOCK_BUS DT_ST_STM32_I2S_40015400_CLOCK_BUS +#define DT_I2S_6_BASE_ADDRESS DT_ST_STM32_I2S_40015400_BASE_ADDRESS +#define DT_I2S_6_IRQ_PRI DT_ST_STM32_I2S_40015400_IRQ_0_PRIORITY +#define DT_I2S_6_NAME DT_ST_STM32_I2S_40015400_LABEL +#define DT_I2S_6_IRQ DT_ST_STM32_I2S_40015400_IRQ_0 +#define DT_I2S_6_CLOCK_BITS DT_ST_STM32_I2S_40015400_CLOCK_BITS +#define DT_I2S_6_CLOCK_BUS DT_ST_STM32_I2S_40015400_CLOCK_BUS -#define FLASH_DEV_BASE_ADDRESS DT_ST_STM32F4_FLASH_CONTROLLER_40023C00_BASE_ADDRESS -#define FLASH_DEV_NAME DT_ST_STM32F4_FLASH_CONTROLLER_40023C00_LABEL +#define DT_FLASH_DEV_BASE_ADDRESS DT_ST_STM32F4_FLASH_CONTROLLER_40023C00_BASE_ADDRESS +#define DT_FLASH_DEV_NAME DT_ST_STM32F4_FLASH_CONTROLLER_40023C00_LABEL #ifdef DT_ST_STM32_OTGFS_50000000_BASE_ADDRESS -#define CONFIG_USB_BASE_ADDRESS DT_ST_STM32_OTGFS_50000000_BASE_ADDRESS -#define CONFIG_USB_IRQ DT_ST_STM32_OTGFS_50000000_IRQ_OTGFS -#define CONFIG_USB_IRQ_PRI DT_ST_STM32_OTGFS_50000000_IRQ_OTGFS_PRIORITY -#define CONFIG_USB_NUM_BIDIR_ENDPOINTS DT_ST_STM32_OTGFS_50000000_NUM_BIDIR_ENDPOINTS -#define CONFIG_USB_RAM_SIZE DT_ST_STM32_OTGFS_50000000_RAM_SIZE -#define CONFIG_USB_MAXIMUM_SPEED DT_ST_STM32_OTGFS_50000000_MAXIMUM_SPEED +#define DT_USB_BASE_ADDRESS DT_ST_STM32_OTGFS_50000000_BASE_ADDRESS +#define DT_USB_IRQ DT_ST_STM32_OTGFS_50000000_IRQ_OTGFS +#define DT_USB_IRQ_PRI DT_ST_STM32_OTGFS_50000000_IRQ_OTGFS_PRIORITY +#define DT_USB_NUM_BIDIR_ENDPOINTS DT_ST_STM32_OTGFS_50000000_NUM_BIDIR_ENDPOINTS +#define DT_USB_RAM_SIZE DT_ST_STM32_OTGFS_50000000_RAM_SIZE +#define DT_USB_MAXIMUM_SPEED DT_ST_STM32_OTGFS_50000000_MAXIMUM_SPEED #endif /* DT_ST_STM32_OTGFS_50000000_BASE_ADDRESS */ #ifdef DT_ST_STM32_OTGHS_40040000_BASE_ADDRESS -#define CONFIG_USB_HS_BASE_ADDRESS DT_ST_STM32_OTGHS_40040000_BASE_ADDRESS -#define CONFIG_USB_IRQ DT_ST_STM32_OTGHS_40040000_IRQ_OTGHS -#define CONFIG_USB_IRQ_PRI DT_ST_STM32_OTGHS_40040000_IRQ_OTGHS_PRIORITY -#define CONFIG_USB_NUM_BIDIR_ENDPOINTS DT_ST_STM32_OTGHS_40040000_NUM_BIDIR_ENDPOINTS -#define CONFIG_USB_RAM_SIZE DT_ST_STM32_OTGHS_40040000_RAM_SIZE -#define CONFIG_USB_MAXIMUM_SPEED DT_ST_STM32_OTGHS_40040000_MAXIMUM_SPEED +#define DT_USB_HS_BASE_ADDRESS DT_ST_STM32_OTGHS_40040000_BASE_ADDRESS +#define DT_USB_IRQ DT_ST_STM32_OTGHS_40040000_IRQ_OTGHS +#define DT_USB_IRQ_PRI DT_ST_STM32_OTGHS_40040000_IRQ_OTGHS_PRIORITY +#define DT_USB_NUM_BIDIR_ENDPOINTS DT_ST_STM32_OTGHS_40040000_NUM_BIDIR_ENDPOINTS +#define DT_USB_RAM_SIZE DT_ST_STM32_OTGHS_40040000_RAM_SIZE +#define DT_USB_MAXIMUM_SPEED DT_ST_STM32_OTGHS_40040000_MAXIMUM_SPEED #endif /* DT_ST_STM32_OTGHS_40040000_BASE_ADDRESS */ -#define CONFIG_PWM_STM32_1_DEV_NAME DT_ST_STM32_PWM_40010000_PWM_LABEL -#define CONFIG_PWM_STM32_1_PRESCALER DT_ST_STM32_PWM_40010000_PWM_ST_PRESCALER +#define DT_PWM_STM32_1_DEV_NAME DT_ST_STM32_PWM_40010000_PWM_LABEL +#define DT_PWM_STM32_1_PRESCALER DT_ST_STM32_PWM_40010000_PWM_ST_PRESCALER -#define CONFIG_PWM_STM32_2_DEV_NAME DT_ST_STM32_PWM_40000000_PWM_LABEL -#define CONFIG_PWM_STM32_2_PRESCALER DT_ST_STM32_PWM_40000000_PWM_ST_PRESCALER +#define DT_PWM_STM32_2_DEV_NAME DT_ST_STM32_PWM_40000000_PWM_LABEL +#define DT_PWM_STM32_2_PRESCALER DT_ST_STM32_PWM_40000000_PWM_ST_PRESCALER -#define CONFIG_PWM_STM32_3_DEV_NAME DT_ST_STM32_PWM_40000400_PWM_LABEL -#define CONFIG_PWM_STM32_3_PRESCALER DT_ST_STM32_PWM_40000400_PWM_ST_PRESCALER +#define DT_PWM_STM32_3_DEV_NAME DT_ST_STM32_PWM_40000400_PWM_LABEL +#define DT_PWM_STM32_3_PRESCALER DT_ST_STM32_PWM_40000400_PWM_ST_PRESCALER -#define CONFIG_PWM_STM32_4_DEV_NAME DT_ST_STM32_PWM_40000800_PWM_LABEL -#define CONFIG_PWM_STM32_4_PRESCALER DT_ST_STM32_PWM_40000800_PWM_ST_PRESCALER +#define DT_PWM_STM32_4_DEV_NAME DT_ST_STM32_PWM_40000800_PWM_LABEL +#define DT_PWM_STM32_4_PRESCALER DT_ST_STM32_PWM_40000800_PWM_ST_PRESCALER -#define CONFIG_PWM_STM32_5_DEV_NAME DT_ST_STM32_PWM_40000C00_PWM_LABEL -#define CONFIG_PWM_STM32_5_PRESCALER DT_ST_STM32_PWM_40000C00_PWM_ST_PRESCALER +#define DT_PWM_STM32_5_DEV_NAME DT_ST_STM32_PWM_40000C00_PWM_LABEL +#define DT_PWM_STM32_5_PRESCALER DT_ST_STM32_PWM_40000C00_PWM_ST_PRESCALER -#define CONFIG_PWM_STM32_6_DEV_NAME DT_ST_STM32_PWM_40001000_PWM_LABEL -#define CONFIG_PWM_STM32_6_PRESCALER DT_ST_STM32_PWM_40001000_PWM_ST_PRESCALER +#define DT_PWM_STM32_6_DEV_NAME DT_ST_STM32_PWM_40001000_PWM_LABEL +#define DT_PWM_STM32_6_PRESCALER DT_ST_STM32_PWM_40001000_PWM_ST_PRESCALER -#define CONFIG_PWM_STM32_7_DEV_NAME DT_ST_STM32_PWM_40001400_PWM_LABEL -#define CONFIG_PWM_STM32_7_PRESCALER DT_ST_STM32_PWM_40001400_PWM_ST_PRESCALER +#define DT_PWM_STM32_7_DEV_NAME DT_ST_STM32_PWM_40001400_PWM_LABEL +#define DT_PWM_STM32_7_PRESCALER DT_ST_STM32_PWM_40001400_PWM_ST_PRESCALER -#define CONFIG_PWM_STM32_8_DEV_NAME DT_ST_STM32_PWM_40010400_PWM_LABEL -#define CONFIG_PWM_STM32_8_PRESCALER DT_ST_STM32_PWM_40010400_PWM_ST_PRESCALER +#define DT_PWM_STM32_8_DEV_NAME DT_ST_STM32_PWM_40010400_PWM_LABEL +#define DT_PWM_STM32_8_PRESCALER DT_ST_STM32_PWM_40010400_PWM_ST_PRESCALER -#define CONFIG_PWM_STM32_9_DEV_NAME DT_ST_STM32_PWM_40014000_PWM_LABEL -#define CONFIG_PWM_STM32_9_PRESCALER DT_ST_STM32_PWM_40014000_PWM_ST_PRESCALER +#define DT_PWM_STM32_9_DEV_NAME DT_ST_STM32_PWM_40014000_PWM_LABEL +#define DT_PWM_STM32_9_PRESCALER DT_ST_STM32_PWM_40014000_PWM_ST_PRESCALER -#define CONFIG_PWM_STM32_10_DEV_NAME DT_ST_STM32_PWM_40014400_PWM_LABEL -#define CONFIG_PWM_STM32_10_PRESCALER DT_ST_STM32_PWM_40014400_PWM_ST_PRESCALER +#define DT_PWM_STM32_10_DEV_NAME DT_ST_STM32_PWM_40014400_PWM_LABEL +#define DT_PWM_STM32_10_PRESCALER DT_ST_STM32_PWM_40014400_PWM_ST_PRESCALER -#define CONFIG_PWM_STM32_11_DEV_NAME DT_ST_STM32_PWM_40014800_PWM_LABEL -#define CONFIG_PWM_STM32_11_PRESCALER DT_ST_STM32_PWM_40014800_PWM_ST_PRESCALER +#define DT_PWM_STM32_11_DEV_NAME DT_ST_STM32_PWM_40014800_PWM_LABEL +#define DT_PWM_STM32_11_PRESCALER DT_ST_STM32_PWM_40014800_PWM_ST_PRESCALER -#define CONFIG_PWM_STM32_12_DEV_NAME DT_ST_STM32_PWM_40001800_PWM_LABEL -#define CONFIG_PWM_STM32_12_PRESCALER DT_ST_STM32_PWM_40001800_PWM_ST_PRESCALER +#define DT_PWM_STM32_12_DEV_NAME DT_ST_STM32_PWM_40001800_PWM_LABEL +#define DT_PWM_STM32_12_PRESCALER DT_ST_STM32_PWM_40001800_PWM_ST_PRESCALER -#define CONFIG_PWM_STM32_13_DEV_NAME DT_ST_STM32_PWM_40001C00_PWM_LABEL -#define CONFIG_PWM_STM32_13_PRESCALER DT_ST_STM32_PWM_40001C00_PWM_ST_PRESCALER +#define DT_PWM_STM32_13_DEV_NAME DT_ST_STM32_PWM_40001C00_PWM_LABEL +#define DT_PWM_STM32_13_PRESCALER DT_ST_STM32_PWM_40001C00_PWM_ST_PRESCALER -#define CONFIG_PWM_STM32_14_DEV_NAME DT_ST_STM32_PWM_40002000_PWM_LABEL -#define CONFIG_PWM_STM32_14_PRESCALER DT_ST_STM32_PWM_40002000_PWM_ST_PRESCALER +#define DT_PWM_STM32_14_DEV_NAME DT_ST_STM32_PWM_40002000_PWM_LABEL +#define DT_PWM_STM32_14_PRESCALER DT_ST_STM32_PWM_40002000_PWM_ST_PRESCALER -#define CONFIG_RTC_0_BASE_ADDRESS DT_ST_STM32_RTC_40002800_BASE_ADDRESS +#define DT_RTC_0_BASE_ADDRESS DT_ST_STM32_RTC_40002800_BASE_ADDRESS #define CONFIG_RTC_0_IRQ_PRI DT_ST_STM32_RTC_40002800_IRQ_0_PRIORITY -#define CONFIG_RTC_0_IRQ DT_ST_STM32_RTC_40002800_IRQ_0 +#define DT_RTC_0_IRQ DT_ST_STM32_RTC_40002800_IRQ_0 #define CONFIG_RTC_0_NAME DT_ST_STM32_RTC_40002800_LABEL #define CONFIG_RTC_PRESCALER DT_ST_STM32_RTC_40002800_PRESCALER diff --git a/soc/arm/st_stm32/stm32f7/dts_fixup.h b/soc/arm/st_stm32/stm32f7/dts_fixup.h index 7b4df8b9fdc..785e0ba563b 100644 --- a/soc/arm/st_stm32/stm32f7/dts_fixup.h +++ b/soc/arm/st_stm32/stm32f7/dts_fixup.h @@ -1,293 +1,293 @@ /* SoC level DTS fixup file */ -#define CONFIG_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS +#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS -#define CONFIG_GPIO_STM32_GPIOA_BASE_ADDRESS DT_ST_STM32_GPIO_40020000_BASE_ADDRESS -#define CONFIG_GPIO_STM32_GPIOA_CLOCK_BITS_0 DT_ST_STM32_GPIO_40020000_CLOCK_BITS_0 -#define CONFIG_GPIO_STM32_GPIOA_CLOCK_BUS_0 DT_ST_STM32_GPIO_40020000_CLOCK_BUS_0 -#define CONFIG_GPIO_STM32_GPIOA_CLOCK_CONTROLLER DT_ST_STM32_GPIO_40020000_CLOCK_CONTROLLER -#define CONFIG_GPIO_STM32_GPIOA_LABEL DT_ST_STM32_GPIO_40020000_LABEL -#define CONFIG_GPIO_STM32_GPIOA_SIZE DT_ST_STM32_GPIO_40020000_SIZE -#define CONFIG_GPIO_STM32_GPIOA_CLOCK_BITS DT_ST_STM32_GPIO_40020000_CLOCK_BITS -#define CONFIG_GPIO_STM32_GPIOA_CLOCK_BUS DT_ST_STM32_GPIO_40020000_CLOCK_BUS +#define DT_GPIO_STM32_GPIOA_BASE_ADDRESS DT_ST_STM32_GPIO_40020000_BASE_ADDRESS +#define DT_GPIO_STM32_GPIOA_CLOCK_BITS_0 DT_ST_STM32_GPIO_40020000_CLOCK_BITS_0 +#define DT_GPIO_STM32_GPIOA_CLOCK_BUS_0 DT_ST_STM32_GPIO_40020000_CLOCK_BUS_0 +#define DT_GPIO_STM32_GPIOA_CLOCK_CONTROLLER DT_ST_STM32_GPIO_40020000_CLOCK_CONTROLLER +#define DT_GPIO_STM32_GPIOA_LABEL DT_ST_STM32_GPIO_40020000_LABEL +#define DT_GPIO_STM32_GPIOA_SIZE DT_ST_STM32_GPIO_40020000_SIZE +#define DT_GPIO_STM32_GPIOA_CLOCK_BITS DT_ST_STM32_GPIO_40020000_CLOCK_BITS +#define DT_GPIO_STM32_GPIOA_CLOCK_BUS DT_ST_STM32_GPIO_40020000_CLOCK_BUS -#define CONFIG_GPIO_STM32_GPIOB_BASE_ADDRESS DT_ST_STM32_GPIO_40020400_BASE_ADDRESS -#define CONFIG_GPIO_STM32_GPIOB_CLOCK_BITS_0 DT_ST_STM32_GPIO_40020400_CLOCK_BITS_0 -#define CONFIG_GPIO_STM32_GPIOB_CLOCK_BUS_0 DT_ST_STM32_GPIO_40020400_CLOCK_BUS_0 -#define CONFIG_GPIO_STM32_GPIOB_CLOCK_CONTROLLER DT_ST_STM32_GPIO_40020400_CLOCK_CONTROLLER -#define CONFIG_GPIO_STM32_GPIOB_LABEL DT_ST_STM32_GPIO_40020400_LABEL -#define CONFIG_GPIO_STM32_GPIOB_SIZE DT_ST_STM32_GPIO_40020400_SIZE -#define CONFIG_GPIO_STM32_GPIOB_CLOCK_BITS DT_ST_STM32_GPIO_40020400_CLOCK_BITS -#define CONFIG_GPIO_STM32_GPIOB_CLOCK_BUS DT_ST_STM32_GPIO_40020400_CLOCK_BUS +#define DT_GPIO_STM32_GPIOB_BASE_ADDRESS DT_ST_STM32_GPIO_40020400_BASE_ADDRESS +#define DT_GPIO_STM32_GPIOB_CLOCK_BITS_0 DT_ST_STM32_GPIO_40020400_CLOCK_BITS_0 +#define DT_GPIO_STM32_GPIOB_CLOCK_BUS_0 DT_ST_STM32_GPIO_40020400_CLOCK_BUS_0 +#define DT_GPIO_STM32_GPIOB_CLOCK_CONTROLLER DT_ST_STM32_GPIO_40020400_CLOCK_CONTROLLER +#define DT_GPIO_STM32_GPIOB_LABEL DT_ST_STM32_GPIO_40020400_LABEL +#define DT_GPIO_STM32_GPIOB_SIZE DT_ST_STM32_GPIO_40020400_SIZE +#define DT_GPIO_STM32_GPIOB_CLOCK_BITS DT_ST_STM32_GPIO_40020400_CLOCK_BITS +#define DT_GPIO_STM32_GPIOB_CLOCK_BUS DT_ST_STM32_GPIO_40020400_CLOCK_BUS -#define CONFIG_GPIO_STM32_GPIOC_BASE_ADDRESS DT_ST_STM32_GPIO_40020800_BASE_ADDRESS -#define CONFIG_GPIO_STM32_GPIOC_CLOCK_BITS_0 DT_ST_STM32_GPIO_40020800_CLOCK_BITS_0 -#define CONFIG_GPIO_STM32_GPIOC_CLOCK_BUS_0 DT_ST_STM32_GPIO_40020800_CLOCK_BUS_0 -#define CONFIG_GPIO_STM32_GPIOC_CLOCK_CONTROLLER DT_ST_STM32_GPIO_40020800_CLOCK_CONTROLLER -#define CONFIG_GPIO_STM32_GPIOC_LABEL DT_ST_STM32_GPIO_40020800_LABEL -#define CONFIG_GPIO_STM32_GPIOC_SIZE DT_ST_STM32_GPIO_40020800_SIZE -#define CONFIG_GPIO_STM32_GPIOC_CLOCK_BITS DT_ST_STM32_GPIO_40020800_CLOCK_BITS -#define CONFIG_GPIO_STM32_GPIOC_CLOCK_BUS DT_ST_STM32_GPIO_40020800_CLOCK_BUS +#define DT_GPIO_STM32_GPIOC_BASE_ADDRESS DT_ST_STM32_GPIO_40020800_BASE_ADDRESS +#define DT_GPIO_STM32_GPIOC_CLOCK_BITS_0 DT_ST_STM32_GPIO_40020800_CLOCK_BITS_0 +#define DT_GPIO_STM32_GPIOC_CLOCK_BUS_0 DT_ST_STM32_GPIO_40020800_CLOCK_BUS_0 +#define DT_GPIO_STM32_GPIOC_CLOCK_CONTROLLER DT_ST_STM32_GPIO_40020800_CLOCK_CONTROLLER +#define DT_GPIO_STM32_GPIOC_LABEL DT_ST_STM32_GPIO_40020800_LABEL +#define DT_GPIO_STM32_GPIOC_SIZE DT_ST_STM32_GPIO_40020800_SIZE +#define DT_GPIO_STM32_GPIOC_CLOCK_BITS DT_ST_STM32_GPIO_40020800_CLOCK_BITS +#define DT_GPIO_STM32_GPIOC_CLOCK_BUS DT_ST_STM32_GPIO_40020800_CLOCK_BUS -#define CONFIG_GPIO_STM32_GPIOD_BASE_ADDRESS DT_ST_STM32_GPIO_40020C00_BASE_ADDRESS -#define CONFIG_GPIO_STM32_GPIOD_CLOCK_BITS_0 DT_ST_STM32_GPIO_40020C00_CLOCK_BITS_0 -#define CONFIG_GPIO_STM32_GPIOD_CLOCK_BUS_0 DT_ST_STM32_GPIO_40020C00_CLOCK_BUS_0 -#define CONFIG_GPIO_STM32_GPIOD_CLOCK_CONTROLLER DT_ST_STM32_GPIO_40020C00_CLOCK_CONTROLLER -#define CONFIG_GPIO_STM32_GPIOD_LABEL DT_ST_STM32_GPIO_40020C00_LABEL -#define CONFIG_GPIO_STM32_GPIOD_SIZE DT_ST_STM32_GPIO_40020C00_SIZE -#define CONFIG_GPIO_STM32_GPIOD_CLOCK_BITS DT_ST_STM32_GPIO_40020C00_CLOCK_BITS -#define CONFIG_GPIO_STM32_GPIOD_CLOCK_BUS DT_ST_STM32_GPIO_40020C00_CLOCK_BUS +#define DT_GPIO_STM32_GPIOD_BASE_ADDRESS DT_ST_STM32_GPIO_40020C00_BASE_ADDRESS +#define DT_GPIO_STM32_GPIOD_CLOCK_BITS_0 DT_ST_STM32_GPIO_40020C00_CLOCK_BITS_0 +#define DT_GPIO_STM32_GPIOD_CLOCK_BUS_0 DT_ST_STM32_GPIO_40020C00_CLOCK_BUS_0 +#define DT_GPIO_STM32_GPIOD_CLOCK_CONTROLLER DT_ST_STM32_GPIO_40020C00_CLOCK_CONTROLLER +#define DT_GPIO_STM32_GPIOD_LABEL DT_ST_STM32_GPIO_40020C00_LABEL +#define DT_GPIO_STM32_GPIOD_SIZE DT_ST_STM32_GPIO_40020C00_SIZE +#define DT_GPIO_STM32_GPIOD_CLOCK_BITS DT_ST_STM32_GPIO_40020C00_CLOCK_BITS +#define DT_GPIO_STM32_GPIOD_CLOCK_BUS DT_ST_STM32_GPIO_40020C00_CLOCK_BUS -#define CONFIG_GPIO_STM32_GPIOE_BASE_ADDRESS DT_ST_STM32_GPIO_40021000_BASE_ADDRESS -#define CONFIG_GPIO_STM32_GPIOE_CLOCK_BITS_0 DT_ST_STM32_GPIO_40021000_CLOCK_BITS_0 -#define CONFIG_GPIO_STM32_GPIOE_CLOCK_BUS_0 DT_ST_STM32_GPIO_40021000_CLOCK_BUS_0 -#define CONFIG_GPIO_STM32_GPIOE_CLOCK_CONTROLLER DT_ST_STM32_GPIO_40021000_CLOCK_CONTROLLER -#define CONFIG_GPIO_STM32_GPIOE_LABEL DT_ST_STM32_GPIO_40021000_LABEL -#define CONFIG_GPIO_STM32_GPIOE_SIZE DT_ST_STM32_GPIO_40021000_SIZE -#define CONFIG_GPIO_STM32_GPIOE_CLOCK_BITS DT_ST_STM32_GPIO_40021000_CLOCK_BITS -#define CONFIG_GPIO_STM32_GPIOE_CLOCK_BUS DT_ST_STM32_GPIO_40021000_CLOCK_BUS +#define DT_GPIO_STM32_GPIOE_BASE_ADDRESS DT_ST_STM32_GPIO_40021000_BASE_ADDRESS +#define DT_GPIO_STM32_GPIOE_CLOCK_BITS_0 DT_ST_STM32_GPIO_40021000_CLOCK_BITS_0 +#define DT_GPIO_STM32_GPIOE_CLOCK_BUS_0 DT_ST_STM32_GPIO_40021000_CLOCK_BUS_0 +#define DT_GPIO_STM32_GPIOE_CLOCK_CONTROLLER DT_ST_STM32_GPIO_40021000_CLOCK_CONTROLLER +#define DT_GPIO_STM32_GPIOE_LABEL DT_ST_STM32_GPIO_40021000_LABEL +#define DT_GPIO_STM32_GPIOE_SIZE DT_ST_STM32_GPIO_40021000_SIZE +#define DT_GPIO_STM32_GPIOE_CLOCK_BITS DT_ST_STM32_GPIO_40021000_CLOCK_BITS +#define DT_GPIO_STM32_GPIOE_CLOCK_BUS DT_ST_STM32_GPIO_40021000_CLOCK_BUS -#define CONFIG_GPIO_STM32_GPIOF_BASE_ADDRESS DT_ST_STM32_GPIO_40021400_BASE_ADDRESS -#define CONFIG_GPIO_STM32_GPIOF_CLOCK_BITS_0 DT_ST_STM32_GPIO_40021400_CLOCK_BITS_0 -#define CONFIG_GPIO_STM32_GPIOF_CLOCK_BUS_0 DT_ST_STM32_GPIO_40021400_CLOCK_BUS_0 -#define CONFIG_GPIO_STM32_GPIOF_CLOCK_CONTROLLER DT_ST_STM32_GPIO_40021400_CLOCK_CONTROLLER -#define CONFIG_GPIO_STM32_GPIOF_LABEL DT_ST_STM32_GPIO_40021400_LABEL -#define CONFIG_GPIO_STM32_GPIOF_SIZE DT_ST_STM32_GPIO_40021400_SIZE -#define CONFIG_GPIO_STM32_GPIOF_CLOCK_BITS DT_ST_STM32_GPIO_40021400_CLOCK_BITS -#define CONFIG_GPIO_STM32_GPIOF_CLOCK_BUS DT_ST_STM32_GPIO_40021400_CLOCK_BUS +#define DT_GPIO_STM32_GPIOF_BASE_ADDRESS DT_ST_STM32_GPIO_40021400_BASE_ADDRESS +#define DT_GPIO_STM32_GPIOF_CLOCK_BITS_0 DT_ST_STM32_GPIO_40021400_CLOCK_BITS_0 +#define DT_GPIO_STM32_GPIOF_CLOCK_BUS_0 DT_ST_STM32_GPIO_40021400_CLOCK_BUS_0 +#define DT_GPIO_STM32_GPIOF_CLOCK_CONTROLLER DT_ST_STM32_GPIO_40021400_CLOCK_CONTROLLER +#define DT_GPIO_STM32_GPIOF_LABEL DT_ST_STM32_GPIO_40021400_LABEL +#define DT_GPIO_STM32_GPIOF_SIZE DT_ST_STM32_GPIO_40021400_SIZE +#define DT_GPIO_STM32_GPIOF_CLOCK_BITS DT_ST_STM32_GPIO_40021400_CLOCK_BITS +#define DT_GPIO_STM32_GPIOF_CLOCK_BUS DT_ST_STM32_GPIO_40021400_CLOCK_BUS -#define CONFIG_GPIO_STM32_GPIOG_BASE_ADDRESS DT_ST_STM32_GPIO_40021800_BASE_ADDRESS -#define CONFIG_GPIO_STM32_GPIOG_CLOCK_BITS_0 DT_ST_STM32_GPIO_40021800_CLOCK_BITS_0 -#define CONFIG_GPIO_STM32_GPIOG_CLOCK_BUS_0 DT_ST_STM32_GPIO_40021800_CLOCK_BUS_0 -#define CONFIG_GPIO_STM32_GPIOG_CLOCK_CONTROLLER DT_ST_STM32_GPIO_40021800_CLOCK_CONTROLLER -#define CONFIG_GPIO_STM32_GPIOG_LABEL DT_ST_STM32_GPIO_40021800_LABEL -#define CONFIG_GPIO_STM32_GPIOG_SIZE DT_ST_STM32_GPIO_40021800_SIZE -#define CONFIG_GPIO_STM32_GPIOG_CLOCK_BITS DT_ST_STM32_GPIO_40021800_CLOCK_BITS -#define CONFIG_GPIO_STM32_GPIOG_CLOCK_BUS DT_ST_STM32_GPIO_40021800_CLOCK_BUS +#define DT_GPIO_STM32_GPIOG_BASE_ADDRESS DT_ST_STM32_GPIO_40021800_BASE_ADDRESS +#define DT_GPIO_STM32_GPIOG_CLOCK_BITS_0 DT_ST_STM32_GPIO_40021800_CLOCK_BITS_0 +#define DT_GPIO_STM32_GPIOG_CLOCK_BUS_0 DT_ST_STM32_GPIO_40021800_CLOCK_BUS_0 +#define DT_GPIO_STM32_GPIOG_CLOCK_CONTROLLER DT_ST_STM32_GPIO_40021800_CLOCK_CONTROLLER +#define DT_GPIO_STM32_GPIOG_LABEL DT_ST_STM32_GPIO_40021800_LABEL +#define DT_GPIO_STM32_GPIOG_SIZE DT_ST_STM32_GPIO_40021800_SIZE +#define DT_GPIO_STM32_GPIOG_CLOCK_BITS DT_ST_STM32_GPIO_40021800_CLOCK_BITS +#define DT_GPIO_STM32_GPIOG_CLOCK_BUS DT_ST_STM32_GPIO_40021800_CLOCK_BUS -#define CONFIG_GPIO_STM32_GPIOH_BASE_ADDRESS DT_ST_STM32_GPIO_40021C00_BASE_ADDRESS -#define CONFIG_GPIO_STM32_GPIOH_CLOCK_BITS_0 DT_ST_STM32_GPIO_40021C00_CLOCK_BITS_0 -#define CONFIG_GPIO_STM32_GPIOH_CLOCK_BUS_0 DT_ST_STM32_GPIO_40021C00_CLOCK_BUS_0 -#define CONFIG_GPIO_STM32_GPIOH_CLOCK_CONTROLLER DT_ST_STM32_GPIO_40021C00_CLOCK_CONTROLLER -#define CONFIG_GPIO_STM32_GPIOH_LABEL DT_ST_STM32_GPIO_40021C00_LABEL -#define CONFIG_GPIO_STM32_GPIOH_SIZE DT_ST_STM32_GPIO_40021C00_SIZE -#define CONFIG_GPIO_STM32_GPIOH_CLOCK_BITS DT_ST_STM32_GPIO_40021C00_CLOCK_BITS -#define CONFIG_GPIO_STM32_GPIOH_CLOCK_BUS DT_ST_STM32_GPIO_40021C00_CLOCK_BUS +#define DT_GPIO_STM32_GPIOH_BASE_ADDRESS DT_ST_STM32_GPIO_40021C00_BASE_ADDRESS +#define DT_GPIO_STM32_GPIOH_CLOCK_BITS_0 DT_ST_STM32_GPIO_40021C00_CLOCK_BITS_0 +#define DT_GPIO_STM32_GPIOH_CLOCK_BUS_0 DT_ST_STM32_GPIO_40021C00_CLOCK_BUS_0 +#define DT_GPIO_STM32_GPIOH_CLOCK_CONTROLLER DT_ST_STM32_GPIO_40021C00_CLOCK_CONTROLLER +#define DT_GPIO_STM32_GPIOH_LABEL DT_ST_STM32_GPIO_40021C00_LABEL +#define DT_GPIO_STM32_GPIOH_SIZE DT_ST_STM32_GPIO_40021C00_SIZE +#define DT_GPIO_STM32_GPIOH_CLOCK_BITS DT_ST_STM32_GPIO_40021C00_CLOCK_BITS +#define DT_GPIO_STM32_GPIOH_CLOCK_BUS DT_ST_STM32_GPIO_40021C00_CLOCK_BUS -#define CONFIG_GPIO_STM32_GPIOI_BASE_ADDRESS DT_ST_STM32_GPIO_40022000_BASE_ADDRESS -#define CONFIG_GPIO_STM32_GPIOI_CLOCK_BITS_0 DT_ST_STM32_GPIO_40022000_CLOCK_BITS_0 -#define CONFIG_GPIO_STM32_GPIOI_CLOCK_BUS_0 DT_ST_STM32_GPIO_40022000_CLOCK_BUS_0 -#define CONFIG_GPIO_STM32_GPIOI_CLOCK_CONTROLLER DT_ST_STM32_GPIO_40022000_CLOCK_CONTROLLER -#define CONFIG_GPIO_STM32_GPIOI_LABEL DT_ST_STM32_GPIO_40022000_LABEL -#define CONFIG_GPIO_STM32_GPIOI_SIZE DT_ST_STM32_GPIO_40022000_SIZE -#define CONFIG_GPIO_STM32_GPIOI_CLOCK_BITS DT_ST_STM32_GPIO_40022000_CLOCK_BITS -#define CONFIG_GPIO_STM32_GPIOI_CLOCK_BUS DT_ST_STM32_GPIO_40022000_CLOCK_BUS +#define DT_GPIO_STM32_GPIOI_BASE_ADDRESS DT_ST_STM32_GPIO_40022000_BASE_ADDRESS +#define DT_GPIO_STM32_GPIOI_CLOCK_BITS_0 DT_ST_STM32_GPIO_40022000_CLOCK_BITS_0 +#define DT_GPIO_STM32_GPIOI_CLOCK_BUS_0 DT_ST_STM32_GPIO_40022000_CLOCK_BUS_0 +#define DT_GPIO_STM32_GPIOI_CLOCK_CONTROLLER DT_ST_STM32_GPIO_40022000_CLOCK_CONTROLLER +#define DT_GPIO_STM32_GPIOI_LABEL DT_ST_STM32_GPIO_40022000_LABEL +#define DT_GPIO_STM32_GPIOI_SIZE DT_ST_STM32_GPIO_40022000_SIZE +#define DT_GPIO_STM32_GPIOI_CLOCK_BITS DT_ST_STM32_GPIO_40022000_CLOCK_BITS +#define DT_GPIO_STM32_GPIOI_CLOCK_BUS DT_ST_STM32_GPIO_40022000_CLOCK_BUS -#define CONFIG_GPIO_STM32_GPIOJ_BASE_ADDRESS DT_ST_STM32_GPIO_40022400_BASE_ADDRESS -#define CONFIG_GPIO_STM32_GPIOJ_CLOCK_BITS_0 DT_ST_STM32_GPIO_40022400_CLOCK_BITS_0 -#define CONFIG_GPIO_STM32_GPIOJ_CLOCK_BUS_0 DT_ST_STM32_GPIO_40022400_CLOCK_BUS_0 -#define CONFIG_GPIO_STM32_GPIOJ_CLOCK_CONTROLLER DT_ST_STM32_GPIO_40022400_CLOCK_CONTROLLER -#define CONFIG_GPIO_STM32_GPIOJ_LABEL DT_ST_STM32_GPIO_40022400_LABEL -#define CONFIG_GPIO_STM32_GPIOJ_SIZE DT_ST_STM32_GPIO_40022400_SIZE -#define CONFIG_GPIO_STM32_GPIOJ_CLOCK_BITS DT_ST_STM32_GPIO_40022400_CLOCK_BITS -#define CONFIG_GPIO_STM32_GPIOJ_CLOCK_BUS DT_ST_STM32_GPIO_40022400_CLOCK_BUS +#define DT_GPIO_STM32_GPIOJ_BASE_ADDRESS DT_ST_STM32_GPIO_40022400_BASE_ADDRESS +#define DT_GPIO_STM32_GPIOJ_CLOCK_BITS_0 DT_ST_STM32_GPIO_40022400_CLOCK_BITS_0 +#define DT_GPIO_STM32_GPIOJ_CLOCK_BUS_0 DT_ST_STM32_GPIO_40022400_CLOCK_BUS_0 +#define DT_GPIO_STM32_GPIOJ_CLOCK_CONTROLLER DT_ST_STM32_GPIO_40022400_CLOCK_CONTROLLER +#define DT_GPIO_STM32_GPIOJ_LABEL DT_ST_STM32_GPIO_40022400_LABEL +#define DT_GPIO_STM32_GPIOJ_SIZE DT_ST_STM32_GPIO_40022400_SIZE +#define DT_GPIO_STM32_GPIOJ_CLOCK_BITS DT_ST_STM32_GPIO_40022400_CLOCK_BITS +#define DT_GPIO_STM32_GPIOJ_CLOCK_BUS DT_ST_STM32_GPIO_40022400_CLOCK_BUS -#define CONFIG_GPIO_STM32_GPIOK_BASE_ADDRESS DT_ST_STM32_GPIO_40022800_BASE_ADDRESS -#define CONFIG_GPIO_STM32_GPIOK_CLOCK_BITS_0 DT_ST_STM32_GPIO_40022800_CLOCK_BITS_0 -#define CONFIG_GPIO_STM32_GPIOK_CLOCK_BUS_0 DT_ST_STM32_GPIO_40022800_CLOCK_BUS_0 -#define CONFIG_GPIO_STM32_GPIOK_CLOCK_CONTROLLER DT_ST_STM32_GPIO_40022800_CLOCK_CONTROLLER -#define CONFIG_GPIO_STM32_GPIOK_LABEL DT_ST_STM32_GPIO_40022800_LABEL -#define CONFIG_GPIO_STM32_GPIOK_SIZE DT_ST_STM32_GPIO_40022800_SIZE -#define CONFIG_GPIO_STM32_GPIOK_CLOCK_BITS DT_ST_STM32_GPIO_40022800_CLOCK_BITS -#define CONFIG_GPIO_STM32_GPIOK_CLOCK_BUS DT_ST_STM32_GPIO_40022800_CLOCK_BUS +#define DT_GPIO_STM32_GPIOK_BASE_ADDRESS DT_ST_STM32_GPIO_40022800_BASE_ADDRESS +#define DT_GPIO_STM32_GPIOK_CLOCK_BITS_0 DT_ST_STM32_GPIO_40022800_CLOCK_BITS_0 +#define DT_GPIO_STM32_GPIOK_CLOCK_BUS_0 DT_ST_STM32_GPIO_40022800_CLOCK_BUS_0 +#define DT_GPIO_STM32_GPIOK_CLOCK_CONTROLLER DT_ST_STM32_GPIO_40022800_CLOCK_CONTROLLER +#define DT_GPIO_STM32_GPIOK_LABEL DT_ST_STM32_GPIO_40022800_LABEL +#define DT_GPIO_STM32_GPIOK_SIZE DT_ST_STM32_GPIO_40022800_SIZE +#define DT_GPIO_STM32_GPIOK_CLOCK_BITS DT_ST_STM32_GPIO_40022800_CLOCK_BITS +#define DT_GPIO_STM32_GPIOK_CLOCK_BUS DT_ST_STM32_GPIO_40022800_CLOCK_BUS -#define CONFIG_UART_STM32_USART_1_BASE_ADDRESS DT_ST_STM32_USART_40011000_BASE_ADDRESS -#define CONFIG_UART_STM32_USART_1_BAUD_RATE DT_ST_STM32_USART_40011000_CURRENT_SPEED -#define CONFIG_UART_STM32_USART_1_IRQ_PRI DT_ST_STM32_USART_40011000_IRQ_0_PRIORITY -#define CONFIG_UART_STM32_USART_1_NAME DT_ST_STM32_USART_40011000_LABEL -#define USART_1_IRQ DT_ST_STM32_USART_40011000_IRQ_0 -#define CONFIG_UART_STM32_USART_1_CLOCK_BITS DT_ST_STM32_USART_40011000_CLOCK_BITS -#define CONFIG_UART_STM32_USART_1_CLOCK_BUS DT_ST_STM32_USART_40011000_CLOCK_BUS +#define DT_UART_STM32_USART_1_BASE_ADDRESS DT_ST_STM32_USART_40011000_BASE_ADDRESS +#define DT_UART_STM32_USART_1_BAUD_RATE DT_ST_STM32_USART_40011000_CURRENT_SPEED +#define DT_UART_STM32_USART_1_IRQ_PRI DT_ST_STM32_USART_40011000_IRQ_0_PRIORITY +#define DT_UART_STM32_USART_1_NAME DT_ST_STM32_USART_40011000_LABEL +#define DT_USART_1_IRQ DT_ST_STM32_USART_40011000_IRQ_0 +#define DT_UART_STM32_USART_1_CLOCK_BITS DT_ST_STM32_USART_40011000_CLOCK_BITS +#define DT_UART_STM32_USART_1_CLOCK_BUS DT_ST_STM32_USART_40011000_CLOCK_BUS -#define CONFIG_UART_STM32_USART_2_BASE_ADDRESS DT_ST_STM32_USART_40004400_BASE_ADDRESS -#define CONFIG_UART_STM32_USART_2_BAUD_RATE DT_ST_STM32_USART_40004400_CURRENT_SPEED -#define CONFIG_UART_STM32_USART_2_IRQ_PRI DT_ST_STM32_USART_40004400_IRQ_0_PRIORITY -#define CONFIG_UART_STM32_USART_2_NAME DT_ST_STM32_USART_40004400_LABEL -#define USART_2_IRQ DT_ST_STM32_USART_40004400_IRQ_0 -#define CONFIG_UART_STM32_USART_2_CLOCK_BITS DT_ST_STM32_USART_40004400_CLOCK_BITS -#define CONFIG_UART_STM32_USART_2_CLOCK_BUS DT_ST_STM32_USART_40004400_CLOCK_BUS +#define DT_UART_STM32_USART_2_BASE_ADDRESS DT_ST_STM32_USART_40004400_BASE_ADDRESS +#define DT_UART_STM32_USART_2_BAUD_RATE DT_ST_STM32_USART_40004400_CURRENT_SPEED +#define DT_UART_STM32_USART_2_IRQ_PRI DT_ST_STM32_USART_40004400_IRQ_0_PRIORITY +#define DT_UART_STM32_USART_2_NAME DT_ST_STM32_USART_40004400_LABEL +#define DT_USART_2_IRQ DT_ST_STM32_USART_40004400_IRQ_0 +#define DT_UART_STM32_USART_2_CLOCK_BITS DT_ST_STM32_USART_40004400_CLOCK_BITS +#define DT_UART_STM32_USART_2_CLOCK_BUS DT_ST_STM32_USART_40004400_CLOCK_BUS -#define CONFIG_UART_STM32_USART_3_BASE_ADDRESS DT_ST_STM32_USART_40004800_BASE_ADDRESS -#define CONFIG_UART_STM32_USART_3_BAUD_RATE DT_ST_STM32_USART_40004800_CURRENT_SPEED -#define CONFIG_UART_STM32_USART_3_IRQ_PRI DT_ST_STM32_USART_40004800_IRQ_0_PRIORITY -#define CONFIG_UART_STM32_USART_3_NAME DT_ST_STM32_USART_40004800_LABEL -#define USART_3_IRQ DT_ST_STM32_USART_40004800_IRQ_0 -#define CONFIG_UART_STM32_USART_3_CLOCK_BITS DT_ST_STM32_USART_40004800_CLOCK_BITS -#define CONFIG_UART_STM32_USART_3_CLOCK_BUS DT_ST_STM32_USART_40004800_CLOCK_BUS +#define DT_UART_STM32_USART_3_BASE_ADDRESS DT_ST_STM32_USART_40004800_BASE_ADDRESS +#define DT_UART_STM32_USART_3_BAUD_RATE DT_ST_STM32_USART_40004800_CURRENT_SPEED +#define DT_UART_STM32_USART_3_IRQ_PRI DT_ST_STM32_USART_40004800_IRQ_0_PRIORITY +#define DT_UART_STM32_USART_3_NAME DT_ST_STM32_USART_40004800_LABEL +#define DT_USART_3_IRQ DT_ST_STM32_USART_40004800_IRQ_0 +#define DT_UART_STM32_USART_3_CLOCK_BITS DT_ST_STM32_USART_40004800_CLOCK_BITS +#define DT_UART_STM32_USART_3_CLOCK_BUS DT_ST_STM32_USART_40004800_CLOCK_BUS -#define CONFIG_UART_STM32_USART_4_BASE_ADDRESS DT_ST_STM32_USART_40004C00_BASE_ADDRESS -#define CONFIG_UART_STM32_USART_4_BAUD_RATE DT_ST_STM32_USART_40004C00_CURRENT_SPEED -#define CONFIG_UART_STM32_USART_4_IRQ_PRI DT_ST_STM32_USART_40004C00_IRQ_0_PRIORITY -#define CONFIG_UART_STM32_USART_4_NAME DT_ST_STM32_USART_40004C00_LABEL -#define USART_4_IRQ DT_ST_STM32_USART_40004C00_IRQ_0 -#define CONFIG_UART_STM32_USART_4_CLOCK_BITS DT_ST_STM32_USART_40004C00_CLOCK_BITS -#define CONFIG_UART_STM32_USART_4_CLOCK_BUS DT_ST_STM32_USART_40004C00_CLOCK_BUS +#define DT_UART_STM32_USART_4_BASE_ADDRESS DT_ST_STM32_USART_40004C00_BASE_ADDRESS +#define DT_UART_STM32_USART_4_BAUD_RATE DT_ST_STM32_USART_40004C00_CURRENT_SPEED +#define DT_UART_STM32_USART_4_IRQ_PRI DT_ST_STM32_USART_40004C00_IRQ_0_PRIORITY +#define DT_UART_STM32_USART_4_NAME DT_ST_STM32_USART_40004C00_LABEL +#define DT_USART_4_IRQ DT_ST_STM32_USART_40004C00_IRQ_0 +#define DT_UART_STM32_USART_4_CLOCK_BITS DT_ST_STM32_USART_40004C00_CLOCK_BITS +#define DT_UART_STM32_USART_4_CLOCK_BUS DT_ST_STM32_USART_40004C00_CLOCK_BUS -#define CONFIG_UART_STM32_USART_5_BASE_ADDRESS DT_ST_STM32_USART_40005000_BASE_ADDRESS -#define CONFIG_UART_STM32_USART_5_BAUD_RATE DT_ST_STM32_USART_40005000_CURRENT_SPEED -#define CONFIG_UART_STM32_USART_5_IRQ_PRI DT_ST_STM32_USART_40005000_IRQ_0_PRIORITY -#define CONFIG_UART_STM32_USART_5_NAME DT_ST_STM32_USART_40005000_LABEL -#define USART_5_IRQ DT_ST_STM32_USART_40005000_IRQ_0 -#define CONFIG_UART_STM32_USART_5_CLOCK_BITS DT_ST_STM32_USART_40005000_CLOCK_BITS -#define CONFIG_UART_STM32_USART_5_CLOCK_BUS DT_ST_STM32_USART_40005000_CLOCK_BUS +#define DT_UART_STM32_USART_5_BASE_ADDRESS DT_ST_STM32_USART_40005000_BASE_ADDRESS +#define DT_UART_STM32_USART_5_BAUD_RATE DT_ST_STM32_USART_40005000_CURRENT_SPEED +#define DT_UART_STM32_USART_5_IRQ_PRI DT_ST_STM32_USART_40005000_IRQ_0_PRIORITY +#define DT_UART_STM32_USART_5_NAME DT_ST_STM32_USART_40005000_LABEL +#define DT_USART_5_IRQ DT_ST_STM32_USART_40005000_IRQ_0 +#define DT_UART_STM32_USART_5_CLOCK_BITS DT_ST_STM32_USART_40005000_CLOCK_BITS +#define DT_UART_STM32_USART_5_CLOCK_BUS DT_ST_STM32_USART_40005000_CLOCK_BUS -#define CONFIG_UART_STM32_USART_6_BASE_ADDRESS DT_ST_STM32_USART_40011400_BASE_ADDRESS -#define CONFIG_UART_STM32_USART_6_BAUD_RATE DT_ST_STM32_USART_40011400_CURRENT_SPEED -#define CONFIG_UART_STM32_USART_6_IRQ_PRI DT_ST_STM32_USART_40011400_IRQ_0_PRIORITY -#define CONFIG_UART_STM32_USART_6_NAME DT_ST_STM32_USART_40011400_LABEL -#define USART_6_IRQ DT_ST_STM32_USART_40011400_IRQ_0 -#define CONFIG_UART_STM32_USART_6_CLOCK_BITS DT_ST_STM32_USART_40011400_CLOCK_BITS -#define CONFIG_UART_STM32_USART_6_CLOCK_BUS DT_ST_STM32_USART_40011400_CLOCK_BUS +#define DT_UART_STM32_USART_6_BASE_ADDRESS DT_ST_STM32_USART_40011400_BASE_ADDRESS +#define DT_UART_STM32_USART_6_BAUD_RATE DT_ST_STM32_USART_40011400_CURRENT_SPEED +#define DT_UART_STM32_USART_6_IRQ_PRI DT_ST_STM32_USART_40011400_IRQ_0_PRIORITY +#define DT_UART_STM32_USART_6_NAME DT_ST_STM32_USART_40011400_LABEL +#define DT_USART_6_IRQ DT_ST_STM32_USART_40011400_IRQ_0 +#define DT_UART_STM32_USART_6_CLOCK_BITS DT_ST_STM32_USART_40011400_CLOCK_BITS +#define DT_UART_STM32_USART_6_CLOCK_BUS DT_ST_STM32_USART_40011400_CLOCK_BUS -#define CONFIG_UART_STM32_USART_7_BASE_ADDRESS DT_ST_STM32_USART_40007800_BASE_ADDRESS -#define CONFIG_UART_STM32_USART_7_BAUD_RATE DT_ST_STM32_USART_40007800_CURRENT_SPEED -#define CONFIG_UART_STM32_USART_7_IRQ_PRI DT_ST_STM32_USART_40007800_IRQ_0_PRIORITY -#define CONFIG_UART_STM32_USART_7_NAME DT_ST_STM32_USART_40007800_LABEL -#define USART_7_IRQ DT_ST_STM32_USART_40007800_IRQ_0 -#define CONFIG_UART_STM32_USART_7_CLOCK_BITS DT_ST_STM32_USART_40007800_CLOCK_BITS -#define CONFIG_UART_STM32_USART_7_CLOCK_BUS DT_ST_STM32_USART_40007800_CLOCK_BUS +#define DT_UART_STM32_USART_7_BASE_ADDRESS DT_ST_STM32_USART_40007800_BASE_ADDRESS +#define DT_UART_STM32_USART_7_BAUD_RATE DT_ST_STM32_USART_40007800_CURRENT_SPEED +#define DT_UART_STM32_USART_7_IRQ_PRI DT_ST_STM32_USART_40007800_IRQ_0_PRIORITY +#define DT_UART_STM32_USART_7_NAME DT_ST_STM32_USART_40007800_LABEL +#define DT_USART_7_IRQ DT_ST_STM32_USART_40007800_IRQ_0 +#define DT_UART_STM32_USART_7_CLOCK_BITS DT_ST_STM32_USART_40007800_CLOCK_BITS +#define DT_UART_STM32_USART_7_CLOCK_BUS DT_ST_STM32_USART_40007800_CLOCK_BUS -#define CONFIG_UART_STM32_USART_8_BASE_ADDRESS DT_ST_STM32_USART_40007C00_BASE_ADDRESS -#define CONFIG_UART_STM32_USART_8_BAUD_RATE DT_ST_STM32_USART_40007C00_CURRENT_SPEED -#define CONFIG_UART_STM32_USART_8_IRQ_PRI DT_ST_STM32_USART_40007C00_IRQ_0_PRIORITY -#define CONFIG_UART_STM32_USART_8_NAME DT_ST_STM32_USART_40007C00_LABEL -#define USART_8_IRQ DT_ST_STM32_USART_40007C00_IRQ_0 -#define CONFIG_UART_STM32_USART_8_CLOCK_BITS DT_ST_STM32_USART_40007C00_CLOCK_BITS -#define CONFIG_UART_STM32_USART_8_CLOCK_BUS DT_ST_STM32_USART_40007C00_CLOCK_BUS +#define DT_UART_STM32_USART_8_BASE_ADDRESS DT_ST_STM32_USART_40007C00_BASE_ADDRESS +#define DT_UART_STM32_USART_8_BAUD_RATE DT_ST_STM32_USART_40007C00_CURRENT_SPEED +#define DT_UART_STM32_USART_8_IRQ_PRI DT_ST_STM32_USART_40007C00_IRQ_0_PRIORITY +#define DT_UART_STM32_USART_8_NAME DT_ST_STM32_USART_40007C00_LABEL +#define DT_USART_8_IRQ DT_ST_STM32_USART_40007C00_IRQ_0 +#define DT_UART_STM32_USART_8_CLOCK_BITS DT_ST_STM32_USART_40007C00_CLOCK_BITS +#define DT_UART_STM32_USART_8_CLOCK_BUS DT_ST_STM32_USART_40007C00_CLOCK_BUS -#define CONFIG_I2C_1_BASE_ADDRESS DT_ST_STM32_I2C_V2_40005400_BASE_ADDRESS -#define CONFIG_I2C_1_EVENT_IRQ_PRI DT_ST_STM32_I2C_V2_40005400_IRQ_EVENT_PRIORITY -#define CONFIG_I2C_1_ERROR_IRQ_PRI DT_ST_STM32_I2C_V2_40005400_IRQ_ERROR_PRIORITY +#define DT_I2C_1_BASE_ADDRESS DT_ST_STM32_I2C_V2_40005400_BASE_ADDRESS +#define DT_I2C_1_EVENT_IRQ_PRI DT_ST_STM32_I2C_V2_40005400_IRQ_EVENT_PRIORITY +#define DT_I2C_1_ERROR_IRQ_PRI DT_ST_STM32_I2C_V2_40005400_IRQ_ERROR_PRIORITY #define CONFIG_I2C_1_NAME DT_ST_STM32_I2C_V2_40005400_LABEL -#define CONFIG_I2C_1_EVENT_IRQ DT_ST_STM32_I2C_V2_40005400_IRQ_EVENT -#define CONFIG_I2C_1_ERROR_IRQ DT_ST_STM32_I2C_V2_40005400_IRQ_ERROR -#define CONFIG_I2C_1_BITRATE DT_ST_STM32_I2C_V2_40005400_CLOCK_FREQUENCY -#define CONFIG_I2C_1_CLOCK_BITS DT_ST_STM32_I2C_V2_40005400_CLOCK_BITS -#define CONFIG_I2C_1_CLOCK_BUS DT_ST_STM32_I2C_V2_40005400_CLOCK_BUS +#define DT_I2C_1_EVENT_IRQ DT_ST_STM32_I2C_V2_40005400_IRQ_EVENT +#define DT_I2C_1_ERROR_IRQ DT_ST_STM32_I2C_V2_40005400_IRQ_ERROR +#define DT_I2C_1_BITRATE DT_ST_STM32_I2C_V2_40005400_CLOCK_FREQUENCY +#define DT_I2C_1_CLOCK_BITS DT_ST_STM32_I2C_V2_40005400_CLOCK_BITS +#define DT_I2C_1_CLOCK_BUS DT_ST_STM32_I2C_V2_40005400_CLOCK_BUS -#define CONFIG_I2C_2_BASE_ADDRESS DT_ST_STM32_I2C_V2_40005800_BASE_ADDRESS -#define CONFIG_I2C_2_EVENT_IRQ_PRI DT_ST_STM32_I2C_V2_40005800_IRQ_EVENT_PRIORITY -#define CONFIG_I2C_2_ERROR_IRQ_PRI DT_ST_STM32_I2C_V2_40005800_IRQ_ERROR_PRIORITY +#define DT_I2C_2_BASE_ADDRESS DT_ST_STM32_I2C_V2_40005800_BASE_ADDRESS +#define DT_I2C_2_EVENT_IRQ_PRI DT_ST_STM32_I2C_V2_40005800_IRQ_EVENT_PRIORITY +#define DT_I2C_2_ERROR_IRQ_PRI DT_ST_STM32_I2C_V2_40005800_IRQ_ERROR_PRIORITY #define CONFIG_I2C_2_NAME DT_ST_STM32_I2C_V2_40005800_LABEL -#define CONFIG_I2C_2_EVENT_IRQ DT_ST_STM32_I2C_V2_40005800_IRQ_EVENT -#define CONFIG_I2C_2_ERROR_IRQ DT_ST_STM32_I2C_V2_40005800_IRQ_ERROR -#define CONFIG_I2C_2_BITRATE DT_ST_STM32_I2C_V2_40005800_CLOCK_FREQUENCY -#define CONFIG_I2C_2_CLOCK_BITS DT_ST_STM32_I2C_V2_40005800_CLOCK_BITS -#define CONFIG_I2C_2_CLOCK_BUS DT_ST_STM32_I2C_V2_40005800_CLOCK_BUS +#define DT_I2C_2_EVENT_IRQ DT_ST_STM32_I2C_V2_40005800_IRQ_EVENT +#define DT_I2C_2_ERROR_IRQ DT_ST_STM32_I2C_V2_40005800_IRQ_ERROR +#define DT_I2C_2_BITRATE DT_ST_STM32_I2C_V2_40005800_CLOCK_FREQUENCY +#define DT_I2C_2_CLOCK_BITS DT_ST_STM32_I2C_V2_40005800_CLOCK_BITS +#define DT_I2C_2_CLOCK_BUS DT_ST_STM32_I2C_V2_40005800_CLOCK_BUS -#define CONFIG_I2C_3_BASE_ADDRESS DT_ST_STM32_I2C_V2_40005C00_BASE_ADDRESS -#define CONFIG_I2C_3_EVENT_IRQ_PRI DT_ST_STM32_I2C_V2_40005C00_IRQ_EVENT_PRIORITY -#define CONFIG_I2C_3_ERROR_IRQ_PRI DT_ST_STM32_I2C_V2_40005C00_IRQ_ERROR_PRIORITY +#define DT_I2C_3_BASE_ADDRESS DT_ST_STM32_I2C_V2_40005C00_BASE_ADDRESS +#define DT_I2C_3_EVENT_IRQ_PRI DT_ST_STM32_I2C_V2_40005C00_IRQ_EVENT_PRIORITY +#define DT_I2C_3_ERROR_IRQ_PRI DT_ST_STM32_I2C_V2_40005C00_IRQ_ERROR_PRIORITY #define CONFIG_I2C_3_NAME DT_ST_STM32_I2C_V2_40005C00_LABEL -#define CONFIG_I2C_3_EVENT_IRQ DT_ST_STM32_I2C_V2_40005C00_IRQ_EVENT -#define CONFIG_I2C_3_ERROR_IRQ DT_ST_STM32_I2C_V2_40005C00_IRQ_ERROR -#define CONFIG_I2C_3_BITRATE DT_ST_STM32_I2C_V2_40005C00_CLOCK_FREQUENCY -#define CONFIG_I2C_3_CLOCK_BITS DT_ST_STM32_I2C_V2_40005C00_CLOCK_BITS -#define CONFIG_I2C_3_CLOCK_BUS DT_ST_STM32_I2C_V2_40005C00_CLOCK_BUS +#define DT_I2C_3_EVENT_IRQ DT_ST_STM32_I2C_V2_40005C00_IRQ_EVENT +#define DT_I2C_3_ERROR_IRQ DT_ST_STM32_I2C_V2_40005C00_IRQ_ERROR +#define DT_I2C_3_BITRATE DT_ST_STM32_I2C_V2_40005C00_CLOCK_FREQUENCY +#define DT_I2C_3_CLOCK_BITS DT_ST_STM32_I2C_V2_40005C00_CLOCK_BITS +#define DT_I2C_3_CLOCK_BUS DT_ST_STM32_I2C_V2_40005C00_CLOCK_BUS -#define CONFIG_SPI_1_BASE_ADDRESS DT_ST_STM32_SPI_40013000_BASE_ADDRESS +#define DT_SPI_1_BASE_ADDRESS DT_ST_STM32_SPI_40013000_BASE_ADDRESS #define CONFIG_SPI_1_IRQ_PRI DT_ST_STM32_SPI_40013000_IRQ_0_PRIORITY #define CONFIG_SPI_1_NAME DT_ST_STM32_SPI_40013000_LABEL -#define CONFIG_SPI_1_IRQ DT_ST_STM32_SPI_40013000_IRQ_0 +#define DT_SPI_1_IRQ DT_ST_STM32_SPI_40013000_IRQ_0 -#define CONFIG_SPI_2_BASE_ADDRESS DT_ST_STM32_SPI_40003800_BASE_ADDRESS +#define DT_SPI_2_BASE_ADDRESS DT_ST_STM32_SPI_40003800_BASE_ADDRESS #define CONFIG_SPI_2_IRQ_PRI DT_ST_STM32_SPI_40003800_IRQ_0_PRIORITY #define CONFIG_SPI_2_NAME DT_ST_STM32_SPI_40003800_LABEL -#define CONFIG_SPI_2_IRQ DT_ST_STM32_SPI_40003800_IRQ_0 +#define DT_SPI_2_IRQ DT_ST_STM32_SPI_40003800_IRQ_0 -#define CONFIG_SPI_3_BASE_ADDRESS DT_ST_STM32_SPI_40003C00_BASE_ADDRESS +#define DT_SPI_3_BASE_ADDRESS DT_ST_STM32_SPI_40003C00_BASE_ADDRESS #define CONFIG_SPI_3_IRQ_PRI DT_ST_STM32_SPI_40003C00_IRQ_0_PRIORITY #define CONFIG_SPI_3_NAME DT_ST_STM32_SPI_40003C00_LABEL -#define CONFIG_SPI_3_IRQ DT_ST_STM32_SPI_40003C00_IRQ_0 +#define DT_SPI_3_IRQ DT_ST_STM32_SPI_40003C00_IRQ_0 -#define CONFIG_SPI_4_BASE_ADDRESS DT_ST_STM32_SPI_40013400_BASE_ADDRESS -#define CONFIG_SPI_4_IRQ_PRI DT_ST_STM32_SPI_40013400_IRQ_0_PRIORITY +#define DT_SPI_4_BASE_ADDRESS DT_ST_STM32_SPI_40013400_BASE_ADDRESS +#define DT_SPI_4_IRQ_PRI DT_ST_STM32_SPI_40013400_IRQ_0_PRIORITY #define CONFIG_SPI_4_NAME DT_ST_STM32_SPI_40013400_LABEL -#define CONFIG_SPI_4_IRQ DT_ST_STM32_SPI_40013400_IRQ_0 +#define DT_SPI_4_IRQ DT_ST_STM32_SPI_40013400_IRQ_0 -#define CONFIG_SPI_5_BASE_ADDRESS DT_ST_STM32_SPI_40015000_BASE_ADDRESS -#define CONFIG_SPI_5_IRQ_PRI DT_ST_STM32_SPI_40015000_IRQ_0_PRIORITY +#define DT_SPI_5_BASE_ADDRESS DT_ST_STM32_SPI_40015000_BASE_ADDRESS +#define DT_SPI_5_IRQ_PRI DT_ST_STM32_SPI_40015000_IRQ_0_PRIORITY #define CONFIG_SPI_5_NAME DT_ST_STM32_SPI_40015000_LABEL -#define CONFIG_SPI_5_IRQ DT_ST_STM32_SPI_40015000_IRQ_0 +#define DT_SPI_5_IRQ DT_ST_STM32_SPI_40015000_IRQ_0 -#define CONFIG_SPI_6_BASE_ADDRESS DT_ST_STM32_SPI_40015400_BASE_ADDRESS -#define CONFIG_SPI_6_IRQ_PRI DT_ST_STM32_SPI_40015400_IRQ_0_PRIORITY -#define CONFIG_SPI_6_NAME DT_ST_STM32_SPI_40015400_LABEL -#define CONFIG_SPI_6_IRQ DT_ST_STM32_SPI_40015400_IRQ_0 +#define DT_SPI_6_BASE_ADDRESS DT_ST_STM32_SPI_40015400_BASE_ADDRESS +#define DT_SPI_6_IRQ_PRI DT_ST_STM32_SPI_40015400_IRQ_0_PRIORITY +#define DT_SPI_6_NAME DT_ST_STM32_SPI_40015400_LABEL +#define DT_SPI_6_IRQ DT_ST_STM32_SPI_40015400_IRQ_0 #ifdef DT_ST_STM32_OTGFS_50000000_BASE_ADDRESS -#define CONFIG_USB_BASE_ADDRESS DT_ST_STM32_OTGFS_50000000_BASE_ADDRESS -#define CONFIG_USB_IRQ DT_ST_STM32_OTGFS_50000000_IRQ_OTGFS -#define CONFIG_USB_IRQ_PRI DT_ST_STM32_OTGFS_50000000_IRQ_OTGFS_PRIORITY -#define CONFIG_USB_NUM_BIDIR_ENDPOINTS DT_ST_STM32_OTGFS_50000000_NUM_BIDIR_ENDPOINTS -#define CONFIG_USB_RAM_SIZE DT_ST_STM32_OTGFS_50000000_RAM_SIZE -#define CONFIG_USB_MAXIMUM_SPEED DT_ST_STM32_OTGFS_50000000_MAXIMUM_SPEED +#define DT_USB_BASE_ADDRESS DT_ST_STM32_OTGFS_50000000_BASE_ADDRESS +#define DT_USB_IRQ DT_ST_STM32_OTGFS_50000000_IRQ_OTGFS +#define DT_USB_IRQ_PRI DT_ST_STM32_OTGFS_50000000_IRQ_OTGFS_PRIORITY +#define DT_USB_NUM_BIDIR_ENDPOINTS DT_ST_STM32_OTGFS_50000000_NUM_BIDIR_ENDPOINTS +#define DT_USB_RAM_SIZE DT_ST_STM32_OTGFS_50000000_RAM_SIZE +#define DT_USB_MAXIMUM_SPEED DT_ST_STM32_OTGFS_50000000_MAXIMUM_SPEED #endif /* DT_ST_STM32_OTGFS_50000000_BASE_ADDRESS */ #ifdef DT_ST_STM32_OTGHS_40040000_BASE_ADDRESS -#define CONFIG_USB_HS_BASE_ADDRESS DT_ST_STM32_OTGHS_40040000_BASE_ADDRESS -#define CONFIG_USB_IRQ DT_ST_STM32_OTGHS_40040000_IRQ_OTGHS -#define CONFIG_USB_IRQ_PRI DT_ST_STM32_OTGHS_40040000_IRQ_OTGHS_PRIORITY -#define CONFIG_USB_NUM_BIDIR_ENDPOINTS DT_ST_STM32_OTGHS_40040000_NUM_BIDIR_ENDPOINTS -#define CONFIG_USB_RAM_SIZE DT_ST_STM32_OTGHS_40040000_RAM_SIZE -#define CONFIG_USB_MAXIMUM_SPEED DT_ST_STM32_OTGHS_40040000_MAXIMUM_SPEED +#define DT_USB_HS_BASE_ADDRESS DT_ST_STM32_OTGHS_40040000_BASE_ADDRESS +#define DT_USB_IRQ DT_ST_STM32_OTGHS_40040000_IRQ_OTGHS +#define DT_USB_IRQ_PRI DT_ST_STM32_OTGHS_40040000_IRQ_OTGHS_PRIORITY +#define DT_USB_NUM_BIDIR_ENDPOINTS DT_ST_STM32_OTGHS_40040000_NUM_BIDIR_ENDPOINTS +#define DT_USB_RAM_SIZE DT_ST_STM32_OTGHS_40040000_RAM_SIZE +#define DT_USB_MAXIMUM_SPEED DT_ST_STM32_OTGHS_40040000_MAXIMUM_SPEED #endif /* DT_ST_STM32_OTGHS_40040000_BASE_ADDRESS */ -#define CONFIG_PWM_STM32_1_DEV_NAME DT_ST_STM32_PWM_40010000_PWM_LABEL -#define CONFIG_PWM_STM32_1_PRESCALER DT_ST_STM32_PWM_40010000_PWM_ST_PRESCALER +#define DT_PWM_STM32_1_DEV_NAME DT_ST_STM32_PWM_40010000_PWM_LABEL +#define DT_PWM_STM32_1_PRESCALER DT_ST_STM32_PWM_40010000_PWM_ST_PRESCALER -#define CONFIG_PWM_STM32_2_DEV_NAME DT_ST_STM32_PWM_40000000_PWM_LABEL -#define CONFIG_PWM_STM32_2_PRESCALER DT_ST_STM32_PWM_40000000_PWM_ST_PRESCALER +#define DT_PWM_STM32_2_DEV_NAME DT_ST_STM32_PWM_40000000_PWM_LABEL +#define DT_PWM_STM32_2_PRESCALER DT_ST_STM32_PWM_40000000_PWM_ST_PRESCALER -#define CONFIG_PWM_STM32_3_DEV_NAME DT_ST_STM32_PWM_40000400_PWM_LABEL -#define CONFIG_PWM_STM32_3_PRESCALER DT_ST_STM32_PWM_40000400_PWM_ST_PRESCALER +#define DT_PWM_STM32_3_DEV_NAME DT_ST_STM32_PWM_40000400_PWM_LABEL +#define DT_PWM_STM32_3_PRESCALER DT_ST_STM32_PWM_40000400_PWM_ST_PRESCALER -#define CONFIG_PWM_STM32_4_DEV_NAME DT_ST_STM32_PWM_40000800_PWM_LABEL -#define CONFIG_PWM_STM32_4_PRESCALER DT_ST_STM32_PWM_40000800_PWM_ST_PRESCALER +#define DT_PWM_STM32_4_DEV_NAME DT_ST_STM32_PWM_40000800_PWM_LABEL +#define DT_PWM_STM32_4_PRESCALER DT_ST_STM32_PWM_40000800_PWM_ST_PRESCALER -#define CONFIG_PWM_STM32_5_DEV_NAME DT_ST_STM32_PWM_40000C00_PWM_LABEL -#define CONFIG_PWM_STM32_5_PRESCALER DT_ST_STM32_PWM_40000C00_PWM_ST_PRESCALER +#define DT_PWM_STM32_5_DEV_NAME DT_ST_STM32_PWM_40000C00_PWM_LABEL +#define DT_PWM_STM32_5_PRESCALER DT_ST_STM32_PWM_40000C00_PWM_ST_PRESCALER -#define CONFIG_PWM_STM32_6_DEV_NAME DT_ST_STM32_PWM_40001000_PWM_LABEL -#define CONFIG_PWM_STM32_6_PRESCALER DT_ST_STM32_PWM_40001000_PWM_ST_PRESCALER +#define DT_PWM_STM32_6_DEV_NAME DT_ST_STM32_PWM_40001000_PWM_LABEL +#define DT_PWM_STM32_6_PRESCALER DT_ST_STM32_PWM_40001000_PWM_ST_PRESCALER -#define CONFIG_PWM_STM32_7_DEV_NAME DT_ST_STM32_PWM_40001400_PWM_LABEL -#define CONFIG_PWM_STM32_7_PRESCALER DT_ST_STM32_PWM_40001400_PWM_ST_PRESCALER +#define DT_PWM_STM32_7_DEV_NAME DT_ST_STM32_PWM_40001400_PWM_LABEL +#define DT_PWM_STM32_7_PRESCALER DT_ST_STM32_PWM_40001400_PWM_ST_PRESCALER -#define CONFIG_PWM_STM32_8_DEV_NAME DT_ST_STM32_PWM_40010400_PWM_LABEL -#define CONFIG_PWM_STM32_8_PRESCALER DT_ST_STM32_PWM_40010400_PWM_ST_PRESCALER +#define DT_PWM_STM32_8_DEV_NAME DT_ST_STM32_PWM_40010400_PWM_LABEL +#define DT_PWM_STM32_8_PRESCALER DT_ST_STM32_PWM_40010400_PWM_ST_PRESCALER -#define CONFIG_PWM_STM32_9_DEV_NAME DT_ST_STM32_PWM_40014000_PWM_LABEL -#define CONFIG_PWM_STM32_9_PRESCALER DT_ST_STM32_PWM_40014000_PWM_ST_PRESCALER +#define DT_PWM_STM32_9_DEV_NAME DT_ST_STM32_PWM_40014000_PWM_LABEL +#define DT_PWM_STM32_9_PRESCALER DT_ST_STM32_PWM_40014000_PWM_ST_PRESCALER -#define CONFIG_PWM_STM32_10_DEV_NAME DT_ST_STM32_PWM_40014400_PWM_LABEL -#define CONFIG_PWM_STM32_10_PRESCALER DT_ST_STM32_PWM_40014400_PWM_ST_PRESCALER +#define DT_PWM_STM32_10_DEV_NAME DT_ST_STM32_PWM_40014400_PWM_LABEL +#define DT_PWM_STM32_10_PRESCALER DT_ST_STM32_PWM_40014400_PWM_ST_PRESCALER -#define CONFIG_PWM_STM32_11_DEV_NAME DT_ST_STM32_PWM_40014800_PWM_LABEL -#define CONFIG_PWM_STM32_11_PRESCALER DT_ST_STM32_PWM_40014800_PWM_ST_PRESCALER +#define DT_PWM_STM32_11_DEV_NAME DT_ST_STM32_PWM_40014800_PWM_LABEL +#define DT_PWM_STM32_11_PRESCALER DT_ST_STM32_PWM_40014800_PWM_ST_PRESCALER -#define CONFIG_PWM_STM32_12_DEV_NAME DT_ST_STM32_PWM_40001800_PWM_LABEL -#define CONFIG_PWM_STM32_12_PRESCALER DT_ST_STM32_PWM_40001800_PWM_ST_PRESCALER +#define DT_PWM_STM32_12_DEV_NAME DT_ST_STM32_PWM_40001800_PWM_LABEL +#define DT_PWM_STM32_12_PRESCALER DT_ST_STM32_PWM_40001800_PWM_ST_PRESCALER -#define CONFIG_PWM_STM32_13_DEV_NAME DT_ST_STM32_PWM_40001C00_PWM_LABEL -#define CONFIG_PWM_STM32_13_PRESCALER DT_ST_STM32_PWM_40001C00_PWM_ST_PRESCALER +#define DT_PWM_STM32_13_DEV_NAME DT_ST_STM32_PWM_40001C00_PWM_LABEL +#define DT_PWM_STM32_13_PRESCALER DT_ST_STM32_PWM_40001C00_PWM_ST_PRESCALER -#define CONFIG_PWM_STM32_14_DEV_NAME DT_ST_STM32_PWM_40002000_PWM_LABEL -#define CONFIG_PWM_STM32_14_PRESCALER DT_ST_STM32_PWM_40002000_PWM_ST_PRESCALER +#define DT_PWM_STM32_14_DEV_NAME DT_ST_STM32_PWM_40002000_PWM_LABEL +#define DT_PWM_STM32_14_PRESCALER DT_ST_STM32_PWM_40002000_PWM_ST_PRESCALER -#define CONFIG_RTC_0_BASE_ADDRESS DT_ST_STM32_RTC_40002800_BASE_ADDRESS +#define DT_RTC_0_BASE_ADDRESS DT_ST_STM32_RTC_40002800_BASE_ADDRESS #define CONFIG_RTC_0_IRQ_PRI DT_ST_STM32_RTC_40002800_IRQ_0_PRIORITY -#define CONFIG_RTC_0_IRQ DT_ST_STM32_RTC_40002800_IRQ_0 +#define DT_RTC_0_IRQ DT_ST_STM32_RTC_40002800_IRQ_0 #define CONFIG_RTC_0_NAME DT_ST_STM32_RTC_40002800_LABEL #define CONFIG_RTC_PRESCALER DT_ST_STM32_RTC_40002800_PRESCALER diff --git a/soc/arm/st_stm32/stm32l0/dts_fixup.h b/soc/arm/st_stm32/stm32l0/dts_fixup.h index 244110441b4..7ef68be86e0 100644 --- a/soc/arm/st_stm32/stm32l0/dts_fixup.h +++ b/soc/arm/st_stm32/stm32l0/dts_fixup.h @@ -1,125 +1,125 @@ /* SoC level DTS fixup file */ -#define CONFIG_NUM_IRQ_PRIO_BITS DT_ARM_V6M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS +#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V6M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS -#define CONFIG_GPIO_STM32_GPIOA_BASE_ADDRESS DT_ST_STM32_GPIO_50000000_BASE_ADDRESS -#define CONFIG_GPIO_STM32_GPIOA_CLOCK_BITS_0 DT_ST_STM32_GPIO_50000000_CLOCK_BITS_0 -#define CONFIG_GPIO_STM32_GPIOA_CLOCK_BUS_0 DT_ST_STM32_GPIO_50000000_CLOCK_BUS_0 -#define CONFIG_GPIO_STM32_GPIOA_CLOCK_CONTROLLER DT_ST_STM32_GPIO_50000000_CLOCK_CONTROLLER -#define CONFIG_GPIO_STM32_GPIOA_LABEL DT_ST_STM32_GPIO_50000000_LABEL -#define CONFIG_GPIO_STM32_GPIOA_SIZE DT_ST_STM32_GPIO_50000000_SIZE -#define CONFIG_GPIO_STM32_GPIOA_CLOCK_BITS DT_ST_STM32_GPIO_50000000_CLOCK_BITS -#define CONFIG_GPIO_STM32_GPIOA_CLOCK_BUS DT_ST_STM32_GPIO_50000000_CLOCK_BUS +#define DT_GPIO_STM32_GPIOA_BASE_ADDRESS DT_ST_STM32_GPIO_50000000_BASE_ADDRESS +#define DT_GPIO_STM32_GPIOA_CLOCK_BITS_0 DT_ST_STM32_GPIO_50000000_CLOCK_BITS_0 +#define DT_GPIO_STM32_GPIOA_CLOCK_BUS_0 DT_ST_STM32_GPIO_50000000_CLOCK_BUS_0 +#define DT_GPIO_STM32_GPIOA_CLOCK_CONTROLLER DT_ST_STM32_GPIO_50000000_CLOCK_CONTROLLER +#define DT_GPIO_STM32_GPIOA_LABEL DT_ST_STM32_GPIO_50000000_LABEL +#define DT_GPIO_STM32_GPIOA_SIZE DT_ST_STM32_GPIO_50000000_SIZE +#define DT_GPIO_STM32_GPIOA_CLOCK_BITS DT_ST_STM32_GPIO_50000000_CLOCK_BITS +#define DT_GPIO_STM32_GPIOA_CLOCK_BUS DT_ST_STM32_GPIO_50000000_CLOCK_BUS -#define CONFIG_GPIO_STM32_GPIOB_BASE_ADDRESS DT_ST_STM32_GPIO_50000400_BASE_ADDRESS -#define CONFIG_GPIO_STM32_GPIOB_CLOCK_BITS_0 DT_ST_STM32_GPIO_50000400_CLOCK_BITS_0 -#define CONFIG_GPIO_STM32_GPIOB_CLOCK_BUS_0 DT_ST_STM32_GPIO_50000400_CLOCK_BUS_0 -#define CONFIG_GPIO_STM32_GPIOB_CLOCK_CONTROLLER DT_ST_STM32_GPIO_50000400_CLOCK_CONTROLLER -#define CONFIG_GPIO_STM32_GPIOB_LABEL DT_ST_STM32_GPIO_50000400_LABEL -#define CONFIG_GPIO_STM32_GPIOB_SIZE DT_ST_STM32_GPIO_50000400_SIZE -#define CONFIG_GPIO_STM32_GPIOB_CLOCK_BITS DT_ST_STM32_GPIO_50000400_CLOCK_BITS -#define CONFIG_GPIO_STM32_GPIOB_CLOCK_BUS DT_ST_STM32_GPIO_50000400_CLOCK_BUS +#define DT_GPIO_STM32_GPIOB_BASE_ADDRESS DT_ST_STM32_GPIO_50000400_BASE_ADDRESS +#define DT_GPIO_STM32_GPIOB_CLOCK_BITS_0 DT_ST_STM32_GPIO_50000400_CLOCK_BITS_0 +#define DT_GPIO_STM32_GPIOB_CLOCK_BUS_0 DT_ST_STM32_GPIO_50000400_CLOCK_BUS_0 +#define DT_GPIO_STM32_GPIOB_CLOCK_CONTROLLER DT_ST_STM32_GPIO_50000400_CLOCK_CONTROLLER +#define DT_GPIO_STM32_GPIOB_LABEL DT_ST_STM32_GPIO_50000400_LABEL +#define DT_GPIO_STM32_GPIOB_SIZE DT_ST_STM32_GPIO_50000400_SIZE +#define DT_GPIO_STM32_GPIOB_CLOCK_BITS DT_ST_STM32_GPIO_50000400_CLOCK_BITS +#define DT_GPIO_STM32_GPIOB_CLOCK_BUS DT_ST_STM32_GPIO_50000400_CLOCK_BUS -#define CONFIG_GPIO_STM32_GPIOC_BASE_ADDRESS DT_ST_STM32_GPIO_50000800_BASE_ADDRESS -#define CONFIG_GPIO_STM32_GPIOC_CLOCK_BITS_0 DT_ST_STM32_GPIO_50000800_CLOCK_BITS_0 -#define CONFIG_GPIO_STM32_GPIOC_CLOCK_BUS_0 DT_ST_STM32_GPIO_50000800_CLOCK_BUS_0 -#define CONFIG_GPIO_STM32_GPIOC_CLOCK_CONTROLLER DT_ST_STM32_GPIO_50000800_CLOCK_CONTROLLER -#define CONFIG_GPIO_STM32_GPIOC_LABEL DT_ST_STM32_GPIO_50000800_LABEL -#define CONFIG_GPIO_STM32_GPIOC_SIZE DT_ST_STM32_GPIO_50000800_SIZE -#define CONFIG_GPIO_STM32_GPIOC_CLOCK_BITS DT_ST_STM32_GPIO_50000800_CLOCK_BITS -#define CONFIG_GPIO_STM32_GPIOC_CLOCK_BUS DT_ST_STM32_GPIO_50000800_CLOCK_BUS +#define DT_GPIO_STM32_GPIOC_BASE_ADDRESS DT_ST_STM32_GPIO_50000800_BASE_ADDRESS +#define DT_GPIO_STM32_GPIOC_CLOCK_BITS_0 DT_ST_STM32_GPIO_50000800_CLOCK_BITS_0 +#define DT_GPIO_STM32_GPIOC_CLOCK_BUS_0 DT_ST_STM32_GPIO_50000800_CLOCK_BUS_0 +#define DT_GPIO_STM32_GPIOC_CLOCK_CONTROLLER DT_ST_STM32_GPIO_50000800_CLOCK_CONTROLLER +#define DT_GPIO_STM32_GPIOC_LABEL DT_ST_STM32_GPIO_50000800_LABEL +#define DT_GPIO_STM32_GPIOC_SIZE DT_ST_STM32_GPIO_50000800_SIZE +#define DT_GPIO_STM32_GPIOC_CLOCK_BITS DT_ST_STM32_GPIO_50000800_CLOCK_BITS +#define DT_GPIO_STM32_GPIOC_CLOCK_BUS DT_ST_STM32_GPIO_50000800_CLOCK_BUS -#define CONFIG_GPIO_STM32_GPIOD_BASE_ADDRESS DT_ST_STM32_GPIO_50000C00_BASE_ADDRESS -#define CONFIG_GPIO_STM32_GPIOD_CLOCK_BITS_0 DT_ST_STM32_GPIO_50000C00_CLOCK_BITS_0 -#define CONFIG_GPIO_STM32_GPIOD_CLOCK_BUS_0 DT_ST_STM32_GPIO_50000C00_CLOCK_BUS_0 -#define CONFIG_GPIO_STM32_GPIOD_CLOCK_CONTROLLER DT_ST_STM32_GPIO_50000C00_CLOCK_CONTROLLER -#define CONFIG_GPIO_STM32_GPIOD_LABEL DT_ST_STM32_GPIO_50000C00_LABEL -#define CONFIG_GPIO_STM32_GPIOD_SIZE DT_ST_STM32_GPIO_50000C00_SIZE -#define CONFIG_GPIO_STM32_GPIOD_CLOCK_BITS DT_ST_STM32_GPIO_50000C00_CLOCK_BITS -#define CONFIG_GPIO_STM32_GPIOD_CLOCK_BUS DT_ST_STM32_GPIO_50000C00_CLOCK_BUS +#define DT_GPIO_STM32_GPIOD_BASE_ADDRESS DT_ST_STM32_GPIO_50000C00_BASE_ADDRESS +#define DT_GPIO_STM32_GPIOD_CLOCK_BITS_0 DT_ST_STM32_GPIO_50000C00_CLOCK_BITS_0 +#define DT_GPIO_STM32_GPIOD_CLOCK_BUS_0 DT_ST_STM32_GPIO_50000C00_CLOCK_BUS_0 +#define DT_GPIO_STM32_GPIOD_CLOCK_CONTROLLER DT_ST_STM32_GPIO_50000C00_CLOCK_CONTROLLER +#define DT_GPIO_STM32_GPIOD_LABEL DT_ST_STM32_GPIO_50000C00_LABEL +#define DT_GPIO_STM32_GPIOD_SIZE DT_ST_STM32_GPIO_50000C00_SIZE +#define DT_GPIO_STM32_GPIOD_CLOCK_BITS DT_ST_STM32_GPIO_50000C00_CLOCK_BITS +#define DT_GPIO_STM32_GPIOD_CLOCK_BUS DT_ST_STM32_GPIO_50000C00_CLOCK_BUS -#define CONFIG_GPIO_STM32_GPIOE_BASE_ADDRESS DT_ST_STM32_GPIO_50001000_BASE_ADDRESS -#define CONFIG_GPIO_STM32_GPIOE_CLOCK_BITS_0 DT_ST_STM32_GPIO_50001000_CLOCK_BITS_0 -#define CONFIG_GPIO_STM32_GPIOE_CLOCK_BUS_0 DT_ST_STM32_GPIO_50001000_CLOCK_BUS_0 -#define CONFIG_GPIO_STM32_GPIOE_CLOCK_CONTROLLER DT_ST_STM32_GPIO_50001000_CLOCK_CONTROLLER -#define CONFIG_GPIO_STM32_GPIOE_LABEL DT_ST_STM32_GPIO_50001000_LABEL -#define CONFIG_GPIO_STM32_GPIOE_SIZE DT_ST_STM32_GPIO_50001000_SIZE -#define CONFIG_GPIO_STM32_GPIOE_CLOCK_BITS DT_ST_STM32_GPIO_50001000_CLOCK_BITS -#define CONFIG_GPIO_STM32_GPIOE_CLOCK_BUS DT_ST_STM32_GPIO_50001000_CLOCK_BUS +#define DT_GPIO_STM32_GPIOE_BASE_ADDRESS DT_ST_STM32_GPIO_50001000_BASE_ADDRESS +#define DT_GPIO_STM32_GPIOE_CLOCK_BITS_0 DT_ST_STM32_GPIO_50001000_CLOCK_BITS_0 +#define DT_GPIO_STM32_GPIOE_CLOCK_BUS_0 DT_ST_STM32_GPIO_50001000_CLOCK_BUS_0 +#define DT_GPIO_STM32_GPIOE_CLOCK_CONTROLLER DT_ST_STM32_GPIO_50001000_CLOCK_CONTROLLER +#define DT_GPIO_STM32_GPIOE_LABEL DT_ST_STM32_GPIO_50001000_LABEL +#define DT_GPIO_STM32_GPIOE_SIZE DT_ST_STM32_GPIO_50001000_SIZE +#define DT_GPIO_STM32_GPIOE_CLOCK_BITS DT_ST_STM32_GPIO_50001000_CLOCK_BITS +#define DT_GPIO_STM32_GPIOE_CLOCK_BUS DT_ST_STM32_GPIO_50001000_CLOCK_BUS /* there is no reference to GPIOF and GPIOG in the dts files */ -#define CONFIG_GPIO_STM32_GPIOH_BASE_ADDRESS DT_ST_STM32_GPIO_50001C00_BASE_ADDRESS -#define CONFIG_GPIO_STM32_GPIOH_CLOCK_BITS_0 DT_ST_STM32_GPIO_50001C00_CLOCK_BITS_0 -#define CONFIG_GPIO_STM32_GPIOH_CLOCK_BUS_0 DT_ST_STM32_GPIO_50001C00_CLOCK_BUS_0 -#define CONFIG_GPIO_STM32_GPIOH_CLOCK_CONTROLLER DT_ST_STM32_GPIO_50001C00_CLOCK_CONTROLLER -#define CONFIG_GPIO_STM32_GPIOH_LABEL DT_ST_STM32_GPIO_50001C00_LABEL -#define CONFIG_GPIO_STM32_GPIOH_SIZE DT_ST_STM32_GPIO_50001C00_SIZE -#define CONFIG_GPIO_STM32_GPIOH_CLOCK_BITS DT_ST_STM32_GPIO_50001C00_CLOCK_BITS -#define CONFIG_GPIO_STM32_GPIOH_CLOCK_BUS DT_ST_STM32_GPIO_50001C00_CLOCK_BUS +#define DT_GPIO_STM32_GPIOH_BASE_ADDRESS DT_ST_STM32_GPIO_50001C00_BASE_ADDRESS +#define DT_GPIO_STM32_GPIOH_CLOCK_BITS_0 DT_ST_STM32_GPIO_50001C00_CLOCK_BITS_0 +#define DT_GPIO_STM32_GPIOH_CLOCK_BUS_0 DT_ST_STM32_GPIO_50001C00_CLOCK_BUS_0 +#define DT_GPIO_STM32_GPIOH_CLOCK_CONTROLLER DT_ST_STM32_GPIO_50001C00_CLOCK_CONTROLLER +#define DT_GPIO_STM32_GPIOH_LABEL DT_ST_STM32_GPIO_50001C00_LABEL +#define DT_GPIO_STM32_GPIOH_SIZE DT_ST_STM32_GPIO_50001C00_SIZE +#define DT_GPIO_STM32_GPIOH_CLOCK_BITS DT_ST_STM32_GPIO_50001C00_CLOCK_BITS +#define DT_GPIO_STM32_GPIOH_CLOCK_BUS DT_ST_STM32_GPIO_50001C00_CLOCK_BUS -#define CONFIG_UART_STM32_USART_1_BASE_ADDRESS DT_ST_STM32_USART_40013800_BASE_ADDRESS -#define CONFIG_UART_STM32_USART_1_BAUD_RATE DT_ST_STM32_USART_40013800_CURRENT_SPEED -#define CONFIG_UART_STM32_USART_1_IRQ_PRI DT_ST_STM32_USART_40013800_IRQ_0_PRIORITY -#define CONFIG_UART_STM32_USART_1_NAME DT_ST_STM32_USART_40013800_LABEL -#define USART_1_IRQ DT_ST_STM32_USART_40013800_IRQ_0 -#define CONFIG_UART_STM32_USART_1_CLOCK_BITS DT_ST_STM32_USART_40013800_CLOCK_BITS -#define CONFIG_UART_STM32_USART_1_CLOCK_BUS DT_ST_STM32_USART_40013800_CLOCK_BUS +#define DT_UART_STM32_USART_1_BASE_ADDRESS DT_ST_STM32_USART_40013800_BASE_ADDRESS +#define DT_UART_STM32_USART_1_BAUD_RATE DT_ST_STM32_USART_40013800_CURRENT_SPEED +#define DT_UART_STM32_USART_1_IRQ_PRI DT_ST_STM32_USART_40013800_IRQ_0_PRIORITY +#define DT_UART_STM32_USART_1_NAME DT_ST_STM32_USART_40013800_LABEL +#define DT_USART_1_IRQ DT_ST_STM32_USART_40013800_IRQ_0 +#define DT_UART_STM32_USART_1_CLOCK_BITS DT_ST_STM32_USART_40013800_CLOCK_BITS +#define DT_UART_STM32_USART_1_CLOCK_BUS DT_ST_STM32_USART_40013800_CLOCK_BUS -#define CONFIG_UART_STM32_USART_2_BASE_ADDRESS DT_ST_STM32_USART_40004400_BASE_ADDRESS -#define CONFIG_UART_STM32_USART_2_BAUD_RATE DT_ST_STM32_USART_40004400_CURRENT_SPEED -#define CONFIG_UART_STM32_USART_2_IRQ_PRI DT_ST_STM32_USART_40004400_IRQ_0_PRIORITY -#define CONFIG_UART_STM32_USART_2_NAME DT_ST_STM32_USART_40004400_LABEL -#define USART_2_IRQ DT_ST_STM32_USART_40004400_IRQ_0 -#define CONFIG_UART_STM32_USART_2_CLOCK_BITS DT_ST_STM32_USART_40004400_CLOCK_BITS -#define CONFIG_UART_STM32_USART_2_CLOCK_BUS DT_ST_STM32_USART_40004400_CLOCK_BUS +#define DT_UART_STM32_USART_2_BASE_ADDRESS DT_ST_STM32_USART_40004400_BASE_ADDRESS +#define DT_UART_STM32_USART_2_BAUD_RATE DT_ST_STM32_USART_40004400_CURRENT_SPEED +#define DT_UART_STM32_USART_2_IRQ_PRI DT_ST_STM32_USART_40004400_IRQ_0_PRIORITY +#define DT_UART_STM32_USART_2_NAME DT_ST_STM32_USART_40004400_LABEL +#define DT_USART_2_IRQ DT_ST_STM32_USART_40004400_IRQ_0 +#define DT_UART_STM32_USART_2_CLOCK_BITS DT_ST_STM32_USART_40004400_CLOCK_BITS +#define DT_UART_STM32_USART_2_CLOCK_BUS DT_ST_STM32_USART_40004400_CLOCK_BUS -#define CONFIG_UART_STM32_LPUART_1_BASE_ADDRESS DT_ST_STM32_LPUART_40004800_BASE_ADDRESS -#define CONFIG_UART_STM32_LPUART_1_BAUD_RATE DT_ST_STM32_LPUART_40004800_CURRENT_SPEED -#define CONFIG_UART_STM32_LPUART_1_IRQ_PRI DT_ST_STM32_LPUART_40004800_IRQ_0_PRIORITY -#define CONFIG_UART_STM32_LPUART_1_NAME DT_ST_STM32_LPUART_40004800_LABEL -#define LPUART_1_IRQ DT_ST_STM32_LPUART_40004800_IRQ_0 -#define CONFIG_UART_STM32_LPUART_1_CLOCK_BITS DT_ST_STM32_LPUART_40004800_CLOCK_BITS -#define CONFIG_UART_STM32_LPUART_1_CLOCK_BUS DT_ST_STM32_LPUART_40004800_CLOCK_BUS +#define DT_UART_STM32_LPUART_1_BASE_ADDRESS DT_ST_STM32_LPUART_40004800_BASE_ADDRESS +#define DT_UART_STM32_LPUART_1_BAUD_RATE DT_ST_STM32_LPUART_40004800_CURRENT_SPEED +#define DT_UART_STM32_LPUART_1_IRQ_PRI DT_ST_STM32_LPUART_40004800_IRQ_0_PRIORITY +#define DT_UART_STM32_LPUART_1_NAME DT_ST_STM32_LPUART_40004800_LABEL +#define DT_LPUART_1_IRQ DT_ST_STM32_LPUART_40004800_IRQ_0 +#define DT_UART_STM32_LPUART_1_CLOCK_BITS DT_ST_STM32_LPUART_40004800_CLOCK_BITS +#define DT_UART_STM32_LPUART_1_CLOCK_BUS DT_ST_STM32_LPUART_40004800_CLOCK_BUS -#define CONFIG_I2C_1_BASE_ADDRESS DT_ST_STM32_I2C_V2_40005400_BASE_ADDRESS -#define CONFIG_I2C_1_COMBINED_IRQ_PRI DT_ST_STM32_I2C_V2_40005400_IRQ_COMBINED_PRIORITY +#define DT_I2C_1_BASE_ADDRESS DT_ST_STM32_I2C_V2_40005400_BASE_ADDRESS +#define DT_I2C_1_COMBINED_IRQ_PRI DT_ST_STM32_I2C_V2_40005400_IRQ_COMBINED_PRIORITY #define CONFIG_I2C_1_NAME DT_ST_STM32_I2C_V2_40005400_LABEL -#define CONFIG_I2C_1_COMBINED_IRQ DT_ST_STM32_I2C_V2_40005400_IRQ_COMBINED -#define CONFIG_I2C_1_BITRATE DT_ST_STM32_I2C_V2_40005400_CLOCK_FREQUENCY -#define CONFIG_I2C_1_CLOCK_BITS DT_ST_STM32_I2C_V2_40005400_CLOCK_BITS -#define CONFIG_I2C_1_CLOCK_BUS DT_ST_STM32_I2C_V2_40005400_CLOCK_BUS +#define DT_I2C_1_COMBINED_IRQ DT_ST_STM32_I2C_V2_40005400_IRQ_COMBINED +#define DT_I2C_1_BITRATE DT_ST_STM32_I2C_V2_40005400_CLOCK_FREQUENCY +#define DT_I2C_1_CLOCK_BITS DT_ST_STM32_I2C_V2_40005400_CLOCK_BITS +#define DT_I2C_1_CLOCK_BUS DT_ST_STM32_I2C_V2_40005400_CLOCK_BUS -#define CONFIG_I2C_2_BASE_ADDRESS DT_ST_STM32_I2C_V2_40005800_BASE_ADDRESS -#define CONFIG_I2C_2_COMBINED_IRQ_PRI DT_ST_STM32_I2C_V2_40005800_IRQ_COMBINED_PRIORITY +#define DT_I2C_2_BASE_ADDRESS DT_ST_STM32_I2C_V2_40005800_BASE_ADDRESS +#define DT_I2C_2_COMBINED_IRQ_PRI DT_ST_STM32_I2C_V2_40005800_IRQ_COMBINED_PRIORITY #define CONFIG_I2C_2_NAME DT_ST_STM32_I2C_V2_40005800_LABEL -#define CONFIG_I2C_2_COMBINED_IRQ DT_ST_STM32_I2C_V2_40005800_IRQ_COMBINED -#define CONFIG_I2C_2_BITRATE DT_ST_STM32_I2C_V2_40005800_CLOCK_FREQUENCY -#define CONFIG_I2C_2_CLOCK_BITS DT_ST_STM32_I2C_V2_40005800_CLOCK_BITS -#define CONFIG_I2C_2_CLOCK_BUS DT_ST_STM32_I2C_V2_40005800_CLOCK_BUS +#define DT_I2C_2_COMBINED_IRQ DT_ST_STM32_I2C_V2_40005800_IRQ_COMBINED +#define DT_I2C_2_BITRATE DT_ST_STM32_I2C_V2_40005800_CLOCK_FREQUENCY +#define DT_I2C_2_CLOCK_BITS DT_ST_STM32_I2C_V2_40005800_CLOCK_BITS +#define DT_I2C_2_CLOCK_BUS DT_ST_STM32_I2C_V2_40005800_CLOCK_BUS -#define CONFIG_I2C_3_BASE_ADDRESS DT_ST_STM32_I2C_V2_40007800_BASE_ADDRESS -#define CONFIG_I2C_3_COMBINED_IRQ_PRI DT_ST_STM32_I2C_V2_40007800_IRQ_COMBINED_PRIORITY +#define DT_I2C_3_BASE_ADDRESS DT_ST_STM32_I2C_V2_40007800_BASE_ADDRESS +#define DT_I2C_3_COMBINED_IRQ_PRI DT_ST_STM32_I2C_V2_40007800_IRQ_COMBINED_PRIORITY #define CONFIG_I2C_3_NAME DT_ST_STM32_I2C_V2_40007800_LABEL -#define CONFIG_I2C_3_COMBINED_IRQ DT_ST_STM32_I2C_V2_40007800_IRQ_COMBINED -#define CONFIG_I2C_3_BITRATE DT_ST_STM32_I2C_V2_40007800_CLOCK_FREQUENCY -#define CONFIG_I2C_3_CLOCK_BITS DT_ST_STM32_I2C_V2_40007800_CLOCK_BITS -#define CONFIG_I2C_3_CLOCK_BUS DT_ST_STM32_I2C_V2_40007800_CLOCK_BUS +#define DT_I2C_3_COMBINED_IRQ DT_ST_STM32_I2C_V2_40007800_IRQ_COMBINED +#define DT_I2C_3_BITRATE DT_ST_STM32_I2C_V2_40007800_CLOCK_FREQUENCY +#define DT_I2C_3_CLOCK_BITS DT_ST_STM32_I2C_V2_40007800_CLOCK_BITS +#define DT_I2C_3_CLOCK_BUS DT_ST_STM32_I2C_V2_40007800_CLOCK_BUS -#define CONFIG_SPI_1_BASE_ADDRESS DT_ST_STM32_SPI_40013000_BASE_ADDRESS +#define DT_SPI_1_BASE_ADDRESS DT_ST_STM32_SPI_40013000_BASE_ADDRESS #define CONFIG_SPI_1_IRQ_PRI DT_ST_STM32_SPI_40013000_IRQ_0_PRIORITY #define CONFIG_SPI_1_NAME DT_ST_STM32_SPI_40013000_LABEL -#define CONFIG_SPI_1_IRQ DT_ST_STM32_SPI_40013000_IRQ_0 +#define DT_SPI_1_IRQ DT_ST_STM32_SPI_40013000_IRQ_0 -#define CONFIG_SPI_2_BASE_ADDRESS DT_ST_STM32_SPI_40003800_BASE_ADDRESS +#define DT_SPI_2_BASE_ADDRESS DT_ST_STM32_SPI_40003800_BASE_ADDRESS #define CONFIG_SPI_2_IRQ_PRI DT_ST_STM32_SPI_40003800_IRQ_0_PRIORITY #define CONFIG_SPI_2_NAME DT_ST_STM32_SPI_40003800_LABEL -#define CONFIG_SPI_2_IRQ DT_ST_STM32_SPI_40003800_IRQ_0 +#define DT_SPI_2_IRQ DT_ST_STM32_SPI_40003800_IRQ_0 -#define CONFIG_USB_BASE_ADDRESS DT_ST_STM32_USB_40005C00_BASE_ADDRESS -#define CONFIG_USB_IRQ DT_ST_STM32_USB_40005C00_IRQ_USB -#define CONFIG_USB_IRQ_PRI DT_ST_STM32_USB_40005C00_IRQ_USB_PRIORITY -#define CONFIG_USB_NUM_BIDIR_ENDPOINTS DT_ST_STM32_USB_40005C00_NUM_BIDIR_ENDPOINTS -#define CONFIG_USB_RAM_SIZE DT_ST_STM32_USB_40005C00_RAM_SIZE +#define DT_USB_BASE_ADDRESS DT_ST_STM32_USB_40005C00_BASE_ADDRESS +#define DT_USB_IRQ DT_ST_STM32_USB_40005C00_IRQ_USB +#define DT_USB_IRQ_PRI DT_ST_STM32_USB_40005C00_IRQ_USB_PRIORITY +#define DT_USB_NUM_BIDIR_ENDPOINTS DT_ST_STM32_USB_40005C00_NUM_BIDIR_ENDPOINTS +#define DT_USB_RAM_SIZE DT_ST_STM32_USB_40005C00_RAM_SIZE /* End of SoC Level DTS fixup file */ diff --git a/soc/arm/st_stm32/stm32l4/dts_fixup.h b/soc/arm/st_stm32/stm32l4/dts_fixup.h index d6b35c7554a..e6f55727e44 100644 --- a/soc/arm/st_stm32/stm32l4/dts_fixup.h +++ b/soc/arm/st_stm32/stm32l4/dts_fixup.h @@ -1,262 +1,262 @@ /* SoC level DTS fixup file */ -#define CONFIG_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS +#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS -#define CONFIG_GPIO_STM32_GPIOA_BASE_ADDRESS DT_ST_STM32_GPIO_48000000_BASE_ADDRESS -#define CONFIG_GPIO_STM32_GPIOA_CLOCK_BITS_0 DT_ST_STM32_GPIO_48000000_CLOCK_BITS_0 -#define CONFIG_GPIO_STM32_GPIOA_CLOCK_BUS_0 DT_ST_STM32_GPIO_48000000_CLOCK_BUS_0 -#define CONFIG_GPIO_STM32_GPIOA_CLOCK_CONTROLLER DT_ST_STM32_GPIO_48000000_CLOCK_CONTROLLER -#define CONFIG_GPIO_STM32_GPIOA_LABEL DT_ST_STM32_GPIO_48000000_LABEL -#define CONFIG_GPIO_STM32_GPIOA_SIZE DT_ST_STM32_GPIO_48000000_SIZE -#define CONFIG_GPIO_STM32_GPIOA_CLOCK_BITS DT_ST_STM32_GPIO_48000000_CLOCK_BITS -#define CONFIG_GPIO_STM32_GPIOA_CLOCK_BUS DT_ST_STM32_GPIO_48000000_CLOCK_BUS +#define DT_GPIO_STM32_GPIOA_BASE_ADDRESS DT_ST_STM32_GPIO_48000000_BASE_ADDRESS +#define DT_GPIO_STM32_GPIOA_CLOCK_BITS_0 DT_ST_STM32_GPIO_48000000_CLOCK_BITS_0 +#define DT_GPIO_STM32_GPIOA_CLOCK_BUS_0 DT_ST_STM32_GPIO_48000000_CLOCK_BUS_0 +#define DT_GPIO_STM32_GPIOA_CLOCK_CONTROLLER DT_ST_STM32_GPIO_48000000_CLOCK_CONTROLLER +#define DT_GPIO_STM32_GPIOA_LABEL DT_ST_STM32_GPIO_48000000_LABEL +#define DT_GPIO_STM32_GPIOA_SIZE DT_ST_STM32_GPIO_48000000_SIZE +#define DT_GPIO_STM32_GPIOA_CLOCK_BITS DT_ST_STM32_GPIO_48000000_CLOCK_BITS +#define DT_GPIO_STM32_GPIOA_CLOCK_BUS DT_ST_STM32_GPIO_48000000_CLOCK_BUS -#define CONFIG_GPIO_STM32_GPIOB_BASE_ADDRESS DT_ST_STM32_GPIO_48000400_BASE_ADDRESS -#define CONFIG_GPIO_STM32_GPIOB_CLOCK_BITS_0 DT_ST_STM32_GPIO_48000400_CLOCK_BITS_0 -#define CONFIG_GPIO_STM32_GPIOB_CLOCK_BUS_0 DT_ST_STM32_GPIO_48000400_CLOCK_BUS_0 -#define CONFIG_GPIO_STM32_GPIOB_CLOCK_CONTROLLER DT_ST_STM32_GPIO_48000400_CLOCK_CONTROLLER -#define CONFIG_GPIO_STM32_GPIOB_LABEL DT_ST_STM32_GPIO_48000400_LABEL -#define CONFIG_GPIO_STM32_GPIOB_SIZE DT_ST_STM32_GPIO_48000400_SIZE -#define CONFIG_GPIO_STM32_GPIOB_CLOCK_BITS DT_ST_STM32_GPIO_48000400_CLOCK_BITS -#define CONFIG_GPIO_STM32_GPIOB_CLOCK_BUS DT_ST_STM32_GPIO_48000400_CLOCK_BUS +#define DT_GPIO_STM32_GPIOB_BASE_ADDRESS DT_ST_STM32_GPIO_48000400_BASE_ADDRESS +#define DT_GPIO_STM32_GPIOB_CLOCK_BITS_0 DT_ST_STM32_GPIO_48000400_CLOCK_BITS_0 +#define DT_GPIO_STM32_GPIOB_CLOCK_BUS_0 DT_ST_STM32_GPIO_48000400_CLOCK_BUS_0 +#define DT_GPIO_STM32_GPIOB_CLOCK_CONTROLLER DT_ST_STM32_GPIO_48000400_CLOCK_CONTROLLER +#define DT_GPIO_STM32_GPIOB_LABEL DT_ST_STM32_GPIO_48000400_LABEL +#define DT_GPIO_STM32_GPIOB_SIZE DT_ST_STM32_GPIO_48000400_SIZE +#define DT_GPIO_STM32_GPIOB_CLOCK_BITS DT_ST_STM32_GPIO_48000400_CLOCK_BITS +#define DT_GPIO_STM32_GPIOB_CLOCK_BUS DT_ST_STM32_GPIO_48000400_CLOCK_BUS -#define CONFIG_GPIO_STM32_GPIOC_BASE_ADDRESS DT_ST_STM32_GPIO_48000800_BASE_ADDRESS -#define CONFIG_GPIO_STM32_GPIOC_CLOCK_BITS_0 DT_ST_STM32_GPIO_48000800_CLOCK_BITS_0 -#define CONFIG_GPIO_STM32_GPIOC_CLOCK_BUS_0 DT_ST_STM32_GPIO_48000800_CLOCK_BUS_0 -#define CONFIG_GPIO_STM32_GPIOC_CLOCK_CONTROLLER DT_ST_STM32_GPIO_48000800_CLOCK_CONTROLLER -#define CONFIG_GPIO_STM32_GPIOC_LABEL DT_ST_STM32_GPIO_48000800_LABEL -#define CONFIG_GPIO_STM32_GPIOC_SIZE DT_ST_STM32_GPIO_48000800_SIZE -#define CONFIG_GPIO_STM32_GPIOC_CLOCK_BITS DT_ST_STM32_GPIO_48000800_CLOCK_BITS -#define CONFIG_GPIO_STM32_GPIOC_CLOCK_BUS DT_ST_STM32_GPIO_48000800_CLOCK_BUS +#define DT_GPIO_STM32_GPIOC_BASE_ADDRESS DT_ST_STM32_GPIO_48000800_BASE_ADDRESS +#define DT_GPIO_STM32_GPIOC_CLOCK_BITS_0 DT_ST_STM32_GPIO_48000800_CLOCK_BITS_0 +#define DT_GPIO_STM32_GPIOC_CLOCK_BUS_0 DT_ST_STM32_GPIO_48000800_CLOCK_BUS_0 +#define DT_GPIO_STM32_GPIOC_CLOCK_CONTROLLER DT_ST_STM32_GPIO_48000800_CLOCK_CONTROLLER +#define DT_GPIO_STM32_GPIOC_LABEL DT_ST_STM32_GPIO_48000800_LABEL +#define DT_GPIO_STM32_GPIOC_SIZE DT_ST_STM32_GPIO_48000800_SIZE +#define DT_GPIO_STM32_GPIOC_CLOCK_BITS DT_ST_STM32_GPIO_48000800_CLOCK_BITS +#define DT_GPIO_STM32_GPIOC_CLOCK_BUS DT_ST_STM32_GPIO_48000800_CLOCK_BUS -#define CONFIG_GPIO_STM32_GPIOD_BASE_ADDRESS DT_ST_STM32_GPIO_48000C00_BASE_ADDRESS -#define CONFIG_GPIO_STM32_GPIOD_CLOCK_BITS_0 DT_ST_STM32_GPIO_48000C00_CLOCK_BITS_0 -#define CONFIG_GPIO_STM32_GPIOD_CLOCK_BUS_0 DT_ST_STM32_GPIO_48000C00_CLOCK_BUS_0 -#define CONFIG_GPIO_STM32_GPIOD_CLOCK_CONTROLLER DT_ST_STM32_GPIO_48000C00_CLOCK_CONTROLLER -#define CONFIG_GPIO_STM32_GPIOD_LABEL DT_ST_STM32_GPIO_48000C00_LABEL -#define CONFIG_GPIO_STM32_GPIOD_SIZE DT_ST_STM32_GPIO_48000C00_SIZE -#define CONFIG_GPIO_STM32_GPIOD_CLOCK_BITS DT_ST_STM32_GPIO_48000C00_CLOCK_BITS -#define CONFIG_GPIO_STM32_GPIOD_CLOCK_BUS DT_ST_STM32_GPIO_48000C00_CLOCK_BUS +#define DT_GPIO_STM32_GPIOD_BASE_ADDRESS DT_ST_STM32_GPIO_48000C00_BASE_ADDRESS +#define DT_GPIO_STM32_GPIOD_CLOCK_BITS_0 DT_ST_STM32_GPIO_48000C00_CLOCK_BITS_0 +#define DT_GPIO_STM32_GPIOD_CLOCK_BUS_0 DT_ST_STM32_GPIO_48000C00_CLOCK_BUS_0 +#define DT_GPIO_STM32_GPIOD_CLOCK_CONTROLLER DT_ST_STM32_GPIO_48000C00_CLOCK_CONTROLLER +#define DT_GPIO_STM32_GPIOD_LABEL DT_ST_STM32_GPIO_48000C00_LABEL +#define DT_GPIO_STM32_GPIOD_SIZE DT_ST_STM32_GPIO_48000C00_SIZE +#define DT_GPIO_STM32_GPIOD_CLOCK_BITS DT_ST_STM32_GPIO_48000C00_CLOCK_BITS +#define DT_GPIO_STM32_GPIOD_CLOCK_BUS DT_ST_STM32_GPIO_48000C00_CLOCK_BUS -#define CONFIG_GPIO_STM32_GPIOE_BASE_ADDRESS DT_ST_STM32_GPIO_48001000_BASE_ADDRESS -#define CONFIG_GPIO_STM32_GPIOE_CLOCK_BITS_0 DT_ST_STM32_GPIO_48001000_CLOCK_BITS_0 -#define CONFIG_GPIO_STM32_GPIOE_CLOCK_BUS_0 DT_ST_STM32_GPIO_48001000_CLOCK_BUS_0 -#define CONFIG_GPIO_STM32_GPIOE_CLOCK_CONTROLLER DT_ST_STM32_GPIO_48001000_CLOCK_CONTROLLER -#define CONFIG_GPIO_STM32_GPIOE_LABEL DT_ST_STM32_GPIO_48001000_LABEL -#define CONFIG_GPIO_STM32_GPIOE_SIZE DT_ST_STM32_GPIO_48001000_SIZE -#define CONFIG_GPIO_STM32_GPIOE_CLOCK_BITS DT_ST_STM32_GPIO_48001000_CLOCK_BITS -#define CONFIG_GPIO_STM32_GPIOE_CLOCK_BUS DT_ST_STM32_GPIO_48001000_CLOCK_BUS +#define DT_GPIO_STM32_GPIOE_BASE_ADDRESS DT_ST_STM32_GPIO_48001000_BASE_ADDRESS +#define DT_GPIO_STM32_GPIOE_CLOCK_BITS_0 DT_ST_STM32_GPIO_48001000_CLOCK_BITS_0 +#define DT_GPIO_STM32_GPIOE_CLOCK_BUS_0 DT_ST_STM32_GPIO_48001000_CLOCK_BUS_0 +#define DT_GPIO_STM32_GPIOE_CLOCK_CONTROLLER DT_ST_STM32_GPIO_48001000_CLOCK_CONTROLLER +#define DT_GPIO_STM32_GPIOE_LABEL DT_ST_STM32_GPIO_48001000_LABEL +#define DT_GPIO_STM32_GPIOE_SIZE DT_ST_STM32_GPIO_48001000_SIZE +#define DT_GPIO_STM32_GPIOE_CLOCK_BITS DT_ST_STM32_GPIO_48001000_CLOCK_BITS +#define DT_GPIO_STM32_GPIOE_CLOCK_BUS DT_ST_STM32_GPIO_48001000_CLOCK_BUS -#define CONFIG_GPIO_STM32_GPIOF_BASE_ADDRESS DT_ST_STM32_GPIO_48001400_BASE_ADDRESS -#define CONFIG_GPIO_STM32_GPIOF_CLOCK_BITS_0 DT_ST_STM32_GPIO_48001400_CLOCK_BITS_0 -#define CONFIG_GPIO_STM32_GPIOF_CLOCK_BUS_0 DT_ST_STM32_GPIO_48001400_CLOCK_BUS_0 -#define CONFIG_GPIO_STM32_GPIOF_CLOCK_CONTROLLER DT_ST_STM32_GPIO_48001400_CLOCK_CONTROLLER -#define CONFIG_GPIO_STM32_GPIOF_LABEL DT_ST_STM32_GPIO_48001400_LABEL -#define CONFIG_GPIO_STM32_GPIOF_SIZE DT_ST_STM32_GPIO_48001400_SIZE -#define CONFIG_GPIO_STM32_GPIOF_CLOCK_BITS DT_ST_STM32_GPIO_48001400_CLOCK_BITS -#define CONFIG_GPIO_STM32_GPIOF_CLOCK_BUS DT_ST_STM32_GPIO_48001400_CLOCK_BUS +#define DT_GPIO_STM32_GPIOF_BASE_ADDRESS DT_ST_STM32_GPIO_48001400_BASE_ADDRESS +#define DT_GPIO_STM32_GPIOF_CLOCK_BITS_0 DT_ST_STM32_GPIO_48001400_CLOCK_BITS_0 +#define DT_GPIO_STM32_GPIOF_CLOCK_BUS_0 DT_ST_STM32_GPIO_48001400_CLOCK_BUS_0 +#define DT_GPIO_STM32_GPIOF_CLOCK_CONTROLLER DT_ST_STM32_GPIO_48001400_CLOCK_CONTROLLER +#define DT_GPIO_STM32_GPIOF_LABEL DT_ST_STM32_GPIO_48001400_LABEL +#define DT_GPIO_STM32_GPIOF_SIZE DT_ST_STM32_GPIO_48001400_SIZE +#define DT_GPIO_STM32_GPIOF_CLOCK_BITS DT_ST_STM32_GPIO_48001400_CLOCK_BITS +#define DT_GPIO_STM32_GPIOF_CLOCK_BUS DT_ST_STM32_GPIO_48001400_CLOCK_BUS -#define CONFIG_GPIO_STM32_GPIOG_BASE_ADDRESS DT_ST_STM32_GPIO_48001800_BASE_ADDRESS -#define CONFIG_GPIO_STM32_GPIOG_CLOCK_BITS_0 DT_ST_STM32_GPIO_48001800_CLOCK_BITS_0 -#define CONFIG_GPIO_STM32_GPIOG_CLOCK_BUS_0 DT_ST_STM32_GPIO_48001800_CLOCK_BUS_0 -#define CONFIG_GPIO_STM32_GPIOG_CLOCK_CONTROLLER DT_ST_STM32_GPIO_48001800_CLOCK_CONTROLLER -#define CONFIG_GPIO_STM32_GPIOG_LABEL DT_ST_STM32_GPIO_48001800_LABEL -#define CONFIG_GPIO_STM32_GPIOG_SIZE DT_ST_STM32_GPIO_48001800_SIZE -#define CONFIG_GPIO_STM32_GPIOG_CLOCK_BITS DT_ST_STM32_GPIO_48001800_CLOCK_BITS -#define CONFIG_GPIO_STM32_GPIOG_CLOCK_BUS DT_ST_STM32_GPIO_48001800_CLOCK_BUS +#define DT_GPIO_STM32_GPIOG_BASE_ADDRESS DT_ST_STM32_GPIO_48001800_BASE_ADDRESS +#define DT_GPIO_STM32_GPIOG_CLOCK_BITS_0 DT_ST_STM32_GPIO_48001800_CLOCK_BITS_0 +#define DT_GPIO_STM32_GPIOG_CLOCK_BUS_0 DT_ST_STM32_GPIO_48001800_CLOCK_BUS_0 +#define DT_GPIO_STM32_GPIOG_CLOCK_CONTROLLER DT_ST_STM32_GPIO_48001800_CLOCK_CONTROLLER +#define DT_GPIO_STM32_GPIOG_LABEL DT_ST_STM32_GPIO_48001800_LABEL +#define DT_GPIO_STM32_GPIOG_SIZE DT_ST_STM32_GPIO_48001800_SIZE +#define DT_GPIO_STM32_GPIOG_CLOCK_BITS DT_ST_STM32_GPIO_48001800_CLOCK_BITS +#define DT_GPIO_STM32_GPIOG_CLOCK_BUS DT_ST_STM32_GPIO_48001800_CLOCK_BUS -#define CONFIG_GPIO_STM32_GPIOH_BASE_ADDRESS DT_ST_STM32_GPIO_48001C00_BASE_ADDRESS -#define CONFIG_GPIO_STM32_GPIOH_CLOCK_BITS_0 DT_ST_STM32_GPIO_48001C00_CLOCK_BITS_0 -#define CONFIG_GPIO_STM32_GPIOH_CLOCK_BUS_0 DT_ST_STM32_GPIO_48001C00_CLOCK_BUS_0 -#define CONFIG_GPIO_STM32_GPIOH_CLOCK_CONTROLLER DT_ST_STM32_GPIO_48001C00_CLOCK_CONTROLLER -#define CONFIG_GPIO_STM32_GPIOH_LABEL DT_ST_STM32_GPIO_48001C00_LABEL -#define CONFIG_GPIO_STM32_GPIOH_SIZE DT_ST_STM32_GPIO_48001C00_SIZE -#define CONFIG_GPIO_STM32_GPIOH_CLOCK_BITS DT_ST_STM32_GPIO_48001C00_CLOCK_BITS -#define CONFIG_GPIO_STM32_GPIOH_CLOCK_BUS DT_ST_STM32_GPIO_48001C00_CLOCK_BUS +#define DT_GPIO_STM32_GPIOH_BASE_ADDRESS DT_ST_STM32_GPIO_48001C00_BASE_ADDRESS +#define DT_GPIO_STM32_GPIOH_CLOCK_BITS_0 DT_ST_STM32_GPIO_48001C00_CLOCK_BITS_0 +#define DT_GPIO_STM32_GPIOH_CLOCK_BUS_0 DT_ST_STM32_GPIO_48001C00_CLOCK_BUS_0 +#define DT_GPIO_STM32_GPIOH_CLOCK_CONTROLLER DT_ST_STM32_GPIO_48001C00_CLOCK_CONTROLLER +#define DT_GPIO_STM32_GPIOH_LABEL DT_ST_STM32_GPIO_48001C00_LABEL +#define DT_GPIO_STM32_GPIOH_SIZE DT_ST_STM32_GPIO_48001C00_SIZE +#define DT_GPIO_STM32_GPIOH_CLOCK_BITS DT_ST_STM32_GPIO_48001C00_CLOCK_BITS +#define DT_GPIO_STM32_GPIOH_CLOCK_BUS DT_ST_STM32_GPIO_48001C00_CLOCK_BUS -#define CONFIG_GPIO_STM32_GPIOI_BASE_ADDRESS DT_ST_STM32_GPIO_48002000_BASE_ADDRESS -#define CONFIG_GPIO_STM32_GPIOI_CLOCK_BITS_0 DT_ST_STM32_GPIO_48002000_CLOCK_BITS_0 -#define CONFIG_GPIO_STM32_GPIOI_CLOCK_BUS_0 DT_ST_STM32_GPIO_48002000_CLOCK_BUS_0 -#define CONFIG_GPIO_STM32_GPIOI_CLOCK_CONTROLLER DT_ST_STM32_GPIO_48002000_CLOCK_CONTROLLER -#define CONFIG_GPIO_STM32_GPIOI_LABEL DT_ST_STM32_GPIO_48002000_LABEL -#define CONFIG_GPIO_STM32_GPIOI_SIZE DT_ST_STM32_GPIO_48002000_SIZE -#define CONFIG_GPIO_STM32_GPIOI_CLOCK_BITS DT_ST_STM32_GPIO_48002000_CLOCK_BITS -#define CONFIG_GPIO_STM32_GPIOI_CLOCK_BUS DT_ST_STM32_GPIO_48002000_CLOCK_BUS +#define DT_GPIO_STM32_GPIOI_BASE_ADDRESS DT_ST_STM32_GPIO_48002000_BASE_ADDRESS +#define DT_GPIO_STM32_GPIOI_CLOCK_BITS_0 DT_ST_STM32_GPIO_48002000_CLOCK_BITS_0 +#define DT_GPIO_STM32_GPIOI_CLOCK_BUS_0 DT_ST_STM32_GPIO_48002000_CLOCK_BUS_0 +#define DT_GPIO_STM32_GPIOI_CLOCK_CONTROLLER DT_ST_STM32_GPIO_48002000_CLOCK_CONTROLLER +#define DT_GPIO_STM32_GPIOI_LABEL DT_ST_STM32_GPIO_48002000_LABEL +#define DT_GPIO_STM32_GPIOI_SIZE DT_ST_STM32_GPIO_48002000_SIZE +#define DT_GPIO_STM32_GPIOI_CLOCK_BITS DT_ST_STM32_GPIO_48002000_CLOCK_BITS +#define DT_GPIO_STM32_GPIOI_CLOCK_BUS DT_ST_STM32_GPIO_48002000_CLOCK_BUS -#define CONFIG_UART_STM32_USART_1_BASE_ADDRESS DT_ST_STM32_USART_40013800_BASE_ADDRESS -#define CONFIG_UART_STM32_USART_1_BAUD_RATE DT_ST_STM32_USART_40013800_CURRENT_SPEED -#define CONFIG_UART_STM32_USART_1_IRQ_PRI DT_ST_STM32_USART_40013800_IRQ_0_PRIORITY -#define CONFIG_UART_STM32_USART_1_NAME DT_ST_STM32_USART_40013800_LABEL -#define USART_1_IRQ DT_ST_STM32_USART_40013800_IRQ_0 -#define CONFIG_UART_STM32_USART_1_CLOCK_BITS DT_ST_STM32_USART_40013800_CLOCK_BITS -#define CONFIG_UART_STM32_USART_1_CLOCK_BUS DT_ST_STM32_USART_40013800_CLOCK_BUS +#define DT_UART_STM32_USART_1_BASE_ADDRESS DT_ST_STM32_USART_40013800_BASE_ADDRESS +#define DT_UART_STM32_USART_1_BAUD_RATE DT_ST_STM32_USART_40013800_CURRENT_SPEED +#define DT_UART_STM32_USART_1_IRQ_PRI DT_ST_STM32_USART_40013800_IRQ_0_PRIORITY +#define DT_UART_STM32_USART_1_NAME DT_ST_STM32_USART_40013800_LABEL +#define DT_USART_1_IRQ DT_ST_STM32_USART_40013800_IRQ_0 +#define DT_UART_STM32_USART_1_CLOCK_BITS DT_ST_STM32_USART_40013800_CLOCK_BITS +#define DT_UART_STM32_USART_1_CLOCK_BUS DT_ST_STM32_USART_40013800_CLOCK_BUS -#define CONFIG_UART_STM32_USART_2_BASE_ADDRESS DT_ST_STM32_USART_40004400_BASE_ADDRESS -#define CONFIG_UART_STM32_USART_2_BAUD_RATE DT_ST_STM32_USART_40004400_CURRENT_SPEED -#define CONFIG_UART_STM32_USART_2_IRQ_PRI DT_ST_STM32_USART_40004400_IRQ_0_PRIORITY -#define CONFIG_UART_STM32_USART_2_NAME DT_ST_STM32_USART_40004400_LABEL -#define USART_2_IRQ DT_ST_STM32_USART_40004400_IRQ_0 -#define CONFIG_UART_STM32_USART_2_CLOCK_BITS DT_ST_STM32_USART_40004400_CLOCK_BITS -#define CONFIG_UART_STM32_USART_2_CLOCK_BUS DT_ST_STM32_USART_40004400_CLOCK_BUS +#define DT_UART_STM32_USART_2_BASE_ADDRESS DT_ST_STM32_USART_40004400_BASE_ADDRESS +#define DT_UART_STM32_USART_2_BAUD_RATE DT_ST_STM32_USART_40004400_CURRENT_SPEED +#define DT_UART_STM32_USART_2_IRQ_PRI DT_ST_STM32_USART_40004400_IRQ_0_PRIORITY +#define DT_UART_STM32_USART_2_NAME DT_ST_STM32_USART_40004400_LABEL +#define DT_USART_2_IRQ DT_ST_STM32_USART_40004400_IRQ_0 +#define DT_UART_STM32_USART_2_CLOCK_BITS DT_ST_STM32_USART_40004400_CLOCK_BITS +#define DT_UART_STM32_USART_2_CLOCK_BUS DT_ST_STM32_USART_40004400_CLOCK_BUS -#define CONFIG_UART_STM32_USART_3_BASE_ADDRESS DT_ST_STM32_USART_40004800_BASE_ADDRESS -#define CONFIG_UART_STM32_USART_3_BAUD_RATE DT_ST_STM32_USART_40004800_CURRENT_SPEED -#define CONFIG_UART_STM32_USART_3_IRQ_PRI DT_ST_STM32_USART_40004800_IRQ_0_PRIORITY -#define CONFIG_UART_STM32_USART_3_NAME DT_ST_STM32_USART_40004800_LABEL -#define USART_3_IRQ DT_ST_STM32_USART_40004800_IRQ_0 -#define CONFIG_UART_STM32_USART_3_CLOCK_BITS DT_ST_STM32_USART_40004800_CLOCK_BITS -#define CONFIG_UART_STM32_USART_3_CLOCK_BUS DT_ST_STM32_USART_40004800_CLOCK_BUS +#define DT_UART_STM32_USART_3_BASE_ADDRESS DT_ST_STM32_USART_40004800_BASE_ADDRESS +#define DT_UART_STM32_USART_3_BAUD_RATE DT_ST_STM32_USART_40004800_CURRENT_SPEED +#define DT_UART_STM32_USART_3_IRQ_PRI DT_ST_STM32_USART_40004800_IRQ_0_PRIORITY +#define DT_UART_STM32_USART_3_NAME DT_ST_STM32_USART_40004800_LABEL +#define DT_USART_3_IRQ DT_ST_STM32_USART_40004800_IRQ_0 +#define DT_UART_STM32_USART_3_CLOCK_BITS DT_ST_STM32_USART_40004800_CLOCK_BITS +#define DT_UART_STM32_USART_3_CLOCK_BUS DT_ST_STM32_USART_40004800_CLOCK_BUS -#define CONFIG_UART_STM32_UART_4_BASE_ADDRESS DT_ST_STM32_UART_40004C00_BASE_ADDRESS -#define CONFIG_UART_STM32_UART_4_BAUD_RATE DT_ST_STM32_UART_40004C00_CURRENT_SPEED -#define CONFIG_UART_STM32_UART_4_IRQ_PRI DT_ST_STM32_UART_40004C00_IRQ_0_PRIORITY -#define CONFIG_UART_STM32_UART_4_NAME DT_ST_STM32_UART_40004C00_LABEL -#define UART_4_IRQ DT_ST_STM32_UART_40004C00_IRQ_0 -#define CONFIG_UART_STM32_UART_4_CLOCK_BITS DT_ST_STM32_UART_40004C00_CLOCK_BITS -#define CONFIG_UART_STM32_UART_4_CLOCK_BUS DT_ST_STM32_UART_40004C00_CLOCK_BUS +#define DT_UART_STM32_UART_4_BASE_ADDRESS DT_ST_STM32_UART_40004C00_BASE_ADDRESS +#define DT_UART_STM32_UART_4_BAUD_RATE DT_ST_STM32_UART_40004C00_CURRENT_SPEED +#define DT_UART_STM32_UART_4_IRQ_PRI DT_ST_STM32_UART_40004C00_IRQ_0_PRIORITY +#define DT_UART_STM32_UART_4_NAME DT_ST_STM32_UART_40004C00_LABEL +#define DT_UART_4_IRQ DT_ST_STM32_UART_40004C00_IRQ_0 +#define DT_UART_STM32_UART_4_CLOCK_BITS DT_ST_STM32_UART_40004C00_CLOCK_BITS +#define DT_UART_STM32_UART_4_CLOCK_BUS DT_ST_STM32_UART_40004C00_CLOCK_BUS -#define CONFIG_UART_STM32_UART_5_BASE_ADDRESS DT_ST_STM32_UART_40005000_BASE_ADDRESS -#define CONFIG_UART_STM32_UART_5_BAUD_RATE DT_ST_STM32_UART_40005000_CURRENT_SPEED -#define CONFIG_UART_STM32_UART_5_IRQ_PRI DT_ST_STM32_UART_40005000_IRQ_0_PRIORITY -#define CONFIG_UART_STM32_UART_5_NAME DT_ST_STM32_UART_40005000_LABEL -#define UART_5_IRQ DT_ST_STM32_UART_40005000_IRQ_0 -#define CONFIG_UART_STM32_UART_5_CLOCK_BITS DT_ST_STM32_UART_40005000_CLOCK_BITS -#define CONFIG_UART_STM32_UART_5_CLOCK_BUS DT_ST_STM32_UART_40005000_CLOCK_BUS +#define DT_UART_STM32_UART_5_BASE_ADDRESS DT_ST_STM32_UART_40005000_BASE_ADDRESS +#define DT_UART_STM32_UART_5_BAUD_RATE DT_ST_STM32_UART_40005000_CURRENT_SPEED +#define DT_UART_STM32_UART_5_IRQ_PRI DT_ST_STM32_UART_40005000_IRQ_0_PRIORITY +#define DT_UART_STM32_UART_5_NAME DT_ST_STM32_UART_40005000_LABEL +#define DT_UART_5_IRQ DT_ST_STM32_UART_40005000_IRQ_0 +#define DT_UART_STM32_UART_5_CLOCK_BITS DT_ST_STM32_UART_40005000_CLOCK_BITS +#define DT_UART_STM32_UART_5_CLOCK_BUS DT_ST_STM32_UART_40005000_CLOCK_BUS -#define CONFIG_UART_STM32_LPUART_1_BASE_ADDRESS DT_ST_STM32_LPUART_40008000_BASE_ADDRESS -#define CONFIG_UART_STM32_LPUART_1_BAUD_RATE DT_ST_STM32_LPUART_40008000_CURRENT_SPEED -#define CONFIG_UART_STM32_LPUART_1_IRQ_PRI DT_ST_STM32_LPUART_40008000_IRQ_0_PRIORITY -#define CONFIG_UART_STM32_LPUART_1_NAME DT_ST_STM32_LPUART_40008000_LABEL -#define LPUART_1_IRQ DT_ST_STM32_LPUART_40008000_IRQ_0 -#define CONFIG_UART_STM32_LPUART_1_CLOCK_BITS DT_ST_STM32_LPUART_40008000_CLOCK_BITS -#define CONFIG_UART_STM32_LPUART_1_CLOCK_BUS DT_ST_STM32_LPUART_40008000_CLOCK_BUS +#define DT_UART_STM32_LPUART_1_BASE_ADDRESS DT_ST_STM32_LPUART_40008000_BASE_ADDRESS +#define DT_UART_STM32_LPUART_1_BAUD_RATE DT_ST_STM32_LPUART_40008000_CURRENT_SPEED +#define DT_UART_STM32_LPUART_1_IRQ_PRI DT_ST_STM32_LPUART_40008000_IRQ_0_PRIORITY +#define DT_UART_STM32_LPUART_1_NAME DT_ST_STM32_LPUART_40008000_LABEL +#define DT_LPUART_1_IRQ DT_ST_STM32_LPUART_40008000_IRQ_0 +#define DT_UART_STM32_LPUART_1_CLOCK_BITS DT_ST_STM32_LPUART_40008000_CLOCK_BITS +#define DT_UART_STM32_LPUART_1_CLOCK_BUS DT_ST_STM32_LPUART_40008000_CLOCK_BUS -#define CONFIG_I2C_1_BASE_ADDRESS DT_ST_STM32_I2C_V2_40005400_BASE_ADDRESS -#define CONFIG_I2C_1_EVENT_IRQ_PRI DT_ST_STM32_I2C_V2_40005400_IRQ_EVENT_PRIORITY -#define CONFIG_I2C_1_ERROR_IRQ_PRI DT_ST_STM32_I2C_V2_40005400_IRQ_ERROR_PRIORITY +#define DT_I2C_1_BASE_ADDRESS DT_ST_STM32_I2C_V2_40005400_BASE_ADDRESS +#define DT_I2C_1_EVENT_IRQ_PRI DT_ST_STM32_I2C_V2_40005400_IRQ_EVENT_PRIORITY +#define DT_I2C_1_ERROR_IRQ_PRI DT_ST_STM32_I2C_V2_40005400_IRQ_ERROR_PRIORITY #define CONFIG_I2C_1_NAME DT_ST_STM32_I2C_V2_40005400_LABEL -#define CONFIG_I2C_1_EVENT_IRQ DT_ST_STM32_I2C_V2_40005400_IRQ_EVENT -#define CONFIG_I2C_1_ERROR_IRQ DT_ST_STM32_I2C_V2_40005400_IRQ_ERROR -#define CONFIG_I2C_1_BITRATE DT_ST_STM32_I2C_V2_40005400_CLOCK_FREQUENCY -#define CONFIG_I2C_1_CLOCK_BITS DT_ST_STM32_I2C_V2_40005400_CLOCK_BITS -#define CONFIG_I2C_1_CLOCK_BUS DT_ST_STM32_I2C_V2_40005400_CLOCK_BUS +#define DT_I2C_1_EVENT_IRQ DT_ST_STM32_I2C_V2_40005400_IRQ_EVENT +#define DT_I2C_1_ERROR_IRQ DT_ST_STM32_I2C_V2_40005400_IRQ_ERROR +#define DT_I2C_1_BITRATE DT_ST_STM32_I2C_V2_40005400_CLOCK_FREQUENCY +#define DT_I2C_1_CLOCK_BITS DT_ST_STM32_I2C_V2_40005400_CLOCK_BITS +#define DT_I2C_1_CLOCK_BUS DT_ST_STM32_I2C_V2_40005400_CLOCK_BUS -#define CONFIG_I2C_2_BASE_ADDRESS DT_ST_STM32_I2C_V2_40005800_BASE_ADDRESS -#define CONFIG_I2C_2_EVENT_IRQ_PRI DT_ST_STM32_I2C_V2_40005800_IRQ_EVENT_PRIORITY -#define CONFIG_I2C_2_ERROR_IRQ_PRI DT_ST_STM32_I2C_V2_40005800_IRQ_ERROR_PRIORITY +#define DT_I2C_2_BASE_ADDRESS DT_ST_STM32_I2C_V2_40005800_BASE_ADDRESS +#define DT_I2C_2_EVENT_IRQ_PRI DT_ST_STM32_I2C_V2_40005800_IRQ_EVENT_PRIORITY +#define DT_I2C_2_ERROR_IRQ_PRI DT_ST_STM32_I2C_V2_40005800_IRQ_ERROR_PRIORITY #define CONFIG_I2C_2_NAME DT_ST_STM32_I2C_V2_40005800_LABEL -#define CONFIG_I2C_2_EVENT_IRQ DT_ST_STM32_I2C_V2_40005800_IRQ_EVENT -#define CONFIG_I2C_2_ERROR_IRQ DT_ST_STM32_I2C_V2_40005800_IRQ_ERROR -#define CONFIG_I2C_2_BITRATE DT_ST_STM32_I2C_V2_40005800_CLOCK_FREQUENCY -#define CONFIG_I2C_2_CLOCK_BITS DT_ST_STM32_I2C_V2_40005800_CLOCK_BITS -#define CONFIG_I2C_2_CLOCK_BUS DT_ST_STM32_I2C_V2_40005800_CLOCK_BUS +#define DT_I2C_2_EVENT_IRQ DT_ST_STM32_I2C_V2_40005800_IRQ_EVENT +#define DT_I2C_2_ERROR_IRQ DT_ST_STM32_I2C_V2_40005800_IRQ_ERROR +#define DT_I2C_2_BITRATE DT_ST_STM32_I2C_V2_40005800_CLOCK_FREQUENCY +#define DT_I2C_2_CLOCK_BITS DT_ST_STM32_I2C_V2_40005800_CLOCK_BITS +#define DT_I2C_2_CLOCK_BUS DT_ST_STM32_I2C_V2_40005800_CLOCK_BUS -#define CONFIG_I2C_3_BASE_ADDRESS DT_ST_STM32_I2C_V2_40005C00_BASE_ADDRESS -#define CONFIG_I2C_3_EVENT_IRQ_PRI DT_ST_STM32_I2C_V2_40005C00_IRQ_EVENT_PRIORITY -#define CONFIG_I2C_3_ERROR_IRQ_PRI DT_ST_STM32_I2C_V2_40005C00_IRQ_ERROR_PRIORITY +#define DT_I2C_3_BASE_ADDRESS DT_ST_STM32_I2C_V2_40005C00_BASE_ADDRESS +#define DT_I2C_3_EVENT_IRQ_PRI DT_ST_STM32_I2C_V2_40005C00_IRQ_EVENT_PRIORITY +#define DT_I2C_3_ERROR_IRQ_PRI DT_ST_STM32_I2C_V2_40005C00_IRQ_ERROR_PRIORITY #define CONFIG_I2C_3_NAME DT_ST_STM32_I2C_V2_40005C00_LABEL -#define CONFIG_I2C_3_EVENT_IRQ DT_ST_STM32_I2C_V2_40005C00_IRQ_EVENT -#define CONFIG_I2C_3_ERROR_IRQ DT_ST_STM32_I2C_V2_40005C00_IRQ_ERROR -#define CONFIG_I2C_3_BITRATE DT_ST_STM32_I2C_V2_40005C00_CLOCK_FREQUENCY -#define CONFIG_I2C_3_CLOCK_BITS DT_ST_STM32_I2C_V2_40005C00_CLOCK_BITS -#define CONFIG_I2C_3_CLOCK_BUS DT_ST_STM32_I2C_V2_40005C00_CLOCK_BUS +#define DT_I2C_3_EVENT_IRQ DT_ST_STM32_I2C_V2_40005C00_IRQ_EVENT +#define DT_I2C_3_ERROR_IRQ DT_ST_STM32_I2C_V2_40005C00_IRQ_ERROR +#define DT_I2C_3_BITRATE DT_ST_STM32_I2C_V2_40005C00_CLOCK_FREQUENCY +#define DT_I2C_3_CLOCK_BITS DT_ST_STM32_I2C_V2_40005C00_CLOCK_BITS +#define DT_I2C_3_CLOCK_BUS DT_ST_STM32_I2C_V2_40005C00_CLOCK_BUS -#define CONFIG_I2C_4_BASE_ADDRESS DT_ST_STM32_I2C_V2_40008400_BASE_ADDRESS -#define CONFIG_I2C_4_EVENT_IRQ_PRI DT_ST_STM32_I2C_V2_40008400_IRQ_EVENT_PRIORITY -#define CONFIG_I2C_4_ERROR_IRQ_PRI DT_ST_STM32_I2C_V2_40008400_IRQ_ERROR_PRIORITY +#define DT_I2C_4_BASE_ADDRESS DT_ST_STM32_I2C_V2_40008400_BASE_ADDRESS +#define DT_I2C_4_EVENT_IRQ_PRI DT_ST_STM32_I2C_V2_40008400_IRQ_EVENT_PRIORITY +#define DT_I2C_4_ERROR_IRQ_PRI DT_ST_STM32_I2C_V2_40008400_IRQ_ERROR_PRIORITY #define CONFIG_I2C_4_NAME DT_ST_STM32_I2C_V2_40008400_LABEL -#define CONFIG_I2C_4_EVENT_IRQ DT_ST_STM32_I2C_V2_40008400_IRQ_EVENT -#define CONFIG_I2C_4_ERROR_IRQ DT_ST_STM32_I2C_V2_40008400_IRQ_ERROR -#define CONFIG_I2C_4_BITRATE DT_ST_STM32_I2C_V2_40008400_CLOCK_FREQUENCY -#define CONFIG_I2C_4_CLOCK_BITS DT_ST_STM32_I2C_V2_40008400_CLOCK_BITS -#define CONFIG_I2C_4_CLOCK_BUS DT_ST_STM32_I2C_V2_40008400_CLOCK_BUS +#define DT_I2C_4_EVENT_IRQ DT_ST_STM32_I2C_V2_40008400_IRQ_EVENT +#define DT_I2C_4_ERROR_IRQ DT_ST_STM32_I2C_V2_40008400_IRQ_ERROR +#define DT_I2C_4_BITRATE DT_ST_STM32_I2C_V2_40008400_CLOCK_FREQUENCY +#define DT_I2C_4_CLOCK_BITS DT_ST_STM32_I2C_V2_40008400_CLOCK_BITS +#define DT_I2C_4_CLOCK_BUS DT_ST_STM32_I2C_V2_40008400_CLOCK_BUS -#define CONFIG_RTC_0_BASE_ADDRESS DT_ST_STM32_RTC_40002800_BASE_ADDRESS +#define DT_RTC_0_BASE_ADDRESS DT_ST_STM32_RTC_40002800_BASE_ADDRESS #define CONFIG_RTC_0_IRQ_PRI DT_ST_STM32_RTC_40002800_IRQ_0_PRIORITY -#define CONFIG_RTC_0_IRQ DT_ST_STM32_RTC_40002800_IRQ_0 +#define DT_RTC_0_IRQ DT_ST_STM32_RTC_40002800_IRQ_0 #define CONFIG_RTC_0_NAME DT_ST_STM32_RTC_40002800_LABEL #define CONFIG_RTC_PRESCALER DT_ST_STM32_RTC_40002800_PRESCALER -#define CONFIG_SPI_1_BASE_ADDRESS DT_ST_STM32_SPI_FIFO_40013000_BASE_ADDRESS +#define DT_SPI_1_BASE_ADDRESS DT_ST_STM32_SPI_FIFO_40013000_BASE_ADDRESS #define CONFIG_SPI_1_IRQ_PRI DT_ST_STM32_SPI_FIFO_40013000_IRQ_0_PRIORITY #define CONFIG_SPI_1_NAME DT_ST_STM32_SPI_FIFO_40013000_LABEL -#define CONFIG_SPI_1_IRQ DT_ST_STM32_SPI_FIFO_40013000_IRQ_0 +#define DT_SPI_1_IRQ DT_ST_STM32_SPI_FIFO_40013000_IRQ_0 -#define CONFIG_SPI_2_BASE_ADDRESS DT_ST_STM32_SPI_FIFO_40003800_BASE_ADDRESS +#define DT_SPI_2_BASE_ADDRESS DT_ST_STM32_SPI_FIFO_40003800_BASE_ADDRESS #define CONFIG_SPI_2_IRQ_PRI DT_ST_STM32_SPI_FIFO_40003800_IRQ_0_PRIORITY #define CONFIG_SPI_2_NAME DT_ST_STM32_SPI_FIFO_40003800_LABEL -#define CONFIG_SPI_2_IRQ DT_ST_STM32_SPI_FIFO_40003800_IRQ_0 +#define DT_SPI_2_IRQ DT_ST_STM32_SPI_FIFO_40003800_IRQ_0 -#define CONFIG_SPI_3_BASE_ADDRESS DT_ST_STM32_SPI_FIFO_40003C00_BASE_ADDRESS +#define DT_SPI_3_BASE_ADDRESS DT_ST_STM32_SPI_FIFO_40003C00_BASE_ADDRESS #define CONFIG_SPI_3_IRQ_PRI DT_ST_STM32_SPI_FIFO_40003C00_IRQ_0_PRIORITY #define CONFIG_SPI_3_NAME DT_ST_STM32_SPI_FIFO_40003C00_LABEL -#define CONFIG_SPI_3_IRQ DT_ST_STM32_SPI_FIFO_40003C00_IRQ_0 +#define DT_SPI_3_IRQ DT_ST_STM32_SPI_FIFO_40003C00_IRQ_0 -#define FLASH_DEV_BASE_ADDRESS DT_ST_STM32L4_FLASH_CONTROLLER_40022000_BASE_ADDRESS -#define FLASH_DEV_NAME DT_ST_STM32L4_FLASH_CONTROLLER_40022000_LABEL +#define DT_FLASH_DEV_BASE_ADDRESS DT_ST_STM32L4_FLASH_CONTROLLER_40022000_BASE_ADDRESS +#define DT_FLASH_DEV_NAME DT_ST_STM32L4_FLASH_CONTROLLER_40022000_LABEL #if defined(DT_ST_STM32_USB_40006800_BASE_ADDRESS) -#define CONFIG_USB_BASE_ADDRESS DT_ST_STM32_USB_40006800_BASE_ADDRESS -#define CONFIG_USB_IRQ DT_ST_STM32_USB_40006800_IRQ_USB -#define CONFIG_USB_IRQ_PRI DT_ST_STM32_USB_40006800_IRQ_USB_PRIORITY -#define CONFIG_USB_NUM_BIDIR_ENDPOINTS DT_ST_STM32_USB_40006800_NUM_BIDIR_ENDPOINTS -#define CONFIG_USB_RAM_SIZE DT_ST_STM32_USB_40006800_RAM_SIZE +#define DT_USB_BASE_ADDRESS DT_ST_STM32_USB_40006800_BASE_ADDRESS +#define DT_USB_IRQ DT_ST_STM32_USB_40006800_IRQ_USB +#define DT_USB_IRQ_PRI DT_ST_STM32_USB_40006800_IRQ_USB_PRIORITY +#define DT_USB_NUM_BIDIR_ENDPOINTS DT_ST_STM32_USB_40006800_NUM_BIDIR_ENDPOINTS +#define DT_USB_RAM_SIZE DT_ST_STM32_USB_40006800_RAM_SIZE #endif #if defined(DT_ST_STM32_OTGFS_50000000_BASE_ADDRESS) -#define CONFIG_USB_BASE_ADDRESS DT_ST_STM32_OTGFS_50000000_BASE_ADDRESS -#define CONFIG_USB_IRQ DT_ST_STM32_OTGFS_50000000_IRQ_OTGFS -#define CONFIG_USB_IRQ_PRI DT_ST_STM32_OTGFS_50000000_IRQ_OTGFS_PRIORITY -#define CONFIG_USB_NUM_BIDIR_ENDPOINTS DT_ST_STM32_OTGFS_50000000_NUM_BIDIR_ENDPOINTS -#define CONFIG_USB_RAM_SIZE DT_ST_STM32_OTGFS_50000000_RAM_SIZE -#define CONFIG_USB_MAXIMUM_SPEED DT_ST_STM32_OTGFS_50000000_MAXIMUM_SPEED +#define DT_USB_BASE_ADDRESS DT_ST_STM32_OTGFS_50000000_BASE_ADDRESS +#define DT_USB_IRQ DT_ST_STM32_OTGFS_50000000_IRQ_OTGFS +#define DT_USB_IRQ_PRI DT_ST_STM32_OTGFS_50000000_IRQ_OTGFS_PRIORITY +#define DT_USB_NUM_BIDIR_ENDPOINTS DT_ST_STM32_OTGFS_50000000_NUM_BIDIR_ENDPOINTS +#define DT_USB_RAM_SIZE DT_ST_STM32_OTGFS_50000000_RAM_SIZE +#define DT_USB_MAXIMUM_SPEED DT_ST_STM32_OTGFS_50000000_MAXIMUM_SPEED #endif -#define CONFIG_PWM_STM32_1_DEV_NAME DT_ST_STM32_PWM_40012C00_PWM_LABEL -#define CONFIG_PWM_STM32_1_PRESCALER DT_ST_STM32_PWM_40012C00_PWM_ST_PRESCALER +#define DT_PWM_STM32_1_DEV_NAME DT_ST_STM32_PWM_40012C00_PWM_LABEL +#define DT_PWM_STM32_1_PRESCALER DT_ST_STM32_PWM_40012C00_PWM_ST_PRESCALER -#define CONFIG_PWM_STM32_2_DEV_NAME DT_ST_STM32_PWM_40000000_PWM_LABEL -#define CONFIG_PWM_STM32_2_PRESCALER DT_ST_STM32_PWM_40000000_PWM_ST_PRESCALER +#define DT_PWM_STM32_2_DEV_NAME DT_ST_STM32_PWM_40000000_PWM_LABEL +#define DT_PWM_STM32_2_PRESCALER DT_ST_STM32_PWM_40000000_PWM_ST_PRESCALER -#define CONFIG_PWM_STM32_3_DEV_NAME DT_ST_STM32_PWM_40000400_PWM_LABEL -#define CONFIG_PWM_STM32_3_PRESCALER DT_ST_STM32_PWM_40000400_PWM_ST_PRESCALER +#define DT_PWM_STM32_3_DEV_NAME DT_ST_STM32_PWM_40000400_PWM_LABEL +#define DT_PWM_STM32_3_PRESCALER DT_ST_STM32_PWM_40000400_PWM_ST_PRESCALER -#define CONFIG_PWM_STM32_4_DEV_NAME DT_ST_STM32_PWM_40000800_PWM_LABEL -#define CONFIG_PWM_STM32_4_PRESCALER DT_ST_STM32_PWM_40000800_PWM_ST_PRESCALER +#define DT_PWM_STM32_4_DEV_NAME DT_ST_STM32_PWM_40000800_PWM_LABEL +#define DT_PWM_STM32_4_PRESCALER DT_ST_STM32_PWM_40000800_PWM_ST_PRESCALER -#define CONFIG_PWM_STM32_5_DEV_NAME DT_ST_STM32_PWM_40000C00_PWM_LABEL -#define CONFIG_PWM_STM32_5_PRESCALER DT_ST_STM32_PWM_40000C00_PWM_ST_PRESCALER +#define DT_PWM_STM32_5_DEV_NAME DT_ST_STM32_PWM_40000C00_PWM_LABEL +#define DT_PWM_STM32_5_PRESCALER DT_ST_STM32_PWM_40000C00_PWM_ST_PRESCALER -#define CONFIG_PWM_STM32_6_DEV_NAME DT_ST_STM32_PWM_40001000_PWM_LABEL -#define CONFIG_PWM_STM32_6_PRESCALER DT_ST_STM32_PWM_40001000_PWM_ST_PRESCALER +#define DT_PWM_STM32_6_DEV_NAME DT_ST_STM32_PWM_40001000_PWM_LABEL +#define DT_PWM_STM32_6_PRESCALER DT_ST_STM32_PWM_40001000_PWM_ST_PRESCALER -#define CONFIG_PWM_STM32_7_DEV_NAME DT_ST_STM32_PWM_40001400_PWM_LABEL -#define CONFIG_PWM_STM32_7_PRESCALER DT_ST_STM32_PWM_40001400_PWM_ST_PRESCALER +#define DT_PWM_STM32_7_DEV_NAME DT_ST_STM32_PWM_40001400_PWM_LABEL +#define DT_PWM_STM32_7_PRESCALER DT_ST_STM32_PWM_40001400_PWM_ST_PRESCALER -#define CONFIG_PWM_STM32_8_DEV_NAME DT_ST_STM32_PWM_40013400_PWM_LABEL -#define CONFIG_PWM_STM32_8_PRESCALER DT_ST_STM32_PWM_40013400_PWM_ST_PRESCALER +#define DT_PWM_STM32_8_DEV_NAME DT_ST_STM32_PWM_40013400_PWM_LABEL +#define DT_PWM_STM32_8_PRESCALER DT_ST_STM32_PWM_40013400_PWM_ST_PRESCALER -#define CONFIG_PWM_STM32_15_DEV_NAME DT_ST_STM32_PWM_40014000_PWM_LABEL -#define CONFIG_PWM_STM32_15_PRESCALER DT_ST_STM32_PWM_40014000_PWM_ST_PRESCALER +#define DT_PWM_STM32_15_DEV_NAME DT_ST_STM32_PWM_40014000_PWM_LABEL +#define DT_PWM_STM32_15_PRESCALER DT_ST_STM32_PWM_40014000_PWM_ST_PRESCALER -#define CONFIG_PWM_STM32_16_DEV_NAME DT_ST_STM32_PWM_40014400_PWM_LABEL -#define CONFIG_PWM_STM32_16_PRESCALER DT_ST_STM32_PWM_40014400_PWM_ST_PRESCALER +#define DT_PWM_STM32_16_DEV_NAME DT_ST_STM32_PWM_40014400_PWM_LABEL +#define DT_PWM_STM32_16_PRESCALER DT_ST_STM32_PWM_40014400_PWM_ST_PRESCALER -#define CONFIG_PWM_STM32_17_DEV_NAME DT_ST_STM32_PWM_40014800_PWM_LABEL -#define CONFIG_PWM_STM32_17_PRESCALER DT_ST_STM32_PWM_40014800_PWM_ST_PRESCALER +#define DT_PWM_STM32_17_DEV_NAME DT_ST_STM32_PWM_40014800_PWM_LABEL +#define DT_PWM_STM32_17_PRESCALER DT_ST_STM32_PWM_40014800_PWM_ST_PRESCALER -#define CONFIG_CAN_1_BASE_ADDRESS DT_ST_STM32_CAN_40006400_BASE_ADDRESS -#define CONFIG_CAN_1_BUS_SPEED DT_ST_STM32_CAN_40006400_BUS_SPEED -#define CONFIG_CAN_1_NAME DT_ST_STM32_CAN_40006400_LABEL -#define CONFIG_CAN_1_IRQ_TX DT_ST_STM32_CAN_40006400_IRQ_TX -#define CONFIG_CAN_1_IRQ_RX0 DT_ST_STM32_CAN_40006400_IRQ_RX0 -#define CONFIG_CAN_1_IRQ_RX1 DT_ST_STM32_CAN_40006400_IRQ_RX1 -#define CONFIG_CAN_1_IRQ_SCE DT_ST_STM32_CAN_40006400_IRQ_SCE -#define CONFIG_CAN_1_IRQ_PRIORITY DT_ST_STM32_CAN_40006400_IRQ_0_PRIORITY -#define CONFIG_CAN_1_SJW DT_ST_STM32_CAN_40006400_SJW -#define CONFIG_CAN_1_PROP_SEG_PHASE_SEG1 DT_ST_STM32_CAN_40006400_PROP_SEG_PHASE_SEG1 -#define CONFIG_CAN_1_PHASE_SEG2 DT_ST_STM32_CAN_40006400_PHASE_SEG2 -#define CONFIG_CAN_1_CLOCK_BUS DT_ST_STM32_CAN_40006400_CLOCK_BUS -#define CONFIG_CAN_1_CLOCK_BITS DT_ST_STM32_CAN_40006400_CLOCK_BITS +#define DT_CAN_1_BASE_ADDRESS DT_ST_STM32_CAN_40006400_BASE_ADDRESS +#define DT_CAN_1_BUS_SPEED DT_ST_STM32_CAN_40006400_BUS_SPEED +#define DT_CAN_1_NAME DT_ST_STM32_CAN_40006400_LABEL +#define DT_CAN_1_IRQ_TX DT_ST_STM32_CAN_40006400_IRQ_TX +#define DT_CAN_1_IRQ_RX0 DT_ST_STM32_CAN_40006400_IRQ_RX0 +#define DT_CAN_1_IRQ_RX1 DT_ST_STM32_CAN_40006400_IRQ_RX1 +#define DT_CAN_1_IRQ_SCE DT_ST_STM32_CAN_40006400_IRQ_SCE +#define DT_CAN_1_IRQ_PRIORITY DT_ST_STM32_CAN_40006400_IRQ_0_PRIORITY +#define DT_CAN_1_SJW DT_ST_STM32_CAN_40006400_SJW +#define DT_CAN_1_PROP_SEG_PHASE_SEG1 DT_ST_STM32_CAN_40006400_PROP_SEG_PHASE_SEG1 +#define DT_CAN_1_PHASE_SEG2 DT_ST_STM32_CAN_40006400_PHASE_SEG2 +#define DT_CAN_1_CLOCK_BUS DT_ST_STM32_CAN_40006400_CLOCK_BUS +#define DT_CAN_1_CLOCK_BITS DT_ST_STM32_CAN_40006400_CLOCK_BITS /* End of SoC Level DTS fixup file */ diff --git a/soc/arm/ti_lm3s6965/dts_fixup.h b/soc/arm/ti_lm3s6965/dts_fixup.h index d72f76807e0..147293ac548 100644 --- a/soc/arm/ti_lm3s6965/dts_fixup.h +++ b/soc/arm/ti_lm3s6965/dts_fixup.h @@ -1,5 +1,5 @@ /* SoC level DTS fixup file */ -#define CONFIG_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS +#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS /* End of SoC Level DTS fixup file */ diff --git a/soc/arm/ti_lm3s6965/soc.h b/soc/arm/ti_lm3s6965/soc.h index 770e42c1383..c73e1d34e87 100644 --- a/soc/arm/ti_lm3s6965/soc.h +++ b/soc/arm/ti_lm3s6965/soc.h @@ -78,7 +78,7 @@ extern "C" { /* uart configuration settings */ #if defined(CONFIG_UART_STELLARIS) -#define UART_STELLARIS_CLK_FREQ SYSCLK_DEFAULT_IOSC_HZ +#define DT_UART_STELLARIS_CLK_FREQ SYSCLK_DEFAULT_IOSC_HZ #endif /* CONFIG_UART_STELLARIS */ diff --git a/soc/arm/ti_simplelink/cc2650/dts_fixup.h b/soc/arm/ti_simplelink/cc2650/dts_fixup.h index c3aa3cc8092..3e71730777c 100644 --- a/soc/arm/ti_simplelink/cc2650/dts_fixup.h +++ b/soc/arm/ti_simplelink/cc2650/dts_fixup.h @@ -1,10 +1,10 @@ /* SoC level DTS fixup file */ -#define CONFIG_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS +#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS #define DT_TI_STELLARIS_UART_4000C000_BASE_ADDRESS DT_TI_STELLARIS_UART_40001000_BASE_ADDRESS #define DT_TI_STELLARIS_UART_4000C000_CURRENT_SPEED DT_TI_STELLARIS_UART_40001000_CURRENT_SPEED -#define UART_STELLARIS_CLK_FREQ CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC +#define DT_UART_STELLARIS_CLK_FREQ CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC #define DT_TI_STELLARIS_UART_4000C000_IRQ_0 DT_TI_STELLARIS_UART_40001000_IRQ_0 #define DT_TI_STELLARIS_UART_4000C000_IRQ_0_PRIORITY DT_TI_STELLARIS_UART_40001000_IRQ_0_PRIORITY #define DT_TI_STELLARIS_UART_4000C000_LABEL DT_TI_STELLARIS_UART_40001000_LABEL diff --git a/soc/arm/ti_simplelink/cc32xx/dts_fixup.h b/soc/arm/ti_simplelink/cc32xx/dts_fixup.h index b819a79bb89..85ba24b14ed 100644 --- a/soc/arm/ti_simplelink/cc32xx/dts_fixup.h +++ b/soc/arm/ti_simplelink/cc32xx/dts_fixup.h @@ -1,32 +1,32 @@ /* SoC level DTS fixup file */ -#define CONFIG_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS -#define CONFIG_UART_CC32XX_NAME DT_TI_CC32XX_UART_4000C000_LABEL +#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS +#define DT_UART_CC32XX_NAME DT_TI_CC32XX_UART_4000C000_LABEL -#define CONFIG_I2C_0_LABEL DT_TI_CC32XX_I2C_40020000_LABEL -#define CONFIG_I2C_0_BASE_ADDRESS DT_TI_CC32XX_I2C_40020000_BASE_ADDRESS -#define CONFIG_I2C_0_BITRATE DT_TI_CC32XX_I2C_40020000_CLOCK_FREQUENCY -#define CONFIG_I2C_0_IRQ DT_TI_CC32XX_I2C_40020000_IRQ_0 -#define CONFIG_I2C_0_IRQ_PRIORITY DT_TI_CC32XX_I2C_40020000_IRQ_0_PRIORITY +#define DT_I2C_0_LABEL DT_TI_CC32XX_I2C_40020000_LABEL +#define DT_I2C_0_BASE_ADDRESS DT_TI_CC32XX_I2C_40020000_BASE_ADDRESS +#define DT_I2C_0_BITRATE DT_TI_CC32XX_I2C_40020000_CLOCK_FREQUENCY +#define DT_I2C_0_IRQ DT_TI_CC32XX_I2C_40020000_IRQ_0 +#define DT_I2C_0_IRQ_PRIORITY DT_TI_CC32XX_I2C_40020000_IRQ_0_PRIORITY -#define CONFIG_GPIO_CC32XX_A0_BASE_ADDRESS DT_TI_CC32XX_GPIO_40004000_BASE_ADDRESS -#define CONFIG_GPIO_CC32XX_A0_IRQ DT_TI_CC32XX_GPIO_40004000_IRQ_0 -#define CONFIG_GPIO_CC32XX_A0_IRQ_PRI DT_TI_CC32XX_GPIO_40004000_IRQ_0_PRIORITY -#define CONFIG_GPIO_CC32XX_A0_NAME DT_TI_CC32XX_GPIO_40004000_LABEL +#define DT_GPIO_CC32XX_A0_BASE_ADDRESS DT_TI_CC32XX_GPIO_40004000_BASE_ADDRESS +#define DT_GPIO_CC32XX_A0_IRQ DT_TI_CC32XX_GPIO_40004000_IRQ_0 +#define DT_GPIO_CC32XX_A0_IRQ_PRI DT_TI_CC32XX_GPIO_40004000_IRQ_0_PRIORITY +#define DT_GPIO_CC32XX_A0_NAME DT_TI_CC32XX_GPIO_40004000_LABEL -#define CONFIG_GPIO_CC32XX_A1_BASE_ADDRESS DT_TI_CC32XX_GPIO_40005000_BASE_ADDRESS -#define CONFIG_GPIO_CC32XX_A1_IRQ DT_TI_CC32XX_GPIO_40005000_IRQ_0 -#define CONFIG_GPIO_CC32XX_A1_IRQ_PRI DT_TI_CC32XX_GPIO_40005000_IRQ_0_PRIORITY -#define CONFIG_GPIO_CC32XX_A1_NAME DT_TI_CC32XX_GPIO_40005000_LABEL +#define DT_GPIO_CC32XX_A1_BASE_ADDRESS DT_TI_CC32XX_GPIO_40005000_BASE_ADDRESS +#define DT_GPIO_CC32XX_A1_IRQ DT_TI_CC32XX_GPIO_40005000_IRQ_0 +#define DT_GPIO_CC32XX_A1_IRQ_PRI DT_TI_CC32XX_GPIO_40005000_IRQ_0_PRIORITY +#define DT_GPIO_CC32XX_A1_NAME DT_TI_CC32XX_GPIO_40005000_LABEL -#define CONFIG_GPIO_CC32XX_A2_BASE_ADDRESS DT_TI_CC32XX_GPIO_40006000_BASE_ADDRESS -#define CONFIG_GPIO_CC32XX_A2_IRQ DT_TI_CC32XX_GPIO_40006000_IRQ_0 -#define CONFIG_GPIO_CC32XX_A2_IRQ_PRI DT_TI_CC32XX_GPIO_40006000_IRQ_0_PRIORITY -#define CONFIG_GPIO_CC32XX_A2_NAME DT_TI_CC32XX_GPIO_40006000_LABEL +#define DT_GPIO_CC32XX_A2_BASE_ADDRESS DT_TI_CC32XX_GPIO_40006000_BASE_ADDRESS +#define DT_GPIO_CC32XX_A2_IRQ DT_TI_CC32XX_GPIO_40006000_IRQ_0 +#define DT_GPIO_CC32XX_A2_IRQ_PRI DT_TI_CC32XX_GPIO_40006000_IRQ_0_PRIORITY +#define DT_GPIO_CC32XX_A2_NAME DT_TI_CC32XX_GPIO_40006000_LABEL -#define CONFIG_GPIO_CC32XX_A3_BASE_ADDRESS DT_TI_CC32XX_GPIO_40007000_BASE_ADDRESS -#define CONFIG_GPIO_CC32XX_A3_IRQ DT_TI_CC32XX_GPIO_40007000_IRQ_0 -#define CONFIG_GPIO_CC32XX_A3_IRQ_PRI DT_TI_CC32XX_GPIO_40007000_IRQ_0_PRIORITY -#define CONFIG_GPIO_CC32XX_A3_NAME DT_TI_CC32XX_GPIO_40007000_LABEL +#define DT_GPIO_CC32XX_A3_BASE_ADDRESS DT_TI_CC32XX_GPIO_40007000_BASE_ADDRESS +#define DT_GPIO_CC32XX_A3_IRQ DT_TI_CC32XX_GPIO_40007000_IRQ_0 +#define DT_GPIO_CC32XX_A3_IRQ_PRI DT_TI_CC32XX_GPIO_40007000_IRQ_0_PRIORITY +#define DT_GPIO_CC32XX_A3_NAME DT_TI_CC32XX_GPIO_40007000_LABEL /* End of SoC Level DTS fixup file */ diff --git a/soc/arm/ti_simplelink/cc32xx/soc.h b/soc/arm/ti_simplelink/cc32xx/soc.h index 83a1948db89..561239f8bb7 100644 --- a/soc/arm/ti_simplelink/cc32xx/soc.h +++ b/soc/arm/ti_simplelink/cc32xx/soc.h @@ -32,5 +32,5 @@ enum { #define __CM4_REV 0 #define __MPU_PRESENT 0 /* Zephyr has no MPU support */ -#define __NVIC_PRIO_BITS CONFIG_NUM_IRQ_PRIO_BITS +#define __NVIC_PRIO_BITS DT_NUM_IRQ_PRIO_BITS #define __Vendor_SysTickConfig 0 /* Default to standard SysTick */ diff --git a/soc/arm/ti_simplelink/msp432p4xx/dts_fixup.h b/soc/arm/ti_simplelink/msp432p4xx/dts_fixup.h index 982d4ccf6da..41336180b64 100644 --- a/soc/arm/ti_simplelink/msp432p4xx/dts_fixup.h +++ b/soc/arm/ti_simplelink/msp432p4xx/dts_fixup.h @@ -6,10 +6,10 @@ /* SoC level DTS fixup file */ -#define CONFIG_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS +#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS -#define CONFIG_UART_MSP432P4XX_NAME DT_TI_MSP432P4XX_UART_40001000_LABEL -#define CONFIG_UART_MSP432P4XX_BASE_ADDRESS DT_TI_MSP432P4XX_UART_40001000_BASE_ADDRESS -#define CONFIG_UART_MSP432P4XX_BAUD_RATE DT_TI_MSP432P4XX_UART_40001000_CURRENT_SPEED +#define DT_UART_MSP432P4XX_NAME DT_TI_MSP432P4XX_UART_40001000_LABEL +#define DT_UART_MSP432P4XX_BASE_ADDRESS DT_TI_MSP432P4XX_UART_40001000_BASE_ADDRESS +#define DT_UART_MSP432P4XX_BAUD_RATE DT_TI_MSP432P4XX_UART_40001000_CURRENT_SPEED /* End of SoC Level DTS fixup file */ diff --git a/soc/nios2/nios2-qemu/soc.h b/soc/nios2/nios2-qemu/soc.h index 47a80e66de6..c1329016409 100644 --- a/soc/nios2/nios2-qemu/soc.h +++ b/soc/nios2/nios2-qemu/soc.h @@ -10,8 +10,8 @@ #include -#define CONFIG_UART_NS16550_PORT_0_BASE_ADDR A_16550_UART_0_BASE -#define CONFIG_UART_NS16550_PORT_0_IRQ A_16550_UART_0_IRQ -#define CONFIG_UART_NS16550_PORT_0_CLK_FREQ A_16550_UART_0_FREQ +#define DT_UART_NS16550_PORT_0_BASE_ADDR A_16550_UART_0_BASE +#define DT_UART_NS16550_PORT_0_IRQ A_16550_UART_0_IRQ +#define DT_UART_NS16550_PORT_0_CLK_FREQ A_16550_UART_0_FREQ #endif diff --git a/soc/nios2/nios2f-zephyr/soc.h b/soc/nios2/nios2f-zephyr/soc.h index dcd232cda23..aebdc583934 100644 --- a/soc/nios2/nios2f-zephyr/soc.h +++ b/soc/nios2/nios2f-zephyr/soc.h @@ -10,8 +10,8 @@ #include -#define CONFIG_UART_NS16550_PORT_0_BASE_ADDR A_16550_UART_0_BASE -#define CONFIG_UART_NS16550_PORT_0_IRQ A_16550_UART_0_IRQ -#define CONFIG_UART_NS16550_PORT_0_CLK_FREQ A_16550_UART_0_FREQ +#define DT_UART_NS16550_PORT_0_BASE_ADDR A_16550_UART_0_BASE +#define DT_UART_NS16550_PORT_0_IRQ A_16550_UART_0_IRQ +#define DT_UART_NS16550_PORT_0_CLK_FREQ A_16550_UART_0_FREQ #endif diff --git a/soc/riscv32/pulpino/dts_fixup.h b/soc/riscv32/pulpino/dts_fixup.h index fefa2bb3b06..53ae3e46a38 100644 --- a/soc/riscv32/pulpino/dts_fixup.h +++ b/soc/riscv32/pulpino/dts_fixup.h @@ -9,8 +9,8 @@ /* * UART configuration */ -#define CONFIG_UART_NS16550_PORT_0_BASE_ADDR DT_NS16550_1A100000_BASE_ADDRESS -#define CONFIG_UART_NS16550_PORT_0_IRQ DT_NS16550_1A100000_IRQ_0 -#define CONFIG_UART_NS16550_PORT_0_CLK_FREQ DT_NS16550_1A100000_CLOCK_FREQUENCY +#define DT_UART_NS16550_PORT_0_BASE_ADDR DT_NS16550_1A100000_BASE_ADDRESS +#define DT_UART_NS16550_PORT_0_IRQ DT_NS16550_1A100000_IRQ_0 +#define DT_UART_NS16550_PORT_0_CLK_FREQ DT_NS16550_1A100000_CLOCK_FREQUENCY #define CONFIG_UART_NS16550_PORT_0_BAUD_RATE DT_NS16550_1A100000_CURRENT_SPEED #define CONFIG_UART_NS16550_PORT_0_NAME DT_NS16550_1A100000_LABEL diff --git a/soc/riscv32/pulpino/soc.h b/soc/riscv32/pulpino/soc.h index a5027ec6ca5..ea81b1e2022 100644 --- a/soc/riscv32/pulpino/soc.h +++ b/soc/riscv32/pulpino/soc.h @@ -58,7 +58,7 @@ /* UART configuration */ #define CONFIG_UART_NS16550_PORT_0_IRQ_PRI 0 -#define CONFIG_UART_NS16550_PORT_0_IRQ_FLAGS 0 +#define DT_UART_NS16550_PORT_0_IRQ_FLAGS 0 /* PAD configuration */ #define PULP_PAD_BASE 0x1A107000 diff --git a/soc/riscv32/riscv-privilege/miv/dts_fixup.h b/soc/riscv32/riscv-privilege/miv/dts_fixup.h index f34b543e994..872173c0ad8 100644 --- a/soc/riscv32/riscv-privilege/miv/dts_fixup.h +++ b/soc/riscv32/riscv-privilege/miv/dts_fixup.h @@ -1,7 +1,7 @@ /* UART 0 */ -#define CONFIG_MIV_UART_0_BASE_ADDR DT_MICROSEMI_COREUART_70001000_BASE_ADDRESS -#define CONFIG_MIV_UART_0_CLOCK_FREQUENCY DT_MICROSEMI_COREUART_70001000_CLOCK_FREQUENCY -#define CONFIG_MIV_UART_0_BAUD_RATE DT_MICROSEMI_COREUART_70001000_CURRENT_SPEED -#define CONFIG_MIV_UART_0_NAME DT_MICROSEMI_COREUART_70001000_LABEL +#define DT_MIV_UART_0_BASE_ADDR DT_MICROSEMI_COREUART_70001000_BASE_ADDRESS +#define DT_MIV_UART_0_CLOCK_FREQUENCY DT_MICROSEMI_COREUART_70001000_CLOCK_FREQUENCY +#define DT_MIV_UART_0_BAUD_RATE DT_MICROSEMI_COREUART_70001000_CURRENT_SPEED +#define DT_MIV_UART_0_NAME DT_MICROSEMI_COREUART_70001000_LABEL diff --git a/soc/riscv32/riscv-privilege/sifive-freedom/dts_fixup.h b/soc/riscv32/riscv-privilege/sifive-freedom/dts_fixup.h index 85c4890323f..ce84912185a 100644 --- a/soc/riscv32/riscv-privilege/sifive-freedom/dts_fixup.h +++ b/soc/riscv32/riscv-privilege/sifive-freedom/dts_fixup.h @@ -5,53 +5,53 @@ */ /* GPIO 0 */ -#define CONFIG_SIFIVE_GPIO_0_BASE_ADDR DT_SIFIVE_GPIO0_10012000_BASE_ADDRESS -#define CONFIG_SIFIVE_GPIO_0_IRQ_0 DT_SIFIVE_GPIO0_10012000_IRQ_0 -#define CONFIG_SIFIVE_GPIO_0_IRQ_1 DT_SIFIVE_GPIO0_10012000_IRQ_1 -#define CONFIG_SIFIVE_GPIO_0_IRQ_2 DT_SIFIVE_GPIO0_10012000_IRQ_2 -#define CONFIG_SIFIVE_GPIO_0_IRQ_3 DT_SIFIVE_GPIO0_10012000_IRQ_3 -#define CONFIG_SIFIVE_GPIO_0_IRQ_4 DT_SIFIVE_GPIO0_10012000_IRQ_4 -#define CONFIG_SIFIVE_GPIO_0_IRQ_5 DT_SIFIVE_GPIO0_10012000_IRQ_5 -#define CONFIG_SIFIVE_GPIO_0_IRQ_6 DT_SIFIVE_GPIO0_10012000_IRQ_6 -#define CONFIG_SIFIVE_GPIO_0_IRQ_7 DT_SIFIVE_GPIO0_10012000_IRQ_7 -#define CONFIG_SIFIVE_GPIO_0_IRQ_8 DT_SIFIVE_GPIO0_10012000_IRQ_8 -#define CONFIG_SIFIVE_GPIO_0_IRQ_9 DT_SIFIVE_GPIO0_10012000_IRQ_9 -#define CONFIG_SIFIVE_GPIO_0_IRQ_10 DT_SIFIVE_GPIO0_10012000_IRQ_10 -#define CONFIG_SIFIVE_GPIO_0_IRQ_11 DT_SIFIVE_GPIO0_10012000_IRQ_11 -#define CONFIG_SIFIVE_GPIO_0_IRQ_12 DT_SIFIVE_GPIO0_10012000_IRQ_12 -#define CONFIG_SIFIVE_GPIO_0_IRQ_13 DT_SIFIVE_GPIO0_10012000_IRQ_13 -#define CONFIG_SIFIVE_GPIO_0_IRQ_14 DT_SIFIVE_GPIO0_10012000_IRQ_14 -#define CONFIG_SIFIVE_GPIO_0_IRQ_15 DT_SIFIVE_GPIO0_10012000_IRQ_15 -#define CONFIG_SIFIVE_GPIO_0_IRQ_16 DT_SIFIVE_GPIO0_10012000_IRQ_16 -#define CONFIG_SIFIVE_GPIO_0_IRQ_17 DT_SIFIVE_GPIO0_10012000_IRQ_17 -#define CONFIG_SIFIVE_GPIO_0_IRQ_18 DT_SIFIVE_GPIO0_10012000_IRQ_18 -#define CONFIG_SIFIVE_GPIO_0_IRQ_19 DT_SIFIVE_GPIO0_10012000_IRQ_19 -#define CONFIG_SIFIVE_GPIO_0_IRQ_20 DT_SIFIVE_GPIO0_10012000_IRQ_20 -#define CONFIG_SIFIVE_GPIO_0_IRQ_21 DT_SIFIVE_GPIO0_10012000_IRQ_21 -#define CONFIG_SIFIVE_GPIO_0_IRQ_22 DT_SIFIVE_GPIO0_10012000_IRQ_22 -#define CONFIG_SIFIVE_GPIO_0_IRQ_23 DT_SIFIVE_GPIO0_10012000_IRQ_23 -#define CONFIG_SIFIVE_GPIO_0_IRQ_24 DT_SIFIVE_GPIO0_10012000_IRQ_24 -#define CONFIG_SIFIVE_GPIO_0_IRQ_25 DT_SIFIVE_GPIO0_10012000_IRQ_25 -#define CONFIG_SIFIVE_GPIO_0_IRQ_26 DT_SIFIVE_GPIO0_10012000_IRQ_26 -#define CONFIG_SIFIVE_GPIO_0_IRQ_27 DT_SIFIVE_GPIO0_10012000_IRQ_27 -#define CONFIG_SIFIVE_GPIO_0_IRQ_28 DT_SIFIVE_GPIO0_10012000_IRQ_28 -#define CONFIG_SIFIVE_GPIO_0_IRQ_29 DT_SIFIVE_GPIO0_10012000_IRQ_29 -#define CONFIG_SIFIVE_GPIO_0_IRQ_30 DT_SIFIVE_GPIO0_10012000_IRQ_30 -#define CONFIG_SIFIVE_GPIO_0_IRQ_31 DT_SIFIVE_GPIO0_10012000_IRQ_31 -#define CONFIG_SIFIVE_GPIO_0_SIZE DT_SIFIVE_GPIO0_10012000_SIZE +#define DT_SIFIVE_GPIO_0_BASE_ADDR DT_SIFIVE_GPIO0_10012000_BASE_ADDRESS +#define DT_SIFIVE_GPIO_0_IRQ_0 DT_SIFIVE_GPIO0_10012000_IRQ_0 +#define DT_SIFIVE_GPIO_0_IRQ_1 DT_SIFIVE_GPIO0_10012000_IRQ_1 +#define DT_SIFIVE_GPIO_0_IRQ_2 DT_SIFIVE_GPIO0_10012000_IRQ_2 +#define DT_SIFIVE_GPIO_0_IRQ_3 DT_SIFIVE_GPIO0_10012000_IRQ_3 +#define DT_SIFIVE_GPIO_0_IRQ_4 DT_SIFIVE_GPIO0_10012000_IRQ_4 +#define DT_SIFIVE_GPIO_0_IRQ_5 DT_SIFIVE_GPIO0_10012000_IRQ_5 +#define DT_SIFIVE_GPIO_0_IRQ_6 DT_SIFIVE_GPIO0_10012000_IRQ_6 +#define DT_SIFIVE_GPIO_0_IRQ_7 DT_SIFIVE_GPIO0_10012000_IRQ_7 +#define DT_SIFIVE_GPIO_0_IRQ_8 DT_SIFIVE_GPIO0_10012000_IRQ_8 +#define DT_SIFIVE_GPIO_0_IRQ_9 DT_SIFIVE_GPIO0_10012000_IRQ_9 +#define DT_SIFIVE_GPIO_0_IRQ_10 DT_SIFIVE_GPIO0_10012000_IRQ_10 +#define DT_SIFIVE_GPIO_0_IRQ_11 DT_SIFIVE_GPIO0_10012000_IRQ_11 +#define DT_SIFIVE_GPIO_0_IRQ_12 DT_SIFIVE_GPIO0_10012000_IRQ_12 +#define DT_SIFIVE_GPIO_0_IRQ_13 DT_SIFIVE_GPIO0_10012000_IRQ_13 +#define DT_SIFIVE_GPIO_0_IRQ_14 DT_SIFIVE_GPIO0_10012000_IRQ_14 +#define DT_SIFIVE_GPIO_0_IRQ_15 DT_SIFIVE_GPIO0_10012000_IRQ_15 +#define DT_SIFIVE_GPIO_0_IRQ_16 DT_SIFIVE_GPIO0_10012000_IRQ_16 +#define DT_SIFIVE_GPIO_0_IRQ_17 DT_SIFIVE_GPIO0_10012000_IRQ_17 +#define DT_SIFIVE_GPIO_0_IRQ_18 DT_SIFIVE_GPIO0_10012000_IRQ_18 +#define DT_SIFIVE_GPIO_0_IRQ_19 DT_SIFIVE_GPIO0_10012000_IRQ_19 +#define DT_SIFIVE_GPIO_0_IRQ_20 DT_SIFIVE_GPIO0_10012000_IRQ_20 +#define DT_SIFIVE_GPIO_0_IRQ_21 DT_SIFIVE_GPIO0_10012000_IRQ_21 +#define DT_SIFIVE_GPIO_0_IRQ_22 DT_SIFIVE_GPIO0_10012000_IRQ_22 +#define DT_SIFIVE_GPIO_0_IRQ_23 DT_SIFIVE_GPIO0_10012000_IRQ_23 +#define DT_SIFIVE_GPIO_0_IRQ_24 DT_SIFIVE_GPIO0_10012000_IRQ_24 +#define DT_SIFIVE_GPIO_0_IRQ_25 DT_SIFIVE_GPIO0_10012000_IRQ_25 +#define DT_SIFIVE_GPIO_0_IRQ_26 DT_SIFIVE_GPIO0_10012000_IRQ_26 +#define DT_SIFIVE_GPIO_0_IRQ_27 DT_SIFIVE_GPIO0_10012000_IRQ_27 +#define DT_SIFIVE_GPIO_0_IRQ_28 DT_SIFIVE_GPIO0_10012000_IRQ_28 +#define DT_SIFIVE_GPIO_0_IRQ_29 DT_SIFIVE_GPIO0_10012000_IRQ_29 +#define DT_SIFIVE_GPIO_0_IRQ_30 DT_SIFIVE_GPIO0_10012000_IRQ_30 +#define DT_SIFIVE_GPIO_0_IRQ_31 DT_SIFIVE_GPIO0_10012000_IRQ_31 +#define DT_SIFIVE_GPIO_0_SIZE DT_SIFIVE_GPIO0_10012000_SIZE /* UART 0 */ -#define CONFIG_SIFIVE_UART_0_BASE_ADDR DT_SIFIVE_UART0_10013000_BASE_ADDRESS -#define CONFIG_SIFIVE_UART_0_CURRENT_SPEED DT_SIFIVE_UART0_10013000_CURRENT_SPEED -#define CONFIG_SIFIVE_UART_0_IRQ_0 DT_SIFIVE_UART0_10013000_IRQ_0 -#define CONFIG_SIFIVE_UART_0_LABEL DT_SIFIVE_UART0_10013000_LABEL -#define CONFIG_SIFIVE_UART_0_SIZE DT_SIFIVE_UART0_10013000_SIZE -#define CONFIG_SIFIVE_UART_0_CLK_FREQ DT_SIFIVE_UART0_10013000_CLOCK_FREQUENCY +#define DT_SIFIVE_UART_0_BASE_ADDR DT_SIFIVE_UART0_10013000_BASE_ADDRESS +#define DT_SIFIVE_UART_0_CURRENT_SPEED DT_SIFIVE_UART0_10013000_CURRENT_SPEED +#define DT_SIFIVE_UART_0_IRQ_0 DT_SIFIVE_UART0_10013000_IRQ_0 +#define DT_SIFIVE_UART_0_LABEL DT_SIFIVE_UART0_10013000_LABEL +#define DT_SIFIVE_UART_0_SIZE DT_SIFIVE_UART0_10013000_SIZE +#define DT_SIFIVE_UART_0_CLK_FREQ DT_SIFIVE_UART0_10013000_CLOCK_FREQUENCY /* UART 1 */ -#define CONFIG_SIFIVE_UART_1_BASE_ADDR DT_SIFIVE_UART0_10023000_BASE_ADDRESS -#define CONFIG_SIFIVE_UART_1_CURRENT_SPEED DT_SIFIVE_UART0_10023000_CURRENT_SPEED -#define CONFIG_SIFIVE_UART_1_IRQ_0 DT_SIFIVE_UART0_10023000_IRQ_0 -#define CONFIG_SIFIVE_UART_1_SIZE DT_SIFIVE_UART0_10023000_SIZE -#define CONFIG_SIFIVE_UART_1_CLK_FREQ DT_SIFIVE_UART0_10023000_CLOCK_FREQUENCY +#define DT_SIFIVE_UART_1_BASE_ADDR DT_SIFIVE_UART0_10023000_BASE_ADDRESS +#define DT_SIFIVE_UART_1_CURRENT_SPEED DT_SIFIVE_UART0_10023000_CURRENT_SPEED +#define DT_SIFIVE_UART_1_IRQ_0 DT_SIFIVE_UART0_10023000_IRQ_0 +#define DT_SIFIVE_UART_1_SIZE DT_SIFIVE_UART0_10023000_SIZE +#define DT_SIFIVE_UART_1_CLK_FREQ DT_SIFIVE_UART0_10023000_CLOCK_FREQUENCY diff --git a/soc/riscv32/riscv-privilege/sifive-freedom/soc.h b/soc/riscv32/riscv-privilege/sifive-freedom/soc.h index 2df9237d1f2..14d5e5237a1 100644 --- a/soc/riscv32/riscv-privilege/sifive-freedom/soc.h +++ b/soc/riscv32/riscv-privilege/sifive-freedom/soc.h @@ -14,7 +14,7 @@ #include /* PINMUX Configuration */ -#define SIFIVE_PINMUX_0_BASE_ADDR (CONFIG_SIFIVE_GPIO_0_BASE_ADDR + 0x38) +#define SIFIVE_PINMUX_0_BASE_ADDR (DT_SIFIVE_GPIO_0_BASE_ADDR + 0x38) /* PINMUX IO Hardware Functions */ #define SIFIVE_PINMUX_IOF0 0x00 diff --git a/soc/x86/apollo_lake/dts_fixup.h b/soc/x86/apollo_lake/dts_fixup.h index 789e6c38bae..7e5baa6e5c8 100644 --- a/soc/x86/apollo_lake/dts_fixup.h +++ b/soc/x86/apollo_lake/dts_fixup.h @@ -6,27 +6,27 @@ /* SoC level DTS fixup file */ -#define CONFIG_PHYS_RAM_ADDR CONFIG_SRAM_BASE_ADDRESS +#define DT_PHYS_RAM_ADDR CONFIG_SRAM_BASE_ADDRESS -#define CONFIG_PHYS_LOAD_ADDR CONFIG_FLASH_BASE_ADDRESS +#define DT_PHYS_LOAD_ADDR CONFIG_FLASH_BASE_ADDRESS -#define CONFIG_RAM_SIZE CONFIG_SRAM_SIZE +#define DT_RAM_SIZE CONFIG_SRAM_SIZE -#define CONFIG_ROM_SIZE CONFIG_FLASH_SIZE +#define DT_ROM_SIZE CONFIG_FLASH_SIZE -#define CONFIG_IOAPIC_BASE_ADDRESS DT_INTEL_IOAPIC_FEC00000_BASE_ADDRESS +#define DT_IOAPIC_BASE_ADDRESS DT_INTEL_IOAPIC_FEC00000_BASE_ADDRESS -#define CONFIG_APL_GPIO_BASE_ADDRESS_0 DT_INTEL_APL_GPIO_D0C50000_BASE_ADDRESS_0 -#define CONFIG_APL_GPIO_BASE_ADDRESS_1 DT_INTEL_APL_GPIO_D0C50000_BASE_ADDRESS_1 -#define CONFIG_APL_GPIO_BASE_ADDRESS_2 DT_INTEL_APL_GPIO_D0C50000_BASE_ADDRESS_2 -#define CONFIG_APL_GPIO_BASE_ADDRESS_3 DT_INTEL_APL_GPIO_D0C50000_BASE_ADDRESS_3 -#define CONFIG_APL_GPIO_IRQ DT_INTEL_APL_GPIO_D0C50000_IRQ_0 -#define CONFIG_APL_GPIO_IRQ_PRIORITY DT_INTEL_APL_GPIO_D0C50000_IRQ_0_PRIORITY -#define CONFIG_APL_GPIO_IRQ_SENSE DT_INTEL_APL_GPIO_D0C50000_IRQ_0_SENSE -#define CONFIG_APL_GPIO_LABEL DT_INTEL_APL_GPIO_D0C50000_LABEL -#define CONFIG_APL_GPIO_MEM_SIZE_0 DT_INTEL_APL_GPIO_D0C50000_SIZE_0 -#define CONFIG_APL_GPIO_MEM_SIZE_1 DT_INTEL_APL_GPIO_D0C50000_SIZE_1 -#define CONFIG_APL_GPIO_MEM_SIZE_2 DT_INTEL_APL_GPIO_D0C50000_SIZE_2 -#define CONFIG_APL_GPIO_MEM_SIZE_3 DT_oINTEL_APL_GPIO_D0C50000_SIZE_3 +#define DT_APL_GPIO_BASE_ADDRESS_0 DT_INTEL_APL_GPIO_D0C50000_BASE_ADDRESS_0 +#define DT_APL_GPIO_BASE_ADDRESS_1 DT_INTEL_APL_GPIO_D0C50000_BASE_ADDRESS_1 +#define DT_APL_GPIO_BASE_ADDRESS_2 DT_INTEL_APL_GPIO_D0C50000_BASE_ADDRESS_2 +#define DT_APL_GPIO_BASE_ADDRESS_3 DT_INTEL_APL_GPIO_D0C50000_BASE_ADDRESS_3 +#define DT_APL_GPIO_IRQ DT_INTEL_APL_GPIO_D0C50000_IRQ_0 +#define DT_APL_GPIO_IRQ_PRIORITY DT_INTEL_APL_GPIO_D0C50000_IRQ_0_PRIORITY +#define DT_APL_GPIO_IRQ_SENSE DT_INTEL_APL_GPIO_D0C50000_IRQ_0_SENSE +#define DT_APL_GPIO_LABEL DT_INTEL_APL_GPIO_D0C50000_LABEL +#define DT_APL_GPIO_MEM_SIZE_0 DT_INTEL_APL_GPIO_D0C50000_SIZE_0 +#define DT_APL_GPIO_MEM_SIZE_1 DT_INTEL_APL_GPIO_D0C50000_SIZE_1 +#define DT_APL_GPIO_MEM_SIZE_2 DT_INTEL_APL_GPIO_D0C50000_SIZE_2 +#define DT_APL_GPIO_MEM_SIZE_3 DT_oINTEL_APL_GPIO_D0C50000_SIZE_3 /* End of SoC Level DTS fixup file */ diff --git a/soc/x86/apollo_lake/linker.ld b/soc/x86/apollo_lake/linker.ld index f742f848071..dc7f6ff63c9 100644 --- a/soc/x86/apollo_lake/linker.ld +++ b/soc/x86/apollo_lake/linker.ld @@ -14,11 +14,11 @@ #include #include /* physical address where the kernel is loaded */ -#define PHYS_LOAD_ADDR CONFIG_PHYS_LOAD_ADDR +#define PHYS_LOAD_ADDR DT_PHYS_LOAD_ADDR /* physical address of RAM */ #ifdef CONFIG_XIP - #define PHYS_RAM_ADDR CONFIG_PHYS_RAM_ADDR + #define PHYS_RAM_ADDR DT_PHYS_RAM_ADDR #else /* !CONFIG_XIP */ #define PHYS_RAM_ADDR PHYS_LOAD_ADDR #endif /* CONFIG_XIP */ @@ -26,10 +26,10 @@ MEMORY { #ifdef CONFIG_XIP - ROM (rx) : ORIGIN = PHYS_LOAD_ADDR, LENGTH = CONFIG_ROM_SIZE*1K - RAM (wx) : ORIGIN = PHYS_RAM_ADDR, LENGTH = CONFIG_RAM_SIZE*1K + ROM (rx) : ORIGIN = PHYS_LOAD_ADDR, LENGTH = DT_ROM_SIZE*1K + RAM (wx) : ORIGIN = PHYS_RAM_ADDR, LENGTH = DT_RAM_SIZE*1K #else /* !CONFIG_XIP */ - RAM (wx) : ORIGIN = PHYS_LOAD_ADDR, LENGTH = CONFIG_RAM_SIZE*1K + RAM (wx) : ORIGIN = PHYS_LOAD_ADDR, LENGTH = DT_RAM_SIZE*1K #endif /* CONFIG_XIP */ /* diff --git a/soc/x86/apollo_lake/soc.c b/soc/x86/apollo_lake/soc.c index 8466b533f0a..33a15b82b9f 100644 --- a/soc/x86/apollo_lake/soc.c +++ b/soc/x86/apollo_lake/soc.c @@ -24,7 +24,7 @@ MMU_BOOT_REGION(CONFIG_LOAPIC_BASE_ADDRESS, 4 * 1024, MMU_ENTRY_WRITE); /* ioapic */ -MMU_BOOT_REGION(CONFIG_IOAPIC_BASE_ADDRESS, 1024 * 1024, MMU_ENTRY_WRITE); +MMU_BOOT_REGION(DT_IOAPIC_BASE_ADDRESS, 1024 * 1024, MMU_ENTRY_WRITE); #ifdef CONFIG_HPET_TIMER MMU_BOOT_REGION(CONFIG_HPET_TIMER_BASE_ADDRESS, KB(4), MMU_ENTRY_WRITE); @@ -34,17 +34,17 @@ MMU_BOOT_REGION(CONFIG_HPET_TIMER_BASE_ADDRESS, KB(4), MMU_ENTRY_WRITE); #ifdef CONFIG_UART_NS16550 #ifdef CONFIG_UART_NS16550_PORT_0 -MMU_BOOT_REGION(CONFIG_UART_NS16550_PORT_0_BASE_ADDR, 0x1000, +MMU_BOOT_REGION(DT_UART_NS16550_PORT_0_BASE_ADDR, 0x1000, (MMU_ENTRY_READ | MMU_ENTRY_WRITE)); #endif #ifdef CONFIG_UART_NS16550_PORT_1 -MMU_BOOT_REGION(CONFIG_UART_NS16550_PORT_1_BASE_ADDR, 0x1000, +MMU_BOOT_REGION(DT_UART_NS16550_PORT_1_BASE_ADDR, 0x1000, (MMU_ENTRY_READ | MMU_ENTRY_WRITE)); #endif #ifdef CONFIG_UART_NS16550_PORT_2 -MMU_BOOT_REGION(CONFIG_UART_NS16550_PORT_2_BASE_ADDR, 0x1000, +MMU_BOOT_REGION(DT_UART_NS16550_PORT_2_BASE_ADDR, 0x1000, (MMU_ENTRY_READ | MMU_ENTRY_WRITE)); #endif @@ -59,42 +59,42 @@ MMU_BOOT_REGION(CONFIG_UART_NS16550_PORT_3_BASE_ADDR, 0x1000, #ifdef CONFIG_I2C #ifdef CONFIG_I2C_0 -MMU_BOOT_REGION(CONFIG_I2C_0_BASE_ADDR, 0x1000, +MMU_BOOT_REGION(DT_I2C_0_BASE_ADDR, 0x1000, (MMU_ENTRY_READ | MMU_ENTRY_WRITE)); #endif #ifdef CONFIG_I2C_1 -MMU_BOOT_REGION(CONFIG_I2C_1_BASE_ADDR, 0x1000, +MMU_BOOT_REGION(DT_I2C_1_BASE_ADDR, 0x1000, (MMU_ENTRY_READ | MMU_ENTRY_WRITE)); #endif #ifdef CONFIG_I2C_2 -MMU_BOOT_REGION(CONFIG_I2C_2_BASE_ADDR, 0x1000, +MMU_BOOT_REGION(DT_I2C_2_BASE_ADDR, 0x1000, (MMU_ENTRY_READ | MMU_ENTRY_WRITE)); #endif #ifdef CONFIG_I2C_3 -MMU_BOOT_REGION(CONFIG_I2C_3_BASE_ADDR, 0x1000, +MMU_BOOT_REGION(DT_I2C_3_BASE_ADDR, 0x1000, (MMU_ENTRY_READ | MMU_ENTRY_WRITE)); #endif #ifdef CONFIG_I2C_4 -MMU_BOOT_REGION(CONFIG_I2C_4_BASE_ADDR, 0x1000, +MMU_BOOT_REGION(DT_I2C_4_BASE_ADDR, 0x1000, (MMU_ENTRY_READ | MMU_ENTRY_WRITE)); #endif #ifdef CONFIG_I2C_5 -MMU_BOOT_REGION(CONFIG_I2C_5_BASE_ADDR, 0x1000, +MMU_BOOT_REGION(DT_I2C_5_BASE_ADDR, 0x1000, (MMU_ENTRY_READ | MMU_ENTRY_WRITE)); #endif #ifdef CONFIG_I2C_6 -MMU_BOOT_REGION(CONFIG_I2C_6_BASE_ADDR, 0x1000, +MMU_BOOT_REGION(DT_I2C_6_BASE_ADDR, 0x1000, (MMU_ENTRY_READ | MMU_ENTRY_WRITE)); #endif #ifdef CONFIG_I2C_7 -MMU_BOOT_REGION(CONFIG_I2C_7_BASE_ADDR, 0x1000, +MMU_BOOT_REGION(DT_I2C_7_BASE_ADDR, 0x1000, (MMU_ENTRY_READ | MMU_ENTRY_WRITE)); #endif @@ -102,17 +102,17 @@ MMU_BOOT_REGION(CONFIG_I2C_7_BASE_ADDR, 0x1000, /* for GPIO controller */ #ifdef CONFIG_GPIO_INTEL_APL -MMU_BOOT_REGION(CONFIG_APL_GPIO_BASE_ADDRESS_0, - CONFIG_APL_GPIO_MEM_SIZE_0, +MMU_BOOT_REGION(DT_APL_GPIO_BASE_ADDRESS_0, + DT_APL_GPIO_MEM_SIZE_0, (MMU_ENTRY_READ | MMU_ENTRY_WRITE)); -MMU_BOOT_REGION(CONFIG_APL_GPIO_BASE_ADDRESS_1, - CONFIG_APL_GPIO_MEM_SIZE_1, +MMU_BOOT_REGION(DT_APL_GPIO_BASE_ADDRESS_1, + DT_APL_GPIO_MEM_SIZE_1, (MMU_ENTRY_READ | MMU_ENTRY_WRITE)); -MMU_BOOT_REGION(CONFIG_APL_GPIO_BASE_ADDRESS_2, - CONFIG_APL_GPIO_MEM_SIZE_2, +MMU_BOOT_REGION(DT_APL_GPIO_BASE_ADDRESS_2, + DT_APL_GPIO_MEM_SIZE_2, (MMU_ENTRY_READ | MMU_ENTRY_WRITE)); -MMU_BOOT_REGION(CONFIG_APL_GPIO_BASE_ADDRESS_3, - CONFIG_APL_GPIO_MEM_SIZE_3, +MMU_BOOT_REGION(DT_APL_GPIO_BASE_ADDRESS_3, + DT_APL_GPIO_MEM_SIZE_3, (MMU_ENTRY_READ | MMU_ENTRY_WRITE)); #endif diff --git a/soc/x86/atom/dts_fixup.h b/soc/x86/atom/dts_fixup.h index a67afd36292..71266e835c3 100644 --- a/soc/x86/atom/dts_fixup.h +++ b/soc/x86/atom/dts_fixup.h @@ -1,29 +1,29 @@ /* SoC level DTS fixup file */ -#define CONFIG_UART_NS16550_PORT_0_BASE_ADDR DT_NS16550_3F8_BASE_ADDRESS +#define DT_UART_NS16550_PORT_0_BASE_ADDR DT_NS16550_3F8_BASE_ADDRESS #define CONFIG_UART_NS16550_PORT_0_BAUD_RATE DT_NS16550_3F8_CURRENT_SPEED #define CONFIG_UART_NS16550_PORT_0_NAME DT_NS16550_3F8_LABEL -#define CONFIG_UART_NS16550_PORT_0_IRQ DT_NS16550_3F8_IRQ_0 +#define DT_UART_NS16550_PORT_0_IRQ DT_NS16550_3F8_IRQ_0 #define CONFIG_UART_NS16550_PORT_0_IRQ_PRI DT_NS16550_3F8_IRQ_0_PRIORITY -#define CONFIG_UART_NS16550_PORT_0_IRQ_FLAGS DT_NS16550_3F8_IRQ_0_SENSE -#define CONFIG_UART_NS16550_PORT_0_CLK_FREQ DT_NS16550_3F8_CLOCK_FREQUENCY +#define DT_UART_NS16550_PORT_0_IRQ_FLAGS DT_NS16550_3F8_IRQ_0_SENSE +#define DT_UART_NS16550_PORT_0_CLK_FREQ DT_NS16550_3F8_CLOCK_FREQUENCY -#define CONFIG_UART_NS16550_PORT_1_BASE_ADDR DT_NS16550_2F8_BASE_ADDRESS +#define DT_UART_NS16550_PORT_1_BASE_ADDR DT_NS16550_2F8_BASE_ADDRESS #define CONFIG_UART_NS16550_PORT_1_BAUD_RATE DT_NS16550_2F8_CURRENT_SPEED #define CONFIG_UART_NS16550_PORT_1_NAME DT_NS16550_2F8_LABEL -#define CONFIG_UART_NS16550_PORT_1_IRQ DT_NS16550_2F8_IRQ_0 +#define DT_UART_NS16550_PORT_1_IRQ DT_NS16550_2F8_IRQ_0 #define CONFIG_UART_NS16550_PORT_1_IRQ_PRI DT_NS16550_2F8_IRQ_0_PRIORITY -#define CONFIG_UART_NS16550_PORT_1_IRQ_FLAGS DT_NS16550_2F8_IRQ_0_SENSE -#define CONFIG_UART_NS16550_PORT_1_CLK_FREQ DT_NS16550_2F8_CLOCK_FREQUENCY +#define DT_UART_NS16550_PORT_1_IRQ_FLAGS DT_NS16550_2F8_IRQ_0_SENSE +#define DT_UART_NS16550_PORT_1_CLK_FREQ DT_NS16550_2F8_CLOCK_FREQUENCY -#define CONFIG_PHYS_RAM_ADDR CONFIG_SRAM_BASE_ADDRESS +#define DT_PHYS_RAM_ADDR CONFIG_SRAM_BASE_ADDRESS -#define CONFIG_PHYS_LOAD_ADDR CONFIG_FLASH_BASE_ADDRESS +#define DT_PHYS_LOAD_ADDR CONFIG_FLASH_BASE_ADDRESS -#define CONFIG_RAM_SIZE CONFIG_SRAM_SIZE +#define DT_RAM_SIZE CONFIG_SRAM_SIZE -#define CONFIG_ROM_SIZE CONFIG_FLASH_SIZE +#define DT_ROM_SIZE CONFIG_FLASH_SIZE -#define CONFIG_IOAPIC_BASE_ADDRESS DT_INTEL_IOAPIC_FEC00000_BASE_ADDRESS +#define DT_IOAPIC_BASE_ADDRESS DT_INTEL_IOAPIC_FEC00000_BASE_ADDRESS /* End of SoC Level DTS fixup file */ diff --git a/soc/x86/atom/linker.ld b/soc/x86/atom/linker.ld index f742f848071..dc7f6ff63c9 100644 --- a/soc/x86/atom/linker.ld +++ b/soc/x86/atom/linker.ld @@ -14,11 +14,11 @@ #include #include /* physical address where the kernel is loaded */ -#define PHYS_LOAD_ADDR CONFIG_PHYS_LOAD_ADDR +#define PHYS_LOAD_ADDR DT_PHYS_LOAD_ADDR /* physical address of RAM */ #ifdef CONFIG_XIP - #define PHYS_RAM_ADDR CONFIG_PHYS_RAM_ADDR + #define PHYS_RAM_ADDR DT_PHYS_RAM_ADDR #else /* !CONFIG_XIP */ #define PHYS_RAM_ADDR PHYS_LOAD_ADDR #endif /* CONFIG_XIP */ @@ -26,10 +26,10 @@ MEMORY { #ifdef CONFIG_XIP - ROM (rx) : ORIGIN = PHYS_LOAD_ADDR, LENGTH = CONFIG_ROM_SIZE*1K - RAM (wx) : ORIGIN = PHYS_RAM_ADDR, LENGTH = CONFIG_RAM_SIZE*1K + ROM (rx) : ORIGIN = PHYS_LOAD_ADDR, LENGTH = DT_ROM_SIZE*1K + RAM (wx) : ORIGIN = PHYS_RAM_ADDR, LENGTH = DT_RAM_SIZE*1K #else /* !CONFIG_XIP */ - RAM (wx) : ORIGIN = PHYS_LOAD_ADDR, LENGTH = CONFIG_RAM_SIZE*1K + RAM (wx) : ORIGIN = PHYS_LOAD_ADDR, LENGTH = DT_RAM_SIZE*1K #endif /* CONFIG_XIP */ /* diff --git a/soc/x86/atom/soc.c b/soc/x86/atom/soc.c index c567669a8d6..45a9aa8e8d0 100644 --- a/soc/x86/atom/soc.c +++ b/soc/x86/atom/soc.c @@ -23,7 +23,7 @@ MMU_BOOT_REGION(CONFIG_LOAPIC_BASE_ADDRESS, 4*1024, MMU_ENTRY_WRITE); /*ioapic */ -MMU_BOOT_REGION(CONFIG_IOAPIC_BASE_ADDRESS, 1024*1024, MMU_ENTRY_WRITE); +MMU_BOOT_REGION(DT_IOAPIC_BASE_ADDRESS, 1024*1024, MMU_ENTRY_WRITE); /* peripherals */ MMU_BOOT_REGION(0xB0000000, 128*1024, MMU_ENTRY_WRITE); diff --git a/soc/x86/ia32/dts_fixup.h b/soc/x86/ia32/dts_fixup.h index 78949b45b7e..bab6e48239b 100644 --- a/soc/x86/ia32/dts_fixup.h +++ b/soc/x86/ia32/dts_fixup.h @@ -1,30 +1,30 @@ /* SoC level DTS fixup file */ -#define CONFIG_UART_NS16550_PORT_0_BASE_ADDR DT_NS16550_3F8_BASE_ADDRESS +#define DT_UART_NS16550_PORT_0_BASE_ADDR DT_NS16550_3F8_BASE_ADDRESS #define CONFIG_UART_NS16550_PORT_0_BAUD_RATE DT_NS16550_3F8_CURRENT_SPEED #define CONFIG_UART_NS16550_PORT_0_NAME DT_NS16550_3F8_LABEL -#define CONFIG_UART_NS16550_PORT_0_IRQ DT_NS16550_3F8_IRQ_0 +#define DT_UART_NS16550_PORT_0_IRQ DT_NS16550_3F8_IRQ_0 #define CONFIG_UART_NS16550_PORT_0_IRQ_PRI DT_NS16550_3F8_IRQ_0_PRIORITY -#define CONFIG_UART_NS16550_PORT_0_IRQ_FLAGS DT_NS16550_3F8_IRQ_0_SENSE -#define CONFIG_UART_NS16550_PORT_0_CLK_FREQ DT_NS16550_3F8_CLOCK_FREQUENCY +#define DT_UART_NS16550_PORT_0_IRQ_FLAGS DT_NS16550_3F8_IRQ_0_SENSE +#define DT_UART_NS16550_PORT_0_CLK_FREQ DT_NS16550_3F8_CLOCK_FREQUENCY -#define CONFIG_UART_NS16550_PORT_1_BASE_ADDR DT_NS16550_2F8_BASE_ADDRESS +#define DT_UART_NS16550_PORT_1_BASE_ADDR DT_NS16550_2F8_BASE_ADDRESS #define CONFIG_UART_NS16550_PORT_1_BAUD_RATE DT_NS16550_2F8_CURRENT_SPEED #define CONFIG_UART_NS16550_PORT_1_NAME DT_NS16550_2F8_LABEL -#define CONFIG_UART_NS16550_PORT_1_IRQ DT_NS16550_2F8_IRQ_0 +#define DT_UART_NS16550_PORT_1_IRQ DT_NS16550_2F8_IRQ_0 #define CONFIG_UART_NS16550_PORT_1_IRQ_PRI DT_NS16550_2F8_IRQ_0_PRIORITY -#define CONFIG_UART_NS16550_PORT_1_IRQ_FLAGS DT_NS16550_2F8_IRQ_0_SENSE -#define CONFIG_UART_NS16550_PORT_1_CLK_FREQ DT_NS16550_2F8_CLOCK_FREQUENCY +#define DT_UART_NS16550_PORT_1_IRQ_FLAGS DT_NS16550_2F8_IRQ_0_SENSE +#define DT_UART_NS16550_PORT_1_CLK_FREQ DT_NS16550_2F8_CLOCK_FREQUENCY -#define CONFIG_PHYS_RAM_ADDR CONFIG_SRAM_BASE_ADDRESS +#define DT_PHYS_RAM_ADDR CONFIG_SRAM_BASE_ADDRESS -#define CONFIG_PHYS_LOAD_ADDR CONFIG_FLASH_BASE_ADDRESS +#define DT_PHYS_LOAD_ADDR CONFIG_FLASH_BASE_ADDRESS -#define CONFIG_RAM_SIZE CONFIG_SRAM_SIZE +#define DT_RAM_SIZE CONFIG_SRAM_SIZE -#define CONFIG_ROM_SIZE CONFIG_FLASH_SIZE +#define DT_ROM_SIZE CONFIG_FLASH_SIZE -#define CONFIG_IOAPIC_BASE_ADDRESS DT_INTEL_IOAPIC_FEC00000_BASE_ADDRESS +#define DT_IOAPIC_BASE_ADDRESS DT_INTEL_IOAPIC_FEC00000_BASE_ADDRESS /* End of SoC Level DTS fixup file */ diff --git a/soc/x86/ia32/linker.ld b/soc/x86/ia32/linker.ld index b72c32f7155..56a5232b804 100644 --- a/soc/x86/ia32/linker.ld +++ b/soc/x86/ia32/linker.ld @@ -15,11 +15,11 @@ #include /* physical address where the kernel is loaded */ -#define PHYS_LOAD_ADDR CONFIG_PHYS_LOAD_ADDR +#define PHYS_LOAD_ADDR DT_PHYS_LOAD_ADDR /* physical address of RAM */ #ifdef CONFIG_XIP - #define PHYS_RAM_ADDR CONFIG_PHYS_RAM_ADDR + #define PHYS_RAM_ADDR DT_PHYS_RAM_ADDR #else /* !CONFIG_XIP */ #define PHYS_RAM_ADDR PHYS_LOAD_ADDR #endif /* CONFIG_XIP */ @@ -27,10 +27,10 @@ MEMORY { #ifdef CONFIG_XIP - ROM (rx) : ORIGIN = PHYS_LOAD_ADDR, LENGTH = CONFIG_ROM_SIZE*1K - RAM (wx) : ORIGIN = PHYS_RAM_ADDR, LENGTH = CONFIG_RAM_SIZE*1K + ROM (rx) : ORIGIN = PHYS_LOAD_ADDR, LENGTH = DT_ROM_SIZE*1K + RAM (wx) : ORIGIN = PHYS_RAM_ADDR, LENGTH = DT_RAM_SIZE*1K #else /* !CONFIG_XIP */ - RAM (wx) : ORIGIN = PHYS_LOAD_ADDR, LENGTH = CONFIG_RAM_SIZE*1K + RAM (wx) : ORIGIN = PHYS_LOAD_ADDR, LENGTH = DT_RAM_SIZE*1K #endif /* CONFIG_XIP */ /* diff --git a/soc/x86/ia32/soc.c b/soc/x86/ia32/soc.c index 226f7d4f9f1..b740191af47 100644 --- a/soc/x86/ia32/soc.c +++ b/soc/x86/ia32/soc.c @@ -22,13 +22,13 @@ #ifdef CONFIG_X86_MMU MMU_BOOT_REGION(CONFIG_LOAPIC_BASE_ADDRESS, KB(4), MMU_ENTRY_WRITE); -MMU_BOOT_REGION(CONFIG_IOAPIC_BASE_ADDRESS, MB(1), MMU_ENTRY_WRITE); +MMU_BOOT_REGION(DT_IOAPIC_BASE_ADDRESS, MB(1), MMU_ENTRY_WRITE); #ifdef CONFIG_HPET_TIMER MMU_BOOT_REGION(CONFIG_HPET_TIMER_BASE_ADDRESS, KB(4), MMU_ENTRY_WRITE); #endif #ifdef CONFIG_ETH_E1000 -MMU_BOOT_REGION(CONFIG_ETH_E1000_BASE_ADDRESS, KB(128), MMU_ENTRY_WRITE); +MMU_BOOT_REGION(DT_ETH_E1000_BASE_ADDRESS, KB(128), MMU_ENTRY_WRITE); #endif #endif /* CONFIG_X86_MMU*/ diff --git a/soc/x86/intel_quark/quark_d2000/dts_fixup.h b/soc/x86/intel_quark/quark_d2000/dts_fixup.h index 7d713cbf565..fdd51ce0cb1 100644 --- a/soc/x86/intel_quark/quark_d2000/dts_fixup.h +++ b/soc/x86/intel_quark/quark_d2000/dts_fixup.h @@ -1,45 +1,45 @@ -#define CONFIG_UART_QMSI_0_BAUDRATE DT_INTEL_QMSI_UART_B0002000_CURRENT_SPEED -#define CONFIG_UART_QMSI_0_NAME DT_INTEL_QMSI_UART_B0002000_LABEL -#define CONFIG_UART_QMSI_0_IRQ DT_INTEL_QMSI_UART_B0002000_IRQ_0 -#define CONFIG_UART_QMSI_0_IRQ_FLAGS DT_INTEL_QMSI_UART_B0002000_IRQ_0_SENSE +#define DT_UART_QMSI_0_BAUDRATE DT_INTEL_QMSI_UART_B0002000_CURRENT_SPEED +#define DT_UART_QMSI_0_NAME DT_INTEL_QMSI_UART_B0002000_LABEL +#define DT_UART_QMSI_0_IRQ DT_INTEL_QMSI_UART_B0002000_IRQ_0 +#define DT_UART_QMSI_0_IRQ_FLAGS DT_INTEL_QMSI_UART_B0002000_IRQ_0_SENSE -#define CONFIG_UART_QMSI_1_BAUDRATE DT_INTEL_QMSI_UART_B0002400_CURRENT_SPEED -#define CONFIG_UART_QMSI_1_NAME DT_INTEL_QMSI_UART_B0002400_LABEL -#define CONFIG_UART_QMSI_1_IRQ DT_INTEL_QMSI_UART_B0002400_IRQ_0 -#define CONFIG_UART_QMSI_1_IRQ_FLAGS DT_INTEL_QMSI_UART_B0002400_IRQ_0_SENSE +#define DT_UART_QMSI_1_BAUDRATE DT_INTEL_QMSI_UART_B0002400_CURRENT_SPEED +#define DT_UART_QMSI_1_NAME DT_INTEL_QMSI_UART_B0002400_LABEL +#define DT_UART_QMSI_1_IRQ DT_INTEL_QMSI_UART_B0002400_IRQ_0 +#define DT_UART_QMSI_1_IRQ_FLAGS DT_INTEL_QMSI_UART_B0002400_IRQ_0_SENSE -#define CONFIG_PHYS_RAM_ADDR CONFIG_SRAM_BASE_ADDRESS +#define DT_PHYS_RAM_ADDR CONFIG_SRAM_BASE_ADDRESS -#define CONFIG_PHYS_LOAD_ADDR CONFIG_FLASH_BASE_ADDRESS +#define DT_PHYS_LOAD_ADDR CONFIG_FLASH_BASE_ADDRESS -#define CONFIG_RAM_SIZE CONFIG_SRAM_SIZE +#define DT_RAM_SIZE CONFIG_SRAM_SIZE -#define CONFIG_ROM_SIZE CONFIG_FLASH_SIZE +#define DT_ROM_SIZE CONFIG_FLASH_SIZE #define CONFIG_I2C_0_NAME DT_INTEL_QMSI_I2C_B0002800_LABEL -#define CONFIG_I2C_0_BITRATE DT_INTEL_QMSI_I2C_B0002800_CLOCK_FREQUENCY -#define CONFIG_I2C_0_IRQ DT_INTEL_QMSI_I2C_B0002800_IRQ_0 -#define CONFIG_I2C_0_IRQ_FLAGS DT_INTEL_QMSI_I2C_B0002800_IRQ_0_SENSE +#define DT_I2C_0_BITRATE DT_INTEL_QMSI_I2C_B0002800_CLOCK_FREQUENCY +#define DT_I2C_0_IRQ DT_INTEL_QMSI_I2C_B0002800_IRQ_0 +#define DT_I2C_0_IRQ_FLAGS DT_INTEL_QMSI_I2C_B0002800_IRQ_0_SENSE -#define CONFIG_GPIO_QMSI_0_NAME DT_INTEL_QMSI_GPIO_B0000C00_LABEL -#define CONFIG_GPIO_QMSI_0_IRQ DT_INTEL_QMSI_GPIO_B0000C00_IRQ_0 -#define CONFIG_GPIO_QMSI_0_IRQ_FLAGS DT_INTEL_QMSI_GPIO_B0000C00_IRQ_0_SENSE +#define DT_GPIO_QMSI_0_NAME DT_INTEL_QMSI_GPIO_B0000C00_LABEL +#define DT_GPIO_QMSI_0_IRQ DT_INTEL_QMSI_GPIO_B0000C00_IRQ_0 +#define DT_GPIO_QMSI_0_IRQ_FLAGS DT_INTEL_QMSI_GPIO_B0000C00_IRQ_0_SENSE #define CONFIG_RTC_0_NAME DT_INTEL_QMSI_RTC_B0000400_LABEL -#define CONFIG_RTC_0_IRQ DT_INTEL_QMSI_RTC_B0000400_IRQ_0 -#define CONFIG_RTC_0_IRQ_FLAGS DT_INTEL_QMSI_RTC_B0000400_IRQ_0_SENSE +#define DT_RTC_0_IRQ DT_INTEL_QMSI_RTC_B0000400_IRQ_0 +#define DT_RTC_0_IRQ_FLAGS DT_INTEL_QMSI_RTC_B0000400_IRQ_0_SENSE #define CONFIG_ADC_0_NAME DT_INTEL_QUARK_D2000_ADC_B0004000_LABEL -#define CONFIG_ADC_0_BASE_ADDRESS DT_INTEL_QUARK_D2000_ADC_B0004000_BASE_ADDRESS -#define CONFIG_ADC_0_IRQ DT_INTEL_QUARK_D2000_ADC_B0004000_IRQ_0 -#define CONFIG_ADC_0_IRQ_FLAGS DT_INTEL_QUARK_D2000_ADC_B0004000_IRQ_0_SENSE +#define DT_ADC_0_BASE_ADDRESS DT_INTEL_QUARK_D2000_ADC_B0004000_BASE_ADDRESS +#define DT_ADC_0_IRQ DT_INTEL_QUARK_D2000_ADC_B0004000_IRQ_0 +#define DT_ADC_0_IRQ_FLAGS DT_INTEL_QUARK_D2000_ADC_B0004000_IRQ_0_SENSE -#define CONFIG_SPI_0_BASE_ADDRESS DT_SNPS_DESIGNWARE_SPI_B0001000_BASE_ADDRESS +#define DT_SPI_0_BASE_ADDRESS DT_SNPS_DESIGNWARE_SPI_B0001000_BASE_ADDRESS #define CONFIG_SPI_0_NAME DT_SNPS_DESIGNWARE_SPI_B0001000_LABEL -#define CONFIG_SPI_0_IRQ DT_SNPS_DESIGNWARE_SPI_B0001000_IRQ_0 +#define DT_SPI_0_IRQ DT_SNPS_DESIGNWARE_SPI_B0001000_IRQ_0 #define CONFIG_SPI_0_IRQ_PRI 0 #define CONFIG_WDT_0_NAME DT_INTEL_QMSI_WATCHDOG_B0000000_LABEL -#define CONFIG_WDT_0_IRQ DT_INTEL_QMSI_WATCHDOG_B0000000_IRQ_0 -#define CONFIG_WDT_0_IRQ_PRI 0 -#define CONFIG_WDT_0_IRQ_FLAGS DT_INTEL_QMSI_WATCHDOG_B0000000_IRQ_0_SENSE +#define DT_WDT_0_IRQ DT_INTEL_QMSI_WATCHDOG_B0000000_IRQ_0 +#define DT_WDT_0_IRQ_PRI 0 +#define DT_WDT_0_IRQ_FLAGS DT_INTEL_QMSI_WATCHDOG_B0000000_IRQ_0_SENSE diff --git a/soc/x86/intel_quark/quark_d2000/linker.ld b/soc/x86/intel_quark/quark_d2000/linker.ld index afee01cc145..afc40757f26 100644 --- a/soc/x86/intel_quark/quark_d2000/linker.ld +++ b/soc/x86/intel_quark/quark_d2000/linker.ld @@ -15,25 +15,25 @@ #include /* physical address of RAM (needed for correct __ram_phys_end symbol) */ -#define PHYS_RAM_ADDR CONFIG_PHYS_RAM_ADDR +#define PHYS_RAM_ADDR DT_PHYS_RAM_ADDR /* physical address where the kernel is loaded */ #ifdef CONFIG_XIP - #define PHYS_LOAD_ADDR CONFIG_PHYS_LOAD_ADDR + #define PHYS_LOAD_ADDR DT_PHYS_LOAD_ADDR #else /* !CONFIG_XIP */ - #define PHYS_LOAD_ADDR CONFIG_PHYS_RAM_ADDR + #define PHYS_LOAD_ADDR DT_PHYS_RAM_ADDR #endif /* CONFIG_XIP */ #ifdef CONFIG_SET_GDT -#define PHYS_RAM_SIZE CONFIG_RAM_SIZE*1K +#define PHYS_RAM_SIZE DT_RAM_SIZE*1K #else /* !CONFIG_SET_GDT */ -#define PHYS_RAM_SIZE CONFIG_RAM_SIZE*1K - CONFIG_SHARED_GDT_RAM_SIZE +#define PHYS_RAM_SIZE DT_RAM_SIZE*1K - CONFIG_SHARED_GDT_RAM_SIZE #endif MEMORY { #ifdef CONFIG_XIP - ROM (rx) : ORIGIN = PHYS_LOAD_ADDR, LENGTH = CONFIG_ROM_SIZE*1K + ROM (rx) : ORIGIN = PHYS_LOAD_ADDR, LENGTH = DT_ROM_SIZE*1K RAM (wx) : ORIGIN = PHYS_RAM_ADDR, LENGTH = PHYS_RAM_SIZE #else /* !CONFIG_XIP */ RAM (wx) : ORIGIN = PHYS_LOAD_ADDR, LENGTH = PHYS_RAM_SIZE diff --git a/soc/x86/intel_quark/quark_d2000/soc.h b/soc/x86/intel_quark/quark_d2000/soc.h index 3660807f5ed..1a50af438db 100644 --- a/soc/x86/intel_quark/quark_d2000/soc.h +++ b/soc/x86/intel_quark/quark_d2000/soc.h @@ -50,7 +50,7 @@ #define SPI_DW_PORT_0_INT_MASK (SCSS_REGISTER_BASE + 0x454) -#define SPI_DW_IRQ_FLAGS (IOAPIC_LEVEL | IOAPIC_HIGH) +#define DT_SPI_DW_IRQ_FLAGS (IOAPIC_LEVEL | IOAPIC_HIGH) #endif diff --git a/soc/x86/intel_quark/quark_se/dts_fixup.h b/soc/x86/intel_quark/quark_se/dts_fixup.h index 955268dcba3..f3dddff8945 100644 --- a/soc/x86/intel_quark/quark_se/dts_fixup.h +++ b/soc/x86/intel_quark/quark_se/dts_fixup.h @@ -1,70 +1,70 @@ /* SoC level DTS fixup file */ -#define CONFIG_UART_QMSI_0_BAUDRATE DT_INTEL_QMSI_UART_B0002000_CURRENT_SPEED -#define CONFIG_UART_QMSI_0_NAME DT_INTEL_QMSI_UART_B0002000_LABEL -#define CONFIG_UART_QMSI_0_IRQ DT_INTEL_QMSI_UART_B0002000_IRQ_0 +#define DT_UART_QMSI_0_BAUDRATE DT_INTEL_QMSI_UART_B0002000_CURRENT_SPEED +#define DT_UART_QMSI_0_NAME DT_INTEL_QMSI_UART_B0002000_LABEL +#define DT_UART_QMSI_0_IRQ DT_INTEL_QMSI_UART_B0002000_IRQ_0 #define CONFIG_UART_QMSI_0_IRQ_PRI DT_INTEL_QMSI_UART_B0002000_IRQ_0_PRIORITY -#define CONFIG_UART_QMSI_0_IRQ_FLAGS DT_INTEL_QMSI_UART_B0002000_IRQ_0_SENSE +#define DT_UART_QMSI_0_IRQ_FLAGS DT_INTEL_QMSI_UART_B0002000_IRQ_0_SENSE -#define CONFIG_UART_QMSI_1_BAUDRATE DT_INTEL_QMSI_UART_B0002400_CURRENT_SPEED -#define CONFIG_UART_QMSI_1_NAME DT_INTEL_QMSI_UART_B0002400_LABEL -#define CONFIG_UART_QMSI_1_IRQ DT_INTEL_QMSI_UART_B0002400_IRQ_0 +#define DT_UART_QMSI_1_BAUDRATE DT_INTEL_QMSI_UART_B0002400_CURRENT_SPEED +#define DT_UART_QMSI_1_NAME DT_INTEL_QMSI_UART_B0002400_LABEL +#define DT_UART_QMSI_1_IRQ DT_INTEL_QMSI_UART_B0002400_IRQ_0 #define CONFIG_UART_QMSI_1_IRQ_PRI DT_INTEL_QMSI_UART_B0002400_IRQ_0_PRIORITY -#define CONFIG_UART_QMSI_1_IRQ_FLAGS DT_INTEL_QMSI_UART_B0002400_IRQ_0_SENSE +#define DT_UART_QMSI_1_IRQ_FLAGS DT_INTEL_QMSI_UART_B0002400_IRQ_0_SENSE -#define CONFIG_PHYS_RAM_ADDR CONFIG_SRAM_BASE_ADDRESS +#define DT_PHYS_RAM_ADDR CONFIG_SRAM_BASE_ADDRESS -#define CONFIG_PHYS_LOAD_ADDR CONFIG_FLASH_BASE_ADDRESS +#define DT_PHYS_LOAD_ADDR CONFIG_FLASH_BASE_ADDRESS -#define CONFIG_RAM_SIZE CONFIG_SRAM_SIZE +#define DT_RAM_SIZE CONFIG_SRAM_SIZE -#define CONFIG_ROM_SIZE CONFIG_FLASH_SIZE +#define DT_ROM_SIZE CONFIG_FLASH_SIZE -#define CONFIG_IOAPIC_BASE_ADDRESS DT_INTEL_IOAPIC_FEC00000_BASE_ADDRESS +#define DT_IOAPIC_BASE_ADDRESS DT_INTEL_IOAPIC_FEC00000_BASE_ADDRESS #define CONFIG_I2C_0_NAME DT_INTEL_QMSI_I2C_B0002800_LABEL -#define CONFIG_I2C_0_BITRATE DT_INTEL_QMSI_I2C_B0002800_CLOCK_FREQUENCY -#define CONFIG_I2C_0_IRQ DT_INTEL_QMSI_I2C_B0002800_IRQ_0 +#define DT_I2C_0_BITRATE DT_INTEL_QMSI_I2C_B0002800_CLOCK_FREQUENCY +#define DT_I2C_0_IRQ DT_INTEL_QMSI_I2C_B0002800_IRQ_0 #define CONFIG_I2C_0_IRQ_PRI DT_INTEL_QMSI_I2C_B0002800_IRQ_0_PRIORITY -#define CONFIG_I2C_0_IRQ_FLAGS DT_INTEL_QMSI_I2C_B0002800_IRQ_0_SENSE +#define DT_I2C_0_IRQ_FLAGS DT_INTEL_QMSI_I2C_B0002800_IRQ_0_SENSE #define CONFIG_I2C_1_NAME DT_INTEL_QMSI_I2C_B0002C00_LABEL -#define CONFIG_I2C_1_BITRATE DT_INTEL_QMSI_I2C_B0002C00_CLOCK_FREQUENCY -#define CONFIG_I2C_1_IRQ DT_INTEL_QMSI_I2C_B0002C00_IRQ_0 +#define DT_I2C_1_BITRATE DT_INTEL_QMSI_I2C_B0002C00_CLOCK_FREQUENCY +#define DT_I2C_1_IRQ DT_INTEL_QMSI_I2C_B0002C00_IRQ_0 #define CONFIG_I2C_1_IRQ_PRI DT_INTEL_QMSI_I2C_B0002C00_IRQ_0_PRIORITY -#define CONFIG_I2C_1_IRQ_FLAGS DT_INTEL_QMSI_I2C_B0002C00_IRQ_0_SENSE +#define DT_I2C_1_IRQ_FLAGS DT_INTEL_QMSI_I2C_B0002C00_IRQ_0_SENSE -#define CONFIG_GPIO_QMSI_0_NAME DT_INTEL_QMSI_GPIO_B0000C00_LABEL -#define CONFIG_GPIO_QMSI_0_IRQ DT_INTEL_QMSI_GPIO_B0000C00_IRQ_0 +#define DT_GPIO_QMSI_0_NAME DT_INTEL_QMSI_GPIO_B0000C00_LABEL +#define DT_GPIO_QMSI_0_IRQ DT_INTEL_QMSI_GPIO_B0000C00_IRQ_0 #define CONFIG_GPIO_QMSI_0_IRQ_PRI DT_INTEL_QMSI_GPIO_B0000C00_IRQ_0_PRIORITY -#define CONFIG_GPIO_QMSI_0_IRQ_FLAGS DT_INTEL_QMSI_GPIO_B0000C00_IRQ_0_SENSE -#define CONFIG_GPIO_QMSI_1_NAME DT_INTEL_QMSI_GPIO_B0800B00_LABEL -#define CONFIG_GPIO_QMSI_1_IRQ DT_INTEL_QMSI_GPIO_B0800B00_IRQ_0 -#define CONFIG_GPIO_QMSI_1_IRQ_PRI DT_INTEL_QMSI_GPIO_B0800B00_IRQ_0_PRIORITY -#define CONFIG_GPIO_QMSI_1_IRQ_FLAGS DT_INTEL_QMSI_GPIO_B0800B00_IRQ_0_SENSE +#define DT_GPIO_QMSI_0_IRQ_FLAGS DT_INTEL_QMSI_GPIO_B0000C00_IRQ_0_SENSE +#define DT_GPIO_QMSI_1_NAME DT_INTEL_QMSI_GPIO_B0800B00_LABEL +#define DT_GPIO_QMSI_1_IRQ DT_INTEL_QMSI_GPIO_B0800B00_IRQ_0 +#define DT_GPIO_QMSI_1_IRQ_PRI DT_INTEL_QMSI_GPIO_B0800B00_IRQ_0_PRIORITY +#define DT_GPIO_QMSI_1_IRQ_FLAGS DT_INTEL_QMSI_GPIO_B0800B00_IRQ_0_SENSE #define CONFIG_RTC_0_NAME DT_INTEL_QMSI_RTC_B0000400_LABEL -#define CONFIG_RTC_0_IRQ DT_INTEL_QMSI_RTC_B0000400_IRQ_0 +#define DT_RTC_0_IRQ DT_INTEL_QMSI_RTC_B0000400_IRQ_0 #define CONFIG_RTC_0_IRQ_PRI DT_INTEL_QMSI_RTC_B0000400_IRQ_0_PRIORITY -#define CONFIG_RTC_0_IRQ_FLAGS DT_INTEL_QMSI_RTC_B0000400_IRQ_0_SENSE +#define DT_RTC_0_IRQ_FLAGS DT_INTEL_QMSI_RTC_B0000400_IRQ_0_SENSE -#define CONFIG_SPI_0_BASE_ADDRESS DT_SNPS_DESIGNWARE_SPI_B0001000_BASE_ADDRESS +#define DT_SPI_0_BASE_ADDRESS DT_SNPS_DESIGNWARE_SPI_B0001000_BASE_ADDRESS #define CONFIG_SPI_0_NAME DT_SNPS_DESIGNWARE_SPI_B0001000_LABEL -#define CONFIG_SPI_0_IRQ DT_SNPS_DESIGNWARE_SPI_B0001000_IRQ_0 +#define DT_SPI_0_IRQ DT_SNPS_DESIGNWARE_SPI_B0001000_IRQ_0 #define CONFIG_SPI_0_IRQ_PRI DT_SNPS_DESIGNWARE_SPI_B0001000_IRQ_0_PRIORITY -#define CONFIG_SPI_1_BASE_ADDRESS DT_SNPS_DESIGNWARE_SPI_B0001400_BASE_ADDRESS +#define DT_SPI_1_BASE_ADDRESS DT_SNPS_DESIGNWARE_SPI_B0001400_BASE_ADDRESS #define CONFIG_SPI_1_NAME DT_SNPS_DESIGNWARE_SPI_B0001400_LABEL -#define CONFIG_SPI_1_IRQ DT_SNPS_DESIGNWARE_SPI_B0001400_IRQ_0 +#define DT_SPI_1_IRQ DT_SNPS_DESIGNWARE_SPI_B0001400_IRQ_0 #define CONFIG_SPI_1_IRQ_PRI DT_SNPS_DESIGNWARE_SPI_B0001400_IRQ_0_PRIORITY -#define CONFIG_SPI_2_BASE_ADDRESS DT_SNPS_DESIGNWARE_SPI_B0001800_BASE_ADDRESS +#define DT_SPI_2_BASE_ADDRESS DT_SNPS_DESIGNWARE_SPI_B0001800_BASE_ADDRESS #define CONFIG_SPI_2_NAME DT_SNPS_DESIGNWARE_SPI_B0001800_LABEL -#define CONFIG_SPI_2_IRQ DT_SNPS_DESIGNWARE_SPI_B0001800_IRQ_0 +#define DT_SPI_2_IRQ DT_SNPS_DESIGNWARE_SPI_B0001800_IRQ_0 #define CONFIG_SPI_2_IRQ_PRI DT_SNPS_DESIGNWARE_SPI_B0001800_IRQ_0_PRIORITY #define CONFIG_WDT_0_NAME DT_INTEL_QMSI_WATCHDOG_B0000000_LABEL -#define CONFIG_WDT_0_IRQ DT_INTEL_QMSI_WATCHDOG_B0000000_IRQ_0 -#define CONFIG_WDT_0_IRQ_PRI DT_INTEL_QMSI_WATCHDOG_B0000000_IRQ_0_PRIORITY -#define CONFIG_WDT_0_IRQ_FLAGS DT_INTEL_QMSI_WATCHDOG_B0000000_IRQ_0_SENSE +#define DT_WDT_0_IRQ DT_INTEL_QMSI_WATCHDOG_B0000000_IRQ_0 +#define DT_WDT_0_IRQ_PRI DT_INTEL_QMSI_WATCHDOG_B0000000_IRQ_0_PRIORITY +#define DT_WDT_0_IRQ_FLAGS DT_INTEL_QMSI_WATCHDOG_B0000000_IRQ_0_SENSE /* End of SoC Level DTS fixup file */ diff --git a/soc/x86/intel_quark/quark_se/eoi.c b/soc/x86/intel_quark/quark_se/eoi.c index 742aea98484..3fe952bba69 100644 --- a/soc/x86/intel_quark/quark_se/eoi.c +++ b/soc/x86/intel_quark/quark_se/eoi.c @@ -27,7 +27,7 @@ void _lakemont_eoi(void) * write to IOAPIC_EOI for every interrupt */ sys_write32(_irq_controller_isr_vector_get(), - CONFIG_IOAPIC_BASE_ADDRESS + IOAPIC_EOI); + DT_IOAPIC_BASE_ADDRESS + IOAPIC_EOI); /* Send EOI to the LOAPIC as well */ sys_write32(0, CONFIG_LOAPIC_BASE_ADDRESS + LOAPIC_EOI); diff --git a/soc/x86/intel_quark/quark_se/linker.ld b/soc/x86/intel_quark/quark_se/linker.ld index ae8236fa4bb..5795419f684 100644 --- a/soc/x86/intel_quark/quark_se/linker.ld +++ b/soc/x86/intel_quark/quark_se/linker.ld @@ -15,13 +15,13 @@ #include /* physical address of RAM (needed for correct __ram_phys_end symbol) */ -#define PHYS_RAM_ADDR CONFIG_PHYS_RAM_ADDR +#define PHYS_RAM_ADDR DT_PHYS_RAM_ADDR /* physical address where the kernel is loaded */ #ifdef CONFIG_XIP - #define PHYS_LOAD_ADDR CONFIG_PHYS_LOAD_ADDR + #define PHYS_LOAD_ADDR DT_PHYS_LOAD_ADDR #else /* !CONFIG_XIP */ - #define PHYS_LOAD_ADDR CONFIG_PHYS_RAM_ADDR + #define PHYS_LOAD_ADDR DT_PHYS_RAM_ADDR #endif /* CONFIG_XIP */ /* total shared RAM size (restore info + gdt) */ @@ -33,19 +33,19 @@ * contiguous unused memory located at the end of RAM should be made available. */ #ifdef CONFIG_SYS_POWER_DEEP_SLEEP -#define PHYS_RAM_SIZE CONFIG_RAM_SIZE*1K - BSP_SHARED_RAM_SIZE +#define PHYS_RAM_SIZE DT_RAM_SIZE*1K - BSP_SHARED_RAM_SIZE #else #ifdef CONFIG_SET_GDT -#define PHYS_RAM_SIZE CONFIG_RAM_SIZE*1K +#define PHYS_RAM_SIZE DT_RAM_SIZE*1K #else -#define PHYS_RAM_SIZE CONFIG_RAM_SIZE*1K - CONFIG_SHARED_GDT_RAM_SIZE +#define PHYS_RAM_SIZE DT_RAM_SIZE*1K - CONFIG_SHARED_GDT_RAM_SIZE #endif #endif MEMORY { #ifdef CONFIG_XIP - ROM (rx) : ORIGIN = PHYS_LOAD_ADDR, LENGTH = CONFIG_ROM_SIZE*1K + ROM (rx) : ORIGIN = PHYS_LOAD_ADDR, LENGTH = DT_ROM_SIZE*1K RAM (wx) : ORIGIN = PHYS_RAM_ADDR, LENGTH = PHYS_RAM_SIZE #else /* !CONFIG_XIP */ RAM (wx) : ORIGIN = PHYS_LOAD_ADDR, LENGTH = PHYS_RAM_SIZE diff --git a/soc/x86/intel_quark/quark_se/soc.c b/soc/x86/intel_quark/quark_se/soc.c index a6f59181930..85d452ca55b 100644 --- a/soc/x86/intel_quark/quark_se/soc.c +++ b/soc/x86/intel_quark/quark_se/soc.c @@ -32,7 +32,7 @@ LOG_MODULE_REGISTER(soc); MMU_BOOT_REGION(CONFIG_LOAPIC_BASE_ADDRESS, 4*1024, MMU_ENTRY_WRITE); /*ioapic */ -MMU_BOOT_REGION(CONFIG_IOAPIC_BASE_ADDRESS, 1024*1024, MMU_ENTRY_WRITE); +MMU_BOOT_REGION(DT_IOAPIC_BASE_ADDRESS, 1024*1024, MMU_ENTRY_WRITE); /* peripherals */ MMU_BOOT_REGION(0xB0000000, 128*1024, MMU_ENTRY_WRITE); diff --git a/soc/x86/intel_quark/quark_se/soc.h b/soc/x86/intel_quark/quark_se/soc.h index e69f57f25ac..adf2c021479 100644 --- a/soc/x86/intel_quark/quark_se/soc.h +++ b/soc/x86/intel_quark/quark_se/soc.h @@ -70,7 +70,7 @@ #define SPI_DW_PORT_2_INT_MASK (SCSS_REGISTER_BASE + 0x45C) -#define SPI_DW_IRQ_FLAGS (IOAPIC_LEVEL | IOAPIC_HIGH) +#define DT_SPI_DW_IRQ_FLAGS (IOAPIC_LEVEL | IOAPIC_HIGH) #endif /* CONFIG_SPI_DW */ diff --git a/soc/x86/intel_quark/quark_x1000/dts_fixup.h b/soc/x86/intel_quark/quark_x1000/dts_fixup.h index 3e3255e465c..281d33d9f9e 100644 --- a/soc/x86/intel_quark/quark_x1000/dts_fixup.h +++ b/soc/x86/intel_quark/quark_x1000/dts_fixup.h @@ -1,43 +1,43 @@ -#define CONFIG_UART_NS16550_PORT_0_BASE_ADDR DT_NS16550_9000F000_BASE_ADDRESS +#define DT_UART_NS16550_PORT_0_BASE_ADDR DT_NS16550_9000F000_BASE_ADDRESS #define CONFIG_UART_NS16550_PORT_0_BAUD_RATE DT_NS16550_9000F000_CURRENT_SPEED #define CONFIG_UART_NS16550_PORT_0_NAME DT_NS16550_9000F000_LABEL -#define CONFIG_UART_NS16550_PORT_0_IRQ DT_NS16550_9000F000_IRQ_0 +#define DT_UART_NS16550_PORT_0_IRQ DT_NS16550_9000F000_IRQ_0 #define CONFIG_UART_NS16550_PORT_0_IRQ_PRI DT_NS16550_9000F000_IRQ_0_PRIORITY -#define CONFIG_UART_NS16550_PORT_0_IRQ_FLAGS DT_NS16550_9000F000_IRQ_0_SENSE -#define CONFIG_UART_NS16550_PORT_0_CLK_FREQ DT_NS16550_9000F000_CLOCK_FREQUENCY +#define DT_UART_NS16550_PORT_0_IRQ_FLAGS DT_NS16550_9000F000_IRQ_0_SENSE +#define DT_UART_NS16550_PORT_0_CLK_FREQ DT_NS16550_9000F000_CLOCK_FREQUENCY -#define CONFIG_UART_NS16550_PORT_1_BASE_ADDR DT_NS16550_9000B000_BASE_ADDRESS +#define DT_UART_NS16550_PORT_1_BASE_ADDR DT_NS16550_9000B000_BASE_ADDRESS #define CONFIG_UART_NS16550_PORT_1_BAUD_RATE DT_NS16550_9000B000_CURRENT_SPEED #define CONFIG_UART_NS16550_PORT_1_NAME DT_NS16550_9000B000_LABEL -#define CONFIG_UART_NS16550_PORT_1_IRQ DT_NS16550_9000B000_IRQ_0 +#define DT_UART_NS16550_PORT_1_IRQ DT_NS16550_9000B000_IRQ_0 #define CONFIG_UART_NS16550_PORT_1_IRQ_PRI DT_NS16550_9000B000_IRQ_0_PRIORITY -#define CONFIG_UART_NS16550_PORT_1_IRQ_FLAGS DT_NS16550_9000B000_IRQ_0_SENSE -#define CONFIG_UART_NS16550_PORT_1_CLK_FREQ DT_NS16550_9000B000_CLOCK_FREQUENCY +#define DT_UART_NS16550_PORT_1_IRQ_FLAGS DT_NS16550_9000B000_IRQ_0_SENSE +#define DT_UART_NS16550_PORT_1_CLK_FREQ DT_NS16550_9000B000_CLOCK_FREQUENCY -#define CONFIG_PHYS_RAM_ADDR CONFIG_SRAM_BASE_ADDRESS +#define DT_PHYS_RAM_ADDR CONFIG_SRAM_BASE_ADDRESS -#define CONFIG_PHYS_LOAD_ADDR CONFIG_FLASH_BASE_ADDRESS +#define DT_PHYS_LOAD_ADDR CONFIG_FLASH_BASE_ADDRESS -#define CONFIG_RAM_SIZE CONFIG_SRAM_SIZE +#define DT_RAM_SIZE CONFIG_SRAM_SIZE -#define CONFIG_ROM_SIZE CONFIG_FLASH_SIZE +#define DT_ROM_SIZE CONFIG_FLASH_SIZE -#define CONFIG_IOAPIC_BASE_ADDRESS DT_INTEL_IOAPIC_FEC00000_BASE_ADDRESS +#define DT_IOAPIC_BASE_ADDRESS DT_INTEL_IOAPIC_FEC00000_BASE_ADDRESS -#define CONFIG_I2C_0_IRQ DT_SNPS_DESIGNWARE_I2C_90007000_IRQ_0 -#define CONFIG_I2C_0_IRQ_FLAGS DT_SNPS_DESIGNWARE_I2C_90007000_IRQ_0_SENSE -#define CONFIG_I2C_0_BASE_ADDR DT_SNPS_DESIGNWARE_I2C_90007000_BASE_ADDRESS +#define DT_I2C_0_IRQ DT_SNPS_DESIGNWARE_I2C_90007000_IRQ_0 +#define DT_I2C_0_IRQ_FLAGS DT_SNPS_DESIGNWARE_I2C_90007000_IRQ_0_SENSE +#define DT_I2C_0_BASE_ADDR DT_SNPS_DESIGNWARE_I2C_90007000_BASE_ADDRESS #define CONFIG_I2C_0_NAME DT_SNPS_DESIGNWARE_I2C_90007000_LABEL -#define CONFIG_I2C_0_BITRATE DT_SNPS_DESIGNWARE_I2C_90007000_CLOCK_FREQUENCY +#define DT_I2C_0_BITRATE DT_SNPS_DESIGNWARE_I2C_90007000_CLOCK_FREQUENCY -#define CONFIG_SPI_0_BASE_ADDRESS DT_INTEL_INTEL_SPI_90009000_BASE_ADDRESS -#define CONFIG_SPI_0_IRQ DT_INTEL_INTEL_SPI_90009000_IRQ_0 -#define CONFIG_SPI_0_IRQ_FLAGS DT_INTEL_INTEL_SPI_90009000_IRQ_0_SENSE +#define DT_SPI_0_BASE_ADDRESS DT_INTEL_INTEL_SPI_90009000_BASE_ADDRESS +#define DT_SPI_0_IRQ DT_INTEL_INTEL_SPI_90009000_IRQ_0 +#define DT_SPI_0_IRQ_FLAGS DT_INTEL_INTEL_SPI_90009000_IRQ_0_SENSE #define CONFIG_SPI_0_IRQ_PRI DT_INTEL_INTEL_SPI_90009000_IRQ_0_PRIORITY #define CONFIG_SPI_0_NAME DT_INTEL_INTEL_SPI_90009000_LABEL -#define CONFIG_SPI_1_BASE_ADDRESS DT_INTEL_INTEL_SPI_90008000_BASE_ADDRESS -#define CONFIG_SPI_1_IRQ DT_INTEL_INTEL_SPI_90008000_IRQ_0 -#define CONFIG_SPI_1_IRQ_FLAGS DT_INTEL_INTEL_SPI_90008000_IRQ_0_SENSE +#define DT_SPI_1_BASE_ADDRESS DT_INTEL_INTEL_SPI_90008000_BASE_ADDRESS +#define DT_SPI_1_IRQ DT_INTEL_INTEL_SPI_90008000_IRQ_0 +#define DT_SPI_1_IRQ_FLAGS DT_INTEL_INTEL_SPI_90008000_IRQ_0_SENSE #define CONFIG_SPI_1_IRQ_PRI DT_INTEL_INTEL_SPI_90008000_IRQ_0_PRIORITY #define CONFIG_SPI_1_NAME DT_INTEL_INTEL_SPI_90008000_LABEL diff --git a/soc/x86/intel_quark/quark_x1000/linker.ld b/soc/x86/intel_quark/quark_x1000/linker.ld index 3bd1d644494..e64c3df231b 100644 --- a/soc/x86/intel_quark/quark_x1000/linker.ld +++ b/soc/x86/intel_quark/quark_x1000/linker.ld @@ -15,11 +15,11 @@ #include /* physical address where the kernel is loaded */ -#define PHYS_LOAD_ADDR CONFIG_PHYS_LOAD_ADDR +#define PHYS_LOAD_ADDR DT_PHYS_LOAD_ADDR /* physical address of RAM */ #ifdef CONFIG_XIP - #define PHYS_RAM_ADDR CONFIG_PHYS_RAM_ADDR + #define PHYS_RAM_ADDR DT_PHYS_RAM_ADDR #else /* !CONFIG_XIP */ #define PHYS_RAM_ADDR PHYS_LOAD_ADDR #endif /* CONFIG_XIP */ @@ -27,10 +27,10 @@ MEMORY { #ifdef CONFIG_XIP - ROM (rx) : ORIGIN = PHYS_LOAD_ADDR, LENGTH = CONFIG_ROM_SIZE*1K - RAM (wx) : ORIGIN = PHYS_RAM_ADDR, LENGTH = CONFIG_RAM_SIZE*1K + ROM (rx) : ORIGIN = PHYS_LOAD_ADDR, LENGTH = DT_ROM_SIZE*1K + RAM (wx) : ORIGIN = PHYS_RAM_ADDR, LENGTH = DT_RAM_SIZE*1K #else /* !CONFIG_XIP */ - RAM (wx) : ORIGIN = PHYS_LOAD_ADDR, LENGTH = CONFIG_RAM_SIZE*1K + RAM (wx) : ORIGIN = PHYS_LOAD_ADDR, LENGTH = DT_RAM_SIZE*1K #endif /* CONFIG_XIP */ /* diff --git a/soc/x86/intel_quark/quark_x1000/soc.h b/soc/x86/intel_quark/quark_x1000/soc.h index 1591d236ffa..1d4a62bd331 100644 --- a/soc/x86/intel_quark/quark_x1000/soc.h +++ b/soc/x86/intel_quark/quark_x1000/soc.h @@ -72,9 +72,9 @@ #define GPIO_DW_PCI_DEVICE_ID 0x0934 #define GPIO_DW_PCI_CLASS 0x0C -#define GPIO_DW_0_BASE_ADDR 0x90006000 -#define GPIO_DW_0_IRQ 18 -#define GPIO_DW_0_BITS 8 +#define DT_GPIO_DW_0_BASE_ADDR 0x90006000 +#define DT_GPIO_DW_0_IRQ 18 +#define DT_GPIO_DW_0_BITS 8 #define GPIO_DW_0_PCI_BUS 0 #define GPIO_DW_0_PCI_DEV 21 @@ -82,7 +82,7 @@ #define GPIO_DW_0_PCI_BAR 1 #if defined(CONFIG_IOAPIC) -#define GPIO_DW_0_IRQ_FLAGS (IOAPIC_LEVEL | IOAPIC_LOW) +#define DT_GPIO_DW_0_IRQ_FLAGS (IOAPIC_LEVEL | IOAPIC_LOW) #endif /* diff --git a/soc/xtensa/intel_s1000/dts_fixup.h b/soc/xtensa/intel_s1000/dts_fixup.h index 630bcb618ee..d2b981aae7e 100644 --- a/soc/xtensa/intel_s1000/dts_fixup.h +++ b/soc/xtensa/intel_s1000/dts_fixup.h @@ -1,49 +1,49 @@ /* SoC level DTS fixup file */ -#define CONFIG_UART_NS16550_PORT_0_BASE_ADDR NS16550_80800_BASE_ADDRESS +#define DT_UART_NS16550_PORT_0_BASE_ADDR NS16550_80800_BASE_ADDRESS #define CONFIG_UART_NS16550_PORT_0_BAUD_RATE NS16550_80800_CURRENT_SPEED #define CONFIG_UART_NS16550_PORT_0_NAME NS16550_80800_LABEL -#define CONFIG_UART_NS16550_PORT_0_IRQ ((NS16550_80800_IRQ_0 << 16) | \ +#define DT_UART_NS16550_PORT_0_IRQ ((NS16550_80800_IRQ_0 << 16) | \ (SNPS_DESIGNWARE_INTC_81800_IRQ_0 << 8) | \ (INTEL_CAVS_INTC_78800_IRQ_0 << 0)) #define CONFIG_UART_NS16550_PORT_0_IRQ_PRI NS16550_80800_IRQ_0_PRIORITY -#define CONFIG_UART_NS16550_PORT_0_IRQ_FLAGS NS16550_80800_IRQ_0_SENSE -#define CONFIG_UART_NS16550_PORT_0_CLK_FREQ NS16550_80800_CLOCK_FREQUENCY +#define DT_UART_NS16550_PORT_0_IRQ_FLAGS NS16550_80800_IRQ_0_SENSE +#define DT_UART_NS16550_PORT_0_CLK_FREQ NS16550_80800_CLOCK_FREQUENCY -#define L2_SRAM_BASE CONFIG_SRAM_BASE_ADDRESS -#define L2_SRAM_SIZE CONFIG_SRAM_SIZE * 1024 +#define DT_L2_SRAM_BASE CONFIG_SRAM_BASE_ADDRESS +#define DT_L2_SRAM_SIZE CONFIG_SRAM_SIZE * 1024 -#define CAVS_ICTL_BASE_ADDR INTEL_CAVS_INTC_78800_BASE_ADDRESS -#define CAVS_ICTL_0_IRQ INTEL_CAVS_INTC_78800_IRQ_0 -#define CONFIG_CAVS_ICTL_0_IRQ_PRI INTEL_CAVS_INTC_78800_IRQ_0_PRIORITY -#define CAVS_ICTL_0_IRQ_FLAGS INTEL_CAVS_INTC_78800_IRQ_0_SENSE +#define DT_CAVS_ICTL_BASE_ADDR INTEL_CAVS_INTC_78800_BASE_ADDRESS +#define DT_CAVS_ICTL_0_IRQ INTEL_CAVS_INTC_78800_IRQ_0 +#define DT_CAVS_ICTL_0_IRQ_PRI INTEL_CAVS_INTC_78800_IRQ_0_PRIORITY +#define DT_CAVS_ICTL_0_IRQ_FLAGS INTEL_CAVS_INTC_78800_IRQ_0_SENSE -#define CAVS_ICTL_1_IRQ INTEL_CAVS_INTC_78810_IRQ_0 -#define CONFIG_CAVS_ICTL_1_IRQ_PRI INTEL_CAVS_INTC_78810_IRQ_0_PRIORITY -#define CAVS_ICTL_1_IRQ_FLAGS INTEL_CAVS_INTC_78810_IRQ_0_SENSE +#define DT_CAVS_ICTL_1_IRQ INTEL_CAVS_INTC_78810_IRQ_0 +#define DT_CAVS_ICTL_1_IRQ_PRI INTEL_CAVS_INTC_78810_IRQ_0_PRIORITY +#define DT_CAVS_ICTL_1_IRQ_FLAGS INTEL_CAVS_INTC_78810_IRQ_0_SENSE -#define CAVS_ICTL_2_IRQ INTEL_CAVS_INTC_78820_IRQ_0 -#define CONFIG_CAVS_ICTL_2_IRQ_PRI INTEL_CAVS_INTC_78820_IRQ_0_PRIORITY -#define CAVS_ICTL_2_IRQ_FLAGS INTEL_CAVS_INTC_78820_IRQ_0_SENSE +#define DT_CAVS_ICTL_2_IRQ INTEL_CAVS_INTC_78820_IRQ_0 +#define DT_CAVS_ICTL_2_IRQ_PRI INTEL_CAVS_INTC_78820_IRQ_0_PRIORITY +#define DT_CAVS_ICTL_2_IRQ_FLAGS INTEL_CAVS_INTC_78820_IRQ_0_SENSE -#define CAVS_ICTL_3_IRQ INTEL_CAVS_INTC_78830_IRQ_0 -#define CONFIG_CAVS_ICTL_3_IRQ_PRI INTEL_CAVS_INTC_78830_IRQ_0_PRIORITY -#define CAVS_ICTL_3_IRQ_FLAGS INTEL_CAVS_INTC_78830_IRQ_0_SENSE +#define DT_CAVS_ICTL_3_IRQ INTEL_CAVS_INTC_78830_IRQ_0 +#define DT_CAVS_ICTL_3_IRQ_PRI INTEL_CAVS_INTC_78830_IRQ_0_PRIORITY +#define DT_CAVS_ICTL_3_IRQ_FLAGS INTEL_CAVS_INTC_78830_IRQ_0_SENSE -#define DW_ICTL_BASE_ADDR SNPS_DESIGNWARE_INTC_81800_BASE_ADDRESS -#define DW_ICTL_IRQ ((SNPS_DESIGNWARE_INTC_81800_IRQ_0 << 8) | \ +#define DT_DW_ICTL_BASE_ADDR SNPS_DESIGNWARE_INTC_81800_BASE_ADDRESS +#define DT_DW_ICTL_IRQ ((SNPS_DESIGNWARE_INTC_81800_IRQ_0 << 8) | \ (INTEL_CAVS_INTC_78800_IRQ_0 << 0)) -#define CONFIG_DW_ICTL_IRQ_PRI SNPS_DESIGNWARE_INTC_81800_IRQ_0_PRIORITY -#define DW_ICTL_IRQ_FLAGS SNPS_DESIGNWARE_INTC_81800_IRQ_0_SENSE +#define DT_DW_ICTL_IRQ_PRI SNPS_DESIGNWARE_INTC_81800_IRQ_0_PRIORITY +#define DT_DW_ICTL_IRQ_FLAGS SNPS_DESIGNWARE_INTC_81800_IRQ_0_SENSE -#define CONFIG_I2C_0_BASE_ADDR SNPS_DESIGNWARE_I2C_80400_BASE_ADDRESS -#define CONFIG_I2C_0_BITRATE SNPS_DESIGNWARE_I2C_80400_CLOCK_FREQUENCY +#define DT_I2C_0_BASE_ADDR SNPS_DESIGNWARE_I2C_80400_BASE_ADDRESS +#define DT_I2C_0_BITRATE SNPS_DESIGNWARE_I2C_80400_CLOCK_FREQUENCY #define CONFIG_I2C_0_NAME SNPS_DESIGNWARE_I2C_80400_LABEL -#define CONFIG_I2C_0_IRQ ((SNPS_DESIGNWARE_I2C_80400_IRQ_0 << 16) | \ +#define DT_I2C_0_IRQ ((SNPS_DESIGNWARE_I2C_80400_IRQ_0 << 16) | \ (SNPS_DESIGNWARE_INTC_81800_IRQ_0 << 8) | \ (INTEL_CAVS_INTC_78800_IRQ_0 << 0)) -#define CONFIG_I2C_0_IRQ_FLAGS SNPS_DESIGNWARE_I2C_80400_IRQ_0_SENSE +#define DT_I2C_0_IRQ_FLAGS SNPS_DESIGNWARE_I2C_80400_IRQ_0_SENSE #define CONFIG_I2C_0_IRQ_PRI SNPS_DESIGNWARE_I2C_80400_IRQ_0_PRIORITY /* End of SoC Level DTS fixup file */ diff --git a/soc/xtensa/intel_s1000/linker.ld b/soc/xtensa/intel_s1000/linker.ld index 28670ea95f8..1e126b71bf9 100644 --- a/soc/xtensa/intel_s1000/linker.ld +++ b/soc/xtensa/intel_s1000/linker.ld @@ -419,7 +419,7 @@ SECTIONS /* stack */ _end = ALIGN(8); PROVIDE(end = ALIGN(8)); - __stack = L2_SRAM_BASE + L2_SRAM_SIZE; + __stack = DT_L2_SRAM_BASE + DT_L2_SRAM_SIZE; .comment 0 : { *(.comment) } .debug 0 : { *(.debug) } .line 0 : { *(.line) } diff --git a/soc/xtensa/intel_s1000/memory.h b/soc/xtensa/intel_s1000/memory.h index 2373698a6e9..5739a655c86 100644 --- a/soc/xtensa/intel_s1000/memory.h +++ b/soc/xtensa/intel_s1000/memory.h @@ -10,26 +10,26 @@ #define L2_VECTOR_SIZE 0x1000 /* The reset vector address in SRAM and its size */ -#define XCHAL_RESET_VECTOR0_PADDR_SRAM L2_SRAM_BASE +#define XCHAL_RESET_VECTOR0_PADDR_SRAM DT_L2_SRAM_BASE #define MEM_RESET_TEXT_SIZE 0x268 #define MEM_RESET_LIT_SIZE 0x8 /* This is the base address of all the vectors defined in SRAM */ -#define XCHAL_VECBASE_RESET_PADDR_SRAM (L2_SRAM_BASE + 0x400) +#define XCHAL_VECBASE_RESET_PADDR_SRAM (DT_L2_SRAM_BASE + 0x400) #define MEM_VECBASE_LIT_SIZE 0x178 /* The addresses of the vectors in SRAM. * Only the memerror vector continues to point to its ROM address. */ -#define XCHAL_INTLEVEL2_VECTOR_PADDR_SRAM (L2_SRAM_BASE + 0x580) -#define XCHAL_INTLEVEL3_VECTOR_PADDR_SRAM (L2_SRAM_BASE + 0x5C0) -#define XCHAL_INTLEVEL4_VECTOR_PADDR_SRAM (L2_SRAM_BASE + 0x600) -#define XCHAL_INTLEVEL5_VECTOR_PADDR_SRAM (L2_SRAM_BASE + 0x640) -#define XCHAL_INTLEVEL6_VECTOR_PADDR_SRAM (L2_SRAM_BASE + 0x680) -#define XCHAL_INTLEVEL7_VECTOR_PADDR_SRAM (L2_SRAM_BASE + 0x6C0) -#define XCHAL_KERNEL_VECTOR_PADDR_SRAM (L2_SRAM_BASE + 0x700) -#define XCHAL_USER_VECTOR_PADDR_SRAM (L2_SRAM_BASE + 0x740) -#define XCHAL_DOUBLEEXC_VECTOR_PADDR_SRAM (L2_SRAM_BASE + 0x7C0) +#define XCHAL_INTLEVEL2_VECTOR_PADDR_SRAM (DT_L2_SRAM_BASE + 0x580) +#define XCHAL_INTLEVEL3_VECTOR_PADDR_SRAM (DT_L2_SRAM_BASE + 0x5C0) +#define XCHAL_INTLEVEL4_VECTOR_PADDR_SRAM (DT_L2_SRAM_BASE + 0x600) +#define XCHAL_INTLEVEL5_VECTOR_PADDR_SRAM (DT_L2_SRAM_BASE + 0x640) +#define XCHAL_INTLEVEL6_VECTOR_PADDR_SRAM (DT_L2_SRAM_BASE + 0x680) +#define XCHAL_INTLEVEL7_VECTOR_PADDR_SRAM (DT_L2_SRAM_BASE + 0x6C0) +#define XCHAL_KERNEL_VECTOR_PADDR_SRAM (DT_L2_SRAM_BASE + 0x700) +#define XCHAL_USER_VECTOR_PADDR_SRAM (DT_L2_SRAM_BASE + 0x740) +#define XCHAL_DOUBLEEXC_VECTOR_PADDR_SRAM (DT_L2_SRAM_BASE + 0x7C0) /* Vector and literal sizes */ #define MEM_VECT_LIT_SIZE 0x8 @@ -44,7 +44,7 @@ #define MEM_ERROR_LIT_SIZE 0x8 /* text and data share the same L2 HP SRAM on Intel S1000 */ -#define TEXT_BASE (L2_SRAM_BASE + L2_VECTOR_SIZE) +#define TEXT_BASE (DT_L2_SRAM_BASE + L2_VECTOR_SIZE) #define TEXT_SIZE 0x16000 /* size of the Interrupt Descriptor Table (IDT) */ diff --git a/soc/xtensa/intel_s1000/soc.c b/soc/xtensa/intel_s1000/soc.c index f4416d80090..c2dd7c16f93 100644 --- a/soc/xtensa/intel_s1000/soc.c +++ b/soc/xtensa/intel_s1000/soc.c @@ -24,16 +24,16 @@ void _soc_irq_enable(u32_t irq) struct device *dev_cavs, *dev_ictl; switch (XTENSA_IRQ_NUMBER(irq)) { - case CAVS_ICTL_0_IRQ: + case DT_CAVS_ICTL_0_IRQ: dev_cavs = device_get_binding(CONFIG_CAVS_ICTL_0_NAME); break; - case CAVS_ICTL_1_IRQ: + case DT_CAVS_ICTL_1_IRQ: dev_cavs = device_get_binding(CONFIG_CAVS_ICTL_1_NAME); break; - case CAVS_ICTL_2_IRQ: + case DT_CAVS_ICTL_2_IRQ: dev_cavs = device_get_binding(CONFIG_CAVS_ICTL_2_NAME); break; - case CAVS_ICTL_3_IRQ: + case DT_CAVS_ICTL_3_IRQ: dev_cavs = device_get_binding(CONFIG_CAVS_ICTL_3_NAME); break; default: @@ -83,16 +83,16 @@ void _soc_irq_disable(u32_t irq) struct device *dev_cavs, *dev_ictl; switch (XTENSA_IRQ_NUMBER(irq)) { - case CAVS_ICTL_0_IRQ: + case DT_CAVS_ICTL_0_IRQ: dev_cavs = device_get_binding(CONFIG_CAVS_ICTL_0_NAME); break; - case CAVS_ICTL_1_IRQ: + case DT_CAVS_ICTL_1_IRQ: dev_cavs = device_get_binding(CONFIG_CAVS_ICTL_1_NAME); break; - case CAVS_ICTL_2_IRQ: + case DT_CAVS_ICTL_2_IRQ: dev_cavs = device_get_binding(CONFIG_CAVS_ICTL_2_NAME); break; - case CAVS_ICTL_3_IRQ: + case DT_CAVS_ICTL_3_IRQ: dev_cavs = device_get_binding(CONFIG_CAVS_ICTL_3_NAME); break; default: diff --git a/soc/xtensa/intel_s1000/soc.h b/soc/xtensa/intel_s1000/soc.h index 26a3925a5bc..2477cc00648 100644 --- a/soc/xtensa/intel_s1000/soc.h +++ b/soc/xtensa/intel_s1000/soc.h @@ -32,16 +32,16 @@ #define IOAPIC_HIGH 0 /* DW interrupt controller */ -#define DW_ICTL_IRQ_CAVS_OFFSET CAVS_IRQ_NUMBER(DW_ICTL_IRQ) +#define DW_ICTL_IRQ_CAVS_OFFSET CAVS_IRQ_NUMBER(DT_DW_ICTL_IRQ) #define DW_ICTL_NUM_IRQS 9 /* GPIO */ -#define GPIO_DW_0_BASE_ADDR 0x00080C00 -#define GPIO_DW_0_BITS 32 +#define DT_GPIO_DW_0_BASE_ADDR 0x00080C00 +#define DT_GPIO_DW_0_BITS 32 #define GPIO_DW_PORT_0_INT_MASK 0 -#define GPIO_DW_0_IRQ_FLAGS 0 -#define GPIO_DW_0_IRQ 0x00040706 -#define GPIO_DW_0_IRQ_ICTL_OFFSET INTR_CNTL_IRQ_NUM(GPIO_DW_0_IRQ) +#define DT_GPIO_DW_0_IRQ_FLAGS 0 +#define DT_GPIO_DW_0_IRQ 0x00040706 +#define GPIO_DW_0_IRQ_ICTL_OFFSET INTR_CNTL_IRQ_NUM(DT_GPIO_DW_0_IRQ) /* low power DMACs */ #define LP_GP_DMA_SIZE 0x00001000 diff --git a/subsys/debug/tracing/sysview_config.c b/subsys/debug/tracing/sysview_config.c index 11c23ecf4c4..8b61470c98d 100644 --- a/subsys/debug/tracing/sysview_config.c +++ b/subsys/debug/tracing/sysview_config.c @@ -21,8 +21,8 @@ void SEGGER_SYSVIEW_Conf(void) CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC, &SYSVIEW_X_OS_TraceAPI, _cbSendSystemDesc); -#if defined(CONFIG_PHYS_RAM_ADDR) /* x86 */ - SEGGER_SYSVIEW_SetRAMBase(CONFIG_PHYS_RAM_ADDR); +#if defined(DT_PHYS_RAM_ADDR) /* x86 */ + SEGGER_SYSVIEW_SetRAMBase(DT_PHYS_RAM_ADDR); #elif defined(CONFIG_SRAM_BASE_ADDRESS) /* arm, default */ SEGGER_SYSVIEW_SetRAMBase(CONFIG_SRAM_BASE_ADDRESS); #else diff --git a/subsys/dfu/boot/mcuboot.c b/subsys/dfu/boot/mcuboot.c index 815e3845ea2..18c10eba7b8 100644 --- a/subsys/dfu/boot/mcuboot.c +++ b/subsys/dfu/boot/mcuboot.c @@ -497,7 +497,7 @@ int boot_erase_img_bank(u32_t bank_offset) static int boot_init(struct device *dev) { ARG_UNUSED(dev); - flash_dev = device_get_binding(FLASH_DEV_NAME); + flash_dev = device_get_binding(DT_FLASH_DEV_NAME); if (!flash_dev) { return -ENODEV; } diff --git a/subsys/fs/shell.c b/subsys/fs/shell.c index 19c3ad3ef7f..da8d6bcd96c 100644 --- a/subsys/fs/shell.c +++ b/subsys/fs/shell.c @@ -486,7 +486,7 @@ static int cmd_mount_nffs(const struct shell *shell, size_t argc, char **argv) } nffs_mnt.mnt_point = (const char *)mntpt; - flash_dev = device_get_binding(FLASH_DEV_NAME); + flash_dev = device_get_binding(DT_FLASH_DEV_NAME); if (!flash_dev) { printk("Error in device_get_binding, while mounting nffs fs\n"); return -ENOEXEC; diff --git a/subsys/net/lib/openthread/platform/flash.c b/subsys/net/lib/openthread/platform/flash.c index 06911b30b89..7aa73ab0cab 100644 --- a/subsys/net/lib/openthread/platform/flash.c +++ b/subsys/net/lib/openthread/platform/flash.c @@ -24,7 +24,7 @@ otError utilsFlashInit(void) struct flash_pages_info info; size_t pages_count; - flash_dev = device_get_binding(FLASH_DEV_NAME); + flash_dev = device_get_binding(DT_FLASH_DEV_NAME); if (!flash_dev) { return OT_ERROR_NOT_IMPLEMENTED; diff --git a/subsys/storage/flash_map/flash_map.c b/subsys/storage/flash_map/flash_map.c index 0c87c43f352..45e9b9e3085 100644 --- a/subsys/storage/flash_map/flash_map.c +++ b/subsys/storage/flash_map/flash_map.c @@ -32,8 +32,8 @@ struct driver_map_entry { }; static const struct driver_map_entry flash_drivers_map[] = { -#ifdef FLASH_DEV_NAME /* SoC embedded flash driver */ - {SOC_FLASH_0_ID, FLASH_DEV_NAME}, +#ifdef DT_FLASH_DEV_NAME /* SoC embedded flash driver */ + {SOC_FLASH_0_ID, DT_FLASH_DEV_NAME}, #endif #ifdef CONFIG_SPI_FLASH_W25QXXDV {SPI_FLASH_0_ID, CONFIG_SPI_FLASH_W25QXXDV_DRV_NAME}, diff --git a/subsys/usb/class/usb_dfu.c b/subsys/usb/class/usb_dfu.c index 06d85d27e58..c14ff82ba14 100644 --- a/subsys/usb/class/usb_dfu.c +++ b/subsys/usb/class/usb_dfu.c @@ -683,7 +683,7 @@ static int usb_dfu_init(struct device *dev) ARG_UNUSED(dev); - dfu_data.flash_dev = device_get_binding(FLASH_DEV_NAME); + dfu_data.flash_dev = device_get_binding(DT_FLASH_DEV_NAME); if (!dfu_data.flash_dev) { LOG_ERR("Flash device not found\n"); return -ENODEV; diff --git a/tests/boards/intel_s1000_crb/src/gpio_test.c b/tests/boards/intel_s1000_crb/src/gpio_test.c index 792645cfe62..8b27873332c 100644 --- a/tests/boards/intel_s1000_crb/src/gpio_test.c +++ b/tests/boards/intel_s1000_crb/src/gpio_test.c @@ -89,7 +89,7 @@ void setup_gpio(struct device *gpio_dev) } /* Disable the GPIO interrupt. It is enabled by default */ - /* irq_disable(GPIO_DW_0_IRQ); */ + /* irq_disable(DT_GPIO_DW_0_IRQ); */ } /* gpio_thread is a static thread that is spawned automatically */ diff --git a/tests/drivers/aio/api/src/test_callback.c b/tests/drivers/aio/api/src/test_callback.c index 75779f1135b..bca28809f8d 100644 --- a/tests/drivers/aio/api/src/test_callback.c +++ b/tests/drivers/aio/api/src/test_callback.c @@ -13,9 +13,9 @@ #define PINMUX_NAME CONFIG_PINMUX_NAME #ifdef CONFIG_ARC -#define GPIO_DEV_NAME CONFIG_GPIO_QMSI_SS_0_NAME +#define GPIO_DEV_NAME DT_GPIO_QMSI_SS_0_NAME #else -#define GPIO_DEV_NAME CONFIG_GPIO_QMSI_0_NAME +#define GPIO_DEV_NAME DT_GPIO_QMSI_0_NAME #endif #if defined(CONFIG_BOARD_QUARK_SE_C1000_DEVBOARD) diff --git a/tests/drivers/build_all/dts_fixup.h b/tests/drivers/build_all/dts_fixup.h index 4e2011d8909..8ba9bd280ed 100644 --- a/tests/drivers/build_all/dts_fixup.h +++ b/tests/drivers/build_all/dts_fixup.h @@ -1,53 +1,53 @@ #if defined(CONFIG_HAS_DTS_I2C) -#ifndef CONFIG_ADT7420_NAME -#define CONFIG_ADT7420_NAME "" -#define CONFIG_ADT7420_I2C_ADDR 0 -#define CONFIG_ADT7420_I2C_MASTER_DEV_NAME "" -#define CONFIG_ADT7420_GPIO_DEV_NAME "" -#define CONFIG_ADT7420_GPIO_PIN_NUM 0 +#ifndef DT_ADT7420_NAME +#define DT_ADT7420_NAME "" +#define DT_ADT7420_I2C_ADDR 0 +#define DT_ADT7420_I2C_MASTER_DEV_NAME "" +#define DT_ADT7420_GPIO_DEV_NAME "" +#define DT_ADT7420_GPIO_PIN_NUM 0 #endif -#ifndef CONFIG_ADXL372_DEV_NAME -#define CONFIG_ADXL372_DEV_NAME "" -#define CONFIG_ADXL372_I2C_ADDR 0 -#define CONFIG_ADXL372_I2C_MASTER_DEV_NAME "" -#define CONFIG_ADXL372_GPIO_DEV_NAME "" -#define CONFIG_ADXL372_GPIO_PIN_NUM 0 +#ifndef DT_ADXL372_DEV_NAME +#define DT_ADXL372_DEV_NAME "" +#define DT_ADXL372_I2C_ADDR 0 +#define DT_ADXL372_I2C_MASTER_DEV_NAME "" +#define DT_ADXL372_GPIO_DEV_NAME "" +#define DT_ADXL372_GPIO_PIN_NUM 0 #endif -#ifndef CONFIG_APDS9960_DRV_NAME -#define CONFIG_APDS9960_DRV_NAME "" -#define CONFIG_APDS9960_I2C_DEV_NAME "" -#define CONFIG_APDS9960_GPIO_DEV_NAME "" -#define CONFIG_APDS9960_GPIO_PIN_NUM 0 +#ifndef DT_APDS9960_DRV_NAME +#define DT_APDS9960_DRV_NAME "" +#define DT_APDS9960_I2C_DEV_NAME "" +#define DT_APDS9960_GPIO_DEV_NAME "" +#define DT_APDS9960_GPIO_PIN_NUM 0 #endif -#ifndef CONFIG_CCS811_NAME -#define CONFIG_CCS811_NAME "" -#define CONFIG_CCS811_I2C_MASTER_DEV_NAME "" -#define CONFIG_CCS811_I2C_ADDR 0 +#ifndef DT_CCS811_NAME +#define DT_CCS811_NAME "" +#define DT_CCS811_I2C_MASTER_DEV_NAME "" +#define DT_CCS811_I2C_ADDR 0 #endif -#ifndef CONFIG_FXAS21002_NAME -#define CONFIG_FXAS21002_NAME "" -#define CONFIG_FXAS21002_I2C_ADDRESS 0 -#define CONFIG_FXAS21002_I2C_NAME "" -#define CONFIG_FXAS21002_GPIO_NAME "" -#define CONFIG_FXAS21002_GPIO_PIN 0 +#ifndef DT_FXAS21002_NAME +#define DT_FXAS21002_NAME "" +#define DT_FXAS21002_I2C_ADDRESS 0 +#define DT_FXAS21002_I2C_NAME "" +#define DT_FXAS21002_GPIO_NAME "" +#define DT_FXAS21002_GPIO_PIN 0 #endif -#ifndef CONFIG_FXOS8700_NAME -#define CONFIG_FXOS8700_NAME "" -#define CONFIG_FXOS8700_I2C_NAME "" -#define CONFIG_FXOS8700_I2C_ADDRESS 0 -#define CONFIG_FXOS8700_GPIO_NAME "" -#define CONFIG_FXOS8700_GPIO_PIN 0 +#ifndef DT_FXOS8700_NAME +#define DT_FXOS8700_NAME "" +#define DT_FXOS8700_I2C_NAME "" +#define DT_FXOS8700_I2C_ADDRESS 0 +#define DT_FXOS8700_GPIO_NAME "" +#define DT_FXOS8700_GPIO_PIN 0 #endif -#ifndef CONFIG_HTS221_NAME -#define CONFIG_HTS221_NAME "" -#define CONFIG_HTS221_I2C_MASTER_DEV_NAME "" +#ifndef DT_HTS221_NAME +#define DT_HTS221_NAME "" +#define DT_HTS221_I2C_MASTER_DEV_NAME "" #endif #ifndef CONFIG_LIS2MDL_GPIO_PIN_NUM @@ -60,27 +60,27 @@ #define CONFIG_LIS2MDL_I2C_MASTER_DEV_NAME "" #endif -#ifndef CONFIG_LIS3MDL_NAME -#define CONFIG_LIS3MDL_NAME "" -#define CONFIG_LIS3MDL_I2C_MASTER_DEV_NAME "" -#define CONFIG_LIS3MDL_I2C_ADDR 0x1e +#ifndef DT_LIS3MDL_NAME +#define DT_LIS3MDL_NAME "" +#define DT_LIS3MDL_I2C_MASTER_DEV_NAME "" +#define DT_LIS3MDL_I2C_ADDR 0x1e #endif -#ifndef CONFIG_LPS25HB_DEV_NAME -#define CONFIG_LPS25HB_DEV_NAME "" -#define CONFIG_LPS25HB_I2C_ADDR 0 -#define CONFIG_LPS25HB_I2C_MASTER_DEV_NAME "" +#ifndef DT_LPS25HB_DEV_NAME +#define DT_LPS25HB_DEV_NAME "" +#define DT_LPS25HB_I2C_ADDR 0 +#define DT_LPS25HB_I2C_MASTER_DEV_NAME "" #endif -#ifndef CONFIG_LSM6DS0_DEV_NAME -#define CONFIG_LSM6DS0_DEV_NAME "" -#define CONFIG_LSM6DS0_I2C_ADDR 0 -#define CONFIG_LSM6DS0_I2C_MASTER_DEV_NAME "" +#ifndef DT_LSM6DS0_DEV_NAME +#define DT_LSM6DS0_DEV_NAME "" +#define DT_LSM6DS0_I2C_ADDR 0 +#define DT_LSM6DS0_I2C_MASTER_DEV_NAME "" #endif -#ifndef CONFIG_MAX30101_NAME -#define CONFIG_MAX30101_I2C_NAME "" -#define CONFIG_MAX30101_NAME "" +#ifndef DT_MAX30101_NAME +#define DT_MAX30101_I2C_NAME "" +#define DT_MAX30101_NAME "" #endif #ifndef CONFIG_GPIO_SX1509B_DEV_NAME @@ -89,56 +89,56 @@ #define CONFIG_GPIO_SX1509B_I2C_MASTER_DEV_NAME "" #endif -#ifndef CONFIG_LSM6DSL_DEV_NAME -#define CONFIG_LSM6DSL_DEV_NAME "" -#define CONFIG_LSM6DSL_I2C_ADDR 0 -#define CONFIG_LSM6DSL_I2C_MASTER_DEV_NAME "" -#define CONFIG_LSM6DSL_GPIO_DEV_NAME "" -#define CONFIG_LSM6DSL_GPIO_PIN_NUM 0 +#ifndef DT_LSM6DSL_DEV_NAME +#define DT_LSM6DSL_DEV_NAME "" +#define DT_LSM6DSL_I2C_ADDR 0 +#define DT_LSM6DSL_I2C_MASTER_DEV_NAME "" +#define DT_LSM6DSL_GPIO_DEV_NAME "" +#define DT_LSM6DSL_GPIO_PIN_NUM 0 #endif -#ifndef CONFIG_LPS22HB_DEV_NAME -#define CONFIG_LPS22HB_DEV_NAME "" -#define CONFIG_LPS22HB_I2C_ADDR 0 -#define CONFIG_LPS22HB_I2C_MASTER_DEV_NAME "" +#ifndef DT_LPS22HB_DEV_NAME +#define DT_LPS22HB_DEV_NAME "" +#define DT_LPS22HB_I2C_ADDR 0 +#define DT_LPS22HB_I2C_MASTER_DEV_NAME "" #endif -#ifndef CONFIG_VL53L0X_NAME -#define CONFIG_VL53L0X_NAME "" -#define CONFIG_VL53L0X_I2C_ADDR 0 -#define CONFIG_VL53L0X_I2C_MASTER_DEV_NAME "" +#ifndef DT_VL53L0X_NAME +#define DT_VL53L0X_NAME "" +#define DT_VL53L0X_I2C_ADDR 0 +#define DT_VL53L0X_I2C_MASTER_DEV_NAME "" #endif -#ifndef CONFIG_LSM303DLHC_ACCEL_NAME -#define CONFIG_LSM303DLHC_ACCEL_NAME "" -#define CONFIG_LSM303DLHC_ACCEL_I2C_MASTER_DEV "" -#define CONFIG_LSM303DLHC_ACCEL_I2C_ADDR 0x19 +#ifndef DT_LSM303DLHC_ACCEL_NAME +#define DT_LSM303DLHC_ACCEL_NAME "" +#define DT_LSM303DLHC_ACCEL_I2C_MASTER_DEV "" +#define DT_LSM303DLHC_ACCEL_I2C_ADDR 0x19 #endif -#ifndef CONFIG_LSM303DLHC_MAGN_NAME -#define CONFIG_LSM303DLHC_MAGN_NAME "" -#define CONFIG_LSM303DLHC_MAGN_I2C_MASTER_DEV "" -#define CONFIG_LSM303DLHC_MAGN_I2C_ADDR 0x1e +#ifndef DT_LSM303DLHC_MAGN_NAME +#define DT_LSM303DLHC_MAGN_NAME "" +#define DT_LSM303DLHC_MAGN_I2C_MASTER_DEV "" +#define DT_LSM303DLHC_MAGN_I2C_ADDR 0x1e #endif #endif /* CONFIG_HAS_DTS_I2C */ #if defined(CONFIG_HAS_DTS_SPI) -#ifndef CONFIG_ADXL372_DEV_NAME -#define CONFIG_ADXL372_DEV_NAME "" -#define CONFIG_ADXL372_SPI_DEV_NAME "" -#define CONFIG_ADXL372_SPI_DEV_SLAVE 0 -#define CONFIG_ADXL372_SPI_BUS_FREQ 8000000 +#ifndef DT_ADXL372_DEV_NAME +#define DT_ADXL372_DEV_NAME "" +#define DT_ADXL372_SPI_DEV_NAME "" +#define DT_ADXL372_SPI_DEV_SLAVE 0 +#define DT_ADXL372_SPI_BUS_FREQ 8000000 #endif -#ifndef CONFIG_BMI160_NAME -#define CONFIG_BMI160_NAME "" -#define CONFIG_BMI160_SLAVE 0 -#define CONFIG_BMI160_SPI_PORT_NAME "" -#define CONFIG_BMI160_GPIO_DEV_NAME "" -#define CONFIG_BMI160_GPIO_PIN_NUM 0 -#define CONFIG_BMI160_SPI_BUS_FREQ 6400000 +#ifndef DT_BMI160_NAME +#define DT_BMI160_NAME "" +#define DT_BMI160_SLAVE 0 +#define DT_BMI160_SPI_PORT_NAME "" +#define DT_BMI160_GPIO_DEV_NAME "" +#define DT_BMI160_GPIO_PIN_NUM 0 +#define DT_BMI160_SPI_BUS_FREQ 6400000 #endif #endif /* CONFIG_HAS_DTS_SPI */ diff --git a/tests/drivers/gpio/gpio_basic_api/src/test_gpio.h b/tests/drivers/gpio/gpio_basic_api/src/test_gpio.h index 9b3ca7aebdf..39a886a7fc0 100644 --- a/tests/drivers/gpio/gpio_basic_api/src/test_gpio.h +++ b/tests/drivers/gpio/gpio_basic_api/src/test_gpio.h @@ -13,23 +13,23 @@ #include #if defined(CONFIG_BOARD_QUARK_SE_C1000_DEVBOARD) -#define DEV_NAME CONFIG_GPIO_QMSI_0_NAME +#define DEV_NAME DT_GPIO_QMSI_0_NAME #define PIN_OUT 15 /* GPIO15_I2S_RXD */ #define PIN_IN 16 /* GPIO16_I2S_RSCK */ #elif defined(CONFIG_BOARD_QUARK_SE_C1000_DEVBOARD_SS) -#define DEV_NAME CONFIG_GPIO_QMSI_SS_0_NAME +#define DEV_NAME DT_GPIO_QMSI_SS_0_NAME #define PIN_OUT 4 /* GPIO_SS_AIN_12 */ #define PIN_IN 5 /* GPIO_SS_AIN_13 */ #elif defined(CONFIG_BOARD_ARDUINO_101) -#define DEV_NAME CONFIG_GPIO_QMSI_0_NAME +#define DEV_NAME DT_GPIO_QMSI_0_NAME #define PIN_OUT 16 /* IO8 */ #define PIN_IN 19 /* IO4 */ #elif defined(CONFIG_BOARD_ARDUINO_101_SSS) -#define DEV_NAME CONFIG_GPIO_QMSI_SS_0_NAME +#define DEV_NAME DT_GPIO_QMSI_SS_0_NAME #define PIN_OUT 2 /* AD0 */ #define PIN_IN 3 /* AD1 */ #elif defined(CONFIG_BOARD_QUARK_D2000_CRB) -#define DEV_NAME CONFIG_GPIO_QMSI_0_NAME +#define DEV_NAME DT_GPIO_QMSI_0_NAME #define PIN_OUT 8 /* DIO7 */ #define PIN_IN 9 /* DIO8 */ #elif defined(CONFIG_BOARD_ESP32) @@ -37,19 +37,19 @@ #define PIN_OUT 4 /* DIO4 */ #define PIN_IN 2 /* DIO2 */ #elif defined(CONFIG_BOARD_ARDUINO_ZERO) -#define DEV_NAME CONFIG_GPIO_SAM0_PORTA_LABEL +#define DEV_NAME DT_GPIO_SAM0_PORTA_LABEL #define PIN_OUT 20 /* PA20 / pin 6 */ #define PIN_IN 15 /* PA15 / pin 5 */ #elif defined(CONFIG_BOARD_NRF52840_PCA10056) -#define DEV_NAME CONFIG_GPIO_P1_DEV_NAME +#define DEV_NAME DT_GPIO_P1_DEV_NAME #define PIN_OUT 1 /* P1.01 */ #define PIN_IN 2 /* P1.02 */ #elif defined(CONFIG_BOARD_NRF52_PCA10040) -#define DEV_NAME CONFIG_GPIO_P0_DEV_NAME +#define DEV_NAME DT_GPIO_P0_DEV_NAME #define PIN_OUT 11 /* P0.11 */ #define PIN_IN 12 /* P0.12 */ #elif defined(CONFIG_BOARD_NRF51_PCA10028) -#define DEV_NAME CONFIG_GPIO_P0_DEV_NAME +#define DEV_NAME DT_GPIO_P0_DEV_NAME #define PIN_OUT 12 /* P0.12 */ #define PIN_IN 13 /* P0.13 */ #else diff --git a/tests/drivers/i2c/i2c_api/src/test_i2c.c b/tests/drivers/i2c/i2c_api/src/test_i2c.c index 0b2aa4f9e8b..4f9a4a6cbc7 100644 --- a/tests/drivers/i2c/i2c_api/src/test_i2c.c +++ b/tests/drivers/i2c/i2c_api/src/test_i2c.c @@ -17,7 +17,7 @@ #include #ifdef CONFIG_ARC -#define I2C_DEV_NAME CONFIG_I2C_SS_0_NAME +#define I2C_DEV_NAME DT_I2C_SS_0_NAME #else #define I2C_DEV_NAME CONFIG_I2C_0_NAME #endif diff --git a/tests/drivers/pinmux/pinmux_basic_api/src/pinmux_gpio.c b/tests/drivers/pinmux/pinmux_basic_api/src/pinmux_gpio.c index 0f3946d1366..182a621a943 100644 --- a/tests/drivers/pinmux/pinmux_basic_api/src/pinmux_gpio.c +++ b/tests/drivers/pinmux/pinmux_basic_api/src/pinmux_gpio.c @@ -31,27 +31,27 @@ #define PINMUX_NAME CONFIG_PINMUX_NAME #if defined(CONFIG_BOARD_QUARK_SE_C1000_DEVBOARD) -#define GPIO_DEV_NAME CONFIG_GPIO_QMSI_0_NAME +#define GPIO_DEV_NAME DT_GPIO_QMSI_0_NAME #define GPIO_OUT 15 /* GPIO15_I2S_RXD */ #define GPIO_IN 16 /* GPIO16_I2S_RSCK */ #define PIN_IN 50 /* GPIO16_I2S_RSCK */ #elif defined(CONFIG_BOARD_QUARK_SE_C1000_DEVBOARD_SS) -#define GPIO_DEV_NAME CONFIG_GPIO_QMSI_SS_0_NAME +#define GPIO_DEV_NAME DT_GPIO_QMSI_SS_0_NAME #define GPIO_OUT 4 /* GPIO_SS_AIN_12 */ #define GPIO_IN 5 /* GPIO_SS_AIN_13 */ #define PIN_IN 13 /* GPIO_SS_AIN_13 */ #elif defined(CONFIG_BOARD_ARDUINO_101) -#define GPIO_DEV_NAME CONFIG_GPIO_QMSI_0_NAME +#define GPIO_DEV_NAME DT_GPIO_QMSI_0_NAME #define GPIO_OUT 16 /* IO8 */ #define GPIO_IN 19 /* IO4 */ #define PIN_IN 53 /* IO4 */ #elif defined(CONFIG_BOARD_ARDUINO_101_SSS) -#define GPIO_DEV_NAME CONFIG_GPIO_QMSI_SS_0_NAME +#define GPIO_DEV_NAME DT_GPIO_QMSI_SS_0_NAME #define GPIO_OUT 2 /* AD0 */ #define GPIO_IN 3 /* AD1 */ #define PIN_IN 11 /* AD1 */ #elif defined(CONFIG_BOARD_QUARK_D2000_CRB) -#define GPIO_DEV_NAME CONFIG_GPIO_QMSI_0_NAME +#define GPIO_DEV_NAME DT_GPIO_QMSI_0_NAME #define GPIO_OUT 8 /* DIO7 */ #define GPIO_IN 9 /* DIO8 */ #define PIN_IN 9 /* DIO8 */ diff --git a/tests/subsys/dfu/img_util/src/main.c b/tests/subsys/dfu/img_util/src/main.c index d73580794c5..3298c9529d4 100644 --- a/tests/subsys/dfu/img_util/src/main.c +++ b/tests/subsys/dfu/img_util/src/main.c @@ -15,7 +15,7 @@ void test_collecting(void) u32_t i, j; u8_t data[5], temp, k; - flash_dev = device_get_binding(FLASH_DEV_NAME); + flash_dev = device_get_binding(DT_FLASH_DEV_NAME); flash_write_protection_set(flash_dev, false); flash_erase(flash_dev, FLASH_AREA_IMAGE_1_OFFSET, diff --git a/tests/subsys/dfu/mcuboot/src/main.c b/tests/subsys/dfu/mcuboot/src/main.c index 5541de01a07..2d94b4cf1aa 100644 --- a/tests/subsys/dfu/mcuboot/src/main.c +++ b/tests/subsys/dfu/mcuboot/src/main.c @@ -23,7 +23,7 @@ void test_bank_erase(void) off_t offs; int ret; - flash_dev = device_get_binding(FLASH_DEV_NAME); + flash_dev = device_get_binding(DT_FLASH_DEV_NAME); for (offs = FLASH_AREA_IMAGE_1_OFFSET; offs <= FLASH_AREA_IMAGE_1_OFFSET + FLASH_AREA_IMAGE_1_SIZE; @@ -74,7 +74,7 @@ void test_request_upgrade(void) u32_t readout[ARRAY_SIZE(expectation)]; int ret; - flash_dev = device_get_binding(FLASH_DEV_NAME); + flash_dev = device_get_binding(DT_FLASH_DEV_NAME); zassert(boot_request_upgrade(false) == 0, "pass", "fail"); @@ -108,7 +108,7 @@ void test_write_confirm(void) struct device *flash_dev; int ret; - flash_dev = device_get_binding(FLASH_DEV_NAME); + flash_dev = device_get_binding(DT_FLASH_DEV_NAME); ret = flash_read(flash_dev, FLASH_AREA_IMAGE_0_OFFSET + FLASH_AREA_IMAGE_0_SIZE - sizeof(img_magic), &readout, diff --git a/tests/subsys/storage/flash_map/src/main.c b/tests/subsys/storage/flash_map/src/main.c index 3b3aab4a898..cf03c8f0c1c 100644 --- a/tests/subsys/storage/flash_map/src/main.c +++ b/tests/subsys/storage/flash_map/src/main.c @@ -37,7 +37,7 @@ void test_flash_area_to_sectors(void) zassert_true(rc == 0, "flash_area_open() fail"); /* First erase the area so it's ready for use. */ - flash_dev = device_get_binding(FLASH_DEV_NAME); + flash_dev = device_get_binding(DT_FLASH_DEV_NAME); rc = flash_write_protection_set(flash_dev, false); zassert_false(rc, "failed to disable flash write protection");