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dts_fixups: Use DT_ prefix in all defined labels not related to Kconfig

Browse source 
These changes were obtained by running a script  created by
Ulf Magnusson <Ulf.Magnusson@nordicsemi.no> for the following
specification:

1. Read the contents of all dts_fixup.h files in Zephyr
2. Check the left-hand side of the #define macros (i.e. the X in
   #define X Y)
3. Check if that name is also the name of a Kconfig option
   3.a If it is, then do nothing
   3.b If it is not, then replace CONFIG_ with DT_ or add DT_ if it
       has neither of these two prefixes
4. Replace the use of the changed #define in the code itself
   (.c, .h, .ld)

Additionally, some tweaks had to be added to this script to catch some
of the macros used in the code in a parameterized form, e.g.:
- CONFIG_GPIO_STM32_GPIO##__SUFFIX##_BASE_ADDRESS
- CONFIG_UART_##idx##_TX_PIN
- I2C_SBCON_##_num##_BASE_ADDR
and to prevent adding DT_ prefix to the following symbols:
- FLASH_START
- FLASH_SIZE
- SRAM_START
- SRAM_SIZE
- _ROM_ADDR
- _ROM_SIZE
- _RAM_ADDR
- _RAM_SIZE
which are surprisingly also defined in some dts_fixup.h files.

Finally, some manual corrections had to be done as well:
- name##_IRQ -> DT_##name##_IRQ in uart_stm32.c

Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
This commit is contained in:
Andrzej Głąbek 2018-11-13 15:15:23 +01:00 • committed by Kumar Gala
commit 20202902f2
304 changed files with 5118 additions and 5118 deletions
Download patch file Download diff file Expand all files Collapse all files

54
soc/xtensa/intel_s1000/dts_fixup.h
View file

@ -1,49 +1,49 @@
/* SoC level DTS fixup file */
#define CONFIG_UART_NS16550_PORT_0_BASE_ADDR NS16550_80800_BASE_ADDRESS
#define DT_UART_NS16550_PORT_0_BASE_ADDR NS16550_80800_BASE_ADDRESS
#define CONFIG_UART_NS16550_PORT_0_BAUD_RATE NS16550_80800_CURRENT_SPEED
#define CONFIG_UART_NS16550_PORT_0_NAME NS16550_80800_LABEL
#define CONFIG_UART_NS16550_PORT_0_IRQ ((NS16550_80800_IRQ_0 << 16) | \
#define DT_UART_NS16550_PORT_0_IRQ ((NS16550_80800_IRQ_0 << 16) | \
(SNPS_DESIGNWARE_INTC_81800_IRQ_0 << 8) | \
(INTEL_CAVS_INTC_78800_IRQ_0 << 0))
#define CONFIG_UART_NS16550_PORT_0_IRQ_PRI NS16550_80800_IRQ_0_PRIORITY
#define CONFIG_UART_NS16550_PORT_0_IRQ_FLAGS NS16550_80800_IRQ_0_SENSE
#define CONFIG_UART_NS16550_PORT_0_CLK_FREQ NS16550_80800_CLOCK_FREQUENCY
#define DT_UART_NS16550_PORT_0_IRQ_FLAGS NS16550_80800_IRQ_0_SENSE
#define DT_UART_NS16550_PORT_0_CLK_FREQ NS16550_80800_CLOCK_FREQUENCY
#define L2_SRAM_BASE CONFIG_SRAM_BASE_ADDRESS
#define L2_SRAM_SIZE CONFIG_SRAM_SIZE * 1024
#define DT_L2_SRAM_BASE CONFIG_SRAM_BASE_ADDRESS
#define DT_L2_SRAM_SIZE CONFIG_SRAM_SIZE * 1024
#define CAVS_ICTL_BASE_ADDR INTEL_CAVS_INTC_78800_BASE_ADDRESS
#define CAVS_ICTL_0_IRQ INTEL_CAVS_INTC_78800_IRQ_0
#define CONFIG_CAVS_ICTL_0_IRQ_PRI INTEL_CAVS_INTC_78800_IRQ_0_PRIORITY
#define CAVS_ICTL_0_IRQ_FLAGS INTEL_CAVS_INTC_78800_IRQ_0_SENSE
#define DT_CAVS_ICTL_BASE_ADDR INTEL_CAVS_INTC_78800_BASE_ADDRESS
#define DT_CAVS_ICTL_0_IRQ INTEL_CAVS_INTC_78800_IRQ_0
#define DT_CAVS_ICTL_0_IRQ_PRI INTEL_CAVS_INTC_78800_IRQ_0_PRIORITY
#define DT_CAVS_ICTL_0_IRQ_FLAGS INTEL_CAVS_INTC_78800_IRQ_0_SENSE
#define CAVS_ICTL_1_IRQ INTEL_CAVS_INTC_78810_IRQ_0
#define CONFIG_CAVS_ICTL_1_IRQ_PRI INTEL_CAVS_INTC_78810_IRQ_0_PRIORITY
#define CAVS_ICTL_1_IRQ_FLAGS INTEL_CAVS_INTC_78810_IRQ_0_SENSE
#define DT_CAVS_ICTL_1_IRQ INTEL_CAVS_INTC_78810_IRQ_0
#define DT_CAVS_ICTL_1_IRQ_PRI INTEL_CAVS_INTC_78810_IRQ_0_PRIORITY
#define DT_CAVS_ICTL_1_IRQ_FLAGS INTEL_CAVS_INTC_78810_IRQ_0_SENSE
#define CAVS_ICTL_2_IRQ INTEL_CAVS_INTC_78820_IRQ_0
#define CONFIG_CAVS_ICTL_2_IRQ_PRI INTEL_CAVS_INTC_78820_IRQ_0_PRIORITY
#define CAVS_ICTL_2_IRQ_FLAGS INTEL_CAVS_INTC_78820_IRQ_0_SENSE
#define DT_CAVS_ICTL_2_IRQ INTEL_CAVS_INTC_78820_IRQ_0
#define DT_CAVS_ICTL_2_IRQ_PRI INTEL_CAVS_INTC_78820_IRQ_0_PRIORITY
#define DT_CAVS_ICTL_2_IRQ_FLAGS INTEL_CAVS_INTC_78820_IRQ_0_SENSE
#define CAVS_ICTL_3_IRQ INTEL_CAVS_INTC_78830_IRQ_0
#define CONFIG_CAVS_ICTL_3_IRQ_PRI INTEL_CAVS_INTC_78830_IRQ_0_PRIORITY
#define CAVS_ICTL_3_IRQ_FLAGS INTEL_CAVS_INTC_78830_IRQ_0_SENSE
#define DT_CAVS_ICTL_3_IRQ INTEL_CAVS_INTC_78830_IRQ_0
#define DT_CAVS_ICTL_3_IRQ_PRI INTEL_CAVS_INTC_78830_IRQ_0_PRIORITY
#define DT_CAVS_ICTL_3_IRQ_FLAGS INTEL_CAVS_INTC_78830_IRQ_0_SENSE
#define DW_ICTL_BASE_ADDR SNPS_DESIGNWARE_INTC_81800_BASE_ADDRESS
#define DW_ICTL_IRQ ((SNPS_DESIGNWARE_INTC_81800_IRQ_0 << 8) | \
#define DT_DW_ICTL_BASE_ADDR SNPS_DESIGNWARE_INTC_81800_BASE_ADDRESS
#define DT_DW_ICTL_IRQ ((SNPS_DESIGNWARE_INTC_81800_IRQ_0 << 8) | \
(INTEL_CAVS_INTC_78800_IRQ_0 << 0))
#define CONFIG_DW_ICTL_IRQ_PRI SNPS_DESIGNWARE_INTC_81800_IRQ_0_PRIORITY
#define DW_ICTL_IRQ_FLAGS SNPS_DESIGNWARE_INTC_81800_IRQ_0_SENSE
#define DT_DW_ICTL_IRQ_PRI SNPS_DESIGNWARE_INTC_81800_IRQ_0_PRIORITY
#define DT_DW_ICTL_IRQ_FLAGS SNPS_DESIGNWARE_INTC_81800_IRQ_0_SENSE
#define CONFIG_I2C_0_BASE_ADDR SNPS_DESIGNWARE_I2C_80400_BASE_ADDRESS
#define CONFIG_I2C_0_BITRATE SNPS_DESIGNWARE_I2C_80400_CLOCK_FREQUENCY
#define DT_I2C_0_BASE_ADDR SNPS_DESIGNWARE_I2C_80400_BASE_ADDRESS
#define DT_I2C_0_BITRATE SNPS_DESIGNWARE_I2C_80400_CLOCK_FREQUENCY
#define CONFIG_I2C_0_NAME SNPS_DESIGNWARE_I2C_80400_LABEL
#define CONFIG_I2C_0_IRQ ((SNPS_DESIGNWARE_I2C_80400_IRQ_0 << 16) | \
#define DT_I2C_0_IRQ ((SNPS_DESIGNWARE_I2C_80400_IRQ_0 << 16) | \
(SNPS_DESIGNWARE_INTC_81800_IRQ_0 << 8) | \
(INTEL_CAVS_INTC_78800_IRQ_0 << 0))
#define CONFIG_I2C_0_IRQ_FLAGS SNPS_DESIGNWARE_I2C_80400_IRQ_0_SENSE
#define DT_I2C_0_IRQ_FLAGS SNPS_DESIGNWARE_I2C_80400_IRQ_0_SENSE
#define CONFIG_I2C_0_IRQ_PRI SNPS_DESIGNWARE_I2C_80400_IRQ_0_PRIORITY
/* End of SoC Level DTS fixup file */

2
soc/xtensa/intel_s1000/linker.ld
View file

@ -419,7 +419,7 @@ SECTIONS
/* stack */
_end = ALIGN(8);
PROVIDE(end = ALIGN(8));
__stack = L2_SRAM_BASE + L2_SRAM_SIZE;
__stack = DT_L2_SRAM_BASE + DT_L2_SRAM_SIZE;
.comment 0 : { *(.comment) }
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }

24
soc/xtensa/intel_s1000/memory.h
View file

@ -10,26 +10,26 @@
#define L2_VECTOR_SIZE 0x1000
/* The reset vector address in SRAM and its size */
#define XCHAL_RESET_VECTOR0_PADDR_SRAM L2_SRAM_BASE
#define XCHAL_RESET_VECTOR0_PADDR_SRAM DT_L2_SRAM_BASE
#define MEM_RESET_TEXT_SIZE 0x268
#define MEM_RESET_LIT_SIZE 0x8
/* This is the base address of all the vectors defined in SRAM */
#define XCHAL_VECBASE_RESET_PADDR_SRAM (L2_SRAM_BASE + 0x400)
#define XCHAL_VECBASE_RESET_PADDR_SRAM (DT_L2_SRAM_BASE + 0x400)
#define MEM_VECBASE_LIT_SIZE 0x178
/* The addresses of the vectors in SRAM.
* Only the memerror vector continues to point to its ROM address.
*/
#define XCHAL_INTLEVEL2_VECTOR_PADDR_SRAM (L2_SRAM_BASE + 0x580)
#define XCHAL_INTLEVEL3_VECTOR_PADDR_SRAM (L2_SRAM_BASE + 0x5C0)
#define XCHAL_INTLEVEL4_VECTOR_PADDR_SRAM (L2_SRAM_BASE + 0x600)
#define XCHAL_INTLEVEL5_VECTOR_PADDR_SRAM (L2_SRAM_BASE + 0x640)
#define XCHAL_INTLEVEL6_VECTOR_PADDR_SRAM (L2_SRAM_BASE + 0x680)
#define XCHAL_INTLEVEL7_VECTOR_PADDR_SRAM (L2_SRAM_BASE + 0x6C0)
#define XCHAL_KERNEL_VECTOR_PADDR_SRAM (L2_SRAM_BASE + 0x700)
#define XCHAL_USER_VECTOR_PADDR_SRAM (L2_SRAM_BASE + 0x740)
#define XCHAL_DOUBLEEXC_VECTOR_PADDR_SRAM (L2_SRAM_BASE + 0x7C0)
#define XCHAL_INTLEVEL2_VECTOR_PADDR_SRAM (DT_L2_SRAM_BASE + 0x580)
#define XCHAL_INTLEVEL3_VECTOR_PADDR_SRAM (DT_L2_SRAM_BASE + 0x5C0)
#define XCHAL_INTLEVEL4_VECTOR_PADDR_SRAM (DT_L2_SRAM_BASE + 0x600)
#define XCHAL_INTLEVEL5_VECTOR_PADDR_SRAM (DT_L2_SRAM_BASE + 0x640)
#define XCHAL_INTLEVEL6_VECTOR_PADDR_SRAM (DT_L2_SRAM_BASE + 0x680)
#define XCHAL_INTLEVEL7_VECTOR_PADDR_SRAM (DT_L2_SRAM_BASE + 0x6C0)
#define XCHAL_KERNEL_VECTOR_PADDR_SRAM (DT_L2_SRAM_BASE + 0x700)
#define XCHAL_USER_VECTOR_PADDR_SRAM (DT_L2_SRAM_BASE + 0x740)
#define XCHAL_DOUBLEEXC_VECTOR_PADDR_SRAM (DT_L2_SRAM_BASE + 0x7C0)
/* Vector and literal sizes */
#define MEM_VECT_LIT_SIZE 0x8
@ -44,7 +44,7 @@
#define MEM_ERROR_LIT_SIZE 0x8
/* text and data share the same L2 HP SRAM on Intel S1000 */
#define TEXT_BASE (L2_SRAM_BASE + L2_VECTOR_SIZE)
#define TEXT_BASE (DT_L2_SRAM_BASE + L2_VECTOR_SIZE)
#define TEXT_SIZE 0x16000
/* size of the Interrupt Descriptor Table (IDT) */

16
soc/xtensa/intel_s1000/soc.c
View file

@ -24,16 +24,16 @@ void _soc_irq_enable(u32_t irq)
struct device *dev_cavs, *dev_ictl;
switch (XTENSA_IRQ_NUMBER(irq)) {
case CAVS_ICTL_0_IRQ:
case DT_CAVS_ICTL_0_IRQ:
dev_cavs = device_get_binding(CONFIG_CAVS_ICTL_0_NAME);
break;
case CAVS_ICTL_1_IRQ:
case DT_CAVS_ICTL_1_IRQ:
dev_cavs = device_get_binding(CONFIG_CAVS_ICTL_1_NAME);
break;
case CAVS_ICTL_2_IRQ:
case DT_CAVS_ICTL_2_IRQ:
dev_cavs = device_get_binding(CONFIG_CAVS_ICTL_2_NAME);
break;
case CAVS_ICTL_3_IRQ:
case DT_CAVS_ICTL_3_IRQ:
dev_cavs = device_get_binding(CONFIG_CAVS_ICTL_3_NAME);
break;
default:
@ -83,16 +83,16 @@ void _soc_irq_disable(u32_t irq)
struct device *dev_cavs, *dev_ictl;
switch (XTENSA_IRQ_NUMBER(irq)) {
case CAVS_ICTL_0_IRQ:
case DT_CAVS_ICTL_0_IRQ:
dev_cavs = device_get_binding(CONFIG_CAVS_ICTL_0_NAME);
break;
case CAVS_ICTL_1_IRQ:
case DT_CAVS_ICTL_1_IRQ:
dev_cavs = device_get_binding(CONFIG_CAVS_ICTL_1_NAME);
break;
case CAVS_ICTL_2_IRQ:
case DT_CAVS_ICTL_2_IRQ:
dev_cavs = device_get_binding(CONFIG_CAVS_ICTL_2_NAME);
break;
case CAVS_ICTL_3_IRQ:
case DT_CAVS_ICTL_3_IRQ:
dev_cavs = device_get_binding(CONFIG_CAVS_ICTL_3_NAME);
break;
default:

12
soc/xtensa/intel_s1000/soc.h
View file

@ -32,16 +32,16 @@
#define IOAPIC_HIGH 0
/* DW interrupt controller */
#define DW_ICTL_IRQ_CAVS_OFFSET CAVS_IRQ_NUMBER(DW_ICTL_IRQ)
#define DW_ICTL_IRQ_CAVS_OFFSET CAVS_IRQ_NUMBER(DT_DW_ICTL_IRQ)
#define DW_ICTL_NUM_IRQS 9
/* GPIO */
#define GPIO_DW_0_BASE_ADDR 0x00080C00
#define GPIO_DW_0_BITS 32
#define DT_GPIO_DW_0_BASE_ADDR 0x00080C00
#define DT_GPIO_DW_0_BITS 32
#define GPIO_DW_PORT_0_INT_MASK 0
#define GPIO_DW_0_IRQ_FLAGS 0
#define GPIO_DW_0_IRQ 0x00040706
#define GPIO_DW_0_IRQ_ICTL_OFFSET INTR_CNTL_IRQ_NUM(GPIO_DW_0_IRQ)
#define DT_GPIO_DW_0_IRQ_FLAGS 0
#define DT_GPIO_DW_0_IRQ 0x00040706
#define GPIO_DW_0_IRQ_ICTL_OFFSET INTR_CNTL_IRQ_NUM(DT_GPIO_DW_0_IRQ)
/* low power DMACs */
#define LP_GP_DMA_SIZE 0x00001000