20202902f2
These changes were obtained by running a script created by
Ulf Magnusson <Ulf.Magnusson@nordicsemi.no> for the following
specification:
1. Read the contents of all dts_fixup.h files in Zephyr
2. Check the left-hand side of the #define macros (i.e. the X in
#define X Y)
3. Check if that name is also the name of a Kconfig option
3.a If it is, then do nothing
3.b If it is not, then replace CONFIG_ with DT_ or add DT_ if it
has neither of these two prefixes
4. Replace the use of the changed #define in the code itself
(.c, .h, .ld)
Additionally, some tweaks had to be added to this script to catch some
of the macros used in the code in a parameterized form, e.g.:
- CONFIG_GPIO_STM32_GPIO##__SUFFIX##_BASE_ADDRESS
- CONFIG_UART_##idx##_TX_PIN
- I2C_SBCON_##_num##_BASE_ADDR
and to prevent adding DT_ prefix to the following symbols:
- FLASH_START
- FLASH_SIZE
- SRAM_START
- SRAM_SIZE
- _ROM_ADDR
- _ROM_SIZE
- _RAM_ADDR
- _RAM_SIZE
which are surprisingly also defined in some dts_fixup.h files.
Finally, some manual corrections had to be done as well:
- name##_IRQ -> DT_##name##_IRQ in uart_stm32.c
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
49 lines
2.4 KiB
C
49 lines
2.4 KiB
C
/* SoC level DTS fixup file */
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#define DT_UART_NS16550_PORT_0_BASE_ADDR NS16550_80800_BASE_ADDRESS
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#define CONFIG_UART_NS16550_PORT_0_BAUD_RATE NS16550_80800_CURRENT_SPEED
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#define CONFIG_UART_NS16550_PORT_0_NAME NS16550_80800_LABEL
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#define DT_UART_NS16550_PORT_0_IRQ ((NS16550_80800_IRQ_0 << 16) | \
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(SNPS_DESIGNWARE_INTC_81800_IRQ_0 << 8) | \
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(INTEL_CAVS_INTC_78800_IRQ_0 << 0))
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#define CONFIG_UART_NS16550_PORT_0_IRQ_PRI NS16550_80800_IRQ_0_PRIORITY
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#define DT_UART_NS16550_PORT_0_IRQ_FLAGS NS16550_80800_IRQ_0_SENSE
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#define DT_UART_NS16550_PORT_0_CLK_FREQ NS16550_80800_CLOCK_FREQUENCY
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#define DT_L2_SRAM_BASE CONFIG_SRAM_BASE_ADDRESS
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#define DT_L2_SRAM_SIZE CONFIG_SRAM_SIZE * 1024
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#define DT_CAVS_ICTL_BASE_ADDR INTEL_CAVS_INTC_78800_BASE_ADDRESS
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#define DT_CAVS_ICTL_0_IRQ INTEL_CAVS_INTC_78800_IRQ_0
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#define DT_CAVS_ICTL_0_IRQ_PRI INTEL_CAVS_INTC_78800_IRQ_0_PRIORITY
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#define DT_CAVS_ICTL_0_IRQ_FLAGS INTEL_CAVS_INTC_78800_IRQ_0_SENSE
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#define DT_CAVS_ICTL_1_IRQ INTEL_CAVS_INTC_78810_IRQ_0
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#define DT_CAVS_ICTL_1_IRQ_PRI INTEL_CAVS_INTC_78810_IRQ_0_PRIORITY
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#define DT_CAVS_ICTL_1_IRQ_FLAGS INTEL_CAVS_INTC_78810_IRQ_0_SENSE
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#define DT_CAVS_ICTL_2_IRQ INTEL_CAVS_INTC_78820_IRQ_0
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#define DT_CAVS_ICTL_2_IRQ_PRI INTEL_CAVS_INTC_78820_IRQ_0_PRIORITY
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#define DT_CAVS_ICTL_2_IRQ_FLAGS INTEL_CAVS_INTC_78820_IRQ_0_SENSE
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#define DT_CAVS_ICTL_3_IRQ INTEL_CAVS_INTC_78830_IRQ_0
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#define DT_CAVS_ICTL_3_IRQ_PRI INTEL_CAVS_INTC_78830_IRQ_0_PRIORITY
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#define DT_CAVS_ICTL_3_IRQ_FLAGS INTEL_CAVS_INTC_78830_IRQ_0_SENSE
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#define DT_DW_ICTL_BASE_ADDR SNPS_DESIGNWARE_INTC_81800_BASE_ADDRESS
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#define DT_DW_ICTL_IRQ ((SNPS_DESIGNWARE_INTC_81800_IRQ_0 << 8) | \
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(INTEL_CAVS_INTC_78800_IRQ_0 << 0))
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#define DT_DW_ICTL_IRQ_PRI SNPS_DESIGNWARE_INTC_81800_IRQ_0_PRIORITY
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#define DT_DW_ICTL_IRQ_FLAGS SNPS_DESIGNWARE_INTC_81800_IRQ_0_SENSE
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#define DT_I2C_0_BASE_ADDR SNPS_DESIGNWARE_I2C_80400_BASE_ADDRESS
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#define DT_I2C_0_BITRATE SNPS_DESIGNWARE_I2C_80400_CLOCK_FREQUENCY
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#define CONFIG_I2C_0_NAME SNPS_DESIGNWARE_I2C_80400_LABEL
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#define DT_I2C_0_IRQ ((SNPS_DESIGNWARE_I2C_80400_IRQ_0 << 16) | \
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(SNPS_DESIGNWARE_INTC_81800_IRQ_0 << 8) | \
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(INTEL_CAVS_INTC_78800_IRQ_0 << 0))
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#define DT_I2C_0_IRQ_FLAGS SNPS_DESIGNWARE_I2C_80400_IRQ_0_SENSE
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#define CONFIG_I2C_0_IRQ_PRI SNPS_DESIGNWARE_I2C_80400_IRQ_0_PRIORITY
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/* End of SoC Level DTS fixup file */
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