2019-04-06 09:08:09 -04:00
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/* SPDX-License-Identifier: Apache-2.0 */
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2017-04-11 12:55:16 -05:00
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#include <arm/armv7-m.dtsi>
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2018-03-03 17:39:47 +02:00
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#include <dt-bindings/i2c/i2c.h>
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2018-07-09 15:24:47 +02:00
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#include <dt-bindings/gpio/gpio.h>
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2019-03-12 08:50:19 +01:00
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#include "nrf5_common.dtsi"
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2017-04-11 12:55:16 -05:00
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/ {
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cpus {
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2017-07-15 21:57:32 +03:00
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#address-cells = <1>;
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#size-cells = <0>;
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2017-04-11 12:55:16 -05:00
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cpu@0 {
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2017-07-15 21:57:32 +03:00
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device_type = "cpu";
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2017-04-11 12:55:16 -05:00
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compatible = "arm,cortex-m4f";
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2017-07-15 21:57:32 +03:00
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reg = <0>;
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2017-04-11 12:55:16 -05:00
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};
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};
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2018-10-03 11:54:11 +02:00
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aliases {
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i2c-0 = &i2c0;
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i2c-1 = &i2c1;
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2018-10-03 14:08:07 +02:00
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spi-0 = &spi0;
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spi-1 = &spi1;
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spi-2 = &spi2;
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spi-3 = &spi3;
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drivers: flash: add Nordic JEDEC QSPI NOR flash driver
Most JEDEC NOR flash devices uses not only typical SPI mode
(MISO,MOSI,SCK and CS), but also QSPI mode (IO0,IO1,IO2,IO3,SCK and CS).
QSPI mode uses more data lines and as a result provide higher
throughput. If this were not enough, Nordic chips provide
hardware acceleration for read/write/erase functions, what
gives significant performance boost.
It does a lot of things "behind the scene", i.e when user has written
some data to the flash and would like to read them back, it has to wait
until the flash is ready by reading WIP bit in Status Register.
This driver does it automatically.
Signed-off-by: Kamil Lazowski <Kamil.Lazowski@nordicsemi.no>
2019-12-19 13:33:37 +01:00
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qspi-0 = &qspi;
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2018-10-03 14:39:06 +02:00
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uart-0 = &uart0;
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uart-1 = &uart1;
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2018-10-03 16:07:41 +02:00
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adc-0 = &adc;
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2018-10-04 12:37:10 +02:00
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gpio-0 = &gpio0;
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gpio-1 = &gpio1;
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gpiote-0 = &gpiote;
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2018-10-04 12:52:00 +02:00
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wdt-0 = &wdt;
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2018-10-04 13:48:55 +02:00
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usbd-0 = &usbd;
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2018-10-04 15:01:36 +02:00
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cc310 = &cryptocell;
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arm-cryptocell-310 = &cryptocell310;
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2018-12-04 17:32:31 +01:00
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pwm-0 = &pwm0;
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pwm-1 = &pwm1;
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pwm-2 = &pwm2;
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pwm-3 = &pwm3;
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2018-11-16 13:46:59 +01:00
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qdec-0 = &qdec;
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2019-02-26 15:18:17 +01:00
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rtc-0 = &rtc0;
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rtc-1 = &rtc1;
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rtc-2 = &rtc2;
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2019-02-26 15:18:17 +01:00
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timer-0 = &timer0;
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timer-1 = &timer1;
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timer-2 = &timer2;
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timer-3 = &timer3;
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timer-4 = &timer4;
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2018-10-03 11:54:11 +02:00
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};
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2017-04-11 12:55:16 -05:00
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soc {
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2019-02-13 10:24:23 -06:00
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flash-controller@4001e000 {
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compatible = "nordic,nrf52-flash-controller";
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reg = <0x4001e000 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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label="NRF_FLASH_DRV_NAME";
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flash0: flash@0 {
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compatible = "soc-nv-flash";
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label = "NRF_FLASH";
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erase-block-size = <4096>;
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write-block-size = <4>;
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};
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};
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sram0: memory@20000000 {
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compatible = "mmio-sram";
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};
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2018-06-28 14:47:45 +02:00
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adc: adc@40007000 {
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compatible = "nordic,nrf-saadc";
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reg = <0x40007000 0x1000>;
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interrupts = <7 1>;
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status = "disabled";
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label = "ADC_0";
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2019-08-22 11:08:13 -05:00
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#io-channel-cells = <1>;
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2018-06-28 14:47:45 +02:00
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};
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2019-01-17 12:53:21 +01:00
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clock: clock@40000000 {
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compatible = "nordic,nrf-clock";
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reg = <0x40000000 0x1000>;
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interrupts = <0 1>;
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2019-06-14 19:31:16 +02:00
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status = "okay";
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2019-02-22 14:33:47 +01:00
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label = "CLOCK";
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2019-01-17 12:53:21 +01:00
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};
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2017-04-11 12:55:16 -05:00
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uart0: uart@40002000 {
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2018-07-05 10:25:46 -05:00
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/* uart can be either UART or UARTE, for the user to pick */
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/* compatible = "nordic,nrf-uarte" or "nordic,nrf-uart"; */
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2017-04-11 12:55:16 -05:00
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reg = <0x40002000 0x1000>;
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interrupts = <2 1>;
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status = "disabled";
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2017-05-16 16:25:03 -05:00
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label = "UART_0";
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2017-04-11 12:55:16 -05:00
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};
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uart1: uart@40028000 {
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compatible = "nordic,nrf-uarte";
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reg = <0x40028000 0x1000>;
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interrupts = <40 1>;
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status = "disabled";
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2017-05-16 16:25:03 -05:00
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label = "UART_1";
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2017-04-11 12:55:16 -05:00
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};
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2018-03-03 17:39:47 +02:00
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2018-05-17 09:53:17 +10:00
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gpiote: gpiote@40006000 {
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2018-07-18 13:05:13 +02:00
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compatible = "nordic,nrf-gpiote";
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2018-05-17 09:53:17 +10:00
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reg = <0x40006000 0x1000>;
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interrupts = <6 5>;
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status = "disabled";
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label = "GPIOTE_0";
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};
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gpio0: gpio@50000000 {
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2018-07-18 13:05:13 +02:00
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compatible = "nordic,nrf-gpio";
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2018-05-17 09:53:17 +10:00
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gpio-controller;
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reg = <0x50000000 0x200
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0x50000500 0x300>;
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#gpio-cells = <2>;
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label = "GPIO_0";
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status = "disabled";
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};
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gpio1: gpio@50000300 {
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2018-07-18 13:05:13 +02:00
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compatible = "nordic,nrf-gpio";
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2018-05-17 09:53:17 +10:00
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gpio-controller;
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reg = <0x50000300 0x200
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0x50000800 0x300>;
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#gpio-cells = <2>;
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2020-04-02 09:49:15 +00:00
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ngpios = <16>;
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2018-05-17 09:53:17 +10:00
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label = "GPIO_1";
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status = "disabled";
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};
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2018-03-03 17:39:47 +02:00
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i2c0: i2c@40003000 {
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2019-09-25 09:58:21 +02:00
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/*
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* This i2c node can be TWI, TWIM, or TWIS,
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* for the user to pick:
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* compatible = "nordic,nrf-twi" or
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* "nordic,nrf-twim" or
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* "nordic,nrf-twis".
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*/
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2018-03-03 17:39:47 +02:00
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40003000 0x1000>;
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clock-frequency = <I2C_BITRATE_STANDARD>;
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interrupts = <3 1>;
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status = "disabled";
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label = "I2C_0";
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};
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i2c1: i2c@40004000 {
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2019-09-25 09:58:21 +02:00
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/*
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* This i2c node can be TWI, TWIM, or TWIS,
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* for the user to pick:
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* compatible = "nordic,nrf-twi" or
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* "nordic,nrf-twim" or
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* "nordic,nrf-twis".
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*/
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2018-03-03 17:39:47 +02:00
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40004000 0x1000>;
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clock-frequency = <I2C_BITRATE_STANDARD>;
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interrupts = <4 1>;
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status = "disabled";
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label = "I2C_1";
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};
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2018-02-28 13:34:38 +05:30
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2018-12-13 11:38:33 -06:00
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pwm0: pwm@4001c000 {
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2018-12-04 17:32:31 +01:00
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compatible = "nordic,nrf-pwm";
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2018-12-13 11:38:33 -06:00
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reg = <0x4001c000 0x1000>;
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2018-12-04 17:32:31 +01:00
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interrupts = <28 1>;
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status = "disabled";
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label = "PWM_0";
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2019-10-03 09:34:42 +02:00
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#pwm-cells = <1>;
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2018-12-04 17:32:31 +01:00
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};
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pwm1: pwm@40021000 {
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compatible = "nordic,nrf-pwm";
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reg = <0x40021000 0x1000>;
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interrupts = <33 1>;
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status = "disabled";
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label = "PWM_1";
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2019-10-03 09:34:42 +02:00
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#pwm-cells = <1>;
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2018-12-04 17:32:31 +01:00
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};
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pwm2: pwm@40022000 {
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compatible = "nordic,nrf-pwm";
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reg = <0x40022000 0x1000>;
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interrupts = <34 1>;
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status = "disabled";
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label = "PWM_2";
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2019-10-03 09:34:42 +02:00
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#pwm-cells = <1>;
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2018-12-04 17:32:31 +01:00
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};
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2018-12-17 10:36:30 -06:00
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pwm3: pwm@4002d000 {
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2018-12-04 17:32:31 +01:00
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compatible = "nordic,nrf-pwm";
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2018-12-17 10:36:30 -06:00
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reg = <0x4002d000 0x1000>;
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2018-12-04 17:32:31 +01:00
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interrupts = <45 1>;
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status = "disabled";
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label = "PWM_3";
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2019-10-03 09:34:42 +02:00
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#pwm-cells = <1>;
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2018-12-04 17:32:31 +01:00
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};
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2018-09-24 14:46:38 +02:00
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qdec: qdec@40012000 {
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compatible = "nordic,nrf-qdec";
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reg = <0x40012000 0x1000>;
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interrupts = <18 1>;
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status = "disabled";
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label = "QDEC";
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};
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2018-09-04 15:03:58 +02:00
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spi0: spi@40003000 {
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2019-09-25 07:43:48 +02:00
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/*
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* This spi node can be SPI, SPIM, or SPIS,
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* for the user to pick:
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* compatible = "nordic,nrf-spi" or
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* "nordic,nrf-spim" or
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* "nordic,nrf-spis".
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*/
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2018-09-04 15:03:58 +02:00
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40003000 0x1000>;
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interrupts = <3 1>;
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status = "disabled";
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label = "SPI_0";
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};
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spi1: spi@40004000 {
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2019-09-25 07:43:48 +02:00
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/*
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* This spi node can be SPI, SPIM, or SPIS,
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* for the user to pick:
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* compatible = "nordic,nrf-spi" or
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* "nordic,nrf-spim" or
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* "nordic,nrf-spis".
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*/
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2018-09-04 15:03:58 +02:00
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40004000 0x1000>;
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interrupts = <4 1>;
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status = "disabled";
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label = "SPI_1";
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};
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spi2: spi@40023000 {
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2019-09-25 07:43:48 +02:00
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/*
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* This spi node can be SPI, SPIM, or SPIS,
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* for the user to pick:
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* compatible = "nordic,nrf-spi" or
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* "nordic,nrf-spim" or
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* "nordic,nrf-spis".
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*/
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2018-09-04 15:03:58 +02:00
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40023000 0x1000>;
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interrupts = <35 1>;
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status = "disabled";
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label = "SPI_2";
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};
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2019-09-23 14:27:15 +02:00
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spi3: spi@4002f000 {
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2019-09-25 07:43:48 +02:00
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compatible = "nordic,nrf-spim";
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2018-09-04 15:03:58 +02:00
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#address-cells = <1>;
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#size-cells = <0>;
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2019-09-23 14:27:15 +02:00
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reg = <0x4002f000 0x1000>;
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2018-09-04 15:03:58 +02:00
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interrupts = <47 1>;
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status = "disabled";
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label = "SPI_3";
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};
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drivers: flash: add Nordic JEDEC QSPI NOR flash driver
Most JEDEC NOR flash devices uses not only typical SPI mode
(MISO,MOSI,SCK and CS), but also QSPI mode (IO0,IO1,IO2,IO3,SCK and CS).
QSPI mode uses more data lines and as a result provide higher
throughput. If this were not enough, Nordic chips provide
hardware acceleration for read/write/erase functions, what
gives significant performance boost.
It does a lot of things "behind the scene", i.e when user has written
some data to the flash and would like to read them back, it has to wait
until the flash is ready by reading WIP bit in Status Register.
This driver does it automatically.
Signed-off-by: Kamil Lazowski <Kamil.Lazowski@nordicsemi.no>
2019-12-19 13:33:37 +01:00
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qspi: qspi@40029000 {
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compatible = "nordic,nrf-qspi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40029000 0x1000>;
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interrupts = <41 1>;
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status = "disabled";
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label = "QSPI";
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};
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2019-02-26 15:18:17 +01:00
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rtc0: rtc@4000b000 {
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compatible = "nordic,nrf-rtc";
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reg = <0x4000b000 0x1000>;
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interrupts = <11 1>;
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2019-06-14 19:31:16 +02:00
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status = "okay";
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2019-05-14 10:38:14 +02:00
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clock-frequency = <32768>;
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prescaler = <1>;
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2019-02-26 15:18:17 +01:00
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label = "RTC_0";
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};
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rtc1: rtc@40011000 {
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compatible = "nordic,nrf-rtc";
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|
|
reg = <0x40011000 0x1000>;
|
|
|
|
interrupts = <17 1>;
|
2019-06-14 19:31:16 +02:00
|
|
|
status = "okay";
|
2019-05-14 10:38:14 +02:00
|
|
|
clock-frequency = <32768>;
|
|
|
|
prescaler = <1>;
|
2019-02-26 15:18:17 +01:00
|
|
|
label = "RTC_1";
|
|
|
|
};
|
|
|
|
|
|
|
|
rtc2: rtc@40024000 {
|
|
|
|
compatible = "nordic,nrf-rtc";
|
|
|
|
reg = <0x40024000 0x1000>;
|
|
|
|
interrupts = <36 1>;
|
2019-06-14 19:31:16 +02:00
|
|
|
status = "okay";
|
2019-05-14 10:38:14 +02:00
|
|
|
clock-frequency = <32768>;
|
|
|
|
prescaler = <1>;
|
2019-02-26 15:18:17 +01:00
|
|
|
label = "RTC_2";
|
|
|
|
};
|
|
|
|
|
2019-02-26 15:18:17 +01:00
|
|
|
timer0: timer@40008000 {
|
|
|
|
compatible = "nordic,nrf-timer";
|
2019-06-14 19:31:16 +02:00
|
|
|
status = "okay";
|
2019-02-26 15:18:17 +01:00
|
|
|
reg = <0x40008000 0x1000>;
|
|
|
|
interrupts = <8 1>;
|
2019-05-14 10:38:14 +02:00
|
|
|
prescaler = <0>;
|
2019-02-26 15:18:17 +01:00
|
|
|
label = "TIMER_0";
|
|
|
|
};
|
|
|
|
|
|
|
|
timer1: timer@40009000 {
|
|
|
|
compatible = "nordic,nrf-timer";
|
2019-06-14 19:31:16 +02:00
|
|
|
status = "okay";
|
2019-02-26 15:18:17 +01:00
|
|
|
reg = <0x40009000 0x1000>;
|
|
|
|
interrupts = <9 1>;
|
2019-05-14 10:38:14 +02:00
|
|
|
prescaler = <0>;
|
2019-02-26 15:18:17 +01:00
|
|
|
label = "TIMER_1";
|
|
|
|
};
|
|
|
|
|
|
|
|
timer2: timer@4000a000 {
|
|
|
|
compatible = "nordic,nrf-timer";
|
2019-06-14 19:31:16 +02:00
|
|
|
status = "okay";
|
2019-02-26 15:18:17 +01:00
|
|
|
reg = <0x4000a000 0x1000>;
|
|
|
|
interrupts = <10 1>;
|
2019-05-14 10:38:14 +02:00
|
|
|
prescaler = <0>;
|
2019-02-26 15:18:17 +01:00
|
|
|
label = "TIMER_2";
|
|
|
|
};
|
|
|
|
|
|
|
|
timer3: timer@4001a000 {
|
|
|
|
compatible = "nordic,nrf-timer";
|
2019-06-14 19:31:16 +02:00
|
|
|
status = "okay";
|
2019-02-26 15:18:17 +01:00
|
|
|
reg = <0x4001a000 0x1000>;
|
|
|
|
interrupts = <26 1>;
|
2019-05-14 10:38:14 +02:00
|
|
|
prescaler = <0>;
|
2019-02-26 15:18:17 +01:00
|
|
|
label = "TIMER_3";
|
|
|
|
};
|
|
|
|
|
|
|
|
timer4: timer@4001b000 {
|
|
|
|
compatible = "nordic,nrf-timer";
|
2019-06-14 19:31:16 +02:00
|
|
|
status = "okay";
|
2019-02-26 15:18:17 +01:00
|
|
|
reg = <0x4001b000 0x1000>;
|
|
|
|
interrupts = <27 1>;
|
2019-05-14 10:38:14 +02:00
|
|
|
prescaler = <0>;
|
2019-02-26 15:18:17 +01:00
|
|
|
label = "TIMER_4";
|
|
|
|
};
|
|
|
|
|
2019-02-14 09:44:04 +01:00
|
|
|
temp: temp@4000c000 {
|
|
|
|
compatible = "nordic,nrf-temp";
|
|
|
|
reg = <0x4000c000 0x1000>;
|
|
|
|
interrupts = <12 1>;
|
2019-06-14 19:31:16 +02:00
|
|
|
status = "okay";
|
2019-02-14 09:44:04 +01:00
|
|
|
label = "TEMP_0";
|
|
|
|
};
|
|
|
|
|
2018-06-16 13:30:07 +02:00
|
|
|
usbd: usbd@40027000 {
|
2018-02-28 13:34:38 +05:30
|
|
|
compatible = "nordic,nrf-usbd";
|
|
|
|
reg = <0x40027000 0x1000>;
|
|
|
|
interrupts = <39 1>;
|
|
|
|
num-bidir-endpoints = <1>;
|
|
|
|
num-in-endpoints = <7>;
|
|
|
|
num-out-endpoints = <7>;
|
|
|
|
num-isoin-endpoints = <1>;
|
|
|
|
num-isoout-endpoints = <1>;
|
|
|
|
status = "disabled";
|
|
|
|
label = "USBD";
|
|
|
|
};
|
2018-04-17 15:29:12 +02:00
|
|
|
|
|
|
|
wdt: watchdog@40010000 {
|
|
|
|
compatible = "nordic,nrf-watchdog";
|
|
|
|
reg = <0x40010000 0x1000>;
|
|
|
|
interrupts = <16 1>;
|
2019-06-14 19:31:16 +02:00
|
|
|
status = "okay";
|
2018-04-17 15:29:12 +02:00
|
|
|
label = "WDT";
|
|
|
|
};
|
2018-09-04 15:06:21 +02:00
|
|
|
|
|
|
|
cryptocell: crypto@5002a000 {
|
|
|
|
compatible = "nordic,nrf-cc310";
|
|
|
|
reg = <0x5002A000 0x1000>;
|
|
|
|
label = "CRYPTOCELL";
|
2019-06-14 19:31:16 +02:00
|
|
|
status = "okay";
|
2018-09-04 15:06:21 +02:00
|
|
|
#address-cells = <1>;
|
|
|
|
#size-cells = <1>;
|
|
|
|
cryptocell310: crypto@5002b000 {
|
|
|
|
compatible = "arm,cryptocell-310";
|
|
|
|
reg = <0x5002B000 0x1000>;
|
|
|
|
interrupts = <42 1>;
|
2019-05-13 20:11:30 +03:00
|
|
|
label = "CRYPTOCELL310";
|
2018-09-04 15:06:21 +02:00
|
|
|
};
|
|
|
|
};
|
2017-04-11 12:55:16 -05:00
|
|
|
};
|
|
|
|
};
|
|
|
|
|
|
|
|
&nvic {
|
|
|
|
arm,num-irq-priority-bits = <3>;
|
|
|
|
};
|
2019-03-12 08:50:19 +01:00
|
|
|
|
|
|
|
&sw_pwm {
|
|
|
|
timer-instance = <2>;
|
|
|
|
channel-count = <3>;
|
|
|
|
clock-prescaler = <0>;
|
|
|
|
ppi-base = <14>;
|
|
|
|
gpiote-base = <0>;
|
2019-10-03 09:34:42 +02:00
|
|
|
#pwm-cells = <1>;
|
2019-03-12 08:50:19 +01:00
|
|
|
};
|