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zephyr/soc/arm/nxp_lpc/lpc54xxx/Kconfig.soc

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kconfig: Clean up header comments and make them consistent Use this short header style in all Kconfig files: # <description> # <copyright> # <license> ... Also change all <description>s from # Kconfig[.extension] - Foo-related options to just # Foo-related options It's clear enough that it's about Kconfig. The <description> cleanup was done with this command, along with some manual cleanup (big letter at the start, etc.) git ls-files '*Kconfig*' | \ xargs sed -i -E '1 s/#\s*Kconfig[\w.-]*\s*-\s*/# /' Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
2019-11-01 13:45:29 +01:00
# LPC LPC54XXX MCU line
lpc: Add nxp_lpc soc family to soc directory Add soc configuration support for lpc soc family, Kconfigs and soc files for lpcxxx soc. Add dtsi file for lpc54xxx. Signed-off-by: Shiksha Patel <shiksha.patel@nxp.com> Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-07-26 04:40:18 -05:00
# Copyright (c) 2017, NXP
# SPDX-License-Identifier: Apache-2.0
choice
kconfig: Global whitespace/consistency cleanup Clean up space errors and use a consistent style throughout the Kconfig files. This makes reading the Kconfig files more distraction-free, helps with grepping, and encourages the same style getting copied around everywhere (meaning another pass hopefully won't be needed). Go for the most common style: - Indent properties with a single tab, including for choices. Properties on choices work exactly the same syntactically as properties on symbols, so not sure how the no-indentation thing happened. - Indent help texts with a tab followed by two spaces - Put a space between 'config' and the symbol name, not a tab. This also helps when grepping for definitions. - Do '# A comment' instead of '#A comment' I tweaked Kconfiglib a bit to find most of the stuff. Some help texts were reflowed to 79 columns with 'gq' in Vim as well, though not all, because I was afraid I'd accidentally mess up formatting. Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
2019-11-01 10:24:07 +01:00
prompt "LPC LPC54XXX MCU Selection"
depends on SOC_SERIES_LPC54XXX
lpc: Add nxp_lpc soc family to soc directory Add soc configuration support for lpc soc family, Kconfigs and soc files for lpcxxx soc. Add dtsi file for lpc54xxx. Signed-off-by: Shiksha Patel <shiksha.patel@nxp.com> Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-07-26 04:40:18 -05:00
arch: nxp: lpc54xxx: Rename SoC bits from LPC54114 to LPC54114_M4 Rename various SoC related defines and files from just being LPC54114 to LPC54114_M4. This is in prep for supporting a build for the second core on the LPC54114 (the Cortex-M0+). * Renamed Kconfig SOC_LPC54114 to SOC_LPC54114_M4 * Renamed Kconfig.defconfig.lpc54114 to Kconfig.defconfig.lpc54114_m4 * Introduced nxp_lpc54xxx_m4.dtsi based on nxp_lpc54xxx.dtsi * Moved some pinmux related defines into SoC code. Signed-off-by: Stanislav Poboril <stanislav.poboril@nxp.com> Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-05-15 13:47:24 -05:00
config SOC_LPC54114_M4
bool "SOC_LPC54114_M4"
select CPU_CORTEX_M4
soc: arm: nxp_lpc: Select CPU DWT feature symbol The Data Watchpoint and Trace (DWT) is an optional debug unit for the Cortex-M family cores (except ARMv6-M; i.e. M0 and M0+) that provides watchpoints, data tracing and system profiling capabilities. Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2020-01-10 10:50:37 +09:00
select CPU_CORTEX_M_HAS_DWT
soc: nxp_lpc: Enable mpu on the lpc54114 m4 core Enables the arm v7m mpu on the lpc54114 m4 core. Reuses the mpu configuration from the i.mx rt, which has the same mpu. Tested on hardware with tests/kernel/mem_protect Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2019-09-12 12:23:03 -05:00
select CPU_HAS_ARM_MPU
soc: arm: fix missing configs & defines Some SoC have missing feature selections in their Kconfig. Some others are missing includes of CMSIS-Core headers. Signed-off-by: Wilfried Chauveau <wilfried.chauveau@arm.com>
2023-11-07 12:57:29 +00:00
select CPU_HAS_FPU
ext: Modified lpc54114 startup code from mcux for use with Zephyr. The instructions performed by standard Zephyr startup files are removed from the file startup_LPC54114_cm4.S. Introduced the section _PlatformInit which will be called when platform specific initialization is needed. Signed-off-by: Stanislav Poboril <stanislav.poboril@nxp.com>
2018-04-24 17:56:56 +02:00
select PLATFORM_SPECIFIC_INIT
soc: LPC54xxx, LPC55xxx: Update to use clock control Use the clock control driver to get flexcomm clock frequency Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
2020-08-25 16:13:16 -05:00
select CLOCK_CONTROL
soc: lpc54xxx: add memory controller definitions Adds device tree and kconfig definitons to use legacy LPC IAP flash driver. Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
2020-07-02 15:05:53 +03:00
select HAS_MCUX_IAP_LEGACY
lpc: Add nxp_lpc soc family to soc directory Add soc configuration support for lpc soc family, Kconfigs and soc files for lpcxxx soc. Add dtsi file for lpc54xxx. Signed-off-by: Shiksha Patel <shiksha.patel@nxp.com> Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-07-26 04:40:18 -05:00
arch: arm: lpc: Added support for Cortex-M0+ on lpc54114 soc Add soc configuration support and dts files for nxp_lpc54xxx_m0. Adjusted nxp_lpc54xxx soc, configuration and dts files for the presence of slave core. Origin: Original Signed-off-by: Stanislav Poboril <stanislav.poboril@nxp.com> Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-05-15 18:51:17 -05:00
config SOC_LPC54114_M0
bool "SOC_LPC54114_M0"
select CPU_CORTEX_M0PLUS
select CPU_CORTEX_M_HAS_VTOR
soc: LPC54xxx, LPC55xxx: Update to use clock control Use the clock control driver to get flexcomm clock frequency Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
2020-08-25 16:13:16 -05:00
select CLOCK_CONTROL
arch: arm: lpc: Added support for Cortex-M0+ on lpc54114 soc Add soc configuration support and dts files for nxp_lpc54xxx_m0. Adjusted nxp_lpc54xxx soc, configuration and dts files for the presence of slave core. Origin: Original Signed-off-by: Stanislav Poboril <stanislav.poboril@nxp.com> Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-05-15 18:51:17 -05:00
lpc: Add nxp_lpc soc family to soc directory Add soc configuration support for lpc soc family, Kconfigs and soc files for lpcxxx soc. Add dtsi file for lpc54xxx. Signed-off-by: Shiksha Patel <shiksha.patel@nxp.com> Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-07-26 04:40:18 -05:00
endchoice
if SOC_SERIES_LPC54XXX
config SOC_PART_NUMBER_LPC54114J256BD64
bool
config SOC_PART_NUMBER_LPC54XXX
string
default "LPC54114J256BD64" if SOC_PART_NUMBER_LPC54114J256BD64
help
This string holds the full part number of the SoC. It is a hidden
option that you should not set directly. The part number selection
choice defines the default value for this string.
soc: lpc54xxx: align to lpc55xxx multicore defs Aligns lpc54xxx Kconfigs and other definitions to lpc55xxx. Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
2020-12-16 18:54:03 +02:00
config SECOND_CORE_MCUX
kconfig: remove Enable from boolean prompts According to Kconfig guidelines, boolean prompts must not start with "Enable...". The following command has been used to automate the changes in this patch: sed -i "s/bool \"[Ee]nables\? \(\w\)/bool \"\U\1/g" **/Kconfig* Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-03-09 12:05:12 +01:00
bool "LPC54114 Cortex-M0 second core"
arch: arm: nxp_lpc: Added support for init of slave core Added ability to load and bootup the slave (Cortex-M0+) core on the LPC54xxx SoC. Currently we expect a binary image to be specified via Kconfig for the code that will run on the slave core. We also specify via Kconfig the boot/load address for the slave core. Origin: Original Signed-off-by: Stanislav Poboril <stanislav.poboril@nxp.com> Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-05-15 18:52:23 -05:00
depends on HAS_MCUX
help
soc: lpc54xxx: align to lpc55xxx multicore defs Aligns lpc54xxx Kconfigs and other definitions to lpc55xxx. Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
2020-12-16 18:54:03 +02:00
Driver for second core startup
arch: arm: nxp_lpc: Added support for init of slave core Added ability to load and bootup the slave (Cortex-M0+) core on the LPC54xxx SoC. Currently we expect a binary image to be specified via Kconfig for the code that will run on the slave core. We also specify via Kconfig the boot/load address for the slave core. Origin: Original Signed-off-by: Stanislav Poboril <stanislav.poboril@nxp.com> Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-05-15 18:52:23 -05:00
soc: lpc54xxx: align to lpc55xxx multicore defs Aligns lpc54xxx Kconfigs and other definitions to lpc55xxx. Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
2020-12-16 18:54:03 +02:00
config SECOND_CORE_BOOT_ADDRESS_MCUX
depends on SECOND_CORE_MCUX
hex "Address the second core will boot at"
arch: arm: nxp_lpc: Added support for init of slave core Added ability to load and bootup the slave (Cortex-M0+) core on the LPC54xxx SoC. Currently we expect a binary image to be specified via Kconfig for the code that will run on the slave core. We also specify via Kconfig the boot/load address for the slave core. Origin: Original Signed-off-by: Stanislav Poboril <stanislav.poboril@nxp.com> Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-05-15 18:52:23 -05:00
default 0x20010000
help
soc: lpc54xxx: align to lpc55xxx multicore defs Aligns lpc54xxx Kconfigs and other definitions to lpc55xxx. Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
2020-12-16 18:54:03 +02:00
This is the address the second core will boot from. Additionally this
address is where we will copy the SECOND_IMAGE to. We default this to
the base of SRAM1.
arch: arm: nxp_lpc: Added support for init of slave core Added ability to load and bootup the slave (Cortex-M0+) core on the LPC54xxx SoC. Currently we expect a binary image to be specified via Kconfig for the code that will run on the slave core. We also specify via Kconfig the boot/load address for the slave core. Origin: Original Signed-off-by: Stanislav Poboril <stanislav.poboril@nxp.com> Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2018-05-15 18:52:23 -05:00
soc: lpc54114: update multi core support for LMA address offset Update lpc54114 support to use LMA address offset instead of linking secondary core image into primary core memory. This will allow support with sysbuild to be enabled. Additionally, use partitions to select where the secondary core image will be located in flash Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-08-04 10:22:38 -05:00
# Workaround for not being able to have commas in macro arguments
DT_CHOSEN_Z_CODE_CPU1_PARTITION := zephyr,code-cpu1-partition
# Move the LMA address of second core into flash
config BUILD_OUTPUT_ADJUST_LMA
depends on SECOND_CORE_MCUX && SOC_LPC54114_M0
default "-0x20010000+\
$(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_CPU1_PARTITION))"
config BUILD_OUTPUT_INFO_HEADER
default y
depends on SECOND_CORE_MCUX && SOC_LPC54114_M0
soc: arm: nxp_lpc: convert NXP LPC SOCs to use CMSIS SystemInit Convert NXP LPC SOCs to use CMSIS SystemInit, and remove redundant code where it exists. This will enable initialization flows to be more standardized across all platforms. Since LPC54xxx and LPC55xxx series enables SRAM banks in SystemInit, provide Kconfigs to bypass this setting and keep additional SRAM banks unclocked. Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-11-30 16:06:40 -06:00
config LPC54XXX_SRAM2_CLOCK
bool "Clock LPC54XXX SRAM2"
default y
help
SRAM2 ram bank is disabled out of reset. By default, CMSIS SystemInit
will enable the clock to this RAM bank. Disable this Kconfig to leave
this ram bank untouched out of reset.
lpc: Add nxp_lpc soc family to soc directory Add soc configuration support for lpc soc family, Kconfigs and soc files for lpcxxx soc. Add dtsi file for lpc54xxx. Signed-off-by: Shiksha Patel <shiksha.patel@nxp.com> Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-07-26 04:40:18 -05:00
endif # SOC_SERIES_LPC54XXX
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