2019-09-01 18:30:41 +01:00
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/*
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* Copyright (c) 2019 Richard Osterloh <richard.osterloh@gmail.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arm/armv7-m.dtsi>
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2019-09-04 09:37:52 +01:00
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#include <dt-bindings/clock/stm32_clock.h>
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2019-09-04 09:44:35 +01:00
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#include <dt-bindings/i2c/i2c.h>
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2019-09-04 09:40:48 +01:00
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#include <dt-bindings/gpio/gpio.h>
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2020-04-23 16:10:12 +02:00
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#include <dt-bindings/pwm/pwm.h>
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2019-09-01 18:30:41 +01:00
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/ {
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2020-04-06 09:59:03 -05:00
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chosen {
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zephyr,entropy = &rng;
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2020-04-22 13:46:15 -05:00
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zephyr,flash-controller = &flash;
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2020-04-06 09:59:03 -05:00
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};
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2019-09-01 18:30:41 +01:00
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-m4f";
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reg = <0>;
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};
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};
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sram0: memory@20000000 {
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compatible = "mmio-sram";
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};
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soc {
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2020-04-10 18:29:02 +02:00
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/*
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* Both adc instances cannot be used in parallel right now.
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*/
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2020-04-27 10:11:40 +02:00
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adc1: adc@50000000 {
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2020-04-10 18:29:02 +02:00
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compatible = "st,stm32-adc";
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reg = <0x50000000 0x100>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00002000>;
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interrupts = <18 0>;
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status = "disabled";
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2020-04-27 10:11:40 +02:00
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label = "ADC_1";
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2020-04-10 18:29:02 +02:00
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#io-channel-cells = <1>;
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};
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2020-04-27 10:11:40 +02:00
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adc2: adc@50000100 {
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2020-04-10 18:29:02 +02:00
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compatible = "st,stm32-adc";
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reg = <0x50000100 0x100>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00002000>;
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interrupts = <18 0>;
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status = "disabled";
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2020-04-27 10:11:40 +02:00
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label = "ADC_2";
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2020-04-10 18:29:02 +02:00
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#io-channel-cells = <1>;
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};
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2020-04-22 13:46:15 -05:00
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flash: flash-controller@40022000 {
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2020-04-13 18:00:09 +02:00
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compatible = "st,stm32-flash-controller", "st,stm32g4-flash-controller";
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2019-09-04 09:43:59 +01:00
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label = "FLASH_CTRL";
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reg = <0x40022000 0x400>;
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interrupts = <3 0>;
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#address-cells = <1>;
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#size-cells = <1>;
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flash0: flash@8000000 {
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compatible = "soc-nv-flash";
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label = "FLASH_STM32";
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write-block-size = <8>;
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erase-block-size = <2048>;
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};
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};
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2019-09-04 09:37:52 +01:00
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rcc: rcc@40021000 {
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compatible = "st,stm32-rcc";
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#clock-cells = <2>;
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reg = <0x40021000 0x400>;
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label = "STM32_CLK_RCC";
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};
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2019-09-01 18:30:41 +01:00
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2019-09-04 09:40:48 +01:00
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pinctrl: pin-controller@48000000 {
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compatible = "st,stm32-pinmux";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x48000000 0x2000>;
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gpioa: gpio@48000000 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x48000000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000001>;
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label = "GPIOA";
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};
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gpiob: gpio@48000400 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x48000400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000002>;
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label = "GPIOB";
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};
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gpioc: gpio@48000800 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x48000800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000004>;
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label = "GPIOC";
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};
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gpiod: gpio@48000c00 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x48000c00 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000008>;
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label = "GPIOD";
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};
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gpioe: gpio@48001000 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x48001000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000010>;
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label = "GPIOE";
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};
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gpiof: gpio@48001400 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x48001400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000020>;
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label = "GPIOF";
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};
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gpiog: gpio@48001800 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x48001800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000040>;
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label = "GPIOG";
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};
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};
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2019-09-04 09:43:07 +01:00
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usart1: serial@40013800 {
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compatible = "st,stm32-usart", "st,stm32-uart";
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reg = <0x40013800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00004000>;
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interrupts = <37 0>;
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status = "disabled";
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label = "UART_1";
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};
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usart2: serial@40004400 {
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compatible = "st,stm32-usart", "st,stm32-uart";
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reg = <0x40004400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00020000>;
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interrupts = <38 0>;
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status = "disabled";
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label = "UART_2";
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};
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usart3: serial@40004800 {
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compatible = "st,stm32-usart", "st,stm32-uart";
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reg = <0x40004800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
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interrupts = <39 0>;
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status = "disabled";
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label = "UART_3";
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};
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uart4: serial@40004c00 {
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compatible = "st,stm32-uart";
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reg = <0x40004c00 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
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interrupts = <52 0>;
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status = "disabled";
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label = "UART_4";
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};
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lpuart1: serial@40008000 {
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compatible = "st,stm32-lpuart", "st,stm32-uart";
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reg = <0x40008000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000001>;
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interrupts = <91 0>;
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status = "disabled";
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label = "LPUART_1";
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};
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2019-09-06 11:31:28 +02:00
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iwdg: watchdog@40003000 {
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compatible = "st,stm32-watchdog";
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reg = <0x40003000 0x400>;
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label = "IWDG";
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status = "disabled";
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};
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wwdg: watchdog@40002c00 {
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compatible = "st,stm32-window-watchdog";
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reg = <0x40002C00 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000800>;
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label = "WWDG";
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interrupts = <0 7>;
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status = "disabled";
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};
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2019-09-04 09:44:35 +01:00
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i2c1: i2c@40005400 {
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compatible = "st,stm32-i2c-v2";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40005400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>;
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interrupts = <31 0>, <32 0>;
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interrupt-names = "event", "error";
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status = "disabled";
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label= "I2C_1";
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};
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i2c2: i2c@40005800 {
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compatible = "st,stm32-i2c-v2";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40005800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00400000>;
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interrupts = <33 0>, <34 0>;
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interrupt-names = "event", "error";
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status = "disabled";
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label= "I2C_2";
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};
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i2c3: i2c@40007800 {
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compatible = "st,stm32-i2c-v2";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40007800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x40000000>;
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interrupts = <92 0>, <93 0>;
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interrupt-names = "event", "error";
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status = "disabled";
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label= "I2C_3";
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};
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2019-09-04 09:45:03 +01:00
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spi1: spi@40013000 {
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drivers/spi: stm32: Modify use of "st,stm32-spi-fifo" compatible
On stm32 spi devices, there are 2 main IP variants, with and w/o
fifo. Fifo is not really used today, but still there is some
additional code handling fifo. Today this code is protected under
Kconfig symbol SPI_STM32_HAS_FIFO.
This code carries redundant information vs dedicated compatible
"st,stm32-spi-fifo", which is provided as unique driver compatible
for devices supporting this IP as opposed to use of "st,stm32-spi"
when fifo is not supported.
Having these 2 compatibles defined exclusively is not convenient for
migration to DT_INST as DT_INST macros contain compatible string and
hence it cannot be used to provide common compatible code for devices
defining different compatibles.
Based on these observations, review stm32 spi devices compatible
declarations. Devices supporting fifo will now declare both
compatibles, as proposed by dt spec: "[compatible] property value
consists of a concatenated list of null terminated strings,
from most specific to most general". Hence field will now be:
"st,stm32-spi-fifo", "st,stm32-spi"
This way, fifo enabled stm32 spi devices will generate both:
DT_INST_STM32_SPI_FOO and DT_INST_STM32_SPI_FIFO_FOO
As well as:
DT_COMPAT_ST_STM32_SPI and DT_COMPAT_ST_STM32_SPI_FIFO
So, DT_INST_STM32_SPI_FOO could be used for device initialization.
Also DT_COMPAT_ST_STM32_SPI_FIFO could be used for FIFO handling
code inside driver. Hence use it to replace Kconfig symbol
SPI_STM32_HAS_FIFO.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2020-03-09 10:43:41 +01:00
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compatible = "st,stm32-spi-fifo", "st,stm32-spi";
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2019-09-04 09:45:03 +01:00
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40013000 0x400>;
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interrupts = <35 5>;
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clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00001000>;
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status = "disabled";
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label = "SPI_1";
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};
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spi2: spi@40003800 {
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drivers/spi: stm32: Modify use of "st,stm32-spi-fifo" compatible
On stm32 spi devices, there are 2 main IP variants, with and w/o
fifo. Fifo is not really used today, but still there is some
additional code handling fifo. Today this code is protected under
Kconfig symbol SPI_STM32_HAS_FIFO.
This code carries redundant information vs dedicated compatible
"st,stm32-spi-fifo", which is provided as unique driver compatible
for devices supporting this IP as opposed to use of "st,stm32-spi"
when fifo is not supported.
Having these 2 compatibles defined exclusively is not convenient for
migration to DT_INST as DT_INST macros contain compatible string and
hence it cannot be used to provide common compatible code for devices
defining different compatibles.
Based on these observations, review stm32 spi devices compatible
declarations. Devices supporting fifo will now declare both
compatibles, as proposed by dt spec: "[compatible] property value
consists of a concatenated list of null terminated strings,
from most specific to most general". Hence field will now be:
"st,stm32-spi-fifo", "st,stm32-spi"
This way, fifo enabled stm32 spi devices will generate both:
DT_INST_STM32_SPI_FOO and DT_INST_STM32_SPI_FIFO_FOO
As well as:
DT_COMPAT_ST_STM32_SPI and DT_COMPAT_ST_STM32_SPI_FIFO
So, DT_INST_STM32_SPI_FOO could be used for device initialization.
Also DT_COMPAT_ST_STM32_SPI_FIFO could be used for FIFO handling
code inside driver. Hence use it to replace Kconfig symbol
SPI_STM32_HAS_FIFO.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2020-03-09 10:43:41 +01:00
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compatible = "st,stm32-spi-fifo", "st,stm32-spi";
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2019-09-04 09:45:03 +01:00
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40003800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
|
|
|
|
|
interrupts = <36 5>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
label = "SPI_2";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
spi3: spi@40003c00 {
|
drivers/spi: stm32: Modify use of "st,stm32-spi-fifo" compatible
On stm32 spi devices, there are 2 main IP variants, with and w/o
fifo. Fifo is not really used today, but still there is some
additional code handling fifo. Today this code is protected under
Kconfig symbol SPI_STM32_HAS_FIFO.
This code carries redundant information vs dedicated compatible
"st,stm32-spi-fifo", which is provided as unique driver compatible
for devices supporting this IP as opposed to use of "st,stm32-spi"
when fifo is not supported.
Having these 2 compatibles defined exclusively is not convenient for
migration to DT_INST as DT_INST macros contain compatible string and
hence it cannot be used to provide common compatible code for devices
defining different compatibles.
Based on these observations, review stm32 spi devices compatible
declarations. Devices supporting fifo will now declare both
compatibles, as proposed by dt spec: "[compatible] property value
consists of a concatenated list of null terminated strings,
from most specific to most general". Hence field will now be:
"st,stm32-spi-fifo", "st,stm32-spi"
This way, fifo enabled stm32 spi devices will generate both:
DT_INST_STM32_SPI_FOO and DT_INST_STM32_SPI_FIFO_FOO
As well as:
DT_COMPAT_ST_STM32_SPI and DT_COMPAT_ST_STM32_SPI_FIFO
So, DT_INST_STM32_SPI_FOO could be used for device initialization.
Also DT_COMPAT_ST_STM32_SPI_FIFO could be used for FIFO handling
code inside driver. Hence use it to replace Kconfig symbol
SPI_STM32_HAS_FIFO.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2020-03-09 10:43:41 +01:00
|
|
|
compatible = "st,stm32-spi-fifo", "st,stm32-spi";
|
2019-09-04 09:45:03 +01:00
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
reg = <0x40003c00 0x400>;
|
|
|
|
|
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00008000>;
|
|
|
|
|
interrupts = <51 5>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
label = "SPI_3";
|
|
|
|
|
};
|
|
|
|
|
|
2019-09-06 13:47:21 +02:00
|
|
|
timers1: timers@40012c00 {
|
|
|
|
|
compatible = "st,stm32-timers";
|
|
|
|
|
reg = <0x40012c00 0x400>;
|
|
|
|
|
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000800>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
label = "TIMERS_1";
|
|
|
|
|
|
|
|
|
|
pwm {
|
|
|
|
|
compatible = "st,stm32-pwm";
|
|
|
|
|
status = "disabled";
|
|
|
|
|
st,prescaler = <10000>;
|
|
|
|
|
label = "PWM_1";
|
2020-04-23 16:10:12 +02:00
|
|
|
#pwm-cells = <3>;
|
2019-09-06 13:47:21 +02:00
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
timers2: timers@40000000 {
|
|
|
|
|
compatible = "st,stm32-timers";
|
|
|
|
|
reg = <0x40000000 0x400>;
|
|
|
|
|
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000001>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
label = "TIMERS_2";
|
|
|
|
|
|
|
|
|
|
pwm {
|
|
|
|
|
compatible = "st,stm32-pwm";
|
|
|
|
|
status = "disabled";
|
|
|
|
|
st,prescaler = <0>;
|
|
|
|
|
label = "PWM_2";
|
2020-04-23 16:10:12 +02:00
|
|
|
#pwm-cells = <3>;
|
2019-09-06 13:47:21 +02:00
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
timers3: timers@40000400 {
|
|
|
|
|
compatible = "st,stm32-timers";
|
|
|
|
|
reg = <0x40000400 0x400>;
|
|
|
|
|
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000002>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
label = "TIMERS_3";
|
|
|
|
|
|
|
|
|
|
pwm {
|
|
|
|
|
compatible = "st,stm32-pwm";
|
|
|
|
|
status = "disabled";
|
|
|
|
|
st,prescaler = <10000>;
|
|
|
|
|
label = "PWM_3";
|
2020-04-23 16:10:12 +02:00
|
|
|
#pwm-cells = <3>;
|
2019-09-06 13:47:21 +02:00
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
timers4: timers@40000800 {
|
|
|
|
|
compatible = "st,stm32-timers";
|
|
|
|
|
reg = <0x40000800 0x400>;
|
|
|
|
|
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000004>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
label = "TIMERS_4";
|
|
|
|
|
|
|
|
|
|
pwm {
|
|
|
|
|
compatible = "st,stm32-pwm";
|
|
|
|
|
status = "disabled";
|
|
|
|
|
st,prescaler = <10000>;
|
|
|
|
|
label = "PWM_4";
|
2020-04-23 16:10:12 +02:00
|
|
|
#pwm-cells = <3>;
|
2019-09-06 13:47:21 +02:00
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
timers6: timers@40001000 {
|
|
|
|
|
compatible = "st,stm32-timers";
|
|
|
|
|
reg = <0x40001000 0x400>;
|
|
|
|
|
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000010>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
label = "TIMERS_6";
|
|
|
|
|
|
|
|
|
|
pwm {
|
|
|
|
|
compatible = "st,stm32-pwm";
|
|
|
|
|
status = "disabled";
|
|
|
|
|
st,prescaler = <10000>;
|
|
|
|
|
label = "PWM_6";
|
2020-04-23 16:10:12 +02:00
|
|
|
#pwm-cells = <3>;
|
2019-09-06 13:47:21 +02:00
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
timers7: timers@40001400 {
|
|
|
|
|
compatible = "st,stm32-timers";
|
|
|
|
|
reg = <0x40001400 0x400>;
|
|
|
|
|
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000020>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
label = "TIMERS_7";
|
|
|
|
|
|
|
|
|
|
pwm {
|
|
|
|
|
compatible = "st,stm32-pwm";
|
|
|
|
|
status = "disabled";
|
|
|
|
|
st,prescaler = <10000>;
|
|
|
|
|
label = "PWM_7";
|
2020-04-23 16:10:12 +02:00
|
|
|
#pwm-cells = <3>;
|
2019-09-06 13:47:21 +02:00
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
timers8: timers@40013400 {
|
|
|
|
|
compatible = "st,stm32-timers";
|
|
|
|
|
reg = <0x40013400 0x400>;
|
|
|
|
|
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00004000>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
label = "TIMERS_8";
|
|
|
|
|
|
|
|
|
|
pwm {
|
|
|
|
|
compatible = "st,stm32-pwm";
|
|
|
|
|
status = "disabled";
|
|
|
|
|
st,prescaler = <10000>;
|
|
|
|
|
label = "PWM_8";
|
2020-04-23 16:10:12 +02:00
|
|
|
#pwm-cells = <3>;
|
2019-09-06 13:47:21 +02:00
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
timers15: timers@40014000 {
|
|
|
|
|
compatible = "st,stm32-timers";
|
|
|
|
|
reg = <0x40014000 0x400>;
|
|
|
|
|
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00010000>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
label = "TIMERS_15";
|
|
|
|
|
|
|
|
|
|
pwm {
|
|
|
|
|
compatible = "st,stm32-pwm";
|
|
|
|
|
status = "disabled";
|
|
|
|
|
st,prescaler = <10000>;
|
|
|
|
|
label = "PWM_15";
|
2020-04-23 16:10:12 +02:00
|
|
|
#pwm-cells = <3>;
|
2019-09-06 13:47:21 +02:00
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
timers16: timers@40014400 {
|
|
|
|
|
compatible = "st,stm32-timers";
|
|
|
|
|
reg = <0x40014400 0x400>;
|
|
|
|
|
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00020000>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
label = "TIMERS_16";
|
|
|
|
|
|
|
|
|
|
pwm {
|
|
|
|
|
compatible = "st,stm32-pwm";
|
|
|
|
|
status = "disabled";
|
|
|
|
|
st,prescaler = <10000>;
|
|
|
|
|
label = "PWM_16";
|
2020-04-23 16:10:12 +02:00
|
|
|
#pwm-cells = <3>;
|
2019-09-06 13:47:21 +02:00
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
timers17: timers@40014800 {
|
|
|
|
|
compatible = "st,stm32-timers";
|
|
|
|
|
reg = <0x40014800 0x400>;
|
|
|
|
|
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00040000>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
label = "TIMERS_17";
|
|
|
|
|
|
|
|
|
|
pwm {
|
|
|
|
|
compatible = "st,stm32-pwm";
|
|
|
|
|
status = "disabled";
|
|
|
|
|
st,prescaler = <10000>;
|
|
|
|
|
label = "PWM_17";
|
2020-04-23 16:10:12 +02:00
|
|
|
#pwm-cells = <3>;
|
2019-09-06 13:47:21 +02:00
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
2019-09-04 09:47:06 +01:00
|
|
|
rtc: rtc@40002800 {
|
|
|
|
|
compatible = "st,stm32-rtc";
|
|
|
|
|
reg = <0x40002800 0x400>;
|
|
|
|
|
interrupts = <41 0>;
|
|
|
|
|
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>;
|
|
|
|
|
prescaler = <32768>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
label = "RTC_0";
|
|
|
|
|
};
|
|
|
|
|
|
2020-04-02 11:20:12 +02:00
|
|
|
rng: rng@50060800 {
|
|
|
|
|
compatible = "st,stm32-rng";
|
|
|
|
|
reg = <0x50060800 0x400>;
|
|
|
|
|
clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x04000000>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
label = "RNG";
|
|
|
|
|
};
|
|
|
|
|
|
2019-09-04 09:48:18 +01:00
|
|
|
usb: usb@40005c00 {
|
|
|
|
|
compatible = "st,stm32-usb";
|
|
|
|
|
reg = <0x40005c00 0x400>;
|
|
|
|
|
interrupts = <20 0>, <19 0>;
|
|
|
|
|
interrupt-names = "usb", "usbhp";
|
|
|
|
|
num-bidir-endpoints = <8>;
|
|
|
|
|
ram-size = <1024>;
|
|
|
|
|
phys = <&usb_fs_phy>;
|
|
|
|
|
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00800000>;
|
|
|
|
|
status = "disabled";
|
|
|
|
|
label= "USB";
|
|
|
|
|
};
|
|
|
|
|
|
2019-09-01 18:30:41 +01:00
|
|
|
};
|
|
|
|
|
|
2019-09-04 09:48:18 +01:00
|
|
|
usb_fs_phy: usbphy {
|
|
|
|
|
compatible = "usb-nop-xceiv";
|
|
|
|
|
#phy-cells = <0>;
|
|
|
|
|
label = "USB_FS_PHY";
|
|
|
|
|
};
|
2019-09-01 18:30:41 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
&nvic {
|
|
|
|
|
arm,num-irq-priority-bits = <4>;
|
|
|
|
|
};
|
