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zephyr/soc/riscv/andes_v5/ae350/l2_cache.c

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soc: riscv: andes_v5: initial support of Andes L2 cache controller This initial support of L2C driver only contains cache enable and HW capability checking. Cache management operation isn't supported yet in this driver. Signed-off-by: Jim Shu <cwshu@andestech.com>
2021-07-29 12:39:27 +08:00
/*
* Copyright (c) 2021 Andes Technology Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT andestech_l2c
/**
* @brief Andes V5 L2 Cache Controller driver
*/
soc: migrate includes to <zephyr/...> In order to bring consistency in-tree, migrate all soc code to the new prefix <zephyr/...>. Note that the conversion has been scripted, refer to zephyrproject-rtos#45388 for more details. Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-05-06 11:11:04 +02:00
#include <zephyr/init.h>
#include <zephyr/kernel.h>
#include <zephyr/arch/cpu.h>
soc: riscv: andes_v5: use syscon driver instead of accessing dts directly Access syscon area by driver instead of parsing dts node. Signed-off-by: Wei-Tai Lee <wtlee@andestech.com>
2022-08-19 17:48:10 +08:00
#include <zephyr/drivers/syscon.h>
soc: riscv: andes_v5: Fix system initialization for L2C - Put L2C init level in pre_kernel_2 to wait for syscon driver - Check if SMU exists when preprocessing Signed-off-by: Wei-Tai Lee <wtlee@andestech.com>
2022-09-02 16:07:14 +08:00
#include <zephyr/logging/log.h>
soc: riscv: andes_v5: refine Andes L2 cache Refine source code and flush all I/D-Cache before update L2 cache register. Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
2023-06-26 18:11:38 +08:00
#include <zephyr/arch/riscv/csr.h>
soc: riscv: andes_v5: use syscon driver instead of accessing dts directly Access syscon area by driver instead of parsing dts node. Signed-off-by: Wei-Tai Lee <wtlee@andestech.com>
2022-08-19 17:48:10 +08:00
soc: riscv: andes_v5: refine Andes L2 cache Refine source code and flush all I/D-Cache before update L2 cache register. Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
2023-06-26 18:11:38 +08:00
LOG_MODULE_REGISTER(andes_v5_l2_cache, CONFIG_SOC_LOG_LEVEL);
soc: riscv: andes_v5: initial support of Andes L2 cache controller This initial support of L2C driver only contains cache enable and HW capability checking. Cache management operation isn't supported yet in this driver. Signed-off-by: Jim Shu <cwshu@andestech.com>
2021-07-29 12:39:27 +08:00
soc: riscv: andes_v5: refine Andes L2 cache Refine source code and flush all I/D-Cache before update L2 cache register. Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
2023-06-26 18:11:38 +08:00
/* L2C Register Base Address */
soc: riscv: riscv-privilege: andes_v5: reworked Andes L2 cache Detect the L2 cache at runtime and removed unused Kconfig CONFIG_SOC_ANDES_V5_L2_CACHE. Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
2022-07-12 15:59:40 +08:00
#define ANDES_V5_L2C_BASE DT_INST_REG_ADDR(0)
soc: riscv: andes_v5: initial support of Andes L2 cache controller This initial support of L2C driver only contains cache enable and HW capability checking. Cache management operation isn't supported yet in this driver. Signed-off-by: Jim Shu <cwshu@andestech.com>
2021-07-29 12:39:27 +08:00
soc: riscv: andes_v5: refine Andes L2 cache Refine source code and flush all I/D-Cache before update L2 cache register. Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
2023-06-26 18:11:38 +08:00
/* L2C Register Offset */
#define L2C_CONFIG (ANDES_V5_L2C_BASE + 0x00)
#define L2C_CTRL (ANDES_V5_L2C_BASE + 0x08)
soc: riscv: andes_v5: initial support of Andes L2 cache controller This initial support of L2C driver only contains cache enable and HW capability checking. Cache management operation isn't supported yet in this driver. Signed-off-by: Jim Shu <cwshu@andestech.com>
2021-07-29 12:39:27 +08:00
soc: riscv: andes_v5: refine Andes L2 cache Refine source code and flush all I/D-Cache before update L2 cache register. Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
2023-06-26 18:11:38 +08:00
/* L2C Helper Constant */
#define L2C_CONFIG_VER GENMASK64(31, 24)
soc: riscv: andes_v5: initial support of Andes L2 cache controller This initial support of L2C driver only contains cache enable and HW capability checking. Cache management operation isn't supported yet in this driver. Signed-off-by: Jim Shu <cwshu@andestech.com>
2021-07-29 12:39:27 +08:00
#define L2C_CTRL_CEN BIT(0)
soc: riscv: andes_v5: refine Andes L2 cache Refine source code and flush all I/D-Cache before update L2 cache register. Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
2023-06-26 18:11:38 +08:00
/* Instruction prefetch depth */
soc: riscv: andes_v5: initial support of Andes L2 cache controller This initial support of L2C driver only contains cache enable and HW capability checking. Cache management operation isn't supported yet in this driver. Signed-off-by: Jim Shu <cwshu@andestech.com>
2021-07-29 12:39:27 +08:00
#define IPFDPT_FIELD(x) (x << 3)
#define L2C_CTRL_IPFDPT_0 IPFDPT_FIELD(0)
#define L2C_CTRL_IPFDPT_1 IPFDPT_FIELD(1)
#define L2C_CTRL_IPFDPT_2 IPFDPT_FIELD(2)
#define L2C_CTRL_IPFDPT_3 IPFDPT_FIELD(3)
soc: riscv: andes_v5: refine Andes L2 cache Refine source code and flush all I/D-Cache before update L2 cache register. Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
2023-06-26 18:11:38 +08:00
/* Data prefetch depth */
soc: riscv: andes_v5: initial support of Andes L2 cache controller This initial support of L2C driver only contains cache enable and HW capability checking. Cache management operation isn't supported yet in this driver. Signed-off-by: Jim Shu <cwshu@andestech.com>
2021-07-29 12:39:27 +08:00
#define DPFDPT_FIELD(x) (x << 5)
#define L2C_CTRL_DPFDPT_0 DPFDPT_FIELD(0)
#define L2C_CTRL_DPFDPT_2 DPFDPT_FIELD(1)
#define L2C_CTRL_DPFDPT_4 DPFDPT_FIELD(2)
#define L2C_CTRL_DPFDPT_8 DPFDPT_FIELD(3)
soc: riscv: andes_v5: refine Andes L2 cache Refine source code and flush all I/D-Cache before update L2 cache register. Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
2023-06-26 18:11:38 +08:00
#if DT_HAS_COMPAT_STATUS_OKAY(andestech_atcsmu100)
/* SMU Register offset */
#define SMU_SYSTEMCFG 0x08
/* SMU Helper Constant */
#define SMU_SYSTEMCFG_L2C BIT(8)
#endif
soc: riscv: andes_v5: initial support of Andes L2 cache controller This initial support of L2C driver only contains cache enable and HW capability checking. Cache management operation isn't supported yet in this driver. Signed-off-by: Jim Shu <cwshu@andestech.com>
2021-07-29 12:39:27 +08:00
static void andes_v5_l2c_enable(void)
{
soc: riscv: andes_v5: refine Andes L2 cache Refine source code and flush all I/D-Cache before update L2 cache register. Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
2023-06-26 18:11:38 +08:00
uint32_t l2c_ctrl = sys_read32(L2C_CTRL);
soc: riscv: riscv-privilege: andes_v5: reworked Andes L2 cache Detect the L2 cache at runtime and removed unused Kconfig CONFIG_SOC_ANDES_V5_L2_CACHE. Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
2022-07-12 15:59:40 +08:00
soc: riscv: andes_v5: refine Andes L2 cache Refine source code and flush all I/D-Cache before update L2 cache register. Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
2023-06-26 18:11:38 +08:00
/* Enable L2C if I-cache or D-cache is enabled */
if (csr_read(NDS_MCACHE_CTL) & BIT_MASK(2)) {
uint32_t l2c_config = sys_read32(L2C_CONFIG);
soc: riscv: andes_v5: initial support of Andes L2 cache controller This initial support of L2C driver only contains cache enable and HW capability checking. Cache management operation isn't supported yet in this driver. Signed-off-by: Jim Shu <cwshu@andestech.com>
2021-07-29 12:39:27 +08:00
soc: riscv: andes_v5: refine Andes L2 cache Refine source code and flush all I/D-Cache before update L2 cache register. Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
2023-06-26 18:11:38 +08:00
/* Memory barrier, flush all I/D-Cache before setting L2C */
__asm__ volatile ("fence.i");
soc: riscv: andes_v5: initial support of Andes L2 cache controller This initial support of L2C driver only contains cache enable and HW capability checking. Cache management operation isn't supported yet in this driver. Signed-off-by: Jim Shu <cwshu@andestech.com>
2021-07-29 12:39:27 +08:00
soc: riscv: andes_v5: refine Andes L2 cache Refine source code and flush all I/D-Cache before update L2 cache register. Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
2023-06-26 18:11:38 +08:00
l2c_ctrl |= (L2C_CTRL_IPFDPT_3 | L2C_CTRL_DPFDPT_8);
sys_write32(l2c_ctrl, L2C_CTRL);
soc: riscv: andes_v5: initial support of Andes L2 cache controller This initial support of L2C driver only contains cache enable and HW capability checking. Cache management operation isn't supported yet in this driver. Signed-off-by: Jim Shu <cwshu@andestech.com>
2021-07-29 12:39:27 +08:00
soc: riscv: andes_v5: refine Andes L2 cache Refine source code and flush all I/D-Cache before update L2 cache register. Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
2023-06-26 18:11:38 +08:00
/* Enable L2C for Gen1 L2C, Gen2 L2C defaults to enable */
if ((l2c_config & L2C_CONFIG_VER) < (16 << 24)) {
l2c_ctrl = sys_read32(L2C_CTRL);
l2c_ctrl |= L2C_CTRL_CEN;
sys_write32(l2c_ctrl, L2C_CTRL);
soc: riscv: riscv-privilege: andes_v5: reworked Andes L2 cache Detect the L2 cache at runtime and removed unused Kconfig CONFIG_SOC_ANDES_V5_L2_CACHE. Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
2022-07-12 15:59:40 +08:00
}
} else {
soc: riscv: andes_v5: refine Andes L2 cache Refine source code and flush all I/D-Cache before update L2 cache register. Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
2023-06-26 18:11:38 +08:00
/* Disable L2C */
l2c_ctrl &= ~L2C_CTRL_CEN;
sys_write32(l2c_ctrl, L2C_CTRL);
soc: riscv: riscv-privilege: andes_v5: reworked Andes L2 cache Detect the L2 cache at runtime and removed unused Kconfig CONFIG_SOC_ANDES_V5_L2_CACHE. Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
2022-07-12 15:59:40 +08:00
}
soc: riscv: andes_v5: initial support of Andes L2 cache controller This initial support of L2C driver only contains cache enable and HW capability checking. Cache management operation isn't supported yet in this driver. Signed-off-by: Jim Shu <cwshu@andestech.com>
2021-07-29 12:39:27 +08:00
}
init: remove the need for a dummy device pointer in SYS_INIT functions The init infrastructure, found in `init.h`, is currently used by: - `SYS_INIT`: to call functions before `main` - `DEVICE_*`: to initialize devices They are all sorted according to an initialization level + a priority. `SYS_INIT` calls are really orthogonal to devices, however, the required function signature requires a `const struct device *dev` as a first argument. The only reason for that is because the same init machinery is used by devices, so we have something like: ```c struct init_entry { int (*init)(const struct device *dev); /* only set by DEVICE_*, otherwise NULL */ const struct device *dev; } ``` As a result, we end up with such weird/ugly pattern: ```c static int my_init(const struct device *dev) { /* always NULL! add ARG_UNUSED to avoid compiler warning */ ARG_UNUSED(dev); ... } ``` This is really a result of poor internals isolation. This patch proposes a to make init entries more flexible so that they can accept sytem initialization calls like this: ```c static int my_init(void) { ... } ``` This is achieved using a union: ```c union init_function { /* for SYS_INIT, used when init_entry.dev == NULL */ int (*sys)(void); /* for DEVICE*, used when init_entry.dev != NULL */ int (*dev)(const struct device *dev); }; struct init_entry { /* stores init function (either for SYS_INIT or DEVICE*) union init_function init_fn; /* stores device pointer for DEVICE*, NULL for SYS_INIT. Allows * to know which union entry to call. */ const struct device *dev; } ``` This solution **does not increase ROM usage**, and allows to offer clean public APIs for both SYS_INIT and DEVICE*. Note that however, init machinery keeps a coupling with devices. **NOTE**: This is a breaking change! All `SYS_INIT` functions will need to be converted to the new signature. See the script offered in the following commit. Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no> init: convert SYS_INIT functions to the new signature Conversion scripted using scripts/utils/migrate_sys_init.py. Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no> manifest: update projects for SYS_INIT changes Update modules with updated SYS_INIT calls: - hal_ti - lvgl - sof - TraceRecorderSource Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no> tests: devicetree: devices: adjust test Adjust test according to the recently introduced SYS_INIT infrastructure. Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no> tests: kernel: threads: adjust SYS_INIT call Adjust to the new signature: int (*init_fn)(void); Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-10-19 09:33:44 +02:00
static int andes_v5_l2c_init(void)
soc: riscv: andes_v5: initial support of Andes L2 cache controller This initial support of L2C driver only contains cache enable and HW capability checking. Cache management operation isn't supported yet in this driver. Signed-off-by: Jim Shu <cwshu@andestech.com>
2021-07-29 12:39:27 +08:00
{
soc: riscv: andes_v5: refine Andes L2 cache Refine source code and flush all I/D-Cache before update L2 cache register. Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
2023-06-26 18:11:38 +08:00
#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(syscon), andestech_atcsmu100, okay)
soc: riscv: andes_v5: use syscon driver instead of accessing dts directly Access syscon area by driver instead of parsing dts node. Signed-off-by: Wei-Tai Lee <wtlee@andestech.com>
2022-08-19 17:48:10 +08:00
const struct device *const syscon_dev = DEVICE_DT_GET(DT_NODELABEL(syscon));
if (device_is_ready(syscon_dev)) {
soc: riscv: andes_v5: refine Andes L2 cache Refine source code and flush all I/D-Cache before update L2 cache register. Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
2023-06-26 18:11:38 +08:00
uint32_t system_cfg;
soc: riscv: andes_v5: use syscon driver instead of accessing dts directly Access syscon area by driver instead of parsing dts node. Signed-off-by: Wei-Tai Lee <wtlee@andestech.com>
2022-08-19 17:48:10 +08:00
syscon_read_reg(syscon_dev, SMU_SYSTEMCFG, &system_cfg);
soc: riscv: andes_v5: initial support of Andes L2 cache controller This initial support of L2C driver only contains cache enable and HW capability checking. Cache management operation isn't supported yet in this driver. Signed-off-by: Jim Shu <cwshu@andestech.com>
2021-07-29 12:39:27 +08:00
soc: riscv: andes_v5: refine Andes L2 cache Refine source code and flush all I/D-Cache before update L2 cache register. Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
2023-06-26 18:11:38 +08:00
/* Platform doesn't have L2C */
soc: riscv: andes_v5: use syscon driver instead of accessing dts directly Access syscon area by driver instead of parsing dts node. Signed-off-by: Wei-Tai Lee <wtlee@andestech.com>
2022-08-19 17:48:10 +08:00
if (!(system_cfg & SMU_SYSTEMCFG_L2C)) {
return -ENODEV;
}
soc: riscv: andes_v5: Fix system initialization for L2C - Put L2C init level in pre_kernel_2 to wait for syscon driver - Check if SMU exists when preprocessing Signed-off-by: Wei-Tai Lee <wtlee@andestech.com>
2022-09-02 16:07:14 +08:00
} else {
soc: riscv: andes_v5: refine Andes L2 cache Refine source code and flush all I/D-Cache before update L2 cache register. Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
2023-06-26 18:11:38 +08:00
LOG_ERR("Syscon driver should be initialized before L2 Cache "
"initialization.");
soc: riscv: andes_v5: initial support of Andes L2 cache controller This initial support of L2C driver only contains cache enable and HW capability checking. Cache management operation isn't supported yet in this driver. Signed-off-by: Jim Shu <cwshu@andestech.com>
2021-07-29 12:39:27 +08:00
}
soc: riscv: andes_v5: Fix system initialization for L2C - Put L2C init level in pre_kernel_2 to wait for syscon driver - Check if SMU exists when preprocessing Signed-off-by: Wei-Tai Lee <wtlee@andestech.com>
2022-09-02 16:07:14 +08:00
#endif
soc: riscv: andes_v5: initial support of Andes L2 cache controller This initial support of L2C driver only contains cache enable and HW capability checking. Cache management operation isn't supported yet in this driver. Signed-off-by: Jim Shu <cwshu@andestech.com>
2021-07-29 12:39:27 +08:00
andes_v5_l2c_enable();
soc: riscv: andes_v5: refine Andes L2 cache Refine source code and flush all I/D-Cache before update L2 cache register. Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
2023-06-26 18:11:38 +08:00
soc: riscv: andes_v5: initial support of Andes L2 cache controller This initial support of L2C driver only contains cache enable and HW capability checking. Cache management operation isn't supported yet in this driver. Signed-off-by: Jim Shu <cwshu@andestech.com>
2021-07-29 12:39:27 +08:00
return 0;
}
soc: riscv: andes_v5: Fix system initialization for L2C - Put L2C init level in pre_kernel_2 to wait for syscon driver - Check if SMU exists when preprocessing Signed-off-by: Wei-Tai Lee <wtlee@andestech.com>
2022-09-02 16:07:14 +08:00
SYS_INIT(andes_v5_l2c_init, PRE_KERNEL_2, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
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