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zephyr/soc/riscv/riscv-privilege/andes_v5/l2_cache.c

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soc: riscv: andes_v5: initial support of Andes L2 cache controller This initial support of L2C driver only contains cache enable and HW capability checking. Cache management operation isn't supported yet in this driver. Signed-off-by: Jim Shu <cwshu@andestech.com>
2021-07-29 12:39:27 +08:00
/*
* Copyright (c) 2021 Andes Technology Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT andestech_l2c
/**
* @brief Andes V5 L2 Cache Controller driver
*/
soc: migrate includes to <zephyr/...> In order to bring consistency in-tree, migrate all soc code to the new prefix <zephyr/...>. Note that the conversion has been scripted, refer to zephyrproject-rtos#45388 for more details. Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
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#include <zephyr/init.h>
#include <zephyr/kernel.h>
#include <zephyr/arch/cpu.h>
soc: riscv: andes_v5: use syscon driver instead of accessing dts directly Access syscon area by driver instead of parsing dts node. Signed-off-by: Wei-Tai Lee <wtlee@andestech.com>
2022-08-19 17:48:10 +08:00
#include <zephyr/drivers/syscon.h>
soc: riscv: andes_v5: initial support of Andes L2 cache controller This initial support of L2C driver only contains cache enable and HW capability checking. Cache management operation isn't supported yet in this driver. Signed-off-by: Jim Shu <cwshu@andestech.com>
2021-07-29 12:39:27 +08:00
soc: riscv: riscv-privilege: andes_v5: reworked Andes L2 cache Detect the L2 cache at runtime and removed unused Kconfig CONFIG_SOC_ANDES_V5_L2_CACHE. Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
2022-07-12 15:59:40 +08:00
#if DT_NODE_EXISTS(DT_INST(0, andestech_l2c))
soc: riscv: andes_v5: use syscon driver instead of accessing dts directly Access syscon area by driver instead of parsing dts node. Signed-off-by: Wei-Tai Lee <wtlee@andestech.com>
2022-08-19 17:48:10 +08:00
/* SMU Configuration Register offset */
#define SMU_SYSTEMCFG 0x08
/* Register bitmask */
#define SMU_SYSTEMCFG_L2C BIT(8)
soc: riscv: andes_v5: initial support of Andes L2 cache controller This initial support of L2C driver only contains cache enable and HW capability checking. Cache management operation isn't supported yet in this driver. Signed-off-by: Jim Shu <cwshu@andestech.com>
2021-07-29 12:39:27 +08:00
/*
* L2C Register Base Address
*/
soc: riscv: riscv-privilege: andes_v5: reworked Andes L2 cache Detect the L2 cache at runtime and removed unused Kconfig CONFIG_SOC_ANDES_V5_L2_CACHE. Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
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#define ANDES_V5_L2C_BASE DT_INST_REG_ADDR(0)
soc: riscv: andes_v5: initial support of Andes L2 cache controller This initial support of L2C driver only contains cache enable and HW capability checking. Cache management operation isn't supported yet in this driver. Signed-off-by: Jim Shu <cwshu@andestech.com>
2021-07-29 12:39:27 +08:00
/*
* L2C Register Offset
*/
soc: riscv: riscv-privilege: andes_v5: reworked Andes L2 cache Detect the L2 cache at runtime and removed unused Kconfig CONFIG_SOC_ANDES_V5_L2_CACHE. Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
2022-07-12 15:59:40 +08:00
#define L2C_CONFIG 0x00
soc: riscv: andes_v5: initial support of Andes L2 cache controller This initial support of L2C driver only contains cache enable and HW capability checking. Cache management operation isn't supported yet in this driver. Signed-off-by: Jim Shu <cwshu@andestech.com>
2021-07-29 12:39:27 +08:00
#define L2C_CTRL 0x08
/*
* L2C Helper Constant
*/
soc: riscv: riscv-privilege: andes_v5: reworked Andes L2 cache Detect the L2 cache at runtime and removed unused Kconfig CONFIG_SOC_ANDES_V5_L2_CACHE. Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
2022-07-12 15:59:40 +08:00
/* L2 cache version */
#define L2C_CONFIG_VERSION_SHIFT 24
soc: riscv: andes_v5: initial support of Andes L2 cache controller This initial support of L2C driver only contains cache enable and HW capability checking. Cache management operation isn't supported yet in this driver. Signed-off-by: Jim Shu <cwshu@andestech.com>
2021-07-29 12:39:27 +08:00
/* enable L2C */
#define L2C_CTRL_CEN BIT(0)
/* instruction prefetch depth */
#define IPFDPT_FIELD(x) (x << 3)
#define L2C_CTRL_IPFDPT_0 IPFDPT_FIELD(0)
#define L2C_CTRL_IPFDPT_1 IPFDPT_FIELD(1)
#define L2C_CTRL_IPFDPT_2 IPFDPT_FIELD(2)
#define L2C_CTRL_IPFDPT_3 IPFDPT_FIELD(3)
/* data prefetch depth */
#define DPFDPT_FIELD(x) (x << 5)
#define L2C_CTRL_DPFDPT_0 DPFDPT_FIELD(0)
#define L2C_CTRL_DPFDPT_2 DPFDPT_FIELD(1)
#define L2C_CTRL_DPFDPT_4 DPFDPT_FIELD(2)
#define L2C_CTRL_DPFDPT_8 DPFDPT_FIELD(3)
static void andes_v5_l2c_enable(void)
{
include: types: remove ulong_t ulong_t was mainly used in MIPS/RISC-V. Just use "unsigned long". Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-08-25 11:45:38 +02:00
unsigned long mcache_ctl;
soc: riscv: andes_v5: initial support of Andes L2 cache controller This initial support of L2C driver only contains cache enable and HW capability checking. Cache management operation isn't supported yet in this driver. Signed-off-by: Jim Shu <cwshu@andestech.com>
2021-07-29 12:39:27 +08:00
volatile uint64_t *l2c_ctrl =
soc: riscv: riscv-privilege: andes_v5: reworked Andes L2 cache Detect the L2 cache at runtime and removed unused Kconfig CONFIG_SOC_ANDES_V5_L2_CACHE. Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
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INT_TO_POINTER(ANDES_V5_L2C_BASE + L2C_CTRL);
__asm__ volatile ("csrr %0, %1"
: "=r" (mcache_ctl) : "i" (NDS_MCACHE_CTL));
soc: riscv: andes_v5: initial support of Andes L2 cache controller This initial support of L2C driver only contains cache enable and HW capability checking. Cache management operation isn't supported yet in this driver. Signed-off-by: Jim Shu <cwshu@andestech.com>
2021-07-29 12:39:27 +08:00
soc: riscv: riscv-privilege: andes_v5: reworked Andes L2 cache Detect the L2 cache at runtime and removed unused Kconfig CONFIG_SOC_ANDES_V5_L2_CACHE. Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
2022-07-12 15:59:40 +08:00
/* Enable L2 cache if L1 I/D cache enabled */
if (mcache_ctl & (BIT(1) | BIT(0))) {
volatile uint64_t *l2c_config =
INT_TO_POINTER(ANDES_V5_L2C_BASE + L2C_CONFIG);
soc: riscv: andes_v5: initial support of Andes L2 cache controller This initial support of L2C driver only contains cache enable and HW capability checking. Cache management operation isn't supported yet in this driver. Signed-off-by: Jim Shu <cwshu@andestech.com>
2021-07-29 12:39:27 +08:00
soc: riscv: riscv-privilege: andes_v5: reworked Andes L2 cache Detect the L2 cache at runtime and removed unused Kconfig CONFIG_SOC_ANDES_V5_L2_CACHE. Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
2022-07-12 15:59:40 +08:00
*l2c_ctrl |= (L2C_CTRL_IPFDPT_3 | L2C_CTRL_DPFDPT_8);
soc: riscv: andes_v5: initial support of Andes L2 cache controller This initial support of L2C driver only contains cache enable and HW capability checking. Cache management operation isn't supported yet in this driver. Signed-off-by: Jim Shu <cwshu@andestech.com>
2021-07-29 12:39:27 +08:00
soc: riscv: riscv-privilege: andes_v5: reworked Andes L2 cache Detect the L2 cache at runtime and removed unused Kconfig CONFIG_SOC_ANDES_V5_L2_CACHE. Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
2022-07-12 15:59:40 +08:00
/* Enable L2 cache manually if device version less than 0xF0 */
if (!((*l2c_config >> L2C_CONFIG_VERSION_SHIFT) & 0xF0)) {
*l2c_ctrl |= L2C_CTRL_CEN;
}
} else {
/* Disable L2 cache */
*l2c_ctrl &= ~L2C_CTRL_CEN;
}
soc: riscv: andes_v5: initial support of Andes L2 cache controller This initial support of L2C driver only contains cache enable and HW capability checking. Cache management operation isn't supported yet in this driver. Signed-off-by: Jim Shu <cwshu@andestech.com>
2021-07-29 12:39:27 +08:00
}
static int andes_v5_l2c_init(const struct device *dev)
{
soc: riscv: andes_v5: use syscon driver instead of accessing dts directly Access syscon area by driver instead of parsing dts node. Signed-off-by: Wei-Tai Lee <wtlee@andestech.com>
2022-08-19 17:48:10 +08:00
uint32_t system_cfg;
const struct device *const syscon_dev = DEVICE_DT_GET(DT_NODELABEL(syscon));
soc: riscv: andes_v5: initial support of Andes L2 cache controller This initial support of L2C driver only contains cache enable and HW capability checking. Cache management operation isn't supported yet in this driver. Signed-off-by: Jim Shu <cwshu@andestech.com>
2021-07-29 12:39:27 +08:00
ARG_UNUSED(dev);
soc: riscv: andes_v5: use syscon driver instead of accessing dts directly Access syscon area by driver instead of parsing dts node. Signed-off-by: Wei-Tai Lee <wtlee@andestech.com>
2022-08-19 17:48:10 +08:00
if (device_is_ready(syscon_dev)) {
syscon_read_reg(syscon_dev, SMU_SYSTEMCFG, &system_cfg);
soc: riscv: andes_v5: initial support of Andes L2 cache controller This initial support of L2C driver only contains cache enable and HW capability checking. Cache management operation isn't supported yet in this driver. Signed-off-by: Jim Shu <cwshu@andestech.com>
2021-07-29 12:39:27 +08:00
soc: riscv: andes_v5: use syscon driver instead of accessing dts directly Access syscon area by driver instead of parsing dts node. Signed-off-by: Wei-Tai Lee <wtlee@andestech.com>
2022-08-19 17:48:10 +08:00
if (!(system_cfg & SMU_SYSTEMCFG_L2C)) {
/* This SoC doesn't have L2 cache */
return -ENODEV;
}
soc: riscv: andes_v5: initial support of Andes L2 cache controller This initial support of L2C driver only contains cache enable and HW capability checking. Cache management operation isn't supported yet in this driver. Signed-off-by: Jim Shu <cwshu@andestech.com>
2021-07-29 12:39:27 +08:00
}
andes_v5_l2c_enable();
return 0;
}
SYS_INIT(andes_v5_l2c_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
soc: riscv: riscv-privilege: andes_v5: reworked Andes L2 cache Detect the L2 cache at runtime and removed unused Kconfig CONFIG_SOC_ANDES_V5_L2_CACHE. Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
2022-07-12 15:59:40 +08:00
#endif /* DT_NODE_EXISTS(DT_INST(0, andestech_l2c)) */
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