2021-10-26 10:24:20 -05:00
|
|
|
/*
|
|
|
|
* Copyright (c) 2021, NXP
|
|
|
|
*
|
|
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
|
|
*/
|
|
|
|
|
|
|
|
/dts-v1/;
|
|
|
|
|
|
|
|
#include <nxp/nxp_rt1160_cm4.dtsi>
|
|
|
|
#include "mimxrt1160_evk.dtsi"
|
|
|
|
|
|
|
|
/ {
|
|
|
|
model = "NXP MIMXRT1160-EVK board";
|
|
|
|
compatible = "nxp,mimxrt1166";
|
|
|
|
|
|
|
|
chosen {
|
2022-04-19 18:11:43 -05:00
|
|
|
/*
|
|
|
|
* Note: when using DMA, the SRAM region must be set to
|
|
|
|
* a memory region that is not cached by the chip. If the chosen
|
|
|
|
* sram region is changed and DMA is in use, you will
|
|
|
|
* encounter issues!
|
|
|
|
*/
|
2021-10-26 10:24:20 -05:00
|
|
|
zephyr,sram = &sram1;
|
|
|
|
zephyr,console = &lpuart1;
|
|
|
|
zephyr,shell-uart = &lpuart1;
|
2021-11-05 17:31:08 -05:00
|
|
|
zephyr,flash-controller = &flexspi;
|
|
|
|
zephyr,flash = &is25wp128;
|
2021-10-26 10:24:20 -05:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
|
|
sdram0: memory@80000000 {
|
|
|
|
/* Winbond W9825G6KH-5I */
|
|
|
|
device_type = "memory";
|
|
|
|
reg = <0x80000000 DT_SIZE_M(64)>;
|
|
|
|
};
|
|
|
|
|
|
|
|
};
|
|
|
|
|
|
|
|
&lpuart1 {
|
|
|
|
status = "okay";
|
|
|
|
current-speed = <115200>;
|
|
|
|
};
|
2021-11-02 17:31:03 -05:00
|
|
|
|
|
|
|
&lpi2c1 {
|
|
|
|
status = "okay";
|
|
|
|
};
|
2021-11-05 17:31:08 -05:00
|
|
|
|
|
|
|
&flexspi {
|
|
|
|
status = "okay";
|
|
|
|
ahb-prefetch;
|
|
|
|
ahb-read-addr-opt;
|
|
|
|
rx-clock-source = <1>;
|
|
|
|
reg = <0x400cc000 0x4000>, <0x30000000 DT_SIZE_M(16)>;
|
|
|
|
is25wp128: is25wp128@0 {
|
|
|
|
compatible = "nxp,imx-flexspi-nor";
|
|
|
|
size = <134217728>;
|
|
|
|
label = "IS25WP128";
|
|
|
|
reg = <0>;
|
|
|
|
spi-max-frequency = <133000000>;
|
|
|
|
status = "okay";
|
|
|
|
jedec-id = [9d 70 17];
|
|
|
|
|
|
|
|
partitions {
|
|
|
|
compatible = "fixed-partitions";
|
|
|
|
#address-cells = <1>;
|
|
|
|
#size-cells = <1>;
|
|
|
|
/* Note: CM4 does not boot from flexspi, but CM7 code will be
|
|
|
|
* stored in slot0
|
|
|
|
*/
|
|
|
|
boot_partition: partition@0 {
|
|
|
|
label = "mcuboot";
|
|
|
|
reg = <0x00000000 DT_SIZE_K(64)>;
|
|
|
|
};
|
|
|
|
slot0_partition: partition@10000 {
|
|
|
|
label = "image-0";
|
|
|
|
reg = <0x00010000 DT_SIZE_M(3)>;
|
|
|
|
};
|
|
|
|
slot1_partition: partition@310000 {
|
|
|
|
label = "image-1";
|
|
|
|
reg = <0x00310000 DT_SIZE_M(3)>;
|
|
|
|
};
|
|
|
|
scratch_partition: partition@610000 {
|
|
|
|
label = "image-scratch";
|
|
|
|
reg = <0x00610000 DT_SIZE_K(128)>;
|
|
|
|
};
|
|
|
|
storage_partition: partition@630000 {
|
|
|
|
label = "storage";
|
|
|
|
reg = <0x00630000 DT_SIZE_K(1856)>;
|
|
|
|
};
|
|
|
|
};
|
|
|
|
};
|
|
|
|
};
|
2021-10-14 09:45:59 -05:00
|
|
|
|
|
|
|
/* Enable GPT for use as a hardware timer. This disables Cortex Systick.
|
|
|
|
* to use systick, change this node from "gpt_hw_timer" to "systick"
|
|
|
|
*/
|
|
|
|
&gpt_hw_timer {
|
|
|
|
status = "okay";
|
|
|
|
};
|
2022-04-19 18:11:43 -05:00
|
|
|
|
|
|
|
&edma_lpsr0 {
|
|
|
|
status = "okay";
|
|
|
|
};
|