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boards: mimxrt11xx: Enable Flash driver on RT1160 and RT1170

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Enable the flash on RT1170 and RT1160. When booting from the CM7 core,
flash will be started in XIP mode and used as storage as well as boot
memory. When booting from the CM4 core, flash is available as storage
only, and does not run in XIP mode.

This commit was tested with the following samples
-flash_shell
-littlefs

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This commit is contained in:
Daniel DeGrasse 2021-11-05 17:31:08 -05:00 • committed by Christopher Friedt
commit e9b74593b8
9 changed files with 244 additions and 5 deletions
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16
boards/arm/mimxrt1160_evk/Kconfig.defconfig
View file

@ -18,4 +18,20 @@ config SYS_CLOCK_HW_CYCLES_PER_SEC
default 240000000 if BOARD_MIMXRT1160_EVK_CM4 && CORTEX_M_SYSTICK
default 600000000 if BOARD_MIMXRT1160_EVK_CM7 && CORTEX_M_SYSTICK
if FLASH
config FLASH_MCUX_FLEXSPI_NOR
default y
# XIP will not be enabled if CPU is cortex m4, since code is flashed to SRAM
config FLASH_MCUX_FLEXSPI_XIP
default y if CPU_CORTEX_M7
choice FLASH_MCUX_FLEXSPI_XIP_MEM_TARGET
default FLASH_MCUX_FLEXSPI_XIP_MEM_ITCM if CPU_CORTEX_M7
default FLASH_MCUX_FLEXSPI_XIP_MEM_SRAM if CPU_CORTEX_M4
endchoice
endif #FLASH
endif # BOARD_MIMXRT1160_EVK_CM7 || BOARD_MIMXRT1160_EVK_CM4

48
boards/arm/mimxrt1160_evk/mimxrt1160_evk_cm4.dts
View file

@ -17,6 +17,8 @@
zephyr,sram = &sram1;
zephyr,console = &lpuart1;
zephyr,shell-uart = &lpuart1;
zephyr,flash-controller = &flexspi;
zephyr,flash = &is25wp128;
};
@ -36,3 +38,49 @@
&lpi2c1 {
status = "okay";
};
&flexspi {
status = "okay";
ahb-prefetch;
ahb-read-addr-opt;
rx-clock-source = <1>;
reg = <0x400cc000 0x4000>, <0x30000000 DT_SIZE_M(16)>;
is25wp128: is25wp128@0 {
compatible = "nxp,imx-flexspi-nor";
size = <134217728>;
label = "IS25WP128";
reg = <0>;
spi-max-frequency = <133000000>;
status = "okay";
jedec-id = [9d 70 17];
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
/* Note: CM4 does not boot from flexspi, but CM7 code will be
* stored in slot0
*/
boot_partition: partition@0 {
label = "mcuboot";
reg = <0x00000000 DT_SIZE_K(64)>;
};
slot0_partition: partition@10000 {
label = "image-0";
reg = <0x00010000 DT_SIZE_M(3)>;
};
slot1_partition: partition@310000 {
label = "image-1";
reg = <0x00310000 DT_SIZE_M(3)>;
};
scratch_partition: partition@610000 {
label = "image-scratch";
reg = <0x00610000 DT_SIZE_K(128)>;
};
storage_partition: partition@630000 {
label = "storage";
reg = <0x00630000 DT_SIZE_K(1856)>;
};
};
};
};

41
boards/arm/mimxrt1160_evk/mimxrt1160_evk_cm7.dts
View file

@ -15,10 +15,14 @@
chosen {
zephyr,sram = &sdram0;
zephyr,itcm = &itcm;
zephyr,dtcm = &dtcm;
zephyr,console = &lpuart1;
zephyr,shell-uart = &lpuart1;
zephyr,canbus = &flexcan3;
zephyr,flash-controller = &flexspi;
zephyr,flash = &is25wp128;
zephyr,code-partition = &slot0_partition;
};
sdram0: memory@80000000 {
@ -46,16 +50,49 @@
status = "okay";
};
&flexspi1 {
&flexspi {
status = "okay";
ahb-prefetch;
ahb-read-addr-opt;
rx-clock-source = <1>;
reg = <0x400cc000 0x4000>, <0x30000000 DT_SIZE_M(16)>;
is25wp128: is25wp128@0 {
compatible = "issi,is25wp128";
compatible = "nxp,imx-flexspi-nor";
size = <134217728>;
label = "IS25WP128";
reg = <0>;
spi-max-frequency = <133000000>;
status = "okay";
jedec-id = [9d 70 17];
erase-block-size = <4096>;
write-block-size = <1>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
boot_partition: partition@0 {
label = "mcuboot";
reg = <0x00000000 DT_SIZE_K(64)>;
};
slot0_partition: partition@10000 {
label = "image-0";
reg = <0x00010000 DT_SIZE_M(3)>;
};
slot1_partition: partition@310000 {
label = "image-1";
reg = <0x00310000 DT_SIZE_M(3)>;
};
scratch_partition: partition@610000 {
label = "image-scratch";
reg = <0x00610000 DT_SIZE_K(128)>;
};
storage_partition: partition@630000 {
label = "storage";
reg = <0x00630000 DT_SIZE_K(1856)>;
};
};
};
};

18
boards/arm/mimxrt1160_evk/pinmux.c
View file

@ -76,6 +76,24 @@ static int mimxrt1160_evk_init(const struct device *dev)
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_04_FLEXPWM1_PWM2_A, 0U);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexspi), okay) && CONFIG_MEMC_MCUX_FLEXSPI
/* Force input on all FLEXSPI pads */
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B2_05_FLEXSPI1_A_DQS, 1U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B2_06_FLEXSPI1_A_SS0_B, 1U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B2_07_FLEXSPI1_A_SCLK, 1U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B2_08_FLEXSPI1_A_DATA00, 1U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B2_09_FLEXSPI1_A_DATA01, 1U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B2_10_FLEXSPI1_A_DATA02, 1U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B2_11_FLEXSPI1_A_DATA03, 1U);
/* Pull down enabled, normal drive strength */
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B2_05_FLEXSPI1_A_DQS, 0x0AU);
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B2_06_FLEXSPI1_A_SS0_B, 0x0AU);
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B2_07_FLEXSPI1_A_SCLK, 0x0AU);
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B2_08_FLEXSPI1_A_DATA00, 0x0AU);
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B2_09_FLEXSPI1_A_DATA01, 0x0AU);
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B2_10_FLEXSPI1_A_DATA02, 0x0AU);
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B2_11_FLEXSPI1_A_DATA03, 0x0AU);
#endif
return 0;
}

17
boards/arm/mimxrt1170_evk/Kconfig.defconfig
View file

@ -25,6 +25,21 @@ config SDMMC_USDHC_DAT3_PWR_TOGGLE
config SDMMC_USDHC_DAT3_PWR_DELAY
default 1000
endif
endif # DISK_DRIVERS
if FLASH
config FLASH_MCUX_FLEXSPI_NOR
default y
config FLASH_MCUX_FLEXSPI_XIP
default y if CPU_CORTEX_M7
choice FLASH_MCUX_FLEXSPI_XIP_MEM_TARGET
default FLASH_MCUX_FLEXSPI_XIP_MEM_ITCM if CPU_CORTEX_M7
default FLASH_MCUX_FLEXSPI_XIP_MEM_SRAM if CPU_CORTEX_M4
endchoice
endif #FLASH
endif # BOARD_MIMXRT1170_EVK_CM7 || BOARD_MIMXRT1170_EVK_CM4

48
boards/arm/mimxrt1170_evk/mimxrt1170_evk_cm4.dts
View file

@ -18,6 +18,8 @@
zephyr,console = &lpuart1;
zephyr,shell-uart = &lpuart1;
zephyr,canbus = &flexcan2;
zephyr,flash-controller = &flexspi;
zephyr,flash = &is25wp128;
};
sdram0: memory@80000000 {
@ -36,3 +38,49 @@
&lpi2c1 {
status = "okay";
};
&flexspi {
status = "okay";
ahb-prefetch;
ahb-read-addr-opt;
rx-clock-source = <1>;
reg = <0x400cc000 0x4000>, <0x30000000 DT_SIZE_M(16)>;
is25wp128: is25wp128@0 {
compatible = "nxp,imx-flexspi-nor";
size = <134217728>;
label = "IS25WP128";
reg = <0>;
spi-max-frequency = <133000000>;
status = "okay";
jedec-id = [9d 70 17];
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
/* Note: CM4 does not boot from flexspi, but CM7 code will be
* stored in slot0
*/
boot_partition: partition@0 {
label = "mcuboot";
reg = <0x00000000 DT_SIZE_K(64)>;
};
slot0_partition: partition@10000 {
label = "image-0";
reg = <0x00010000 DT_SIZE_M(3)>;
};
slot1_partition: partition@310000 {
label = "image-1";
reg = <0x00310000 DT_SIZE_M(3)>;
};
scratch_partition: partition@610000 {
label = "image-scratch";
reg = <0x00610000 DT_SIZE_K(128)>;
};
storage_partition: partition@630000 {
label = "storage";
reg = <0x00630000 DT_SIZE_K(1856)>;
};
};
};
};

41
boards/arm/mimxrt1170_evk/mimxrt1170_evk_cm7.dts
View file

@ -16,9 +16,13 @@
chosen {
zephyr,sram = &sdram0;
zephyr,dtcm = &dtcm;
zephyr,itcm = &itcm;
zephyr,console = &lpuart1;
zephyr,shell-uart = &lpuart1;
zephyr,canbus = &flexcan3;
zephyr,flash-controller = &flexspi;
zephyr,flash = &is25wp128;
zephyr,code-partition = &slot0_partition;
};
sdram0: memory@80000000 {
@ -46,16 +50,49 @@
status = "okay";
};
&flexspi1 {
&flexspi {
status = "okay";
ahb-prefetch;
ahb-read-addr-opt;
rx-clock-source = <1>;
reg = <0x400cc000 0x4000>, <0x30000000 DT_SIZE_M(16)>;
is25wp128: is25wp128@0 {
compatible = "issi,is25wp128", "jedec,spi-nor";
compatible = "nxp,imx-flexspi-nor";
size = <134217728>;
label = "IS25WP128";
reg = <0>;
spi-max-frequency = <133000000>;
status = "okay";
jedec-id = [9d 70 17];
erase-block-size = <4096>;
write-block-size = <1>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
boot_partition: partition@0 {
label = "mcuboot";
reg = <0x00000000 DT_SIZE_K(64)>;
};
slot0_partition: partition@10000 {
label = "image-0";
reg = <0x00010000 DT_SIZE_M(3)>;
};
slot1_partition: partition@310000 {
label = "image-1";
reg = <0x00310000 DT_SIZE_M(3)>;
};
scratch_partition: partition@610000 {
label = "image-scratch";
reg = <0x00610000 DT_SIZE_K(128)>;
};
storage_partition: partition@630000 {
label = "storage";
reg = <0x00630000 DT_SIZE_K(1856)>;
};
};
};
};

19
boards/arm/mimxrt1170_evk/pinmux.c
View file

@ -167,6 +167,25 @@ static int mimxrt1170_evk_init(const struct device *dev)
IOMUXC_SetPinConfig(IOMUXC_GPIO_LPSR_01_FLEXCAN3_RX, 0x02U);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexspi), okay) && CONFIG_MEMC_MCUX_FLEXSPI
/* Force input on all FLEXSPI pads */
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B2_05_FLEXSPI1_A_DQS, 1U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B2_06_FLEXSPI1_A_SS0_B, 1U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B2_07_FLEXSPI1_A_SCLK, 1U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B2_08_FLEXSPI1_A_DATA00, 1U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B2_09_FLEXSPI1_A_DATA01, 1U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B2_10_FLEXSPI1_A_DATA02, 1U);
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B2_11_FLEXSPI1_A_DATA03, 1U);
/* Pull down enabled, normal drive strength */
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B2_05_FLEXSPI1_A_DQS, 0x0AU);
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B2_06_FLEXSPI1_A_SS0_B, 0x0AU);
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B2_07_FLEXSPI1_A_SCLK, 0x0AU);
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B2_08_FLEXSPI1_A_DATA00, 0x0AU);
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B2_09_FLEXSPI1_A_DATA01, 0x0AU);
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B2_10_FLEXSPI1_A_DATA02, 0x0AU);
IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B2_11_FLEXSPI1_A_DATA03, 0x0AU);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(usdhc1), okay) && CONFIG_DISK_DRIVER_SDMMC
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_32_GPIO_MUX3_IO31, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_34_USDHC1_VSELECT, 0U);

1
samples/subsys/fs/littlefs/sample.yaml
View file

@ -5,4 +5,5 @@ tests:
build_only: true
platform_allow: nrf52840dk_nrf52840 particle_xenon disco_l475_iot1
mimxrt685_evk_cm33 mimxrt1060_evk mimxrt1064_evk qemu_x86 native_posix
mimxrt1160_evk_cm7
tags: filesystem