17d9bea474
SOCs using the EDMA IP that supported caching must locate EDMA transfer control descriptors (TCDs) in non cacheable memory. For M7 cores, this can simply use the "nocache" section. For M4 cores, where the nocache section does not exist, the chosen SRAM section must be a tightly coupled memory block which cannot be cached. Add a note to all boards with M4 SOCs that support caching explaining this issue, and enable EDMA driver to locate TCDs in SRAM. Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
103 lines
2.1 KiB
Text
103 lines
2.1 KiB
Text
/*
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* Copyright (c) 2021, NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/dts-v1/;
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#include <nxp/nxp_rt1160_cm4.dtsi>
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#include "mimxrt1160_evk.dtsi"
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/ {
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model = "NXP MIMXRT1160-EVK board";
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compatible = "nxp,mimxrt1166";
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chosen {
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/*
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* Note: when using DMA, the SRAM region must be set to
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* a memory region that is not cached by the chip. If the chosen
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* sram region is changed and DMA is in use, you will
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* encounter issues!
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*/
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zephyr,sram = &sram1;
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zephyr,console = &lpuart1;
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zephyr,shell-uart = &lpuart1;
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zephyr,flash-controller = &flexspi;
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zephyr,flash = &is25wp128;
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};
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sdram0: memory@80000000 {
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/* Winbond W9825G6KH-5I */
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device_type = "memory";
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reg = <0x80000000 DT_SIZE_M(64)>;
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};
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};
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&lpuart1 {
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status = "okay";
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current-speed = <115200>;
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};
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&lpi2c1 {
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status = "okay";
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};
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&flexspi {
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status = "okay";
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ahb-prefetch;
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ahb-read-addr-opt;
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rx-clock-source = <1>;
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reg = <0x400cc000 0x4000>, <0x30000000 DT_SIZE_M(16)>;
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is25wp128: is25wp128@0 {
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compatible = "nxp,imx-flexspi-nor";
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size = <134217728>;
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label = "IS25WP128";
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reg = <0>;
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spi-max-frequency = <133000000>;
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status = "okay";
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jedec-id = [9d 70 17];
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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/* Note: CM4 does not boot from flexspi, but CM7 code will be
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* stored in slot0
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*/
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boot_partition: partition@0 {
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label = "mcuboot";
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reg = <0x00000000 DT_SIZE_K(64)>;
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};
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slot0_partition: partition@10000 {
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label = "image-0";
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reg = <0x00010000 DT_SIZE_M(3)>;
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};
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slot1_partition: partition@310000 {
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label = "image-1";
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reg = <0x00310000 DT_SIZE_M(3)>;
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};
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scratch_partition: partition@610000 {
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label = "image-scratch";
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reg = <0x00610000 DT_SIZE_K(128)>;
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};
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storage_partition: partition@630000 {
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label = "storage";
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reg = <0x00630000 DT_SIZE_K(1856)>;
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};
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};
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};
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};
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/* Enable GPT for use as a hardware timer. This disables Cortex Systick.
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* to use systick, change this node from "gpt_hw_timer" to "systick"
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*/
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&gpt_hw_timer {
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status = "okay";
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};
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&edma_lpsr0 {
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status = "okay";
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};
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