2020-02-05 01:01:50 +01:00
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/*
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* Copyright (c) 2020 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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2020-03-24 21:45:46 +01:00
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#define DT_DRV_COMPAT microchip_xec_peci
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2020-02-05 01:01:50 +01:00
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#include <errno.h>
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2022-05-06 10:25:46 +02:00
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#include <zephyr/device.h>
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2022-10-11 20:05:39 +02:00
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#include <zephyr/kernel.h>
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2022-03-24 19:28:59 +01:00
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#ifdef CONFIG_SOC_SERIES_MEC172X
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2022-05-06 10:25:46 +02:00
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#include <zephyr/drivers/clock_control/mchp_xec_clock_control.h>
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#include <zephyr/drivers/interrupt_controller/intc_mchp_xec_ecia.h>
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2022-03-24 19:28:59 +01:00
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#endif
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2022-05-06 10:25:46 +02:00
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#include <zephyr/drivers/peci.h>
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#include <zephyr/drivers/pinctrl.h>
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2023-03-15 18:38:09 +01:00
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#include <zephyr/pm/device.h>
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#include <zephyr/pm/policy.h>
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2020-02-05 01:01:50 +01:00
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#include <soc.h>
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2022-05-06 10:25:46 +02:00
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#include <zephyr/logging/log.h>
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2022-10-17 10:24:11 +02:00
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#include <zephyr/irq.h>
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2020-02-05 01:01:50 +01:00
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LOG_MODULE_REGISTER(peci_mchp_xec, CONFIG_PECI_LOG_LEVEL);
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/* Maximum PECI core clock is the main clock 48Mhz */
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#define MAX_PECI_CORE_CLOCK 48000u
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/* 1 ms */
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#define PECI_RESET_DELAY 1000u
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2020-12-30 23:20:40 +01:00
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#define PECI_RESET_DELAY_MS 1u
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2020-02-05 01:01:50 +01:00
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/* 100 us */
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#define PECI_IDLE_DELAY 100u
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/* 5 ms */
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#define PECI_IDLE_TIMEOUT 50u
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2020-10-20 21:07:14 +02:00
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/* Maximum retries */
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#define PECI_TIMEOUT_RETRIES 3u
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2021-02-15 17:49:17 +01:00
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/* Maximum read buffer fill wait retries */
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#define PECI_RX_BUF_FILL_WAIT_RETRY 100u
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2020-10-20 21:07:14 +02:00
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2020-02-05 01:01:50 +01:00
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/* 10 us */
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#define PECI_IO_DELAY 10
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#define OPT_BIT_TIME_MSB_OFS 8u
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#define PECI_FCS_LEN 2
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struct peci_xec_config {
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2022-03-24 19:28:59 +01:00
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struct peci_regs * const regs;
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2020-05-27 18:26:57 +02:00
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uint8_t irq_num;
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2022-03-24 19:28:59 +01:00
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uint8_t girq;
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uint8_t girq_pos;
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uint8_t pcr_idx;
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uint8_t pcr_pos;
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2022-03-24 19:48:38 +01:00
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const struct pinctrl_dev_config *pcfg;
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2020-02-05 01:01:50 +01:00
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};
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2023-03-15 18:38:09 +01:00
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enum peci_pm_policy_state_flag {
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PECI_PM_POLICY_FLAG,
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PECI_PM_POLICY_FLAG_COUNT,
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};
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2020-02-05 01:01:50 +01:00
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struct peci_xec_data {
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struct k_sem tx_lock;
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2020-10-20 21:07:14 +02:00
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uint32_t bitrate;
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int timeout_retries;
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2023-03-15 18:38:09 +01:00
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#ifdef CONFIG_PM_DEVICE
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ATOMIC_DEFINE(pm_policy_state_flag, PECI_PM_POLICY_FLAG_COUNT);
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#endif
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2020-02-05 01:01:50 +01:00
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};
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2023-03-15 18:38:09 +01:00
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#ifdef CONFIG_PM_DEVICE
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static void peci_xec_pm_policy_state_lock_get(struct peci_xec_data *data,
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enum peci_pm_policy_state_flag flag)
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{
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if (atomic_test_and_set_bit(data->pm_policy_state_flag, flag) == 0) {
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pm_policy_state_lock_get(PM_STATE_SUSPEND_TO_IDLE, PM_ALL_SUBSTATES);
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}
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}
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static void peci_xec_pm_policy_state_lock_put(struct peci_xec_data *data,
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enum peci_pm_policy_state_flag flag)
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{
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if (atomic_test_and_clear_bit(data->pm_policy_state_flag, flag) == 1) {
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pm_policy_state_lock_put(PM_STATE_SUSPEND_TO_IDLE, PM_ALL_SUBSTATES);
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}
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}
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#endif
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2022-03-24 19:28:59 +01:00
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#ifdef CONFIG_SOC_SERIES_MEC172X
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static inline void peci_girq_enable(const struct device *dev)
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{
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const struct peci_xec_config * const cfg = dev->config;
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mchp_xec_ecia_girq_src_en(cfg->girq, cfg->girq_pos);
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}
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static inline void peci_girq_status_clear(const struct device *dev)
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{
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const struct peci_xec_config * const cfg = dev->config;
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mchp_soc_ecia_girq_src_clr(cfg->girq, cfg->girq_pos);
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}
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static inline void peci_clr_slp_en(const struct device *dev)
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{
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const struct peci_xec_config * const cfg = dev->config;
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z_mchp_xec_pcr_periph_sleep(cfg->pcr_idx, cfg->pcr_pos, 0);
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}
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#else
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2022-03-24 19:28:59 +01:00
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static inline void peci_girq_enable(const struct device *dev)
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{
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const struct peci_xec_config * const cfg = dev->config;
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MCHP_GIRQ_ENSET(cfg->girq) = BIT(cfg->girq_pos);
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}
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static inline void peci_girq_status_clear(const struct device *dev)
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{
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const struct peci_xec_config * const cfg = dev->config;
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MCHP_GIRQ_SRC(cfg->girq) = BIT(cfg->girq_pos);
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}
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static inline void peci_clr_slp_en(const struct device *dev)
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{
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ARG_UNUSED(dev);
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mchp_pcr_periph_slp_ctrl(PCR_PECI, 0);
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}
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2022-03-24 19:28:59 +01:00
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#endif
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2022-03-24 19:28:59 +01:00
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static int check_bus_idle(struct peci_regs * const regs)
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2020-02-05 01:01:50 +01:00
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{
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2020-05-27 18:26:57 +02:00
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uint8_t delay_cnt = PECI_IDLE_TIMEOUT;
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2020-02-05 01:01:50 +01:00
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/* Wait until PECI bus becomes idle.
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* Note that when IDLE bit in the status register changes, HW do not
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* generate an interrupt, so need to poll.
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*/
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2022-03-24 19:28:59 +01:00
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while (!(regs->STATUS2 & MCHP_PECI_STS2_IDLE)) {
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2020-02-05 01:01:50 +01:00
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k_busy_wait(PECI_IDLE_DELAY);
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delay_cnt--;
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if (!delay_cnt) {
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2020-10-20 21:07:14 +02:00
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LOG_WRN("Bus is busy");
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2020-02-05 01:01:50 +01:00
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return -EBUSY;
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}
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}
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return 0;
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}
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2020-04-30 20:33:38 +02:00
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static int peci_xec_configure(const struct device *dev, uint32_t bitrate)
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2020-02-05 01:01:50 +01:00
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{
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2022-03-24 19:28:59 +01:00
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const struct peci_xec_config * const cfg = dev->config;
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struct peci_xec_data * const data = dev->data;
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struct peci_regs * const regs = cfg->regs;
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2020-05-27 18:26:57 +02:00
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uint16_t value;
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2020-02-05 01:01:50 +01:00
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2022-03-24 19:28:59 +01:00
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data->bitrate = bitrate;
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2020-02-05 01:01:50 +01:00
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/* Power down PECI interface */
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2022-03-24 19:28:59 +01:00
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regs->CONTROL = MCHP_PECI_CTRL_PD;
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2020-02-05 01:01:50 +01:00
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/* Adjust bitrate */
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value = MAX_PECI_CORE_CLOCK / bitrate;
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2022-03-24 19:28:59 +01:00
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regs->OPT_BIT_TIME_LSB = value & MCHP_PECI_OPT_BT_LSB_MASK;
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regs->OPT_BIT_TIME_MSB = ((value >> OPT_BIT_TIME_MSB_OFS) &
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MCHP_PECI_OPT_BT_MSB_MASK);
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2020-02-05 01:01:50 +01:00
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/* Power up PECI interface */
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2022-03-24 19:28:59 +01:00
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regs->CONTROL &= ~MCHP_PECI_CTRL_PD;
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2020-02-05 01:01:50 +01:00
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return 0;
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}
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2020-04-30 20:33:38 +02:00
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static int peci_xec_disable(const struct device *dev)
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2020-02-05 01:01:50 +01:00
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{
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2022-03-24 19:28:59 +01:00
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const struct peci_xec_config * const cfg = dev->config;
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struct peci_regs * const regs = cfg->regs;
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2020-02-05 01:01:50 +01:00
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int ret;
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/* Make sure no transaction is interrupted before disabling the HW */
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2022-03-24 19:28:59 +01:00
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ret = check_bus_idle(regs);
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2020-02-05 01:01:50 +01:00
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if (ret) {
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return ret;
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}
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#ifdef CONFIG_PECI_INTERRUPT_DRIVEN
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2022-03-24 19:28:59 +01:00
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peci_girq_status_clear(dev);
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NVIC_ClearPendingIRQ(cfg->irq_num);
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irq_disable(cfg->irq_num);
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2020-02-05 01:01:50 +01:00
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#endif
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2022-03-24 19:28:59 +01:00
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regs->CONTROL |= MCHP_PECI_CTRL_PD;
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2020-02-05 01:01:50 +01:00
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return 0;
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}
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2020-04-30 20:33:38 +02:00
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static int peci_xec_enable(const struct device *dev)
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2020-02-05 01:01:50 +01:00
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{
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2022-03-24 19:28:59 +01:00
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const struct peci_xec_config * const cfg = dev->config;
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struct peci_regs * const regs = cfg->regs;
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2020-02-05 01:01:50 +01:00
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2022-03-24 19:28:59 +01:00
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regs->CONTROL &= ~MCHP_PECI_CTRL_PD;
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2020-02-05 01:01:50 +01:00
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#ifdef CONFIG_PECI_INTERRUPT_DRIVEN
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2022-03-24 19:28:59 +01:00
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peci_girq_status_clear(dev);
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peci_girq_enable(dev);
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irq_enable(cfg->irq_num);
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2020-02-05 01:01:50 +01:00
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#endif
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return 0;
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}
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2020-10-20 21:07:14 +02:00
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static void peci_xec_bus_recovery(const struct device *dev, bool full_reset)
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{
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2022-03-24 19:28:59 +01:00
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const struct peci_xec_config * const cfg = dev->config;
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struct peci_xec_data * const data = dev->data;
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struct peci_regs * const regs = cfg->regs;
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2020-10-20 21:07:14 +02:00
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LOG_WRN("%s full_reset:%d", __func__, full_reset);
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if (full_reset) {
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2022-03-24 19:28:59 +01:00
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regs->CONTROL = MCHP_PECI_CTRL_PD | MCHP_PECI_CTRL_RST;
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2020-12-30 23:20:40 +01:00
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if (k_is_in_isr()) {
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k_busy_wait(PECI_RESET_DELAY_MS);
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} else {
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k_msleep(PECI_RESET_DELAY);
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}
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2022-03-24 19:28:59 +01:00
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regs->CONTROL &= ~MCHP_PECI_CTRL_RST;
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2020-10-20 21:07:14 +02:00
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2022-03-24 19:28:59 +01:00
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peci_xec_configure(dev, data->bitrate);
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2020-10-20 21:07:14 +02:00
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} else {
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/* Only reset internal FIFOs */
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2022-03-24 19:28:59 +01:00
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regs->CONTROL |= MCHP_PECI_CTRL_FRST;
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2020-10-20 21:07:14 +02:00
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}
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}
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2020-04-30 20:33:38 +02:00
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static int peci_xec_write(const struct device *dev, struct peci_msg *msg)
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2020-02-05 01:01:50 +01:00
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{
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2022-03-24 19:28:59 +01:00
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const struct peci_xec_config * const cfg = dev->config;
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struct peci_xec_data * const data = dev->data;
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struct peci_regs * const regs = cfg->regs;
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2020-02-05 01:01:50 +01:00
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int i;
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int ret;
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struct peci_buf *tx_buf = &msg->tx_buffer;
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struct peci_buf *rx_buf = &msg->rx_buffer;
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/* Check if FIFO is full */
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2022-03-24 19:28:59 +01:00
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if (regs->STATUS2 & MCHP_PECI_STS2_WFF) {
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2020-10-20 21:07:14 +02:00
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LOG_WRN("%s FIFO is full", __func__);
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2020-02-05 01:01:50 +01:00
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return -EIO;
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}
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2022-03-24 19:28:59 +01:00
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regs->CONTROL &= ~MCHP_PECI_CTRL_FRST;
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2020-02-05 01:01:50 +01:00
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/* Add PECI transaction header to TX FIFO */
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2022-03-24 19:28:59 +01:00
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regs->WR_DATA = msg->addr;
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regs->WR_DATA = tx_buf->len;
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regs->WR_DATA = rx_buf->len;
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2020-02-05 01:01:50 +01:00
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2020-11-09 05:43:14 +01:00
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/* Add PECI payload to Tx FIFO only if write length is valid */
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if (tx_buf->len) {
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2022-03-24 19:28:59 +01:00
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regs->WR_DATA = msg->cmd_code;
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2020-11-09 05:43:14 +01:00
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for (i = 0; i < tx_buf->len - 1; i++) {
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2022-03-24 19:28:59 +01:00
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if (!(regs->STATUS2 & MCHP_PECI_STS2_WFF)) {
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regs->WR_DATA = tx_buf->buf[i];
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2020-11-09 05:43:14 +01:00
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}
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2020-02-05 01:01:50 +01:00
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}
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}
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/* Check bus is idle before starting a new transfer */
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2022-03-24 19:28:59 +01:00
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ret = check_bus_idle(regs);
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2020-02-05 01:01:50 +01:00
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if (ret) {
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return ret;
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}
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2022-03-24 19:28:59 +01:00
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regs->CONTROL |= MCHP_PECI_CTRL_TXEN;
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2020-02-05 01:01:50 +01:00
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k_busy_wait(PECI_IO_DELAY);
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/* Wait for transmission to complete */
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#ifdef CONFIG_PECI_INTERRUPT_DRIVEN
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2022-03-24 19:28:59 +01:00
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if (k_sem_take(&data->tx_lock, PECI_IO_DELAY * tx_buf->len)) {
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2020-02-05 01:01:50 +01:00
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return -ETIMEDOUT;
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}
|
|
|
|
#else
|
2020-11-09 05:43:14 +01:00
|
|
|
/* In worst case, overall timeout will be 1msec (100 * 10usec) */
|
|
|
|
uint8_t wait_timeout_cnt = 100;
|
|
|
|
|
2022-03-24 19:28:59 +01:00
|
|
|
while (!(regs->STATUS1 & MCHP_PECI_STS1_EOF)) {
|
2020-02-05 01:01:50 +01:00
|
|
|
k_busy_wait(PECI_IO_DELAY);
|
2020-11-09 05:43:14 +01:00
|
|
|
wait_timeout_cnt--;
|
|
|
|
if (!wait_timeout_cnt) {
|
2020-10-20 21:07:14 +02:00
|
|
|
LOG_WRN("Tx timeout");
|
2022-03-24 19:28:59 +01:00
|
|
|
data->timeout_retries++;
|
2020-10-20 21:07:14 +02:00
|
|
|
/* Full reset only if multiple consecutive failures */
|
2022-03-24 19:28:59 +01:00
|
|
|
if (data->timeout_retries > PECI_TIMEOUT_RETRIES) {
|
2020-10-20 21:07:14 +02:00
|
|
|
peci_xec_bus_recovery(dev, true);
|
|
|
|
} else {
|
|
|
|
peci_xec_bus_recovery(dev, false);
|
|
|
|
}
|
|
|
|
|
2020-02-05 01:01:50 +01:00
|
|
|
return -ETIMEDOUT;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
#endif
|
2022-03-24 19:28:59 +01:00
|
|
|
data->timeout_retries = 0;
|
2020-10-20 21:07:14 +02:00
|
|
|
|
2020-02-05 01:01:50 +01:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2020-04-30 20:33:38 +02:00
|
|
|
static int peci_xec_read(const struct device *dev, struct peci_msg *msg)
|
2020-02-05 01:01:50 +01:00
|
|
|
{
|
2022-03-24 19:28:59 +01:00
|
|
|
const struct peci_xec_config * const cfg = dev->config;
|
|
|
|
struct peci_regs * const regs = cfg->regs;
|
2020-02-05 01:01:50 +01:00
|
|
|
int i;
|
|
|
|
int ret;
|
2020-05-27 18:26:57 +02:00
|
|
|
uint8_t tx_fcs;
|
|
|
|
uint8_t bytes_rcvd;
|
2021-02-15 17:49:17 +01:00
|
|
|
uint8_t wait_timeout_cnt;
|
2020-02-05 01:01:50 +01:00
|
|
|
struct peci_buf *rx_buf = &msg->rx_buffer;
|
|
|
|
|
|
|
|
/* Attempt to read data from RX FIFO */
|
|
|
|
bytes_rcvd = 0;
|
|
|
|
for (i = 0; i < (rx_buf->len + PECI_FCS_LEN); i++) {
|
2021-02-15 17:49:17 +01:00
|
|
|
/* Worst case timeout will be 1msec (100 * 10usec) */
|
|
|
|
wait_timeout_cnt = PECI_RX_BUF_FILL_WAIT_RETRY;
|
|
|
|
/* Wait for read buffer to fill up */
|
2022-03-24 19:28:59 +01:00
|
|
|
while (regs->STATUS2 & MCHP_PECI_STS2_RFE) {
|
2021-02-15 17:49:17 +01:00
|
|
|
k_usleep(PECI_IO_DELAY);
|
|
|
|
wait_timeout_cnt--;
|
|
|
|
if (!wait_timeout_cnt) {
|
|
|
|
LOG_WRN("Rx buffer empty");
|
|
|
|
return -ETIMEDOUT;
|
2020-02-05 01:01:50 +01:00
|
|
|
}
|
|
|
|
}
|
2021-02-15 17:49:17 +01:00
|
|
|
|
|
|
|
if (i == 0) {
|
|
|
|
/* Get write block FCS just for debug */
|
2022-03-24 19:28:59 +01:00
|
|
|
tx_fcs = regs->RD_DATA;
|
2021-02-15 17:49:17 +01:00
|
|
|
LOG_DBG("TX FCS %x", tx_fcs);
|
2022-02-24 08:06:27 +01:00
|
|
|
|
|
|
|
/* If a Ping is done, write Tx fcs to rx buffer*/
|
|
|
|
if (msg->cmd_code == PECI_CMD_PING) {
|
|
|
|
rx_buf->buf[0] = tx_fcs;
|
|
|
|
break;
|
|
|
|
}
|
2021-02-15 17:49:17 +01:00
|
|
|
} else if (i == (rx_buf->len + 1)) {
|
|
|
|
/* Get read block FCS, but don't count it */
|
2022-03-24 19:28:59 +01:00
|
|
|
rx_buf->buf[i-1] = regs->RD_DATA;
|
2021-02-15 17:49:17 +01:00
|
|
|
} else {
|
|
|
|
/* Get response */
|
2022-03-24 19:28:59 +01:00
|
|
|
rx_buf->buf[i-1] = regs->RD_DATA;
|
2021-02-15 17:49:17 +01:00
|
|
|
bytes_rcvd++;
|
|
|
|
}
|
2020-02-05 01:01:50 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Check if transaction is as expected */
|
|
|
|
if (rx_buf->len != bytes_rcvd) {
|
2020-10-20 21:07:14 +02:00
|
|
|
LOG_INF("Incomplete %x vs %x", bytes_rcvd, rx_buf->len);
|
2020-02-05 01:01:50 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Once write-read transaction is complete, ensure bus is idle
|
|
|
|
* before resetting the internal FIFOs
|
|
|
|
*/
|
2022-03-24 19:28:59 +01:00
|
|
|
ret = check_bus_idle(regs);
|
2020-02-05 01:01:50 +01:00
|
|
|
if (ret) {
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2020-04-30 20:33:38 +02:00
|
|
|
static int peci_xec_transfer(const struct device *dev, struct peci_msg *msg)
|
2020-02-05 01:01:50 +01:00
|
|
|
{
|
2022-03-24 19:28:59 +01:00
|
|
|
const struct peci_xec_config * const cfg = dev->config;
|
|
|
|
struct peci_regs * const regs = cfg->regs;
|
2023-03-15 18:38:09 +01:00
|
|
|
int ret = 0;
|
|
|
|
uint8_t err_val = 0;
|
|
|
|
#ifdef CONFIG_PM_DEVICE
|
|
|
|
struct peci_xec_data *data = dev->data;
|
2020-02-05 01:01:50 +01:00
|
|
|
|
2023-03-15 18:38:09 +01:00
|
|
|
peci_xec_pm_policy_state_lock_get(data, PECI_PM_POLICY_FLAG);
|
|
|
|
#endif
|
2020-02-05 01:01:50 +01:00
|
|
|
|
2023-03-15 18:38:09 +01:00
|
|
|
do {
|
|
|
|
ret = peci_xec_write(dev, msg);
|
2020-02-05 01:01:50 +01:00
|
|
|
if (ret) {
|
2023-03-15 18:38:09 +01:00
|
|
|
break;
|
2020-02-05 01:01:50 +01:00
|
|
|
}
|
|
|
|
|
2023-03-15 18:38:09 +01:00
|
|
|
/* If a PECI transmission is successful, it may or not involve
|
|
|
|
* a read operation, check if transaction expects a response
|
|
|
|
* Also perform a read when PECI cmd is Ping to get Write FCS
|
|
|
|
*/
|
|
|
|
if (msg->rx_buffer.len || (msg->cmd_code == PECI_CMD_PING)) {
|
|
|
|
ret = peci_xec_read(dev, msg);
|
|
|
|
if (ret) {
|
|
|
|
break;
|
|
|
|
}
|
2020-02-05 01:01:50 +01:00
|
|
|
}
|
|
|
|
|
2023-03-15 18:38:09 +01:00
|
|
|
/* Cleanup */
|
|
|
|
if (regs->STATUS1 & MCHP_PECI_STS1_EOF) {
|
|
|
|
regs->STATUS1 |= MCHP_PECI_STS1_EOF;
|
2020-02-05 01:01:50 +01:00
|
|
|
}
|
|
|
|
|
2023-03-15 18:38:09 +01:00
|
|
|
/* Check for error conditions and perform bus recovery if necessary */
|
|
|
|
err_val = regs->ERROR;
|
|
|
|
if (err_val) {
|
|
|
|
if (err_val & MCHP_PECI_ERR_RDOV) {
|
|
|
|
LOG_ERR("Read buffer is not empty");
|
|
|
|
}
|
|
|
|
|
|
|
|
if (err_val & MCHP_PECI_ERR_WRUN) {
|
|
|
|
LOG_ERR("Write buffer is not empty");
|
|
|
|
}
|
|
|
|
|
|
|
|
if (err_val & MCHP_PECI_ERR_BERR) {
|
|
|
|
LOG_ERR("PECI bus error");
|
|
|
|
}
|
|
|
|
|
|
|
|
LOG_DBG("PECI err %x", err_val);
|
|
|
|
LOG_DBG("PECI sts1 %x", regs->STATUS1);
|
|
|
|
LOG_DBG("PECI sts2 %x", regs->STATUS2);
|
|
|
|
|
|
|
|
/* ERROR is a clear-on-write register, need to clear errors
|
|
|
|
* occurring at the end of a transaction. A temp variable is
|
|
|
|
* used to overcome complaints by the static code analyzer
|
|
|
|
*/
|
|
|
|
regs->ERROR = err_val;
|
|
|
|
peci_xec_bus_recovery(dev, false);
|
|
|
|
ret = -EIO;
|
|
|
|
break;
|
2020-02-05 01:01:50 +01:00
|
|
|
}
|
2023-03-15 18:38:09 +01:00
|
|
|
} while (0);
|
2020-02-05 01:01:50 +01:00
|
|
|
|
2023-03-15 18:38:09 +01:00
|
|
|
#ifdef CONFIG_PM_DEVICE
|
|
|
|
peci_xec_pm_policy_state_lock_put(data, PECI_PM_POLICY_FLAG);
|
|
|
|
#endif
|
|
|
|
return ret;
|
|
|
|
}
|
2020-10-20 21:07:14 +02:00
|
|
|
|
2023-03-15 18:38:09 +01:00
|
|
|
#ifdef CONFIG_PM_DEVICE
|
|
|
|
static int peci_xec_pm_action(const struct device *dev, enum pm_device_action action)
|
|
|
|
{
|
|
|
|
const struct peci_xec_config *const devcfg = dev->config;
|
|
|
|
struct peci_regs * const regs = devcfg->regs;
|
|
|
|
struct ecs_regs * const ecs_regs = (struct ecs_regs *)(DT_REG_ADDR(DT_NODELABEL(ecs)));
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
switch (action) {
|
|
|
|
case PM_DEVICE_ACTION_RESUME:
|
|
|
|
ret = pinctrl_apply_state(devcfg->pcfg, PINCTRL_STATE_DEFAULT);
|
|
|
|
/* VREF_VTT function is enabled*/
|
|
|
|
ecs_regs->PECI_DIS = 0x00u;
|
|
|
|
|
|
|
|
/* Power up PECI interface */
|
|
|
|
regs->CONTROL &= ~MCHP_PECI_CTRL_PD;
|
|
|
|
break;
|
|
|
|
case PM_DEVICE_ACTION_SUSPEND:
|
|
|
|
regs->CONTROL |= MCHP_PECI_CTRL_PD;
|
|
|
|
/* This bit reduces leakage current through the CPU voltage reference
|
|
|
|
* pin if PECI is not used. VREF_VTT function is disabled.
|
2020-09-10 07:56:59 +02:00
|
|
|
*/
|
2023-03-15 18:38:09 +01:00
|
|
|
ecs_regs->PECI_DIS = 0x01u;
|
|
|
|
|
|
|
|
/* If application does not want to turn off PECI pins it will
|
|
|
|
* not define pinctrl-1 for this node.
|
|
|
|
*/
|
|
|
|
ret = pinctrl_apply_state(devcfg->pcfg, PINCTRL_STATE_SLEEP);
|
|
|
|
if (ret == -ENOENT) { /* pinctrl-1 does not exist. */
|
|
|
|
ret = 0;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
ret = -ENOTSUP;
|
2020-02-05 01:01:50 +01:00
|
|
|
}
|
|
|
|
|
2023-03-15 18:38:09 +01:00
|
|
|
return ret;
|
2020-02-05 01:01:50 +01:00
|
|
|
}
|
2023-03-15 18:38:09 +01:00
|
|
|
#endif /* CONFIG_PM_DEVICE */
|
2020-02-05 01:01:50 +01:00
|
|
|
|
|
|
|
#ifdef CONFIG_PECI_INTERRUPT_DRIVEN
|
isr: Normalize usage of device instance through ISR
The goal of this patch is to replace the 'void *' parameter by 'struct
device *' if they use such variable or just 'const void *' on all
relevant ISRs
This will avoid not-so-nice const qualifier tweaks when device instances
will be constant.
Note that only the ISR passed to IRQ_CONNECT are of interest here.
In order to do so, the script fix_isr.py below is necessary:
from pathlib import Path
import subprocess
import pickle
import mmap
import sys
import re
import os
cocci_template = """
@r_fix_isr_0
@
type ret_type;
identifier P;
identifier D;
@@
-ret_type <!fn!>(void *P)
+ret_type <!fn!>(const struct device *P)
{
...
(
const struct device *D = (const struct device *)P;
|
const struct device *D = P;
)
...
}
@r_fix_isr_1
@
type ret_type;
identifier P;
identifier D;
@@
-ret_type <!fn!>(void *P)
+ret_type <!fn!>(const struct device *P)
{
...
const struct device *D;
...
(
D = (const struct device *)P;
|
D = P;
)
...
}
@r_fix_isr_2
@
type ret_type;
identifier A;
@@
-ret_type <!fn!>(void *A)
+ret_type <!fn!>(const void *A)
{
...
}
@r_fix_isr_3
@
const struct device *D;
@@
-<!fn!>((void *)D);
+<!fn!>(D);
@r_fix_isr_4
@
type ret_type;
identifier D;
identifier P;
@@
-ret_type <!fn!>(const struct device *P)
+ret_type <!fn!>(const struct device *D)
{
...
(
-const struct device *D = (const struct device *)P;
|
-const struct device *D = P;
)
...
}
@r_fix_isr_5
@
type ret_type;
identifier D;
identifier P;
@@
-ret_type <!fn!>(const struct device *P)
+ret_type <!fn!>(const struct device *D)
{
...
-const struct device *D;
...
(
-D = (const struct device *)P;
|
-D = P;
)
...
}
"""
def find_isr(fn):
db = []
data = None
start = 0
try:
with open(fn, 'r+') as f:
data = str(mmap.mmap(f.fileno(), 0).read())
except Exception as e:
return db
while True:
isr = ""
irq = data.find('IRQ_CONNECT', start)
while irq > -1:
p = 1
arg = 1
p_o = data.find('(', irq)
if p_o < 0:
irq = -1
break;
pos = p_o + 1
while p > 0:
if data[pos] == ')':
p -= 1
elif data[pos] == '(':
p += 1
elif data[pos] == ',' and p == 1:
arg += 1
if arg == 3:
isr += data[pos]
pos += 1
isr = isr.strip(',\\n\\t ')
if isr not in db and len(isr) > 0:
db.append(isr)
start = pos
break
if irq < 0:
break
return db
def patch_isr(fn, isr_list):
if len(isr_list) <= 0:
return
for isr in isr_list:
tmplt = cocci_template.replace('<!fn!>', isr)
with open('/tmp/isr_fix.cocci', 'w') as f:
f.write(tmplt)
cmd = ['spatch', '--sp-file', '/tmp/isr_fix.cocci', '--in-place', fn]
subprocess.run(cmd)
def process_files(path):
if path.is_file() and path.suffix in ['.h', '.c']:
p = str(path.parent) + '/' + path.name
isr_list = find_isr(p)
patch_isr(p, isr_list)
elif path.is_dir():
for p in path.iterdir():
process_files(p)
if len(sys.argv) < 2:
print("You need to provide a dir/file path")
sys.exit(1)
process_files(Path(sys.argv[1]))
And is run: ./fix_isr.py <zephyr root directory>
Finally, some files needed manual fixes such.
Fixes #27399
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2020-06-17 14:58:56 +02:00
|
|
|
static void peci_xec_isr(const void *arg)
|
2020-02-05 01:01:50 +01:00
|
|
|
{
|
2022-03-24 19:28:59 +01:00
|
|
|
const struct device *dev = arg;
|
|
|
|
struct peci_xec_config * const cfg = dev->config;
|
|
|
|
struct peci_xec_data * const data = dev->data;
|
|
|
|
struct peci_regs * const regs = cfg->regs;
|
|
|
|
uint8_t peci_error = regs->ERROR;
|
|
|
|
uint8_t peci_status2 = regs->STATUS2;
|
2020-02-05 01:01:50 +01:00
|
|
|
|
2022-03-24 19:28:59 +01:00
|
|
|
peci_girq_status_clear(dev);
|
2020-02-05 01:01:50 +01:00
|
|
|
|
2022-03-24 19:28:59 +01:00
|
|
|
if (peci_error) {
|
|
|
|
regs->ERROR = peci_error;
|
2020-02-05 01:01:50 +01:00
|
|
|
}
|
|
|
|
|
2022-03-24 19:28:59 +01:00
|
|
|
if (peci_status2 & MCHP_PECI_STS2_WFE) {
|
|
|
|
LOG_WRN("TX FIFO empty ST2:%x", peci_status2);
|
|
|
|
k_sem_give(&data->tx_lock);
|
2020-02-05 01:01:50 +01:00
|
|
|
}
|
|
|
|
|
2022-03-24 19:28:59 +01:00
|
|
|
if (peci_status2 & MCHP_PECI_STS2_RFE) {
|
|
|
|
LOG_WRN("RX FIFO full ST2:%x", peci_status2);
|
2020-02-05 01:01:50 +01:00
|
|
|
}
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
static const struct peci_driver_api peci_xec_driver_api = {
|
|
|
|
.config = peci_xec_configure,
|
|
|
|
.enable = peci_xec_enable,
|
|
|
|
.disable = peci_xec_disable,
|
|
|
|
.transfer = peci_xec_transfer,
|
|
|
|
};
|
|
|
|
|
2020-04-30 20:33:38 +02:00
|
|
|
static int peci_xec_init(const struct device *dev)
|
2020-02-05 01:01:50 +01:00
|
|
|
{
|
2022-03-24 19:28:59 +01:00
|
|
|
const struct peci_xec_config * const cfg = dev->config;
|
|
|
|
struct peci_regs * const regs = cfg->regs;
|
2022-11-01 18:21:30 +01:00
|
|
|
struct ecs_regs * const ecs_regs = (struct ecs_regs *)(DT_REG_ADDR(DT_NODELABEL(ecs)));
|
2020-02-05 01:01:50 +01:00
|
|
|
|
2022-03-24 19:48:38 +01:00
|
|
|
int ret = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT);
|
|
|
|
|
|
|
|
if (ret != 0) {
|
|
|
|
LOG_ERR("XEC PECI pinctrl init failed (%d)", ret);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2020-02-05 01:01:50 +01:00
|
|
|
#ifdef CONFIG_PECI_INTERRUPT_DRIVEN
|
2022-03-24 19:28:59 +01:00
|
|
|
k_sem_init(&data->tx_lock, 0, 1);
|
2020-02-05 01:01:50 +01:00
|
|
|
#endif
|
|
|
|
|
2022-03-24 19:28:59 +01:00
|
|
|
peci_clr_slp_en(dev);
|
|
|
|
|
2022-11-01 18:21:30 +01:00
|
|
|
ecs_regs->PECI_DIS = 0x00u;
|
|
|
|
|
2020-02-05 01:01:50 +01:00
|
|
|
/* Reset PECI interface */
|
2022-03-24 19:28:59 +01:00
|
|
|
regs->CONTROL |= MCHP_PECI_CTRL_RST;
|
2020-12-30 23:20:40 +01:00
|
|
|
k_msleep(PECI_RESET_DELAY_MS);
|
2022-03-24 19:28:59 +01:00
|
|
|
regs->CONTROL &= ~MCHP_PECI_CTRL_RST;
|
2020-02-05 01:01:50 +01:00
|
|
|
|
|
|
|
#ifdef CONFIG_PECI_INTERRUPT_DRIVEN
|
|
|
|
/* Enable interrupt for errors */
|
2022-03-24 19:28:59 +01:00
|
|
|
regs->INT_EN1 = (MCHP_PECI_IEN1_EREN | MCHP_PECI_IEN1_EIEN);
|
2020-02-05 01:01:50 +01:00
|
|
|
|
|
|
|
/* Enable interrupt for Tx FIFO is empty */
|
2022-03-24 19:28:59 +01:00
|
|
|
regs->INT_EN2 |= MCHP_PECI_IEN2_ENWFE;
|
2020-02-05 01:01:50 +01:00
|
|
|
/* Enable interrupt for Rx FIFO is full */
|
2022-03-24 19:28:59 +01:00
|
|
|
regs->INT_EN2 |= MCHP_PECI_IEN2_ENRFF;
|
2020-02-05 01:01:50 +01:00
|
|
|
|
2022-03-24 19:28:59 +01:00
|
|
|
regs->CONTROL |= MCHP_PECI_CTRL_MIEN;
|
2020-02-05 01:01:50 +01:00
|
|
|
|
|
|
|
/* Direct NVIC */
|
2022-03-24 19:28:59 +01:00
|
|
|
IRQ_CONNECT(cfg->irq_num,
|
2020-03-24 21:45:46 +01:00
|
|
|
DT_INST_IRQ(0, priority),
|
2020-02-05 01:01:50 +01:00
|
|
|
peci_xec_isr, NULL, 0);
|
|
|
|
#endif
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2022-03-24 19:48:38 +01:00
|
|
|
static struct peci_xec_data peci_data;
|
|
|
|
|
|
|
|
PINCTRL_DT_INST_DEFINE(0);
|
|
|
|
|
|
|
|
static const struct peci_xec_config peci_xec_config = {
|
|
|
|
.regs = (struct peci_regs * const)(DT_INST_REG_ADDR(0)),
|
|
|
|
.irq_num = DT_INST_IRQN(0),
|
|
|
|
.girq = DT_INST_PROP_BY_IDX(0, girqs, 0),
|
|
|
|
.girq_pos = DT_INST_PROP_BY_IDX(0, girqs, 1),
|
|
|
|
.pcr_idx = DT_INST_PROP_BY_IDX(0, pcrs, 0),
|
|
|
|
.pcr_pos = DT_INST_PROP_BY_IDX(0, pcrs, 1),
|
|
|
|
.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(0),
|
|
|
|
};
|
|
|
|
|
2023-03-15 18:38:09 +01:00
|
|
|
PM_DEVICE_DT_INST_DEFINE(0, peci_xec_pm_action);
|
|
|
|
|
2020-12-15 15:12:20 +01:00
|
|
|
DEVICE_DT_INST_DEFINE(0,
|
2020-02-05 01:01:50 +01:00
|
|
|
&peci_xec_init,
|
2023-03-15 18:38:09 +01:00
|
|
|
PM_DEVICE_DT_INST_GET(0),
|
2022-03-24 19:28:59 +01:00
|
|
|
&peci_data, &peci_xec_config,
|
2020-02-05 01:01:50 +01:00
|
|
|
POST_KERNEL, CONFIG_PECI_INIT_PRIORITY,
|
|
|
|
&peci_xec_driver_api);
|