drivers: microchip: Convert microchip drivers to new DT_INST macros
Convert older DT_INST_ macro use in microchip drivers to the new include/devicetree.h DT_INST macro APIs. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit is contained in:
Kumar Gala
Kumar Gala
parent
3af49c5b55
commit
7a81cd9747
11 changed files with 170 additions and 148 deletions
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@ -4,6 +4,8 @@
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT microchip_xec_adc
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#define LOG_LEVEL CONFIG_ADC_LOG_LEVEL
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#include <logging/log.h>
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LOG_MODULE_REGISTER(adc_mchp_xec);
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@ -48,7 +50,7 @@ struct adc_xec_regs {
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};
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#define ADC_XEC_REG_BASE \
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((struct adc_xec_regs *)(DT_INST_0_MICROCHIP_XEC_ADC_BASE_ADDRESS))
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((struct adc_xec_regs *)(DT_INST_REG_ADDR(0)))
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DEVICE_DECLARE(adc_xec);
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@ -293,10 +295,10 @@ static int adc_xec_init(struct device *dev)
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MCHP_GIRQ_SRC(MCHP_ADC_GIRQ) = MCHP_ADC_SNG_DONE_GIRQ_VAL;
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MCHP_GIRQ_ENSET(MCHP_ADC_GIRQ) = MCHP_ADC_SNG_DONE_GIRQ_VAL;
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IRQ_CONNECT(DT_INST_0_MICROCHIP_XEC_ADC_IRQ_0,
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DT_INST_0_MICROCHIP_XEC_ADC_IRQ_0_PRIORITY,
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IRQ_CONNECT(DT_INST_IRQN(0),
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DT_INST_IRQ(0, priority),
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adc_xec_isr, DEVICE_GET(adc_xec), 0);
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irq_enable(DT_INST_0_MICROCHIP_XEC_ADC_IRQ_0);
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irq_enable(DT_INST_IRQN(0));
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adc_context_unlock_unconditionally(&data->ctx);
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@ -309,7 +311,7 @@ static struct adc_xec_data adc_xec_dev_data_0 = {
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ADC_CONTEXT_INIT_SYNC(adc_xec_dev_data_0, ctx),
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};
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DEVICE_AND_API_INIT(adc_xec, DT_INST_0_MICROCHIP_XEC_ADC_LABEL,
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DEVICE_AND_API_INIT(adc_xec, DT_INST_LABEL(0),
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adc_xec_init, &adc_xec_dev_data_0, NULL,
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PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
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&adc_xec_api);
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@ -4,6 +4,8 @@
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT microchip_xec_timer
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/**
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* @file
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* @brief Microchip XEC Counter driver
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@ -307,7 +309,7 @@ static int counter_xec_init(struct device *dev)
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return 0;
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}
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#if defined(DT_INST_0_MICROCHIP_XEC_TIMER)
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#if DT_HAS_DRV_INST(0)
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static void counder_xec_irq_config_0(void);
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@ -315,21 +317,21 @@ static struct counter_xec_data counter_xec_dev_data_0;
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static struct counter_xec_config counter_xec_dev_config_0 = {
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.info = {
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.max_top_value = DT_INST_0_MICROCHIP_XEC_TIMER_MAX_VALUE,
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.freq = DT_INST_0_MICROCHIP_XEC_TIMER_CLOCK_FREQUENCY /
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(1 << DT_INST_0_MICROCHIP_XEC_TIMER_PRESCALER),
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.max_top_value = DT_INST_PROP(0, max_value),
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.freq = DT_INST_PROP(0, clock_frequency) /
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(1 << DT_INST_PROP(0, prescaler)),
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.flags = 0,
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.channels = 1,
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},
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.config_func = counder_xec_irq_config_0,
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.base_address = DT_INST_0_MICROCHIP_XEC_TIMER_BASE_ADDRESS,
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.prescaler = DT_INST_0_MICROCHIP_XEC_TIMER_PRESCALER,
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.girq_id = DT_INST_0_MICROCHIP_XEC_TIMER_GIRQ,
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.girq_bit = DT_INST_0_MICROCHIP_XEC_TIMER_GIRQ_BIT,
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.base_address = DT_INST_REG_ADDR(0),
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.prescaler = DT_INST_PROP(0, prescaler),
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.girq_id = DT_INST_PROP(0, girq),
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.girq_bit = DT_INST_PROP(0, girq_bit),
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};
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DEVICE_AND_API_INIT(counter_xec_0, DT_INST_0_MICROCHIP_XEC_TIMER_LABEL,
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DEVICE_AND_API_INIT(counter_xec_0, DT_INST_LABEL(0),
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counter_xec_init, &counter_xec_dev_data_0,
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&counter_xec_dev_config_0,
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POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
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@ -337,15 +339,15 @@ DEVICE_AND_API_INIT(counter_xec_0, DT_INST_0_MICROCHIP_XEC_TIMER_LABEL,
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static void counder_xec_irq_config_0(void)
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{
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IRQ_CONNECT(DT_INST_0_MICROCHIP_XEC_TIMER_IRQ_0,
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DT_INST_0_MICROCHIP_XEC_TIMER_IRQ_0_PRIORITY,
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IRQ_CONNECT(DT_INST_IRQN(0),
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DT_INST_IRQ(0, priority),
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counter_xec_isr, DEVICE_GET(counter_xec_0), 0);
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irq_enable(DT_INST_0_MICROCHIP_XEC_TIMER_IRQ_0);
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irq_enable(DT_INST_IRQN(0));
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}
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#endif /* DT_INST_0_MICROCHIP_XEC_TIMER */
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#endif /* DT_HAS_DRV_INST(0) */
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#if defined(DT_INST_1_MICROCHIP_XEC_TIMER)
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#if DT_HAS_DRV_INST(1)
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static void counder_xec_irq_config_1(void);
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@ -353,21 +355,21 @@ static struct counter_xec_data counter_xec_dev_data_1;
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static struct counter_xec_config counter_xec_dev_config_1 = {
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.info = {
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.max_top_value = DT_INST_1_MICROCHIP_XEC_TIMER_MAX_VALUE,
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.freq = DT_INST_1_MICROCHIP_XEC_TIMER_CLOCK_FREQUENCY /
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(1 << DT_INST_1_MICROCHIP_XEC_TIMER_PRESCALER),
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.max_top_value = DT_INST_PROP(1, max_value),
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.freq = DT_INST_PROP(1, clock_frequency) /
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(1 << DT_INST_PROP(1, prescaler)),
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.flags = 0,
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.channels = 1,
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},
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.config_func = counder_xec_irq_config_1,
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.base_address = DT_INST_1_MICROCHIP_XEC_TIMER_BASE_ADDRESS,
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.prescaler = DT_INST_1_MICROCHIP_XEC_TIMER_PRESCALER,
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.girq_id = DT_INST_1_MICROCHIP_XEC_TIMER_GIRQ,
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.girq_bit = DT_INST_1_MICROCHIP_XEC_TIMER_GIRQ_BIT,
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.base_address = DT_INST_REG_ADDR(1),
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.prescaler = DT_INST_PROP(1, prescaler),
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.girq_id = DT_INST_PROP(1, girq),
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.girq_bit = DT_INST_PROP(1, girq_bit),
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};
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DEVICE_AND_API_INIT(counter_xec_1, DT_INST_1_MICROCHIP_XEC_TIMER_LABEL,
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DEVICE_AND_API_INIT(counter_xec_1, DT_INST_LABEL(1),
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counter_xec_init, &counter_xec_dev_data_1,
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&counter_xec_dev_config_1,
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POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
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@ -375,15 +377,15 @@ DEVICE_AND_API_INIT(counter_xec_1, DT_INST_1_MICROCHIP_XEC_TIMER_LABEL,
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static void counder_xec_irq_config_1(void)
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{
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IRQ_CONNECT(DT_INST_1_MICROCHIP_XEC_TIMER_IRQ_0,
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DT_INST_1_MICROCHIP_XEC_TIMER_IRQ_0_PRIORITY,
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IRQ_CONNECT(DT_INST_IRQN(1),
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DT_INST_IRQ(1, priority),
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counter_xec_isr, DEVICE_GET(counter_xec_1), 0);
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irq_enable(DT_INST_1_MICROCHIP_XEC_TIMER_IRQ_0);
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irq_enable(DT_INST_IRQN(1));
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}
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#endif /* DT_INST_1_MICROCHIP_XEC_TIMER */
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#endif /* DT_HAS_DRV_INST(1) */
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#if defined(DT_INST_2_MICROCHIP_XEC_TIMER)
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#if DT_HAS_DRV_INST(2)
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static void counder_xec_irq_config_2(void);
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@ -391,21 +393,21 @@ static struct counter_xec_data counter_xec_dev_data_2;
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static struct counter_xec_config counter_xec_dev_config_2 = {
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.info = {
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.max_top_value = DT_INST_2_MICROCHIP_XEC_TIMER_MAX_VALUE,
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.freq = DT_INST_2_MICROCHIP_XEC_TIMER_CLOCK_FREQUENCY /
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(1 << DT_INST_2_MICROCHIP_XEC_TIMER_PRESCALER),
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.max_top_value = DT_INST_PROP(2, max_value),
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.freq = DT_INST_PROP(2, clock_frequency) /
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(1 << DT_INST_PROP(2, prescaler)),
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.flags = 0,
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.channels = 1,
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},
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.config_func = counder_xec_irq_config_2,
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.base_address = DT_INST_2_MICROCHIP_XEC_TIMER_BASE_ADDRESS,
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.prescaler = DT_INST_2_MICROCHIP_XEC_TIMER_PRESCALER,
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.girq_id = DT_INST_2_MICROCHIP_XEC_TIMER_GIRQ,
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.girq_bit = DT_INST_2_MICROCHIP_XEC_TIMER_GIRQ_BIT,
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.base_address = DT_INST_REG_ADDR(2),
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.prescaler = DT_INST_PROP(2, prescaler),
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.girq_id = DT_INST_PROP(2, girq),
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.girq_bit = DT_INST_PROP(2, girq_bit),
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};
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DEVICE_AND_API_INIT(counter_xec_2, DT_INST_2_MICROCHIP_XEC_TIMER_LABEL,
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DEVICE_AND_API_INIT(counter_xec_2, DT_INST_LABEL(2),
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counter_xec_init, &counter_xec_dev_data_2,
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&counter_xec_dev_config_2,
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POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
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@ -413,10 +415,10 @@ DEVICE_AND_API_INIT(counter_xec_2, DT_INST_2_MICROCHIP_XEC_TIMER_LABEL,
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static void counder_xec_irq_config_2(void)
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{
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IRQ_CONNECT(DT_INST_2_MICROCHIP_XEC_TIMER_IRQ,
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DT_INST_2_MICROCHIP_XEC_TIMER_IRQ_PRIORITY,
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IRQ_CONNECT(DT_INST_PROP(2, irq),
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DT_INST_IRQ_BY_NAME(2, priority, irq),
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counter_xec_isr, DEVICE_GET(counter_xec_2), 0);
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irq_enable(DT_INST_2_MICROCHIP_XEC_TIMER_IRQ);
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irq_enable(DT_INST_PROP(2, irq));
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}
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#endif /* DT_INST_2_MICROCHIP_XEC_TIMER */
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#endif /* DT_HAS_DRV_INST(2) */
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@ -4,6 +4,8 @@
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT microchip_xec_espi
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#include <kernel.h>
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#include <soc.h>
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#include <errno.h>
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@ -1025,13 +1027,13 @@ static const struct espi_driver_api espi_xec_driver_api = {
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static struct espi_xec_data espi_xec_data;
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static const struct espi_xec_config espi_xec_config = {
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.base_addr = DT_INST_0_MICROCHIP_XEC_ESPI_BASE_ADDRESS,
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.bus_girq_id = DT_INST_0_MICROCHIP_XEC_ESPI_IO_GIRQ,
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.vw_girq_id = DT_INST_0_MICROCHIP_XEC_ESPI_VW_GIRQ,
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.pc_girq_id = DT_INST_0_MICROCHIP_XEC_ESPI_PC_GIRQ,
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.base_addr = DT_INST_REG_ADDR(0),
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.bus_girq_id = DT_INST_PROP(0, io_girq),
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.vw_girq_id = DT_INST_PROP(0, vw_girq),
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.pc_girq_id = DT_INST_PROP(0, pc_girq),
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};
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DEVICE_AND_API_INIT(espi_xec_0, DT_INST_0_MICROCHIP_XEC_ESPI_LABEL,
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DEVICE_AND_API_INIT(espi_xec_0, DT_INST_LABEL(0),
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&espi_xec_init, &espi_xec_data, &espi_xec_config,
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PRE_KERNEL_2, CONFIG_ESPI_INIT_PRIORITY,
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&espi_xec_driver_api);
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@ -1116,27 +1118,27 @@ static int espi_xec_init(struct device *dev)
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#endif
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/* Enable aggregated interrupt block for eSPI bus events */
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MCHP_GIRQ_BLK_SETEN(config->bus_girq_id);
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IRQ_CONNECT(DT_INST_0_MICROCHIP_XEC_ESPI_IRQ_0,
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DT_INST_0_MICROCHIP_XEC_ESPI_IRQ_0_PRIORITY,
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IRQ_CONNECT(DT_INST_IRQN(0),
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DT_INST_IRQ(0, priority),
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espi_xec_bus_isr,
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DEVICE_GET(espi_xec_0), 0);
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irq_enable(DT_INST_0_MICROCHIP_XEC_ESPI_IRQ_0);
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irq_enable(DT_INST_IRQN(0));
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/* Enable aggregated interrupt block for eSPI VWire events */
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MCHP_GIRQ_BLK_SETEN(config->vw_girq_id);
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IRQ_CONNECT(DT_INST_0_MICROCHIP_XEC_ESPI_IRQ_1,
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DT_INST_0_MICROCHIP_XEC_ESPI_IRQ_1_PRIORITY,
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IRQ_CONNECT(DT_INST_IRQ_BY_IDX(0, 1, irq),
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DT_INST_IRQ_BY_IDX(0, 1, priority),
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espi_xec_vw_isr,
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DEVICE_GET(espi_xec_0), 0);
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irq_enable(DT_INST_0_MICROCHIP_XEC_ESPI_IRQ_1);
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irq_enable(DT_INST_IRQ_BY_IDX(0, 1, irq));
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/* Enable aggregated interrupt block for eSPI peripheral channel */
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MCHP_GIRQ_BLK_SETEN(config->pc_girq_id);
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IRQ_CONNECT(DT_INST_0_MICROCHIP_XEC_ESPI_IRQ_2,
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DT_INST_0_MICROCHIP_XEC_ESPI_IRQ_2_PRIORITY,
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IRQ_CONNECT(DT_INST_IRQ_BY_IDX(0, 2, irq),
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DT_INST_IRQ_BY_IDX(0, 2, priority),
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espi_xec_periph_isr,
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DEVICE_GET(espi_xec_0), 0);
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irq_enable(DT_INST_0_MICROCHIP_XEC_ESPI_IRQ_2);
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irq_enable(DT_INST_IRQ_BY_IDX(0, 2, irq));
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return 0;
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}
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@ -4,6 +4,8 @@
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT microchip_xec_gpio
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#include <errno.h>
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#include <device.h>
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#include <drivers/gpio.h>
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@ -334,7 +336,7 @@ static int gpio_xec_port000_036_init(struct device *dev);
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static const struct gpio_xec_config gpio_xec_port000_036_config = {
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.common = {
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.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_NGPIOS(DT_INST_0_MICROCHIP_XEC_GPIO_NGPIOS),
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.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_NGPIOS(DT_INST_PROP(0, ngpios)),
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},
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.pcr1_base = (u32_t *) DT_GPIO_XEC_GPIO000_036_BASE_ADDR,
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.port_num = MCHP_GPIO_000_036,
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@ -377,7 +379,7 @@ static int gpio_xec_port040_076_init(struct device *dev);
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static const struct gpio_xec_config gpio_xec_port040_076_config = {
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.common = {
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.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_NGPIOS(DT_INST_1_MICROCHIP_XEC_GPIO_NGPIOS),
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.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_NGPIOS(DT_INST_PROP(1, ngpios)),
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},
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.pcr1_base = (u32_t *) DT_GPIO_XEC_GPIO040_076_BASE_ADDR,
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.port_num = MCHP_GPIO_040_076,
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@ -420,7 +422,7 @@ static int gpio_xec_port100_136_init(struct device *dev);
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static const struct gpio_xec_config gpio_xec_port100_136_config = {
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.common = {
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.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_NGPIOS(DT_INST_2_MICROCHIP_XEC_GPIO_NGPIOS),
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.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_NGPIOS(DT_INST_PROP(2, ngpios)),
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},
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.pcr1_base = (u32_t *) DT_GPIO_XEC_GPIO100_136_BASE_ADDR,
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.port_num = MCHP_GPIO_100_136,
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@ -463,7 +465,7 @@ static int gpio_xec_port140_176_init(struct device *dev);
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static const struct gpio_xec_config gpio_xec_port140_176_config = {
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.common = {
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.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_NGPIOS(DT_INST_3_MICROCHIP_XEC_GPIO_NGPIOS),
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.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_NGPIOS(DT_INST_PROP(3, ngpios)),
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},
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.pcr1_base = (u32_t *) DT_GPIO_XEC_GPIO140_176_BASE_ADDR,
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.port_num = MCHP_GPIO_140_176,
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@ -506,7 +508,7 @@ static int gpio_xec_port200_236_init(struct device *dev);
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static const struct gpio_xec_config gpio_xec_port200_236_config = {
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.common = {
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.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_NGPIOS(DT_INST_4_MICROCHIP_XEC_GPIO_NGPIOS),
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.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_NGPIOS(DT_INST_PROP(4, ngpios)),
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},
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.pcr1_base = (u32_t *) DT_GPIO_XEC_GPIO200_236_BASE_ADDR,
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.port_num = MCHP_GPIO_200_236,
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@ -549,7 +551,7 @@ static int gpio_xec_port240_276_init(struct device *dev);
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static const struct gpio_xec_config gpio_xec_port240_276_config = {
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.common = {
|
||||
.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_NGPIOS(DT_INST_5_MICROCHIP_XEC_GPIO_NGPIOS),
|
||||
.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_NGPIOS(DT_INST_PROP(5, ngpios)),
|
||||
},
|
||||
.pcr1_base = (u32_t *) DT_GPIO_XEC_GPIO240_276_BASE_ADDR,
|
||||
.port_num = MCHP_GPIO_240_276,
|
||||
|
|
|
|||
|
|
@ -4,6 +4,8 @@
|
|||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#define DT_DRV_COMPAT microchip_xec_i2c
|
||||
|
||||
#include <drivers/clock_control.h>
|
||||
#include <kernel.h>
|
||||
#include <soc.h>
|
||||
|
|
@ -418,31 +420,31 @@ static int i2c_xec_init(struct device *dev)
|
|||
static struct i2c_xec_data i2c_xec_data_##n; \
|
||||
static const struct i2c_xec_config i2c_xec_config_##n = { \
|
||||
.base_addr = \
|
||||
DT_INST_##n##_MICROCHIP_XEC_I2C_BASE_ADDRESS, \
|
||||
.port_sel = DT_INST_##n##_MICROCHIP_XEC_I2C_PORT_SEL, \
|
||||
DT_INST_REG_ADDR(n), \
|
||||
.port_sel = DT_INST_PROP(n, port_sel), \
|
||||
}; \
|
||||
DEVICE_AND_API_INIT(i2c_xec_##n, \
|
||||
DT_INST_##n##_MICROCHIP_XEC_I2C_LABEL, \
|
||||
DT_INST_LABEL(n), \
|
||||
&i2c_xec_init, &i2c_xec_data_##n, &i2c_xec_config_##n, \
|
||||
POST_KERNEL, CONFIG_I2C_INIT_PRIORITY, \
|
||||
&i2c_xec_driver_api)
|
||||
|
||||
#ifdef DT_INST_0_MICROCHIP_XEC_I2C
|
||||
#if DT_HAS_DRV_INST(0)
|
||||
I2C_XEC_DEVICE(0);
|
||||
#endif
|
||||
|
||||
#ifdef DT_INST_1_MICROCHIP_XEC_I2C
|
||||
#if DT_HAS_DRV_INST(1)
|
||||
I2C_XEC_DEVICE(1);
|
||||
#endif
|
||||
|
||||
#ifdef DT_INST_2_MICROCHIP_XEC_I2C
|
||||
#if DT_HAS_DRV_INST(2)
|
||||
I2C_XEC_DEVICE(2);
|
||||
#endif
|
||||
|
||||
#ifdef DT_INST_3_MICROCHIP_XEC_I2C
|
||||
#if DT_HAS_DRV_INST(3)
|
||||
I2C_XEC_DEVICE(3);
|
||||
#endif
|
||||
|
||||
#ifdef DT_INST_4_MICROCHIP_XEC_I2C
|
||||
#if DT_HAS_DRV_INST(4)
|
||||
I2C_XEC_DEVICE(4);
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -4,6 +4,8 @@
|
|||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#define DT_DRV_COMPAT microchip_xec_kscan
|
||||
|
||||
#include <errno.h>
|
||||
#include <device.h>
|
||||
#include <drivers/kscan.h>
|
||||
|
|
@ -56,7 +58,7 @@ struct kscan_xec_data {
|
|||
};
|
||||
|
||||
static KSCAN_Type *base = (KSCAN_Type *)
|
||||
(DT_INST_0_MICROCHIP_XEC_KSCAN_BASE_ADDRESS);
|
||||
(DT_INST_REG_ADDR(0));
|
||||
|
||||
static struct kscan_xec_data kbd_data;
|
||||
|
||||
|
|
@ -146,7 +148,7 @@ static void scan_matrix_xec_isr(void *arg)
|
|||
ARG_UNUSED(arg);
|
||||
|
||||
MCHP_GIRQ_SRC(MCHP_KSCAN_GIRQ) = BIT(MCHP_KSCAN_GIRQ_POS);
|
||||
irq_disable(DT_INST_0_MICROCHIP_XEC_KSCAN_IRQ_0);
|
||||
irq_disable(DT_INST_IRQN(0));
|
||||
k_sem_give(&kbd_data.poll_lock);
|
||||
LOG_DBG(" ");
|
||||
}
|
||||
|
|
@ -366,7 +368,7 @@ static const struct kscan_driver_api kscan_xec_driver_api = {
|
|||
|
||||
static int kscan_xec_init(struct device *dev);
|
||||
|
||||
DEVICE_AND_API_INIT(kscan_xec, DT_INST_0_MICROCHIP_XEC_KSCAN_LABEL,
|
||||
DEVICE_AND_API_INIT(kscan_xec, DT_INST_LABEL(0),
|
||||
&kscan_xec_init,
|
||||
NULL, NULL,
|
||||
POST_KERNEL, CONFIG_KSCAN_INIT_PRIORITY,
|
||||
|
|
|
|||
|
|
@ -4,6 +4,8 @@
|
|||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#define DT_DRV_COMPAT microchip_xec_peci
|
||||
|
||||
#include <errno.h>
|
||||
#include <device.h>
|
||||
#include <drivers/peci.h>
|
||||
|
|
@ -40,8 +42,8 @@ static struct peci_xec_data peci_data;
|
|||
#endif
|
||||
|
||||
static const struct peci_xec_config peci_xec_config = {
|
||||
.base = (PECI_Type *) DT_INST_0_MICROCHIP_XEC_PECI_BASE_ADDRESS,
|
||||
.irq_num = DT_INST_0_MICROCHIP_XEC_PECI_IRQ_0,
|
||||
.base = (PECI_Type *) DT_INST_REG_ADDR(0),
|
||||
.irq_num = DT_INST_IRQN(0),
|
||||
};
|
||||
|
||||
static int check_bus_idle(PECI_Type *base)
|
||||
|
|
@ -347,13 +349,13 @@ static int peci_xec_init(struct device *dev)
|
|||
|
||||
/* Direct NVIC */
|
||||
IRQ_CONNECT(peci_xec_config.irq_num,
|
||||
DT_INST_0_MICROCHIP_XEC_PECI_IRQ_0_PRIORITY,
|
||||
DT_INST_IRQ(0, priority),
|
||||
peci_xec_isr, NULL, 0);
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
||||
DEVICE_AND_API_INIT(peci_xec, DT_INST_0_MICROCHIP_XEC_PECI_LABEL,
|
||||
DEVICE_AND_API_INIT(peci_xec, DT_INST_LABEL(0),
|
||||
&peci_xec_init,
|
||||
NULL, NULL,
|
||||
POST_KERNEL, CONFIG_PECI_INIT_PRIORITY,
|
||||
|
|
|
|||
|
|
@ -4,6 +4,8 @@
|
|||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#define DT_DRV_COMPAT microchip_xec_ps2
|
||||
|
||||
#include <errno.h>
|
||||
#include <device.h>
|
||||
#include <drivers/ps2.h>
|
||||
|
|
@ -188,15 +190,15 @@ static const struct ps2_driver_api ps2_xec_driver_api = {
|
|||
static int ps2_xec_init_0(struct device *dev);
|
||||
|
||||
static const struct ps2_xec_config ps2_xec_config_0 = {
|
||||
.base = (PS2_Type *) DT_INST_0_MICROCHIP_XEC_PS2_BASE_ADDRESS,
|
||||
.girq_id = DT_INST_0_MICROCHIP_XEC_PS2_GIRQ,
|
||||
.girq_bit = DT_INST_0_MICROCHIP_XEC_PS2_GIRQ_BIT,
|
||||
.isr_nvic = DT_INST_0_MICROCHIP_XEC_PS2_IRQ_0,
|
||||
.base = (PS2_Type *) DT_INST_REG_ADDR(0),
|
||||
.girq_id = DT_INST_PROP(0, girq),
|
||||
.girq_bit = DT_INST_PROP(0, girq_bit),
|
||||
.isr_nvic = DT_INST_IRQN(0),
|
||||
};
|
||||
|
||||
static struct ps2_xec_data ps2_xec_port_data_0;
|
||||
|
||||
DEVICE_AND_API_INIT(ps2_xec_0, DT_INST_0_MICROCHIP_XEC_PS2_LABEL,
|
||||
DEVICE_AND_API_INIT(ps2_xec_0, DT_INST_LABEL(0),
|
||||
&ps2_xec_init_0,
|
||||
&ps2_xec_port_data_0, &ps2_xec_config_0,
|
||||
POST_KERNEL, CONFIG_PS2_INIT_PRIORITY,
|
||||
|
|
@ -211,11 +213,11 @@ static int ps2_xec_init_0(struct device *dev)
|
|||
|
||||
k_sem_init(&data->tx_lock, 0, 1);
|
||||
|
||||
IRQ_CONNECT(DT_INST_0_MICROCHIP_XEC_PS2_IRQ_0,
|
||||
DT_INST_0_MICROCHIP_XEC_PS2_IRQ_0_PRIORITY,
|
||||
IRQ_CONNECT(DT_INST_IRQN(0),
|
||||
DT_INST_IRQ(0, priority),
|
||||
ps2_xec_isr, DEVICE_GET(ps2_xec_0), 0);
|
||||
|
||||
irq_enable(DT_INST_0_MICROCHIP_XEC_PS2_IRQ_0);
|
||||
irq_enable(DT_INST_IRQN(0));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -225,16 +227,16 @@ static int ps2_xec_init_0(struct device *dev)
|
|||
static int ps2_xec_init_1(struct device *dev);
|
||||
|
||||
static const struct ps2_xec_config ps2_xec_config_1 = {
|
||||
.base = (PS2_Type *) DT_INST_1_MICROCHIP_XEC_PS2_BASE_ADDRESS,
|
||||
.girq_id = DT_INST_1_MICROCHIP_XEC_PS2_GIRQ,
|
||||
.girq_bit = DT_INST_1_MICROCHIP_XEC_PS2_GIRQ_BIT,
|
||||
.isr_nvic = DT_INST_1_MICROCHIP_XEC_PS2_IRQ_0,
|
||||
.base = (PS2_Type *) DT_INST_REG_ADDR(1),
|
||||
.girq_id = DT_INST_PROP(1, girq),
|
||||
.girq_bit = DT_INST_PROP(1, girq_bit),
|
||||
.isr_nvic = DT_INST_IRQN(1),
|
||||
|
||||
};
|
||||
|
||||
static struct ps2_xec_data ps2_xec_port_data_1;
|
||||
|
||||
DEVICE_AND_API_INIT(ps2_xec_1, DT_INST_1_MICROCHIP_XEC_PS2_LABEL,
|
||||
DEVICE_AND_API_INIT(ps2_xec_1, DT_INST_LABEL(1),
|
||||
&ps2_xec_init_1,
|
||||
&ps2_xec_port_data_1, &ps2_xec_config_1,
|
||||
POST_KERNEL, CONFIG_PS2_INIT_PRIORITY,
|
||||
|
|
@ -248,11 +250,11 @@ static int ps2_xec_init_1(struct device *dev)
|
|||
|
||||
k_sem_init(&data->tx_lock, 0, 1);
|
||||
|
||||
IRQ_CONNECT(DT_INST_1_MICROCHIP_XEC_PS2_IRQ_0,
|
||||
DT_INST_1_MICROCHIP_XEC_PS2_IRQ_0_PRIORITY,
|
||||
IRQ_CONNECT(DT_INST_IRQN(1),
|
||||
DT_INST_IRQ(1, priority),
|
||||
ps2_xec_isr, DEVICE_GET(ps2_xec_1), 0);
|
||||
|
||||
irq_enable(DT_INST_1_MICROCHIP_XEC_PS2_IRQ_0);
|
||||
irq_enable(DT_INST_IRQN(1));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,5 +1,7 @@
|
|||
/* pwm_mchp_xec.c - Microchip XEC PWM driver */
|
||||
|
||||
#define DT_DRV_COMPAT microchip_xec_pwm
|
||||
|
||||
/*
|
||||
* Copyright (c) 2019 Intel Corporation
|
||||
*
|
||||
|
|
@ -380,119 +382,119 @@ static struct pwm_driver_api pwm_xec_api = {
|
|||
.get_cycles_per_sec = pwm_xec_get_cycles_per_sec
|
||||
};
|
||||
|
||||
#if defined(DT_INST_0_MICROCHIP_XEC_PWM)
|
||||
#if DT_HAS_DRV_INST(0)
|
||||
|
||||
static struct pwm_xec_config pwm_xec_dev_config_0 = {
|
||||
.base_address = DT_INST_0_MICROCHIP_XEC_PWM_BASE_ADDRESS
|
||||
.base_address = DT_INST_REG_ADDR(0)
|
||||
};
|
||||
|
||||
DEVICE_AND_API_INIT(pwm_xec_0, DT_INST_0_MICROCHIP_XEC_PWM_LABEL,
|
||||
DEVICE_AND_API_INIT(pwm_xec_0, DT_INST_LABEL(0),
|
||||
pwm_xec_init, NULL, &pwm_xec_dev_config_0,
|
||||
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
|
||||
&pwm_xec_api);
|
||||
|
||||
#endif /* DT_INST_0_MICROCHIP_XEC_PWM */
|
||||
#endif /* DT_HAS_DRV_INST(0) */
|
||||
|
||||
#if defined(DT_INST_1_MICROCHIP_XEC_PWM)
|
||||
#if DT_HAS_DRV_INST(1)
|
||||
|
||||
static struct pwm_xec_config pwm_xec_dev_config_1 = {
|
||||
.base_address = DT_INST_1_MICROCHIP_XEC_PWM_BASE_ADDRESS
|
||||
.base_address = DT_INST_REG_ADDR(1)
|
||||
};
|
||||
|
||||
DEVICE_AND_API_INIT(pwm_xec_1, DT_INST_1_MICROCHIP_XEC_PWM_LABEL,
|
||||
DEVICE_AND_API_INIT(pwm_xec_1, DT_INST_LABEL(1),
|
||||
pwm_xec_init, NULL, &pwm_xec_dev_config_1,
|
||||
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
|
||||
&pwm_xec_api);
|
||||
|
||||
#endif /* DT_INST_1_MICROCHIP_XEC_PWM */
|
||||
#endif /* DT_HAS_DRV_INST(1) */
|
||||
|
||||
#if defined(DT_INST_2_MICROCHIP_XEC_PWM)
|
||||
#if DT_HAS_DRV_INST(2)
|
||||
|
||||
static struct pwm_xec_config pwm_xec_dev_config_2 = {
|
||||
.base_address = DT_INST_2_MICROCHIP_XEC_PWM_BASE_ADDRESS
|
||||
.base_address = DT_INST_REG_ADDR(2)
|
||||
};
|
||||
|
||||
DEVICE_AND_API_INIT(pwm_xec_2, DT_INST_2_MICROCHIP_XEC_PWM_LABEL,
|
||||
DEVICE_AND_API_INIT(pwm_xec_2, DT_INST_LABEL(2),
|
||||
pwm_xec_init, NULL, &pwm_xec_dev_config_2,
|
||||
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
|
||||
&pwm_xec_api);
|
||||
|
||||
#endif /* DT_INST_2_MICROCHIP_XEC_PWM */
|
||||
#endif /* DT_HAS_DRV_INST(2) */
|
||||
|
||||
#if defined(DT_INST_3_MICROCHIP_XEC_PWM)
|
||||
#if DT_HAS_DRV_INST(3)
|
||||
|
||||
static struct pwm_xec_config pwm_xec_dev_config_3 = {
|
||||
.base_address = DT_INST_3_MICROCHIP_XEC_PWM_BASE_ADDRESS
|
||||
.base_address = DT_INST_REG_ADDR(3)
|
||||
};
|
||||
|
||||
DEVICE_AND_API_INIT(pwm_xec_3, DT_INST_3_MICROCHIP_XEC_PWM_LABEL,
|
||||
DEVICE_AND_API_INIT(pwm_xec_3, DT_INST_LABEL(3),
|
||||
pwm_xec_init, NULL, &pwm_xec_dev_config_3,
|
||||
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
|
||||
&pwm_xec_api);
|
||||
|
||||
#endif /* DT_INST_3_MICROCHIP_XEC_PWM */
|
||||
#endif /* DT_HAS_DRV_INST(3) */
|
||||
|
||||
#if defined(DT_INST_4_MICROCHIP_XEC_PWM)
|
||||
#if DT_HAS_DRV_INST(4)
|
||||
|
||||
static struct pwm_xec_config pwm_xec_dev_config_4 = {
|
||||
.base_address = DT_INST_4_MICROCHIP_XEC_PWM_BASE_ADDRESS
|
||||
.base_address = DT_INST_REG_ADDR(4)
|
||||
};
|
||||
|
||||
DEVICE_AND_API_INIT(pwm_xec_4, DT_INST_4_MICROCHIP_XEC_PWM_LABEL,
|
||||
DEVICE_AND_API_INIT(pwm_xec_4, DT_INST_LABEL(4),
|
||||
pwm_xec_init, NULL, &pwm_xec_dev_config_4,
|
||||
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
|
||||
&pwm_xec_api);
|
||||
|
||||
#endif /* DT_INST_4_MICROCHIP_XEC_PWM */
|
||||
#endif /* DT_HAS_DRV_INST(4) */
|
||||
|
||||
#if defined(DT_INST_5_MICROCHIP_XEC_PWM)
|
||||
#if DT_HAS_DRV_INST(5)
|
||||
|
||||
static struct pwm_xec_config pwm_xec_dev_config_5 = {
|
||||
.base_address = DT_INST_5_MICROCHIP_XEC_PWM_BASE_ADDRESS
|
||||
.base_address = DT_INST_REG_ADDR(5)
|
||||
};
|
||||
|
||||
DEVICE_AND_API_INIT(pwm_xec_5, DT_INST_5_MICROCHIP_XEC_PWM_LABEL,
|
||||
DEVICE_AND_API_INIT(pwm_xec_5, DT_INST_LABEL(5),
|
||||
pwm_xec_init, NULL, &pwm_xec_dev_config_5,
|
||||
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
|
||||
&pwm_xec_api);
|
||||
|
||||
#endif /* DT_INST_5_MICROCHIP_XEC_PWM */
|
||||
#endif /* DT_HAS_DRV_INST(5) */
|
||||
|
||||
#if defined(DT_INST_6_MICROCHIP_XEC_PWM)
|
||||
#if DT_HAS_DRV_INST(6)
|
||||
|
||||
static struct pwm_xec_config pwm_xec_dev_config_6 = {
|
||||
.base_address = DT_INST_6_MICROCHIP_XEC_PWM_BASE_ADDRESS
|
||||
.base_address = DT_INST_REG_ADDR(6)
|
||||
};
|
||||
|
||||
DEVICE_AND_API_INIT(pwm_xec_6, DT_INST_6_MICROCHIP_XEC_PWM_LABEL,
|
||||
DEVICE_AND_API_INIT(pwm_xec_6, DT_INST_LABEL(6),
|
||||
pwm_xec_init, NULL, &pwm_xec_dev_config_6,
|
||||
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
|
||||
&pwm_xec_api);
|
||||
|
||||
#endif /* DT_INST_6_MICROCHIP_XEC_PWM */
|
||||
#endif /* DT_HAS_DRV_INST(6) */
|
||||
|
||||
#if defined(DT_INST_7_MICROCHIP_XEC_PWM)
|
||||
#if DT_HAS_DRV_INST(7)
|
||||
|
||||
static struct pwm_xec_config pwm_xec_dev_config_7 = {
|
||||
.base_address = DT_INST_7_MICROCHIP_XEC_PWM_BASE_ADDRESS
|
||||
.base_address = DT_INST_REG_ADDR(7)
|
||||
};
|
||||
|
||||
DEVICE_AND_API_INIT(pwm_xec_7, DT_INST_7_MICROCHIP_XEC_PWM_LABEL,
|
||||
DEVICE_AND_API_INIT(pwm_xec_7, DT_INST_LABEL(7),
|
||||
pwm_xec_init, NULL, &pwm_xec_dev_config_7,
|
||||
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
|
||||
&pwm_xec_api);
|
||||
|
||||
#endif /* DT_INST_7_MICROCHIP_XEC_PWM */
|
||||
#endif /* DT_HAS_DRV_INST(7) */
|
||||
|
||||
#if defined(DT_INST_8_MICROCHIP_XEC_PWM)
|
||||
#if DT_HAS_DRV_INST(8)
|
||||
|
||||
static struct pwm_xec_config pwm_xec_dev_config_8 = {
|
||||
.base_address = DT_INST_8_MICROCHIP_XEC_PWM_BASE_ADDRESS
|
||||
.base_address = DT_INST_REG_ADDR(8)
|
||||
};
|
||||
|
||||
DEVICE_AND_API_INIT(pwm_xec_8, DT_INST_8_MICROCHIP_XEC_PWM_LABEL,
|
||||
DEVICE_AND_API_INIT(pwm_xec_8, DT_INST_LABEL(8),
|
||||
pwm_xec_init, NULL, &pwm_xec_dev_config_8,
|
||||
POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
|
||||
&pwm_xec_api);
|
||||
|
||||
#endif /* DT_INST_8_MICROCHIP_XEC_PWM */
|
||||
#endif /* DT_HAS_DRV_INST(8) */
|
||||
|
|
|
|||
|
|
@ -4,6 +4,8 @@
|
|||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#define DT_DRV_COMPAT microchip_xec_rtos_timer
|
||||
|
||||
#include <soc.h>
|
||||
#include <drivers/timer/system_timer.h>
|
||||
#include <sys_clock.h>
|
||||
|
|
@ -48,7 +50,7 @@ BUILD_ASSERT_MSG(CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC == 32768,
|
|||
(CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC / CONFIG_SYS_CLOCK_TICKS_PER_SEC)
|
||||
|
||||
#define TIMER_REGS \
|
||||
((RTMR_Type *) DT_INST_0_MICROCHIP_XEC_RTOS_TIMER_BASE_ADDRESS)
|
||||
((RTMR_Type *) DT_INST_REG_ADDR(0))
|
||||
|
||||
/* Mask off bits[31:28] of 32-bit count */
|
||||
#define TIMER_MAX 0x0FFFFFFFUL
|
||||
|
|
@ -159,8 +161,8 @@ void z_clock_set_timeout(s32_t n, bool idle)
|
|||
|
||||
/* turn off to clear any pending interrupt status */
|
||||
TIMER_REGS->CTRL = 0U;
|
||||
MCHP_GIRQ_SRC(DT_INST_0_MICROCHIP_XEC_RTOS_TIMER_GIRQ) =
|
||||
BIT(DT_INST_0_MICROCHIP_XEC_RTOS_TIMER_GIRQ_BIT);
|
||||
MCHP_GIRQ_SRC(DT_INST_PROP(0, girq)) =
|
||||
BIT(DT_INST_PROP(0, girq_bit));
|
||||
NVIC_ClearPendingIRQ(RTMR_IRQn);
|
||||
|
||||
temp = total_cycles;
|
||||
|
|
@ -220,8 +222,8 @@ static void xec_rtos_timer_isr(void *arg)
|
|||
|
||||
k_spinlock_key_t key = k_spin_lock(&lock);
|
||||
|
||||
MCHP_GIRQ_SRC(DT_INST_0_MICROCHIP_XEC_RTOS_TIMER_GIRQ) =
|
||||
BIT(DT_INST_0_MICROCHIP_XEC_RTOS_TIMER_GIRQ_BIT);
|
||||
MCHP_GIRQ_SRC(DT_INST_PROP(0, girq)) =
|
||||
BIT(DT_INST_PROP(0, girq_bit));
|
||||
|
||||
/* Restart the timer as early as possible to minimize drift... */
|
||||
timer_restart(MAX_TICKS * CYCLES_PER_TICK);
|
||||
|
|
@ -253,8 +255,8 @@ static void xec_rtos_timer_isr(void *arg)
|
|||
|
||||
k_spinlock_key_t key = k_spin_lock(&lock);
|
||||
|
||||
MCHP_GIRQ_SRC(DT_INST_0_MICROCHIP_XEC_RTOS_TIMER_GIRQ) =
|
||||
BIT(DT_INST_0_MICROCHIP_XEC_RTOS_TIMER_GIRQ_BIT);
|
||||
MCHP_GIRQ_SRC(DT_INST_PROP(0, girq)) =
|
||||
BIT(DT_INST_PROP(0, girq_bit));
|
||||
|
||||
/* Restart the timer as early as possible to minimize drift... */
|
||||
timer_restart(cached_icr);
|
||||
|
|
@ -323,16 +325,16 @@ int z_clock_driver_init(struct device *device)
|
|||
#endif
|
||||
|
||||
TIMER_REGS->CTRL = 0U;
|
||||
MCHP_GIRQ_SRC(DT_INST_0_MICROCHIP_XEC_RTOS_TIMER_GIRQ) =
|
||||
BIT(DT_INST_0_MICROCHIP_XEC_RTOS_TIMER_GIRQ_BIT);
|
||||
MCHP_GIRQ_SRC(DT_INST_PROP(0, girq)) =
|
||||
BIT(DT_INST_PROP(0, girq_bit));
|
||||
NVIC_ClearPendingIRQ(RTMR_IRQn);
|
||||
|
||||
IRQ_CONNECT(RTMR_IRQn,
|
||||
DT_INST_0_MICROCHIP_XEC_RTOS_TIMER_IRQ_0_PRIORITY,
|
||||
DT_INST_IRQ(0, priority),
|
||||
xec_rtos_timer_isr, 0, 0);
|
||||
|
||||
MCHP_GIRQ_ENSET(DT_INST_0_MICROCHIP_XEC_RTOS_TIMER_GIRQ) =
|
||||
BIT(DT_INST_0_MICROCHIP_XEC_RTOS_TIMER_GIRQ_BIT);
|
||||
MCHP_GIRQ_ENSET(DT_INST_PROP(0, girq)) =
|
||||
BIT(DT_INST_PROP(0, girq_bit));
|
||||
irq_enable(RTMR_IRQn);
|
||||
|
||||
#ifdef CONFIG_ARCH_HAS_CUSTOM_BUSY_WAIT
|
||||
|
|
|
|||
|
|
@ -1,5 +1,7 @@
|
|||
/* wdt_xec.c - Microchip XEC watchdog driver */
|
||||
|
||||
#define DT_DRV_COMPAT microchip_xec_watchdog
|
||||
|
||||
/*
|
||||
* Copyright (c) 2019 Intel Corporation.
|
||||
*
|
||||
|
|
@ -16,7 +18,7 @@ LOG_MODULE_REGISTER(wdt_mchp_xec);
|
|||
#include <assert.h>
|
||||
|
||||
#define WDT_XEC_REG_BASE \
|
||||
((WDT_Type *)(DT_INST_0_MICROCHIP_XEC_WATCHDOG_BASE_ADDRESS))
|
||||
((WDT_Type *)(DT_INST_REG_ADDR(0)))
|
||||
|
||||
struct wdt_xec_data {
|
||||
wdt_callback_t cb;
|
||||
|
|
@ -167,17 +169,17 @@ static int wdt_xec_init(struct device *dev)
|
|||
|
||||
MCHP_GIRQ_ENSET(MCHP_WDT_GIRQ) = MCHP_WDT_GIRQ_VAL;
|
||||
|
||||
IRQ_CONNECT(DT_INST_0_MICROCHIP_XEC_WATCHDOG_IRQ_0,
|
||||
DT_INST_0_MICROCHIP_XEC_WATCHDOG_IRQ_0_PRIORITY,
|
||||
IRQ_CONNECT(DT_INST_IRQN(0),
|
||||
DT_INST_IRQ(0, priority),
|
||||
wdt_xec_isr, DEVICE_GET(wdt_xec), 0);
|
||||
irq_enable(DT_INST_0_MICROCHIP_XEC_WATCHDOG_IRQ_0);
|
||||
irq_enable(DT_INST_IRQN(0));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct wdt_xec_data wdt_xec_dev_data;
|
||||
|
||||
DEVICE_AND_API_INIT(wdt_xec, DT_INST_0_MICROCHIP_XEC_WATCHDOG_LABEL,
|
||||
DEVICE_AND_API_INIT(wdt_xec, DT_INST_LABEL(0),
|
||||
wdt_xec_init, &wdt_xec_dev_data, NULL,
|
||||
PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
|
||||
&wdt_xec_api);
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue