drivers: peci: Add PECI driver for microchip XEC family
Add PECI driver that support PECI API. Signed-off-by: Jose Alberto Meza <jose.a.meza.arellano@intel.com>
This commit is contained in:
Jose Alberto Meza
Andrew Boie
parent
0b6b2bc17c
commit
55e6b294f2
4 changed files with 370 additions and 1 deletions
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@ -1,3 +1,5 @@
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# SPDX-License-Identifier: Apache-2.0
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zephyr_library()
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zephyr_library()
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zephyr_library_sources_ifdef(CONFIG_PECI_XEC peci_mchp_xec.c)
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@ -10,6 +10,8 @@ menuconfig PECI
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if PECI
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source "drivers/peci/Kconfig.xec"
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module = PECI
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module-str = peci
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source "subsys/logging/Kconfig.template.log_config"
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10
drivers/peci/Kconfig.xec
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10
drivers/peci/Kconfig.xec
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@ -0,0 +1,10 @@
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# Microchip XEC PECI configuration options
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# Copyright (c) 2020 Intel Corporation
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# SPDX-License-Identifier: Apache-2.0
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config PECI_XEC
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bool "XEC Microchip PECI driver"
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depends on SOC_FAMILY_MEC
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help
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Enable the Microchip XEC PECI IO driver.
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355
drivers/peci/peci_mchp_xec.c
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355
drivers/peci/peci_mchp_xec.c
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@ -0,0 +1,355 @@
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/*
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* Copyright (c) 2020 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <errno.h>
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#include <device.h>
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#include <drivers/peci.h>
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#include <soc.h>
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#include <logging/log.h>
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LOG_MODULE_REGISTER(peci_mchp_xec, CONFIG_PECI_LOG_LEVEL);
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/* Maximum PECI core clock is the main clock 48Mhz */
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#define MAX_PECI_CORE_CLOCK 48000u
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/* 1 ms */
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#define PECI_RESET_DELAY 1000u
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/* 100 us */
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#define PECI_IDLE_DELAY 100u
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/* 5 ms */
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#define PECI_IDLE_TIMEOUT 50u
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/* 10 us */
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#define PECI_IO_DELAY 10
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#define OPT_BIT_TIME_MSB_OFS 8u
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#define PECI_FCS_LEN 2
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struct peci_xec_config {
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PECI_Type *base;
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u8_t irq_num;
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};
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struct peci_xec_data {
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struct k_sem tx_lock;
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};
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#ifdef CONFIG_PECI_INTERRUPT_DRIVEN
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static struct peci_xec_data peci_data;
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#endif
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static const struct peci_xec_config peci_xec_config = {
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.base = (PECI_Type *) DT_INST_0_MICROCHIP_XEC_PECI_BASE_ADDRESS,
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.irq_num = DT_INST_0_MICROCHIP_XEC_PECI_IRQ_0,
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};
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static int check_bus_idle(PECI_Type *base)
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{
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u8_t delay_cnt = PECI_IDLE_TIMEOUT;
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/* Wait until PECI bus becomes idle.
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* Note that when IDLE bit in the status register changes, HW do not
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* generate an interrupt, so need to poll.
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*/
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while (!(base->STATUS2 & MCHP_PECI_STS2_IDLE)) {
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k_busy_wait(PECI_IDLE_DELAY);
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delay_cnt--;
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if (!delay_cnt) {
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LOG_WRN("Bus is busy\n");
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return -EBUSY;
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}
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}
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return 0;
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}
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static int peci_xec_configure(struct device *dev, u32_t bitrate)
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{
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ARG_UNUSED(dev);
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PECI_Type *base = peci_xec_config.base;
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u16_t value;
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/* Power down PECI interface */
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base->CONTROL = MCHP_PECI_CTRL_PD;
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/* Adjust bitrate */
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value = MAX_PECI_CORE_CLOCK / bitrate;
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base->OPT_BIT_TIME_LSB = value & MCHP_PECI_OPT_BT_LSB_MASK;
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base->OPT_BIT_TIME_MSB = (value >> OPT_BIT_TIME_MSB_OFS) &
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MCHP_PECI_OPT_BT_MSB_MASK;
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/* Power up PECI interface */
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base->CONTROL &= ~MCHP_PECI_CTRL_PD;
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return 0;
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}
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static int peci_xec_disable(struct device *dev)
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{
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ARG_UNUSED(dev);
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int ret;
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PECI_Type *base = peci_xec_config.base;
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/* Make sure no transaction is interrupted before disabling the HW */
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ret = check_bus_idle(base);
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if (ret) {
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return ret;
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}
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#ifdef CONFIG_PECI_INTERRUPT_DRIVEN
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NVIC_ClearPendingIRQ(peci_xec_config.irq_num);
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irq_disable(peci_xec_config.irq_num);
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#endif
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base->CONTROL |= MCHP_PECI_CTRL_PD;
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return 0;
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}
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static int peci_xec_enable(struct device *dev)
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{
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ARG_UNUSED(dev);
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PECI_Type *base = peci_xec_config.base;
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base->CONTROL &= ~MCHP_PECI_CTRL_PD;
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#ifdef CONFIG_PECI_INTERRUPT_DRIVEN
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irq_enable(peci_xec_config.irq_num);
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#endif
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return 0;
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}
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static int peci_xec_write(struct device *dev, struct peci_msg *msg)
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{
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ARG_UNUSED(dev);
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int i;
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int ret;
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#ifndef CONFIG_PECI_INTERRUPT_DRIVEN
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u8_t wait_timeout;
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#endif
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struct peci_buf *tx_buf = &msg->tx_buffer;
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struct peci_buf *rx_buf = &msg->rx_buffer;
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PECI_Type *base = peci_xec_config.base;
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/* Check if FIFO is full */
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if (base->STATUS2 & MCHP_PECI_STS2_WFF) {
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LOG_WRN("%s FIFO is full\n", __func__);
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return -EIO;
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}
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base->CONTROL &= ~MCHP_PECI_CTRL_FRST;
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/* Add PECI transaction header to TX FIFO */
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base->WR_DATA = msg->addr;
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base->WR_DATA = tx_buf->len;
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base->WR_DATA = rx_buf->len;
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/* PING command doesn't require opcode to be sent */
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if (msg->cmd_code != PECI_CMD_PING) {
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base->WR_DATA = msg->cmd_code;
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}
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/* Add PECI payload data to FIFO */
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for (i = 0; i < tx_buf->len - 1; i++) {
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if (!(base->STATUS2 & MCHP_PECI_STS2_WFF)) {
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base->WR_DATA = tx_buf->buf[i];
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}
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}
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/* Check bus is idle before starting a new transfer */
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ret = check_bus_idle(base);
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if (ret) {
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return ret;
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}
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base->CONTROL |= MCHP_PECI_CTRL_TXEN;
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k_busy_wait(PECI_IO_DELAY);
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/* Wait for transmission to complete */
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#ifdef CONFIG_PECI_INTERRUPT_DRIVEN
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if (k_sem_take(&peci_data.tx_lock, PECI_IO_DELAY * tx_buf->len)) {
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return -ETIMEDOUT;
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}
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#else
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wait_timeout = tx_buf->len;
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while (!(base->STATUS1 & MCHP_PECI_STS1_EOF)) {
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k_busy_wait(PECI_IO_DELAY);
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if (!wait_timeout) {
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LOG_WRN("Tx timeout\n");
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base->CONTROL = MCHP_PECI_CTRL_FRST;
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return -ETIMEDOUT;
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}
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}
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#endif
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return 0;
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}
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static int peci_xec_read(struct device *dev, struct peci_msg *msg)
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{
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ARG_UNUSED(dev);
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int i;
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int ret;
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u8_t tx_fcs;
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u8_t bytes_rcvd;
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struct peci_buf *rx_buf = &msg->rx_buffer;
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PECI_Type *base = peci_xec_config.base;
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/* Attempt to read data from RX FIFO */
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bytes_rcvd = 0;
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for (i = 0; i < (rx_buf->len + PECI_FCS_LEN); i++) {
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/* Check if data available */
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if (!(base->STATUS2 & MCHP_PECI_STS2_RFE)) {
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if (i == 0) {
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/* Get write block FCS just for debug */
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tx_fcs = base->RD_DATA;
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LOG_DBG("TX FCS %x", tx_fcs);
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} else if (i == (rx_buf->len + 1)) {
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/* Get read block FCS, but don't count it */
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rx_buf->buf[i-1] = base->RD_DATA;
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} else {
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/* Get response */
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rx_buf->buf[i-1] = base->RD_DATA;
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bytes_rcvd++;
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}
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}
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}
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/* Check if transaction is as expected */
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if (rx_buf->len != bytes_rcvd) {
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LOG_DBG("Incomplete %x vs %x", bytes_rcvd, rx_buf->len);
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}
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/* Once write-read transaction is complete, ensure bus is idle
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* before resetting the internal FIFOs
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*/
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ret = check_bus_idle(base);
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if (ret) {
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return ret;
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}
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/* Reset internal FIFOs for next transaction */
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base->CONTROL = MCHP_PECI_CTRL_FRST;
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return 0;
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}
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static int peci_xec_transfer(struct device *dev, struct peci_msg *msg)
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{
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ARG_UNUSED(dev);
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int ret;
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PECI_Type *base = peci_xec_config.base;
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ret = peci_xec_write(dev, msg);
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if (ret) {
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return ret;
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}
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/* If a PECI transmission is successful, it may or not involve
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* a read operation, check if transaction expects a response
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*/
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if (msg->rx_buffer.len) {
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ret = peci_xec_read(dev, msg);
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if (ret) {
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return ret;
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}
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}
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/* Cleanup */
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if (base->STATUS1 & MCHP_PECI_STS1_EOF) {
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base->STATUS1 |= MCHP_PECI_STS1_EOF;
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}
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/* Check for error conditions and perform bus recovery if necessary */
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if (base->ERROR) {
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if (base->ERROR & MCHP_PECI_ERR_RDOV) {
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LOG_WRN("Read buffer is not empty\n");
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}
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if (base->ERROR & MCHP_PECI_ERR_WRUN) {
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LOG_WRN("Write buffer is not empty\n");
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}
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if (base->ERROR & MCHP_PECI_ERR_BERR) {
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LOG_WRN("Write buffer is not empty\n");
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}
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base->ERROR = base->ERROR;
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LOG_WRN("Transaction error %x\n", base->ERROR);
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return -EIO;
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}
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return 0;
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}
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#ifdef CONFIG_PECI_INTERRUPT_DRIVEN
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static void peci_xec_isr(void *arg)
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{
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ARG_UNUSED(arg);
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PECI_Type *base = peci_xec_config.base;
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MCHP_GIRQ_SRC(MCHP_PECI_GIRQ) = MCHP_PECI_GIRQ_VAL;
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if (base->ERROR) {
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base->ERROR = base->ERROR;
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}
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if (base->STATUS2 & MCHP_PECI_STS2_WFE) {
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LOG_WRN("TX FIFO empty ST2:%x\n", base->STATUS2);
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k_sem_give(&peci_data.tx_lock);
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}
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if (base->STATUS2 & MCHP_PECI_STS2_RFE) {
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LOG_WRN("RX FIFO full ST2:%x\n", base->STATUS2);
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}
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}
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#endif
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static const struct peci_driver_api peci_xec_driver_api = {
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.config = peci_xec_configure,
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.enable = peci_xec_enable,
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.disable = peci_xec_disable,
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.transfer = peci_xec_transfer,
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};
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static int peci_xec_init(struct device *dev)
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{
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ARG_UNUSED(dev);
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PECI_Type *base = peci_xec_config.base;
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#ifdef CONFIG_PECI_INTERRUPT_DRIVEN
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k_sem_init(&peci_data.tx_lock, 0, 1);
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#endif
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/* Reset PECI interface */
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base->CONTROL |= MCHP_PECI_CTRL_RST;
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k_busy_wait(PECI_RESET_DELAY);
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base->CONTROL &= ~MCHP_PECI_CTRL_RST;
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#ifdef CONFIG_PECI_INTERRUPT_DRIVEN
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/* Enable interrupt for errors */
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base->INT_EN1 = (MCHP_PECI_IEN1_EREN | MCHP_PECI_IEN1_EIEN);
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/* Enable interrupt for Tx FIFO is empty */
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base->INT_EN2 |= MCHP_PECI_IEN2_ENWFE;
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/* Enable interrupt for Rx FIFO is full */
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base->INT_EN2 |= MCHP_PECI_IEN2_ENRFF;
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base->CONTROL |= MCHP_PECI_CTRL_MIEN;
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/* Direct NVIC */
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IRQ_CONNECT(peci_xec_config.irq_num,
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DT_INST_0_MICROCHIP_XEC_PECI_IRQ_0_PRIORITY,
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peci_xec_isr, NULL, 0);
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#endif
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return 0;
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}
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DEVICE_AND_API_INIT(peci_xec, DT_INST_0_MICROCHIP_XEC_PECI_LABEL,
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&peci_xec_init,
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NULL, NULL,
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POST_KERNEL, CONFIG_PECI_INIT_PRIORITY,
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&peci_xec_driver_api);
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