2015-04-11 01:44:37 +02:00
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/*
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2015-08-20 17:04:01 +02:00
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* Copyright (c) 2014-2015 Wind River Systems, Inc.
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2015-04-11 01:44:37 +02:00
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*
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2017-01-19 02:01:01 +01:00
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* SPDX-License-Identifier: Apache-2.0
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2015-04-11 01:44:37 +02:00
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*/
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2015-12-04 16:09:39 +01:00
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/**
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* @file
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* @brief Wrapper around ISRs with logic for context switching
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*
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*
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* Wrapper installed in vector table for handling dynamic interrupts that accept
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* a parameter.
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2015-07-01 23:22:39 +02:00
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*/
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2015-04-11 01:44:37 +02:00
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2016-11-08 16:36:50 +01:00
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#include <offsets_short.h>
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2022-05-09 13:56:13 +02:00
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#include <zephyr/toolchain.h>
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#include <zephyr/linker/sections.h>
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#include <zephyr/sw_isr_table.h>
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#include <zephyr/kernel_structs.h>
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#include <zephyr/arch/cpu.h>
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2018-06-27 10:40:30 +02:00
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#include <swap_macros.h>
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2022-05-09 13:56:13 +02:00
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#include <zephyr/arch/arc/asm-compat/assembler.h>
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2015-04-11 01:44:37 +02:00
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2017-02-13 18:36:32 +01:00
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GTEXT(_isr_wrapper)
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2015-04-11 01:44:37 +02:00
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GTEXT(_isr_demux)
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2020-09-02 00:31:40 +02:00
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#if defined(CONFIG_PM)
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2020-09-02 03:46:30 +02:00
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GTEXT(z_pm_save_idle_exit)
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2015-06-10 01:46:29 +02:00
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#endif
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2015-04-11 01:44:37 +02:00
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/*
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The symbols in this file are not real functions, and neither are
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_rirq_enter/_firq_enter: they are jump points.
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The flow is the following:
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2017-02-13 18:36:32 +01:00
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ISR -> _isr_wrapper -- + -> _rirq_enter -> _isr_demux -> ISR -> _rirq_exit
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2020-02-29 15:58:22 +01:00
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+ -> _firq_enter -> _isr_demux -> ISR -> _firq_exit
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2015-04-11 01:44:37 +02:00
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Context switch explanation:
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The context switch code is spread in these files:
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2020-02-29 15:58:22 +01:00
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isr_wrapper.s, switch.s, swap_macros.h, fast_irq.s, regular_irq.s
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2015-04-11 01:44:37 +02:00
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IRQ stack frame layout:
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2020-02-29 15:58:22 +01:00
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high address
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2015-04-11 01:44:37 +02:00
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2020-02-29 15:58:22 +01:00
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status32
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pc
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lp_count
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lp_start
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lp_end
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blink
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r13
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...
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sp -> r0
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2015-04-11 01:44:37 +02:00
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2020-02-29 15:58:22 +01:00
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low address
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2015-04-11 01:44:37 +02:00
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The context switch code adopts this standard so that it is easier to follow:
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2020-02-29 15:58:22 +01:00
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- r2 contains _kernel.current ASAP, and the incoming thread when we
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transition from outgoing thread to incoming thread
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2015-04-11 01:44:37 +02:00
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2016-11-08 16:36:50 +01:00
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Not loading _kernel into r0 allows loading _kernel without stomping on
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2019-11-07 21:43:29 +01:00
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the parameter in r0 in arch_switch().
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2015-04-11 01:44:37 +02:00
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2015-08-04 17:27:27 +02:00
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ARCv2 processors have two kinds of interrupts: fast (FIRQ) and regular. The
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official documentation calls the regular interrupts 'IRQs', but the internals
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of the kernel call them 'RIRQs' to differentiate from the 'irq' subsystem,
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which is the interrupt API/layer of abstraction.
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2015-04-11 01:44:37 +02:00
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arc: Support FIRQ handling when CONFIG_RGF_NUM_BANKS==1
For the EM Starterkit, one SOC I will soon be adding is EM7D.
This SOC has FIRQ, but only has one register bank.
Thus the interrupt handling for FIRQ needs to be different
when CONFIG_RGF_NUM_BANKS==1. The handler must instead push
registers onto the stack in the same stack frame layout that RIRQ uses.
This allows for context switch to be easily done since its compatible.
The common interrupt entry point _isr_enter must save r0 before using
it, because in the FIRQ 1-bank case, it would be destroyed otherwise.
So a global variable named saved_r0 has been added for this reason.
The stack cannot be used to save r0, because it first has to determine
whether its FIRQ or RIRQ here. This change has been tested on the
EM Starterkit with EM7D SOC changes -- coming soon. To make the review
easier, these 3 files are submitted first.
Also, exceptions will no longer use the _firq_stack.
This stack is not needed in the 1-bank case, but an exception stack
is needed. I've added a new stack called _exception_stack,
and made it be 512B, which should be enough for one exception.
See ZEP-966
Change-Id: I6f228b840da7c4db440dd1cfef4ae25336c87f0d
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
2016-10-15 18:50:27 +02:00
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For FIRQ, there are two cases, depending upon the value of
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CONFIG_RGF_NUM_BANKS.
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CONFIG_RGF_NUM_BANKS==1 case:
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Scratch registers are pushed onto the current stack just as they are with
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RIRQ. See the above frame layout. Unlike RIRQ, the status32_p0 and ilink
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registers are where status32 and the program counter are located, so these
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need to be pushed.
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CONFIG_RGF_NUM_BANKS!=1 case:
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The FIRQ handler has its own register bank for general purpose registers,
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and thus it doesn't have to save them on a stack. The 'loop' registers
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(lp_count, lp_end, lp_start), however, are not present in the
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second bank. The handler saves these special registers in unused callee saved
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registers (to avoid stack accesses). It is possible to register a FIRQ
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handler that operates outside of the kernel, but care must be taken to only
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use instructions that only use the banked registers.
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2015-04-11 01:44:37 +02:00
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2017-10-29 12:10:22 +01:00
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The kernel is able to handle transitions to and from FIRQ, RIRQ and threads.
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The contexts are saved 'lazily': the minimum amount of work is
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2015-04-11 01:44:37 +02:00
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done upfront, and the rest is done when needed:
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o RIRQ
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2020-02-29 15:58:22 +01:00
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All needed registers to run C code in the ISR are saved automatically
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on the outgoing thread's stack: loop, status32, pc, and the caller-
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saved GPRs. That stack frame layout is pre-determined. If returning
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to a thread, the stack is popped and no registers have to be saved by
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the kernel. If a context switch is required, the callee-saved GPRs
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are then saved in the thread's stack.
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2015-04-11 01:44:37 +02:00
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o FIRQ
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2020-02-29 15:58:22 +01:00
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First, a FIRQ can be interrupting a lower-priority RIRQ: if this is
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the case, the FIRQ does not take a scheduling decision and leaves it
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the RIRQ to handle. This limits the amount of code that has to run at
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interrupt-level.
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CONFIG_RGF_NUM_BANKS==1 case:
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Registers are saved on the stack frame just as they are for RIRQ.
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Context switch can happen just as it does in the RIRQ case, however,
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if the FIRQ interrupted a RIRQ, the FIRQ will return from interrupt
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and let the RIRQ do the context switch. At entry, one register is
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needed in order to have code to save other registers. r0 is saved
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first in the stack and restored later
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CONFIG_RGF_NUM_BANKS!=1 case:
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During early initialization, the sp in the 2nd register bank is made to
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refer to _firq_stack. This allows for the FIRQ handler to use its own
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stack. GPRs are banked, loop registers are saved in unused callee saved
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regs upon interrupt entry. If returning to a thread, loop registers are
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restored and the CPU switches back to bank 0 for the GPRs. If a context
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switch is needed, at this point only are all the registers saved.
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First, a stack frame with the same layout as the automatic RIRQ one is
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created and then the callee-saved GPRs are saved in the stack.
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status32_p0 and ilink are saved in this case, not status32 and pc.
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To create the stack frame, the FIRQ handling code must first go back to
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using bank0 of registers, since that is where the registers containing
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the exiting thread are saved. Care must be taken not to touch any
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register before saving them: the only one usable at that point is the
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stack pointer.
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2015-04-11 01:44:37 +02:00
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o coop
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2020-02-29 15:58:22 +01:00
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When a coop context switch is done, the callee-saved registers are
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saved in the stack. The other GPRs do not need to be saved, since the
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compiler has already placed them on the stack.
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2015-04-11 01:44:37 +02:00
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For restoring the contexts, there are six cases. In all cases, the
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callee-saved registers of the incoming thread have to be restored. Then, there
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are specifics for each case:
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From coop:
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2020-02-29 15:58:22 +01:00
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o to coop
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2015-04-11 01:44:37 +02:00
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2020-02-29 15:58:22 +01:00
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Do a normal function call return.
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2015-04-11 01:44:37 +02:00
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2020-02-29 15:58:22 +01:00
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o to any irq
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2015-04-11 01:44:37 +02:00
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2020-02-29 15:58:22 +01:00
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The incoming interrupted thread has an IRQ stack frame containing the
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caller-saved registers that has to be popped. status32 has to be
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restored, then we jump to the interrupted instruction.
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2015-04-11 01:44:37 +02:00
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From FIRQ:
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2020-02-29 15:58:22 +01:00
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When CONFIG_RGF_NUM_BANKS==1, context switch is done as it is for RIRQ.
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When CONFIG_RGF_NUM_BANKS!=1, the processor is put back to using bank0,
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not bank1 anymore, because it had to save the outgoing context from
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bank0, and now has to load the incoming one into bank0.
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2015-04-11 01:44:37 +02:00
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2020-02-29 15:58:22 +01:00
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o to coop
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2015-04-11 01:44:37 +02:00
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2020-02-29 15:58:22 +01:00
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The address of the returning instruction from arch_switch() is loaded
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in ilink and the saved status32 in status32_p0.
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2015-04-11 01:44:37 +02:00
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2020-02-29 15:58:22 +01:00
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o to any irq
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2015-04-11 01:44:37 +02:00
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2020-02-29 15:58:22 +01:00
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The IRQ has saved the caller-saved registers in a stack frame, which
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must be popped, and status32 and pc loaded in status32_p0 and ilink.
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2015-04-11 01:44:37 +02:00
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From RIRQ:
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2020-02-29 15:58:22 +01:00
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o to coop
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2015-04-11 01:44:37 +02:00
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2020-02-29 15:58:22 +01:00
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The interrupt return mechanism in the processor expects a stack frame,
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but the outgoing context did not create one. A fake one is created
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here, with only the relevant values filled in: pc, status32.
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2015-04-11 01:44:37 +02:00
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2020-02-29 15:58:22 +01:00
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There is a discrepancy between the ABI from the ARCv2 docs,
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including the way the processor pushes GPRs in pairs in the IRQ stack
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frame, and the ABI GCC uses. r13 should be a callee-saved register,
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but GCC treats it as caller-saved. This means that the processor pushes
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it in the stack frame along with r12, but the compiler does not save it
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before entering a function. So, it is saved as part of the callee-saved
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registers, and restored there, but the processor restores it _a second
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time_ when popping the IRQ stack frame. Thus, the correct value must
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also be put in the fake stack frame when returning to a thread that
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context switched out cooperatively.
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2015-04-11 01:44:37 +02:00
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2020-02-29 15:58:22 +01:00
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o to any irq
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2015-04-11 01:44:37 +02:00
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2020-02-29 15:58:22 +01:00
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Both types of IRQs already have an IRQ stack frame: simply return from
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interrupt.
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2015-07-01 23:22:39 +02:00
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*/
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2015-04-11 01:44:37 +02:00
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2017-02-13 18:36:32 +01:00
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SECTION_FUNC(TEXT, _isr_wrapper)
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2020-10-21 09:03:36 +02:00
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#ifdef CONFIG_ARC_FIRQ
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2019-03-07 06:14:15 +01:00
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#if CONFIG_RGF_NUM_BANKS == 1
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2019-07-03 13:46:13 +02:00
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/* free r0 here, use r0 to check whether irq is firq.
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* for rirq, as sp will not change and r0 already saved, this action
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2020-07-06 10:37:07 +02:00
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* in fact is useless
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2019-07-03 13:46:13 +02:00
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* for firq, r0 will be restored later
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*/
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2020-07-06 10:37:07 +02:00
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push r0
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2019-03-07 06:14:15 +01:00
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#endif
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2015-04-11 01:44:37 +02:00
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lr r0, [_ARC_V2_AUX_IRQ_ACT]
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ffs r0, r0
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cmp r0, 0
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arc: Support FIRQ handling when CONFIG_RGF_NUM_BANKS==1
For the EM Starterkit, one SOC I will soon be adding is EM7D.
This SOC has FIRQ, but only has one register bank.
Thus the interrupt handling for FIRQ needs to be different
when CONFIG_RGF_NUM_BANKS==1. The handler must instead push
registers onto the stack in the same stack frame layout that RIRQ uses.
This allows for context switch to be easily done since its compatible.
The common interrupt entry point _isr_enter must save r0 before using
it, because in the FIRQ 1-bank case, it would be destroyed otherwise.
So a global variable named saved_r0 has been added for this reason.
The stack cannot be used to save r0, because it first has to determine
whether its FIRQ or RIRQ here. This change has been tested on the
EM Starterkit with EM7D SOC changes -- coming soon. To make the review
easier, these 3 files are submitted first.
Also, exceptions will no longer use the _firq_stack.
This stack is not needed in the 1-bank case, but an exception stack
is needed. I've added a new stack called _exception_stack,
and made it be 512B, which should be enough for one exception.
See ZEP-966
Change-Id: I6f228b840da7c4db440dd1cfef4ae25336c87f0d
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
2016-10-15 18:50:27 +02:00
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#if CONFIG_RGF_NUM_BANKS == 1
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bnz rirq_path
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2020-07-06 10:37:07 +02:00
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pop r0
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arc: Support FIRQ handling when CONFIG_RGF_NUM_BANKS==1
For the EM Starterkit, one SOC I will soon be adding is EM7D.
This SOC has FIRQ, but only has one register bank.
Thus the interrupt handling for FIRQ needs to be different
when CONFIG_RGF_NUM_BANKS==1. The handler must instead push
registers onto the stack in the same stack frame layout that RIRQ uses.
This allows for context switch to be easily done since its compatible.
The common interrupt entry point _isr_enter must save r0 before using
it, because in the FIRQ 1-bank case, it would be destroyed otherwise.
So a global variable named saved_r0 has been added for this reason.
The stack cannot be used to save r0, because it first has to determine
whether its FIRQ or RIRQ here. This change has been tested on the
EM Starterkit with EM7D SOC changes -- coming soon. To make the review
easier, these 3 files are submitted first.
Also, exceptions will no longer use the _firq_stack.
This stack is not needed in the 1-bank case, but an exception stack
is needed. I've added a new stack called _exception_stack,
and made it be 512B, which should be enough for one exception.
See ZEP-966
Change-Id: I6f228b840da7c4db440dd1cfef4ae25336c87f0d
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
2016-10-15 18:50:27 +02:00
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/* 1-register bank FIRQ handling must save registers on stack */
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2019-03-15 07:24:43 +01:00
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_create_irq_stack_frame
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lr r0, [_ARC_V2_STATUS32_P0]
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st_s r0, [sp, ___isf_t_status32_OFFSET]
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2020-11-23 12:50:07 +01:00
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st ilink, [sp, ___isf_t_pc_OFFSET]
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2019-07-03 13:46:13 +02:00
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2019-08-29 12:52:04 +02:00
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mov_s r3, _firq_exit
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mov_s r2, _firq_enter
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arc: Support FIRQ handling when CONFIG_RGF_NUM_BANKS==1
For the EM Starterkit, one SOC I will soon be adding is EM7D.
This SOC has FIRQ, but only has one register bank.
Thus the interrupt handling for FIRQ needs to be different
when CONFIG_RGF_NUM_BANKS==1. The handler must instead push
registers onto the stack in the same stack frame layout that RIRQ uses.
This allows for context switch to be easily done since its compatible.
The common interrupt entry point _isr_enter must save r0 before using
it, because in the FIRQ 1-bank case, it would be destroyed otherwise.
So a global variable named saved_r0 has been added for this reason.
The stack cannot be used to save r0, because it first has to determine
whether its FIRQ or RIRQ here. This change has been tested on the
EM Starterkit with EM7D SOC changes -- coming soon. To make the review
easier, these 3 files are submitted first.
Also, exceptions will no longer use the _firq_stack.
This stack is not needed in the 1-bank case, but an exception stack
is needed. I've added a new stack called _exception_stack,
and made it be 512B, which should be enough for one exception.
See ZEP-966
Change-Id: I6f228b840da7c4db440dd1cfef4ae25336c87f0d
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
2016-10-15 18:50:27 +02:00
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j_s [r2]
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rirq_path:
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2020-07-06 10:37:07 +02:00
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add sp, sp, 4
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2019-08-29 12:52:04 +02:00
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|
mov_s r3, _rirq_exit
|
|
|
|
mov_s r2, _rirq_enter
|
arc: Support FIRQ handling when CONFIG_RGF_NUM_BANKS==1
For the EM Starterkit, one SOC I will soon be adding is EM7D.
This SOC has FIRQ, but only has one register bank.
Thus the interrupt handling for FIRQ needs to be different
when CONFIG_RGF_NUM_BANKS==1. The handler must instead push
registers onto the stack in the same stack frame layout that RIRQ uses.
This allows for context switch to be easily done since its compatible.
The common interrupt entry point _isr_enter must save r0 before using
it, because in the FIRQ 1-bank case, it would be destroyed otherwise.
So a global variable named saved_r0 has been added for this reason.
The stack cannot be used to save r0, because it first has to determine
whether its FIRQ or RIRQ here. This change has been tested on the
EM Starterkit with EM7D SOC changes -- coming soon. To make the review
easier, these 3 files are submitted first.
Also, exceptions will no longer use the _firq_stack.
This stack is not needed in the 1-bank case, but an exception stack
is needed. I've added a new stack called _exception_stack,
and made it be 512B, which should be enough for one exception.
See ZEP-966
Change-Id: I6f228b840da7c4db440dd1cfef4ae25336c87f0d
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
2016-10-15 18:50:27 +02:00
|
|
|
j_s [r2]
|
|
|
|
#else
|
2015-04-11 01:44:37 +02:00
|
|
|
mov.z r3, _firq_exit
|
|
|
|
mov.z r2, _firq_enter
|
|
|
|
mov.nz r3, _rirq_exit
|
|
|
|
mov.nz r2, _rirq_enter
|
2016-05-25 18:24:55 +02:00
|
|
|
j_s [r2]
|
arc: Support FIRQ handling when CONFIG_RGF_NUM_BANKS==1
For the EM Starterkit, one SOC I will soon be adding is EM7D.
This SOC has FIRQ, but only has one register bank.
Thus the interrupt handling for FIRQ needs to be different
when CONFIG_RGF_NUM_BANKS==1. The handler must instead push
registers onto the stack in the same stack frame layout that RIRQ uses.
This allows for context switch to be easily done since its compatible.
The common interrupt entry point _isr_enter must save r0 before using
it, because in the FIRQ 1-bank case, it would be destroyed otherwise.
So a global variable named saved_r0 has been added for this reason.
The stack cannot be used to save r0, because it first has to determine
whether its FIRQ or RIRQ here. This change has been tested on the
EM Starterkit with EM7D SOC changes -- coming soon. To make the review
easier, these 3 files are submitted first.
Also, exceptions will no longer use the _firq_stack.
This stack is not needed in the 1-bank case, but an exception stack
is needed. I've added a new stack called _exception_stack,
and made it be 512B, which should be enough for one exception.
See ZEP-966
Change-Id: I6f228b840da7c4db440dd1cfef4ae25336c87f0d
Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
2016-10-15 18:50:27 +02:00
|
|
|
#endif
|
2017-11-29 09:55:18 +01:00
|
|
|
#else
|
2021-04-06 14:58:53 +02:00
|
|
|
MOVR r3, _rirq_exit
|
|
|
|
MOVR r2, _rirq_enter
|
2017-11-29 09:55:18 +01:00
|
|
|
j_s [r2]
|
|
|
|
#endif
|
2015-04-11 01:44:37 +02:00
|
|
|
|
2020-10-21 08:59:47 +02:00
|
|
|
/* r0, r1, and r3 will be used in exit_tickless_idle macro */
|
2016-10-12 17:09:58 +02:00
|
|
|
.macro exit_tickless_idle
|
2020-09-02 00:31:40 +02:00
|
|
|
#if defined(CONFIG_PM)
|
2016-10-12 17:09:58 +02:00
|
|
|
clri r0 /* do not interrupt exiting tickless idle operations */
|
2021-04-06 14:58:53 +02:00
|
|
|
MOVR r1, _kernel
|
2020-09-02 03:46:30 +02:00
|
|
|
breq r3, 0, _skip_pm_save_idle_exit
|
2016-10-12 17:09:58 +02:00
|
|
|
|
2016-11-08 16:36:50 +01:00
|
|
|
st 0, [r1, _kernel_offset_to_idle] /* zero idle duration */
|
2021-04-06 14:58:53 +02:00
|
|
|
PUSHR blink
|
2020-09-02 03:46:30 +02:00
|
|
|
jl z_pm_save_idle_exit
|
2021-04-06 14:58:53 +02:00
|
|
|
POPR blink
|
2016-10-12 17:09:58 +02:00
|
|
|
|
2020-09-02 03:46:30 +02:00
|
|
|
_skip_pm_save_idle_exit:
|
2016-10-12 17:09:58 +02:00
|
|
|
seti r0
|
2015-06-10 01:46:29 +02:00
|
|
|
#endif
|
2020-06-30 19:08:26 +02:00
|
|
|
.endm
|
2015-06-10 01:46:29 +02:00
|
|
|
|
2015-04-11 01:44:37 +02:00
|
|
|
/* when getting here, r3 contains the interrupt exit stub to call */
|
|
|
|
SECTION_FUNC(TEXT, _isr_demux)
|
2021-04-06 14:58:53 +02:00
|
|
|
PUSHR r3
|
2019-03-15 04:04:46 +01:00
|
|
|
|
2019-07-30 13:53:30 +02:00
|
|
|
/* according to ARCv2 ISA, r25, r30, r58, r59 are caller-saved
|
|
|
|
* scratch registers, possibly used by interrupt handlers
|
|
|
|
*/
|
2021-04-06 14:58:53 +02:00
|
|
|
PUSHR r25
|
|
|
|
PUSHR r30
|
2019-07-30 13:53:30 +02:00
|
|
|
#ifdef CONFIG_ARC_HAS_ACCL_REGS
|
2021-04-06 14:58:53 +02:00
|
|
|
PUSHR r58
|
2022-08-18 19:06:45 +02:00
|
|
|
#ifndef CONFIG_64BIT
|
2021-04-06 14:58:53 +02:00
|
|
|
PUSHR r59
|
2022-08-18 19:06:45 +02:00
|
|
|
#endif /* !CONFIG_64BIT */
|
2019-07-30 13:53:30 +02:00
|
|
|
#endif
|
|
|
|
|
2021-10-28 21:58:02 +02:00
|
|
|
#ifdef CONFIG_SCHED_THREAD_USAGE
|
|
|
|
bl z_sched_usage_stop
|
|
|
|
#endif
|
|
|
|
|
2020-10-21 09:03:36 +02:00
|
|
|
#ifdef CONFIG_TRACING_ISR
|
2020-02-29 16:07:47 +01:00
|
|
|
bl sys_trace_isr_enter
|
|
|
|
#endif
|
2015-06-10 01:46:29 +02:00
|
|
|
/* cannot be done before this point because we must be able to run C */
|
|
|
|
exit_tickless_idle
|
|
|
|
|
2015-04-11 01:44:37 +02:00
|
|
|
lr r0, [_ARC_V2_ICAUSE]
|
2017-07-11 04:39:54 +02:00
|
|
|
/* handle software triggered interrupt */
|
2019-03-07 06:14:15 +01:00
|
|
|
lr r3, [_ARC_V2_AUX_IRQ_HINT]
|
|
|
|
brne r3, r0, irq_hint_handled
|
|
|
|
sr 0, [_ARC_V2_AUX_IRQ_HINT]
|
2017-07-11 04:39:54 +02:00
|
|
|
irq_hint_handled:
|
|
|
|
|
2015-04-11 01:44:37 +02:00
|
|
|
sub r0, r0, 16
|
|
|
|
|
2021-04-06 14:58:53 +02:00
|
|
|
MOVR r1, _sw_isr_table
|
|
|
|
/* SW ISR table entries are 8-bytes wide for 32bit ISA and
|
|
|
|
* 16-bytes wide for 64bit ISA */
|
|
|
|
ASLR r0, r0, (ARC_REGSHIFT + 1)
|
|
|
|
ADDR r0, r1, r0
|
|
|
|
/* ISR into r1 */
|
|
|
|
LDR r1, r0, ARC_REGSZ
|
2015-04-11 01:44:37 +02:00
|
|
|
jl_s.d [r1]
|
2021-04-06 14:58:53 +02:00
|
|
|
/* delay slot: ISR parameter into r0 */
|
|
|
|
LDR r0, r0
|
2015-04-11 01:44:37 +02:00
|
|
|
|
2020-10-21 09:03:36 +02:00
|
|
|
#ifdef CONFIG_TRACING_ISR
|
2020-02-29 16:07:47 +01:00
|
|
|
bl sys_trace_isr_exit
|
|
|
|
#endif
|
|
|
|
|
2019-07-30 13:53:30 +02:00
|
|
|
#ifdef CONFIG_ARC_HAS_ACCL_REGS
|
2022-08-18 19:06:45 +02:00
|
|
|
#ifndef CONFIG_64BIT
|
2021-04-06 14:58:53 +02:00
|
|
|
POPR r59
|
2022-08-18 19:06:45 +02:00
|
|
|
#endif /* !CONFIG_64BIT */
|
2021-04-06 14:58:53 +02:00
|
|
|
POPR r58
|
2019-07-30 13:53:30 +02:00
|
|
|
#endif
|
|
|
|
|
2021-04-06 14:58:53 +02:00
|
|
|
POPR r30
|
|
|
|
POPR r25
|
2019-07-30 13:53:30 +02:00
|
|
|
|
2015-04-11 01:44:37 +02:00
|
|
|
/* back from ISR, jump to exit stub */
|
2021-04-06 14:58:53 +02:00
|
|
|
POPR r3
|
2016-05-25 18:24:55 +02:00
|
|
|
j_s [r3]
|
2019-08-29 12:52:04 +02:00
|
|
|
nop_s
|