2016-11-04 22:48:23 +01:00
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/* cache.c - d-cache support for ARC CPUs */
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/*
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* Copyright (c) 2016 Synopsys, Inc. All rights reserved.
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*
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2017-01-19 02:01:01 +01:00
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* SPDX-License-Identifier: Apache-2.0
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2016-11-04 22:48:23 +01:00
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*/
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/**
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* @file
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* @brief d-cache manipulation
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*
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* This module contains functions for manipulation of the d-cache.
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*/
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2022-05-06 10:49:15 +02:00
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#include <zephyr/kernel.h>
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#include <zephyr/arch/cpu.h>
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#include <zephyr/sys/util.h>
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#include <zephyr/toolchain.h>
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#include <zephyr/cache.h>
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#include <zephyr/linker/linker-defs.h>
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#include <zephyr/arch/arc/v2/aux_regs.h>
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2018-01-31 05:41:47 +01:00
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#include <kernel_internal.h>
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2022-05-06 10:49:15 +02:00
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#include <zephyr/sys/__assert.h>
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#include <zephyr/init.h>
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2018-12-16 21:20:40 +01:00
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#include <stdbool.h>
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2016-11-04 22:48:23 +01:00
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2020-12-02 15:44:49 +01:00
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#if defined(CONFIG_DCACHE_LINE_SIZE_DETECT)
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size_t sys_cache_line_size;
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2016-11-04 22:48:23 +01:00
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#endif
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#define DC_CTRL_DC_ENABLE 0x0 /* enable d-cache */
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#define DC_CTRL_DC_DISABLE 0x1 /* disable d-cache */
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#define DC_CTRL_INVALID_ONLY 0x0 /* invalid d-cache only */
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#define DC_CTRL_INVALID_FLUSH 0x40 /* invalid and flush d-cache */
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#define DC_CTRL_ENABLE_FLUSH_LOCKED 0x80 /* locked d-cache can be flushed */
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#define DC_CTRL_DISABLE_FLUSH_LOCKED 0x0 /* locked d-cache cannot be flushed */
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#define DC_CTRL_FLUSH_STATUS 0x100/* flush status */
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#define DC_CTRL_DIRECT_ACCESS 0x0 /* direct access mode */
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#define DC_CTRL_INDIRECT_ACCESS 0x20 /* indirect access mode */
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#define DC_CTRL_OP_SUCCEEDED 0x4 /* d-cache operation succeeded */
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2018-12-16 21:20:40 +01:00
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static bool dcache_available(void)
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2016-11-04 22:48:23 +01:00
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{
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2019-03-08 22:19:05 +01:00
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unsigned long val = z_arc_v2_aux_reg_read(_ARC_V2_D_CACHE_BUILD);
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2016-11-04 22:48:23 +01:00
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val &= 0xff; /* extract version */
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2018-12-16 21:20:40 +01:00
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return (val == 0) ? false : true;
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2016-11-04 22:48:23 +01:00
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}
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2020-05-27 18:26:57 +02:00
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static void dcache_dc_ctrl(uint32_t dcache_en_mask)
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2016-11-04 22:48:23 +01:00
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{
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2018-11-29 22:16:34 +01:00
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if (dcache_available()) {
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2019-03-08 22:19:05 +01:00
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z_arc_v2_aux_reg_write(_ARC_V2_DC_CTRL, dcache_en_mask);
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2018-11-29 22:16:34 +01:00
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}
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2016-11-04 22:48:23 +01:00
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}
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2020-12-02 15:44:49 +01:00
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void arch_dcache_enable(void)
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2016-11-04 22:48:23 +01:00
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{
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dcache_dc_ctrl(DC_CTRL_DC_ENABLE);
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}
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2022-10-05 10:13:49 +02:00
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void arch_dcache_disable(void)
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{
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/* nothing */
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}
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int arch_dcache_flush_range(void *start_addr_ptr, size_t size)
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2016-11-04 22:48:23 +01:00
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{
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2021-05-04 16:26:10 +02:00
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size_t line_size = sys_cache_data_line_size_get();
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2020-04-28 22:14:54 +02:00
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uintptr_t start_addr = (uintptr_t)start_addr_ptr;
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uintptr_t end_addr;
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2016-11-04 22:48:23 +01:00
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unsigned int key;
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2020-12-02 15:44:49 +01:00
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if (!dcache_available() || (size == 0U) || line_size == 0U) {
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2022-10-05 10:13:49 +02:00
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return -ENOTSUP;
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2016-11-04 22:48:23 +01:00
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}
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2020-04-28 22:14:54 +02:00
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end_addr = start_addr + size;
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2020-12-02 15:44:49 +01:00
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start_addr = ROUND_DOWN(start_addr, line_size);
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2016-11-04 22:48:23 +01:00
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2020-04-06 12:30:36 +02:00
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key = arch_irq_lock(); /* --enter critical section-- */
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2016-11-04 22:48:23 +01:00
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do {
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2019-03-08 22:19:05 +01:00
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z_arc_v2_aux_reg_write(_ARC_V2_DC_FLDL, start_addr);
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2020-07-20 17:14:58 +02:00
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__builtin_arc_nop();
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__builtin_arc_nop();
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__builtin_arc_nop();
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2016-11-04 22:48:23 +01:00
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/* wait for flush completion */
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do {
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2019-03-08 22:19:05 +01:00
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if ((z_arc_v2_aux_reg_read(_ARC_V2_DC_CTRL) &
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2018-11-29 22:16:34 +01:00
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DC_CTRL_FLUSH_STATUS) == 0) {
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2016-11-04 22:48:23 +01:00
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break;
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2018-11-29 22:16:34 +01:00
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}
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2016-11-04 22:48:23 +01:00
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} while (1);
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2020-12-02 15:44:49 +01:00
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start_addr += line_size;
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2020-04-28 22:14:54 +02:00
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} while (start_addr < end_addr);
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2016-11-04 22:48:23 +01:00
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2020-04-06 12:30:36 +02:00
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arch_irq_unlock(key); /* --exit critical section-- */
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2016-11-04 22:48:23 +01:00
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2022-10-05 10:13:49 +02:00
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return 0;
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2016-11-04 22:48:23 +01:00
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}
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2022-10-05 10:13:49 +02:00
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int arch_dcache_invd_range(void *start_addr_ptr, size_t size)
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2020-04-28 22:14:54 +02:00
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{
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2021-05-04 16:26:10 +02:00
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size_t line_size = sys_cache_data_line_size_get();
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2020-04-28 22:14:54 +02:00
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uintptr_t start_addr = (uintptr_t)start_addr_ptr;
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uintptr_t end_addr;
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unsigned int key;
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2016-11-04 22:48:23 +01:00
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2020-12-02 15:44:49 +01:00
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if (!dcache_available() || (size == 0U) || line_size == 0U) {
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2022-10-05 10:13:49 +02:00
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return -ENOTSUP;
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2020-04-28 22:14:54 +02:00
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}
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end_addr = start_addr + size;
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2020-12-02 15:44:49 +01:00
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start_addr = ROUND_DOWN(start_addr, line_size);
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2016-11-04 22:48:23 +01:00
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2020-04-28 22:14:54 +02:00
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key = arch_irq_lock(); /* -enter critical section- */
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2016-11-04 22:48:23 +01:00
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2020-04-28 22:14:54 +02:00
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do {
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z_arc_v2_aux_reg_write(_ARC_V2_DC_IVDL, start_addr);
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2020-07-20 17:14:58 +02:00
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__builtin_arc_nop();
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__builtin_arc_nop();
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__builtin_arc_nop();
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2020-12-02 15:44:49 +01:00
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start_addr += line_size;
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2020-04-28 22:14:54 +02:00
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} while (start_addr < end_addr);
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irq_unlock(key); /* -exit critical section- */
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2022-10-05 10:13:49 +02:00
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return 0;
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2020-04-28 22:14:54 +02:00
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}
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2016-11-04 22:48:23 +01:00
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2022-10-05 10:13:49 +02:00
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int arch_dcache_flush_and_invd_range(void *start_addr_ptr, size_t size)
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2020-12-02 15:44:49 +01:00
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{
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2022-10-05 10:13:49 +02:00
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return -ENOTSUP;
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2020-12-02 15:44:49 +01:00
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}
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2022-10-05 10:13:49 +02:00
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int arch_dcache_flush_all(void)
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2022-08-22 12:06:25 +02:00
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{
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return -ENOTSUP;
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}
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2022-10-05 10:13:49 +02:00
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int arch_dcache_invd_all(void)
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2022-08-22 12:06:25 +02:00
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{
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return -ENOTSUP;
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}
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2022-10-05 10:13:49 +02:00
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int arch_dcache_flush_and_invd_all(void)
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2022-08-22 12:06:25 +02:00
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{
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return -ENOTSUP;
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}
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2020-12-02 15:44:49 +01:00
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#if defined(CONFIG_DCACHE_LINE_SIZE_DETECT)
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2016-11-04 22:48:23 +01:00
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static void init_dcache_line_size(void)
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{
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2020-05-27 18:26:57 +02:00
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uint32_t val;
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2016-11-04 22:48:23 +01:00
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2019-03-08 22:19:05 +01:00
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val = z_arc_v2_aux_reg_read(_ARC_V2_D_CACHE_BUILD);
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2019-03-27 02:57:45 +01:00
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__ASSERT((val&0xff) != 0U, "d-cache is not present");
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2016-11-04 22:48:23 +01:00
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val = ((val>>16) & 0xf) + 1;
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2019-03-27 02:57:45 +01:00
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val *= 16U;
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2016-11-04 22:48:23 +01:00
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sys_cache_line_size = (size_t) val;
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}
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2020-12-02 15:44:49 +01:00
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size_t arch_dcache_line_size_get(void)
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2020-04-28 22:14:54 +02:00
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{
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return sys_cache_line_size;
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}
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2020-12-02 15:44:49 +01:00
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#endif
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2020-04-28 22:14:54 +02:00
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2022-10-05 10:13:49 +02:00
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void arch_icache_enable(void)
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{
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/* nothing */
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}
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void arch_icache_disable(void)
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{
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/* nothing */
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}
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int arch_icache_flush_all(void)
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{
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return -ENOTSUP;
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}
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int arch_icache_invd_all(void)
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{
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return -ENOTSUP;
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}
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int arch_icache_flush_and_invd_all(void)
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{
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return -ENOTSUP;
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}
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int arch_icache_flush_range(void *addr, size_t size)
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{
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ARG_UNUSED(addr);
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ARG_UNUSED(size);
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return -ENOTSUP;
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}
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int arch_icache_invd_range(void *addr, size_t size)
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{
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ARG_UNUSED(addr);
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ARG_UNUSED(size);
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return -ENOTSUP;
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}
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int arch_icache_flush_and_invd_range(void *addr, size_t size)
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{
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ARG_UNUSED(addr);
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ARG_UNUSED(size);
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return -ENOTSUP;
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}
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init: remove the need for a dummy device pointer in SYS_INIT functions
The init infrastructure, found in `init.h`, is currently used by:
- `SYS_INIT`: to call functions before `main`
- `DEVICE_*`: to initialize devices
They are all sorted according to an initialization level + a priority.
`SYS_INIT` calls are really orthogonal to devices, however, the required
function signature requires a `const struct device *dev` as a first
argument. The only reason for that is because the same init machinery is
used by devices, so we have something like:
```c
struct init_entry {
int (*init)(const struct device *dev);
/* only set by DEVICE_*, otherwise NULL */
const struct device *dev;
}
```
As a result, we end up with such weird/ugly pattern:
```c
static int my_init(const struct device *dev)
{
/* always NULL! add ARG_UNUSED to avoid compiler warning */
ARG_UNUSED(dev);
...
}
```
This is really a result of poor internals isolation. This patch proposes
a to make init entries more flexible so that they can accept sytem
initialization calls like this:
```c
static int my_init(void)
{
...
}
```
This is achieved using a union:
```c
union init_function {
/* for SYS_INIT, used when init_entry.dev == NULL */
int (*sys)(void);
/* for DEVICE*, used when init_entry.dev != NULL */
int (*dev)(const struct device *dev);
};
struct init_entry {
/* stores init function (either for SYS_INIT or DEVICE*)
union init_function init_fn;
/* stores device pointer for DEVICE*, NULL for SYS_INIT. Allows
* to know which union entry to call.
*/
const struct device *dev;
}
```
This solution **does not increase ROM usage**, and allows to offer clean
public APIs for both SYS_INIT and DEVICE*. Note that however, init
machinery keeps a coupling with devices.
**NOTE**: This is a breaking change! All `SYS_INIT` functions will need
to be converted to the new signature. See the script offered in the
following commit.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
init: convert SYS_INIT functions to the new signature
Conversion scripted using scripts/utils/migrate_sys_init.py.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
manifest: update projects for SYS_INIT changes
Update modules with updated SYS_INIT calls:
- hal_ti
- lvgl
- sof
- TraceRecorderSource
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
tests: devicetree: devices: adjust test
Adjust test according to the recently introduced SYS_INIT
infrastructure.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
tests: kernel: threads: adjust SYS_INIT call
Adjust to the new signature: int (*init_fn)(void);
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-10-19 09:33:44 +02:00
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static int init_dcache(void)
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2016-11-04 22:48:23 +01:00
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{
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2023-12-18 10:49:10 +01:00
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sys_cache_data_enable();
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2016-11-04 22:48:23 +01:00
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2020-12-02 15:44:49 +01:00
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#if defined(CONFIG_DCACHE_LINE_SIZE_DETECT)
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2016-11-04 22:48:23 +01:00
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init_dcache_line_size();
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#endif
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return 0;
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}
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2016-11-08 20:06:55 +01:00
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SYS_INIT(init_dcache, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
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