f623571a73
Set TP in exception context so that it gets loaded into the CPU when first running the thread. Set TP for secondary cores to related idle TLS area. Signed-off-by: Keith Packard <keithp@keithp.com>
100 lines
2 KiB
C
100 lines
2 KiB
C
/*
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* Copyright (c) 2021 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <init.h>
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#include <kernel.h>
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#include <ksched.h>
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volatile struct {
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arch_cpustart_t fn;
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void *arg;
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} riscv_cpu_init[CONFIG_MP_NUM_CPUS];
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volatile uintptr_t riscv_cpu_wake_flag;
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volatile void *riscv_cpu_sp;
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void arch_start_cpu(int cpu_num, k_thread_stack_t *stack, int sz,
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arch_cpustart_t fn, void *arg)
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{
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riscv_cpu_init[cpu_num].fn = fn;
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riscv_cpu_init[cpu_num].arg = arg;
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riscv_cpu_sp = Z_THREAD_STACK_BUFFER(stack) + sz;
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riscv_cpu_wake_flag = cpu_num;
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while (riscv_cpu_wake_flag != 0U) {
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;
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}
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}
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void z_riscv_secondary_cpu_init(int cpu_num)
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{
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#if defined(CONFIG_RISCV_SOC_INTERRUPT_INIT)
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soc_interrupt_init();
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#endif
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#ifdef CONFIG_PMP_STACK_GUARD
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z_riscv_configure_interrupt_stack_guard();
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#endif
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#ifdef CONFIG_SMP
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irq_enable(RISCV_MACHINE_SOFT_IRQ);
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#endif
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#ifdef CONFIG_THREAD_LOCAL_STORAGE
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__asm__("mv tp, %0" : : "r" (z_idle_threads[cpu_num].tls));
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#endif
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riscv_cpu_init[cpu_num].fn(riscv_cpu_init[cpu_num].arg);
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}
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#ifdef CONFIG_SMP
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static uintptr_t *get_hart_msip(int hart_id)
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{
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#ifdef CONFIG_64BIT
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return (uintptr_t *)(uint64_t)(RISCV_MSIP_BASE + (hart_id * 4));
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#else
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return (uintptr_t *)(RISCV_MSIP_BASE + (hart_id * 4));
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#endif
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}
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void arch_sched_ipi(void)
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{
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unsigned int key;
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uint32_t i;
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uint8_t id;
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key = arch_irq_lock();
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id = _current_cpu->id;
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for (i = 0U; i < CONFIG_MP_NUM_CPUS; i++) {
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if (i != id) {
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volatile uint32_t *r = (uint32_t *)get_hart_msip(i);
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*r = 1U;
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}
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}
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arch_irq_unlock(key);
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}
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static void sched_ipi_handler(const void *unused)
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{
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ARG_UNUSED(unused);
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volatile uint32_t *r = (uint32_t *)get_hart_msip(_current_cpu->id);
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*r = 0U;
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z_sched_ipi();
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}
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static int riscv_smp_init(const struct device *dev)
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{
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ARG_UNUSED(dev);
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IRQ_CONNECT(RISCV_MACHINE_SOFT_IRQ, 0, sched_ipi_handler, NULL, 0);
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irq_enable(RISCV_MACHINE_SOFT_IRQ);
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return 0;
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}
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SYS_INIT(riscv_smp_init, PRE_KERNEL_2, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
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#endif /* CONFIG_SMP */
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