Keith Packard f623571a73 riscv: Initialize TP register when starting threads ... Set TP in exception context so that it gets loaded into the CPU when first running the thread. Set TP for secondary cores to related idle TLS area. Signed-off-by: Keith Packard <keithp@keithp.com>		2022-04-28 11:09:01 +09:00
..
offsets	riscv: Initialize TP register when starting threads	2022-04-28 11:09:01 +09:00
pmp	riscv: make arch_is_user_context() SMP compatible	2022-03-21 07:28:05 -04:00
asm_macros.inc	riscv: isr.S: compute _current_cpu using CPU number on SMP	2022-03-21 07:28:05 -04:00
CMakeLists.txt	arch: common: semihost: add semihosting operations	2022-04-21 13:04:52 +02:00
coredump.c	riscv: move the tp register from caller-saved to callee-saved	2022-03-21 07:28:05 -04:00
cpu_idle.c	riscv: use standard MSTATUS	2020-01-06 13:27:45 -05:00
fatal.c	riscv: Initialize TP register when starting threads	2022-04-28 11:09:01 +09:00
irq_manage.c	kernel: Cleanup logger setup in kernel files	2020-11-27 09:56:34 -05:00
irq_offload.c	riscv: irq_offload: simpler implementation	2022-03-21 07:28:05 -04:00
isr.S	riscv: Initialize TP register when starting threads	2022-04-28 11:09:01 +09:00
prep_c.c	core: z_data_copy does not depend on CONFIG_XIP	2022-02-22 10:22:53 +01:00
reboot.c	riscv: remove @return doc for void functions	2022-01-12 16:02:16 -05:00
reset.S	riscv: exception code mega simplification and optimization	2022-03-21 07:28:05 -04:00
semihost.c	semihosting: fix inline assembly output dependency	2022-04-24 19:46:15 +02:00
smp.c	riscv: Initialize TP register when starting threads	2022-04-28 11:09:01 +09:00
switch.S	riscv: implement arch_switch()	2022-03-21 07:28:05 -04:00
thread.c	riscv: Initialize TP register when starting threads	2022-04-28 11:09:01 +09:00
tls.c	riscv: add support for thread local storage	2020-10-24 10:52:00 -07:00
userspace.S	riscv: exception code mega simplification and optimization	2022-03-21 07:28:05 -04:00