Jim Shu d7b53226d1 soc: riscv: andes_v5: initial support of Andes L2 cache controller ... This initial support of L2C driver only contains cache enable and HW capability checking. Cache management operation isn't supported yet in this driver. Signed-off-by: Jim Shu <cwshu@andestech.com>		2021-08-30 13:40:14 -04:00
..
arc	boards: arc: add a nsim_hs_mpuv6 board simulator	2021-08-27 11:45:43 -04:00
arm	cmake: linker: arm: adding Zephyr CMake linker files for arm arch	2021-08-30 08:54:23 -04:00
arm64	linker: align _image_text_start/end/size linker symbols name	2021-08-28 08:48:03 -04:00
nios2	soc: nios2: Cleanup linker scripts to use new DTS macros	2020-04-30 20:59:13 -05:00
posix	posix: Add missing include	2021-04-27 13:17:36 -04:00
riscv	soc: riscv: andes_v5: initial support of Andes L2 cache controller	2021-08-30 13:40:14 -04:00
sparc	boards: set CPU_HAS_FPU on LEON3 soc and boards	2020-12-04 14:33:43 +02:00
x86	bluetooth: remove Kconfig options CONFIG_BT_*_ON_DEV_NAME	2021-08-25 18:05:17 -04:00
xtensa	arch: xtensa: modify asm for interrupt sections	2021-08-28 23:27:02 -04:00
Kconfig	kconfig: soc and shield cleanup	2021-06-11 16:13:22 +02:00