d267ad1b22
Convert older DT_INST_ macro use the new include/devicetree.h DT_INST macro APIs. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
290 lines
11 KiB
C
290 lines
11 KiB
C
/*
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* Copyright (c) 2019 Vestas Wind Systems A/S
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*
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* Based on NXP k6x soc.c, which is:
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* Copyright (c) 2014-2015 Wind River Systems, Inc.
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* Copyright (c) 2016, Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <kernel.h>
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#include <device.h>
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#include <init.h>
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#include <fsl_clock.h>
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#include <fsl_cache.h>
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#include <arch/arm/aarch32/cortex_m/cmsis.h>
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#define ASSERT_WITHIN_RANGE(val, min, max, str) \
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BUILD_ASSERT_MSG(val >= min && val <= max, str)
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#define ASSERT_ASYNC_CLK_DIV_VALID(val, str) \
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BUILD_ASSERT_MSG(val == 0 || val == 1 || val == 2 || val == 4 || \
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val == 8 || val == 16 || val == 2 || val == 64, str)
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#define TO_SYS_CLK_DIV(val) _DO_CONCAT(kSCG_SysClkDivBy, val)
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#define kSCG_AsyncClkDivBy0 kSCG_AsyncClkDisable
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#define TO_ASYNC_CLK_DIV(val) _DO_CONCAT(kSCG_AsyncClkDivBy, val)
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/* System Clock configuration */
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ASSERT_WITHIN_RANGE(DT_PROP(DT_INST(0, nxp_kinetis_scg), clk_divider_slow), 2, 8,
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"Invalid SCG slow clock divider value");
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ASSERT_WITHIN_RANGE(DT_PROP(DT_INST(0, nxp_kinetis_scg), clk_divider_bus), 1, 16,
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"Invalid SCG bus clock divider value");
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#if DT_PROP(DT_INST(0, nxp_kinetis_scg), clk_source) == KINETIS_SCG_SCLK_SRC_SPLL
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/* Core divider range is 1 to 4 with SPLL as clock source */
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ASSERT_WITHIN_RANGE(DT_PROP(DT_INST(0, nxp_kinetis_scg), clk_divider_core), 1, 4,
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"Invalid SCG core clock divider value");
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#else
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ASSERT_WITHIN_RANGE(DT_PROP(DT_INST(0, nxp_kinetis_scg), clk_divider_core), 1, 16,
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"Invalid SCG core clock divider value");
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#endif
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static const scg_sys_clk_config_t scg_sys_clk_config = {
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.divSlow = TO_SYS_CLK_DIV(DT_PROP(DT_INST(0, nxp_kinetis_scg), clk_divider_slow)),
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.divBus = TO_SYS_CLK_DIV(DT_PROP(DT_INST(0, nxp_kinetis_scg), clk_divider_bus)),
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.divCore = TO_SYS_CLK_DIV(DT_PROP(DT_INST(0, nxp_kinetis_scg), clk_divider_core)),
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.src = DT_PROP(DT_INST(0, nxp_kinetis_scg), clk_source)
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};
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#if DT_NODE_HAS_PROP(DT_INST(0, nxp_kinetis_scg), sosc_freq)
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/* System Oscillator (SOSC) configuration */
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ASSERT_ASYNC_CLK_DIV_VALID(DT_PROP(DT_INST(0, nxp_kinetis_scg), sosc_divider_1),
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"Invalid SCG SOSC divider 1 value");
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ASSERT_ASYNC_CLK_DIV_VALID(DT_PROP(DT_INST(0, nxp_kinetis_scg), sosc_divider_2),
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"Invalid SCG SOSC divider 2 value");
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static const scg_sosc_config_t scg_sosc_config = {
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.freq = DT_PROP(DT_INST(0, nxp_kinetis_scg), sosc_freq),
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.monitorMode = kSCG_SysOscMonitorDisable,
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.enableMode = kSCG_SysOscEnable | kSCG_SysOscEnableInLowPower,
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.div1 = TO_ASYNC_CLK_DIV(DT_PROP(DT_INST(0, nxp_kinetis_scg), sosc_divider_1)),
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.div2 = TO_ASYNC_CLK_DIV(DT_PROP(DT_INST(0, nxp_kinetis_scg), sosc_divider_2)),
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.workMode = DT_PROP(DT_INST(0, nxp_kinetis_scg), sosc_mode)
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};
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#endif /* DT_NODE_HAS_PROP(DT_INST(0, nxp_kinetis_scg), sosc_freq) */
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/* Slow Internal Reference Clock (SIRC) configuration */
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ASSERT_ASYNC_CLK_DIV_VALID(DT_PROP(DT_INST(0, nxp_kinetis_scg), sirc_divider_1),
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"Invalid SCG SIRC divider 1 value");
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ASSERT_ASYNC_CLK_DIV_VALID(DT_PROP(DT_INST(0, nxp_kinetis_scg), sirc_divider_2),
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"Invalid SCG SIRC divider 2 value");
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static const scg_sirc_config_t scg_sirc_config = {
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.enableMode = kSCG_SircEnable,
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.div1 = TO_ASYNC_CLK_DIV(DT_PROP(DT_INST(0, nxp_kinetis_scg), sirc_divider_1)),
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.div2 = TO_ASYNC_CLK_DIV(DT_PROP(DT_INST(0, nxp_kinetis_scg), sirc_divider_2)),
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#if MHZ(2) == DT_PROP(DT_INST(0, nxp_kinetis_scg), sirc_range)
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.range = kSCG_SircRangeLow
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#elif MHZ(8) == DT_PROP(DT_INST(0, nxp_kinetis_scg), sirc_range)
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.range = kSCG_SircRangeHigh
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#else
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#error Invalid SCG SIRC range
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#endif
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};
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/* Fast Internal Reference Clock (FIRC) configuration */
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ASSERT_ASYNC_CLK_DIV_VALID(DT_PROP(DT_INST(0, nxp_kinetis_scg), firc_divider_1),
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"Invalid SCG FIRC divider 1 value");
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ASSERT_ASYNC_CLK_DIV_VALID(DT_PROP(DT_INST(0, nxp_kinetis_scg), firc_divider_2),
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"Invalid SCG FIRC divider 2 value");
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static const scg_firc_config_t scg_firc_config = {
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.enableMode = kSCG_FircEnable,
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.div1 = TO_ASYNC_CLK_DIV(DT_PROP(DT_INST(0, nxp_kinetis_scg), firc_divider_1)),
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.div2 = TO_ASYNC_CLK_DIV(DT_PROP(DT_INST(0, nxp_kinetis_scg), firc_divider_2)),
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#if MHZ(48) == DT_PROP(DT_INST(0, nxp_kinetis_scg), firc_range)
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.range = kSCG_FircRange48M,
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#elif MHZ(52) == DT_PROP(DT_INST(0, nxp_kinetis_scg), firc_range)
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.range = kSCG_FircRange52M,
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#elif MHZ(56) == DT_PROP(DT_INST(0, nxp_kinetis_scg), firc_range)
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.range = kSCG_FircRange56M,
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#elif MHZ(60) == DT_PROP(DT_INST(0, nxp_kinetis_scg), firc_range)
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.range = kSCG_FircRange60M,
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#else
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#error Invalid SCG FIRC range
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#endif
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.trimConfig = NULL
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};
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/* System Phase-Locked Loop (SPLL) configuration */
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ASSERT_ASYNC_CLK_DIV_VALID(DT_PROP(DT_INST(0, nxp_kinetis_scg), spll_divider_1),
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"Invalid SCG SPLL divider 1 value");
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ASSERT_ASYNC_CLK_DIV_VALID(DT_PROP(DT_INST(0, nxp_kinetis_scg), spll_divider_2),
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"Invalid SCG SPLL divider 2 value");
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ASSERT_WITHIN_RANGE(DT_PROP(DT_INST(0, nxp_kinetis_scg), spll_divider_pre), 1, 8,
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"Invalid SCG SPLL pre divider value");
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ASSERT_WITHIN_RANGE(DT_PROP(DT_INST(0, nxp_kinetis_scg), spll_multiplier), 16, 47,
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"Invalid SCG SPLL multiplier value");
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static const scg_spll_config_t scg_spll_config = {
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.enableMode = kSCG_SysPllEnable,
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.monitorMode = kSCG_SysPllMonitorDisable,
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.div1 = TO_ASYNC_CLK_DIV(DT_PROP(DT_INST(0, nxp_kinetis_scg), spll_divider_1)),
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.div2 = TO_ASYNC_CLK_DIV(DT_PROP(DT_INST(0, nxp_kinetis_scg), spll_divider_2)),
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#if DT_PROP(DT_INST(0, nxp_kinetis_scg), spll_source) == KINETIS_SCG_SPLL_SRC_SOSC
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.src = kSCG_SysPllSrcSysOsc,
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#elif DT_PROP(DT_INST(0, nxp_kinetis_scg), spll_source) == KINETIS_SCG_SPLL_SRC_FIRC
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.src = kSCG_SysPllSrcFirc,
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#else
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#error Invalid SCG SPLL source
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#endif
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.prediv = (DT_PROP(DT_INST(0, nxp_kinetis_scg), spll_divider_pre) - 1U),
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.mult = (DT_PROP(DT_INST(0, nxp_kinetis_scg), spll_multiplier) - 16U)
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};
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static ALWAYS_INLINE void clk_init(void)
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{
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const scg_sys_clk_config_t scg_sys_clk_config_safe = {
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.divSlow = kSCG_SysClkDivBy4,
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.divBus = kSCG_SysClkDivBy1,
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.divCore = kSCG_SysClkDivBy1,
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.src = kSCG_SysClkSrcSirc
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};
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scg_sys_clk_config_t current;
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#if DT_NODE_HAS_PROP(DT_INST(0, nxp_kinetis_scg), sosc_freq)
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/* Optionally initialize system oscillator */
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CLOCK_InitSysOsc(&scg_sosc_config);
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CLOCK_SetXtal0Freq(scg_sosc_config.freq);
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#endif
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/* Configure SIRC */
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CLOCK_InitSirc(&scg_sirc_config);
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/* Temporary switch to safe SIRC in order to configure FIRC */
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CLOCK_SetRunModeSysClkConfig(&scg_sys_clk_config_safe);
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do {
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CLOCK_GetCurSysClkConfig(¤t);
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} while (current.src != scg_sys_clk_config_safe.src);
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CLOCK_InitFirc(&scg_firc_config);
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/* Configure System PLL */
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CLOCK_InitSysPll(&scg_spll_config);
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/* Only RUN mode supported for now */
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CLOCK_SetRunModeSysClkConfig(&scg_sys_clk_config);
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do {
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CLOCK_GetCurSysClkConfig(¤t);
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} while (current.src != scg_sys_clk_config.src);
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#ifdef DT_NXP_KINETIS_LPUART_UART_0_CLOCK_IP_SOURCE
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CLOCK_SetIpSrc(kCLOCK_Lpuart0,
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DT_NXP_KINETIS_LPUART_UART_0_CLOCK_IP_SOURCE);
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#endif
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#ifdef DT_NXP_KINETIS_LPUART_UART_1_CLOCK_IP_SOURCE
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CLOCK_SetIpSrc(kCLOCK_Lpuart1,
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DT_NXP_KINETIS_LPUART_UART_1_CLOCK_IP_SOURCE);
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#endif
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#ifdef DT_NXP_KINETIS_LPUART_UART_2_CLOCK_IP_SOURCE
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CLOCK_SetIpSrc(kCLOCK_Lpuart2,
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DT_NXP_KINETIS_LPUART_UART_2_CLOCK_IP_SOURCE);
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#endif
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#ifdef DT_NXP_IMX_LPI2C_I2C_0_CLOCK_IP_SOURCE
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CLOCK_SetIpSrc(kCLOCK_Lpi2c0, DT_NXP_IMX_LPI2C_I2C_0_CLOCK_IP_SOURCE);
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#endif
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#ifdef DT_NXP_IMX_LPI2C_I2C_1_CLOCK_IP_SOURCE
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CLOCK_SetIpSrc(kCLOCK_Lpi2c1, DT_NXP_IMX_LPI2C_I2C_1_CLOCK_IP_SOURCE);
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#endif
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#ifdef DT_NXP_IMX_LPSPI_SPI_0_CLOCK_IP_SOURCE
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CLOCK_SetIpSrc(kCLOCK_Lpspi0, DT_NXP_IMX_LPSPI_SPI_0_CLOCK_IP_SOURCE);
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#endif
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#ifdef DT_NXP_IMX_LPSPI_SPI_1_CLOCK_IP_SOURCE
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CLOCK_SetIpSrc(kCLOCK_Lpspi1, DT_NXP_IMX_LPSPI_SPI_1_CLOCK_IP_SOURCE);
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#endif
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#ifdef DT_NXP_KINETIS_ADC12_ADC_0_CLOCK_IP_SOURCE
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CLOCK_SetIpSrc(kCLOCK_Adc0, DT_NXP_KINETIS_ADC12_ADC_0_CLOCK_IP_SOURCE);
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#endif
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#ifdef DT_NXP_KINETIS_ADC12_ADC_1_CLOCK_IP_SOURCE
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CLOCK_SetIpSrc(kCLOCK_Adc1, DT_NXP_KINETIS_ADC12_ADC_1_CLOCK_IP_SOURCE);
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#endif
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#ifdef DT_NXP_KINETIS_ADC12_ADC_2_CLOCK_IP_SOURCE
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CLOCK_SetIpSrc(kCLOCK_Adc2, DT_NXP_KINETIS_ADC12_ADC_2_CLOCK_IP_SOURCE);
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#endif
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#ifdef DT_NXP_KINETIS_FTM_PWM_0_CLOCK_IP_SOURCE
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CLOCK_SetIpSrc(kCLOCK_Ftm0, DT_NXP_KINETIS_FTM_PWM_0_CLOCK_IP_SOURCE);
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#endif
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#ifdef DT_NXP_KINETIS_FTM_PWM_1_CLOCK_IP_SOURCE
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CLOCK_SetIpSrc(kCLOCK_Ftm1, DT_NXP_KINETIS_FTM_PWM_1_CLOCK_IP_SOURCE);
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#endif
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#ifdef DT_NXP_KINETIS_FTM_PWM_2_CLOCK_IP_SOURCE
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CLOCK_SetIpSrc(kCLOCK_Ftm2, DT_NXP_KINETIS_FTM_PWM_2_CLOCK_IP_SOURCE);
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#endif
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#ifdef DT_NXP_KINETIS_FTM_PWM_3_CLOCK_IP_SOURCE
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CLOCK_SetIpSrc(kCLOCK_Ftm3, DT_NXP_KINETIS_FTM_PWM_3_CLOCK_IP_SOURCE);
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#endif
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}
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static int ke1xf_init(struct device *arg)
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{
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ARG_UNUSED(arg);
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unsigned int old_level; /* old interrupt lock level */
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#if !defined(CONFIG_ARM_MPU)
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u32_t temp_reg;
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#endif /* !CONFIG_ARM_MPU */
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/* Disable interrupts */
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old_level = irq_lock();
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#if !defined(CONFIG_ARM_MPU)
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/*
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* Disable memory protection and clear slave port errors.
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* Note that the KE1xF does not implement the optional ARMv7-M memory
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* protection unit (MPU), specified by the architecture (PMSAv7), in the
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* Cortex-M4 core. Instead, the processor includes its own MPU module.
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*/
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temp_reg = SYSMPU->CESR;
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temp_reg &= ~SYSMPU_CESR_VLD_MASK;
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temp_reg |= SYSMPU_CESR_SPERR_MASK;
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SYSMPU->CESR = temp_reg;
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#endif /* !CONFIG_ARM_MPU */
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/* Initialize system clocks and PLL */
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clk_init();
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/*
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* Install default handler that simply resets the CPU if
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* configured in the kernel, NOP otherwise
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*/
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NMI_INIT();
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#ifdef CONFIG_KINETIS_KE1XF_ENABLE_CODE_CACHE
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L1CACHE_EnableCodeCache();
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#endif
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/* Restore interrupt state */
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irq_unlock(old_level);
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return 0;
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}
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void z_arm_watchdog_init(void)
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{
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/*
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* NOTE: DO NOT SINGLE STEP THROUGH THIS FUNCTION!!! Watchdog
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* reconfiguration must take place within 128 bus clocks from
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* unlocking. Single stepping through the code will cause the
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* watchdog to close the unlock window again.
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*/
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/* Unlock watchdog to enable reconfiguration after bootloader */
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WDOG->CNT = WDOG_UPDATE_KEY;
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while (!(WDOG->CS & WDOG_CS_ULK_MASK)) {
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;
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}
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/*
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* Watchdog reconfiguration only takes effect after writing to
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* both TOVAL and CS registers.
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*/
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#ifdef CONFIG_WDOG_ENABLE_AT_BOOT
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WDOG->TOVAL = CONFIG_WDOG_INITIAL_TIMEOUT >> 1;
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WDOG->CS = WDOG_CS_PRES(1) | WDOG_CS_CLK(1) | WDOG_CS_WAIT(1) |
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WDOG_CS_EN(1) | WDOG_CS_UPDATE(1);
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#else /* !CONFIG_WDOG_ENABLE_AT_BOOT */
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WDOG->TOVAL = 1024;
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WDOG->CS = WDOG_CS_EN(0) | WDOG_CS_UPDATE(1);
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#endif /* !CONFIG_WDOG_ENABLE_AT_BOOT */
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while (!(WDOG->CS & WDOG_CS_RCS_MASK)) {
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;
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}
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}
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SYS_INIT(ke1xf_init, PRE_KERNEL_1, 0);
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