zephyr/arch/riscv/core
Nicolas Pitre cb4c0f6c94 riscv: smarter FPU context switching support
Instead of saving/restoring FPU content on every exception and task
switch, this replaces FPU sharing support with a "lazy" (on-demand)
context switching algorithm similar to the one used on ARM64.

Every thread starts with FPU access disabled. On the first access the
FPU trap is invoked to:

- flush the FPU content to the previous thread's memory storage;

- restore the current thread's FPU content from memory.

When a thread loads its data in the FPU, it becomes the FPU owner.

FPU content is preserved across task switching, however FPU access is
either allowed if the new thread is the FPU owner, or denied otherwise.
A thread may claim FPU ownership only through the FPU trap. This way,
threads that don't use the FPU won't force an FPU context switch.
If only one running thread uses the FPU, there will be no FPU context
switching to do at all.

It is possible to do FP accesses in ISRs and syscalls. This is not the
norm though, so the same principle is applied here, although exception
contexts may not own the FPU. When they access the FPU, the FPU content
is flushed and the exception context is granted FPU access for the
duration of the exception. Nested IRQs are disallowed in that case to
dispense with the need to save and restore exception's FPU context data.

This is the core implementation only to ease reviewing. It is not yet
hooked into the build.

Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
2023-01-24 15:26:18 +01:00
..
offsets riscv: decouple the Zephyr CPU number from the hart ID 2023-01-19 13:48:42 +01:00
asm_macros.inc riscv: abstract RV32E register access 2022-06-23 13:12:05 -04:00
CMakeLists.txt riscv: don't include the secondary CPU boot code when not needed 2023-01-19 13:48:42 +01:00
coredump.c riscv: Introduce support for RV32E 2022-06-08 18:50:22 +09:00
cpu_idle.c arch: migrate includes to <zephyr/...> 2022-05-06 19:57:22 +02:00
fatal.c include: types: remove ulong_t 2022-09-06 18:16:33 +02:00
fpu.c riscv: smarter FPU context switching support 2023-01-24 15:26:18 +01:00
fpu.S riscv: smarter FPU context switching support 2023-01-24 15:26:18 +01:00
irq_manage.c include: types: remove ulong_t 2022-09-06 18:16:33 +02:00
irq_offload.c arch: migrate includes to <zephyr/...> 2022-05-06 19:57:22 +02:00
isr.S riscv: decouple the Zephyr CPU number from the hart ID 2023-01-19 13:48:42 +01:00
pmp.c riscv: pmp: fix stackguard when used on SMP 2022-09-28 07:53:56 +00:00
pmp.S include: types: remove ulong_t 2022-09-06 18:16:33 +02:00
prep_c.c arch: migrate includes to <zephyr/...> 2022-05-06 19:57:22 +02:00
reboot.c arch: migrate includes to <zephyr/...> 2022-05-06 19:57:22 +02:00
reset.S riscv: don't include the secondary CPU boot code when not needed 2023-01-19 13:48:42 +01:00
semihost.c arch: riscv: Align semihost_exec function at 16-byte boundary 2022-08-08 10:52:34 +02:00
smp.c riscv: smp: prepare for more than one IPI type 2023-01-24 15:26:18 +01:00
switch.S riscv: stop preserving the tp register needlessly 2022-06-23 13:12:05 -04:00
thread.c riscv: decouple the Zephyr CPU number from the hart ID 2023-01-19 13:48:42 +01:00
tls.c arch: migrate includes to <zephyr/...> 2022-05-06 19:57:22 +02:00
userspace.S asm: update files with <zephyr/...> include prefix 2022-05-09 12:45:29 -04:00
vector_table.ld arch: riscv: core: Place vectors section through zephyr_linker_sources() 2022-09-08 10:39:31 +02:00