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zephyr/soc/riscv/openisa_rv32m1
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Olof Johansson a6b3b616f5 riscv: use standard MSTATUS 
This is no longer needed, since all in-tree platforms are only using
the standard mstatus formats. Remove it to avoid the complexity.

Signed-off-by: Olof Johansson <olof@lixom.net>
2020-01-06 13:27:45 -05:00
..
CMakeLists.txt riscv: linker.ld: Port vector table to zephyr_linker_sources() 2019-12-20 08:54:53 -05:00
dts_fixup.h riscv32: rename to riscv 2019-08-02 13:54:48 -07:00
Kconfig kconfig: Clean up header comments and make them consistent 2019-11-04 17:31:27 -05:00
Kconfig.defconfig openisa_rv32m1: kconfig: Remove base address/size symbols 2019-12-11 12:44:47 -06:00
Kconfig.soc kconfig: Clean up header comments and make them consistent 2019-11-04 17:31:27 -05:00
linker.ld arch: arm: Move ARM code to AArch32 sub-directory 2019-12-20 11:40:59 -05:00
soc.c kernel: rename z_arch_ to arch_ 2019-11-07 15:21:46 -08:00
soc.h riscv32: rename to riscv 2019-08-02 13:54:48 -07:00
soc_context.h riscv32: rename to riscv 2019-08-02 13:54:48 -07:00
soc_irq.S riscv32: rename to riscv 2019-08-02 13:54:48 -07:00
soc_offsets.h riscv32: rename to riscv 2019-08-02 13:54:48 -07:00
soc_ri5cy.h riscv: use standard MSTATUS 2020-01-06 13:27:45 -05:00
soc_zero_riscy.h riscv: use standard MSTATUS 2020-01-06 13:27:45 -05:00
vector.S riscv32: rename to riscv 2019-08-02 13:54:48 -07:00
vector_table.ld riscv: linker.ld: Port vector table to zephyr_linker_sources() 2019-12-20 08:54:53 -05:00
wdog.S riscv: use standard MSTATUS 2020-01-06 13:27:45 -05:00