1f4b5ddd0f
With the upcoming riscv64 support, it is best to use "riscv" as the subdirectory name and common symbols as riscv32 and riscv64 support code is almost identical. Then later decide whether 32-bit or 64-bit compilation is wanted. Redirects for the web documentation are also included. Then zephyrbot complained about this: " New files added that are not covered in CODEOWNERS: dts/riscv/microsemi-miv.dtsi dts/riscv/riscv32-fe310.dtsi Please add one or more entries in the CODEOWNERS file to cover those files " So I assigned them to those who created them. Feel free to readjust as necessary. Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
42 lines
1.1 KiB
C
42 lines
1.1 KiB
C
/*
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* Copyright (c) 2018 Foundries.io Ltd
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/*
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* Extra definitions required for CONFIG_RISCV_SOC_OFFSETS.
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*/
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#ifndef SOC_RISCV32_OPENISA_RV32M1_SOC_OFFSETS_H_
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#define SOC_RISCV32_OPENISA_RV32M1_SOC_OFFSETS_H_
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#ifdef CONFIG_SOC_OPENISA_RV32M1_RI5CY
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/*
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* Ensure offset macros are available in <offsets.h>.
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*
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* Also create a macro which contains the value of &EVENT0->INTPTPENDCLEAR,
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* for use in assembly.
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*/
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#define GEN_SOC_OFFSET_SYMS() \
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GEN_OFFSET_SYM(soc_esf_t, lpstart0); \
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GEN_OFFSET_SYM(soc_esf_t, lpend0); \
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GEN_OFFSET_SYM(soc_esf_t, lpcount0); \
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GEN_OFFSET_SYM(soc_esf_t, lpstart1); \
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GEN_OFFSET_SYM(soc_esf_t, lpend1); \
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GEN_OFFSET_SYM(soc_esf_t, lpcount1); \
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GEN_ABSOLUTE_SYM(__EVENT_INTPTPENDCLEAR, \
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(uint32_t)&EVENT0->INTPTPENDCLEAR)
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#endif /* CONFIG_SOC_OPENISA_RV32M1_RI5CY */
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#ifdef CONFIG_SOC_OPENISA_RV32M1_ZERO_RISCY
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#define GEN_SOC_OFFSET_SYMS() \
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GEN_ABSOLUTE_SYM(__EVENT_INTPTPENDCLEAR, \
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(uint32_t)&EVENT1->INTPTPENDCLEAR)
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#endif /* CONFIG_SOC_OPENISA_RV32M1_ZERO_RISCY */
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#endif /* SOC_RISCV32_OPENISA_RV32M1_SOC_OFFSETS_H_ */
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