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openisa_rv32m1: kconfig: Remove base address/size symbols

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RISCV_RV32M1_VECTOR_BASE_ADDR is unused after commit 34b0516466
("boards: riscv32: rv32m1_vega: enable MCUboot for ri5cy core") (it was
called RISCV32_RV32M1_BASE_ADDR then).

RISCV_RV32M1_VECTOR_SIZE is still used, but is always 0x100, so remove
it too.

These symbols were only defined in a Kconfig.defconfig file.

Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
This commit is contained in:
Ulf Magnusson 2019-10-25 11:38:51 +02:00 • committed by Maureen Helm
commit fdb936adae
2 changed files with 1 additions and 12 deletions
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11
soc/riscv/openisa_rv32m1/Kconfig.defconfig
View file

@ -41,17 +41,6 @@ config RISCV_SOC_INTERRUPT_INIT
config WDOG_INIT
def_bool y
# The event unit looks for vector tables at the end of each core's
# flash space. These vector tables are not relocatable.
config RISCV_RV32M1_VECTOR_BASE_ADDR
hex
default 0x000FFF00 if SOC_OPENISA_RV32M1_RI5CY
default 0x0103FF00 if SOC_OPENISA_RV32M1_ZERO_RISCY
config RISCV_RV32M1_VECTOR_SIZE
hex
default 0x100
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 8000000

2
soc/riscv/openisa_rv32m1/linker.ld
View file

@ -26,7 +26,7 @@
#define ROMABLE_REGION ROM
#define RAMABLE_REGION RAM
#define VECTOR_SIZE CONFIG_RISCV_RV32M1_VECTOR_SIZE
#define VECTOR_SIZE 0x100
#ifdef CONFIG_USE_DT_CODE_PARTITION